// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from stm32mp157.svd, see https://github.com/tinygo-org/stm32-svd

// +build stm32,stm32mp157x

// STM32MP157x
//

package stm32

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "STM32MP157x"
	CPU          = "CM4"
	FPUPresent   = true
	NVICPrioBits = 4
)

// Interrupt numbers.
const (
	// WWDG1
	IRQ_WWDG1_IT = 0

	// EXTI
	IRQ_PVD_AVD = 1

	// TAMP
	IRQ_TAMP = 2

	// RTC
	IRQ_RTC_WKUP_ALARM = 3

	// TZC
	IRQ_TZC_IT = 4

	// RCC
	IRQ_RCC = 5

	// EXTI
	IRQ_EXTI0 = 6

	// EXTI
	IRQ_EXTI1 = 7

	// EXTI
	IRQ_EXTI2 = 8

	// EXTI
	IRQ_EXTI3 = 9

	// EXTI
	IRQ_EXTI4 = 10

	// DMA1
	IRQ_DMA1_STR0 = 11

	// DMA1
	IRQ_DMA1_STR1 = 12

	// DMA1
	IRQ_DMA1_STR2 = 13

	// DMA1
	IRQ_DMA1_STR3 = 14

	// DMA1
	IRQ_DMA1_STR4 = 15

	// DMA1
	IRQ_DMA1_STR5 = 16

	// DMA1
	IRQ_DMA1_STR6 = 17

	// ADC
	IRQ_ADC1 = 18

	// FDCAN1
	IRQ_FDCAN1_IT0 = 19

	IRQ_FDCAN2_IT0 = 20

	// FDCAN1
	IRQ_FDCAN1_IT1 = 21

	IRQ_FDCAN2_IT1 = 22

	// EXTI
	IRQ_EXTI5 = 23

	// TIM1
	IRQ_TIM1_BRK = 24

	// TIM1
	IRQ_TIM1_UP = 25

	// TIM1
	IRQ_TIM1_TRG_COM = 26

	// TIM1
	IRQ_TIM1_CC = 27

	// TIM2
	IRQ_TIM2 = 28

	// TIM3
	IRQ_TIM3 = 29

	// TIM4
	IRQ_TIM4 = 30

	// I2C1
	IRQ_I2C1_EVT = 31

	// I2C1
	IRQ_I2C1_ERR = 32

	IRQ_I2C2_EVT = 33

	IRQ_I2C2_ERR = 34

	// SPI1
	IRQ_SPI1 = 35

	IRQ_SPI2 = 36

	// Universal synchronous asynchronous receiver transmitter
	IRQ_USART1 = 37

	IRQ_USART2 = 38

	IRQ_USART3 = 39

	// EXTI
	IRQ_EXTI10 = 40

	// RTC
	IRQ_RTC_TS = 41

	// EXTI
	IRQ_EXTI11 = 42

	// TIM8
	IRQ_TIM8_BRK = 43

	// TIM8
	IRQ_TIM8_UP = 44

	// TIM8
	IRQ_TIM8_TRG_COM = 45

	// TIM8
	IRQ_TIM8_CC = 46

	// DMA1
	IRQ_DMA1_STR7 = 47

	// FMC register block
	IRQ_FMC = 48

	// SDMMC1
	IRQ_SDMMC1 = 49

	// TIM5
	IRQ_TIM5 = 50

	IRQ_SPI3 = 51

	IRQ_USART4 = 52

	IRQ_USART5 = 53

	// TIM6
	IRQ_TIM6 = 54

	// TIM7
	IRQ_TIM7 = 55

	IRQ_DMA2_STR0 = 56

	IRQ_DMA2_STR1 = 57

	IRQ_DMA2_STR2 = 58

	IRQ_DMA2_STR3 = 59

	IRQ_DMA2_STR4 = 60

	// ETH_MAC_MMC
	IRQ_ETH1 = 61

	// ETH_MAC_MMC
	IRQ_ETH1_WKUP = 62

	// EXTI
	IRQ_EXTI6 = 64

	// EXTI
	IRQ_EXTI7 = 65

	// EXTI
	IRQ_EXTI8 = 66

	// EXTI
	IRQ_EXTI9 = 67

	IRQ_DMA2_STR5 = 68

	IRQ_DMA2_STR6 = 69

	IRQ_DMA2_STR7 = 70

	IRQ_USART6 = 71

	IRQ_I2C3_EVT = 72

	IRQ_I2C3_ERR = 73

	// EXTI
	IRQ_EXTI12 = 76

	// EXTI
	IRQ_EXTI13 = 77

	// DCMI
	IRQ_DCMI = 78

	// CRYP1
	IRQ_CRYP1 = 79

	// HASH register block
	IRQ_HASH1 = 80

	IRQ_USART7 = 82

	IRQ_USART8 = 83

	IRQ_SPI4 = 84

	IRQ_SPI5 = 85

	IRQ_SPI6 = 86

	// SAI1 register block
	IRQ_SAI1 = 87

	// LTDC
	IRQ_LTDC = 88

	// LTDC
	IRQ_LTDC_ER = 89

	// ADC2
	IRQ_ADC2 = 90

	IRQ_SAI2 = 91

	// QUADSPI1
	IRQ_QUADSPI = 92

	// LPTIM1
	IRQ_LPTIM1 = 93

	// HDMI_CEC
	IRQ_CEC = 94

	IRQ_I2C4_EVT = 95

	IRQ_I2C4_ERR = 96

	// SPDIFRX
	IRQ_SPDIFRX = 97

	// OTG
	IRQ_OTG = 98

	// IPCC
	IRQ_IPCC_RX0 = 100

	// IPCC
	IRQ_IPCC_TX0 = 101

	// DMAMUX1
	IRQ_DMAMUX1_OVR_REQ = 102

	// IPCC
	IRQ_IPCC_RX1 = 103

	// IPCC
	IRQ_IPCC_TX1 = 104

	IRQ_CRYP2 = 105

	// HASH register block
	IRQ_HASH2 = 106

	IRQ_I2C5_EVT = 107

	IRQ_I2C5_ERR = 108

	// DFSDM1
	IRQ_DFSDM1_FLT0 = 110

	// DFSDM1
	IRQ_DFSDM1_FLT1 = 111

	// DFSDM1
	IRQ_DFSDM1_FLT2 = 112

	// DFSDM1
	IRQ_DFSDM1_FLT3 = 113

	IRQ_SAI3 = 114

	// DFSDM1
	IRQ_DFSDM1_FLT4 = 115

	// TIM15
	IRQ_TIM15 = 116

	// TIM16
	IRQ_TIM16 = 117

	IRQ_TIM17 = 118

	// TIM12
	IRQ_TIM12 = 119

	// MDIOS
	IRQ_MDIOS = 120

	// EXTI
	IRQ_EXTI14 = 121

	// MDMA1
	IRQ_MDMA = 122

	// DSIHOST1
	IRQ_DSI = 123

	IRQ_SDMMC2 = 124

	// HSEM
	IRQ_HSEM_IT2 = 125

	// DFSDM1
	IRQ_DFSDM1_FLT5 = 126

	// EXTI
	IRQ_EXTI15 = 127

	// TIM13
	IRQ_TIM13 = 130

	// TIM14
	IRQ_TIM14 = 131

	// DAC1
	IRQ_DAC = 132

	// RNG1
	IRQ_RNG1 = 133

	IRQ_RNG2 = 134

	IRQ_I2C6_EVT = 135

	IRQ_I2C6_ERR = 136

	IRQ_SDMMC3 = 137

	IRQ_LPTIM2 = 138

	IRQ_LPTIM3 = 139

	IRQ_LPTIM4 = 140

	IRQ_LPTIM5 = 141

	// ETH_MAC_MMC
	IRQ_ETH1_LPI = 142

	// RCC
	IRQ_RCC_WAKEUP = 145

	IRQ_SAI4 = 146

	// DTS register block
	IRQ_DTS = 147

	// IWDG1
	IRQ_IWDG1_IT = 150

	IRQ_IWDG2_IT = 151

	// TAMP
	IRQ_TAMP_S = 197

	// RTC
	IRQ_RTC_WKUP_ALARM_S = 198

	// RTC
	IRQ_RTC_TS_S = 199

	// DDRPERFM
	IRQ_DDRPERFM = 213

	// Highest interrupt number on this device.
	IRQ_max = 213
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_WWDG1_IT, "WWDG1_IT_IRQHandler")
	_ = interrupt.Register(IRQ_PVD_AVD, "PVD_AVD_IRQHandler")
	_ = interrupt.Register(IRQ_TAMP, "TAMP_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_WKUP_ALARM, "RTC_WKUP_ALARM_IRQHandler")
	_ = interrupt.Register(IRQ_TZC_IT, "TZC_IT_IRQHandler")
	_ = interrupt.Register(IRQ_RCC, "RCC_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI0, "EXTI0_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI1, "EXTI1_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI2, "EXTI2_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI3, "EXTI3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI4, "EXTI4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR0, "DMA1_STR0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR1, "DMA1_STR1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR2, "DMA1_STR2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR3, "DMA1_STR3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR4, "DMA1_STR4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR5, "DMA1_STR5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR6, "DMA1_STR6_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1, "ADC1_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN1_IT0, "FDCAN1_IT0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_IT0, "FDCAN2_IT0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN1_IT1, "FDCAN1_IT1_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_IT1, "FDCAN2_IT1_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI5, "EXTI5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_BRK, "TIM1_BRK_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_UP, "TIM1_UP_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_TRG_COM, "TIM1_TRG_COM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_CC, "TIM1_CC_IRQHandler")
	_ = interrupt.Register(IRQ_TIM2, "TIM2_IRQHandler")
	_ = interrupt.Register(IRQ_TIM3, "TIM3_IRQHandler")
	_ = interrupt.Register(IRQ_TIM4, "TIM4_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_EVT, "I2C1_EVT_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_ERR, "I2C1_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_EVT, "I2C2_EVT_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_ERR, "I2C2_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_SPI1, "SPI1_IRQHandler")
	_ = interrupt.Register(IRQ_SPI2, "SPI2_IRQHandler")
	_ = interrupt.Register(IRQ_USART1, "USART1_IRQHandler")
	_ = interrupt.Register(IRQ_USART2, "USART2_IRQHandler")
	_ = interrupt.Register(IRQ_USART3, "USART3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI10, "EXTI10_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_TS, "RTC_TS_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI11, "EXTI11_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_BRK, "TIM8_BRK_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_UP, "TIM8_UP_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_TRG_COM, "TIM8_TRG_COM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_CC, "TIM8_CC_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR7, "DMA1_STR7_IRQHandler")
	_ = interrupt.Register(IRQ_FMC, "FMC_IRQHandler")
	_ = interrupt.Register(IRQ_SDMMC1, "SDMMC1_IRQHandler")
	_ = interrupt.Register(IRQ_TIM5, "TIM5_IRQHandler")
	_ = interrupt.Register(IRQ_SPI3, "SPI3_IRQHandler")
	_ = interrupt.Register(IRQ_USART4, "USART4_IRQHandler")
	_ = interrupt.Register(IRQ_USART5, "USART5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM6, "TIM6_IRQHandler")
	_ = interrupt.Register(IRQ_TIM7, "TIM7_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR0, "DMA2_STR0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR1, "DMA2_STR1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR2, "DMA2_STR2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR3, "DMA2_STR3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR4, "DMA2_STR4_IRQHandler")
	_ = interrupt.Register(IRQ_ETH1, "ETH1_IRQHandler")
	_ = interrupt.Register(IRQ_ETH1_WKUP, "ETH1_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI6, "EXTI6_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI7, "EXTI7_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI8, "EXTI8_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI9, "EXTI9_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR5, "DMA2_STR5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR6, "DMA2_STR6_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR7, "DMA2_STR7_IRQHandler")
	_ = interrupt.Register(IRQ_USART6, "USART6_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_EVT, "I2C3_EVT_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_ERR, "I2C3_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI12, "EXTI12_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI13, "EXTI13_IRQHandler")
	_ = interrupt.Register(IRQ_DCMI, "DCMI_IRQHandler")
	_ = interrupt.Register(IRQ_CRYP1, "CRYP1_IRQHandler")
	_ = interrupt.Register(IRQ_HASH1, "HASH1_IRQHandler")
	_ = interrupt.Register(IRQ_USART7, "USART7_IRQHandler")
	_ = interrupt.Register(IRQ_USART8, "USART8_IRQHandler")
	_ = interrupt.Register(IRQ_SPI4, "SPI4_IRQHandler")
	_ = interrupt.Register(IRQ_SPI5, "SPI5_IRQHandler")
	_ = interrupt.Register(IRQ_SPI6, "SPI6_IRQHandler")
	_ = interrupt.Register(IRQ_SAI1, "SAI1_IRQHandler")
	_ = interrupt.Register(IRQ_LTDC, "LTDC_IRQHandler")
	_ = interrupt.Register(IRQ_LTDC_ER, "LTDC_ER_IRQHandler")
	_ = interrupt.Register(IRQ_ADC2, "ADC2_IRQHandler")
	_ = interrupt.Register(IRQ_SAI2, "SAI2_IRQHandler")
	_ = interrupt.Register(IRQ_QUADSPI, "QUADSPI_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM1, "LPTIM1_IRQHandler")
	_ = interrupt.Register(IRQ_CEC, "CEC_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_EVT, "I2C4_EVT_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_ERR, "I2C4_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_SPDIFRX, "SPDIFRX_IRQHandler")
	_ = interrupt.Register(IRQ_OTG, "OTG_IRQHandler")
	_ = interrupt.Register(IRQ_IPCC_RX0, "IPCC_RX0_IRQHandler")
	_ = interrupt.Register(IRQ_IPCC_TX0, "IPCC_TX0_IRQHandler")
	_ = interrupt.Register(IRQ_DMAMUX1_OVR_REQ, "DMAMUX1_OVR_REQ_IRQHandler")
	_ = interrupt.Register(IRQ_IPCC_RX1, "IPCC_RX1_IRQHandler")
	_ = interrupt.Register(IRQ_IPCC_TX1, "IPCC_TX1_IRQHandler")
	_ = interrupt.Register(IRQ_CRYP2, "CRYP2_IRQHandler")
	_ = interrupt.Register(IRQ_HASH2, "HASH2_IRQHandler")
	_ = interrupt.Register(IRQ_I2C5_EVT, "I2C5_EVT_IRQHandler")
	_ = interrupt.Register(IRQ_I2C5_ERR, "I2C5_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT0, "DFSDM1_FLT0_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT1, "DFSDM1_FLT1_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT2, "DFSDM1_FLT2_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT3, "DFSDM1_FLT3_IRQHandler")
	_ = interrupt.Register(IRQ_SAI3, "SAI3_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT4, "DFSDM1_FLT4_IRQHandler")
	_ = interrupt.Register(IRQ_TIM15, "TIM15_IRQHandler")
	_ = interrupt.Register(IRQ_TIM16, "TIM16_IRQHandler")
	_ = interrupt.Register(IRQ_TIM17, "TIM17_IRQHandler")
	_ = interrupt.Register(IRQ_TIM12, "TIM12_IRQHandler")
	_ = interrupt.Register(IRQ_MDIOS, "MDIOS_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI14, "EXTI14_IRQHandler")
	_ = interrupt.Register(IRQ_MDMA, "MDMA_IRQHandler")
	_ = interrupt.Register(IRQ_DSI, "DSI_IRQHandler")
	_ = interrupt.Register(IRQ_SDMMC2, "SDMMC2_IRQHandler")
	_ = interrupt.Register(IRQ_HSEM_IT2, "HSEM_IT2_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT5, "DFSDM1_FLT5_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI15, "EXTI15_IRQHandler")
	_ = interrupt.Register(IRQ_TIM13, "TIM13_IRQHandler")
	_ = interrupt.Register(IRQ_TIM14, "TIM14_IRQHandler")
	_ = interrupt.Register(IRQ_DAC, "DAC_IRQHandler")
	_ = interrupt.Register(IRQ_RNG1, "RNG1_IRQHandler")
	_ = interrupt.Register(IRQ_RNG2, "RNG2_IRQHandler")
	_ = interrupt.Register(IRQ_I2C6_EVT, "I2C6_EVT_IRQHandler")
	_ = interrupt.Register(IRQ_I2C6_ERR, "I2C6_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_SDMMC3, "SDMMC3_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM2, "LPTIM2_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM3, "LPTIM3_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM4, "LPTIM4_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM5, "LPTIM5_IRQHandler")
	_ = interrupt.Register(IRQ_ETH1_LPI, "ETH1_LPI_IRQHandler")
	_ = interrupt.Register(IRQ_RCC_WAKEUP, "RCC_WAKEUP_IRQHandler")
	_ = interrupt.Register(IRQ_SAI4, "SAI4_IRQHandler")
	_ = interrupt.Register(IRQ_DTS, "DTS_IRQHandler")
	_ = interrupt.Register(IRQ_IWDG1_IT, "IWDG1_IT_IRQHandler")
	_ = interrupt.Register(IRQ_IWDG2_IT, "IWDG2_IT_IRQHandler")
	_ = interrupt.Register(IRQ_TAMP_S, "TAMP_S_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_WKUP_ALARM_S, "RTC_WKUP_ALARM_S_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_TS_S, "RTC_TS_S_IRQHandler")
	_ = interrupt.Register(IRQ_DDRPERFM, "DDRPERFM_IRQHandler")
)

// Peripherals.
var (
	// ADC
	ADC = (*ADC_Type)(unsafe.Pointer(uintptr(0x48003000)))

	// ADC2
	ADC2 = (*ADC2_Type)(unsafe.Pointer(uintptr(0x48003100)))

	// Analog-to-Digital Converter
	ADC_common = (*ADC_Type)(unsafe.Pointer(uintptr(0x48003300)))

	// AXIMC_Mx
	AXIMC_Mx = (*AXIMC_Mx_Type)(unsafe.Pointer(uintptr(0x57042024)))

	// BSEC2
	BSEC = (*BSEC2_Type)(unsafe.Pointer(uintptr(0x5c005000)))

	// CCU
	CCU = (*CCU_Type)(unsafe.Pointer(uintptr(0x44010000)))

	// CRC1
	CRC1 = (*CRC1_Type)(unsafe.Pointer(uintptr(0x58009000)))

	// CRC1
	CRC2 = (*CRC1_Type)(unsafe.Pointer(uintptr(0x4c004000)))

	// CRYP1
	CRYP1 = (*CRYP1_Type)(unsafe.Pointer(uintptr(0x54001000)))

	// CRYP1
	CRYP2 = (*CRYP1_Type)(unsafe.Pointer(uintptr(0x4c005000)))

	// DAC1
	DAC1 = (*DAC1_Type)(unsafe.Pointer(uintptr(0x40017000)))

	// DCMI
	DCMI = (*DCMI_Type)(unsafe.Pointer(uintptr(0x4c006000)))

	// DDRCTRL
	DDRCTRL = (*DDRCTRL_Type)(unsafe.Pointer(uintptr(0x5a003000)))

	// DDRPERFM
	DDRPERFM = (*DDRPERFM_Type)(unsafe.Pointer(uintptr(0x5a007000)))

	// DDRPHYC
	DDRPHYC = (*DDRPHYC_Type)(unsafe.Pointer(uintptr(0x5a004000)))

	// DFSDM1
	DFSDM1 = (*DFSDM1_Type)(unsafe.Pointer(uintptr(0x4400d000)))

	// DLYBQS
	DLYBQS = (*DLYB_Type)(unsafe.Pointer(uintptr(0x58004000)))

	// DLYBSD1
	DLYBSD1 = (*DLYBSD1_Type)(unsafe.Pointer(uintptr(0x58006000)))

	// DLYBSD1
	DLYBSD2 = (*DLYBSD1_Type)(unsafe.Pointer(uintptr(0x58008000)))

	// DLYBSD1
	DLYBSD3 = (*DLYBSD1_Type)(unsafe.Pointer(uintptr(0x48005000)))

	// DMA1
	DMA1 = (*DMA1_Type)(unsafe.Pointer(uintptr(0x48000000)))

	// DMA1
	DMA2 = (*DMA1_Type)(unsafe.Pointer(uintptr(0x48001000)))

	// DMAMUX1
	DMAMUX1 = (*DMAMUX1_Type)(unsafe.Pointer(uintptr(0x48002000)))

	// DSIHOST1
	DSIHOST1 = (*DSIHOST1_Type)(unsafe.Pointer(uintptr(0x5a000000)))

	// DTS register block
	DTS = (*DTS_Type)(unsafe.Pointer(uintptr(0x50028000)))

	// ETH_MAC_MMC
	ETH_MAC_MMC = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x5800a000)))

	// ETH_MTL
	ETH_MTL = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x5800ac00)))

	// ETH_DMA
	ETH_DMA = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x5800b000)))

	// ETZPC
	ETZPC = (*ETZPC_Type)(unsafe.Pointer(uintptr(0x5c007000)))

	// EXTI
	EXTI = (*EXTI_Type)(unsafe.Pointer(uintptr(0x5000d000)))

	// FDCAN1
	FDCAN1 = (*FDCAN1_Type)(unsafe.Pointer(uintptr(0x4400e000)))

	// FDCAN1
	FDCAN2 = (*FDCAN1_Type)(unsafe.Pointer(uintptr(0x4400f000)))

	// FMC register block
	FMC = (*FMC_Type)(unsafe.Pointer(uintptr(0x58002000)))

	// GICC
	GICC = (*GICC_Type)(unsafe.Pointer(uintptr(0xa0022000)))

	// GICD
	GICD = (*GICD_Type)(unsafe.Pointer(uintptr(0xa0021000)))

	// GICH
	GICH = (*GICH_Type)(unsafe.Pointer(uintptr(0xa0024000)))

	// GICV
	GICV = (*GICV_Type)(unsafe.Pointer(uintptr(0xa0026000)))

	// GPIOA
	GPIOA = (*GPIOA_Type)(unsafe.Pointer(uintptr(0x50002000)))

	// GPIOB
	GPIOB = (*GPIOB_Type)(unsafe.Pointer(uintptr(0x50003000)))

	// GPIOC
	GPIOC = (*GPIOC_Type)(unsafe.Pointer(uintptr(0x50004000)))

	// GPIOD
	GPIOD = (*GPIOD_Type)(unsafe.Pointer(uintptr(0x50005000)))

	// GPIOE
	GPIOE = (*GPIOE_Type)(unsafe.Pointer(uintptr(0x50006000)))

	// GPIOF
	GPIOF = (*GPIOF_Type)(unsafe.Pointer(uintptr(0x50007000)))

	// GPIOG
	GPIOG = (*GPIOG_Type)(unsafe.Pointer(uintptr(0x50008000)))

	// GPIOH
	GPIOH = (*GPIOH_Type)(unsafe.Pointer(uintptr(0x50009000)))

	// GPIOI
	GPIOI = (*GPIOI_Type)(unsafe.Pointer(uintptr(0x5000a000)))

	// GPIOJ
	GPIOJ = (*GPIOJ_Type)(unsafe.Pointer(uintptr(0x5000b000)))

	// GPIOK
	GPIOK = (*GPIOK_Type)(unsafe.Pointer(uintptr(0x5000c000)))

	// GPIOZ
	GPIOZ = (*GPIOZ_Type)(unsafe.Pointer(uintptr(0x54004000)))

	// HASH register block
	HASH1 = (*HASH_Type)(unsafe.Pointer(uintptr(0x54002000)))

	// HASH register block
	HASH2 = (*HASH_Type)(unsafe.Pointer(uintptr(0x4c002000)))

	// HDMI_CEC
	HDMI_CEC = (*HDMI_CEC_Type)(unsafe.Pointer(uintptr(0x40016000)))

	// HDP
	HDP = (*HDP_Type)(unsafe.Pointer(uintptr(0x5002a000)))

	// HSEM
	HSEM = (*HSEM_IPXACT_Type)(unsafe.Pointer(uintptr(0x4c000000)))

	// I2C1
	I2C1 = (*I2C2_IPXACT_Type)(unsafe.Pointer(uintptr(0x40012000)))

	// IPCC
	IPCC = (*IPCC_Type)(unsafe.Pointer(uintptr(0x4c001000)))

	// IWDG1
	IWDG1 = (*IWDG1_Type)(unsafe.Pointer(uintptr(0x5c003000)))

	// IWDG1
	IWDG2 = (*IWDG1_Type)(unsafe.Pointer(uintptr(0x5a002000)))

	// LPTIM1
	LPTIM1 = (*LPTIM1_Type)(unsafe.Pointer(uintptr(0x40009000)))

	// LPTIM1
	LPTIM2 = (*LPTIM1_Type)(unsafe.Pointer(uintptr(0x50021000)))

	// LPTIM1
	LPTIM3 = (*LPTIM1_Type)(unsafe.Pointer(uintptr(0x50022000)))

	// LPTIM1
	LPTIM4 = (*LPTIM1_Type)(unsafe.Pointer(uintptr(0x50023000)))

	// LPTIM1
	LPTIM5 = (*LPTIM1_Type)(unsafe.Pointer(uintptr(0x50024000)))

	// LTDC
	LTDC = (*LTDC_Type)(unsafe.Pointer(uintptr(0x5a001000)))

	// MDIOS
	MDIOS = (*MDIOS_Type)(unsafe.Pointer(uintptr(0x4001c000)))

	// MDMA1
	MDMA = (*MDMA1_Type)(unsafe.Pointer(uintptr(0x58000000)))

	// Nested Vectored Interrupt Controller
	NVIC = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000e100)))

	// OTG
	OTG = (*OTG_Type)(unsafe.Pointer(uintptr(0x49000000)))

	// PWR
	PWR = (*PWR_Type)(unsafe.Pointer(uintptr(0x50001000)))

	// QUADSPI1
	QUADSPI = (*QUADSPI1_Type)(unsafe.Pointer(uintptr(0x58003000)))

	// RCC
	RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x50000000)))

	// RNG1
	RNG1 = (*RNG1_Type)(unsafe.Pointer(uintptr(0x54003000)))

	// RNG1
	RNG2 = (*RNG1_Type)(unsafe.Pointer(uintptr(0x4c003000)))

	// RTC
	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x5c004000)))

	// SAI1 register block
	SAI1 = (*SAI_Type)(unsafe.Pointer(uintptr(0x4400a000)))

	// SDMMC1
	SDMMC1 = (*SDMMC2_Type)(unsafe.Pointer(uintptr(0x58005000)))

	// SPDIFRX
	SPDIFRX = (*SPDIFRX_Type)(unsafe.Pointer(uintptr(0x4000d000)))

	// SPI1
	SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x44004000)))

	// SPI1
	SPI2 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x4000b000)))

	// SPI1
	SPI3 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x4000c000)))

	// SPI1
	SPI4 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x44005000)))

	// SPI1
	SPI5 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x44009000)))

	// SPI1
	SPI6 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x5c001000)))

	// STGENC
	STGENC = (*STGENC_Type)(unsafe.Pointer(uintptr(0x5c008000)))

	// STGENR
	STGENR = (*STGENR_Type)(unsafe.Pointer(uintptr(0x5a005000)))

	// SYSCFG
	SYSCFG = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x50020000)))

	// TAMP
	TAMP = (*TAMP_Type)(unsafe.Pointer(uintptr(0x5c00a000)))

	// TIM1
	TIM1 = (*TIM1_Type)(unsafe.Pointer(uintptr(0x44000000)))

	// TIM2
	TIM2 = (*TIM2_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// TIM3
	TIM3 = (*TIM3_Type)(unsafe.Pointer(uintptr(0x40001000)))

	// TIM4
	TIM4 = (*TIM4_Type)(unsafe.Pointer(uintptr(0x40002000)))

	// TIM5
	TIM5 = (*TIM5_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// TIM6
	TIM6 = (*TIM6_Type)(unsafe.Pointer(uintptr(0x40004000)))

	// TIM7
	TIM7 = (*TIM7_Type)(unsafe.Pointer(uintptr(0x40005000)))

	// TIM8
	TIM8 = (*TIM8_Type)(unsafe.Pointer(uintptr(0x44001000)))

	// TIM12
	TIM12 = (*TIM12_Type)(unsafe.Pointer(uintptr(0x40006000)))

	// TIM13
	TIM13 = (*TIM13_Type)(unsafe.Pointer(uintptr(0x40007000)))

	// TIM14
	TIM14 = (*TIM14_Type)(unsafe.Pointer(uintptr(0x40008000)))

	// TIM15
	TIM15 = (*TIMER_Type)(unsafe.Pointer(uintptr(0x44006000)))

	// TIM16
	TIM16 = (*TIMER_Type)(unsafe.Pointer(uintptr(0x44007000)))

	// TZC
	TZC = (*TZC_Type)(unsafe.Pointer(uintptr(0x5c006000)))

	// Universal synchronous asynchronous receiver transmitter
	USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x5c000000)))

	// USBPHYC
	USBPHYC = (*USBPHYC_Type)(unsafe.Pointer(uintptr(0x5a006000)))

	// VREFBUF
	VREFBUF = (*VREFBUF_Type)(unsafe.Pointer(uintptr(0x50025000)))

	// WWDG1
	WWDG1 = (*WWDG1_Type)(unsafe.Pointer(uintptr(0x4000a000)))

	// I2C1
	I2C2 = (*I2C2_IPXACT_Type)(unsafe.Pointer(uintptr(0x40013000)))

	// I2C1
	I2C3 = (*I2C2_IPXACT_Type)(unsafe.Pointer(uintptr(0x40014000)))

	// I2C1
	I2C4 = (*I2C2_IPXACT_Type)(unsafe.Pointer(uintptr(0x5c002000)))

	// I2C1
	I2C5 = (*I2C2_IPXACT_Type)(unsafe.Pointer(uintptr(0x40015000)))

	// I2C1
	I2C6 = (*I2C2_IPXACT_Type)(unsafe.Pointer(uintptr(0x5c009000)))

	// SAI1 register block
	SAI2 = (*SAI_Type)(unsafe.Pointer(uintptr(0x4400b000)))

	// SAI1 register block
	SAI3 = (*SAI_Type)(unsafe.Pointer(uintptr(0x4400c000)))

	// SAI1 register block
	SAI4 = (*SAI_Type)(unsafe.Pointer(uintptr(0x50027000)))

	// SDMMC1
	SDMMC2 = (*SDMMC2_Type)(unsafe.Pointer(uintptr(0x58007000)))

	// SDMMC1
	SDMMC3 = (*SDMMC2_Type)(unsafe.Pointer(uintptr(0x48004000)))

	// TIM16
	TIM17 = (*TIMER_Type)(unsafe.Pointer(uintptr(0x44008000)))

	// Universal synchronous asynchronous receiver transmitter
	USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x4000e000)))

	// Universal synchronous asynchronous receiver transmitter
	USART3 = (*USART_Type)(unsafe.Pointer(uintptr(0x4000f000)))

	// Universal synchronous asynchronous receiver transmitter
	USART4 = (*USART_Type)(unsafe.Pointer(uintptr(0x40010000)))

	// Universal synchronous asynchronous receiver transmitter
	USART5 = (*USART_Type)(unsafe.Pointer(uintptr(0x40011000)))

	// Universal synchronous asynchronous receiver transmitter
	USART6 = (*USART_Type)(unsafe.Pointer(uintptr(0x44003000)))

	// Universal synchronous asynchronous receiver transmitter
	USART7 = (*USART_Type)(unsafe.Pointer(uintptr(0x40018000)))

	// Universal synchronous asynchronous receiver transmitter
	USART8 = (*USART_Type)(unsafe.Pointer(uintptr(0x40019000)))
)

// ADC
type ADC_Type struct {
	ADC_ISR      volatile.Register32 // 0x0
	ADC_IER      volatile.Register32 // 0x4
	ADC_CR       volatile.Register32 // 0x8
	ADC_CFGR     volatile.Register32 // 0xC
	ADC_CFGR2    volatile.Register32 // 0x10
	ADC_SMPR1    volatile.Register32 // 0x14
	ADC_SMPR2    volatile.Register32 // 0x18
	ADC_PCSEL    volatile.Register32 // 0x1C
	ADC_LTR1     volatile.Register32 // 0x20
	ADC_HTR1     volatile.Register32 // 0x24
	_            [8]byte
	ADC_SQR1     volatile.Register32 // 0x30
	ADC_SQR2     volatile.Register32 // 0x34
	ADC_SQR3     volatile.Register32 // 0x38
	ADC_SQR4     volatile.Register32 // 0x3C
	ADC_DR       volatile.Register32 // 0x40
	_            [8]byte
	ADC_JSQR     volatile.Register32 // 0x4C
	_            [16]byte
	ADC_OFR1     volatile.Register32 // 0x60
	ADC_OFR2     volatile.Register32 // 0x64
	ADC_OFR3     volatile.Register32 // 0x68
	ADC_OFR4     volatile.Register32 // 0x6C
	_            [16]byte
	ADC_JDR1     volatile.Register32 // 0x80
	ADC_JDR2     volatile.Register32 // 0x84
	ADC_JDR3     volatile.Register32 // 0x88
	ADC_JDR4     volatile.Register32 // 0x8C
	_            [16]byte
	ADC_AWD2CR   volatile.Register32 // 0xA0
	ADC_AWD3CR   volatile.Register32 // 0xA4
	_            [8]byte
	ADC_LTR2     volatile.Register32 // 0xB0
	ADC_HTR2     volatile.Register32 // 0xB4
	ADC_LTR3     volatile.Register32 // 0xB8
	ADC_HTR3     volatile.Register32 // 0xBC
	ADC_DIFSEL   volatile.Register32 // 0xC0
	ADC_CALFACT  volatile.Register32 // 0xC4
	ADC_CALFACT2 volatile.Register32 // 0xC8
}

// ADC2
type ADC2_Type struct {
	ADC_ISR      volatile.Register32 // 0x0
	ADC_IER      volatile.Register32 // 0x4
	ADC_CR       volatile.Register32 // 0x8
	ADC_CFGR     volatile.Register32 // 0xC
	ADC_CFGR2    volatile.Register32 // 0x10
	ADC_SMPR1    volatile.Register32 // 0x14
	ADC_SMPR2    volatile.Register32 // 0x18
	ADC_PCSEL    volatile.Register32 // 0x1C
	ADC_LTR1     volatile.Register32 // 0x20
	ADC_HTR1     volatile.Register32 // 0x24
	_            [8]byte
	ADC_SQR1     volatile.Register32 // 0x30
	ADC_SQR2     volatile.Register32 // 0x34
	ADC_SQR3     volatile.Register32 // 0x38
	ADC_SQR4     volatile.Register32 // 0x3C
	ADC_DR       volatile.Register32 // 0x40
	_            [8]byte
	ADC_JSQR     volatile.Register32 // 0x4C
	_            [16]byte
	ADC_OFR1     volatile.Register32 // 0x60
	ADC_OFR2     volatile.Register32 // 0x64
	ADC_OFR3     volatile.Register32 // 0x68
	ADC_OFR4     volatile.Register32 // 0x6C
	_            [16]byte
	ADC_JDR1     volatile.Register32 // 0x80
	ADC_JDR2     volatile.Register32 // 0x84
	ADC_JDR3     volatile.Register32 // 0x88
	ADC_JDR4     volatile.Register32 // 0x8C
	_            [16]byte
	ADC_AWD2CR   volatile.Register32 // 0xA0
	ADC_AWD3CR   volatile.Register32 // 0xA4
	_            [8]byte
	ADC_LTR2     volatile.Register32 // 0xB0
	ADC_HTR2     volatile.Register32 // 0xB4
	ADC_LTR3     volatile.Register32 // 0xB8
	ADC_HTR3     volatile.Register32 // 0xBC
	ADC_DIFSEL   volatile.Register32 // 0xC0
	ADC_CALFACT  volatile.Register32 // 0xC4
	ADC_CALFACT2 volatile.Register32 // 0xC8
	_            [4]byte
	ADC2_OR      volatile.Register32 // 0xD0
}

// AXIMC_Mx
type AXIMC_Mx_Type struct {
	AXIMC_M0_FN_MOD2    volatile.Register32 // 0x0
	_                   [216]byte
	AXIMC_M0_READ_QOS   volatile.Register32 // 0xDC
	AXIMC_M0_FN_MOD     volatile.Register32 // 0xE0
	AXIMC_M0_WRITE_QOS  volatile.Register32 // 0xE4
	_                   [3864]byte
	AXIMC_M1_FN_MOD2    volatile.Register32 // 0x1000
	_                   [216]byte
	AXIMC_M1_READ_QOS   volatile.Register32 // 0x10DC
	AXIMC_M1_WRITE_QOS  volatile.Register32 // 0x10E0
	AXIMC_M1_FN_MOD     volatile.Register32 // 0x10E4
	_                   [3816]byte
	AXIMC_PERIPH_ID_4   volatile.Register32 // 0x1FD0
	AXIMC_PERIPH_ID_5   volatile.Register32 // 0x1FD4
	AXIMC_PERIPH_ID_6   volatile.Register32 // 0x1FD8
	AXIMC_PERIPH_ID_7   volatile.Register32 // 0x1FDC
	AXIMC_PERIPH_ID_0   volatile.Register32 // 0x1FE0
	AXIMC_PERIPH_ID_1   volatile.Register32 // 0x1FE4
	AXIMC_PERIPH_ID_2   volatile.Register32 // 0x1FE8
	AXIMC_PERIPH_ID_3   volatile.Register32 // 0x1FEC
	AXIMC_COMP_ID_0     volatile.Register32 // 0x1FF0
	AXIMC_COMP_ID_1     volatile.Register32 // 0x1FF4
	AXIMC_COMP_ID_2     volatile.Register32 // 0x1FF8
	AXIMC_COMP_ID_3     volatile.Register32 // 0x1FFC
	AXIMC_M2_FN_MOD2    volatile.Register32 // 0x2000
	_                   [216]byte
	AXIMC_M2_READ_QOS   volatile.Register32 // 0x20DC
	AXIMC_M2_WRITE_QOS  volatile.Register32 // 0x20E0
	AXIMC_M2_FN_MOD     volatile.Register32 // 0x20E4
	_                   [3864]byte
	AXIMC_M5_FN_MOD2    volatile.Register32 // 0x3000
	_                   [216]byte
	AXIMC_M5_READ_QOS   volatile.Register32 // 0x30DC
	AXIMC_M5_WRITE_QOS  volatile.Register32 // 0x30E0
	AXIMC_M5_FN_MOD     volatile.Register32 // 0x30E4
	_                   [4084]byte
	AXIMC_M3_READ_QOS   volatile.Register32 // 0x40DC
	AXIMC_M3_WRITE_QOS  volatile.Register32 // 0x40E0
	AXIMC_M3_FN_MOD     volatile.Register32 // 0x40E4
	_                   [4084]byte
	AXIMC_M7_READ_QOS   volatile.Register32 // 0x50DC
	AXIMC_M7_WRITE_QOS  volatile.Register32 // 0x50E0
	AXIMC_M7_FN_MOD     volatile.Register32 // 0x50E4
	_                   [4084]byte
	AXIMC_M8_READ_QOS   volatile.Register32 // 0x60DC
	AXIMC_M8_WRITE_QOS  volatile.Register32 // 0x60E0
	AXIMC_M8_FN_MOD     volatile.Register32 // 0x60E4
	_                   [7960]byte
	AXIMC_M4_FN_MOD2    volatile.Register32 // 0x8000
	_                   [216]byte
	AXIMC_M4_READ_QOS   volatile.Register32 // 0x80DC
	AXIMC_M4_WRITE_QOS  volatile.Register32 // 0x80E0
	AXIMC_M4_FN_MOD     volatile.Register32 // 0x80E4
	_                   [4084]byte
	AXIMC_M9_READ_QOS   volatile.Register32 // 0x90DC
	AXIMC_M9_WRITE_QOS  volatile.Register32 // 0x90E0
	AXIMC_M9_FN_MOD     volatile.Register32 // 0x90E4
	_                   [4084]byte
	AXIMC_M10_READ_QOS  volatile.Register32 // 0xA0DC
	AXIMC_M10_WRITE_QOS volatile.Register32 // 0xA0E0
	AXIMC_M10_FN_MOD    volatile.Register32 // 0xA0E4
	_                   [3864]byte
	AXIMC_M6_FN_MOD2    volatile.Register32 // 0xB000
	_                   [216]byte
	AXIMC_M6_READ_QOS   volatile.Register32 // 0xB0DC
	AXIMC_M6_WRITE_QOS  volatile.Register32 // 0xB0E0
	AXIMC_M6_FN_MOD     volatile.Register32 // 0xB0E4
	_                   [225088]byte
	AXIMC_M0_FN_MOD_AHB volatile.Register32 // 0x42028
	_                   [4092]byte
	AXIMC_M1_FN_MOD_AHB volatile.Register32 // 0x43028
	_                   [4092]byte
	AXIMC_M2_FN_MOD_AHB volatile.Register32 // 0x44028
	_                   [4092]byte
	AXIMC_M5_FN_MOD_AHB volatile.Register32 // 0x45028
	_                   [20480]byte
	AXIMC_FN_MOD_LB     volatile.Register32 // 0x4A02C
	_                   [12280]byte
	AXIMC_M6_FN_MOD_AHB volatile.Register32 // 0x4D028
}

// BSEC2
type BSEC2_Type struct {
	BSEC_OTP_CONFIG     volatile.Register32 // 0x0
	BSEC_OTP_CONTROL    volatile.Register32 // 0x4
	BSEC_OTP_WRDATA     volatile.Register32 // 0x8
	BSEC_OTP_STATUS     volatile.Register32 // 0xC
	BSEC_OTP_LOCK       volatile.Register32 // 0x10
	BSEC_DENABLE        volatile.Register32 // 0x14
	_                   [4]byte
	BSEC_OTP_DISTURBED0 volatile.Register32 // 0x1C
	BSEC_OTP_DISTURBED1 volatile.Register32 // 0x20
	BSEC_OTP_DISTURBED2 volatile.Register32 // 0x24
	_                   [12]byte
	BSEC_OTP_ERROR0     volatile.Register32 // 0x34
	BSEC_OTP_ERROR1     volatile.Register32 // 0x38
	BSEC_OTP_ERROR2     volatile.Register32 // 0x3C
	_                   [12]byte
	BSEC_OTP_WRLOCK0    volatile.Register32 // 0x4C
	BSEC_OTP_WRLOCK1    volatile.Register32 // 0x50
	BSEC_OTP_WRLOCK2    volatile.Register32 // 0x54
	_                   [12]byte
	BSEC_OTP_SPLOCK0    volatile.Register32 // 0x64
	BSEC_OTP_SPLOCK1    volatile.Register32 // 0x68
	BSEC_OTP_SPLOCK2    volatile.Register32 // 0x6C
	_                   [12]byte
	BSEC_OTP_SWLOCK0    volatile.Register32 // 0x7C
	BSEC_OTP_SWLOCK1    volatile.Register32 // 0x80
	BSEC_OTP_SWLOCK2    volatile.Register32 // 0x84
	_                   [12]byte
	BSEC_OTP_SRLOCK0    volatile.Register32 // 0x94
	BSEC_OTP_SRLOCK1    volatile.Register32 // 0x98
	BSEC_OTP_SRLOCK2    volatile.Register32 // 0x9C
	_                   [12]byte
	BSEC_JTAGIN         volatile.Register32 // 0xAC
	BSEC_JTAGOUT        volatile.Register32 // 0xB0
	BSEC_SCRATCH        volatile.Register32 // 0xB4
	_                   [328]byte
	BSEC_OTP_DATA0      volatile.Register32 // 0x200
	BSEC_OTP_DATA1      volatile.Register32 // 0x204
	BSEC_OTP_DATA2      volatile.Register32 // 0x208
	BSEC_OTP_DATA3      volatile.Register32 // 0x20C
	BSEC_OTP_DATA4      volatile.Register32 // 0x210
	BSEC_OTP_DATA5      volatile.Register32 // 0x214
	BSEC_OTP_DATA6      volatile.Register32 // 0x218
	BSEC_OTP_DATA7      volatile.Register32 // 0x21C
	BSEC_OTP_DATA8      volatile.Register32 // 0x220
	BSEC_OTP_DATA9      volatile.Register32 // 0x224
	BSEC_OTP_DATA10     volatile.Register32 // 0x228
	BSEC_OTP_DATA11     volatile.Register32 // 0x22C
	BSEC_OTP_DATA12     volatile.Register32 // 0x230
	BSEC_OTP_DATA13     volatile.Register32 // 0x234
	BSEC_OTP_DATA14     volatile.Register32 // 0x238
	BSEC_OTP_DATA15     volatile.Register32 // 0x23C
	BSEC_OTP_DATA16     volatile.Register32 // 0x240
	BSEC_OTP_DATA17     volatile.Register32 // 0x244
	BSEC_OTP_DATA18     volatile.Register32 // 0x248
	BSEC_OTP_DATA19     volatile.Register32 // 0x24C
	BSEC_OTP_DATA20     volatile.Register32 // 0x250
	BSEC_OTP_DATA21     volatile.Register32 // 0x254
	BSEC_OTP_DATA22     volatile.Register32 // 0x258
	BSEC_OTP_DATA23     volatile.Register32 // 0x25C
	BSEC_OTP_DATA24     volatile.Register32 // 0x260
	BSEC_OTP_DATA25     volatile.Register32 // 0x264
	BSEC_OTP_DATA26     volatile.Register32 // 0x268
	BSEC_OTP_DATA27     volatile.Register32 // 0x26C
	BSEC_OTP_DATA28     volatile.Register32 // 0x270
	BSEC_OTP_DATA29     volatile.Register32 // 0x274
	BSEC_OTP_DATA30     volatile.Register32 // 0x278
	BSEC_OTP_DATA31     volatile.Register32 // 0x27C
	BSEC_OTP_DATA32     volatile.Register32 // 0x280
	BSEC_OTP_DATA33     volatile.Register32 // 0x284
	BSEC_OTP_DATA34     volatile.Register32 // 0x288
	BSEC_OTP_DATA35     volatile.Register32 // 0x28C
	BSEC_OTP_DATA36     volatile.Register32 // 0x290
	BSEC_OTP_DATA37     volatile.Register32 // 0x294
	BSEC_OTP_DATA38     volatile.Register32 // 0x298
	BSEC_OTP_DATA39     volatile.Register32 // 0x29C
	BSEC_OTP_DATA40     volatile.Register32 // 0x2A0
	BSEC_OTP_DATA41     volatile.Register32 // 0x2A4
	BSEC_OTP_DATA42     volatile.Register32 // 0x2A8
	BSEC_OTP_DATA43     volatile.Register32 // 0x2AC
	BSEC_OTP_DATA44     volatile.Register32 // 0x2B0
	BSEC_OTP_DATA45     volatile.Register32 // 0x2B4
	BSEC_OTP_DATA46     volatile.Register32 // 0x2B8
	BSEC_OTP_DATA47     volatile.Register32 // 0x2BC
	BSEC_OTP_DATA48     volatile.Register32 // 0x2C0
	BSEC_OTP_DATA49     volatile.Register32 // 0x2C4
	BSEC_OTP_DATA50     volatile.Register32 // 0x2C8
	BSEC_OTP_DATA51     volatile.Register32 // 0x2CC
	BSEC_OTP_DATA52     volatile.Register32 // 0x2D0
	BSEC_OTP_DATA53     volatile.Register32 // 0x2D4
	BSEC_OTP_DATA54     volatile.Register32 // 0x2D8
	BSEC_OTP_DATA55     volatile.Register32 // 0x2DC
	BSEC_OTP_DATA56     volatile.Register32 // 0x2E0
	BSEC_OTP_DATA57     volatile.Register32 // 0x2E4
	BSEC_OTP_DATA58     volatile.Register32 // 0x2E8
	BSEC_OTP_DATA59     volatile.Register32 // 0x2EC
	BSEC_OTP_DATA60     volatile.Register32 // 0x2F0
	BSEC_OTP_DATA61     volatile.Register32 // 0x2F4
	BSEC_OTP_DATA62     volatile.Register32 // 0x2F8
	BSEC_OTP_DATA63     volatile.Register32 // 0x2FC
	BSEC_OTP_DATA64     volatile.Register32 // 0x300
	BSEC_OTP_DATA65     volatile.Register32 // 0x304
	BSEC_OTP_DATA66     volatile.Register32 // 0x308
	BSEC_OTP_DATA67     volatile.Register32 // 0x30C
	BSEC_OTP_DATA68     volatile.Register32 // 0x310
	BSEC_OTP_DATA69     volatile.Register32 // 0x314
	BSEC_OTP_DATA70     volatile.Register32 // 0x318
	BSEC_OTP_DATA71     volatile.Register32 // 0x31C
	BSEC_OTP_DATA72     volatile.Register32 // 0x320
	BSEC_OTP_DATA73     volatile.Register32 // 0x324
	BSEC_OTP_DATA74     volatile.Register32 // 0x328
	BSEC_OTP_DATA75     volatile.Register32 // 0x32C
	BSEC_OTP_DATA76     volatile.Register32 // 0x330
	BSEC_OTP_DATA77     volatile.Register32 // 0x334
	BSEC_OTP_DATA78     volatile.Register32 // 0x338
	BSEC_OTP_DATA79     volatile.Register32 // 0x33C
	BSEC_OTP_DATA80     volatile.Register32 // 0x340
	BSEC_OTP_DATA81     volatile.Register32 // 0x344
	BSEC_OTP_DATA82     volatile.Register32 // 0x348
	BSEC_OTP_DATA83     volatile.Register32 // 0x34C
	BSEC_OTP_DATA84     volatile.Register32 // 0x350
	BSEC_OTP_DATA85     volatile.Register32 // 0x354
	BSEC_OTP_DATA86     volatile.Register32 // 0x358
	BSEC_OTP_DATA87     volatile.Register32 // 0x35C
	BSEC_OTP_DATA88     volatile.Register32 // 0x360
	BSEC_OTP_DATA89     volatile.Register32 // 0x364
	BSEC_OTP_DATA90     volatile.Register32 // 0x368
	BSEC_OTP_DATA91     volatile.Register32 // 0x36C
	BSEC_OTP_DATA92     volatile.Register32 // 0x370
	BSEC_OTP_DATA93     volatile.Register32 // 0x374
	BSEC_OTP_DATA94     volatile.Register32 // 0x378
	BSEC_OTP_DATA95     volatile.Register32 // 0x37C
	_                   [3184]byte
	BSEC_HWCFGR         volatile.Register32 // 0xFF0
	BSEC_VERR           volatile.Register32 // 0xFF4
	BSEC_IPIDR          volatile.Register32 // 0xFF8
	BSEC_SIDR           volatile.Register32 // 0xFFC
}

// CCU
type CCU_Type struct {
	FCCAN_CCU_CREL  volatile.Register32 // 0x0
	FCCAN_CCU_CCFG  volatile.Register32 // 0x4
	FCCAN_CCU_CSTAT volatile.Register32 // 0x8
	FCCAN_CCU_CWD   volatile.Register32 // 0xC
	FCCAN_CCU_IR    volatile.Register32 // 0x10
	FCCAN_CCU_IE    volatile.Register32 // 0x14
}

// CRC1
type CRC1_Type struct {
	CRC_DR   volatile.Register32 // 0x0
	CRC_IDR  volatile.Register32 // 0x4
	CRC_CR   volatile.Register32 // 0x8
	_        [4]byte
	CRC_INIT volatile.Register32 // 0x10
	CRC_POL  volatile.Register32 // 0x14
}

// CRYP1
type CRYP1_Type struct {
	CRYP_CR         volatile.Register32 // 0x0
	CRYP_SR         volatile.Register32 // 0x4
	CRYP_DIN        volatile.Register32 // 0x8
	CRYP_DOUT       volatile.Register32 // 0xC
	CRYP_DMACR      volatile.Register32 // 0x10
	CRYP_IMSCR      volatile.Register32 // 0x14
	CRYP_RISR       volatile.Register32 // 0x18
	CRYP_MISR       volatile.Register32 // 0x1C
	CRYP_K0LR       volatile.Register32 // 0x20
	CRYP_K0RR       volatile.Register32 // 0x24
	CRYP_K1LR       volatile.Register32 // 0x28
	CRYP_K1RR       volatile.Register32 // 0x2C
	CRYP_K2LR       volatile.Register32 // 0x30
	CRYP_K2RR       volatile.Register32 // 0x34
	CRYP_K3LR       volatile.Register32 // 0x38
	CRYP_K3RR       volatile.Register32 // 0x3C
	CRYP_IV0LR      volatile.Register32 // 0x40
	CRYP_IV0RR      volatile.Register32 // 0x44
	CRYP_IV1LR      volatile.Register32 // 0x48
	CRYP_IV1RR      volatile.Register32 // 0x4C
	CRYP_CSGCMCCM0R volatile.Register32 // 0x50
	CRYP_CSGCMCCM1R volatile.Register32 // 0x54
	CRYP_CSGCMCCM2R volatile.Register32 // 0x58
	CRYP_CSGCMCCM3R volatile.Register32 // 0x5C
	CRYP_CSGCMCCM4R volatile.Register32 // 0x60
	CRYP_CSGCMCCM5R volatile.Register32 // 0x64
	CRYP_CSGCMCCM6R volatile.Register32 // 0x68
	CRYP_CSGCMCCM7R volatile.Register32 // 0x6C
	CRYP_CSGCM0R    volatile.Register32 // 0x70
	CRYP_CSGCM1R    volatile.Register32 // 0x74
	CRYP_CSGCM2R    volatile.Register32 // 0x78
	CRYP_CSGCM3R    volatile.Register32 // 0x7C
	CRYP_CSGCM4R    volatile.Register32 // 0x80
	CRYP_CSGCM5R    volatile.Register32 // 0x84
	CRYP_CSGCM6R    volatile.Register32 // 0x88
	CRYP_CSGCM7R    volatile.Register32 // 0x8C
	_               [864]byte
	CRYP_HWCFGR     volatile.Register32 // 0x3F0
	CRYP_VERR       volatile.Register32 // 0x3F4
	CRYP_IPIDR      volatile.Register32 // 0x3F8
	CRYP_MID        volatile.Register32 // 0x3FC
}

// DAC1
type DAC1_Type struct {
	DAC_CR      volatile.Register32 // 0x0
	DAC_SWTRGR  volatile.Register32 // 0x4
	DAC_DHR12R1 volatile.Register32 // 0x8
	DAC_DHR12L1 volatile.Register32 // 0xC
	DAC_DHR8R1  volatile.Register32 // 0x10
	DAC_DHR12R2 volatile.Register32 // 0x14
	DAC_DHR12L2 volatile.Register32 // 0x18
	DAC_DHR8R2  volatile.Register32 // 0x1C
	DAC_DHR12RD volatile.Register32 // 0x20
	DAC_DHR12LD volatile.Register32 // 0x24
	DAC_DHR8RD  volatile.Register32 // 0x28
	DAC_DOR1    volatile.Register32 // 0x2C
	DAC_DOR2    volatile.Register32 // 0x30
	DAC_SR      volatile.Register32 // 0x34
	DAC_CCR     volatile.Register32 // 0x38
	DAC_MCR     volatile.Register32 // 0x3C
	DAC_SHSR1   volatile.Register32 // 0x40
	DAC_SHSR2   volatile.Register32 // 0x44
	DAC_SHHR    volatile.Register32 // 0x48
	DAC_SHRR    volatile.Register32 // 0x4C
	_           [928]byte
	DAC_HWCFGR0 volatile.Register32 // 0x3F0
	DAC_VERR    volatile.Register32 // 0x3F4
	DAC_IPIDR   volatile.Register32 // 0x3F8
	DAC_SIDR    volatile.Register32 // 0x3FC
}

// DCMI
type DCMI_Type struct {
	DCMI_CR     volatile.Register32 // 0x0
	DCMI_SR     volatile.Register32 // 0x4
	DCMI_RIS    volatile.Register32 // 0x8
	DCMI_IER    volatile.Register32 // 0xC
	DCMI_MIS    volatile.Register32 // 0x10
	DCMI_ICR    volatile.Register32 // 0x14
	DCMI_ESCR   volatile.Register32 // 0x18
	DCMI_ESUR   volatile.Register32 // 0x1C
	DCMI_CWSTRT volatile.Register32 // 0x20
	DCMI_CWSIZE volatile.Register32 // 0x24
	DCMI_DR     volatile.Register32 // 0x28
}

// DDRCTRL
type DDRCTRL_Type struct {
	DDRCTRL_MSTR        volatile.Register32 // 0x0
	DDRCTRL_STAT        volatile.Register32 // 0x4
	_                   [8]byte
	DDRCTRL_MRCTRL0     volatile.Register32 // 0x10
	DDRCTRL_MRCTRL1     volatile.Register32 // 0x14
	DDRCTRL_MRSTAT      volatile.Register32 // 0x18
	_                   [4]byte
	DDRCTRL_DERATEEN    volatile.Register32 // 0x20
	DDRCTRL_DERATEINT   volatile.Register32 // 0x24
	_                   [8]byte
	DDRCTRL_PWRCTL      volatile.Register32 // 0x30
	DDRCTRL_PWRTMG      volatile.Register32 // 0x34
	DDRCTRL_HWLPCTL     volatile.Register32 // 0x38
	_                   [20]byte
	DDRCTRL_RFSHCTL0    volatile.Register32 // 0x50
	_                   [12]byte
	DDRCTRL_RFSHCTL3    volatile.Register32 // 0x60
	DDRCTRL_RFSHTMG     volatile.Register32 // 0x64
	_                   [88]byte
	DDRCTRL_CRCPARCTL0  volatile.Register32 // 0xC0
	_                   [8]byte
	DDRCTRL_CRCPARSTAT  volatile.Register32 // 0xCC
	DDRCTRL_INIT0       volatile.Register32 // 0xD0
	DDRCTRL_INIT1       volatile.Register32 // 0xD4
	DDRCTRL_INIT2       volatile.Register32 // 0xD8
	DDRCTRL_INIT3       volatile.Register32 // 0xDC
	DDRCTRL_INIT4       volatile.Register32 // 0xE0
	DDRCTRL_INIT5       volatile.Register32 // 0xE4
	_                   [8]byte
	DDRCTRL_DIMMCTL     volatile.Register32 // 0xF0
	_                   [12]byte
	DDRCTRL_DRAMTMG0    volatile.Register32 // 0x100
	DDRCTRL_DRAMTMG1    volatile.Register32 // 0x104
	DDRCTRL_DRAMTMG2    volatile.Register32 // 0x108
	DDRCTRL_DRAMTMG3    volatile.Register32 // 0x10C
	DDRCTRL_DRAMTMG4    volatile.Register32 // 0x110
	DDRCTRL_DRAMTMG5    volatile.Register32 // 0x114
	DDRCTRL_DRAMTMG6    volatile.Register32 // 0x118
	DDRCTRL_DRAMTMG7    volatile.Register32 // 0x11C
	DDRCTRL_DRAMTMG8    volatile.Register32 // 0x120
	_                   [20]byte
	DDRCTRL_DRAMTMG14   volatile.Register32 // 0x138
	DDRCTRL_DRAMTMG15   volatile.Register32 // 0x13C
	_                   [64]byte
	DDRCTRL_ZQCTL0      volatile.Register32 // 0x180
	DDRCTRL_ZQCTL1      volatile.Register32 // 0x184
	DDRCTRL_ZQCTL2      volatile.Register32 // 0x188
	DDRCTRL_ZQSTAT      volatile.Register32 // 0x18C
	DDRCTRL_DFITMG0     volatile.Register32 // 0x190
	DDRCTRL_DFITMG1     volatile.Register32 // 0x194
	DDRCTRL_DFILPCFG0   volatile.Register32 // 0x198
	_                   [4]byte
	DDRCTRL_DFIUPD0     volatile.Register32 // 0x1A0
	DDRCTRL_DFIUPD1     volatile.Register32 // 0x1A4
	DDRCTRL_DFIUPD2     volatile.Register32 // 0x1A8
	_                   [4]byte
	DDRCTRL_DFIMISC     volatile.Register32 // 0x1B0
	_                   [8]byte
	DDRCTRL_DFISTAT     volatile.Register32 // 0x1BC
	_                   [4]byte
	DDRCTRL_DFIPHYMSTR  volatile.Register32 // 0x1C4
	_                   [60]byte
	DDRCTRL_ADDRMAP1    volatile.Register32 // 0x204
	DDRCTRL_ADDRMAP2    volatile.Register32 // 0x208
	DDRCTRL_ADDRMAP3    volatile.Register32 // 0x20C
	DDRCTRL_ADDRMAP4    volatile.Register32 // 0x210
	DDRCTRL_ADDRMAP5    volatile.Register32 // 0x214
	DDRCTRL_ADDRMAP6    volatile.Register32 // 0x218
	_                   [8]byte
	DDRCTRL_ADDRMAP9    volatile.Register32 // 0x224
	DDRCTRL_ADDRMAP10   volatile.Register32 // 0x228
	DDRCTRL_ADDRMAP11   volatile.Register32 // 0x22C
	_                   [16]byte
	DDRCTRL_ODTCFG      volatile.Register32 // 0x240
	DDRCTRL_ODTMAP      volatile.Register32 // 0x244
	_                   [8]byte
	DDRCTRL_SCHED       volatile.Register32 // 0x250
	DDRCTRL_SCHED1      volatile.Register32 // 0x254
	_                   [4]byte
	DDRCTRL_PERFHPR1    volatile.Register32 // 0x25C
	_                   [4]byte
	DDRCTRL_PERFLPR1    volatile.Register32 // 0x264
	_                   [4]byte
	DDRCTRL_PERFWR1     volatile.Register32 // 0x26C
	_                   [144]byte
	DDRCTRL_DBG0        volatile.Register32 // 0x300
	DDRCTRL_DBG1        volatile.Register32 // 0x304
	DDRCTRL_DBGCAM      volatile.Register32 // 0x308
	DDRCTRL_DBGCMD      volatile.Register32 // 0x30C
	DDRCTRL_DBGSTAT     volatile.Register32 // 0x310
	_                   [12]byte
	DDRCTRL_SWCTL       volatile.Register32 // 0x320
	DDRCTRL_SWSTAT      volatile.Register32 // 0x324
	_                   [68]byte
	DDRCTRL_POISONCFG   volatile.Register32 // 0x36C
	DDRCTRL_POISONSTAT  volatile.Register32 // 0x370
	_                   [136]byte
	DDRCTRL_PSTAT       volatile.Register32 // 0x3FC
	DDRCTRL_PCCFG       volatile.Register32 // 0x400
	DDRCTRL_PCFGR_0     volatile.Register32 // 0x404
	DDRCTRL_PCFGW_0     volatile.Register32 // 0x408
	_                   [132]byte
	DDRCTRL_PCTRL_0     volatile.Register32 // 0x490
	DDRCTRL_PCFGQOS0_0  volatile.Register32 // 0x494
	DDRCTRL_PCFGQOS1_0  volatile.Register32 // 0x498
	DDRCTRL_PCFGWQOS0_0 volatile.Register32 // 0x49C
	DDRCTRL_PCFGWQOS1_0 volatile.Register32 // 0x4A0
	_                   [16]byte
	DDRCTRL_PCFGR_1     volatile.Register32 // 0x4B4
	DDRCTRL_PCFGW_1     volatile.Register32 // 0x4B8
	_                   [132]byte
	DDRCTRL_PCTRL_1     volatile.Register32 // 0x540
	DDRCTRL_PCFGQOS0_1  volatile.Register32 // 0x544
	DDRCTRL_PCFGQOS1_1  volatile.Register32 // 0x548
	DDRCTRL_PCFGWQOS0_1 volatile.Register32 // 0x54C
	DDRCTRL_PCFGWQOS1_1 volatile.Register32 // 0x550
}

// DDRPERFM
type DDRPERFM_Type struct {
	DDRPERFM_CTL    volatile.Register32 // 0x0
	DDRPERFM_CFG    volatile.Register32 // 0x4
	DDRPERFM_STATUS volatile.Register32 // 0x8
	DDRPERFM_CCR    volatile.Register32 // 0xC
	DDRPERFM_IER    volatile.Register32 // 0x10
	DDRPERFM_ISR    volatile.Register32 // 0x14
	DDRPERFM_ICR    volatile.Register32 // 0x18
	_               [4]byte
	DDRPERFM_TCNT   volatile.Register32 // 0x20
	_               [60]byte
	DDRPERFM_CNT0   volatile.Register32 // 0x60
	_               [4]byte
	DDRPERFM_CNT1   volatile.Register32 // 0x68
	_               [4]byte
	DDRPERFM_CNT2   volatile.Register32 // 0x70
	_               [4]byte
	DDRPERFM_CNT3   volatile.Register32 // 0x78
	_               [884]byte
	DDRPERFM_HWCFG  volatile.Register32 // 0x3F0
	DDRPERFM_VER    volatile.Register32 // 0x3F4
	DDRPERFM_ID     volatile.Register32 // 0x3F8
	DDRPERFM_SID    volatile.Register32 // 0x3FC
}

// DDRPHYC
type DDRPHYC_Type struct {
	DDRPHYC_RIDR     volatile.Register32 // 0x0
	DDRPHYC_PIR      volatile.Register32 // 0x4
	DDRPHYC_PGCR     volatile.Register32 // 0x8
	DDRPHYC_PGSR     volatile.Register32 // 0xC
	DDRPHYC_DLLGCR   volatile.Register32 // 0x10
	DDRPHYC_ACDLLCR  volatile.Register32 // 0x14
	DDRPHYC_PTR0     volatile.Register32 // 0x18
	DDRPHYC_PTR1     volatile.Register32 // 0x1C
	DDRPHYC_PTR2     volatile.Register32 // 0x20
	DDRPHYC_ACIOCR   volatile.Register32 // 0x24
	DDRPHYC_DXCCR    volatile.Register32 // 0x28
	DDRPHYC_DSGCR    volatile.Register32 // 0x2C
	DDRPHYC_DCR      volatile.Register32 // 0x30
	DDRPHYC_DTPR0    volatile.Register32 // 0x34
	DDRPHYC_DTPR1    volatile.Register32 // 0x38
	DDRPHYC_DTPR2    volatile.Register32 // 0x3C
	DDRPHYC_DDR3_MR0 volatile.Register16 // 0x40
	_                [2]byte
	DDRPHYC_DDR3_MR1 volatile.Register16 // 0x44
	_                [2]byte
	DDRPHYC_DDR3_MR2 volatile.Register16 // 0x48
	_                [2]byte
	DDRPHYC_DDR3_MR3 volatile.Register8 // 0x4C
	_                [3]byte
	DDRPHYC_ODTCR    volatile.Register32 // 0x50
	DDRPHYC_DTAR     volatile.Register32 // 0x54
	DDRPHYC_DTDR0    volatile.Register32 // 0x58
	DDRPHYC_DTDR1    volatile.Register32 // 0x5C
	_                [280]byte
	DDRPHYC_GPR0     volatile.Register32 // 0x178
	DDRPHYC_GPR1     volatile.Register32 // 0x17C
	DDRPHYC_ZQ0CR0   volatile.Register32 // 0x180
	DDRPHYC_ZQ0CR1   volatile.Register8  // 0x184
	_                [3]byte
	DDRPHYC_ZQ0SR0   volatile.Register32 // 0x188
	DDRPHYC_ZQ0SR1   volatile.Register8  // 0x18C
	_                [51]byte
	DDRPHYC_DX0GCR   volatile.Register32 // 0x1C0
	DDRPHYC_DX0GSR0  volatile.Register16 // 0x1C4
	_                [2]byte
	DDRPHYC_DX0GSR1  volatile.Register32 // 0x1C8
	DDRPHYC_DX0DLLCR volatile.Register32 // 0x1CC
	DDRPHYC_DX0DQTR  volatile.Register32 // 0x1D0
	DDRPHYC_DX0DQSTR volatile.Register32 // 0x1D4
	_                [40]byte
	DDRPHYC_DX1GCR   volatile.Register32 // 0x200
	DDRPHYC_DX1GSR0  volatile.Register16 // 0x204
	_                [2]byte
	DDRPHYC_DX1GSR1  volatile.Register32 // 0x208
	DDRPHYC_DX1DLLCR volatile.Register32 // 0x20C
	DDRPHYC_DX1DQTR  volatile.Register32 // 0x210
	DDRPHYC_DX1DQSTR volatile.Register32 // 0x214
	_                [40]byte
	DDRPHYC_DX2GCR   volatile.Register32 // 0x240
	DDRPHYC_DX2GSR0  volatile.Register16 // 0x244
	_                [2]byte
	DDRPHYC_DX2GSR1  volatile.Register32 // 0x248
	DDRPHYC_DX2DLLCR volatile.Register32 // 0x24C
	DDRPHYC_DX2DQTR  volatile.Register32 // 0x250
	DDRPHYC_DX2DQSTR volatile.Register32 // 0x254
	_                [40]byte
	DDRPHYC_DX3GCR   volatile.Register32 // 0x280
	DDRPHYC_DX3GSR0  volatile.Register16 // 0x284
	_                [2]byte
	DDRPHYC_DX3GSR1  volatile.Register32 // 0x288
	DDRPHYC_DX3DLLCR volatile.Register32 // 0x28C
	DDRPHYC_DX3DQTR  volatile.Register32 // 0x290
	DDRPHYC_DX3DQSTR volatile.Register32 // 0x294
}

// DFSDM1
type DFSDM1_Type struct {
	DFSDM_CH0CFGR1    volatile.Register32 // 0x0
	DFSDM_CH0CFGR2    volatile.Register32 // 0x4
	DFSDM_CH0AWSCDR   volatile.Register32 // 0x8
	DFSDM_CH0WDATR    volatile.Register32 // 0xC
	DFSDM_CH0DATINR   volatile.Register32 // 0x10
	DFSDM_CH0DLYR     volatile.Register32 // 0x14
	_                 [8]byte
	DFSDM_CH1CFGR1    volatile.Register32 // 0x20
	DFSDM_CH1CFGR2    volatile.Register32 // 0x24
	DFSDM_CH1AWSCDR   volatile.Register32 // 0x28
	DFSDM_CH1WDATR    volatile.Register32 // 0x2C
	DFSDM_CH1DATINR   volatile.Register32 // 0x30
	DFSDM_CH1DLYR     volatile.Register32 // 0x34
	_                 [8]byte
	DFSDM_CH2CFGR1    volatile.Register32 // 0x40
	DFSDM_CH2CFGR2    volatile.Register32 // 0x44
	DFSDM_CH2AWSCDR   volatile.Register32 // 0x48
	DFSDM_CH2WDATR    volatile.Register32 // 0x4C
	DFSDM_CH2DATINR   volatile.Register32 // 0x50
	DFSDM_CH2DLYR     volatile.Register32 // 0x54
	_                 [8]byte
	DFSDM_CH3CFGR1    volatile.Register32 // 0x60
	DFSDM_CH3CFGR2    volatile.Register32 // 0x64
	DFSDM_CH3AWSCDR   volatile.Register32 // 0x68
	DFSDM_CH3WDATR    volatile.Register32 // 0x6C
	DFSDM_CH3DATINR   volatile.Register32 // 0x70
	DFSDM_CH3DLYR     volatile.Register32 // 0x74
	_                 [8]byte
	DFSDM_CH4CFGR1    volatile.Register32 // 0x80
	DFSDM_CH4CFGR2    volatile.Register32 // 0x84
	DFSDM_CH4AWSCDR   volatile.Register32 // 0x88
	DFSDM_CH4WDATR    volatile.Register32 // 0x8C
	DFSDM_CH4DATINR   volatile.Register32 // 0x90
	DFSDM_CH4DLYR     volatile.Register32 // 0x94
	_                 [8]byte
	DFSDM_CH5CFGR1    volatile.Register32 // 0xA0
	DFSDM_CH5CFGR2    volatile.Register32 // 0xA4
	DFSDM_CH5AWSCDR   volatile.Register32 // 0xA8
	DFSDM_CH5WDATR    volatile.Register32 // 0xAC
	DFSDM_CH5DATINR   volatile.Register32 // 0xB0
	DFSDM_CH5DLYR     volatile.Register32 // 0xB4
	_                 [8]byte
	DFSDM_CH6CFGR1    volatile.Register32 // 0xC0
	DFSDM_CH6CFGR2    volatile.Register32 // 0xC4
	DFSDM_CH6AWSCDR   volatile.Register32 // 0xC8
	DFSDM_CH6WDATR    volatile.Register32 // 0xCC
	DFSDM_CH6DATINR   volatile.Register32 // 0xD0
	DFSDM_CH6DLYR     volatile.Register32 // 0xD4
	_                 [8]byte
	DFSDM_CH7CFGR1    volatile.Register32 // 0xE0
	DFSDM_CH7CFGR2    volatile.Register32 // 0xE4
	DFSDM_CH7AWSCDR   volatile.Register32 // 0xE8
	DFSDM_CH7WDATR    volatile.Register32 // 0xEC
	DFSDM_CH7DATINR   volatile.Register32 // 0xF0
	DFSDM_CH7DLYR     volatile.Register32 // 0xF4
	_                 [8]byte
	DFSDM_FLT0CR1     volatile.Register32 // 0x100
	DFSDM_FLT0CR2     volatile.Register32 // 0x104
	DFSDM_FLT0ISR     volatile.Register32 // 0x108
	DFSDM_FLT0ICR     volatile.Register32 // 0x10C
	DFSDM_FLT0JCHGR   volatile.Register32 // 0x110
	DFSDM_FLT0FCR     volatile.Register32 // 0x114
	DFSDM_FLT0JDATAR  volatile.Register32 // 0x118
	DFSDM_FLT0RDATAR  volatile.Register32 // 0x11C
	DFSDM_FLT0AWHTR   volatile.Register32 // 0x120
	DFSDM_FLT0AWLTR   volatile.Register32 // 0x124
	DFSDM_FLT0AWSR    volatile.Register32 // 0x128
	DFSDM_FLT0AWCFR   volatile.Register32 // 0x12C
	DFSDM_FLT0EXMAX   volatile.Register32 // 0x130
	DFSDM_FLT0EXMIN   volatile.Register32 // 0x134
	DFSDM_FLT0CNVTIMR volatile.Register32 // 0x138
	_                 [68]byte
	DFSDM_FLT1CR1     volatile.Register32 // 0x180
	DFSDM_FLT1CR2     volatile.Register32 // 0x184
	DFSDM_FLT1ISR     volatile.Register32 // 0x188
	DFSDM_FLT1ICR     volatile.Register32 // 0x18C
	DFSDM_FLT1JCHGR   volatile.Register32 // 0x190
	DFSDM_FLT1FCR     volatile.Register32 // 0x194
	DFSDM_FLT1JDATAR  volatile.Register32 // 0x198
	DFSDM_FLT1RDATAR  volatile.Register32 // 0x19C
	DFSDM_FLT1AWHTR   volatile.Register32 // 0x1A0
	DFSDM_FLT1AWLTR   volatile.Register32 // 0x1A4
	DFSDM_FLT1AWSR    volatile.Register32 // 0x1A8
	DFSDM_FLT1AWCFR   volatile.Register32 // 0x1AC
	DFSDM_FLT1EXMAX   volatile.Register32 // 0x1B0
	DFSDM_FLT1EXMIN   volatile.Register32 // 0x1B4
	DFSDM_FLT1CNVTIMR volatile.Register32 // 0x1B8
	_                 [68]byte
	DFSDM_FLT2CR1     volatile.Register32 // 0x200
	DFSDM_FLT2CR2     volatile.Register32 // 0x204
	DFSDM_FLT2ISR     volatile.Register32 // 0x208
	DFSDM_FLT2ICR     volatile.Register32 // 0x20C
	DFSDM_FLT2JCHGR   volatile.Register32 // 0x210
	DFSDM_FLT2FCR     volatile.Register32 // 0x214
	DFSDM_FLT2JDATAR  volatile.Register32 // 0x218
	DFSDM_FLT2RDATAR  volatile.Register32 // 0x21C
	DFSDM_FLT2AWHTR   volatile.Register32 // 0x220
	DFSDM_FLT2AWLTR   volatile.Register32 // 0x224
	DFSDM_FLT2AWSR    volatile.Register32 // 0x228
	DFSDM_FLT2AWCFR   volatile.Register32 // 0x22C
	DFSDM_FLT2EXMAX   volatile.Register32 // 0x230
	DFSDM_FLT2EXMIN   volatile.Register32 // 0x234
	DFSDM_FLT2CNVTIMR volatile.Register32 // 0x238
	_                 [68]byte
	DFSDM_FLT3CR1     volatile.Register32 // 0x280
	DFSDM_FLT3CR2     volatile.Register32 // 0x284
	DFSDM_FLT3ISR     volatile.Register32 // 0x288
	DFSDM_FLT3ICR     volatile.Register32 // 0x28C
	DFSDM_FLT3JCHGR   volatile.Register32 // 0x290
	DFSDM_FLT3FCR     volatile.Register32 // 0x294
	DFSDM_FLT3JDATAR  volatile.Register32 // 0x298
	DFSDM_FLT3RDATAR  volatile.Register32 // 0x29C
	DFSDM_FLT3AWHTR   volatile.Register32 // 0x2A0
	DFSDM_FLT3AWLTR   volatile.Register32 // 0x2A4
	DFSDM_FLT3AWSR    volatile.Register32 // 0x2A8
	DFSDM_FLT3AWCFR   volatile.Register32 // 0x2AC
	DFSDM_FLT3EXMAX   volatile.Register32 // 0x2B0
	DFSDM_FLT3EXMIN   volatile.Register32 // 0x2B4
	DFSDM_FLT3CNVTIMR volatile.Register32 // 0x2B8
	_                 [68]byte
	DFSDM_FLT4CR1     volatile.Register32 // 0x300
	DFSDM_FLT4CR2     volatile.Register32 // 0x304
	DFSDM_FLT4ISR     volatile.Register32 // 0x308
	DFSDM_FLT4ICR     volatile.Register32 // 0x30C
	DFSDM_FLT4JCHGR   volatile.Register32 // 0x310
	DFSDM_FLT4FCR     volatile.Register32 // 0x314
	DFSDM_FLT4JDATAR  volatile.Register32 // 0x318
	DFSDM_FLT4RDATAR  volatile.Register32 // 0x31C
	DFSDM_FLT4AWHTR   volatile.Register32 // 0x320
	DFSDM_FLT4AWLTR   volatile.Register32 // 0x324
	DFSDM_FLT4AWSR    volatile.Register32 // 0x328
	DFSDM_FLT4AWCFR   volatile.Register32 // 0x32C
	DFSDM_FLT4EXMAX   volatile.Register32 // 0x330
	DFSDM_FLT4EXMIN   volatile.Register32 // 0x334
	DFSDM_FLT4CNVTIMR volatile.Register32 // 0x338
	_                 [68]byte
	DFSDM_FLT5CR1     volatile.Register32 // 0x380
	DFSDM_FLT5CR2     volatile.Register32 // 0x384
	DFSDM_FLT5ISR     volatile.Register32 // 0x388
	DFSDM_FLT5ICR     volatile.Register32 // 0x38C
	DFSDM_FLT5JCHGR   volatile.Register32 // 0x390
	DFSDM_FLT5FCR     volatile.Register32 // 0x394
	DFSDM_FLT5JDATAR  volatile.Register32 // 0x398
	DFSDM_FLT5RDATAR  volatile.Register32 // 0x39C
	DFSDM_FLT5AWHTR   volatile.Register32 // 0x3A0
	DFSDM_FLT5AWLTR   volatile.Register32 // 0x3A4
	DFSDM_FLT5AWSR    volatile.Register32 // 0x3A8
	DFSDM_FLT5AWCFR   volatile.Register32 // 0x3AC
	DFSDM_FLT5EXMAX   volatile.Register32 // 0x3B0
	DFSDM_FLT5EXMIN   volatile.Register32 // 0x3B4
	DFSDM_FLT5CNVTIMR volatile.Register32 // 0x3B8
	_                 [1076]byte
	DFSDM_HWCFGR      volatile.Register32 // 0x7F0
	DFSDM_VERR        volatile.Register32 // 0x7F4
	DFSDM_IPIDR       volatile.Register32 // 0x7F8
	DFSDM_SIDR        volatile.Register32 // 0x7FC
}

// DLYBQS
type DLYB_Type struct {
	DLYB_CR    volatile.Register32 // 0x0
	DLYB_CFGR  volatile.Register32 // 0x4
	_          [1004]byte
	DLYB_VERR  volatile.Register32 // 0x3F4
	DLYB_IPIDR volatile.Register32 // 0x3F8
	DLYB_SIDR  volatile.Register32 // 0x3FC
}

// DLYBSD1
type DLYBSD1_Type struct {
	DLYB_CR    volatile.Register32 // 0x0
	DLYB_CFGR  volatile.Register32 // 0x4
	_          [1004]byte
	DLYB_VERR  volatile.Register32 // 0x3F4
	DLYB_IPIDR volatile.Register32 // 0x3F8
	DLYB_SIDR  volatile.Register32 // 0x3FC
}

// DMA1
type DMA1_Type struct {
	DMA_LISR    volatile.Register32 // 0x0
	DMA_HISR    volatile.Register32 // 0x4
	DMA_LIFCR   volatile.Register32 // 0x8
	DMA_HIFCR   volatile.Register32 // 0xC
	DMA_S0CR    volatile.Register32 // 0x10
	DMA_S0NDTR  volatile.Register32 // 0x14
	DMA_S0PAR   volatile.Register32 // 0x18
	DMA_S0M0AR  volatile.Register32 // 0x1C
	DMA_S0M1AR  volatile.Register32 // 0x20
	DMA_S0FCR   volatile.Register32 // 0x24
	DMA_S1CR    volatile.Register32 // 0x28
	DMA_S1NDTR  volatile.Register32 // 0x2C
	DMA_S1PAR   volatile.Register32 // 0x30
	DMA_S1M0AR  volatile.Register32 // 0x34
	DMA_S1M1AR  volatile.Register32 // 0x38
	DMA_S1FCR   volatile.Register32 // 0x3C
	DMA_S2CR    volatile.Register32 // 0x40
	DMA_S2NDTR  volatile.Register32 // 0x44
	DMA_S2PAR   volatile.Register32 // 0x48
	DMA_S2M0AR  volatile.Register32 // 0x4C
	DMA_S2M1AR  volatile.Register32 // 0x50
	DMA_S2FCR   volatile.Register32 // 0x54
	DMA_S3CR    volatile.Register32 // 0x58
	DMA_S3NDTR  volatile.Register32 // 0x5C
	DMA_S3PAR   volatile.Register32 // 0x60
	DMA_S3M0AR  volatile.Register32 // 0x64
	DMA_S3M1AR  volatile.Register32 // 0x68
	DMA_S3FCR   volatile.Register32 // 0x6C
	DMA_S4CR    volatile.Register32 // 0x70
	DMA_S4NDTR  volatile.Register32 // 0x74
	DMA_S4PAR   volatile.Register32 // 0x78
	DMA_S4M0AR  volatile.Register32 // 0x7C
	DMA_S4M1AR  volatile.Register32 // 0x80
	DMA_S4FCR   volatile.Register32 // 0x84
	DMA_S5CR    volatile.Register32 // 0x88
	DMA_S5NDTR  volatile.Register32 // 0x8C
	DMA_S5PAR   volatile.Register32 // 0x90
	DMA_S5M0AR  volatile.Register32 // 0x94
	DMA_S5M1AR  volatile.Register32 // 0x98
	DMA_S5FCR   volatile.Register32 // 0x9C
	DMA_S6CR    volatile.Register32 // 0xA0
	DMA_S6NDTR  volatile.Register32 // 0xA4
	DMA_S6PAR   volatile.Register32 // 0xA8
	DMA_S6M0AR  volatile.Register32 // 0xAC
	DMA_S6M1AR  volatile.Register32 // 0xB0
	DMA_S6FCR   volatile.Register32 // 0xB4
	DMA_S7CR    volatile.Register32 // 0xB8
	DMA_S7NDTR  volatile.Register32 // 0xBC
	DMA_S7PAR   volatile.Register32 // 0xC0
	DMA_S7M0AR  volatile.Register32 // 0xC4
	DMA_S7M1AR  volatile.Register32 // 0xC8
	DMA_S7FCR   volatile.Register32 // 0xCC
	_           [796]byte
	DMA_HWCFGR2 volatile.Register32 // 0x3EC
	DMA_HWCFGR1 volatile.Register32 // 0x3F0
	DMA_VERR    volatile.Register32 // 0x3F4
	DMA_IPDR    volatile.Register32 // 0x3F8
	DMA_SIDR    volatile.Register32 // 0x3FC
}

// DMAMUX1
type DMAMUX1_Type struct {
	DMAMUX_C0CR    volatile.Register32 // 0x0
	DMAMUX_C1CR    volatile.Register32 // 0x4
	DMAMUX_C2CR    volatile.Register32 // 0x8
	DMAMUX_C3CR    volatile.Register32 // 0xC
	DMAMUX_C4CR    volatile.Register32 // 0x10
	DMAMUX_C5CR    volatile.Register32 // 0x14
	DMAMUX_C6CR    volatile.Register32 // 0x18
	DMAMUX_C7CR    volatile.Register32 // 0x1C
	DMAMUX_C8CR    volatile.Register32 // 0x20
	DMAMUX_C9CR    volatile.Register32 // 0x24
	DMAMUX_C10CR   volatile.Register32 // 0x28
	DMAMUX_C11CR   volatile.Register32 // 0x2C
	DMAMUX_C12CR   volatile.Register32 // 0x30
	DMAMUX_C13CR   volatile.Register32 // 0x34
	DMAMUX_C14CR   volatile.Register32 // 0x38
	DMAMUX_C15CR   volatile.Register32 // 0x3C
	_              [64]byte
	DMAMUX_CSR     volatile.Register32 // 0x80
	DMAMUX_CFR     volatile.Register32 // 0x84
	_              [120]byte
	DMAMUX_RG0CR   volatile.Register32 // 0x100
	DMAMUX_RG1CR   volatile.Register32 // 0x104
	DMAMUX_RG2CR   volatile.Register32 // 0x108
	DMAMUX_RG3CR   volatile.Register32 // 0x10C
	DMAMUX_RG4CR   volatile.Register32 // 0x110
	DMAMUX_RG5CR   volatile.Register32 // 0x114
	DMAMUX_RG6CR   volatile.Register32 // 0x118
	DMAMUX_RG7CR   volatile.Register32 // 0x11C
	_              [32]byte
	DMAMUX_RGSR    volatile.Register32 // 0x140
	DMAMUX_RGCFR   volatile.Register32 // 0x144
	_              [676]byte
	DMAMUX_HWCFGR2 volatile.Register32 // 0x3EC
	DMAMUX_HWCFGR1 volatile.Register32 // 0x3F0
	DMAMUX_VERR    volatile.Register32 // 0x3F4
	DMAMUX_IPIDR   volatile.Register32 // 0x3F8
	DMAMUX_SIDR    volatile.Register32 // 0x3FC
}

// DSIHOST1
type DSIHOST1_Type struct {
	DSI_VR      volatile.Register32 // 0x0
	DSI_CR      volatile.Register32 // 0x4
	DSI_CCR     volatile.Register32 // 0x8
	DSI_LVCIDR  volatile.Register32 // 0xC
	DSI_LCOLCR  volatile.Register32 // 0x10
	DSI_LPCR    volatile.Register32 // 0x14
	DSI_LPMCR   volatile.Register32 // 0x18
	_           [16]byte
	DSI_PCR     volatile.Register32 // 0x2C
	DSI_GVCIDR  volatile.Register32 // 0x30
	DSI_MCR     volatile.Register32 // 0x34
	DSI_VMCR    volatile.Register32 // 0x38
	DSI_VPCR    volatile.Register32 // 0x3C
	DSI_VCCR    volatile.Register32 // 0x40
	DSI_VNPCR   volatile.Register32 // 0x44
	DSI_VHSACR  volatile.Register32 // 0x48
	DSI_VHBPCR  volatile.Register32 // 0x4C
	DSI_VLCR    volatile.Register32 // 0x50
	DSI_VVSACR  volatile.Register32 // 0x54
	DSI_VVBPCR  volatile.Register32 // 0x58
	DSI_VVFPCR  volatile.Register32 // 0x5C
	DSI_VVACR   volatile.Register32 // 0x60
	DSI_LCCR    volatile.Register32 // 0x64
	DSI_CMCR    volatile.Register32 // 0x68
	DSI_GHCR    volatile.Register32 // 0x6C
	DSI_GPDR    volatile.Register32 // 0x70
	DSI_GPSR    volatile.Register32 // 0x74
	DSI_TCCR0   volatile.Register32 // 0x78
	DSI_TCCR1   volatile.Register32 // 0x7C
	DSI_TCCR2   volatile.Register32 // 0x80
	DSI_TCCR3   volatile.Register32 // 0x84
	DSI_TCCR4   volatile.Register32 // 0x88
	DSI_TCCR5   volatile.Register32 // 0x8C
	_           [4]byte
	DSI_CLCR    volatile.Register32 // 0x94
	DSI_CLTCR   volatile.Register32 // 0x98
	DSI_DLTCR   volatile.Register32 // 0x9C
	DSI_PCTLR   volatile.Register32 // 0xA0
	DSI_PCONFR  volatile.Register32 // 0xA4
	DSI_PUCR    volatile.Register32 // 0xA8
	DSI_PTTCR   volatile.Register32 // 0xAC
	DSI_PSR     volatile.Register32 // 0xB0
	_           [8]byte
	DSI_ISR0    volatile.Register32 // 0xBC
	DSI_ISR1    volatile.Register32 // 0xC0
	DSI_IER0    volatile.Register32 // 0xC4
	DSI_IER1    volatile.Register32 // 0xC8
	_           [12]byte
	DSI_FIR0    volatile.Register32 // 0xD8
	DSI_FIR1    volatile.Register32 // 0xDC
	_           [20]byte
	DSI_DLTRCR  volatile.Register32 // 0xF4
	_           [8]byte
	DSI_VSCR    volatile.Register32 // 0x100
	_           [8]byte
	DSI_LCVCIDR volatile.Register32 // 0x10C
	DSI_LCCCR   volatile.Register32 // 0x110
	_           [4]byte
	DSI_LPMCCR  volatile.Register32 // 0x118
	_           [28]byte
	DSI_VMCCR   volatile.Register32 // 0x138
	DSI_VPCCR   volatile.Register32 // 0x13C
	DSI_VCCCR   volatile.Register32 // 0x140
	DSI_VNPCCR  volatile.Register32 // 0x144
	DSI_VHSACCR volatile.Register32 // 0x148
	DSI_VHBPCCR volatile.Register32 // 0x14C
	DSI_VLCCR   volatile.Register32 // 0x150
	DSI_VVSACCR volatile.Register32 // 0x154
	DSI_VVBPCCR volatile.Register32 // 0x158
	DSI_VVFPCCR volatile.Register32 // 0x15C
	DSI_VVACCR  volatile.Register32 // 0x160
	_           [668]byte
	DSI_WCFGR   volatile.Register32 // 0x400
	DSI_WCR     volatile.Register32 // 0x404
	DSI_WIER    volatile.Register32 // 0x408
	DSI_WISR    volatile.Register32 // 0x40C
	DSI_WIFCR   volatile.Register32 // 0x410
	_           [4]byte
	DSI_WPCR0   volatile.Register32 // 0x418
	DSI_WPCR1   volatile.Register32 // 0x41C
	_           [16]byte
	DSI_WRPCR   volatile.Register32 // 0x430
	_           [956]byte
	DSI_HWCFGR  volatile.Register32 // 0x7F0
	DSI_VERR    volatile.Register32 // 0x7F4
	DSI_IPIDR   volatile.Register32 // 0x7F8
	DSI_SIDR    volatile.Register32 // 0x7FC
}

// DTS register block
type DTS_Type struct {
	DTS_CFGR1    volatile.Register32 // 0x0
	_            [4]byte
	DTS_T0VALR1  volatile.Register32 // 0x8
	_            [4]byte
	DTS_RAMPVALR volatile.Register32 // 0x10
	DTS_ITR1     volatile.Register32 // 0x14
	_            [4]byte
	DTS_DR       volatile.Register32 // 0x1C
	DTS_SR       volatile.Register32 // 0x20
	DTS_ITENR    volatile.Register32 // 0x24
	DTS_ICIFR    volatile.Register32 // 0x28
	DTS_OR       volatile.Register32 // 0x2C
}

// ETH_MAC_MMC
type Ethernet_Type struct {
	ETH_MACCR                          volatile.Register32 // 0x0
	ETH_MACECR                         volatile.Register32 // 0x4
	ETH_MACPFR                         volatile.Register32 // 0x8
	ETH_MACWTR                         volatile.Register32 // 0xC
	ETH_MACHT0R                        volatile.Register32 // 0x10
	ETH_MACHT1R                        volatile.Register32 // 0x14
	_                                  [56]byte
	ETH_MACVTR                         volatile.Register32 // 0x50
	_                                  [4]byte
	ETH_MACVHTR                        volatile.Register32 // 0x58
	_                                  [4]byte
	ETH_MACVIR                         volatile.Register32 // 0x60
	ETH_MACIVIR                        volatile.Register32 // 0x64
	_                                  [8]byte
	ETH_MACQ0TxFCR                     volatile.Register32 // 0x70
	_                                  [28]byte
	ETH_MACRxFCR                       volatile.Register32 // 0x90
	_                                  [4]byte
	ETH_MACTxQPMR                      volatile.Register32 // 0x98
	_                                  [4]byte
	ETH_MACRxQC0R                      volatile.Register32 // 0xA0
	ETH_MACRxQC1R                      volatile.Register32 // 0xA4
	ETH_MACRxQC2R                      volatile.Register32 // 0xA8
	_                                  [4]byte
	ETH_MACISR                         volatile.Register32 // 0xB0
	ETH_MACIER                         volatile.Register32 // 0xB4
	ETH_MACRxTxSR                      volatile.Register32 // 0xB8
	_                                  [4]byte
	ETH_MACPCSR                        volatile.Register32 // 0xC0
	ETH_MACRWKPFR                      volatile.Register32 // 0xC4
	_                                  [8]byte
	ETH_MACLCSR                        volatile.Register32 // 0xD0
	ETH_MACLTCR                        volatile.Register32 // 0xD4
	ETH_MACLETR                        volatile.Register32 // 0xD8
	ETH_MAC1USTCR                      volatile.Register32 // 0xDC
	_                                  [24]byte
	ETH_MACPHYCSR                      volatile.Register32 // 0xF8
	_                                  [20]byte
	ETH_MACVR                          volatile.Register32 // 0x110
	ETH_MACDR                          volatile.Register32 // 0x114
	_                                  [8]byte
	ETH_MACHWF1R                       volatile.Register32 // 0x120
	ETH_MACHWF2R                       volatile.Register32 // 0x124
	_                                  [216]byte
	ETH_MACMDIOAR                      volatile.Register32 // 0x200
	ETH_MACMDIODR                      volatile.Register32 // 0x204
	_                                  [248]byte
	ETH_MACA0HR                        volatile.Register32 // 0x300
	ETH_MACA0LR                        volatile.Register32 // 0x304
	ETH_MACA1HR                        volatile.Register32 // 0x308
	ETH_MACA1LR                        volatile.Register32 // 0x30C
	ETH_MACA2HR                        volatile.Register32 // 0x310
	ETH_MACA2LR                        volatile.Register32 // 0x314
	ETH_MACA3HR                        volatile.Register32 // 0x318
	ETH_MACA3LR                        volatile.Register32 // 0x31C
	_                                  [992]byte
	MMC_CONTROL                        volatile.Register32 // 0x700
	MMC_RX_INTERRUPT                   volatile.Register32 // 0x704
	MMC_TX_INTERRUPT                   volatile.Register32 // 0x708
	MMC_RX_INTERRUPT_MASK              volatile.Register32 // 0x70C
	MMC_TX_INTERRUPT_MASK              volatile.Register32 // 0x710
	_                                  [56]byte
	TX_SINGLE_COLLISION_GOOD_PACKETS   volatile.Register32 // 0x74C
	TX_MULTIPLE_COLLISION_GOOD_PACKETS volatile.Register32 // 0x750
	_                                  [20]byte
	TX_PACKET_COUNT_GOOD               volatile.Register32 // 0x768
	_                                  [40]byte
	RX_CRC_ERROR_PACKETS               volatile.Register32 // 0x794
	RX_ALIGNMENT_ERROR_PACKETS         volatile.Register32 // 0x798
	_                                  [40]byte
	RX_UNICAST_PACKETS_GOOD            volatile.Register32 // 0x7C4
	_                                  [36]byte
	TX_LPI_USEC_CNTR                   volatile.Register32 // 0x7EC
	TX_LPI_TRAN_CNTR                   volatile.Register32 // 0x7F0
	RX_LPI_USEC_CNTR                   volatile.Register32 // 0x7F4
	RX_LPI_TRAN_CNTR                   volatile.Register32 // 0x7F8
	_                                  [260]byte
	ETH_MACL3L4C0R                     volatile.Register32 // 0x900
	ETH_MACL4A0R                       volatile.Register32 // 0x904
	_                                  [8]byte
	ETH_MACL3A00R                      volatile.Register32 // 0x910
	ETH_MACL3A10R                      volatile.Register32 // 0x914
	ETH_MACL3A20                       volatile.Register32 // 0x918
	ETH_MACL3A30                       volatile.Register32 // 0x91C
	_                                  [16]byte
	ETH_MACL3L4C1R                     volatile.Register32 // 0x930
	ETH_MACL4A1R                       volatile.Register32 // 0x934
	_                                  [8]byte
	ETH_MACL3A01R                      volatile.Register32 // 0x940
	ETH_MACL3A11R                      volatile.Register32 // 0x944
	ETH_MACL3A21R                      volatile.Register32 // 0x948
	ETH_MACL3A31R                      volatile.Register32 // 0x94C
	_                                  [400]byte
	ETH_MACARPAR                       volatile.Register32 // 0xAE0
	_                                  [28]byte
	ETH_MACTSCR                        volatile.Register32 // 0xB00
	ETH_MACSSIR                        volatile.Register32 // 0xB04
	ETH_MACSTSR                        volatile.Register32 // 0xB08
	ETH_MACSTNR                        volatile.Register32 // 0xB0C
	ETH_MACSTSUR                       volatile.Register32 // 0xB10
	ETH_MACSTNUR                       volatile.Register32 // 0xB14
	ETH_MACTSAR                        volatile.Register32 // 0xB18
	_                                  [4]byte
	ETH_MACTSSR                        volatile.Register32 // 0xB20
	_                                  [12]byte
	ETH_MACTxTSSNR                     volatile.Register32 // 0xB30
	ETH_MACTxTSSSR                     volatile.Register32 // 0xB34
	_                                  [8]byte
	ETH_MACACR                         volatile.Register32 // 0xB40
	_                                  [4]byte
	ETH_MACATSNR                       volatile.Register32 // 0xB48
	ETH_MACATSSR                       volatile.Register32 // 0xB4C
	ETH_MACTSIACR                      volatile.Register32 // 0xB50
	ETH_MACTSEACR                      volatile.Register32 // 0xB54
	ETH_MACTSICNR                      volatile.Register32 // 0xB58
	ETH_MACTSECNR                      volatile.Register32 // 0xB5C
	_                                  [16]byte
	ETH_MACPPSCR                       volatile.Register32 // 0xB70
	_                                  [12]byte
	ETH_MACPPSTTSR                     volatile.Register32 // 0xB80
	ETH_MACPPSTTNR                     volatile.Register32 // 0xB84
	ETH_MACPPSIR                       volatile.Register32 // 0xB88
	ETH_MACPPSWR                       volatile.Register32 // 0xB8C
	_                                  [48]byte
	ETH_MACPOCR                        volatile.Register32 // 0xBC0
	ETH_MACSPI0R                       volatile.Register32 // 0xBC4
	ETH_MACSPI1R                       volatile.Register32 // 0xBC8
	ETH_MACSPI2R                       volatile.Register32 // 0xBCC
	ETH_MACLMIR                        volatile.Register32 // 0xBD0
}

// ETZPC
type ETZPC_Type struct {
	ETZPC_TZMA0_SIZE    volatile.Register32 // 0x0
	ETZPC_TZMA1_SIZE    volatile.Register32 // 0x4
	_                   [8]byte
	ETZPC_DECPROT0      volatile.Register32 // 0x10
	ETZPC_DECPROT1      volatile.Register32 // 0x14
	ETZPC_DECPROT2      volatile.Register32 // 0x18
	ETZPC_DECPROT3      volatile.Register32 // 0x1C
	ETZPC_DECPROT4      volatile.Register32 // 0x20
	ETZPC_DECPROT5      volatile.Register32 // 0x24
	_                   [8]byte
	ETZPC_DECPROT_LOCK0 volatile.Register32 // 0x30
	ETZPC_DECPROT_LOCK1 volatile.Register32 // 0x34
	ETZPC_DECPROT_LOCK2 volatile.Register32 // 0x38
	_                   [948]byte
	ETZPC_HWCFGR        volatile.Register32 // 0x3F0
	ETZPC_VERR          volatile.Register32 // 0x3F4
	ETZPC_IDR           volatile.Register32 // 0x3F8
	ETZPC_SIDR          volatile.Register32 // 0x3FC
}

// EXTI
type EXTI_Type struct {
	EXTI_RTSR1    volatile.Register32 // 0x0
	EXTI_FTSR1    volatile.Register32 // 0x4
	EXTI_SWIER1   volatile.Register32 // 0x8
	EXTI_RPR1     volatile.Register32 // 0xC
	EXTI_FPR1     volatile.Register32 // 0x10
	EXTI_TZENR1   volatile.Register32 // 0x14
	_             [8]byte
	EXTI_RTSR2    volatile.Register32 // 0x20
	EXTI_FTSR2    volatile.Register32 // 0x24
	EXTI_SWIER2   volatile.Register32 // 0x28
	EXTI_RPR2     volatile.Register32 // 0x2C
	EXTI_FPR2     volatile.Register32 // 0x30
	EXTI_TZENR2   volatile.Register32 // 0x34
	_             [8]byte
	EXTI_RTSR3    volatile.Register32 // 0x40
	EXTI_FTSR3    volatile.Register32 // 0x44
	EXTI_SWIER3   volatile.Register32 // 0x48
	EXTI_RPR3     volatile.Register32 // 0x4C
	EXTI_FPR3     volatile.Register32 // 0x50
	EXTI_TZENR3   volatile.Register32 // 0x54
	_             [8]byte
	EXTI_EXTICR1  volatile.Register32 // 0x60
	EXTI_EXTICR2  volatile.Register32 // 0x64
	EXTI_EXTICR3  volatile.Register32 // 0x68
	EXTI_EXTICR4  volatile.Register32 // 0x6C
	_             [16]byte
	EXTI_IMR1     volatile.Register32 // 0x80
	EXTI_EMR1     volatile.Register32 // 0x84
	_             [8]byte
	EXTI_IMR2     volatile.Register32 // 0x90
	EXTI_EMR2     volatile.Register32 // 0x94
	_             [8]byte
	EXTI_IMR3     volatile.Register32 // 0xA0
	EXTI_EMR3     volatile.Register32 // 0xA4
	_             [24]byte
	EXTI_C2IMR1   volatile.Register32 // 0xC0
	EXTI_C2EMR1   volatile.Register32 // 0xC4
	_             [8]byte
	EXTI_C2IMR2   volatile.Register32 // 0xD0
	EXTI_C2EMR2   volatile.Register32 // 0xD4
	_             [8]byte
	EXTI_C2IMR3   volatile.Register32 // 0xE0
	EXTI_C2EMR3   volatile.Register32 // 0xE4
	_             [728]byte
	EXTI_HWCFGR13 volatile.Register32 // 0x3C0
	EXTI_HWCFGR12 volatile.Register32 // 0x3C4
	EXTI_HWCFGR11 volatile.Register32 // 0x3C8
	EXTI_HWCFGR10 volatile.Register32 // 0x3CC
	EXTI_HWCFGR9  volatile.Register32 // 0x3D0
	EXTI_HWCFGR8  volatile.Register32 // 0x3D4
	EXTI_HWCFGR7  volatile.Register32 // 0x3D8
	EXTI_HWCFGR6  volatile.Register32 // 0x3DC
	EXTI_HWCFGR5  volatile.Register32 // 0x3E0
	EXTI_HWCFGR4  volatile.Register32 // 0x3E4
	EXTI_HWCFGR3  volatile.Register32 // 0x3E8
	EXTI_HWCFGR2  volatile.Register32 // 0x3EC
	EXTI_HWCFGR1  volatile.Register32 // 0x3F0
	EXTI_VERR     volatile.Register32 // 0x3F4
	EXTI_IPIDR    volatile.Register32 // 0x3F8
	EXTI_SIDR     volatile.Register32 // 0x3FC
}

// FDCAN1
type FDCAN1_Type struct {
	FDCAN_CREL   volatile.Register32 // 0x0
	FDCAN_ENDN   volatile.Register32 // 0x4
	_            [4]byte
	FDCAN_DBTP   volatile.Register32 // 0xC
	FDCAN_TEST   volatile.Register32 // 0x10
	FDCAN_RWD    volatile.Register32 // 0x14
	FDCAN_CCCR   volatile.Register32 // 0x18
	FDCAN_NBTP   volatile.Register32 // 0x1C
	FDCAN_TSCC   volatile.Register32 // 0x20
	FDCAN_TSCV   volatile.Register32 // 0x24
	FDCAN_TOCC   volatile.Register32 // 0x28
	FDCAN_TOCV   volatile.Register32 // 0x2C
	_            [16]byte
	FDCAN_ECR    volatile.Register32 // 0x40
	FDCAN_PSR    volatile.Register32 // 0x44
	FDCAN_TDCR   volatile.Register32 // 0x48
	_            [4]byte
	FDCAN_IR     volatile.Register32 // 0x50
	FDCAN_IE     volatile.Register32 // 0x54
	FDCAN_ILS    volatile.Register32 // 0x58
	FDCAN_ILE    volatile.Register32 // 0x5C
	_            [32]byte
	FDCAN_GFC    volatile.Register32 // 0x80
	FDCAN_SIDFC  volatile.Register32 // 0x84
	FDCAN_XIDFC  volatile.Register32 // 0x88
	_            [4]byte
	FDCAN_XIDAM  volatile.Register32 // 0x90
	FDCAN_HPMS   volatile.Register32 // 0x94
	FDCAN_NDAT1  volatile.Register32 // 0x98
	FDCAN_NDAT2  volatile.Register32 // 0x9C
	FDCAN_RXF0C  volatile.Register32 // 0xA0
	FDCAN_RXF0S  volatile.Register32 // 0xA4
	FDCAN_RXF0A  volatile.Register32 // 0xA8
	FDCAN_RXBC   volatile.Register32 // 0xAC
	FDCAN_RXF1C  volatile.Register32 // 0xB0
	FDCAN_RXF1S  volatile.Register32 // 0xB4
	FDCAN_RXF1A  volatile.Register32 // 0xB8
	FDCAN_RXESC  volatile.Register32 // 0xBC
	FDCAN_TXBC   volatile.Register32 // 0xC0
	FDCAN_TXFQS  volatile.Register32 // 0xC4
	FDCAN_TXESC  volatile.Register32 // 0xC8
	_            [4]byte
	FDCAN_TXBAR  volatile.Register32 // 0xD0
	FDCAN_TXBCR  volatile.Register32 // 0xD4
	FDCAN_TXBTO  volatile.Register32 // 0xD8
	FDCAN_TXBCF  volatile.Register32 // 0xDC
	FDCAN_TXBTIE volatile.Register32 // 0xE0
	FDCAN_TXBCIE volatile.Register32 // 0xE4
	_            [8]byte
	FDCAN_TXEFC  volatile.Register32 // 0xF0
	FDCAN_TXEFS  volatile.Register32 // 0xF4
	FDCAN_TXEFA  volatile.Register32 // 0xF8
	_            [4]byte
	FDCAN_TTTMC  volatile.Register32 // 0x100
	FDCAN_TTRMC  volatile.Register32 // 0x104
	FDCAN_TTOCF  volatile.Register32 // 0x108
	FDCAN_TTMLM  volatile.Register32 // 0x10C
	FDCAN_TURCF  volatile.Register32 // 0x110
	FDCAN_TTOCN  volatile.Register32 // 0x114
	FDCAN_TTGTP  volatile.Register32 // 0x118
	FDCAN_TTTMK  volatile.Register32 // 0x11C
	FDCAN_TTIR   volatile.Register32 // 0x120
	FDCAN_TTIE   volatile.Register32 // 0x124
	FDCAN_TTILS  volatile.Register32 // 0x128
	FDCAN_TTOST  volatile.Register32 // 0x12C
	FDCAN_TURNA  volatile.Register32 // 0x130
	FDCAN_TTLGT  volatile.Register32 // 0x134
	FDCAN_TTCTC  volatile.Register32 // 0x138
	FDCAN_TTCPT  volatile.Register32 // 0x13C
	FDCAN_TTCSM  volatile.Register32 // 0x140
	_            [444]byte
	FDCAN_TTTS   volatile.Register32 // 0x300
}

// FMC register block
type FMC_Type struct {
	FMC_BCR1     volatile.Register32 // 0x0
	FMC_BTR1     volatile.Register32 // 0x4
	FMC_BCR2     volatile.Register32 // 0x8
	FMC_BTR2     volatile.Register32 // 0xC
	FMC_BCR3     volatile.Register32 // 0x10
	FMC_BTR3     volatile.Register32 // 0x14
	FMC_BCR4     volatile.Register32 // 0x18
	FMC_BTR4     volatile.Register32 // 0x1C
	FMC_PCSCNTR  volatile.Register32 // 0x20
	_            [92]byte
	FMC_PCR      volatile.Register32 // 0x80
	FMC_SR       volatile.Register32 // 0x84
	FMC_PMEM     volatile.Register32 // 0x88
	FMC_PATT     volatile.Register32 // 0x8C
	FMC_HPR      volatile.Register32 // 0x90
	FMC_HECCR    volatile.Register32 // 0x94
	_            [108]byte
	FMC_BWTR1    volatile.Register32 // 0x104
	_            [4]byte
	FMC_BWTR2    volatile.Register32 // 0x10C
	_            [4]byte
	FMC_BWTR3    volatile.Register32 // 0x114
	_            [4]byte
	FMC_BWTR4    volatile.Register32 // 0x11C
	_            [224]byte
	FMC_CSQCR    volatile.Register32 // 0x200
	FMC_CSQCFGR1 volatile.Register32 // 0x204
	FMC_CSQCFGR2 volatile.Register32 // 0x208
	FMC_CSQCFGR3 volatile.Register32 // 0x20C
	FMC_CSQAR1   volatile.Register32 // 0x210
	FMC_CSQAR2   volatile.Register32 // 0x214
	_            [8]byte
	FMC_CSQIER   volatile.Register32 // 0x220
	FMC_CSQISR   volatile.Register32 // 0x224
	FMC_CSQICR   volatile.Register32 // 0x228
	_            [4]byte
	FMC_CSQEMSR  volatile.Register32 // 0x230
	_            [28]byte
	FMC_BCHIER   volatile.Register32 // 0x250
	FMC_BCHISR   volatile.Register32 // 0x254
	FMC_BCHICR   volatile.Register32 // 0x258
	_            [4]byte
	FMC_BCHPBR1  volatile.Register32 // 0x260
	FMC_BCHPBR2  volatile.Register32 // 0x264
	FMC_BCHPBR3  volatile.Register32 // 0x268
	FMC_BCHPBR4  volatile.Register32 // 0x26C
	_            [12]byte
	FMC_BCHDSR0  volatile.Register32 // 0x27C
	FMC_BCHDSR1  volatile.Register32 // 0x280
	FMC_BCHDSR2  volatile.Register32 // 0x284
	FMC_BCHDSR3  volatile.Register32 // 0x288
	FMC_BCHDSR4  volatile.Register32 // 0x28C
	_            [348]byte
	FMC_HWCFGR2  volatile.Register32 // 0x3EC
	FMC_HWCFGR1  volatile.Register32 // 0x3F0
	FMC_VERR     volatile.Register32 // 0x3F4
	FMC_IPIDR    volatile.Register32 // 0x3F8
	FMC_SIDR     volatile.Register32 // 0x3FC
}

// GICC
type GICC_Type struct {
	GICC_CTLR   volatile.Register32 // 0x0
	GICC_PMR    volatile.Register32 // 0x4
	GICC_BPR    volatile.Register32 // 0x8
	GICC_IAR    volatile.Register32 // 0xC
	GICC_EOIR   volatile.Register32 // 0x10
	GICC_RPR    volatile.Register32 // 0x14
	GICC_HPPIR  volatile.Register32 // 0x18
	GICC_ABPR   volatile.Register32 // 0x1C
	GICC_AIAR   volatile.Register32 // 0x20
	GICC_AEOIR  volatile.Register32 // 0x24
	GICC_AHPPIR volatile.Register32 // 0x28
	_           [164]byte
	GICC_APR0   volatile.Register32 // 0xD0
	_           [12]byte
	GICC_NSAPR0 volatile.Register32 // 0xE0
	_           [24]byte
	GICC_IIDR   volatile.Register32 // 0xFC
	_           [3840]byte
	GICC_DIR    volatile.Register32 // 0x1000
}

// GICD
type GICD_Type struct {
	GICD_CTLR         volatile.Register32 // 0x0
	GICD_TYPER        volatile.Register32 // 0x4
	GICD_IIDR         volatile.Register32 // 0x8
	_                 [116]byte
	GICD_IGROUPR0     volatile.Register32 // 0x80
	GICD_IGROUPR1     volatile.Register32 // 0x84
	GICD_IGROUPR2     volatile.Register32 // 0x88
	GICD_IGROUPR3     volatile.Register32 // 0x8C
	GICD_IGROUPR4     volatile.Register32 // 0x90
	GICD_IGROUPR5     volatile.Register32 // 0x94
	GICD_IGROUPR6     volatile.Register32 // 0x98
	GICD_IGROUPR7     volatile.Register32 // 0x9C
	GICD_IGROUPR8     volatile.Register32 // 0xA0
	_                 [92]byte
	GICD_ISENABLER0   volatile.Register32 // 0x100
	GICD_ISENABLER1   volatile.Register32 // 0x104
	GICD_ISENABLER2   volatile.Register32 // 0x108
	GICD_ISENABLER3   volatile.Register32 // 0x10C
	GICD_ISENABLER4   volatile.Register32 // 0x110
	GICD_ISENABLER5   volatile.Register32 // 0x114
	GICD_ISENABLER6   volatile.Register32 // 0x118
	GICD_ISENABLER7   volatile.Register32 // 0x11C
	GICD_ISENABLER8   volatile.Register32 // 0x120
	_                 [92]byte
	GICD_ICENABLER0   volatile.Register32 // 0x180
	GICD_ICENABLER1   volatile.Register32 // 0x184
	GICD_ICENABLER2   volatile.Register32 // 0x188
	GICD_ICENABLER3   volatile.Register32 // 0x18C
	GICD_ICENABLER4   volatile.Register32 // 0x190
	GICD_ICENABLER5   volatile.Register32 // 0x194
	GICD_ICENABLER6   volatile.Register32 // 0x198
	GICD_ICENABLER7   volatile.Register32 // 0x19C
	GICD_ICENABLER8   volatile.Register32 // 0x1A0
	_                 [92]byte
	GICD_ISPENDR0     volatile.Register32 // 0x200
	GICD_ISPENDR1     volatile.Register32 // 0x204
	GICD_ISPENDR2     volatile.Register32 // 0x208
	GICD_ISPENDR3     volatile.Register32 // 0x20C
	GICD_ISPENDR4     volatile.Register32 // 0x210
	GICD_ISPENDR5     volatile.Register32 // 0x214
	GICD_ISPENDR6     volatile.Register32 // 0x218
	GICD_ISPENDR7     volatile.Register32 // 0x21C
	GICD_ISPENDR8     volatile.Register32 // 0x220
	_                 [92]byte
	GICD_ICPENDR0     volatile.Register32 // 0x280
	GICD_ICPENDR1     volatile.Register32 // 0x284
	GICD_ICPENDR2     volatile.Register32 // 0x288
	GICD_ICPENDR3     volatile.Register32 // 0x28C
	GICD_ICPENDR4     volatile.Register32 // 0x290
	GICD_ICPENDR5     volatile.Register32 // 0x294
	GICD_ICPENDR6     volatile.Register32 // 0x298
	GICD_ICPENDR7     volatile.Register32 // 0x29C
	GICD_ICPENDR8     volatile.Register32 // 0x2A0
	_                 [92]byte
	GICD_ISACTIVER0   volatile.Register32 // 0x300
	GICD_ISACTIVER1   volatile.Register32 // 0x304
	GICD_ISACTIVER2   volatile.Register32 // 0x308
	GICD_ISACTIVER3   volatile.Register32 // 0x30C
	GICD_ISACTIVER4   volatile.Register32 // 0x310
	GICD_ISACTIVER5   volatile.Register32 // 0x314
	GICD_ISACTIVER6   volatile.Register32 // 0x318
	GICD_ISACTIVER7   volatile.Register32 // 0x31C
	GICD_ISACTIVER8   volatile.Register32 // 0x320
	_                 [92]byte
	GICD_ICACTIVER0   volatile.Register32 // 0x380
	GICD_ICACTIVER1   volatile.Register32 // 0x384
	GICD_ICACTIVER2   volatile.Register32 // 0x388
	GICD_ICACTIVER3   volatile.Register32 // 0x38C
	GICD_ICACTIVER4   volatile.Register32 // 0x390
	GICD_ICACTIVER5   volatile.Register32 // 0x394
	GICD_ICACTIVER6   volatile.Register32 // 0x398
	GICD_ICACTIVER7   volatile.Register32 // 0x39C
	GICD_ICACTIVER8   volatile.Register32 // 0x3A0
	_                 [92]byte
	GICD_IPRIORITYR0  volatile.Register32 // 0x400
	GICD_IPRIORITYR1  volatile.Register32 // 0x404
	GICD_IPRIORITYR2  volatile.Register32 // 0x408
	GICD_IPRIORITYR3  volatile.Register32 // 0x40C
	GICD_IPRIORITYR4  volatile.Register32 // 0x410
	GICD_IPRIORITYR5  volatile.Register32 // 0x414
	GICD_IPRIORITYR6  volatile.Register32 // 0x418
	GICD_IPRIORITYR7  volatile.Register32 // 0x41C
	GICD_IPRIORITYR8  volatile.Register32 // 0x420
	GICD_IPRIORITYR9  volatile.Register32 // 0x424
	GICD_IPRIORITYR10 volatile.Register32 // 0x428
	GICD_IPRIORITYR11 volatile.Register32 // 0x42C
	GICD_IPRIORITYR12 volatile.Register32 // 0x430
	GICD_IPRIORITYR13 volatile.Register32 // 0x434
	GICD_IPRIORITYR14 volatile.Register32 // 0x438
	GICD_IPRIORITYR15 volatile.Register32 // 0x43C
	GICD_IPRIORITYR16 volatile.Register32 // 0x440
	GICD_IPRIORITYR17 volatile.Register32 // 0x444
	GICD_IPRIORITYR18 volatile.Register32 // 0x448
	GICD_IPRIORITYR19 volatile.Register32 // 0x44C
	GICD_IPRIORITYR20 volatile.Register32 // 0x450
	GICD_IPRIORITYR21 volatile.Register32 // 0x454
	GICD_IPRIORITYR22 volatile.Register32 // 0x458
	GICD_IPRIORITYR23 volatile.Register32 // 0x45C
	GICD_IPRIORITYR24 volatile.Register32 // 0x460
	GICD_IPRIORITYR25 volatile.Register32 // 0x464
	GICD_IPRIORITYR26 volatile.Register32 // 0x468
	GICD_IPRIORITYR27 volatile.Register32 // 0x46C
	GICD_IPRIORITYR28 volatile.Register32 // 0x470
	GICD_IPRIORITYR29 volatile.Register32 // 0x474
	GICD_IPRIORITYR30 volatile.Register32 // 0x478
	GICD_IPRIORITYR31 volatile.Register32 // 0x47C
	GICD_IPRIORITYR32 volatile.Register32 // 0x480
	GICD_IPRIORITYR33 volatile.Register32 // 0x484
	GICD_IPRIORITYR34 volatile.Register32 // 0x488
	GICD_IPRIORITYR35 volatile.Register32 // 0x48C
	GICD_IPRIORITYR36 volatile.Register32 // 0x490
	GICD_IPRIORITYR37 volatile.Register32 // 0x494
	GICD_IPRIORITYR38 volatile.Register32 // 0x498
	GICD_IPRIORITYR39 volatile.Register32 // 0x49C
	GICD_IPRIORITYR40 volatile.Register32 // 0x4A0
	GICD_IPRIORITYR41 volatile.Register32 // 0x4A4
	GICD_IPRIORITYR42 volatile.Register32 // 0x4A8
	GICD_IPRIORITYR43 volatile.Register32 // 0x4AC
	GICD_IPRIORITYR44 volatile.Register32 // 0x4B0
	GICD_IPRIORITYR45 volatile.Register32 // 0x4B4
	GICD_IPRIORITYR46 volatile.Register32 // 0x4B8
	GICD_IPRIORITYR47 volatile.Register32 // 0x4BC
	GICD_IPRIORITYR48 volatile.Register32 // 0x4C0
	GICD_IPRIORITYR49 volatile.Register32 // 0x4C4
	GICD_IPRIORITYR50 volatile.Register32 // 0x4C8
	GICD_IPRIORITYR51 volatile.Register32 // 0x4CC
	GICD_IPRIORITYR52 volatile.Register32 // 0x4D0
	GICD_IPRIORITYR53 volatile.Register32 // 0x4D4
	GICD_IPRIORITYR54 volatile.Register32 // 0x4D8
	GICD_IPRIORITYR55 volatile.Register32 // 0x4DC
	GICD_IPRIORITYR56 volatile.Register32 // 0x4E0
	GICD_IPRIORITYR57 volatile.Register32 // 0x4E4
	GICD_IPRIORITYR58 volatile.Register32 // 0x4E8
	GICD_IPRIORITYR59 volatile.Register32 // 0x4EC
	GICD_IPRIORITYR60 volatile.Register32 // 0x4F0
	GICD_IPRIORITYR61 volatile.Register32 // 0x4F4
	GICD_IPRIORITYR62 volatile.Register32 // 0x4F8
	GICD_IPRIORITYR63 volatile.Register32 // 0x4FC
	GICD_IPRIORITYR64 volatile.Register32 // 0x500
	GICD_IPRIORITYR65 volatile.Register32 // 0x504
	GICD_IPRIORITYR66 volatile.Register32 // 0x508
	GICD_IPRIORITYR67 volatile.Register32 // 0x50C
	GICD_IPRIORITYR68 volatile.Register32 // 0x510
	GICD_IPRIORITYR69 volatile.Register32 // 0x514
	GICD_IPRIORITYR70 volatile.Register32 // 0x518
	GICD_IPRIORITYR71 volatile.Register32 // 0x51C
	_                 [736]byte
	GICD_ITARGETSR0   volatile.Register32 // 0x800
	GICD_ITARGETSR1   volatile.Register32 // 0x804
	GICD_ITARGETSR2   volatile.Register32 // 0x808
	GICD_ITARGETSR3   volatile.Register32 // 0x80C
	GICD_ITARGETSR4   volatile.Register32 // 0x810
	GICD_ITARGETSR5   volatile.Register32 // 0x814
	GICD_ITARGETSR6   volatile.Register32 // 0x818
	GICD_ITARGETSR7   volatile.Register32 // 0x81C
	GICD_ITARGETSR8   volatile.Register32 // 0x820
	GICD_ITARGETSR9   volatile.Register32 // 0x824
	GICD_ITARGETSR10  volatile.Register32 // 0x828
	GICD_ITARGETSR11  volatile.Register32 // 0x82C
	GICD_ITARGETSR12  volatile.Register32 // 0x830
	GICD_ITARGETSR13  volatile.Register32 // 0x834
	GICD_ITARGETSR14  volatile.Register32 // 0x838
	GICD_ITARGETSR15  volatile.Register32 // 0x83C
	GICD_ITARGETSR16  volatile.Register32 // 0x840
	GICD_ITARGETSR17  volatile.Register32 // 0x844
	GICD_ITARGETSR18  volatile.Register32 // 0x848
	GICD_ITARGETSR19  volatile.Register32 // 0x84C
	GICD_ITARGETSR20  volatile.Register32 // 0x850
	GICD_ITARGETSR21  volatile.Register32 // 0x854
	GICD_ITARGETSR22  volatile.Register32 // 0x858
	GICD_ITARGETSR23  volatile.Register32 // 0x85C
	GICD_ITARGETSR24  volatile.Register32 // 0x860
	GICD_ITARGETSR25  volatile.Register32 // 0x864
	GICD_ITARGETSR26  volatile.Register32 // 0x868
	GICD_ITARGETSR27  volatile.Register32 // 0x86C
	GICD_ITARGETSR28  volatile.Register32 // 0x870
	GICD_ITARGETSR29  volatile.Register32 // 0x874
	GICD_ITARGETSR30  volatile.Register32 // 0x878
	GICD_ITARGETSR31  volatile.Register32 // 0x87C
	GICD_ITARGETSR32  volatile.Register32 // 0x880
	GICD_ITARGETSR33  volatile.Register32 // 0x884
	GICD_ITARGETSR34  volatile.Register32 // 0x888
	GICD_ITARGETSR35  volatile.Register32 // 0x88C
	GICD_ITARGETSR36  volatile.Register32 // 0x890
	GICD_ITARGETSR37  volatile.Register32 // 0x894
	GICD_ITARGETSR38  volatile.Register32 // 0x898
	GICD_ITARGETSR39  volatile.Register32 // 0x89C
	GICD_ITARGETSR40  volatile.Register32 // 0x8A0
	GICD_ITARGETSR41  volatile.Register32 // 0x8A4
	GICD_ITARGETSR42  volatile.Register32 // 0x8A8
	GICD_ITARGETSR43  volatile.Register32 // 0x8AC
	GICD_ITARGETSR44  volatile.Register32 // 0x8B0
	GICD_ITARGETSR45  volatile.Register32 // 0x8B4
	GICD_ITARGETSR46  volatile.Register32 // 0x8B8
	GICD_ITARGETSR47  volatile.Register32 // 0x8BC
	GICD_ITARGETSR48  volatile.Register32 // 0x8C0
	GICD_ITARGETSR49  volatile.Register32 // 0x8C4
	GICD_ITARGETSR50  volatile.Register32 // 0x8C8
	GICD_ITARGETSR51  volatile.Register32 // 0x8CC
	GICD_ITARGETSR52  volatile.Register32 // 0x8D0
	GICD_ITARGETSR53  volatile.Register32 // 0x8D4
	GICD_ITARGETSR54  volatile.Register32 // 0x8D8
	GICD_ITARGETSR55  volatile.Register32 // 0x8DC
	GICD_ITARGETSR56  volatile.Register32 // 0x8E0
	GICD_ITARGETSR57  volatile.Register32 // 0x8E4
	GICD_ITARGETSR58  volatile.Register32 // 0x8E8
	GICD_ITARGETSR59  volatile.Register32 // 0x8EC
	GICD_ITARGETSR60  volatile.Register32 // 0x8F0
	GICD_ITARGETSR61  volatile.Register32 // 0x8F4
	GICD_ITARGETSR62  volatile.Register32 // 0x8F8
	GICD_ITARGETSR63  volatile.Register32 // 0x8FC
	GICD_ITARGETSR64  volatile.Register32 // 0x900
	GICD_ITARGETSR65  volatile.Register32 // 0x904
	GICD_ITARGETSR66  volatile.Register32 // 0x908
	GICD_ITARGETSR67  volatile.Register32 // 0x90C
	GICD_ITARGETSR68  volatile.Register32 // 0x910
	GICD_ITARGETSR69  volatile.Register32 // 0x914
	GICD_ITARGETSR70  volatile.Register32 // 0x918
	GICD_ITARGETSR71  volatile.Register32 // 0x91C
	_                 [736]byte
	GICD_ICFGR0       volatile.Register32 // 0xC00
	GICD_ICFGR1       volatile.Register32 // 0xC04
	GICD_ICFGR2       volatile.Register32 // 0xC08
	GICD_ICFGR3       volatile.Register32 // 0xC0C
	GICD_ICFGR4       volatile.Register32 // 0xC10
	GICD_ICFGR5       volatile.Register32 // 0xC14
	GICD_ICFGR6       volatile.Register32 // 0xC18
	GICD_ICFGR7       volatile.Register32 // 0xC1C
	GICD_ICFGR8       volatile.Register32 // 0xC20
	GICD_ICFGR9       volatile.Register32 // 0xC24
	GICD_ICFGR10      volatile.Register32 // 0xC28
	GICD_ICFGR11      volatile.Register32 // 0xC2C
	GICD_ICFGR12      volatile.Register32 // 0xC30
	GICD_ICFGR13      volatile.Register32 // 0xC34
	GICD_ICFGR14      volatile.Register32 // 0xC38
	GICD_ICFGR15      volatile.Register32 // 0xC3C
	GICD_ICFGR16      volatile.Register32 // 0xC40
	GICD_ICFGR17      volatile.Register32 // 0xC44
	_                 [184]byte
	GICD_PPISR        volatile.Register32 // 0xD00
	_                 [4]byte
	GICD_SPISR1       volatile.Register32 // 0xD08
	GICD_SPISR2       volatile.Register32 // 0xD0C
	GICD_SPISR3       volatile.Register32 // 0xD10
	GICD_SPISR4       volatile.Register32 // 0xD14
	GICD_SPISR5       volatile.Register32 // 0xD18
	GICD_SPISR6       volatile.Register32 // 0xD1C
	GICD_SPISR7       volatile.Register32 // 0xD20
	_                 [476]byte
	GICD_SGIR         volatile.Register32 // 0xF00
	_                 [12]byte
	GICD_CPENDSGIR0   volatile.Register32 // 0xF10
	GICD_CPENDSGIR1   volatile.Register32 // 0xF14
	GICD_CPENDSGIR2   volatile.Register32 // 0xF18
	GICD_CPENDSGIR3   volatile.Register32 // 0xF1C
	GICD_SPENDSGIR0   volatile.Register32 // 0xF20
	GICD_SPENDSGIR1   volatile.Register32 // 0xF24
	GICD_SPENDSGIR2   volatile.Register32 // 0xF28
	GICD_SPENDSGIR3   volatile.Register32 // 0xF2C
	_                 [160]byte
	GICD_PIDR4        volatile.Register32 // 0xFD0
	GICD_PIDR5        volatile.Register32 // 0xFD4
	GICD_PIDR6        volatile.Register32 // 0xFD8
	GICD_PIDR7        volatile.Register32 // 0xFDC
	GICD_PIDR0        volatile.Register32 // 0xFE0
	GICD_PIDR1        volatile.Register32 // 0xFE4
	GICD_PIDR2        volatile.Register32 // 0xFE8
	GICD_PIDR3        volatile.Register32 // 0xFEC
	GICD_CIDR0        volatile.Register32 // 0xFF0
	GICD_CIDR1        volatile.Register32 // 0xFF4
	GICD_CIDR2        volatile.Register32 // 0xFF8
	GICD_CIDR3        volatile.Register32 // 0xFFC
}

// GICH
type GICH_Type struct {
	GICH_HCR   volatile.Register32 // 0x0
	GICH_VTR   volatile.Register32 // 0x4
	GICH_VMCR  volatile.Register32 // 0x8
	_          [4]byte
	GICH_MISR  volatile.Register32 // 0x10
	_          [12]byte
	GICH_EISR0 volatile.Register32 // 0x20
	_          [12]byte
	GICH_ELSR0 volatile.Register32 // 0x30
	_          [188]byte
	GICH_APR0  volatile.Register32 // 0xF0
	_          [12]byte
	GICH_LR0   volatile.Register32 // 0x100
	GICH_LR1   volatile.Register32 // 0x104
	GICH_LR2   volatile.Register32 // 0x108
	GICH_LR3   volatile.Register32 // 0x10C
}

// GICV
type GICV_Type struct {
	GICV_CTLR   volatile.Register32 // 0x0
	GICV_PMR    volatile.Register32 // 0x4
	GICV_BPR    volatile.Register32 // 0x8
	GICV_IAR    volatile.Register32 // 0xC
	GICV_EOIR   volatile.Register32 // 0x10
	GICV_RPR    volatile.Register32 // 0x14
	GICV_HPPIR  volatile.Register32 // 0x18
	GICV_ABPR   volatile.Register32 // 0x1C
	GICV_AIAR   volatile.Register32 // 0x20
	GICV_AEOIR  volatile.Register32 // 0x24
	GICV_AHPPIR volatile.Register32 // 0x28
	_           [164]byte
	GICV_APR0   volatile.Register32 // 0xD0
	_           [40]byte
	GICV_IIDR   volatile.Register32 // 0xFC
	_           [3840]byte
	GICV_DIR    volatile.Register32 // 0x1000
}

// GPIOA
type GPIOA_Type struct {
	GPIOA_MODER    volatile.Register32 // 0x0
	GPIOA_OTYPER   volatile.Register32 // 0x4
	GPIOA_OSPEEDR  volatile.Register32 // 0x8
	GPIOA_PUPDR    volatile.Register32 // 0xC
	GPIOA_IDR      volatile.Register32 // 0x10
	GPIOA_ODR      volatile.Register32 // 0x14
	GPIOA_BSRR     volatile.Register32 // 0x18
	GPIOA_LCKR     volatile.Register32 // 0x1C
	GPIOA_AFRL     volatile.Register32 // 0x20
	GPIOA_AFRH     volatile.Register32 // 0x24
	GPIOA_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOA_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOA_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOA_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOA_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOA_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOA_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOA_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOA_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOA_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOA_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOA_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOA_VERR     volatile.Register32 // 0x3F4
	GPIOA_IPIDR    volatile.Register32 // 0x3F8
	GPIOA_SIDR     volatile.Register32 // 0x3FC
}

// GPIOB
type GPIOB_Type struct {
	GPIOB_MODER    volatile.Register32 // 0x0
	GPIOB_OTYPER   volatile.Register32 // 0x4
	GPIOB_OSPEEDR  volatile.Register32 // 0x8
	GPIOB_PUPDR    volatile.Register32 // 0xC
	GPIOB_IDR      volatile.Register32 // 0x10
	GPIOB_ODR      volatile.Register32 // 0x14
	GPIOB_BSRR     volatile.Register32 // 0x18
	GPIOB_LCKR     volatile.Register32 // 0x1C
	GPIOB_AFRL     volatile.Register32 // 0x20
	GPIOB_AFRH     volatile.Register32 // 0x24
	GPIOB_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOB_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOB_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOB_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOB_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOB_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOB_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOB_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOB_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOB_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOB_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOB_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOB_VERR     volatile.Register32 // 0x3F4
	GPIOB_IPIDR    volatile.Register32 // 0x3F8
	GPIOB_SIDR     volatile.Register32 // 0x3FC
}

// GPIOC
type GPIOC_Type struct {
	GPIOC_MODER    volatile.Register32 // 0x0
	GPIOC_OTYPER   volatile.Register32 // 0x4
	GPIOC_OSPEEDR  volatile.Register32 // 0x8
	GPIOC_PUPDR    volatile.Register32 // 0xC
	GPIOC_IDR      volatile.Register32 // 0x10
	GPIOC_ODR      volatile.Register32 // 0x14
	GPIOC_BSRR     volatile.Register32 // 0x18
	GPIOC_LCKR     volatile.Register32 // 0x1C
	GPIOC_AFRL     volatile.Register32 // 0x20
	GPIOC_AFRH     volatile.Register32 // 0x24
	GPIOC_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOC_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOC_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOC_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOC_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOC_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOC_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOC_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOC_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOC_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOC_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOC_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOC_VERR     volatile.Register32 // 0x3F4
	GPIOC_IPIDR    volatile.Register32 // 0x3F8
	GPIOC_SIDR     volatile.Register32 // 0x3FC
}

// GPIOD
type GPIOD_Type struct {
	GPIOD_MODER    volatile.Register32 // 0x0
	GPIOD_OTYPER   volatile.Register32 // 0x4
	GPIOD_OSPEEDR  volatile.Register32 // 0x8
	GPIOD_PUPDR    volatile.Register32 // 0xC
	GPIOD_IDR      volatile.Register32 // 0x10
	GPIOD_ODR      volatile.Register32 // 0x14
	GPIOD_BSRR     volatile.Register32 // 0x18
	GPIOD_LCKR     volatile.Register32 // 0x1C
	GPIOD_AFRL     volatile.Register32 // 0x20
	GPIOD_AFRH     volatile.Register32 // 0x24
	GPIOD_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOD_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOD_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOD_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOD_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOD_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOD_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOD_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOD_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOD_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOD_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOD_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOD_VERR     volatile.Register32 // 0x3F4
	GPIOD_IPIDR    volatile.Register32 // 0x3F8
	GPIOD_SIDR     volatile.Register32 // 0x3FC
}

// GPIOE
type GPIOE_Type struct {
	GPIOE_MODER    volatile.Register32 // 0x0
	GPIOE_OTYPER   volatile.Register32 // 0x4
	GPIOE_OSPEEDR  volatile.Register32 // 0x8
	GPIOE_PUPDR    volatile.Register32 // 0xC
	GPIOE_IDR      volatile.Register32 // 0x10
	GPIOE_ODR      volatile.Register32 // 0x14
	GPIOE_BSRR     volatile.Register32 // 0x18
	GPIOE_LCKR     volatile.Register32 // 0x1C
	GPIOE_AFRL     volatile.Register32 // 0x20
	GPIOE_AFRH     volatile.Register32 // 0x24
	GPIOE_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOE_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOE_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOE_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOE_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOE_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOE_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOE_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOE_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOE_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOE_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOE_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOE_VERR     volatile.Register32 // 0x3F4
	GPIOE_IPIDR    volatile.Register32 // 0x3F8
	GPIOE_SIDR     volatile.Register32 // 0x3FC
}

// GPIOF
type GPIOF_Type struct {
	GPIOF_MODER    volatile.Register32 // 0x0
	GPIOF_OTYPER   volatile.Register32 // 0x4
	GPIOF_OSPEEDR  volatile.Register32 // 0x8
	GPIOF_PUPDR    volatile.Register32 // 0xC
	GPIOF_IDR      volatile.Register32 // 0x10
	GPIOF_ODR      volatile.Register32 // 0x14
	GPIOF_BSRR     volatile.Register32 // 0x18
	GPIOF_LCKR     volatile.Register32 // 0x1C
	GPIOF_AFRL     volatile.Register32 // 0x20
	GPIOF_AFRH     volatile.Register32 // 0x24
	GPIOF_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOF_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOF_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOF_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOF_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOF_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOF_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOF_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOF_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOF_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOF_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOF_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOF_VERR     volatile.Register32 // 0x3F4
	GPIOF_IPIDR    volatile.Register32 // 0x3F8
	GPIOF_SIDR     volatile.Register32 // 0x3FC
}

// GPIOG
type GPIOG_Type struct {
	GPIOG_MODER    volatile.Register32 // 0x0
	GPIOG_OTYPER   volatile.Register32 // 0x4
	GPIOG_OSPEEDR  volatile.Register32 // 0x8
	GPIOG_PUPDR    volatile.Register32 // 0xC
	GPIOG_IDR      volatile.Register32 // 0x10
	GPIOG_ODR      volatile.Register32 // 0x14
	GPIOG_BSRR     volatile.Register32 // 0x18
	GPIOG_LCKR     volatile.Register32 // 0x1C
	GPIOG_AFRL     volatile.Register32 // 0x20
	GPIOG_AFRH     volatile.Register32 // 0x24
	GPIOG_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOG_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOG_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOG_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOG_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOG_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOG_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOG_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOG_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOG_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOG_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOG_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOG_VERR     volatile.Register32 // 0x3F4
	GPIOG_IPIDR    volatile.Register32 // 0x3F8
	GPIOG_SIDR     volatile.Register32 // 0x3FC
}

// GPIOH
type GPIOH_Type struct {
	GPIOH_MODER    volatile.Register32 // 0x0
	GPIOH_OTYPER   volatile.Register32 // 0x4
	GPIOH_OSPEEDR  volatile.Register32 // 0x8
	GPIOH_PUPDR    volatile.Register32 // 0xC
	GPIOH_IDR      volatile.Register32 // 0x10
	GPIOH_ODR      volatile.Register32 // 0x14
	GPIOH_BSRR     volatile.Register32 // 0x18
	GPIOH_LCKR     volatile.Register32 // 0x1C
	GPIOH_AFRL     volatile.Register32 // 0x20
	GPIOH_AFRH     volatile.Register32 // 0x24
	GPIOH_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOH_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOH_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOH_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOH_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOH_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOH_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOH_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOH_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOH_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOH_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOH_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOH_VERR     volatile.Register32 // 0x3F4
	GPIOH_IPIDR    volatile.Register32 // 0x3F8
	GPIOH_SIDR     volatile.Register32 // 0x3FC
}

// GPIOI
type GPIOI_Type struct {
	GPIOI_MODER    volatile.Register32 // 0x0
	GPIOI_OTYPER   volatile.Register32 // 0x4
	GPIOI_OSPEEDR  volatile.Register32 // 0x8
	GPIOI_PUPDR    volatile.Register32 // 0xC
	GPIOI_IDR      volatile.Register32 // 0x10
	GPIOI_ODR      volatile.Register32 // 0x14
	GPIOI_BSRR     volatile.Register32 // 0x18
	GPIOI_LCKR     volatile.Register32 // 0x1C
	GPIOI_AFRL     volatile.Register32 // 0x20
	GPIOI_AFRH     volatile.Register32 // 0x24
	GPIOI_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOI_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOI_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOI_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOI_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOI_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOI_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOI_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOI_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOI_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOI_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOI_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOI_VERR     volatile.Register32 // 0x3F4
	GPIOI_IPIDR    volatile.Register32 // 0x3F8
	GPIOI_SIDR     volatile.Register32 // 0x3FC
}

// GPIOJ
type GPIOJ_Type struct {
	GPIOJ_MODER    volatile.Register32 // 0x0
	GPIOJ_OTYPER   volatile.Register32 // 0x4
	GPIOJ_OSPEEDR  volatile.Register32 // 0x8
	GPIOJ_PUPDR    volatile.Register32 // 0xC
	GPIOJ_IDR      volatile.Register32 // 0x10
	GPIOJ_ODR      volatile.Register32 // 0x14
	GPIOJ_BSRR     volatile.Register32 // 0x18
	GPIOJ_LCKR     volatile.Register32 // 0x1C
	GPIOJ_AFRL     volatile.Register32 // 0x20
	GPIOJ_AFRH     volatile.Register32 // 0x24
	GPIOJ_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOJ_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOJ_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOJ_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOJ_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOJ_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOJ_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOJ_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOJ_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOJ_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOJ_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOJ_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOJ_VERR     volatile.Register32 // 0x3F4
	GPIOJ_IPIDR    volatile.Register32 // 0x3F8
	GPIOJ_SIDR     volatile.Register32 // 0x3FC
}

// GPIOK
type GPIOK_Type struct {
	GPIOK_MODER    volatile.Register32 // 0x0
	GPIOK_OTYPER   volatile.Register32 // 0x4
	GPIOK_OSPEEDR  volatile.Register32 // 0x8
	GPIOK_PUPDR    volatile.Register32 // 0xC
	GPIOK_IDR      volatile.Register32 // 0x10
	GPIOK_ODR      volatile.Register32 // 0x14
	GPIOK_BSRR     volatile.Register32 // 0x18
	GPIOK_LCKR     volatile.Register32 // 0x1C
	GPIOK_AFRL     volatile.Register32 // 0x20
	GPIOK_AFRH     volatile.Register32 // 0x24
	GPIOK_BRR      volatile.Register32 // 0x28
	_              [924]byte
	GPIOK_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOK_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOK_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOK_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOK_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOK_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOK_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOK_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOK_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOK_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOK_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOK_VERR     volatile.Register32 // 0x3F4
	GPIOK_IPIDR    volatile.Register32 // 0x3F8
	GPIOK_SIDR     volatile.Register32 // 0x3FC
}

// GPIOZ
type GPIOZ_Type struct {
	GPIOZ_MODER    volatile.Register32 // 0x0
	GPIOZ_OTYPER   volatile.Register32 // 0x4
	GPIOZ_OSPEEDR  volatile.Register32 // 0x8
	GPIOZ_PUPDR    volatile.Register32 // 0xC
	GPIOZ_IDR      volatile.Register32 // 0x10
	GPIOZ_ODR      volatile.Register32 // 0x14
	GPIOZ_BSRR     volatile.Register32 // 0x18
	GPIOZ_LCKR     volatile.Register32 // 0x1C
	GPIOZ_AFRL     volatile.Register32 // 0x20
	GPIOZ_AFRH     volatile.Register32 // 0x24
	GPIOZ_BRR      volatile.Register32 // 0x28
	_              [4]byte
	GPIOZ_SECCFGR  volatile.Register32 // 0x30
	_              [916]byte
	GPIOZ_HWCFGR10 volatile.Register32 // 0x3C8
	GPIOZ_HWCFGR9  volatile.Register32 // 0x3CC
	GPIOZ_HWCFGR8  volatile.Register32 // 0x3D0
	GPIOZ_HWCFGR7  volatile.Register32 // 0x3D4
	GPIOZ_HWCFGR6  volatile.Register32 // 0x3D8
	GPIOZ_HWCFGR5  volatile.Register32 // 0x3DC
	GPIOZ_HWCFGR4  volatile.Register32 // 0x3E0
	GPIOZ_HWCFGR3  volatile.Register32 // 0x3E4
	GPIOZ_HWCFGR2  volatile.Register32 // 0x3E8
	GPIOZ_HWCFGR1  volatile.Register32 // 0x3EC
	GPIOZ_HWCFGR0  volatile.Register32 // 0x3F0
	GPIOZ_VERR     volatile.Register32 // 0x3F4
	GPIOZ_IPIDR    volatile.Register32 // 0x3F8
	GPIOZ_SIDR     volatile.Register32 // 0x3FC
}

// HASH register block
type HASH_Type struct {
	HASH_CR     volatile.Register32 // 0x0
	HASH_DIN    volatile.Register32 // 0x4
	HASH_STR    volatile.Register32 // 0x8
	HASH_HR0    volatile.Register32 // 0xC
	HASH_HR1    volatile.Register32 // 0x10
	HASH_HR2    volatile.Register32 // 0x14
	HASH_HR3    volatile.Register32 // 0x18
	HASH_HR4    volatile.Register32 // 0x1C
	HASH_IMR    volatile.Register32 // 0x20
	HASH_SR     volatile.Register32 // 0x24
	_           [208]byte
	HASH_CSR0   volatile.Register32 // 0xF8
	HASH_CSR1   volatile.Register32 // 0xFC
	HASH_CSR2   volatile.Register32 // 0x100
	HASH_CSR3   volatile.Register32 // 0x104
	HASH_CSR4   volatile.Register32 // 0x108
	HASH_CSR5   volatile.Register32 // 0x10C
	HASH_CSR6   volatile.Register32 // 0x110
	HASH_CSR7   volatile.Register32 // 0x114
	HASH_CSR8   volatile.Register32 // 0x118
	HASH_CSR9   volatile.Register32 // 0x11C
	HASH_CSR10  volatile.Register32 // 0x120
	HASH_CSR11  volatile.Register32 // 0x124
	HASH_CSR12  volatile.Register32 // 0x128
	HASH_CSR13  volatile.Register32 // 0x12C
	HASH_CSR14  volatile.Register32 // 0x130
	HASH_CSR15  volatile.Register32 // 0x134
	HASH_CSR16  volatile.Register32 // 0x138
	HASH_CSR17  volatile.Register32 // 0x13C
	HASH_CSR18  volatile.Register32 // 0x140
	HASH_CSR19  volatile.Register32 // 0x144
	HASH_CSR20  volatile.Register32 // 0x148
	HASH_CSR21  volatile.Register32 // 0x14C
	HASH_CSR22  volatile.Register32 // 0x150
	HASH_CSR23  volatile.Register32 // 0x154
	HASH_CSR24  volatile.Register32 // 0x158
	HASH_CSR25  volatile.Register32 // 0x15C
	HASH_CSR26  volatile.Register32 // 0x160
	HASH_CSR27  volatile.Register32 // 0x164
	HASH_CSR28  volatile.Register32 // 0x168
	HASH_CSR29  volatile.Register32 // 0x16C
	HASH_CSR30  volatile.Register32 // 0x170
	HASH_CSR31  volatile.Register32 // 0x174
	HASH_CSR32  volatile.Register32 // 0x178
	HASH_CSR33  volatile.Register32 // 0x17C
	HASH_CSR34  volatile.Register32 // 0x180
	HASH_CSR35  volatile.Register32 // 0x184
	HASH_CSR36  volatile.Register32 // 0x188
	HASH_CSR37  volatile.Register32 // 0x18C
	HASH_CSR38  volatile.Register32 // 0x190
	HASH_CSR39  volatile.Register32 // 0x194
	HASH_CSR40  volatile.Register32 // 0x198
	HASH_CSR41  volatile.Register32 // 0x19C
	HASH_CSR42  volatile.Register32 // 0x1A0
	HASH_CSR43  volatile.Register32 // 0x1A4
	HASH_CSR44  volatile.Register32 // 0x1A8
	HASH_CSR45  volatile.Register32 // 0x1AC
	HASH_CSR46  volatile.Register32 // 0x1B0
	HASH_CSR47  volatile.Register32 // 0x1B4
	HASH_CSR48  volatile.Register32 // 0x1B8
	HASH_CSR49  volatile.Register32 // 0x1BC
	HASH_CSR50  volatile.Register32 // 0x1C0
	HASH_CSR51  volatile.Register32 // 0x1C4
	HASH_CSR52  volatile.Register32 // 0x1C8
	HASH_CSR53  volatile.Register32 // 0x1CC
	_           [340]byte
	HASH_HR5    volatile.Register32 // 0x324
	HASH_HR6    volatile.Register32 // 0x328
	HASH_HR7    volatile.Register32 // 0x32C
	_           [192]byte
	HASH_HWCFGR volatile.Register32 // 0x3F0
	HASH_VERR   volatile.Register32 // 0x3F4
	HASH_IPIDR  volatile.Register32 // 0x3F8
	HASH_MID    volatile.Register32 // 0x3FC
}

// HDMI_CEC
type HDMI_CEC_Type struct {
	CEC_CR   volatile.Register32 // 0x0
	CEC_CFGR volatile.Register32 // 0x4
	CEC_TXDR volatile.Register32 // 0x8
	CEC_RXDR volatile.Register32 // 0xC
	CEC_ISR  volatile.Register32 // 0x10
	CEC_IER  volatile.Register32 // 0x14
}

// HDP
type HDP_Type struct {
	HDP_CTRL   volatile.Register32 // 0x0
	HDP_MUX    volatile.Register32 // 0x4
	_          [8]byte
	HDP_VAL    volatile.Register32 // 0x10
	HDP_GPOSET volatile.Register32 // 0x14
	HDP_GPOCLR volatile.Register32 // 0x18
	HDP_GPOVAL volatile.Register32 // 0x1C
	_          [980]byte
	HDP_VERR   volatile.Register32 // 0x3F4
	HDP_IPIDR  volatile.Register32 // 0x3F8
	HDP_SIDR   volatile.Register32 // 0x3FC
}

// HSEM
type HSEM_IPXACT_Type struct {
	HSEM_R0      volatile.Register32 // 0x0
	HSEM_R1      volatile.Register32 // 0x4
	HSEM_R2      volatile.Register32 // 0x8
	HSEM_R3      volatile.Register32 // 0xC
	HSEM_R4      volatile.Register32 // 0x10
	HSEM_R5      volatile.Register32 // 0x14
	HSEM_R6      volatile.Register32 // 0x18
	HSEM_R7      volatile.Register32 // 0x1C
	HSEM_R8      volatile.Register32 // 0x20
	HSEM_R9      volatile.Register32 // 0x24
	HSEM_R10     volatile.Register32 // 0x28
	HSEM_R11     volatile.Register32 // 0x2C
	HSEM_R12     volatile.Register32 // 0x30
	HSEM_R13     volatile.Register32 // 0x34
	HSEM_R14     volatile.Register32 // 0x38
	HSEM_R15     volatile.Register32 // 0x3C
	HSEM_R16     volatile.Register32 // 0x40
	HSEM_R17     volatile.Register32 // 0x44
	HSEM_R18     volatile.Register32 // 0x48
	HSEM_R19     volatile.Register32 // 0x4C
	HSEM_R20     volatile.Register32 // 0x50
	HSEM_R21     volatile.Register32 // 0x54
	HSEM_R22     volatile.Register32 // 0x58
	HSEM_R23     volatile.Register32 // 0x5C
	HSEM_R24     volatile.Register32 // 0x60
	HSEM_R25     volatile.Register32 // 0x64
	HSEM_R26     volatile.Register32 // 0x68
	HSEM_R27     volatile.Register32 // 0x6C
	HSEM_R28     volatile.Register32 // 0x70
	HSEM_R29     volatile.Register32 // 0x74
	HSEM_R30     volatile.Register32 // 0x78
	HSEM_R31     volatile.Register32 // 0x7C
	HSEM_RLR0    volatile.Register32 // 0x80
	HSEM_RLR1    volatile.Register32 // 0x84
	HSEM_RLR2    volatile.Register32 // 0x88
	HSEM_RLR3    volatile.Register32 // 0x8C
	HSEM_RLR4    volatile.Register32 // 0x90
	HSEM_RLR5    volatile.Register32 // 0x94
	HSEM_RLR6    volatile.Register32 // 0x98
	HSEM_RLR7    volatile.Register32 // 0x9C
	HSEM_RLR8    volatile.Register32 // 0xA0
	HSEM_RLR9    volatile.Register32 // 0xA4
	HSEM_RLR10   volatile.Register32 // 0xA8
	HSEM_RLR11   volatile.Register32 // 0xAC
	HSEM_RLR12   volatile.Register32 // 0xB0
	HSEM_RLR13   volatile.Register32 // 0xB4
	HSEM_RLR14   volatile.Register32 // 0xB8
	HSEM_RLR15   volatile.Register32 // 0xBC
	HSEM_RLR16   volatile.Register32 // 0xC0
	HSEM_RLR17   volatile.Register32 // 0xC4
	HSEM_RLR18   volatile.Register32 // 0xC8
	HSEM_RLR19   volatile.Register32 // 0xCC
	HSEM_RLR20   volatile.Register32 // 0xD0
	HSEM_RLR21   volatile.Register32 // 0xD4
	HSEM_RLR22   volatile.Register32 // 0xD8
	HSEM_RLR23   volatile.Register32 // 0xDC
	HSEM_RLR24   volatile.Register32 // 0xE0
	HSEM_RLR25   volatile.Register32 // 0xE4
	HSEM_RLR26   volatile.Register32 // 0xE8
	HSEM_RLR27   volatile.Register32 // 0xEC
	HSEM_RLR28   volatile.Register32 // 0xF0
	HSEM_RLR29   volatile.Register32 // 0xF4
	HSEM_RLR30   volatile.Register32 // 0xF8
	HSEM_RLR31   volatile.Register32 // 0xFC
	HSEM_C1IER   volatile.Register32 // 0x100
	HSEM_C1ICR   volatile.Register32 // 0x104
	HSEM_C1ISR   volatile.Register32 // 0x108
	HSEM_C1MISR  volatile.Register32 // 0x10C
	HSEM_C2IER   volatile.Register32 // 0x110
	HSEM_C2ICR   volatile.Register32 // 0x114
	HSEM_C2ISR   volatile.Register32 // 0x118
	HSEM_C2MISR  volatile.Register32 // 0x11C
	_            [32]byte
	HSEM_CR      volatile.Register32 // 0x140
	HSEM_KEYR    volatile.Register32 // 0x144
	_            [676]byte
	HSEM_HWCFGR2 volatile.Register32 // 0x3EC
	HSEM_HWCFGR1 volatile.Register32 // 0x3F0
	HSEM_VERR    volatile.Register32 // 0x3F4
	HSEM_IPIDR   volatile.Register32 // 0x3F8
	HSEM_SIDR    volatile.Register32 // 0x3FC
}

// I2C1
type I2C2_IPXACT_Type struct {
	I2C_CR1      volatile.Register32 // 0x0
	I2C_CR2      volatile.Register32 // 0x4
	I2C_OAR1     volatile.Register32 // 0x8
	I2C_OAR2     volatile.Register32 // 0xC
	I2C_TIMINGR  volatile.Register32 // 0x10
	I2C_TIMEOUTR volatile.Register32 // 0x14
	I2C_ISR      volatile.Register32 // 0x18
	I2C_ICR      volatile.Register32 // 0x1C
	I2C_PECR     volatile.Register32 // 0x20
	I2C_RXDR     volatile.Register32 // 0x24
	I2C_TXDR     volatile.Register32 // 0x28
	_            [964]byte
	I2C_HWCFGR   volatile.Register32 // 0x3F0
	I2C_VERR     volatile.Register32 // 0x3F4
	I2C_IPIDR    volatile.Register32 // 0x3F8
	I2C_SIDR     volatile.Register32 // 0x3FC
}

// IPCC
type IPCC_Type struct {
	IPCC_C1CR     volatile.Register32 // 0x0
	IPCC_C1MR     volatile.Register32 // 0x4
	IPCC_C1SCR    volatile.Register32 // 0x8
	IPCC_C1TOC2SR volatile.Register32 // 0xC
	IPCC_C2CR     volatile.Register32 // 0x10
	IPCC_C2MR     volatile.Register32 // 0x14
	IPCC_C2SCR    volatile.Register32 // 0x18
	IPCC_C2TOC1SR volatile.Register32 // 0x1C
	_             [976]byte
	IPCC_HWCFGR   volatile.Register32 // 0x3F0
	IPCC_VER      volatile.Register32 // 0x3F4
	IPCC_ID       volatile.Register32 // 0x3F8
	IPCC_SID      volatile.Register32 // 0x3FC
}

// IWDG1
type IWDG1_Type struct {
	IWDG_KR     volatile.Register32 // 0x0
	IWDG_PR     volatile.Register32 // 0x4
	IWDG_RLR    volatile.Register32 // 0x8
	IWDG_SR     volatile.Register32 // 0xC
	IWDG_WINR   volatile.Register32 // 0x10
	_           [988]byte
	IWDG_HWCFGR volatile.Register32 // 0x3F0
	IWDG_VERR   volatile.Register32 // 0x3F4
	IWDG_IDR    volatile.Register32 // 0x3F8
	IWDG_SIDR   volatile.Register32 // 0x3FC
}

// LPTIM1
type LPTIM1_Type struct {
	LPTIM_ISR     volatile.Register32 // 0x0
	LPTIM_ICR     volatile.Register32 // 0x4
	LPTIM_IER     volatile.Register32 // 0x8
	LPTIM_CFGR    volatile.Register32 // 0xC
	LPTIM_CR      volatile.Register32 // 0x10
	LPTIM_CMP     volatile.Register32 // 0x14
	LPTIM_ARR     volatile.Register32 // 0x18
	LPTIM_CNT     volatile.Register32 // 0x1C
	_             [4]byte
	LPTIM_CFGR2   volatile.Register32 // 0x24
	_             [968]byte
	LPTIM1_HWCFGR volatile.Register32 // 0x3F0
	LPTIM_VERR    volatile.Register32 // 0x3F4
	LPTIM_PIDR    volatile.Register32 // 0x3F8
	LPTIM_SIDR    volatile.Register32 // 0x3FC
}

// LTDC
type LTDC_Type struct {
	LTDC_IDR      volatile.Register32 // 0x0
	LTDC_LCR      volatile.Register32 // 0x4
	LTDC_SSCR     volatile.Register32 // 0x8
	LTDC_BPCR     volatile.Register32 // 0xC
	LTDC_AWCR     volatile.Register32 // 0x10
	LTDC_TWCR     volatile.Register32 // 0x14
	LTDC_GCR      volatile.Register32 // 0x18
	LTDC_GC1R     volatile.Register32 // 0x1C
	LTDC_GC2R     volatile.Register32 // 0x20
	LTDC_SRCR     volatile.Register32 // 0x24
	_             [4]byte
	LTDC_BCCR     volatile.Register32 // 0x2C
	_             [4]byte
	LTDC_IER      volatile.Register32 // 0x34
	LTDC_ISR      volatile.Register32 // 0x38
	LTDC_ICR      volatile.Register32 // 0x3C
	LTDC_LIPCR    volatile.Register32 // 0x40
	LTDC_CPSR     volatile.Register32 // 0x44
	LTDC_CDSR     volatile.Register32 // 0x48
	_             [56]byte
	LTDC_L1CR     volatile.Register32 // 0x84
	LTDC_L1WHPCR  volatile.Register32 // 0x88
	LTDC_L1WVPCR  volatile.Register32 // 0x8C
	LTDC_L1CKCR   volatile.Register32 // 0x90
	LTDC_L1PFCR   volatile.Register32 // 0x94
	LTDC_L1CACR   volatile.Register32 // 0x98
	LTDC_L1DCCR   volatile.Register32 // 0x9C
	LTDC_L1BFCR   volatile.Register32 // 0xA0
	_             [8]byte
	LTDC_L1CFBAR  volatile.Register32 // 0xAC
	LTDC_L1CFBLR  volatile.Register32 // 0xB0
	LTDC_L1CFBLNR volatile.Register32 // 0xB4
	_             [12]byte
	LTDC_L1CLUTWR volatile.Register32 // 0xC4
	_             [60]byte
	LTDC_L2CR     volatile.Register32 // 0x104
	LTDC_L2WHPCR  volatile.Register32 // 0x108
	LTDC_L2WVPCR  volatile.Register32 // 0x10C
	LTDC_L2CKCR   volatile.Register32 // 0x110
	LTDC_L2PFCR   volatile.Register32 // 0x114
	LTDC_L2CACR   volatile.Register32 // 0x118
	LTDC_L2DCCR   volatile.Register32 // 0x11C
	LTDC_L2BFCR   volatile.Register32 // 0x120
	_             [8]byte
	LTDC_L2CFBAR  volatile.Register32 // 0x12C
	LTDC_L2CFBLR  volatile.Register32 // 0x130
	LTDC_L2CFBLNR volatile.Register32 // 0x134
	_             [12]byte
	LTDC_L2CLUTWR volatile.Register32 // 0x144
}

// MDIOS
type MDIOS_Type struct {
	MDIOS_CR      volatile.Register32 // 0x0
	MDIOS_WRFR    volatile.Register32 // 0x4
	MDIOS_CWRFR   volatile.Register32 // 0x8
	MDIOS_RDFR    volatile.Register32 // 0xC
	MDIOS_CRDFR   volatile.Register32 // 0x10
	MDIOS_SR      volatile.Register32 // 0x14
	MDIOS_CLRFR   volatile.Register32 // 0x18
	_             [228]byte
	MDIOS_DINR0   volatile.Register32 // 0x100
	MDIOS_DINR1   volatile.Register32 // 0x104
	MDIOS_DINR2   volatile.Register32 // 0x108
	MDIOS_DINR3   volatile.Register32 // 0x10C
	MDIOS_DINR4   volatile.Register32 // 0x110
	MDIOS_DINR5   volatile.Register32 // 0x114
	MDIOS_DINR6   volatile.Register32 // 0x118
	MDIOS_DINR7   volatile.Register32 // 0x11C
	MDIOS_DINR8   volatile.Register32 // 0x120
	MDIOS_DINR9   volatile.Register32 // 0x124
	MDIOS_DINR10  volatile.Register32 // 0x128
	MDIOS_DINR11  volatile.Register32 // 0x12C
	MDIOS_DINR12  volatile.Register32 // 0x130
	MDIOS_DINR13  volatile.Register32 // 0x134
	MDIOS_DINR14  volatile.Register32 // 0x138
	MDIOS_DINR15  volatile.Register32 // 0x13C
	MDIOS_DINR16  volatile.Register32 // 0x140
	MDIOS_DINR17  volatile.Register32 // 0x144
	MDIOS_DINR18  volatile.Register32 // 0x148
	MDIOS_DINR19  volatile.Register32 // 0x14C
	MDIOS_DINR20  volatile.Register32 // 0x150
	MDIOS_DINR21  volatile.Register32 // 0x154
	MDIOS_DINR22  volatile.Register32 // 0x158
	MDIOS_DINR23  volatile.Register32 // 0x15C
	MDIOS_DINR24  volatile.Register32 // 0x160
	MDIOS_DINR25  volatile.Register32 // 0x164
	MDIOS_DINR26  volatile.Register32 // 0x168
	MDIOS_DINR27  volatile.Register32 // 0x16C
	MDIOS_DINR28  volatile.Register32 // 0x170
	MDIOS_DINR29  volatile.Register32 // 0x174
	MDIOS_DINR30  volatile.Register32 // 0x178
	MDIOS_DINR31  volatile.Register32 // 0x17C
	MDIOS_DOUTR0  volatile.Register32 // 0x180
	MDIOS_DOUTR1  volatile.Register32 // 0x184
	MDIOS_DOUTR2  volatile.Register32 // 0x188
	MDIOS_DOUTR3  volatile.Register32 // 0x18C
	MDIOS_DOUTR4  volatile.Register32 // 0x190
	MDIOS_DOUTR5  volatile.Register32 // 0x194
	MDIOS_DOUTR6  volatile.Register32 // 0x198
	MDIOS_DOUTR7  volatile.Register32 // 0x19C
	MDIOS_DOUTR8  volatile.Register32 // 0x1A0
	MDIOS_DOUTR9  volatile.Register32 // 0x1A4
	MDIOS_DOUTR10 volatile.Register32 // 0x1A8
	MDIOS_DOUTR11 volatile.Register32 // 0x1AC
	MDIOS_DOUTR12 volatile.Register32 // 0x1B0
	MDIOS_DOUTR13 volatile.Register32 // 0x1B4
	MDIOS_DOUTR14 volatile.Register32 // 0x1B8
	MDIOS_DOUTR15 volatile.Register32 // 0x1BC
	MDIOS_DOUTR16 volatile.Register32 // 0x1C0
	MDIOS_DOUTR17 volatile.Register32 // 0x1C4
	MDIOS_DOUTR18 volatile.Register32 // 0x1C8
	MDIOS_DOUTR19 volatile.Register32 // 0x1CC
	MDIOS_DOUTR20 volatile.Register32 // 0x1D0
	MDIOS_DOUTR21 volatile.Register32 // 0x1D4
	MDIOS_DOUTR22 volatile.Register32 // 0x1D8
	MDIOS_DOUTR23 volatile.Register32 // 0x1DC
	MDIOS_DOUTR24 volatile.Register32 // 0x1E0
	MDIOS_DOUTR25 volatile.Register32 // 0x1E4
	MDIOS_DOUTR26 volatile.Register32 // 0x1E8
	MDIOS_DOUTR27 volatile.Register32 // 0x1EC
	MDIOS_DOUTR28 volatile.Register32 // 0x1F0
	MDIOS_DOUTR29 volatile.Register32 // 0x1F4
	MDIOS_DOUTR30 volatile.Register32 // 0x1F8
	MDIOS_DOUTR31 volatile.Register32 // 0x1FC
	_             [496]byte
	MDIOS_HWCFGR  volatile.Register32 // 0x3F0
	MDIOS_VERR    volatile.Register32 // 0x3F4
	MDIOS_IPIDR   volatile.Register32 // 0x3F8
	MDIOS_SIDR    volatile.Register32 // 0x3FC
}

// MDMA1
type MDMA1_Type struct {
	MDMA_GISR0    volatile.Register32 // 0x0
	_             [4]byte
	MDMA_SGISR0   volatile.Register32 // 0x8
	_             [52]byte
	MDMA_C0ISR    volatile.Register32 // 0x40
	MDMA_C0IFCR   volatile.Register32 // 0x44
	MDMA_C0ESR    volatile.Register32 // 0x48
	MDMA_C0CR     volatile.Register32 // 0x4C
	MDMA_C0TCR    volatile.Register32 // 0x50
	MDMA_C0BNDTR  volatile.Register32 // 0x54
	MDMA_C0SAR    volatile.Register32 // 0x58
	MDMA_C0DAR    volatile.Register32 // 0x5C
	MDMA_C0BRUR   volatile.Register32 // 0x60
	MDMA_C0LAR    volatile.Register32 // 0x64
	MDMA_C0TBR    volatile.Register32 // 0x68
	_             [4]byte
	MDMA_C0MAR    volatile.Register32 // 0x70
	MDMA_C0MDR    volatile.Register32 // 0x74
	_             [8]byte
	MDMA_C1ISR    volatile.Register32 // 0x80
	MDMA_C1IFCR   volatile.Register32 // 0x84
	MDMA_C1ESR    volatile.Register32 // 0x88
	MDMA_C1CR     volatile.Register32 // 0x8C
	MDMA_C1TCR    volatile.Register32 // 0x90
	MDMA_C1BNDTR  volatile.Register32 // 0x94
	MDMA_C1SAR    volatile.Register32 // 0x98
	MDMA_C1DAR    volatile.Register32 // 0x9C
	MDMA_C1BRUR   volatile.Register32 // 0xA0
	MDMA_C1LAR    volatile.Register32 // 0xA4
	MDMA_C1TBR    volatile.Register32 // 0xA8
	_             [4]byte
	MDMA_C1MAR    volatile.Register32 // 0xB0
	MDMA_C1MDR    volatile.Register32 // 0xB4
	_             [8]byte
	MDMA_C2ISR    volatile.Register32 // 0xC0
	MDMA_C2IFCR   volatile.Register32 // 0xC4
	MDMA_C2ESR    volatile.Register32 // 0xC8
	MDMA_C2CR     volatile.Register32 // 0xCC
	MDMA_C2TCR    volatile.Register32 // 0xD0
	MDMA_C2BNDTR  volatile.Register32 // 0xD4
	MDMA_C2SAR    volatile.Register32 // 0xD8
	MDMA_C2DAR    volatile.Register32 // 0xDC
	MDMA_C2BRUR   volatile.Register32 // 0xE0
	MDMA_C2LAR    volatile.Register32 // 0xE4
	MDMA_C2TBR    volatile.Register32 // 0xE8
	_             [4]byte
	MDMA_C2MAR    volatile.Register32 // 0xF0
	MDMA_C2MDR    volatile.Register32 // 0xF4
	_             [8]byte
	MDMA_C3ISR    volatile.Register32 // 0x100
	MDMA_C3IFCR   volatile.Register32 // 0x104
	MDMA_C3ESR    volatile.Register32 // 0x108
	MDMA_C3CR     volatile.Register32 // 0x10C
	MDMA_C3TCR    volatile.Register32 // 0x110
	MDMA_C3BNDTR  volatile.Register32 // 0x114
	MDMA_C3SAR    volatile.Register32 // 0x118
	MDMA_C3DAR    volatile.Register32 // 0x11C
	MDMA_C3BRUR   volatile.Register32 // 0x120
	MDMA_C3LAR    volatile.Register32 // 0x124
	MDMA_C3TBR    volatile.Register32 // 0x128
	_             [4]byte
	MDMA_C3MAR    volatile.Register32 // 0x130
	MDMA_C3MDR    volatile.Register32 // 0x134
	_             [8]byte
	MDMA_C4ISR    volatile.Register32 // 0x140
	MDMA_C4IFCR   volatile.Register32 // 0x144
	MDMA_C4ESR    volatile.Register32 // 0x148
	MDMA_C4CR     volatile.Register32 // 0x14C
	MDMA_C4TCR    volatile.Register32 // 0x150
	MDMA_C4BNDTR  volatile.Register32 // 0x154
	MDMA_C4SAR    volatile.Register32 // 0x158
	MDMA_C4DAR    volatile.Register32 // 0x15C
	MDMA_C4BRUR   volatile.Register32 // 0x160
	MDMA_C4LAR    volatile.Register32 // 0x164
	MDMA_C4TBR    volatile.Register32 // 0x168
	_             [4]byte
	MDMA_C4MAR    volatile.Register32 // 0x170
	MDMA_C4MDR    volatile.Register32 // 0x174
	_             [8]byte
	MDMA_C5ISR    volatile.Register32 // 0x180
	MDMA_C5IFCR   volatile.Register32 // 0x184
	MDMA_C5ESR    volatile.Register32 // 0x188
	MDMA_C5CR     volatile.Register32 // 0x18C
	MDMA_C5TCR    volatile.Register32 // 0x190
	MDMA_C5BNDTR  volatile.Register32 // 0x194
	MDMA_C5SAR    volatile.Register32 // 0x198
	MDMA_C5DAR    volatile.Register32 // 0x19C
	MDMA_C5BRUR   volatile.Register32 // 0x1A0
	MDMA_C5LAR    volatile.Register32 // 0x1A4
	MDMA_C5TBR    volatile.Register32 // 0x1A8
	_             [4]byte
	MDMA_C5MAR    volatile.Register32 // 0x1B0
	MDMA_C5MDR    volatile.Register32 // 0x1B4
	_             [8]byte
	MDMA_C6ISR    volatile.Register32 // 0x1C0
	MDMA_C6IFCR   volatile.Register32 // 0x1C4
	MDMA_C6ESR    volatile.Register32 // 0x1C8
	MDMA_C6CR     volatile.Register32 // 0x1CC
	MDMA_C6TCR    volatile.Register32 // 0x1D0
	MDMA_C6BNDTR  volatile.Register32 // 0x1D4
	MDMA_C6SAR    volatile.Register32 // 0x1D8
	MDMA_C6DAR    volatile.Register32 // 0x1DC
	MDMA_C6BRUR   volatile.Register32 // 0x1E0
	MDMA_C6LAR    volatile.Register32 // 0x1E4
	MDMA_C6TBR    volatile.Register32 // 0x1E8
	_             [4]byte
	MDMA_C6MAR    volatile.Register32 // 0x1F0
	MDMA_C6MDR    volatile.Register32 // 0x1F4
	_             [8]byte
	MDMA_C7ISR    volatile.Register32 // 0x200
	MDMA_C7IFCR   volatile.Register32 // 0x204
	MDMA_C7ESR    volatile.Register32 // 0x208
	MDMA_C7CR     volatile.Register32 // 0x20C
	MDMA_C7TCR    volatile.Register32 // 0x210
	MDMA_C7BNDTR  volatile.Register32 // 0x214
	MDMA_C7SAR    volatile.Register32 // 0x218
	MDMA_C7DAR    volatile.Register32 // 0x21C
	MDMA_C7BRUR   volatile.Register32 // 0x220
	MDMA_C7LAR    volatile.Register32 // 0x224
	MDMA_C7TBR    volatile.Register32 // 0x228
	_             [4]byte
	MDMA_C7MAR    volatile.Register32 // 0x230
	MDMA_C7MDR    volatile.Register32 // 0x234
	_             [8]byte
	MDMA_C8ISR    volatile.Register32 // 0x240
	MDMA_C8IFCR   volatile.Register32 // 0x244
	MDMA_C8ESR    volatile.Register32 // 0x248
	MDMA_C8CR     volatile.Register32 // 0x24C
	MDMA_C8TCR    volatile.Register32 // 0x250
	MDMA_C8BNDTR  volatile.Register32 // 0x254
	MDMA_C8SAR    volatile.Register32 // 0x258
	MDMA_C8DAR    volatile.Register32 // 0x25C
	MDMA_C8BRUR   volatile.Register32 // 0x260
	MDMA_C8LAR    volatile.Register32 // 0x264
	MDMA_C8TBR    volatile.Register32 // 0x268
	_             [4]byte
	MDMA_C8MAR    volatile.Register32 // 0x270
	MDMA_C8MDR    volatile.Register32 // 0x274
	_             [8]byte
	MDMA_C9ISR    volatile.Register32 // 0x280
	MDMA_C9IFCR   volatile.Register32 // 0x284
	MDMA_C9ESR    volatile.Register32 // 0x288
	MDMA_C9CR     volatile.Register32 // 0x28C
	MDMA_C9TCR    volatile.Register32 // 0x290
	MDMA_C9BNDTR  volatile.Register32 // 0x294
	MDMA_C9SAR    volatile.Register32 // 0x298
	MDMA_C9DAR    volatile.Register32 // 0x29C
	MDMA_C9BRUR   volatile.Register32 // 0x2A0
	MDMA_C9LAR    volatile.Register32 // 0x2A4
	MDMA_C9TBR    volatile.Register32 // 0x2A8
	_             [4]byte
	MDMA_C9MAR    volatile.Register32 // 0x2B0
	MDMA_C9MDR    volatile.Register32 // 0x2B4
	_             [8]byte
	MDMA_C10ISR   volatile.Register32 // 0x2C0
	MDMA_C10IFCR  volatile.Register32 // 0x2C4
	MDMA_C10ESR   volatile.Register32 // 0x2C8
	MDMA_C10CR    volatile.Register32 // 0x2CC
	MDMA_C10TCR   volatile.Register32 // 0x2D0
	MDMA_C10BNDTR volatile.Register32 // 0x2D4
	MDMA_C10SAR   volatile.Register32 // 0x2D8
	MDMA_C10DAR   volatile.Register32 // 0x2DC
	MDMA_C10BRUR  volatile.Register32 // 0x2E0
	MDMA_C10LAR   volatile.Register32 // 0x2E4
	MDMA_C10TBR   volatile.Register32 // 0x2E8
	_             [4]byte
	MDMA_C10MAR   volatile.Register32 // 0x2F0
	MDMA_C10MDR   volatile.Register32 // 0x2F4
	_             [8]byte
	MDMA_C11ISR   volatile.Register32 // 0x300
	MDMA_C11IFCR  volatile.Register32 // 0x304
	MDMA_C11ESR   volatile.Register32 // 0x308
	MDMA_C11CR    volatile.Register32 // 0x30C
	MDMA_C11TCR   volatile.Register32 // 0x310
	MDMA_C11BNDTR volatile.Register32 // 0x314
	MDMA_C11SAR   volatile.Register32 // 0x318
	MDMA_C11DAR   volatile.Register32 // 0x31C
	MDMA_C11BRUR  volatile.Register32 // 0x320
	MDMA_C11LAR   volatile.Register32 // 0x324
	MDMA_C11TBR   volatile.Register32 // 0x328
	_             [4]byte
	MDMA_C11MAR   volatile.Register32 // 0x330
	MDMA_C11MDR   volatile.Register32 // 0x334
	_             [8]byte
	MDMA_C12ISR   volatile.Register32 // 0x340
	MDMA_C12IFCR  volatile.Register32 // 0x344
	MDMA_C12ESR   volatile.Register32 // 0x348
	MDMA_C12CR    volatile.Register32 // 0x34C
	MDMA_C12TCR   volatile.Register32 // 0x350
	MDMA_C12BNDTR volatile.Register32 // 0x354
	MDMA_C12SAR   volatile.Register32 // 0x358
	MDMA_C12DAR   volatile.Register32 // 0x35C
	MDMA_C12BRUR  volatile.Register32 // 0x360
	MDMA_C12LAR   volatile.Register32 // 0x364
	MDMA_C12TBR   volatile.Register32 // 0x368
	_             [4]byte
	MDMA_C12MAR   volatile.Register32 // 0x370
	MDMA_C12MDR   volatile.Register32 // 0x374
	_             [8]byte
	MDMA_C13ISR   volatile.Register32 // 0x380
	MDMA_C13IFCR  volatile.Register32 // 0x384
	MDMA_C13ESR   volatile.Register32 // 0x388
	MDMA_C13CR    volatile.Register32 // 0x38C
	MDMA_C13TCR   volatile.Register32 // 0x390
	MDMA_C13BNDTR volatile.Register32 // 0x394
	MDMA_C13SAR   volatile.Register32 // 0x398
	MDMA_C13DAR   volatile.Register32 // 0x39C
	MDMA_C13BRUR  volatile.Register32 // 0x3A0
	MDMA_C13LAR   volatile.Register32 // 0x3A4
	MDMA_C13TBR   volatile.Register32 // 0x3A8
	_             [4]byte
	MDMA_C13MAR   volatile.Register32 // 0x3B0
	MDMA_C13MDR   volatile.Register32 // 0x3B4
	_             [8]byte
	MDMA_C14ISR   volatile.Register32 // 0x3C0
	MDMA_C14IFCR  volatile.Register32 // 0x3C4
	MDMA_C14ESR   volatile.Register32 // 0x3C8
	MDMA_C14CR    volatile.Register32 // 0x3CC
	MDMA_C14TCR   volatile.Register32 // 0x3D0
	MDMA_C14BNDTR volatile.Register32 // 0x3D4
	MDMA_C14SAR   volatile.Register32 // 0x3D8
	MDMA_C14DAR   volatile.Register32 // 0x3DC
	MDMA_C14BRUR  volatile.Register32 // 0x3E0
	MDMA_C14LAR   volatile.Register32 // 0x3E4
	MDMA_C14TBR   volatile.Register32 // 0x3E8
	_             [4]byte
	MDMA_C14MAR   volatile.Register32 // 0x3F0
	MDMA_C14MDR   volatile.Register32 // 0x3F4
	_             [8]byte
	MDMA_C15ISR   volatile.Register32 // 0x400
	MDMA_C15IFCR  volatile.Register32 // 0x404
	MDMA_C15ESR   volatile.Register32 // 0x408
	MDMA_C15CR    volatile.Register32 // 0x40C
	MDMA_C15TCR   volatile.Register32 // 0x410
	MDMA_C15BNDTR volatile.Register32 // 0x414
	MDMA_C15SAR   volatile.Register32 // 0x418
	MDMA_C15DAR   volatile.Register32 // 0x41C
	MDMA_C15BRUR  volatile.Register32 // 0x420
	MDMA_C15LAR   volatile.Register32 // 0x424
	MDMA_C15TBR   volatile.Register32 // 0x428
	_             [4]byte
	MDMA_C15MAR   volatile.Register32 // 0x430
	MDMA_C15MDR   volatile.Register32 // 0x434
	_             [8]byte
	MDMA_C16ISR   volatile.Register32 // 0x440
	MDMA_C16IFCR  volatile.Register32 // 0x444
	MDMA_C16ESR   volatile.Register32 // 0x448
	MDMA_C16CR    volatile.Register32 // 0x44C
	MDMA_C16TCR   volatile.Register32 // 0x450
	MDMA_C16BNDTR volatile.Register32 // 0x454
	MDMA_C16SAR   volatile.Register32 // 0x458
	MDMA_C16DAR   volatile.Register32 // 0x45C
	MDMA_C16BRUR  volatile.Register32 // 0x460
	MDMA_C16LAR   volatile.Register32 // 0x464
	MDMA_C16TBR   volatile.Register32 // 0x468
	_             [4]byte
	MDMA_C16MAR   volatile.Register32 // 0x470
	MDMA_C16MDR   volatile.Register32 // 0x474
	_             [8]byte
	MDMA_C17ISR   volatile.Register32 // 0x480
	MDMA_C17IFCR  volatile.Register32 // 0x484
	MDMA_C17ESR   volatile.Register32 // 0x488
	MDMA_C17CR    volatile.Register32 // 0x48C
	MDMA_C17TCR   volatile.Register32 // 0x490
	MDMA_C17BNDTR volatile.Register32 // 0x494
	MDMA_C17SAR   volatile.Register32 // 0x498
	MDMA_C17DAR   volatile.Register32 // 0x49C
	MDMA_C17BRUR  volatile.Register32 // 0x4A0
	MDMA_C17LAR   volatile.Register32 // 0x4A4
	MDMA_C17TBR   volatile.Register32 // 0x4A8
	_             [4]byte
	MDMA_C17MAR   volatile.Register32 // 0x4B0
	MDMA_C17MDR   volatile.Register32 // 0x4B4
	_             [8]byte
	MDMA_C18ISR   volatile.Register32 // 0x4C0
	MDMA_C18IFCR  volatile.Register32 // 0x4C4
	MDMA_C18ESR   volatile.Register32 // 0x4C8
	MDMA_C18CR    volatile.Register32 // 0x4CC
	MDMA_C18TCR   volatile.Register32 // 0x4D0
	MDMA_C18BNDTR volatile.Register32 // 0x4D4
	MDMA_C18SAR   volatile.Register32 // 0x4D8
	MDMA_C18DAR   volatile.Register32 // 0x4DC
	MDMA_C18BRUR  volatile.Register32 // 0x4E0
	MDMA_C18LAR   volatile.Register32 // 0x4E4
	MDMA_C18TBR   volatile.Register32 // 0x4E8
	_             [4]byte
	MDMA_C18MAR   volatile.Register32 // 0x4F0
	MDMA_C18MDR   volatile.Register32 // 0x4F4
	_             [8]byte
	MDMA_C19ISR   volatile.Register32 // 0x500
	MDMA_C19IFCR  volatile.Register32 // 0x504
	MDMA_C19ESR   volatile.Register32 // 0x508
	MDMA_C19CR    volatile.Register32 // 0x50C
	MDMA_C19TCR   volatile.Register32 // 0x510
	MDMA_C19BNDTR volatile.Register32 // 0x514
	MDMA_C19SAR   volatile.Register32 // 0x518
	MDMA_C19DAR   volatile.Register32 // 0x51C
	MDMA_C19BRUR  volatile.Register32 // 0x520
	MDMA_C19LAR   volatile.Register32 // 0x524
	MDMA_C19TBR   volatile.Register32 // 0x528
	_             [4]byte
	MDMA_C19MAR   volatile.Register32 // 0x530
	MDMA_C19MDR   volatile.Register32 // 0x534
	_             [8]byte
	MDMA_C20ISR   volatile.Register32 // 0x540
	MDMA_C20IFCR  volatile.Register32 // 0x544
	MDMA_C20ESR   volatile.Register32 // 0x548
	MDMA_C20CR    volatile.Register32 // 0x54C
	MDMA_C20TCR   volatile.Register32 // 0x550
	MDMA_C20BNDTR volatile.Register32 // 0x554
	MDMA_C20SAR   volatile.Register32 // 0x558
	MDMA_C20DAR   volatile.Register32 // 0x55C
	MDMA_C20BRUR  volatile.Register32 // 0x560
	MDMA_C20LAR   volatile.Register32 // 0x564
	MDMA_C20TBR   volatile.Register32 // 0x568
	_             [4]byte
	MDMA_C20MAR   volatile.Register32 // 0x570
	MDMA_C20MDR   volatile.Register32 // 0x574
	_             [8]byte
	MDMA_C21ISR   volatile.Register32 // 0x580
	MDMA_C21IFCR  volatile.Register32 // 0x584
	MDMA_C21ESR   volatile.Register32 // 0x588
	MDMA_C21CR    volatile.Register32 // 0x58C
	MDMA_C21TCR   volatile.Register32 // 0x590
	MDMA_C21BNDTR volatile.Register32 // 0x594
	MDMA_C21SAR   volatile.Register32 // 0x598
	MDMA_C21DAR   volatile.Register32 // 0x59C
	MDMA_C21BRUR  volatile.Register32 // 0x5A0
	MDMA_C21LAR   volatile.Register32 // 0x5A4
	MDMA_C21TBR   volatile.Register32 // 0x5A8
	_             [4]byte
	MDMA_C21MAR   volatile.Register32 // 0x5B0
	MDMA_C21MDR   volatile.Register32 // 0x5B4
	_             [8]byte
	MDMA_C22ISR   volatile.Register32 // 0x5C0
	MDMA_C22IFCR  volatile.Register32 // 0x5C4
	MDMA_C22ESR   volatile.Register32 // 0x5C8
	MDMA_C22CR    volatile.Register32 // 0x5CC
	MDMA_C22TCR   volatile.Register32 // 0x5D0
	MDMA_C22BNDTR volatile.Register32 // 0x5D4
	MDMA_C22SAR   volatile.Register32 // 0x5D8
	MDMA_C22DAR   volatile.Register32 // 0x5DC
	MDMA_C22BRUR  volatile.Register32 // 0x5E0
	MDMA_C22LAR   volatile.Register32 // 0x5E4
	MDMA_C22TBR   volatile.Register32 // 0x5E8
	_             [4]byte
	MDMA_C22MAR   volatile.Register32 // 0x5F0
	MDMA_C22MDR   volatile.Register32 // 0x5F4
	_             [8]byte
	MDMA_C23ISR   volatile.Register32 // 0x600
	MDMA_C23IFCR  volatile.Register32 // 0x604
	MDMA_C23ESR   volatile.Register32 // 0x608
	MDMA_C23CR    volatile.Register32 // 0x60C
	MDMA_C23TCR   volatile.Register32 // 0x610
	MDMA_C23BNDTR volatile.Register32 // 0x614
	MDMA_C23SAR   volatile.Register32 // 0x618
	MDMA_C23DAR   volatile.Register32 // 0x61C
	MDMA_C23BRUR  volatile.Register32 // 0x620
	MDMA_C23LAR   volatile.Register32 // 0x624
	MDMA_C23TBR   volatile.Register32 // 0x628
	_             [4]byte
	MDMA_C23MAR   volatile.Register32 // 0x630
	MDMA_C23MDR   volatile.Register32 // 0x634
	_             [8]byte
	MDMA_C24ISR   volatile.Register32 // 0x640
	MDMA_C24IFCR  volatile.Register32 // 0x644
	MDMA_C24ESR   volatile.Register32 // 0x648
	MDMA_C24CR    volatile.Register32 // 0x64C
	MDMA_C24TCR   volatile.Register32 // 0x650
	MDMA_C24BNDTR volatile.Register32 // 0x654
	MDMA_C24SAR   volatile.Register32 // 0x658
	MDMA_C24DAR   volatile.Register32 // 0x65C
	MDMA_C24BRUR  volatile.Register32 // 0x660
	MDMA_C24LAR   volatile.Register32 // 0x664
	MDMA_C24TBR   volatile.Register32 // 0x668
	_             [4]byte
	MDMA_C24MAR   volatile.Register32 // 0x670
	MDMA_C24MDR   volatile.Register32 // 0x674
	_             [8]byte
	MDMA_C25ISR   volatile.Register32 // 0x680
	MDMA_C25IFCR  volatile.Register32 // 0x684
	MDMA_C25ESR   volatile.Register32 // 0x688
	MDMA_C25CR    volatile.Register32 // 0x68C
	MDMA_C25TCR   volatile.Register32 // 0x690
	MDMA_C25BNDTR volatile.Register32 // 0x694
	MDMA_C25SAR   volatile.Register32 // 0x698
	MDMA_C25DAR   volatile.Register32 // 0x69C
	MDMA_C25BRUR  volatile.Register32 // 0x6A0
	MDMA_C25LAR   volatile.Register32 // 0x6A4
	MDMA_C25TBR   volatile.Register32 // 0x6A8
	_             [4]byte
	MDMA_C25MAR   volatile.Register32 // 0x6B0
	MDMA_C25MDR   volatile.Register32 // 0x6B4
	_             [8]byte
	MDMA_C26ISR   volatile.Register32 // 0x6C0
	MDMA_C26IFCR  volatile.Register32 // 0x6C4
	MDMA_C26ESR   volatile.Register32 // 0x6C8
	MDMA_C26CR    volatile.Register32 // 0x6CC
	MDMA_C26TCR   volatile.Register32 // 0x6D0
	MDMA_C26BNDTR volatile.Register32 // 0x6D4
	MDMA_C26SAR   volatile.Register32 // 0x6D8
	MDMA_C26DAR   volatile.Register32 // 0x6DC
	MDMA_C26BRUR  volatile.Register32 // 0x6E0
	MDMA_C26LAR   volatile.Register32 // 0x6E4
	MDMA_C26TBR   volatile.Register32 // 0x6E8
	_             [4]byte
	MDMA_C26MAR   volatile.Register32 // 0x6F0
	MDMA_C26MDR   volatile.Register32 // 0x6F4
	_             [8]byte
	MDMA_C27ISR   volatile.Register32 // 0x700
	MDMA_C27IFCR  volatile.Register32 // 0x704
	MDMA_C27ESR   volatile.Register32 // 0x708
	MDMA_C27CR    volatile.Register32 // 0x70C
	MDMA_C27TCR   volatile.Register32 // 0x710
	MDMA_C27BNDTR volatile.Register32 // 0x714
	MDMA_C27SAR   volatile.Register32 // 0x718
	MDMA_C27DAR   volatile.Register32 // 0x71C
	MDMA_C27BRUR  volatile.Register32 // 0x720
	MDMA_C27LAR   volatile.Register32 // 0x724
	MDMA_C27TBR   volatile.Register32 // 0x728
	_             [4]byte
	MDMA_C27MAR   volatile.Register32 // 0x730
	MDMA_C27MDR   volatile.Register32 // 0x734
	_             [8]byte
	MDMA_C28ISR   volatile.Register32 // 0x740
	MDMA_C28IFCR  volatile.Register32 // 0x744
	MDMA_C28ESR   volatile.Register32 // 0x748
	MDMA_C28CR    volatile.Register32 // 0x74C
	MDMA_C28TCR   volatile.Register32 // 0x750
	MDMA_C28BNDTR volatile.Register32 // 0x754
	MDMA_C28SAR   volatile.Register32 // 0x758
	MDMA_C28DAR   volatile.Register32 // 0x75C
	MDMA_C28BRUR  volatile.Register32 // 0x760
	MDMA_C28LAR   volatile.Register32 // 0x764
	MDMA_C28TBR   volatile.Register32 // 0x768
	_             [4]byte
	MDMA_C28MAR   volatile.Register32 // 0x770
	MDMA_C28MDR   volatile.Register32 // 0x774
	_             [8]byte
	MDMA_C29ISR   volatile.Register32 // 0x780
	MDMA_C29IFCR  volatile.Register32 // 0x784
	MDMA_C29ESR   volatile.Register32 // 0x788
	MDMA_C29CR    volatile.Register32 // 0x78C
	MDMA_C29TCR   volatile.Register32 // 0x790
	MDMA_C29BNDTR volatile.Register32 // 0x794
	MDMA_C29SAR   volatile.Register32 // 0x798
	MDMA_C29DAR   volatile.Register32 // 0x79C
	MDMA_C29BRUR  volatile.Register32 // 0x7A0
	MDMA_C29LAR   volatile.Register32 // 0x7A4
	MDMA_C29TBR   volatile.Register32 // 0x7A8
	_             [4]byte
	MDMA_C29MAR   volatile.Register32 // 0x7B0
	MDMA_C29MDR   volatile.Register32 // 0x7B4
	_             [8]byte
	MDMA_C30ISR   volatile.Register32 // 0x7C0
	MDMA_C30IFCR  volatile.Register32 // 0x7C4
	MDMA_C30ESR   volatile.Register32 // 0x7C8
	MDMA_C30CR    volatile.Register32 // 0x7CC
	MDMA_C30TCR   volatile.Register32 // 0x7D0
	MDMA_C30BNDTR volatile.Register32 // 0x7D4
	MDMA_C30SAR   volatile.Register32 // 0x7D8
	MDMA_C30DAR   volatile.Register32 // 0x7DC
	MDMA_C30BRUR  volatile.Register32 // 0x7E0
	MDMA_C30LAR   volatile.Register32 // 0x7E4
	MDMA_C30TBR   volatile.Register32 // 0x7E8
	_             [4]byte
	MDMA_C30MAR   volatile.Register32 // 0x7F0
	MDMA_C30MDR   volatile.Register32 // 0x7F4
	_             [8]byte
	MDMA_C31ISR   volatile.Register32 // 0x800
	MDMA_C31IFCR  volatile.Register32 // 0x804
	MDMA_C31ESR   volatile.Register32 // 0x808
	MDMA_C31CR    volatile.Register32 // 0x80C
	MDMA_C31TCR   volatile.Register32 // 0x810
	MDMA_C31BNDTR volatile.Register32 // 0x814
	MDMA_C31SAR   volatile.Register32 // 0x818
	MDMA_C31DAR   volatile.Register32 // 0x81C
	MDMA_C31BRUR  volatile.Register32 // 0x820
	MDMA_C31LAR   volatile.Register32 // 0x824
	MDMA_C31TBR   volatile.Register32 // 0x828
	_             [4]byte
	MDMA_C31MAR   volatile.Register32 // 0x830
	MDMA_C31MDR   volatile.Register32 // 0x834
}

// Nested Vectored Interrupt Controller
type NVIC_Type struct {
	ISER0 volatile.Register32 // 0x0
	ISER1 volatile.Register32 // 0x4
	ISER2 volatile.Register32 // 0x8
	ISER3 volatile.Register32 // 0xC
	ISER4 volatile.Register32 // 0x10
	_     [108]byte
	ICER0 volatile.Register32 // 0x80
	ICER1 volatile.Register32 // 0x84
	ICER2 volatile.Register32 // 0x88
	ICER3 volatile.Register32 // 0x8C
	ICER4 volatile.Register32 // 0x90
	_     [108]byte
	ISPR0 volatile.Register32 // 0x100
	ISPR1 volatile.Register32 // 0x104
	ISPR2 volatile.Register32 // 0x108
	ISPR3 volatile.Register32 // 0x10C
	ISPR4 volatile.Register32 // 0x110
	_     [108]byte
	ICPR0 volatile.Register32 // 0x180
	ICPR1 volatile.Register32 // 0x184
	ICPR2 volatile.Register32 // 0x188
	ICPR3 volatile.Register32 // 0x18C
	_     [52]byte
	ICPR4 volatile.Register32 // 0x1C4
	_     [56]byte
	IABR0 volatile.Register32 // 0x200
	IABR1 volatile.Register32 // 0x204
	IABR2 volatile.Register32 // 0x208
	IABR3 volatile.Register32 // 0x20C
	IABR4 volatile.Register32 // 0x210
	_     [236]byte
	IPR0  volatile.Register32 // 0x300
	IPR1  volatile.Register32 // 0x304
	IPR2  volatile.Register32 // 0x308
	IPR3  volatile.Register32 // 0x30C
	IPR4  volatile.Register32 // 0x310
	IPR5  volatile.Register32 // 0x314
	IPR6  volatile.Register32 // 0x318
	IPR7  volatile.Register32 // 0x31C
	IPR8  volatile.Register32 // 0x320
	IPR9  volatile.Register32 // 0x324
	IPR10 volatile.Register32 // 0x328
	IPR11 volatile.Register32 // 0x32C
	IPR12 volatile.Register32 // 0x330
	IPR13 volatile.Register32 // 0x334
	IPR14 volatile.Register32 // 0x338
	IPR15 volatile.Register32 // 0x33C
	IPR16 volatile.Register32 // 0x340
	IPR17 volatile.Register32 // 0x344
	IPR18 volatile.Register32 // 0x348
	IPR19 volatile.Register32 // 0x34C
	IPR20 volatile.Register32 // 0x350
	IPR21 volatile.Register32 // 0x354
	IPR22 volatile.Register32 // 0x358
	IPR23 volatile.Register32 // 0x35C
	IPR24 volatile.Register32 // 0x360
	IPR25 volatile.Register32 // 0x364
	IPR26 volatile.Register32 // 0x368
	IPR27 volatile.Register32 // 0x36C
	IPR28 volatile.Register32 // 0x370
	IPR29 volatile.Register32 // 0x374
	IPR30 volatile.Register32 // 0x378
	IPR31 volatile.Register32 // 0x37C
	IPR32 volatile.Register32 // 0x380
	IPR33 volatile.Register32 // 0x384
	IPR34 volatile.Register32 // 0x388
	IPR35 volatile.Register32 // 0x38C
	IPR36 volatile.Register32 // 0x390
	IPR37 volatile.Register32 // 0x394
	IPR38 volatile.Register32 // 0x398
}

// OTG
type OTG_Type struct {
	OTG_GOTGCTL         volatile.Register32 // 0x0
	OTG_GOTGINT         volatile.Register32 // 0x4
	OTG_GAHBCFG         volatile.Register32 // 0x8
	OTG_GUSBCFG         volatile.Register32 // 0xC
	OTG_GRSTCTL         volatile.Register32 // 0x10
	OTG_GINTSTS         volatile.Register32 // 0x14
	OTG_GINTMSK         volatile.Register32 // 0x18
	OTG_GRXSTSR         volatile.Register32 // 0x1C
	OTG_GRXSTSP         volatile.Register32 // 0x20
	OTG_GRXFSIZ         volatile.Register32 // 0x24
	OTG_HNPTXFSIZ       volatile.Register32 // 0x28
	OTG_HNPTXSTS        volatile.Register32 // 0x2C
	_                   [8]byte
	OTG_GCCFG           volatile.Register32 // 0x38
	OTG_CID             volatile.Register32 // 0x3C
	_                   [20]byte
	OTG_GLPMCFG         volatile.Register32 // 0x54
	_                   [168]byte
	OTG_HPTXFSIZ        volatile.Register32 // 0x100
	OTG_DIEPTXF1        volatile.Register32 // 0x104
	OTG_DIEPTXF2        volatile.Register32 // 0x108
	OTG_DIEPTXF3        volatile.Register32 // 0x10C
	OTG_DIEPTXF4        volatile.Register32 // 0x110
	OTG_DIEPTXF5        volatile.Register32 // 0x114
	OTG_DIEPTXF6        volatile.Register32 // 0x118
	OTG_DIEPTXF7        volatile.Register32 // 0x11C
	OTG_DIEPTXF8        volatile.Register32 // 0x120
	_                   [732]byte
	OTG_HCFG            volatile.Register32 // 0x400
	OTG_HFIR            volatile.Register32 // 0x404
	OTG_HFNUM           volatile.Register32 // 0x408
	_                   [4]byte
	OTG_HPTXSTS         volatile.Register32 // 0x410
	OTG_HAINT           volatile.Register32 // 0x414
	OTG_HAINTMSK        volatile.Register32 // 0x418
	OTG_HFLBADDR        volatile.Register32 // 0x41C
	_                   [32]byte
	OTG_HPRT            volatile.Register32 // 0x440
	_                   [188]byte
	OTG_HCCHAR0         volatile.Register32 // 0x500
	OTG_HCSPLT0         volatile.Register32 // 0x504
	OTG_HCINT0          volatile.Register32 // 0x508
	OTG_HCINTMSK0       volatile.Register32 // 0x50C
	OTG_HCTSIZ0         volatile.Register32 // 0x510
	OTG_HCDMA0          volatile.Register32 // 0x514
	_                   [4]byte
	OTG_HCDMAB0         volatile.Register32 // 0x51C
	OTG_HCCHAR1         volatile.Register32 // 0x520
	OTG_HCSPLT1         volatile.Register32 // 0x524
	OTG_HCINT1          volatile.Register32 // 0x528
	OTG_HCINTMSK1       volatile.Register32 // 0x52C
	OTG_HCTSIZ1         volatile.Register32 // 0x530
	OTG_HCDMA1          volatile.Register32 // 0x534
	_                   [4]byte
	OTG_HCDMAB1         volatile.Register32 // 0x53C
	OTG_HCCHAR2         volatile.Register32 // 0x540
	OTG_HCSPLT2         volatile.Register32 // 0x544
	OTG_HCINT2          volatile.Register32 // 0x548
	OTG_HCINTMSK2       volatile.Register32 // 0x54C
	OTG_HCTSIZ2         volatile.Register32 // 0x550
	OTG_HCDMA2          volatile.Register32 // 0x554
	_                   [4]byte
	OTG_HCDMAB2         volatile.Register32 // 0x55C
	OTG_HCCHAR3         volatile.Register32 // 0x560
	OTG_HCSPLT3         volatile.Register32 // 0x564
	OTG_HCINT3          volatile.Register32 // 0x568
	OTG_HCINTMSK3       volatile.Register32 // 0x56C
	OTG_HCTSIZ3         volatile.Register32 // 0x570
	OTG_HCDMA3          volatile.Register32 // 0x574
	_                   [4]byte
	OTG_HCDMAB3         volatile.Register32 // 0x57C
	OTG_HCCHAR4         volatile.Register32 // 0x580
	OTG_HCSPLT4         volatile.Register32 // 0x584
	OTG_HCINT4          volatile.Register32 // 0x588
	OTG_HCINTMSK4       volatile.Register32 // 0x58C
	OTG_HCTSIZ4         volatile.Register32 // 0x590
	OTG_HCDMA4          volatile.Register32 // 0x594
	_                   [4]byte
	OTG_HCDMAB4         volatile.Register32 // 0x59C
	OTG_HCCHAR5         volatile.Register32 // 0x5A0
	OTG_HCSPLT5         volatile.Register32 // 0x5A4
	OTG_HCINT5          volatile.Register32 // 0x5A8
	OTG_HCINTMSK5       volatile.Register32 // 0x5AC
	OTG_HCTSIZ5         volatile.Register32 // 0x5B0
	OTG_HCDMA5          volatile.Register32 // 0x5B4
	_                   [4]byte
	OTG_HCDMAB5         volatile.Register32 // 0x5BC
	OTG_HCCHAR6         volatile.Register32 // 0x5C0
	OTG_HCSPLT6         volatile.Register32 // 0x5C4
	OTG_HCINT6          volatile.Register32 // 0x5C8
	OTG_HCINTMSK6       volatile.Register32 // 0x5CC
	OTG_HCTSIZ6         volatile.Register32 // 0x5D0
	OTG_HCDMA6          volatile.Register32 // 0x5D4
	_                   [4]byte
	OTG_HCDMAB6         volatile.Register32 // 0x5DC
	OTG_HCCHAR7         volatile.Register32 // 0x5E0
	OTG_HCSPLT7         volatile.Register32 // 0x5E4
	OTG_HCINT7          volatile.Register32 // 0x5E8
	OTG_HCINTMSK7       volatile.Register32 // 0x5EC
	OTG_HCTSIZ7         volatile.Register32 // 0x5F0
	OTG_HCDMA7          volatile.Register32 // 0x5F4
	_                   [4]byte
	OTG_HCDMAB7         volatile.Register32 // 0x5FC
	OTG_HCCHAR8         volatile.Register32 // 0x600
	OTG_HCSPLT8         volatile.Register32 // 0x604
	OTG_HCINT8          volatile.Register32 // 0x608
	OTG_HCINTMSK8       volatile.Register32 // 0x60C
	OTG_HCTSIZ8         volatile.Register32 // 0x610
	OTG_HCDMA8          volatile.Register32 // 0x614
	_                   [4]byte
	OTG_HCDMAB8         volatile.Register32 // 0x61C
	OTG_HCCHAR9         volatile.Register32 // 0x620
	OTG_HCSPLT9         volatile.Register32 // 0x624
	OTG_HCINT9          volatile.Register32 // 0x628
	OTG_HCINTMSK9       volatile.Register32 // 0x62C
	OTG_HCTSIZ9         volatile.Register32 // 0x630
	OTG_HCDMA9          volatile.Register32 // 0x634
	_                   [4]byte
	OTG_HCDMAB9         volatile.Register32 // 0x63C
	OTG_HCCHAR10        volatile.Register32 // 0x640
	OTG_HCSPLT10        volatile.Register32 // 0x644
	OTG_HCINT10         volatile.Register32 // 0x648
	OTG_HCINTMSK10      volatile.Register32 // 0x64C
	OTG_HCTSIZ10        volatile.Register32 // 0x650
	OTG_HCDMA10         volatile.Register32 // 0x654
	_                   [4]byte
	OTG_HCDMAB10        volatile.Register32 // 0x65C
	OTG_HCCHAR11        volatile.Register32 // 0x660
	OTG_HCSPLT11        volatile.Register32 // 0x664
	OTG_HCINT11         volatile.Register32 // 0x668
	OTG_HCINTMSK11      volatile.Register32 // 0x66C
	OTG_HCTSIZ11        volatile.Register32 // 0x670
	OTG_HCDMA11         volatile.Register32 // 0x674
	_                   [4]byte
	OTG_HCDMAB11        volatile.Register32 // 0x67C
	OTG_HCCHAR12        volatile.Register32 // 0x680
	OTG_HCSPLT12        volatile.Register32 // 0x684
	OTG_HCINT12         volatile.Register32 // 0x688
	OTG_HCINTMSK12      volatile.Register32 // 0x68C
	OTG_HCTSIZ12        volatile.Register32 // 0x690
	OTG_HCDMA12         volatile.Register32 // 0x694
	_                   [4]byte
	OTG_HCDMAB12        volatile.Register32 // 0x69C
	OTG_HCCHAR13        volatile.Register32 // 0x6A0
	OTG_HCSPLT13        volatile.Register32 // 0x6A4
	OTG_HCINT13         volatile.Register32 // 0x6A8
	OTG_HCINTMSK13      volatile.Register32 // 0x6AC
	OTG_HCTSIZ13        volatile.Register32 // 0x6B0
	OTG_HCDMA13         volatile.Register32 // 0x6B4
	_                   [4]byte
	OTG_HCDMAB13        volatile.Register32 // 0x6BC
	OTG_HCCHAR14        volatile.Register32 // 0x6C0
	OTG_HCSPLT14        volatile.Register32 // 0x6C4
	OTG_HCINT14         volatile.Register32 // 0x6C8
	OTG_HCINTMSK14      volatile.Register32 // 0x6CC
	OTG_HCTSIZ14        volatile.Register32 // 0x6D0
	OTG_HCDMA14         volatile.Register32 // 0x6D4
	_                   [4]byte
	OTG_HCDMAB14        volatile.Register32 // 0x6DC
	OTG_HCCHAR15        volatile.Register32 // 0x6E0
	OTG_HCSPLT15        volatile.Register32 // 0x6E4
	OTG_HCINT15         volatile.Register32 // 0x6E8
	OTG_HCINTMSK15      volatile.Register32 // 0x6EC
	OTG_HCTSIZ15        volatile.Register32 // 0x6F0
	OTG_HCDMA15         volatile.Register32 // 0x6F4
	_                   [4]byte
	OTG_HCDMAB15        volatile.Register32 // 0x6FC
	_                   [256]byte
	OTG_DCFG            volatile.Register32 // 0x800
	OTG_DCTL            volatile.Register32 // 0x804
	OTG_DSTS            volatile.Register32 // 0x808
	_                   [4]byte
	OTG_DIEPMSK         volatile.Register32 // 0x810
	OTG_DOEPMSK         volatile.Register32 // 0x814
	OTG_DAINT           volatile.Register32 // 0x818
	OTG_DAINTMSK        volatile.Register32 // 0x81C
	_                   [8]byte
	OTG_DVBUSDIS        volatile.Register32 // 0x828
	OTG_DVBUSPULSE      volatile.Register32 // 0x82C
	OTG_DTHRCTL         volatile.Register32 // 0x830
	OTG_DIEPEMPMSK      volatile.Register32 // 0x834
	OTG_DEACHINT        volatile.Register32 // 0x838
	OTG_DEACHINTMSK     volatile.Register32 // 0x83C
	_                   [4]byte
	OTG_HS_DIEPEACHMSK1 volatile.Register32 // 0x844
	_                   [60]byte
	OTG_HS_DOEPEACHMSK1 volatile.Register32 // 0x884
	_                   [120]byte
	OTG_DIEPCTL0        volatile.Register32 // 0x900
	_                   [4]byte
	OTG_DIEPINT0        volatile.Register32 // 0x908
	_                   [4]byte
	OTG_DIEPTSIZ0       volatile.Register32 // 0x910
	OTG_DIEPDMA0        volatile.Register32 // 0x914
	OTG_DTXFSTS0        volatile.Register32 // 0x918
	_                   [4]byte
	OTG_DIEPCTL1        volatile.Register32 // 0x920
	_                   [4]byte
	OTG_DIEPINT1        volatile.Register32 // 0x928
	_                   [4]byte
	OTG_DIEPTSIZ1       volatile.Register32 // 0x930
	OTG_DIEPDMA1        volatile.Register32 // 0x934
	OTG_DTXFSTS1        volatile.Register32 // 0x938
	_                   [4]byte
	OTG_DIEPCTL2        volatile.Register32 // 0x940
	_                   [4]byte
	OTG_DIEPINT2        volatile.Register32 // 0x948
	_                   [4]byte
	OTG_DIEPTSIZ2       volatile.Register32 // 0x950
	OTG_DIEPDMA2        volatile.Register32 // 0x954
	OTG_DTXFSTS2        volatile.Register32 // 0x958
	_                   [4]byte
	OTG_DIEPCTL3        volatile.Register32 // 0x960
	_                   [4]byte
	OTG_DIEPINT3        volatile.Register32 // 0x968
	_                   [4]byte
	OTG_DIEPTSIZ3       volatile.Register32 // 0x970
	OTG_DIEPDMA3        volatile.Register32 // 0x974
	OTG_DTXFSTS3        volatile.Register32 // 0x978
	_                   [4]byte
	OTG_DIEPCTL4        volatile.Register32 // 0x980
	_                   [4]byte
	OTG_DIEPINT4        volatile.Register32 // 0x988
	_                   [4]byte
	OTG_DIEPTSIZ4       volatile.Register32 // 0x990
	OTG_DIEPDMA4        volatile.Register32 // 0x994
	OTG_DTXFSTS4        volatile.Register32 // 0x998
	_                   [4]byte
	OTG_DIEPCTL5        volatile.Register32 // 0x9A0
	_                   [4]byte
	OTG_DIEPINT5        volatile.Register32 // 0x9A8
	_                   [4]byte
	OTG_DIEPTSIZ5       volatile.Register32 // 0x9B0
	OTG_DIEPDMA5        volatile.Register32 // 0x9B4
	OTG_DTXFSTS5        volatile.Register32 // 0x9B8
	_                   [4]byte
	OTG_DIEPCTL6        volatile.Register32 // 0x9C0
	_                   [4]byte
	OTG_DIEPINT6        volatile.Register32 // 0x9C8
	_                   [4]byte
	OTG_DIEPTSIZ6       volatile.Register32 // 0x9D0
	OTG_DIEPDMA6        volatile.Register32 // 0x9D4
	OTG_DTXFSTS6        volatile.Register32 // 0x9D8
	_                   [4]byte
	OTG_DIEPCTL7        volatile.Register32 // 0x9E0
	_                   [4]byte
	OTG_DIEPINT7        volatile.Register32 // 0x9E8
	_                   [4]byte
	OTG_DIEPTSIZ7       volatile.Register32 // 0x9F0
	OTG_DIEPDMA7        volatile.Register32 // 0x9F4
	OTG_DTXFSTS7        volatile.Register32 // 0x9F8
	_                   [4]byte
	OTG_DIEPCTL8        volatile.Register32 // 0xA00
	_                   [4]byte
	OTG_DIEPINT8        volatile.Register32 // 0xA08
	_                   [4]byte
	OTG_DIEPTSIZ8       volatile.Register32 // 0xA10
	OTG_DIEPDMA8        volatile.Register32 // 0xA14
	OTG_DTXFSTS8        volatile.Register32 // 0xA18
	_                   [228]byte
	OTG_DOEPCTL0        volatile.Register32 // 0xB00
	_                   [4]byte
	OTG_DOEPINT0        volatile.Register32 // 0xB08
	_                   [4]byte
	OTG_DOEPTSIZ0       volatile.Register32 // 0xB10
	OTG_DOEPDMA0        volatile.Register32 // 0xB14
	_                   [8]byte
	OTG_DOEPCTL1        volatile.Register32 // 0xB20
	_                   [4]byte
	OTG_DOEPINT1        volatile.Register32 // 0xB28
	_                   [4]byte
	OTG_DOEPTSIZ1       volatile.Register32 // 0xB30
	OTG_DOEPDMA1        volatile.Register32 // 0xB34
	_                   [8]byte
	OTG_DOEPCTL2        volatile.Register32 // 0xB40
	_                   [4]byte
	OTG_DOEPINT2        volatile.Register32 // 0xB48
	_                   [4]byte
	OTG_DOEPTSIZ2       volatile.Register32 // 0xB50
	OTG_DOEPDMA2        volatile.Register32 // 0xB54
	_                   [8]byte
	OTG_DOEPCTL3        volatile.Register32 // 0xB60
	_                   [4]byte
	OTG_DOEPINT3        volatile.Register32 // 0xB68
	_                   [4]byte
	OTG_DOEPTSIZ3       volatile.Register32 // 0xB70
	OTG_DOEPDMA3        volatile.Register32 // 0xB74
	_                   [8]byte
	OTG_DOEPCTL4        volatile.Register32 // 0xB80
	_                   [4]byte
	OTG_DOEPINT4        volatile.Register32 // 0xB88
	_                   [4]byte
	OTG_DOEPTSIZ4       volatile.Register32 // 0xB90
	OTG_DOEPDMA4        volatile.Register32 // 0xB94
	_                   [8]byte
	OTG_DOEPCTL5        volatile.Register32 // 0xBA0
	_                   [4]byte
	OTG_DOEPINT5        volatile.Register32 // 0xBA8
	_                   [4]byte
	OTG_DOEPTSIZ5       volatile.Register32 // 0xBB0
	OTG_DOEPDMA5        volatile.Register32 // 0xBB4
	_                   [8]byte
	OTG_DOEPCTL6        volatile.Register32 // 0xBC0
	_                   [4]byte
	OTG_DOEPINT6        volatile.Register32 // 0xBC8
	_                   [4]byte
	OTG_DOEPTSIZ6       volatile.Register32 // 0xBD0
	OTG_DOEPDMA6        volatile.Register32 // 0xBD4
	_                   [8]byte
	OTG_DOEPCTL7        volatile.Register32 // 0xBE0
	_                   [4]byte
	OTG_DOEPINT7        volatile.Register32 // 0xBE8
	_                   [4]byte
	OTG_DOEPTSIZ7       volatile.Register32 // 0xBF0
	OTG_DOEPDMA7        volatile.Register32 // 0xBF4
	_                   [8]byte
	OTG_DOEPCTL8        volatile.Register32 // 0xC00
	_                   [4]byte
	OTG_DOEPINT8        volatile.Register32 // 0xC08
	_                   [4]byte
	OTG_DOEPTSIZ8       volatile.Register32 // 0xC10
	OTG_DOEPDMA8        volatile.Register32 // 0xC14
	_                   [488]byte
	OTG_PCGCCTL         volatile.Register32 // 0xE00
}

// PWR
type PWR_Type struct {
	PWR_CR1        volatile.Register32 // 0x0
	PWR_CSR1       volatile.Register32 // 0x4
	PWR_CR2        volatile.Register32 // 0x8
	PWR_CR3        volatile.Register32 // 0xC
	PWR_MPUCR      volatile.Register32 // 0x10
	PWR_MCUCR      volatile.Register32 // 0x14
	_              [8]byte
	PWR_WKUPCR     volatile.Register32 // 0x20
	PWR_WKUPFR     volatile.Register32 // 0x24
	PWR_MPUWKUPENR volatile.Register32 // 0x28
	PWR_MCUWKUPENR volatile.Register32 // 0x2C
	_              [964]byte
	PWR_VER        volatile.Register32 // 0x3F4
	PWR_ID         volatile.Register32 // 0x3F8
	PWR_SID        volatile.Register32 // 0x3FC
}

// QUADSPI1
type QUADSPI1_Type struct {
	QUADSPI_CR     volatile.Register32 // 0x0
	QUADSPI_DCR    volatile.Register32 // 0x4
	QUADSPI_SR     volatile.Register32 // 0x8
	QUADSPI_FCR    volatile.Register32 // 0xC
	QUADSPI_DLR    volatile.Register32 // 0x10
	QUADSPI_CCR    volatile.Register32 // 0x14
	QUADSPI_AR     volatile.Register32 // 0x18
	QUADSPI_ABR    volatile.Register32 // 0x1C
	QUADSPI_DR     volatile.Register32 // 0x20
	QUADSPI_PSMKR  volatile.Register32 // 0x24
	QUADSPI_PSMAR  volatile.Register32 // 0x28
	QUADSPI_PIR    volatile.Register32 // 0x2C
	QUADSPI_LPTR   volatile.Register32 // 0x30
	_              [956]byte
	QUADSPI_HWCFGR volatile.Register32 // 0x3F0
	QUADSPI_VERR   volatile.Register32 // 0x3F4
	QUADSPI_IPIDR  volatile.Register32 // 0x3F8
	QUADSPI_SIDR   volatile.Register32 // 0x3FC
}

// RCC
type RCC_Type struct {
	RCC_TZCR              volatile.Register32 // 0x0
	_                     [8]byte
	RCC_OCENSETR          volatile.Register32 // 0xC
	RCC_OCENCLRR          volatile.Register32 // 0x10
	_                     [4]byte
	RCC_HSICFGR           volatile.Register32 // 0x18
	RCC_CSICFGR           volatile.Register32 // 0x1C
	RCC_MPCKSELR          volatile.Register32 // 0x20
	RCC_ASSCKSELR         volatile.Register32 // 0x24
	RCC_RCK12SELR         volatile.Register32 // 0x28
	RCC_MPCKDIVR          volatile.Register32 // 0x2C
	RCC_AXIDIVR           volatile.Register32 // 0x30
	_                     [8]byte
	RCC_APB4DIVR          volatile.Register32 // 0x3C
	RCC_APB5DIVR          volatile.Register32 // 0x40
	RCC_RTCDIVR           volatile.Register32 // 0x44
	RCC_MSSCKSELR         volatile.Register32 // 0x48
	_                     [52]byte
	RCC_PLL1CR            volatile.Register32 // 0x80
	RCC_PLL1CFGR1         volatile.Register32 // 0x84
	RCC_PLL1CFGR2         volatile.Register32 // 0x88
	RCC_PLL1FRACR         volatile.Register32 // 0x8C
	RCC_PLL1CSGR          volatile.Register32 // 0x90
	RCC_PLL2CR            volatile.Register32 // 0x94
	RCC_PLL2CFGR1         volatile.Register32 // 0x98
	RCC_PLL2CFGR2         volatile.Register32 // 0x9C
	RCC_PLL2FRACR         volatile.Register32 // 0xA0
	RCC_PLL2CSGR          volatile.Register32 // 0xA4
	_                     [24]byte
	RCC_I2C46CKSELR       volatile.Register32 // 0xC0
	RCC_SPI6CKSELR        volatile.Register32 // 0xC4
	RCC_UART1CKSELR       volatile.Register32 // 0xC8
	RCC_RNG1CKSELR        volatile.Register32 // 0xCC
	RCC_CPERCKSELR        volatile.Register32 // 0xD0
	RCC_STGENCKSELR       volatile.Register32 // 0xD4
	RCC_DDRITFCR          volatile.Register32 // 0xD8
	_                     [36]byte
	RCC_MP_BOOTCR         volatile.Register32 // 0x100
	RCC_MP_SREQSETR       volatile.Register32 // 0x104
	RCC_MP_SREQCLRR       volatile.Register32 // 0x108
	RCC_MP_GCR            volatile.Register32 // 0x10C
	RCC_MP_APRSTCR        volatile.Register32 // 0x110
	RCC_MP_APRSTSR        volatile.Register32 // 0x114
	_                     [40]byte
	RCC_BDCR              volatile.Register32 // 0x140
	RCC_RDLSICR           volatile.Register32 // 0x144
	_                     [56]byte
	RCC_APB4RSTSETR       volatile.Register32 // 0x180
	RCC_APB4RSTCLRR       volatile.Register32 // 0x184
	RCC_APB5RSTSETR       volatile.Register32 // 0x188
	RCC_APB5RSTCLRR       volatile.Register32 // 0x18C
	RCC_AHB5RSTSETR       volatile.Register32 // 0x190
	RCC_AHB5RSTCLRR       volatile.Register32 // 0x194
	RCC_AHB6RSTSETR       volatile.Register32 // 0x198
	RCC_AHB6RSTCLRR       volatile.Register32 // 0x19C
	RCC_TZAHB6RSTSETR     volatile.Register32 // 0x1A0
	RCC_TZAHB6RSTCLRR     volatile.Register32 // 0x1A4
	_                     [88]byte
	RCC_MP_APB4ENSETR     volatile.Register32 // 0x200
	RCC_MP_APB4ENCLRR     volatile.Register32 // 0x204
	RCC_MP_APB5ENSETR     volatile.Register32 // 0x208
	RCC_MP_APB5ENCLRR     volatile.Register32 // 0x20C
	RCC_MP_AHB5ENSETR     volatile.Register32 // 0x210
	RCC_MP_AHB5ENCLRR     volatile.Register32 // 0x214
	RCC_MP_AHB6ENSETR     volatile.Register32 // 0x218
	RCC_MP_AHB6ENCLRR     volatile.Register32 // 0x21C
	RCC_MP_TZAHB6ENSETR   volatile.Register32 // 0x220
	RCC_MP_TZAHB6ENCLRR   volatile.Register32 // 0x224
	_                     [88]byte
	RCC_MC_APB4ENSETR     volatile.Register32 // 0x280
	RCC_MC_APB4ENCLRR     volatile.Register32 // 0x284
	RCC_MC_APB5ENSETR     volatile.Register32 // 0x288
	RCC_MC_APB5ENCLRR     volatile.Register32 // 0x28C
	RCC_MC_AHB5ENSETR     volatile.Register32 // 0x290
	RCC_MC_AHB5ENCLRR     volatile.Register32 // 0x294
	RCC_MC_AHB6ENSETR     volatile.Register32 // 0x298
	RCC_MC_AHB6ENCLRR     volatile.Register32 // 0x29C
	_                     [96]byte
	RCC_MP_APB4LPENSETR   volatile.Register32 // 0x300
	RCC_MP_APB4LPENCLRR   volatile.Register32 // 0x304
	RCC_MP_APB5LPENSETR   volatile.Register32 // 0x308
	RCC_MP_APB5LPENCLRR   volatile.Register32 // 0x30C
	RCC_MP_AHB5LPENSETR   volatile.Register32 // 0x310
	RCC_MP_AHB5LPENCLRR   volatile.Register32 // 0x314
	RCC_MP_AHB6LPENSETR   volatile.Register32 // 0x318
	RCC_MP_AHB6LPENCLRR   volatile.Register32 // 0x31C
	RCC_MP_TZAHB6LPENSETR volatile.Register32 // 0x320
	RCC_MP_TZAHB6LPENCLRR volatile.Register32 // 0x324
	_                     [88]byte
	RCC_MC_APB4LPENSETR   volatile.Register32 // 0x380
	RCC_MC_APB4LPENCLRR   volatile.Register32 // 0x384
	RCC_MC_APB5LPENSETR   volatile.Register32 // 0x388
	RCC_MC_APB5LPENCLRR   volatile.Register32 // 0x38C
	RCC_MC_AHB5LPENSETR   volatile.Register32 // 0x390
	RCC_MC_AHB5LPENCLRR   volatile.Register32 // 0x394
	RCC_MC_AHB6LPENSETR   volatile.Register32 // 0x398
	RCC_MC_AHB6LPENCLRR   volatile.Register32 // 0x39C
	_                     [96]byte
	RCC_BR_RSTSCLRR       volatile.Register32 // 0x400
	RCC_MP_GRSTCSETR      volatile.Register32 // 0x404
	RCC_MP_RSTSCLRR       volatile.Register32 // 0x408
	RCC_MP_IWDGFZSETR     volatile.Register32 // 0x40C
	RCC_MP_IWDGFZCLRR     volatile.Register32 // 0x410
	RCC_MP_CIER           volatile.Register32 // 0x414
	RCC_MP_CIFR           volatile.Register32 // 0x418
	RCC_PWRLPDLYCR        volatile.Register32 // 0x41C
	RCC_MP_RSTSSETR       volatile.Register32 // 0x420
	_                     [988]byte
	RCC_MCO1CFGR          volatile.Register32 // 0x800
	RCC_MCO2CFGR          volatile.Register32 // 0x804
	RCC_OCRDYR            volatile.Register32 // 0x808
	RCC_DBGCFGR           volatile.Register32 // 0x80C
	_                     [16]byte
	RCC_RCK3SELR          volatile.Register32 // 0x820
	RCC_RCK4SELR          volatile.Register32 // 0x824
	RCC_TIMG1PRER         volatile.Register32 // 0x828
	RCC_TIMG2PRER         volatile.Register32 // 0x82C
	RCC_MCUDIVR           volatile.Register32 // 0x830
	RCC_APB1DIVR          volatile.Register32 // 0x834
	RCC_APB2DIVR          volatile.Register32 // 0x838
	RCC_APB3DIVR          volatile.Register32 // 0x83C
	_                     [64]byte
	RCC_PLL3CR            volatile.Register32 // 0x880
	RCC_PLL3CFGR1         volatile.Register32 // 0x884
	RCC_PLL3CFGR2         volatile.Register32 // 0x888
	RCC_PLL3FRACR         volatile.Register32 // 0x88C
	RCC_PLL3CSGR          volatile.Register32 // 0x890
	RCC_PLL4CR            volatile.Register32 // 0x894
	RCC_PLL4CFGR1         volatile.Register32 // 0x898
	RCC_PLL4CFGR2         volatile.Register32 // 0x89C
	RCC_PLL4FRACR         volatile.Register32 // 0x8A0
	RCC_PLL4CSGR          volatile.Register32 // 0x8A4
	_                     [24]byte
	RCC_I2C12CKSELR       volatile.Register32 // 0x8C0
	RCC_I2C35CKSELR       volatile.Register32 // 0x8C4
	RCC_SAI1CKSELR        volatile.Register32 // 0x8C8
	RCC_SAI2CKSELR        volatile.Register32 // 0x8CC
	RCC_SAI3CKSELR        volatile.Register32 // 0x8D0
	RCC_SAI4CKSELR        volatile.Register32 // 0x8D4
	RCC_SPI2S1CKSELR      volatile.Register32 // 0x8D8
	RCC_SPI2S23CKSELR     volatile.Register32 // 0x8DC
	RCC_SPI45CKSELR       volatile.Register32 // 0x8E0
	RCC_UART6CKSELR       volatile.Register32 // 0x8E4
	RCC_UART24CKSELR      volatile.Register32 // 0x8E8
	RCC_UART35CKSELR      volatile.Register32 // 0x8EC
	RCC_UART78CKSELR      volatile.Register32 // 0x8F0
	RCC_SDMMC12CKSELR     volatile.Register32 // 0x8F4
	RCC_SDMMC3CKSELR      volatile.Register32 // 0x8F8
	RCC_ETHCKSELR         volatile.Register32 // 0x8FC
	RCC_QSPICKSELR        volatile.Register32 // 0x900
	RCC_FMCCKSELR         volatile.Register32 // 0x904
	_                     [4]byte
	RCC_FDCANCKSELR       volatile.Register32 // 0x90C
	_                     [4]byte
	RCC_SPDIFCKSELR       volatile.Register32 // 0x914
	RCC_CECCKSELR         volatile.Register32 // 0x918
	RCC_USBCKSELR         volatile.Register32 // 0x91C
	RCC_RNG2CKSELR        volatile.Register32 // 0x920
	RCC_DSICKSELR         volatile.Register32 // 0x924
	RCC_ADCCKSELR         volatile.Register32 // 0x928
	RCC_LPTIM45CKSELR     volatile.Register32 // 0x92C
	RCC_LPTIM23CKSELR     volatile.Register32 // 0x930
	RCC_LPTIM1CKSELR      volatile.Register32 // 0x934
	_                     [72]byte
	RCC_APB1RSTSETR       volatile.Register32 // 0x980
	RCC_APB1RSTCLRR       volatile.Register32 // 0x984
	RCC_APB2RSTSETR       volatile.Register32 // 0x988
	RCC_APB2RSTCLRR       volatile.Register32 // 0x98C
	RCC_APB3RSTSETR       volatile.Register32 // 0x990
	RCC_APB3RSTCLRR       volatile.Register32 // 0x994
	RCC_AHB2RSTSETR       volatile.Register32 // 0x998
	RCC_AHB2RSTCLRR       volatile.Register32 // 0x99C
	RCC_AHB3RSTSETR       volatile.Register32 // 0x9A0
	RCC_AHB3RSTCLRR       volatile.Register32 // 0x9A4
	RCC_AHB4RSTSETR       volatile.Register32 // 0x9A8
	RCC_AHB4RSTCLRR       volatile.Register32 // 0x9AC
	_                     [80]byte
	RCC_MP_APB1ENSETR     volatile.Register32 // 0xA00
	RCC_MP_APB1ENCLRR     volatile.Register32 // 0xA04
	RCC_MP_APB2ENSETR     volatile.Register32 // 0xA08
	RCC_MP_APB2ENCLRR     volatile.Register32 // 0xA0C
	RCC_MP_APB3ENSETR     volatile.Register32 // 0xA10
	RCC_MP_APB3ENCLRR     volatile.Register32 // 0xA14
	RCC_MP_AHB2ENSETR     volatile.Register32 // 0xA18
	RCC_MP_AHB2ENCLRR     volatile.Register32 // 0xA1C
	RCC_MP_AHB3ENSETR     volatile.Register32 // 0xA20
	RCC_MP_AHB3ENCLRR     volatile.Register32 // 0xA24
	RCC_MP_AHB4ENSETR     volatile.Register32 // 0xA28
	RCC_MP_AHB4ENCLRR     volatile.Register32 // 0xA2C
	_                     [8]byte
	RCC_MP_MLAHBENSETR    volatile.Register32 // 0xA38
	RCC_MP_MLAHBENCLRR    volatile.Register32 // 0xA3C
	_                     [64]byte
	RCC_MC_APB1ENSETR     volatile.Register32 // 0xA80
	RCC_MC_APB1ENCLRR     volatile.Register32 // 0xA84
	RCC_MC_APB2ENSETR     volatile.Register32 // 0xA88
	RCC_MC_APB2ENCLRR     volatile.Register32 // 0xA8C
	RCC_MC_APB3ENSETR     volatile.Register32 // 0xA90
	RCC_MC_APB3ENCLRR     volatile.Register32 // 0xA94
	RCC_MC_AHB2ENSETR     volatile.Register32 // 0xA98
	RCC_MC_AHB2ENCLRR     volatile.Register32 // 0xA9C
	RCC_MC_AHB3ENSETR     volatile.Register32 // 0xAA0
	RCC_MC_AHB3ENCLRR     volatile.Register32 // 0xAA4
	RCC_MC_AHB4ENSETR     volatile.Register32 // 0xAA8
	RCC_MC_AHB4ENCLRR     volatile.Register32 // 0xAAC
	RCC_MC_AXIMENSETR     volatile.Register32 // 0xAB0
	RCC_MC_AXIMENCLRR     volatile.Register32 // 0xAB4
	RCC_MC_MLAHBENSETR    volatile.Register32 // 0xAB8
	RCC_MC_MLAHBENCLRR    volatile.Register32 // 0xABC
	_                     [64]byte
	RCC_MP_APB1LPENSETR   volatile.Register32 // 0xB00
	RCC_MP_APB1LPENCLRR   volatile.Register32 // 0xB04
	RCC_MP_APB2LPENSETR   volatile.Register32 // 0xB08
	RCC_MP_APB2LPENCLRR   volatile.Register32 // 0xB0C
	RCC_MP_APB3LPENSETR   volatile.Register32 // 0xB10
	RCC_MP_APB3LPENCLRR   volatile.Register32 // 0xB14
	RCC_MP_AHB2LPENSETR   volatile.Register32 // 0xB18
	RCC_MP_AHB2LPENCLRR   volatile.Register32 // 0xB1C
	RCC_MP_AHB3LPENSETR   volatile.Register32 // 0xB20
	RCC_MP_AHB3LPENCLRR   volatile.Register32 // 0xB24
	RCC_MP_AHB4LPENSETR   volatile.Register32 // 0xB28
	RCC_MP_AHB4LPENCLRR   volatile.Register32 // 0xB2C
	RCC_MP_AXIMLPENSETR   volatile.Register32 // 0xB30
	RCC_MP_AXIMLPENCLRR   volatile.Register32 // 0xB34
	RCC_MP_MLAHBLPENSETR  volatile.Register32 // 0xB38
	RCC_MP_MLAHBLPENCLRR  volatile.Register32 // 0xB3C
	_                     [64]byte
	RCC_MC_APB1LPENSETR   volatile.Register32 // 0xB80
	RCC_MC_APB1LPENCLRR   volatile.Register32 // 0xB84
	RCC_MC_APB2LPENSETR   volatile.Register32 // 0xB88
	RCC_MC_APB2LPENCLRR   volatile.Register32 // 0xB8C
	RCC_MC_APB3LPENSETR   volatile.Register32 // 0xB90
	RCC_MC_APB3LPENCLRR   volatile.Register32 // 0xB94
	RCC_MC_AHB2LPENSETR   volatile.Register32 // 0xB98
	RCC_MC_AHB2LPENCLRR   volatile.Register32 // 0xB9C
	RCC_MC_AHB3LPENSETR   volatile.Register32 // 0xBA0
	RCC_MC_AHB3LPENCLRR   volatile.Register32 // 0xBA4
	RCC_MC_AHB4LPENSETR   volatile.Register32 // 0xBA8
	RCC_MC_AHB4LPENCLRR   volatile.Register32 // 0xBAC
	RCC_MC_AXIMLPENSETR   volatile.Register32 // 0xBB0
	RCC_MC_AXIMLPENCLRR   volatile.Register32 // 0xBB4
	RCC_MC_MLAHBLPENSETR  volatile.Register32 // 0xBB8
	RCC_MC_MLAHBLPENCLRR  volatile.Register32 // 0xBBC
	_                     [64]byte
	RCC_MC_RSTSCLRR       volatile.Register32 // 0xC00
	_                     [16]byte
	RCC_MC_CIER           volatile.Register32 // 0xC14
	RCC_MC_CIFR           volatile.Register32 // 0xC18
	_                     [984]byte
	RCC_VERR              volatile.Register32 // 0xFF4
	RCC_IDR               volatile.Register32 // 0xFF8
	RCC_SIDR              volatile.Register32 // 0xFFC
}

// RNG1
type RNG1_Type struct {
	RNG_CR     volatile.Register32 // 0x0
	RNG_SR     volatile.Register32 // 0x4
	RNG_DR     volatile.Register32 // 0x8
	_          [996]byte
	RNG_HWCFGR volatile.Register32 // 0x3F0
	RNG_VERR   volatile.Register32 // 0x3F4
	RNG_IPIDR  volatile.Register32 // 0x3F8
	RNG_SIDR   volatile.Register32 // 0x3FC
}

// RTC
type RTC_Type struct {
	RTC_TR       volatile.Register32 // 0x0
	RTC_DR       volatile.Register32 // 0x4
	RTC_SSR      volatile.Register32 // 0x8
	RTC_ICSR     volatile.Register32 // 0xC
	RTC_PRER     volatile.Register32 // 0x10
	RTC_WUTR     volatile.Register32 // 0x14
	RTC_CR       volatile.Register32 // 0x18
	_            [4]byte
	RTC_SMCR     volatile.Register32 // 0x20
	RTC_WPR      volatile.Register32 // 0x24
	RTC_CALR     volatile.Register32 // 0x28
	RTC_SHIFTR   volatile.Register32 // 0x2C
	RTC_TSTR     volatile.Register32 // 0x30
	RTC_TSDR     volatile.Register32 // 0x34
	RTC_TSSSR    volatile.Register32 // 0x38
	_            [4]byte
	RTC_ALRMAR   volatile.Register32 // 0x40
	RTC_ALRMASSR volatile.Register32 // 0x44
	RTC_ALRMBR   volatile.Register32 // 0x48
	RTC_ALRMBSSR volatile.Register32 // 0x4C
	RTC_SR       volatile.Register32 // 0x50
	RTC_MISR     volatile.Register32 // 0x54
	RTC_SMISR    volatile.Register32 // 0x58
	RTC_SCR      volatile.Register32 // 0x5C
	RTC_CFGR     volatile.Register32 // 0x60
	_            [908]byte
	RTC_HWCFGR   volatile.Register32 // 0x3F0
	RTC_VERR     volatile.Register32 // 0x3F4
	RTC_IPIDR    volatile.Register32 // 0x3F8
	RTC_SIDR     volatile.Register32 // 0x3FC
}

// SAI1 register block
type SAI_Type struct {
	SAI_GCR    volatile.Register32 // 0x0
	SAI_ACR1   volatile.Register32 // 0x4
	SAI_ACR2   volatile.Register32 // 0x8
	SAI_AFRCR  volatile.Register32 // 0xC
	SAI_ASLOTR volatile.Register32 // 0x10
	SAI_AIM    volatile.Register32 // 0x14
	SAI_ASR    volatile.Register32 // 0x18
	SAI_ACLRFR volatile.Register32 // 0x1C
	SAI_ADR    volatile.Register32 // 0x20
	SAI_BCR1   volatile.Register32 // 0x24
	SAI_BCR2   volatile.Register32 // 0x28
	SAI_BFRCR  volatile.Register32 // 0x2C
	SAI_BSLOTR volatile.Register32 // 0x30
	SAI_BIM    volatile.Register32 // 0x34
	SAI_BSR    volatile.Register32 // 0x38
	SAI_BCLRFR volatile.Register32 // 0x3C
	SAI_BDR    volatile.Register32 // 0x40
	SAI_PDMCR  volatile.Register32 // 0x44
	SAI_PDMDLY volatile.Register32 // 0x48
	_          [932]byte
	SAI_HWCFGR volatile.Register32 // 0x3F0
	SAI_VERR   volatile.Register32 // 0x3F4
	SAI_IPIDR  volatile.Register32 // 0x3F8
	SAI_SIDR   volatile.Register32 // 0x3FC
}

// SDMMC1
type SDMMC2_Type struct {
	SDMMC_POWER      volatile.Register32 // 0x0
	SDMMC_CLKCR      volatile.Register32 // 0x4
	SDMMC_ARGR       volatile.Register32 // 0x8
	SDMMC_CMDR       volatile.Register32 // 0xC
	SDMMC_RESPCMDR   volatile.Register32 // 0x10
	SDMMC_RESP1R     volatile.Register32 // 0x14
	SDMMC_RESP2R     volatile.Register32 // 0x18
	SDMMC_RESP3R     volatile.Register32 // 0x1C
	SDMMC_RESP4R     volatile.Register32 // 0x20
	SDMMC_DTIMER     volatile.Register32 // 0x24
	SDMMC_DLENR      volatile.Register32 // 0x28
	SDMMC_DCTRL      volatile.Register32 // 0x2C
	SDMMC_DCNTR      volatile.Register32 // 0x30
	SDMMC_STAR       volatile.Register32 // 0x34
	SDMMC_ICR        volatile.Register32 // 0x38
	SDMMC_MASKR      volatile.Register32 // 0x3C
	SDMMC_ACKTIMER   volatile.Register32 // 0x40
	_                [12]byte
	SDMMC_IDMACTRLR  volatile.Register32 // 0x50
	SDMMC_IDMABSIZER volatile.Register32 // 0x54
	SDMMC_IDMABASER  volatile.Register32 // 0x58
	_                [8]byte
	SDMMC_IDMALAR    volatile.Register32 // 0x64
	SDMMC_IDMABAR    volatile.Register32 // 0x68
	_                [20]byte
	SDMMC_FIFOR0     volatile.Register32 // 0x80
	SDMMC_FIFOR1     volatile.Register32 // 0x84
	SDMMC_FIFOR2     volatile.Register32 // 0x88
	SDMMC_FIFOR3     volatile.Register32 // 0x8C
	SDMMC_FIFOR4     volatile.Register32 // 0x90
	SDMMC_FIFOR5     volatile.Register32 // 0x94
	SDMMC_FIFOR6     volatile.Register32 // 0x98
	SDMMC_FIFOR7     volatile.Register32 // 0x9C
	SDMMC_FIFOR8     volatile.Register32 // 0xA0
	SDMMC_FIFOR9     volatile.Register32 // 0xA4
	SDMMC_FIFOR10    volatile.Register32 // 0xA8
	SDMMC_FIFOR11    volatile.Register32 // 0xAC
	SDMMC_FIFOR12    volatile.Register32 // 0xB0
	SDMMC_FIFOR13    volatile.Register32 // 0xB4
	SDMMC_FIFOR14    volatile.Register32 // 0xB8
	SDMMC_FIFOR15    volatile.Register32 // 0xBC
	_                [820]byte
	SDMMC_VERR       volatile.Register32 // 0x3F4
	SDMMC_IPIDR      volatile.Register32 // 0x3F8
	SDMMC_SIDR       volatile.Register32 // 0x3FC
}

// SPDIFRX
type SPDIFRX_Type struct {
	SPDIFRX_CR      volatile.Register32 // 0x0
	SPDIFRX_IMR     volatile.Register32 // 0x4
	SPDIFRX_SR      volatile.Register32 // 0x8
	SPDIFRX_IFCR    volatile.Register32 // 0xC
	SPDIFRX_FMT0_DR volatile.Register32 // 0x10
	SPDIFRX_CSR     volatile.Register32 // 0x14
	SPDIFRX_DIR     volatile.Register32 // 0x18
	_               [984]byte
	SPDIFRX_VERR    volatile.Register32 // 0x3F4
	SPDIFRX_IPIDR   volatile.Register32 // 0x3F8
	SPDIFRX_SIDR    volatile.Register32 // 0x3FC
}

// SPI1
type SPI1_Type struct {
	SPI2S_CR1      volatile.Register32 // 0x0
	SPI_CR2        volatile.Register32 // 0x4
	SPI_CFG1       volatile.Register32 // 0x8
	SPI_CFG2       volatile.Register32 // 0xC
	SPI2S_IER      volatile.Register32 // 0x10
	SPI2S_SR       volatile.Register32 // 0x14
	SPI2S_IFCR     volatile.Register32 // 0x18
	_              [4]byte
	SPI2S_TXDR     volatile.Register32 // 0x20
	_              [12]byte
	SPI2S_RXDR     volatile.Register32 // 0x30
	_              [12]byte
	SPI_CRCPOLY    volatile.Register32 // 0x40
	SPI_TXCRC      volatile.Register32 // 0x44
	SPI_RXCRC      volatile.Register32 // 0x48
	SPI_UDRDR      volatile.Register32 // 0x4C
	SPI_I2SCFGR    volatile.Register32 // 0x50
	_              [924]byte
	SPI_I2S_HWCFGR volatile.Register32 // 0x3F0
	SPI_VERR       volatile.Register32 // 0x3F4
	SPI_IPIDR      volatile.Register32 // 0x3F8
	SPI_SIDR       volatile.Register32 // 0x3FC
}

// STGENC
type STGENC_Type struct {
	STGENC_CNTCR   volatile.Register32 // 0x0
	STGENC_CNTSR   volatile.Register32 // 0x4
	STGENC_CNTCVL  volatile.Register32 // 0x8
	STGENC_CNTCVU  volatile.Register32 // 0xC
	_              [16]byte
	STGENC_CNTFID0 volatile.Register32 // 0x20
	_              [4012]byte
	STGENC_PIDR4   volatile.Register32 // 0xFD0
	STGENC_PIDR5   volatile.Register32 // 0xFD4
	STGENC_PIDR6   volatile.Register32 // 0xFD8
	STGENC_PIDR7   volatile.Register32 // 0xFDC
	STGENC_PIDR0   volatile.Register32 // 0xFE0
	STGENC_PIDR1   volatile.Register32 // 0xFE4
	STGENC_PIDR2   volatile.Register32 // 0xFE8
	STGENC_PIDR3   volatile.Register32 // 0xFEC
	STGENC_CIDR0   volatile.Register32 // 0xFF0
	STGENC_CIDR1   volatile.Register32 // 0xFF4
	STGENC_CIDR2   volatile.Register32 // 0xFF8
	STGENC_CIDR3   volatile.Register32 // 0xFFC
}

// STGENR
type STGENR_Type struct {
	STGENR_CNTCVL volatile.Register32 // 0x0
	STGENR_CNTCVU volatile.Register32 // 0x4
	_             [4040]byte
	STGENR_PIDR4  volatile.Register32 // 0xFD0
	STGENR_PIDR5  volatile.Register32 // 0xFD4
	STGENR_PIDR6  volatile.Register32 // 0xFD8
	STGENR_PIDR7  volatile.Register32 // 0xFDC
	STGENR_PIDR0  volatile.Register32 // 0xFE0
	STGENR_PIDR1  volatile.Register32 // 0xFE4
	STGENR_PIDR2  volatile.Register32 // 0xFE8
	STGENR_PIDR3  volatile.Register32 // 0xFEC
	STGENR_CIDR0  volatile.Register32 // 0xFF0
	STGENR_CIDR1  volatile.Register32 // 0xFF4
	STGENR_CIDR2  volatile.Register32 // 0xFF8
	STGENR_CIDR3  volatile.Register32 // 0xFFC
}

// SYSCFG
type SYSCFG_Type struct {
	SYSCFG_BOOTR      volatile.Register32 // 0x0
	SYSCFG_PMCSETR    volatile.Register32 // 0x4
	_                 [16]byte
	SYSCFG_IOCTRLSETR volatile.Register32 // 0x18
	SYSCFG_ICNR       volatile.Register32 // 0x1C
	SYSCFG_CMPCR      volatile.Register32 // 0x20
	SYSCFG_CMPENSETR  volatile.Register32 // 0x24
	SYSCFG_CMPENCLRR  volatile.Register32 // 0x28
	SYSCFG_CBR        volatile.Register32 // 0x2C
	_                 [20]byte
	SYSCFG_PMCCLRR    volatile.Register32 // 0x44
	_                 [16]byte
	SYSCFG_IOCTRLCLRR volatile.Register32 // 0x58
	_                 [920]byte
	SYSCFG_VERR       volatile.Register32 // 0x3F4
	SYSCFG_IPIDR      volatile.Register32 // 0x3F8
	SYSCFG_SIDR       volatile.Register32 // 0x3FC
}

// TAMP
type TAMP_Type struct {
	TAMP_CR1     volatile.Register32 // 0x0
	TAMP_CR2     volatile.Register32 // 0x4
	_            [4]byte
	TAMP_FLTCR   volatile.Register32 // 0xC
	TAMP_ATCR1   volatile.Register32 // 0x10
	TAMP_ATSEEDR volatile.Register32 // 0x14
	TAMP_ATOR    volatile.Register32 // 0x18
	_            [4]byte
	TAMP_SMCR    volatile.Register32 // 0x20
	_            [8]byte
	TAMP_IER     volatile.Register32 // 0x2C
	TAMP_SR      volatile.Register32 // 0x30
	TAMP_MISR    volatile.Register32 // 0x34
	TAMP_SMISR   volatile.Register32 // 0x38
	TAMP_SCR     volatile.Register32 // 0x3C
	TAMP_COUNTR  volatile.Register32 // 0x40
	_            [12]byte
	TAMP_CFGR    volatile.Register32 // 0x50
	_            [172]byte
	TAMP_BKP0R   volatile.Register32 // 0x100
	TAMP_BKP1R   volatile.Register32 // 0x104
	TAMP_BKP2R   volatile.Register32 // 0x108
	TAMP_BKP3R   volatile.Register32 // 0x10C
	TAMP_BKP4R   volatile.Register32 // 0x110
	TAMP_BKP5R   volatile.Register32 // 0x114
	TAMP_BKP6R   volatile.Register32 // 0x118
	TAMP_BKP7R   volatile.Register32 // 0x11C
	TAMP_BKP8R   volatile.Register32 // 0x120
	TAMP_BKP9R   volatile.Register32 // 0x124
	TAMP_BKP10R  volatile.Register32 // 0x128
	TAMP_BKP11R  volatile.Register32 // 0x12C
	TAMP_BKP12R  volatile.Register32 // 0x130
	TAMP_BKP13R  volatile.Register32 // 0x134
	TAMP_BKP14R  volatile.Register32 // 0x138
	TAMP_BKP15R  volatile.Register32 // 0x13C
	TAMP_BKP16R  volatile.Register32 // 0x140
	TAMP_BKP17R  volatile.Register32 // 0x144
	TAMP_BKP18R  volatile.Register32 // 0x148
	TAMP_BKP19R  volatile.Register32 // 0x14C
	TAMP_BKP20R  volatile.Register32 // 0x150
	TAMP_BKP21R  volatile.Register32 // 0x154
	TAMP_BKP22R  volatile.Register32 // 0x158
	TAMP_BKP23R  volatile.Register32 // 0x15C
	TAMP_BKP24R  volatile.Register32 // 0x160
	TAMP_BKP25R  volatile.Register32 // 0x164
	TAMP_BKP26R  volatile.Register32 // 0x168
	TAMP_BKP27R  volatile.Register32 // 0x16C
	TAMP_BKP28R  volatile.Register32 // 0x170
	TAMP_BKP29R  volatile.Register32 // 0x174
	TAMP_BKP30R  volatile.Register32 // 0x178
	TAMP_BKP31R  volatile.Register32 // 0x17C
	_            [620]byte
	TAMP_HWCFGR2 volatile.Register32 // 0x3EC
	TAMP_HWCFGR1 volatile.Register32 // 0x3F0
	TAMP_VERR    volatile.Register32 // 0x3F4
	TAMP_IPIDR   volatile.Register32 // 0x3F8
	TAMP_SIDR    volatile.Register32 // 0x3FC
}

// TIM1
type TIM1_Type struct {
	TIM1_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM1_CR2              volatile.Register32 // 0x4
	TIM1_SMCR             volatile.Register32 // 0x8
	TIM1_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM1_SR               volatile.Register32 // 0x10
	TIM1_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM1_CCMR1ALTERNATE1  volatile.Register32 // 0x18
	TIM1_CCMR2ALTERNATE17 volatile.Register32 // 0x1C
	TIM1_CCER             volatile.Register32 // 0x20
	TIM1_CNT              volatile.Register32 // 0x24
	TIM1_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM1_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM1_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM1_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM1_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM1_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM1_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM1_BDTR             volatile.Register32 // 0x44
	TIM1_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM1_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM1_CCMR3            volatile.Register32 // 0x54
	TIM1_CCR5             volatile.Register32 // 0x58
	TIM1_CCR6             volatile.Register16 // 0x5C
	_                     [2]byte
	TIM1_AF1              volatile.Register32 // 0x60
	TIM1_AF2              volatile.Register32 // 0x64
	TIM1_TISEL            volatile.Register32 // 0x68
}

// TIM2
type TIM2_Type struct {
	TIM2_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM2_CR2              volatile.Register32 // 0x4
	TIM2_SMCR             volatile.Register32 // 0x8
	TIM2_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM2_SR               volatile.Register32 // 0x10
	TIM2_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM2_CCMR1ALTERNATE2  volatile.Register32 // 0x18
	TIM2_CCMR2ALTERNATE18 volatile.Register32 // 0x1C
	TIM2_CCER             volatile.Register32 // 0x20
	TIM2_CNT              volatile.Register32 // 0x24
	TIM2_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM2_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM2_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM2_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM2_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM2_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM2_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM2_BDTR             volatile.Register32 // 0x44
	TIM2_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM2_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM2_CCMR3            volatile.Register32 // 0x54
	TIM2_CCR5             volatile.Register32 // 0x58
	TIM2_CCR6             volatile.Register16 // 0x5C
}

// TIM3
type TIM3_Type struct {
	TIM3_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM3_CR2              volatile.Register32 // 0x4
	TIM3_SMCR             volatile.Register32 // 0x8
	TIM3_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM3_SR               volatile.Register32 // 0x10
	TIM3_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM3_CCMR1ALTERNATE3  volatile.Register32 // 0x18
	TIM3_CCMR2ALTERNATE19 volatile.Register32 // 0x1C
	TIM3_CCER             volatile.Register32 // 0x20
	TIM3_CNT              volatile.Register32 // 0x24
	TIM3_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM3_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM3_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM3_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM3_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM3_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM3_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM3_BDTR             volatile.Register32 // 0x44
	TIM3_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM3_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM3_CCMR3            volatile.Register32 // 0x54
	TIM3_CCR5             volatile.Register32 // 0x58
	TIM3_CCR6             volatile.Register16 // 0x5C
}

// TIM4
type TIM4_Type struct {
	TIM4_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM4_CR2              volatile.Register32 // 0x4
	TIM4_SMCR             volatile.Register32 // 0x8
	TIM4_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM4_SR               volatile.Register32 // 0x10
	TIM4_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM4_CCMR1ALTERNATE4  volatile.Register32 // 0x18
	TIM4_CCMR2ALTERNATE20 volatile.Register32 // 0x1C
	TIM4_CCER             volatile.Register32 // 0x20
	TIM4_CNT              volatile.Register32 // 0x24
	TIM4_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM4_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM4_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM4_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM4_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM4_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM4_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM4_BDTR             volatile.Register32 // 0x44
	TIM4_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM4_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM4_CCMR3            volatile.Register32 // 0x54
	TIM4_CCR5             volatile.Register32 // 0x58
	TIM4_CCR6             volatile.Register16 // 0x5C
}

// TIM5
type TIM5_Type struct {
	TIM5_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM5_CR2              volatile.Register32 // 0x4
	TIM5_SMCR             volatile.Register32 // 0x8
	TIM5_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM5_SR               volatile.Register32 // 0x10
	TIM5_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM5_CCMR1ALTERNATE5  volatile.Register32 // 0x18
	TIM5_CCMR2ALTERNATE21 volatile.Register32 // 0x1C
	TIM5_CCER             volatile.Register32 // 0x20
	TIM5_CNT              volatile.Register32 // 0x24
	TIM5_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM5_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM5_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM5_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM5_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM5_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM5_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM5_BDTR             volatile.Register32 // 0x44
	TIM5_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM5_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM5_CCMR3            volatile.Register32 // 0x54
	TIM5_CCR5             volatile.Register32 // 0x58
	TIM5_CCR6             volatile.Register16 // 0x5C
}

// TIM6
type TIM6_Type struct {
	TIM6_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM6_CR2              volatile.Register32 // 0x4
	TIM6_SMCR             volatile.Register32 // 0x8
	TIM6_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM6_SR               volatile.Register32 // 0x10
	TIM6_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM6_CCMR1ALTERNATE6  volatile.Register32 // 0x18
	TIM6_CCMR2ALTERNATE22 volatile.Register32 // 0x1C
	TIM6_CCER             volatile.Register32 // 0x20
	TIM6_CNT              volatile.Register32 // 0x24
	TIM6_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM6_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM6_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM6_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM6_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM6_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM6_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM6_BDTR             volatile.Register32 // 0x44
	TIM6_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM6_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM6_CCMR3            volatile.Register32 // 0x54
	TIM6_CCR5             volatile.Register32 // 0x58
	TIM6_CCR6             volatile.Register16 // 0x5C
}

// TIM7
type TIM7_Type struct {
	TIM7_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM7_CR2              volatile.Register32 // 0x4
	TIM7_SMCR             volatile.Register32 // 0x8
	TIM7_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM7_SR               volatile.Register32 // 0x10
	TIM7_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM7_CCMR1ALTERNATE7  volatile.Register32 // 0x18
	TIM7_CCMR2ALTERNATE23 volatile.Register32 // 0x1C
	TIM7_CCER             volatile.Register32 // 0x20
	TIM7_CNT              volatile.Register32 // 0x24
	TIM7_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM7_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM7_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM7_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM7_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM7_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM7_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM7_BDTR             volatile.Register32 // 0x44
	TIM7_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM7_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM7_CCMR3            volatile.Register32 // 0x54
	TIM7_CCR5             volatile.Register32 // 0x58
	TIM7_CCR6             volatile.Register16 // 0x5C
}

// TIM8
type TIM8_Type struct {
	TIM8_CR1              volatile.Register16 // 0x0
	_                     [2]byte
	TIM8_CR2              volatile.Register32 // 0x4
	TIM8_SMCR             volatile.Register32 // 0x8
	TIM8_DIER             volatile.Register16 // 0xC
	_                     [2]byte
	TIM8_SR               volatile.Register32 // 0x10
	TIM8_EGR              volatile.Register16 // 0x14
	_                     [2]byte
	TIM8_CCMR1ALTERNATE8  volatile.Register32 // 0x18
	TIM8_CCMR2ALTERNATE24 volatile.Register32 // 0x1C
	TIM8_CCER             volatile.Register32 // 0x20
	TIM8_CNT              volatile.Register32 // 0x24
	TIM8_PSC              volatile.Register16 // 0x28
	_                     [2]byte
	TIM8_ARR              volatile.Register16 // 0x2C
	_                     [2]byte
	TIM8_RCR              volatile.Register16 // 0x30
	_                     [2]byte
	TIM8_CCR1             volatile.Register16 // 0x34
	_                     [2]byte
	TIM8_CCR2             volatile.Register16 // 0x38
	_                     [2]byte
	TIM8_CCR3             volatile.Register16 // 0x3C
	_                     [2]byte
	TIM8_CCR4             volatile.Register16 // 0x40
	_                     [2]byte
	TIM8_BDTR             volatile.Register32 // 0x44
	TIM8_DCR              volatile.Register16 // 0x48
	_                     [2]byte
	TIM8_DMAR             volatile.Register32 // 0x4C
	_                     [4]byte
	TIM8_CCMR3            volatile.Register32 // 0x54
	TIM8_CCR5             volatile.Register32 // 0x58
	TIM8_CCR6             volatile.Register16 // 0x5C
	_                     [2]byte
	TIM8_AF1              volatile.Register32 // 0x60
	TIM8_AF2              volatile.Register32 // 0x64
	TIM8_TISEL            volatile.Register32 // 0x68
}

// TIM12
type TIM12_Type struct {
	TIM12_CR1         volatile.Register16 // 0x0
	_                 [2]byte
	TIM12_CR2         volatile.Register32 // 0x4
	TIM12_SMCR        volatile.Register32 // 0x8
	TIM12_DIER        volatile.Register16 // 0xC
	_                 [2]byte
	TIM12_SR          volatile.Register32 // 0x10
	TIM12_EGR         volatile.Register16 // 0x14
	_                 [2]byte
	TIM12_CCMR1_input volatile.Register32 // 0x18
	_                 [4]byte
	TIM12_CCER        volatile.Register32 // 0x20
	TIM12_CNT         volatile.Register32 // 0x24
	TIM12_PSC         volatile.Register16 // 0x28
	_                 [2]byte
	TIM12_ARR         volatile.Register16 // 0x2C
	_                 [6]byte
	TIM12_CCR1        volatile.Register16 // 0x34
	_                 [2]byte
	TIM12_CCR2        volatile.Register16 // 0x38
	_                 [46]byte
	TIM12_TISEL       volatile.Register32 // 0x68
}

// TIM13
type TIM13_Type struct {
	TIM13_CR1   volatile.Register16 // 0x0
	_           [10]byte
	TIM13_DIER  volatile.Register16 // 0xC
	_           [2]byte
	TIM13_SR    volatile.Register16 // 0x10
	_           [2]byte
	TIM13_EGR   volatile.Register16 // 0x14
	_           [2]byte
	TIM13_CCMR1 volatile.Register32 // 0x18
	_           [4]byte
	TIM13_CCER  volatile.Register16 // 0x20
	_           [2]byte
	TIM13_CNT   volatile.Register32 // 0x24
	TIM13_PSC   volatile.Register16 // 0x28
	_           [2]byte
	TIM13_ARR   volatile.Register16 // 0x2C
	_           [6]byte
	TIM13_CCR1  volatile.Register16 // 0x34
	_           [50]byte
	TIM13_TISEL volatile.Register16 // 0x68
}

// TIM14
type TIM14_Type struct {
	TIM14_CR1   volatile.Register16 // 0x0
	_           [10]byte
	TIM14_DIER  volatile.Register16 // 0xC
	_           [2]byte
	TIM14_SR    volatile.Register16 // 0x10
	_           [2]byte
	TIM14_EGR   volatile.Register16 // 0x14
	_           [2]byte
	TIM14_CCMR1 volatile.Register32 // 0x18
	_           [4]byte
	TIM14_CCER  volatile.Register16 // 0x20
	_           [2]byte
	TIM14_CNT   volatile.Register32 // 0x24
	TIM14_PSC   volatile.Register16 // 0x28
	_           [2]byte
	TIM14_ARR   volatile.Register16 // 0x2C
	_           [6]byte
	TIM14_CCR1  volatile.Register16 // 0x34
	_           [50]byte
	TIM14_TISEL volatile.Register16 // 0x68
}

// TIM15
type TIMER_Type struct {
	TIM15_CR1         volatile.Register16 // 0x0
	_                 [2]byte
	TIM15_CR2         volatile.Register16 // 0x4
	_                 [2]byte
	TIMx_SMCR         volatile.Register32 // 0x8
	TIM15_DIER        volatile.Register16 // 0xC
	_                 [2]byte
	TIM15_SR          volatile.Register16 // 0x10
	_                 [2]byte
	TIMx_EGR          volatile.Register32 // 0x14
	TIMx_CCMR1_Output volatile.Register32 // 0x18
	_                 [4]byte
	TIM15_CCER        volatile.Register16 // 0x20
	_                 [2]byte
	TIM15_CNT         volatile.Register32 // 0x24
	TIM15_PSC         volatile.Register16 // 0x28
	_                 [2]byte
	TIM15_ARR         volatile.Register16 // 0x2C
	_                 [2]byte
	TIM15_RCR         volatile.Register16 // 0x30
	_                 [2]byte
	TIM15_CCR1        volatile.Register16 // 0x34
	_                 [2]byte
	TIM15_CCR2        volatile.Register16 // 0x38
	_                 [10]byte
	TIMx_BDTR         volatile.Register32 // 0x44
	TIM15_DCR         volatile.Register16 // 0x48
	_                 [2]byte
	TIM15_DMAR        volatile.Register16 // 0x4C
	_                 [18]byte
	TIM15_AF1         volatile.Register32 // 0x60
	_                 [4]byte
	TIM15_TISEL       volatile.Register32 // 0x68
}

// TZC
type TZC_Type struct {
	TZC_BUILD_CONFIG       volatile.Register32 // 0x0
	TZC_ACTION             volatile.Register32 // 0x4
	TZC_GATE_KEEPER        volatile.Register32 // 0x8
	TZC_SPECULATION_CTRL   volatile.Register32 // 0xC
	TZC_INT_STATUS         volatile.Register32 // 0x10
	TZC_INT_CLEAR          volatile.Register32 // 0x14
	_                      [8]byte
	TZC_FAIL_ADDRESS_LOW0  volatile.Register32 // 0x20
	TZC_FAIL_ADDRESS_HIGH0 volatile.Register32 // 0x24
	TZC_FAIL_CONTROL0      volatile.Register32 // 0x28
	TZC_FAIL_ID0           volatile.Register32 // 0x2C
	TZC_FAIL_ADDRESS_LOW1  volatile.Register32 // 0x30
	TZC_FAIL_ADDRESS_HIGH1 volatile.Register32 // 0x34
	TZC_FAIL_CONTROL1      volatile.Register32 // 0x38
	TZC_FAIL_ID1           volatile.Register32 // 0x3C
	_                      [196]byte
	TZC_REGION_BASE_HIGH0  volatile.Register32 // 0x104
	TZC_REGION_TOP_LOW0    volatile.Register32 // 0x108
	TZC_REGION_TOP_HIGH0   volatile.Register32 // 0x10C
	TZC_REGION_ATTRIBUTE0  volatile.Register32 // 0x110
	TZC_REGION_ID_ACCESS0  volatile.Register32 // 0x114
	_                      [8]byte
	TZC_REGION_BASE_LOW1   volatile.Register32 // 0x120
	TZC_REGION_BASE_HIGH1  volatile.Register32 // 0x124
	TZC_REGION_TOP_LOW1    volatile.Register32 // 0x128
	TZC_REGION_TOP_HIGH1   volatile.Register32 // 0x12C
	TZC_REGION_ATTRIBUTE1  volatile.Register32 // 0x130
	TZC_REGION_ID_ACCESS1  volatile.Register32 // 0x134
	_                      [8]byte
	TZC_REGION_BASE_LOW2   volatile.Register32 // 0x140
	TZC_REGION_BASE_HIGH2  volatile.Register32 // 0x144
	TZC_REGION_TOP_LOW2    volatile.Register32 // 0x148
	TZC_REGION_TOP_HIGH2   volatile.Register32 // 0x14C
	TZC_REGION_ATTRIBUTE2  volatile.Register32 // 0x150
	TZC_REGION_ID_ACCESS2  volatile.Register32 // 0x154
	_                      [8]byte
	TZC_REGION_BASE_LOW3   volatile.Register32 // 0x160
	TZC_REGION_BASE_HIGH3  volatile.Register32 // 0x164
	TZC_REGION_TOP_LOW3    volatile.Register32 // 0x168
	TZC_REGION_TOP_HIGH3   volatile.Register32 // 0x16C
	TZC_REGION_ATTRIBUTE3  volatile.Register32 // 0x170
	TZC_REGION_ID_ACCESS3  volatile.Register32 // 0x174
	_                      [8]byte
	TZC_REGION_BASE_LOW4   volatile.Register32 // 0x180
	TZC_REGION_BASE_HIGH4  volatile.Register32 // 0x184
	TZC_REGION_TOP_LOW4    volatile.Register32 // 0x188
	TZC_REGION_TOP_HIGH4   volatile.Register32 // 0x18C
	TZC_REGION_ATTRIBUTE4  volatile.Register32 // 0x190
	TZC_REGION_ID_ACCESS4  volatile.Register32 // 0x194
	_                      [8]byte
	TZC_REGION_BASE_LOW5   volatile.Register32 // 0x1A0
	TZC_REGION_BASE_HIGH5  volatile.Register32 // 0x1A4
	TZC_REGION_TOP_LOW5    volatile.Register32 // 0x1A8
	TZC_REGION_TOP_HIGH5   volatile.Register32 // 0x1AC
	TZC_REGION_ATTRIBUTE5  volatile.Register32 // 0x1B0
	TZC_REGION_ID_ACCESS5  volatile.Register32 // 0x1B4
	_                      [8]byte
	TZC_REGION_BASE_LOW6   volatile.Register32 // 0x1C0
	TZC_REGION_BASE_HIGH6  volatile.Register32 // 0x1C4
	TZC_REGION_TOP_LOW6    volatile.Register32 // 0x1C8
	TZC_REGION_TOP_HIGH6   volatile.Register32 // 0x1CC
	TZC_REGION_ATTRIBUTE6  volatile.Register32 // 0x1D0
	TZC_REGION_ID_ACCESS6  volatile.Register32 // 0x1D4
	_                      [16]byte
	TZC_REGION_TOP_LOW7    volatile.Register32 // 0x1E8
	_                      [4]byte
	TZC_REGION_ATTRIBUTE7  volatile.Register32 // 0x1F0
	_                      [12]byte
	TZC_REGION_BASE_LOW8   volatile.Register32 // 0x200
	TZC_REGION_BASE_HIGH8  volatile.Register32 // 0x204
	_                      [8]byte
	TZC_REGION_ATTRIBUTE8  volatile.Register32 // 0x210
	_                      [204]byte
	TZC_REGION_BASE_LOW7   volatile.Register32 // 0x2E0
	TZC_REGION_BASE_HIGH7  volatile.Register32 // 0x2E4
	_                      [4]byte
	TZC_REGION_TOP_HIGH7   volatile.Register32 // 0x2EC
	_                      [4]byte
	TZC_REGION_ID_ACCESS7  volatile.Register32 // 0x2F4
	_                      [16]byte
	TZC_REGION_TOP_LOW8    volatile.Register32 // 0x308
	TZC_REGION_TOP_HIGH8   volatile.Register32 // 0x30C
	_                      [4]byte
	TZC_REGION_ID_ACCESS8  volatile.Register32 // 0x314
	_                      [3256]byte
	TZC_PID4               volatile.Register32 // 0xFD0
	TZC_PID5               volatile.Register32 // 0xFD4
	TZC_PID6               volatile.Register32 // 0xFD8
	TZC_PID7               volatile.Register32 // 0xFDC
	TZC_PID0               volatile.Register32 // 0xFE0
	TZC_PID1               volatile.Register32 // 0xFE4
	TZC_PID2               volatile.Register32 // 0xFE8
	TZC_PID3               volatile.Register32 // 0xFEC
	TZC_CID0               volatile.Register32 // 0xFF0
	TZC_CID1               volatile.Register32 // 0xFF4
	TZC_CID2               volatile.Register32 // 0xFF8
	TZC_CID3               volatile.Register32 // 0xFFC
}

// Universal synchronous asynchronous receiver transmitter
type USART_Type struct {
	CR1     volatile.Register32 // 0x0
	CR2     volatile.Register32 // 0x4
	CR3     volatile.Register32 // 0x8
	BRR     volatile.Register32 // 0xC
	GTPR    volatile.Register32 // 0x10
	RTOR    volatile.Register32 // 0x14
	RQR     volatile.Register32 // 0x18
	ISR     volatile.Register32 // 0x1C
	ICR     volatile.Register32 // 0x20
	RDR     volatile.Register32 // 0x24
	TDR     volatile.Register32 // 0x28
	PRESC   volatile.Register32 // 0x2C
	_       [956]byte
	HWCFGR2 volatile.Register32 // 0x3EC
	HWCFGR1 volatile.Register32 // 0x3F0
	VERR    volatile.Register32 // 0x3F4
	IPIDR   volatile.Register32 // 0x3F8
	SIDR    volatile.Register32 // 0x3FC
}

// USBPHYC
type USBPHYC_Type struct {
	USBPHYC_PLL   volatile.Register32 // 0x0
	_             [4]byte
	USBPHYC_MISC  volatile.Register32 // 0x8
	_             [256]byte
	USBPHYC_TUNE1 volatile.Register32 // 0x10C
	_             [252]byte
	USBPHYC_TUNE2 volatile.Register32 // 0x20C
	_             [3564]byte
	USBPHYC_VERR  volatile.Register32 // 0xFFC
}

// VREFBUF
type VREFBUF_Type struct {
	VREFBUF_CSR volatile.Register32 // 0x0
	VREFBUF_CCR volatile.Register32 // 0x4
}

// WWDG1
type WWDG1_Type struct {
	WWDG_CR     volatile.Register32 // 0x0
	WWDG_CFR    volatile.Register32 // 0x4
	WWDG_SR     volatile.Register32 // 0x8
	_           [996]byte
	WWDG_HWCFGR volatile.Register32 // 0x3F0
	WWDG_VERR   volatile.Register32 // 0x3F4
	WWDG_IPIDR  volatile.Register32 // 0x3F8
	WWDG_SIDR   volatile.Register32 // 0x3FC
}

// Bitfields for ADC: ADC
const (
	// ADC_ISR: ADC interrupt and status register
	// Position of ADRDY field.
	ADC_ADC_ISR_ADRDY_Pos = 0x0
	// Bit mask of ADRDY field.
	ADC_ADC_ISR_ADRDY_Msk = 0x1
	// Bit ADRDY.
	ADC_ADC_ISR_ADRDY = 0x1
	// Position of EOSMP field.
	ADC_ADC_ISR_EOSMP_Pos = 0x1
	// Bit mask of EOSMP field.
	ADC_ADC_ISR_EOSMP_Msk = 0x2
	// Bit EOSMP.
	ADC_ADC_ISR_EOSMP = 0x2
	// Position of EOC field.
	ADC_ADC_ISR_EOC_Pos = 0x2
	// Bit mask of EOC field.
	ADC_ADC_ISR_EOC_Msk = 0x4
	// Bit EOC.
	ADC_ADC_ISR_EOC = 0x4
	// Position of EOS field.
	ADC_ADC_ISR_EOS_Pos = 0x3
	// Bit mask of EOS field.
	ADC_ADC_ISR_EOS_Msk = 0x8
	// Bit EOS.
	ADC_ADC_ISR_EOS = 0x8
	// Position of OVR field.
	ADC_ADC_ISR_OVR_Pos = 0x4
	// Bit mask of OVR field.
	ADC_ADC_ISR_OVR_Msk = 0x10
	// Bit OVR.
	ADC_ADC_ISR_OVR = 0x10
	// Position of JEOC field.
	ADC_ADC_ISR_JEOC_Pos = 0x5
	// Bit mask of JEOC field.
	ADC_ADC_ISR_JEOC_Msk = 0x20
	// Bit JEOC.
	ADC_ADC_ISR_JEOC = 0x20
	// Position of JEOS field.
	ADC_ADC_ISR_JEOS_Pos = 0x6
	// Bit mask of JEOS field.
	ADC_ADC_ISR_JEOS_Msk = 0x40
	// Bit JEOS.
	ADC_ADC_ISR_JEOS = 0x40
	// Position of AWD1 field.
	ADC_ADC_ISR_AWD1_Pos = 0x7
	// Bit mask of AWD1 field.
	ADC_ADC_ISR_AWD1_Msk = 0x80
	// Bit AWD1.
	ADC_ADC_ISR_AWD1 = 0x80
	// Position of AWD2 field.
	ADC_ADC_ISR_AWD2_Pos = 0x8
	// Bit mask of AWD2 field.
	ADC_ADC_ISR_AWD2_Msk = 0x100
	// Bit AWD2.
	ADC_ADC_ISR_AWD2 = 0x100
	// Position of AWD3 field.
	ADC_ADC_ISR_AWD3_Pos = 0x9
	// Bit mask of AWD3 field.
	ADC_ADC_ISR_AWD3_Msk = 0x200
	// Bit AWD3.
	ADC_ADC_ISR_AWD3 = 0x200
	// Position of JQOVF field.
	ADC_ADC_ISR_JQOVF_Pos = 0xa
	// Bit mask of JQOVF field.
	ADC_ADC_ISR_JQOVF_Msk = 0x400
	// Bit JQOVF.
	ADC_ADC_ISR_JQOVF = 0x400

	// ADC_IER: ADC interrupt enable register
	// Position of ADRDYIE field.
	ADC_ADC_IER_ADRDYIE_Pos = 0x0
	// Bit mask of ADRDYIE field.
	ADC_ADC_IER_ADRDYIE_Msk = 0x1
	// Bit ADRDYIE.
	ADC_ADC_IER_ADRDYIE = 0x1
	// Position of EOSMPIE field.
	ADC_ADC_IER_EOSMPIE_Pos = 0x1
	// Bit mask of EOSMPIE field.
	ADC_ADC_IER_EOSMPIE_Msk = 0x2
	// Bit EOSMPIE.
	ADC_ADC_IER_EOSMPIE = 0x2
	// Position of EOCIE field.
	ADC_ADC_IER_EOCIE_Pos = 0x2
	// Bit mask of EOCIE field.
	ADC_ADC_IER_EOCIE_Msk = 0x4
	// Bit EOCIE.
	ADC_ADC_IER_EOCIE = 0x4
	// Position of EOSIE field.
	ADC_ADC_IER_EOSIE_Pos = 0x3
	// Bit mask of EOSIE field.
	ADC_ADC_IER_EOSIE_Msk = 0x8
	// Bit EOSIE.
	ADC_ADC_IER_EOSIE = 0x8
	// Position of OVRIE field.
	ADC_ADC_IER_OVRIE_Pos = 0x4
	// Bit mask of OVRIE field.
	ADC_ADC_IER_OVRIE_Msk = 0x10
	// Bit OVRIE.
	ADC_ADC_IER_OVRIE = 0x10
	// Position of JEOCIE field.
	ADC_ADC_IER_JEOCIE_Pos = 0x5
	// Bit mask of JEOCIE field.
	ADC_ADC_IER_JEOCIE_Msk = 0x20
	// Bit JEOCIE.
	ADC_ADC_IER_JEOCIE = 0x20
	// Position of JEOSIE field.
	ADC_ADC_IER_JEOSIE_Pos = 0x6
	// Bit mask of JEOSIE field.
	ADC_ADC_IER_JEOSIE_Msk = 0x40
	// Bit JEOSIE.
	ADC_ADC_IER_JEOSIE = 0x40
	// Position of AWD1IE field.
	ADC_ADC_IER_AWD1IE_Pos = 0x7
	// Bit mask of AWD1IE field.
	ADC_ADC_IER_AWD1IE_Msk = 0x80
	// Bit AWD1IE.
	ADC_ADC_IER_AWD1IE = 0x80
	// Position of AWD2IE field.
	ADC_ADC_IER_AWD2IE_Pos = 0x8
	// Bit mask of AWD2IE field.
	ADC_ADC_IER_AWD2IE_Msk = 0x100
	// Bit AWD2IE.
	ADC_ADC_IER_AWD2IE = 0x100
	// Position of AWD3IE field.
	ADC_ADC_IER_AWD3IE_Pos = 0x9
	// Bit mask of AWD3IE field.
	ADC_ADC_IER_AWD3IE_Msk = 0x200
	// Bit AWD3IE.
	ADC_ADC_IER_AWD3IE = 0x200
	// Position of JQOVFIE field.
	ADC_ADC_IER_JQOVFIE_Pos = 0xa
	// Bit mask of JQOVFIE field.
	ADC_ADC_IER_JQOVFIE_Msk = 0x400
	// Bit JQOVFIE.
	ADC_ADC_IER_JQOVFIE = 0x400

	// ADC_CR: ADC control register
	// Position of ADEN field.
	ADC_ADC_CR_ADEN_Pos = 0x0
	// Bit mask of ADEN field.
	ADC_ADC_CR_ADEN_Msk = 0x1
	// Bit ADEN.
	ADC_ADC_CR_ADEN = 0x1
	// Position of ADDIS field.
	ADC_ADC_CR_ADDIS_Pos = 0x1
	// Bit mask of ADDIS field.
	ADC_ADC_CR_ADDIS_Msk = 0x2
	// Bit ADDIS.
	ADC_ADC_CR_ADDIS = 0x2
	// Position of ADSTART field.
	ADC_ADC_CR_ADSTART_Pos = 0x2
	// Bit mask of ADSTART field.
	ADC_ADC_CR_ADSTART_Msk = 0x4
	// Bit ADSTART.
	ADC_ADC_CR_ADSTART = 0x4
	// Position of JADSTART field.
	ADC_ADC_CR_JADSTART_Pos = 0x3
	// Bit mask of JADSTART field.
	ADC_ADC_CR_JADSTART_Msk = 0x8
	// Bit JADSTART.
	ADC_ADC_CR_JADSTART = 0x8
	// Position of ADSTP field.
	ADC_ADC_CR_ADSTP_Pos = 0x4
	// Bit mask of ADSTP field.
	ADC_ADC_CR_ADSTP_Msk = 0x10
	// Bit ADSTP.
	ADC_ADC_CR_ADSTP = 0x10
	// Position of JADSTP field.
	ADC_ADC_CR_JADSTP_Pos = 0x5
	// Bit mask of JADSTP field.
	ADC_ADC_CR_JADSTP_Msk = 0x20
	// Bit JADSTP.
	ADC_ADC_CR_JADSTP = 0x20
	// Position of BOOST field.
	ADC_ADC_CR_BOOST_Pos = 0x8
	// Bit mask of BOOST field.
	ADC_ADC_CR_BOOST_Msk = 0x100
	// Bit BOOST.
	ADC_ADC_CR_BOOST = 0x100
	// Position of ADCALLIN field.
	ADC_ADC_CR_ADCALLIN_Pos = 0x10
	// Bit mask of ADCALLIN field.
	ADC_ADC_CR_ADCALLIN_Msk = 0x10000
	// Bit ADCALLIN.
	ADC_ADC_CR_ADCALLIN = 0x10000
	// Position of LINCALRDYW1 field.
	ADC_ADC_CR_LINCALRDYW1_Pos = 0x16
	// Bit mask of LINCALRDYW1 field.
	ADC_ADC_CR_LINCALRDYW1_Msk = 0x400000
	// Bit LINCALRDYW1.
	ADC_ADC_CR_LINCALRDYW1 = 0x400000
	// Position of LINCALRDYW2 field.
	ADC_ADC_CR_LINCALRDYW2_Pos = 0x17
	// Bit mask of LINCALRDYW2 field.
	ADC_ADC_CR_LINCALRDYW2_Msk = 0x800000
	// Bit LINCALRDYW2.
	ADC_ADC_CR_LINCALRDYW2 = 0x800000
	// Position of LINCALRDYW3 field.
	ADC_ADC_CR_LINCALRDYW3_Pos = 0x18
	// Bit mask of LINCALRDYW3 field.
	ADC_ADC_CR_LINCALRDYW3_Msk = 0x1000000
	// Bit LINCALRDYW3.
	ADC_ADC_CR_LINCALRDYW3 = 0x1000000
	// Position of LINCALRDYW4 field.
	ADC_ADC_CR_LINCALRDYW4_Pos = 0x19
	// Bit mask of LINCALRDYW4 field.
	ADC_ADC_CR_LINCALRDYW4_Msk = 0x2000000
	// Bit LINCALRDYW4.
	ADC_ADC_CR_LINCALRDYW4 = 0x2000000
	// Position of LINCALRDYW5 field.
	ADC_ADC_CR_LINCALRDYW5_Pos = 0x1a
	// Bit mask of LINCALRDYW5 field.
	ADC_ADC_CR_LINCALRDYW5_Msk = 0x4000000
	// Bit LINCALRDYW5.
	ADC_ADC_CR_LINCALRDYW5 = 0x4000000
	// Position of LINCALRDYW6 field.
	ADC_ADC_CR_LINCALRDYW6_Pos = 0x1b
	// Bit mask of LINCALRDYW6 field.
	ADC_ADC_CR_LINCALRDYW6_Msk = 0x8000000
	// Bit LINCALRDYW6.
	ADC_ADC_CR_LINCALRDYW6 = 0x8000000
	// Position of ADVREGEN field.
	ADC_ADC_CR_ADVREGEN_Pos = 0x1c
	// Bit mask of ADVREGEN field.
	ADC_ADC_CR_ADVREGEN_Msk = 0x10000000
	// Bit ADVREGEN.
	ADC_ADC_CR_ADVREGEN = 0x10000000
	// Position of DEEPPWD field.
	ADC_ADC_CR_DEEPPWD_Pos = 0x1d
	// Bit mask of DEEPPWD field.
	ADC_ADC_CR_DEEPPWD_Msk = 0x20000000
	// Bit DEEPPWD.
	ADC_ADC_CR_DEEPPWD = 0x20000000
	// Position of ADCALDIF field.
	ADC_ADC_CR_ADCALDIF_Pos = 0x1e
	// Bit mask of ADCALDIF field.
	ADC_ADC_CR_ADCALDIF_Msk = 0x40000000
	// Bit ADCALDIF.
	ADC_ADC_CR_ADCALDIF = 0x40000000
	// Position of ADCAL field.
	ADC_ADC_CR_ADCAL_Pos = 0x1f
	// Bit mask of ADCAL field.
	ADC_ADC_CR_ADCAL_Msk = 0x80000000
	// Bit ADCAL.
	ADC_ADC_CR_ADCAL = 0x80000000

	// ADC_CFGR: ADC configuration register
	// Position of DMNGT field.
	ADC_ADC_CFGR_DMNGT_Pos = 0x0
	// Bit mask of DMNGT field.
	ADC_ADC_CFGR_DMNGT_Msk = 0x3
	// Position of RES field.
	ADC_ADC_CFGR_RES_Pos = 0x2
	// Bit mask of RES field.
	ADC_ADC_CFGR_RES_Msk = 0x1c
	// Position of EXTSEL field.
	ADC_ADC_CFGR_EXTSEL_Pos = 0x5
	// Bit mask of EXTSEL field.
	ADC_ADC_CFGR_EXTSEL_Msk = 0x3e0
	// Position of EXTEN field.
	ADC_ADC_CFGR_EXTEN_Pos = 0xa
	// Bit mask of EXTEN field.
	ADC_ADC_CFGR_EXTEN_Msk = 0xc00
	// Position of OVRMOD field.
	ADC_ADC_CFGR_OVRMOD_Pos = 0xc
	// Bit mask of OVRMOD field.
	ADC_ADC_CFGR_OVRMOD_Msk = 0x1000
	// Bit OVRMOD.
	ADC_ADC_CFGR_OVRMOD = 0x1000
	// Position of CONT field.
	ADC_ADC_CFGR_CONT_Pos = 0xd
	// Bit mask of CONT field.
	ADC_ADC_CFGR_CONT_Msk = 0x2000
	// Bit CONT.
	ADC_ADC_CFGR_CONT = 0x2000
	// Position of AUTDLY field.
	ADC_ADC_CFGR_AUTDLY_Pos = 0xe
	// Bit mask of AUTDLY field.
	ADC_ADC_CFGR_AUTDLY_Msk = 0x4000
	// Bit AUTDLY.
	ADC_ADC_CFGR_AUTDLY = 0x4000
	// Position of DISCEN field.
	ADC_ADC_CFGR_DISCEN_Pos = 0x10
	// Bit mask of DISCEN field.
	ADC_ADC_CFGR_DISCEN_Msk = 0x10000
	// Bit DISCEN.
	ADC_ADC_CFGR_DISCEN = 0x10000
	// Position of DISCNUM field.
	ADC_ADC_CFGR_DISCNUM_Pos = 0x11
	// Bit mask of DISCNUM field.
	ADC_ADC_CFGR_DISCNUM_Msk = 0xe0000
	// Position of JDISCEN field.
	ADC_ADC_CFGR_JDISCEN_Pos = 0x14
	// Bit mask of JDISCEN field.
	ADC_ADC_CFGR_JDISCEN_Msk = 0x100000
	// Bit JDISCEN.
	ADC_ADC_CFGR_JDISCEN = 0x100000
	// Position of JQM field.
	ADC_ADC_CFGR_JQM_Pos = 0x15
	// Bit mask of JQM field.
	ADC_ADC_CFGR_JQM_Msk = 0x200000
	// Bit JQM.
	ADC_ADC_CFGR_JQM = 0x200000
	// Position of AWD1SGL field.
	ADC_ADC_CFGR_AWD1SGL_Pos = 0x16
	// Bit mask of AWD1SGL field.
	ADC_ADC_CFGR_AWD1SGL_Msk = 0x400000
	// Bit AWD1SGL.
	ADC_ADC_CFGR_AWD1SGL = 0x400000
	// Position of AWD1EN field.
	ADC_ADC_CFGR_AWD1EN_Pos = 0x17
	// Bit mask of AWD1EN field.
	ADC_ADC_CFGR_AWD1EN_Msk = 0x800000
	// Bit AWD1EN.
	ADC_ADC_CFGR_AWD1EN = 0x800000
	// Position of JAWD1EN field.
	ADC_ADC_CFGR_JAWD1EN_Pos = 0x18
	// Bit mask of JAWD1EN field.
	ADC_ADC_CFGR_JAWD1EN_Msk = 0x1000000
	// Bit JAWD1EN.
	ADC_ADC_CFGR_JAWD1EN = 0x1000000
	// Position of JAUTO field.
	ADC_ADC_CFGR_JAUTO_Pos = 0x19
	// Bit mask of JAUTO field.
	ADC_ADC_CFGR_JAUTO_Msk = 0x2000000
	// Bit JAUTO.
	ADC_ADC_CFGR_JAUTO = 0x2000000
	// Position of AWD1CH field.
	ADC_ADC_CFGR_AWD1CH_Pos = 0x1a
	// Bit mask of AWD1CH field.
	ADC_ADC_CFGR_AWD1CH_Msk = 0x7c000000
	// Position of JQDIS field.
	ADC_ADC_CFGR_JQDIS_Pos = 0x1f
	// Bit mask of JQDIS field.
	ADC_ADC_CFGR_JQDIS_Msk = 0x80000000
	// Bit JQDIS.
	ADC_ADC_CFGR_JQDIS = 0x80000000

	// ADC_CFGR2: ADC configuration register 2
	// Position of ROVSE field.
	ADC_ADC_CFGR2_ROVSE_Pos = 0x0
	// Bit mask of ROVSE field.
	ADC_ADC_CFGR2_ROVSE_Msk = 0x1
	// Bit ROVSE.
	ADC_ADC_CFGR2_ROVSE = 0x1
	// Position of JOVSE field.
	ADC_ADC_CFGR2_JOVSE_Pos = 0x1
	// Bit mask of JOVSE field.
	ADC_ADC_CFGR2_JOVSE_Msk = 0x2
	// Bit JOVSE.
	ADC_ADC_CFGR2_JOVSE = 0x2
	// Position of OVSS field.
	ADC_ADC_CFGR2_OVSS_Pos = 0x5
	// Bit mask of OVSS field.
	ADC_ADC_CFGR2_OVSS_Msk = 0x1e0
	// Position of TROVS field.
	ADC_ADC_CFGR2_TROVS_Pos = 0x9
	// Bit mask of TROVS field.
	ADC_ADC_CFGR2_TROVS_Msk = 0x200
	// Bit TROVS.
	ADC_ADC_CFGR2_TROVS = 0x200
	// Position of ROVSM field.
	ADC_ADC_CFGR2_ROVSM_Pos = 0xa
	// Bit mask of ROVSM field.
	ADC_ADC_CFGR2_ROVSM_Msk = 0x400
	// Bit ROVSM.
	ADC_ADC_CFGR2_ROVSM = 0x400
	// Position of RSHIFT1 field.
	ADC_ADC_CFGR2_RSHIFT1_Pos = 0xb
	// Bit mask of RSHIFT1 field.
	ADC_ADC_CFGR2_RSHIFT1_Msk = 0x800
	// Bit RSHIFT1.
	ADC_ADC_CFGR2_RSHIFT1 = 0x800
	// Position of RSHIFT2 field.
	ADC_ADC_CFGR2_RSHIFT2_Pos = 0xc
	// Bit mask of RSHIFT2 field.
	ADC_ADC_CFGR2_RSHIFT2_Msk = 0x1000
	// Bit RSHIFT2.
	ADC_ADC_CFGR2_RSHIFT2 = 0x1000
	// Position of RSHIFT3 field.
	ADC_ADC_CFGR2_RSHIFT3_Pos = 0xd
	// Bit mask of RSHIFT3 field.
	ADC_ADC_CFGR2_RSHIFT3_Msk = 0x2000
	// Bit RSHIFT3.
	ADC_ADC_CFGR2_RSHIFT3 = 0x2000
	// Position of RSHIFT4 field.
	ADC_ADC_CFGR2_RSHIFT4_Pos = 0xe
	// Bit mask of RSHIFT4 field.
	ADC_ADC_CFGR2_RSHIFT4_Msk = 0x4000
	// Bit RSHIFT4.
	ADC_ADC_CFGR2_RSHIFT4 = 0x4000
	// Position of OSVR field.
	ADC_ADC_CFGR2_OSVR_Pos = 0x10
	// Bit mask of OSVR field.
	ADC_ADC_CFGR2_OSVR_Msk = 0x3ff0000
	// Position of LSHIFT field.
	ADC_ADC_CFGR2_LSHIFT_Pos = 0x1c
	// Bit mask of LSHIFT field.
	ADC_ADC_CFGR2_LSHIFT_Msk = 0xf0000000

	// ADC_SMPR1: ADC sample time register 1
	// Position of SMP0 field.
	ADC_ADC_SMPR1_SMP0_Pos = 0x0
	// Bit mask of SMP0 field.
	ADC_ADC_SMPR1_SMP0_Msk = 0x7
	// Position of SMP1 field.
	ADC_ADC_SMPR1_SMP1_Pos = 0x3
	// Bit mask of SMP1 field.
	ADC_ADC_SMPR1_SMP1_Msk = 0x38
	// Position of SMP2 field.
	ADC_ADC_SMPR1_SMP2_Pos = 0x6
	// Bit mask of SMP2 field.
	ADC_ADC_SMPR1_SMP2_Msk = 0x1c0
	// Position of SMP3 field.
	ADC_ADC_SMPR1_SMP3_Pos = 0x9
	// Bit mask of SMP3 field.
	ADC_ADC_SMPR1_SMP3_Msk = 0xe00
	// Position of SMP4 field.
	ADC_ADC_SMPR1_SMP4_Pos = 0xc
	// Bit mask of SMP4 field.
	ADC_ADC_SMPR1_SMP4_Msk = 0x7000
	// Position of SMP5 field.
	ADC_ADC_SMPR1_SMP5_Pos = 0xf
	// Bit mask of SMP5 field.
	ADC_ADC_SMPR1_SMP5_Msk = 0x38000
	// Position of SMP6 field.
	ADC_ADC_SMPR1_SMP6_Pos = 0x12
	// Bit mask of SMP6 field.
	ADC_ADC_SMPR1_SMP6_Msk = 0x1c0000
	// Position of SMP7 field.
	ADC_ADC_SMPR1_SMP7_Pos = 0x15
	// Bit mask of SMP7 field.
	ADC_ADC_SMPR1_SMP7_Msk = 0xe00000
	// Position of SMP8 field.
	ADC_ADC_SMPR1_SMP8_Pos = 0x18
	// Bit mask of SMP8 field.
	ADC_ADC_SMPR1_SMP8_Msk = 0x7000000
	// Position of SMP9 field.
	ADC_ADC_SMPR1_SMP9_Pos = 0x1b
	// Bit mask of SMP9 field.
	ADC_ADC_SMPR1_SMP9_Msk = 0x38000000

	// ADC_SMPR2: ADC sample time register 2
	// Position of SMP10 field.
	ADC_ADC_SMPR2_SMP10_Pos = 0x0
	// Bit mask of SMP10 field.
	ADC_ADC_SMPR2_SMP10_Msk = 0x7
	// Position of SMP11 field.
	ADC_ADC_SMPR2_SMP11_Pos = 0x3
	// Bit mask of SMP11 field.
	ADC_ADC_SMPR2_SMP11_Msk = 0x38
	// Position of SMP12 field.
	ADC_ADC_SMPR2_SMP12_Pos = 0x6
	// Bit mask of SMP12 field.
	ADC_ADC_SMPR2_SMP12_Msk = 0x1c0
	// Position of SMP13 field.
	ADC_ADC_SMPR2_SMP13_Pos = 0x9
	// Bit mask of SMP13 field.
	ADC_ADC_SMPR2_SMP13_Msk = 0xe00
	// Position of SMP14 field.
	ADC_ADC_SMPR2_SMP14_Pos = 0xc
	// Bit mask of SMP14 field.
	ADC_ADC_SMPR2_SMP14_Msk = 0x7000
	// Position of SMP15 field.
	ADC_ADC_SMPR2_SMP15_Pos = 0xf
	// Bit mask of SMP15 field.
	ADC_ADC_SMPR2_SMP15_Msk = 0x38000
	// Position of SMP16 field.
	ADC_ADC_SMPR2_SMP16_Pos = 0x12
	// Bit mask of SMP16 field.
	ADC_ADC_SMPR2_SMP16_Msk = 0x1c0000
	// Position of SMP17 field.
	ADC_ADC_SMPR2_SMP17_Pos = 0x15
	// Bit mask of SMP17 field.
	ADC_ADC_SMPR2_SMP17_Msk = 0xe00000
	// Position of SMP18 field.
	ADC_ADC_SMPR2_SMP18_Pos = 0x18
	// Bit mask of SMP18 field.
	ADC_ADC_SMPR2_SMP18_Msk = 0x7000000
	// Position of SMP19 field.
	ADC_ADC_SMPR2_SMP19_Pos = 0x1b
	// Bit mask of SMP19 field.
	ADC_ADC_SMPR2_SMP19_Msk = 0x38000000

	// ADC_PCSEL: ADC channel preselection register
	// Position of PCSEL0 field.
	ADC_ADC_PCSEL_PCSEL0_Pos = 0x0
	// Bit mask of PCSEL0 field.
	ADC_ADC_PCSEL_PCSEL0_Msk = 0x1
	// Bit PCSEL0.
	ADC_ADC_PCSEL_PCSEL0 = 0x1
	// Position of PCSEL1 field.
	ADC_ADC_PCSEL_PCSEL1_Pos = 0x1
	// Bit mask of PCSEL1 field.
	ADC_ADC_PCSEL_PCSEL1_Msk = 0x2
	// Bit PCSEL1.
	ADC_ADC_PCSEL_PCSEL1 = 0x2
	// Position of PCSEL2 field.
	ADC_ADC_PCSEL_PCSEL2_Pos = 0x2
	// Bit mask of PCSEL2 field.
	ADC_ADC_PCSEL_PCSEL2_Msk = 0x4
	// Bit PCSEL2.
	ADC_ADC_PCSEL_PCSEL2 = 0x4
	// Position of PCSEL3 field.
	ADC_ADC_PCSEL_PCSEL3_Pos = 0x3
	// Bit mask of PCSEL3 field.
	ADC_ADC_PCSEL_PCSEL3_Msk = 0x8
	// Bit PCSEL3.
	ADC_ADC_PCSEL_PCSEL3 = 0x8
	// Position of PCSEL4 field.
	ADC_ADC_PCSEL_PCSEL4_Pos = 0x4
	// Bit mask of PCSEL4 field.
	ADC_ADC_PCSEL_PCSEL4_Msk = 0x10
	// Bit PCSEL4.
	ADC_ADC_PCSEL_PCSEL4 = 0x10
	// Position of PCSEL5 field.
	ADC_ADC_PCSEL_PCSEL5_Pos = 0x5
	// Bit mask of PCSEL5 field.
	ADC_ADC_PCSEL_PCSEL5_Msk = 0x20
	// Bit PCSEL5.
	ADC_ADC_PCSEL_PCSEL5 = 0x20
	// Position of PCSEL6 field.
	ADC_ADC_PCSEL_PCSEL6_Pos = 0x6
	// Bit mask of PCSEL6 field.
	ADC_ADC_PCSEL_PCSEL6_Msk = 0x40
	// Bit PCSEL6.
	ADC_ADC_PCSEL_PCSEL6 = 0x40
	// Position of PCSEL7 field.
	ADC_ADC_PCSEL_PCSEL7_Pos = 0x7
	// Bit mask of PCSEL7 field.
	ADC_ADC_PCSEL_PCSEL7_Msk = 0x80
	// Bit PCSEL7.
	ADC_ADC_PCSEL_PCSEL7 = 0x80
	// Position of PCSEL8 field.
	ADC_ADC_PCSEL_PCSEL8_Pos = 0x8
	// Bit mask of PCSEL8 field.
	ADC_ADC_PCSEL_PCSEL8_Msk = 0x100
	// Bit PCSEL8.
	ADC_ADC_PCSEL_PCSEL8 = 0x100
	// Position of PCSEL9 field.
	ADC_ADC_PCSEL_PCSEL9_Pos = 0x9
	// Bit mask of PCSEL9 field.
	ADC_ADC_PCSEL_PCSEL9_Msk = 0x200
	// Bit PCSEL9.
	ADC_ADC_PCSEL_PCSEL9 = 0x200
	// Position of PCSEL10 field.
	ADC_ADC_PCSEL_PCSEL10_Pos = 0xa
	// Bit mask of PCSEL10 field.
	ADC_ADC_PCSEL_PCSEL10_Msk = 0x400
	// Bit PCSEL10.
	ADC_ADC_PCSEL_PCSEL10 = 0x400
	// Position of PCSEL11 field.
	ADC_ADC_PCSEL_PCSEL11_Pos = 0xb
	// Bit mask of PCSEL11 field.
	ADC_ADC_PCSEL_PCSEL11_Msk = 0x800
	// Bit PCSEL11.
	ADC_ADC_PCSEL_PCSEL11 = 0x800
	// Position of PCSEL12 field.
	ADC_ADC_PCSEL_PCSEL12_Pos = 0xc
	// Bit mask of PCSEL12 field.
	ADC_ADC_PCSEL_PCSEL12_Msk = 0x1000
	// Bit PCSEL12.
	ADC_ADC_PCSEL_PCSEL12 = 0x1000
	// Position of PCSEL13 field.
	ADC_ADC_PCSEL_PCSEL13_Pos = 0xd
	// Bit mask of PCSEL13 field.
	ADC_ADC_PCSEL_PCSEL13_Msk = 0x2000
	// Bit PCSEL13.
	ADC_ADC_PCSEL_PCSEL13 = 0x2000
	// Position of PCSEL14 field.
	ADC_ADC_PCSEL_PCSEL14_Pos = 0xe
	// Bit mask of PCSEL14 field.
	ADC_ADC_PCSEL_PCSEL14_Msk = 0x4000
	// Bit PCSEL14.
	ADC_ADC_PCSEL_PCSEL14 = 0x4000
	// Position of PCSEL15 field.
	ADC_ADC_PCSEL_PCSEL15_Pos = 0xf
	// Bit mask of PCSEL15 field.
	ADC_ADC_PCSEL_PCSEL15_Msk = 0x8000
	// Bit PCSEL15.
	ADC_ADC_PCSEL_PCSEL15 = 0x8000
	// Position of PCSEL16 field.
	ADC_ADC_PCSEL_PCSEL16_Pos = 0x10
	// Bit mask of PCSEL16 field.
	ADC_ADC_PCSEL_PCSEL16_Msk = 0x10000
	// Bit PCSEL16.
	ADC_ADC_PCSEL_PCSEL16 = 0x10000
	// Position of PCSEL17 field.
	ADC_ADC_PCSEL_PCSEL17_Pos = 0x11
	// Bit mask of PCSEL17 field.
	ADC_ADC_PCSEL_PCSEL17_Msk = 0x20000
	// Bit PCSEL17.
	ADC_ADC_PCSEL_PCSEL17 = 0x20000
	// Position of PCSEL18 field.
	ADC_ADC_PCSEL_PCSEL18_Pos = 0x12
	// Bit mask of PCSEL18 field.
	ADC_ADC_PCSEL_PCSEL18_Msk = 0x40000
	// Bit PCSEL18.
	ADC_ADC_PCSEL_PCSEL18 = 0x40000
	// Position of PCSEL19 field.
	ADC_ADC_PCSEL_PCSEL19_Pos = 0x13
	// Bit mask of PCSEL19 field.
	ADC_ADC_PCSEL_PCSEL19_Msk = 0x80000
	// Bit PCSEL19.
	ADC_ADC_PCSEL_PCSEL19 = 0x80000

	// ADC_LTR1: ADC watchdog threshold register 1
	// Position of LTR1 field.
	ADC_ADC_LTR1_LTR1_Pos = 0x0
	// Bit mask of LTR1 field.
	ADC_ADC_LTR1_LTR1_Msk = 0x3ffffff

	// ADC_HTR1: ADC watchdog threshold register 1
	// Position of HTR1 field.
	ADC_ADC_HTR1_HTR1_Pos = 0x0
	// Bit mask of HTR1 field.
	ADC_ADC_HTR1_HTR1_Msk = 0x3ffffff

	// ADC_SQR1: ADC regular sequence register 1
	// Position of L field.
	ADC_ADC_SQR1_L_Pos = 0x0
	// Bit mask of L field.
	ADC_ADC_SQR1_L_Msk = 0xf
	// Position of SQ1 field.
	ADC_ADC_SQR1_SQ1_Pos = 0x6
	// Bit mask of SQ1 field.
	ADC_ADC_SQR1_SQ1_Msk = 0x7c0
	// Position of SQ2 field.
	ADC_ADC_SQR1_SQ2_Pos = 0xc
	// Bit mask of SQ2 field.
	ADC_ADC_SQR1_SQ2_Msk = 0x1f000
	// Position of SQ3 field.
	ADC_ADC_SQR1_SQ3_Pos = 0x12
	// Bit mask of SQ3 field.
	ADC_ADC_SQR1_SQ3_Msk = 0x7c0000
	// Position of SQ4 field.
	ADC_ADC_SQR1_SQ4_Pos = 0x18
	// Bit mask of SQ4 field.
	ADC_ADC_SQR1_SQ4_Msk = 0x1f000000

	// ADC_SQR2: ADC regular sequence register 2
	// Position of SQ5 field.
	ADC_ADC_SQR2_SQ5_Pos = 0x0
	// Bit mask of SQ5 field.
	ADC_ADC_SQR2_SQ5_Msk = 0x1f
	// Position of SQ6 field.
	ADC_ADC_SQR2_SQ6_Pos = 0x6
	// Bit mask of SQ6 field.
	ADC_ADC_SQR2_SQ6_Msk = 0x7c0
	// Position of SQ7 field.
	ADC_ADC_SQR2_SQ7_Pos = 0xc
	// Bit mask of SQ7 field.
	ADC_ADC_SQR2_SQ7_Msk = 0x1f000
	// Position of SQ8 field.
	ADC_ADC_SQR2_SQ8_Pos = 0x12
	// Bit mask of SQ8 field.
	ADC_ADC_SQR2_SQ8_Msk = 0x7c0000
	// Position of SQ9 field.
	ADC_ADC_SQR2_SQ9_Pos = 0x18
	// Bit mask of SQ9 field.
	ADC_ADC_SQR2_SQ9_Msk = 0x1f000000

	// ADC_SQR3: ADC regular sequence register 3
	// Position of SQ10 field.
	ADC_ADC_SQR3_SQ10_Pos = 0x0
	// Bit mask of SQ10 field.
	ADC_ADC_SQR3_SQ10_Msk = 0x1f
	// Position of SQ11 field.
	ADC_ADC_SQR3_SQ11_Pos = 0x6
	// Bit mask of SQ11 field.
	ADC_ADC_SQR3_SQ11_Msk = 0x7c0
	// Position of SQ12 field.
	ADC_ADC_SQR3_SQ12_Pos = 0xc
	// Bit mask of SQ12 field.
	ADC_ADC_SQR3_SQ12_Msk = 0x1f000
	// Position of SQ13 field.
	ADC_ADC_SQR3_SQ13_Pos = 0x12
	// Bit mask of SQ13 field.
	ADC_ADC_SQR3_SQ13_Msk = 0x7c0000
	// Position of SQ14 field.
	ADC_ADC_SQR3_SQ14_Pos = 0x18
	// Bit mask of SQ14 field.
	ADC_ADC_SQR3_SQ14_Msk = 0x1f000000

	// ADC_SQR4: ADC regular sequence register 4
	// Position of SQ15 field.
	ADC_ADC_SQR4_SQ15_Pos = 0x0
	// Bit mask of SQ15 field.
	ADC_ADC_SQR4_SQ15_Msk = 0x1f
	// Position of SQ16 field.
	ADC_ADC_SQR4_SQ16_Pos = 0x6
	// Bit mask of SQ16 field.
	ADC_ADC_SQR4_SQ16_Msk = 0x7c0

	// ADC_DR: ADC regular Data Register
	// Position of RDATA field.
	ADC_ADC_DR_RDATA_Pos = 0x0
	// Bit mask of RDATA field.
	ADC_ADC_DR_RDATA_Msk = 0xffffffff

	// ADC_JSQR: ADC injected sequence register
	// Position of JL field.
	ADC_ADC_JSQR_JL_Pos = 0x0
	// Bit mask of JL field.
	ADC_ADC_JSQR_JL_Msk = 0x3
	// Position of JEXTSEL field.
	ADC_ADC_JSQR_JEXTSEL_Pos = 0x2
	// Bit mask of JEXTSEL field.
	ADC_ADC_JSQR_JEXTSEL_Msk = 0x7c
	// Position of JEXTEN field.
	ADC_ADC_JSQR_JEXTEN_Pos = 0x7
	// Bit mask of JEXTEN field.
	ADC_ADC_JSQR_JEXTEN_Msk = 0x180
	// Position of JSQ1 field.
	ADC_ADC_JSQR_JSQ1_Pos = 0x9
	// Bit mask of JSQ1 field.
	ADC_ADC_JSQR_JSQ1_Msk = 0x3e00
	// Position of JSQ2 field.
	ADC_ADC_JSQR_JSQ2_Pos = 0xf
	// Bit mask of JSQ2 field.
	ADC_ADC_JSQR_JSQ2_Msk = 0xf8000
	// Position of JSQ3 field.
	ADC_ADC_JSQR_JSQ3_Pos = 0x15
	// Bit mask of JSQ3 field.
	ADC_ADC_JSQR_JSQ3_Msk = 0x3e00000
	// Position of JSQ4 field.
	ADC_ADC_JSQR_JSQ4_Pos = 0x1b
	// Bit mask of JSQ4 field.
	ADC_ADC_JSQR_JSQ4_Msk = 0xf8000000

	// ADC_OFR1: ADC offset register
	// Position of OFFSET1 field.
	ADC_ADC_OFR1_OFFSET1_Pos = 0x0
	// Bit mask of OFFSET1 field.
	ADC_ADC_OFR1_OFFSET1_Msk = 0x3ffffff
	// Position of OFFSET1_CH field.
	ADC_ADC_OFR1_OFFSET1_CH_Pos = 0x1a
	// Bit mask of OFFSET1_CH field.
	ADC_ADC_OFR1_OFFSET1_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC_ADC_OFR1_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_ADC_OFR1_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_ADC_OFR1_SSATE = 0x80000000

	// ADC_OFR2: ADC offset register
	// Position of OFFSET2 field.
	ADC_ADC_OFR2_OFFSET2_Pos = 0x0
	// Bit mask of OFFSET2 field.
	ADC_ADC_OFR2_OFFSET2_Msk = 0x3ffffff
	// Position of OFFSET2_CH field.
	ADC_ADC_OFR2_OFFSET2_CH_Pos = 0x1a
	// Bit mask of OFFSET2_CH field.
	ADC_ADC_OFR2_OFFSET2_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC_ADC_OFR2_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_ADC_OFR2_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_ADC_OFR2_SSATE = 0x80000000

	// ADC_OFR3: ADC offset register
	// Position of OFFSET3 field.
	ADC_ADC_OFR3_OFFSET3_Pos = 0x0
	// Bit mask of OFFSET3 field.
	ADC_ADC_OFR3_OFFSET3_Msk = 0x3ffffff
	// Position of OFFSET3_CH field.
	ADC_ADC_OFR3_OFFSET3_CH_Pos = 0x1a
	// Bit mask of OFFSET3_CH field.
	ADC_ADC_OFR3_OFFSET3_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC_ADC_OFR3_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_ADC_OFR3_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_ADC_OFR3_SSATE = 0x80000000

	// ADC_OFR4: ADC offset register
	// Position of OFFSET4 field.
	ADC_ADC_OFR4_OFFSET4_Pos = 0x0
	// Bit mask of OFFSET4 field.
	ADC_ADC_OFR4_OFFSET4_Msk = 0x3ffffff
	// Position of OFFSET4_CH field.
	ADC_ADC_OFR4_OFFSET4_CH_Pos = 0x1a
	// Bit mask of OFFSET4_CH field.
	ADC_ADC_OFR4_OFFSET4_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC_ADC_OFR4_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_ADC_OFR4_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_ADC_OFR4_SSATE = 0x80000000

	// ADC_JDR1: ADC injected data register
	// Position of JDATA field.
	ADC_ADC_JDR1_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC_ADC_JDR1_JDATA_Msk = 0xffffffff

	// ADC_JDR2: ADC injected data register
	// Position of JDATA field.
	ADC_ADC_JDR2_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC_ADC_JDR2_JDATA_Msk = 0xffffffff

	// ADC_JDR3: ADC injected data register
	// Position of JDATA field.
	ADC_ADC_JDR3_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC_ADC_JDR3_JDATA_Msk = 0xffffffff

	// ADC_JDR4: ADC injected data register
	// Position of JDATA field.
	ADC_ADC_JDR4_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC_ADC_JDR4_JDATA_Msk = 0xffffffff

	// ADC_AWD2CR: ADC analog watchdog 2 configuration register
	// Position of AWD2CH field.
	ADC_ADC_AWD2CR_AWD2CH_Pos = 0x0
	// Bit mask of AWD2CH field.
	ADC_ADC_AWD2CR_AWD2CH_Msk = 0xfffff

	// ADC_AWD3CR: ADC analog watchdog 3 configuration register
	// Position of AWD3CH field.
	ADC_ADC_AWD3CR_AWD3CH_Pos = 0x0
	// Bit mask of AWD3CH field.
	ADC_ADC_AWD3CR_AWD3CH_Msk = 0xfffff

	// ADC_LTR2: ADC watchdog lower threshold register 2
	// Position of LTR2 field.
	ADC_ADC_LTR2_LTR2_Pos = 0x0
	// Bit mask of LTR2 field.
	ADC_ADC_LTR2_LTR2_Msk = 0x3ffffff

	// ADC_HTR2: ADC watchdog higher threshold register 2
	// Position of HTR2 field.
	ADC_ADC_HTR2_HTR2_Pos = 0x0
	// Bit mask of HTR2 field.
	ADC_ADC_HTR2_HTR2_Msk = 0x3ffffff

	// ADC_LTR3: ADC watchdog lower threshold register 3
	// Position of LTR3 field.
	ADC_ADC_LTR3_LTR3_Pos = 0x0
	// Bit mask of LTR3 field.
	ADC_ADC_LTR3_LTR3_Msk = 0x3ffffff

	// ADC_HTR3: ADC watchdog higher threshold register 3
	// Position of HTR3 field.
	ADC_ADC_HTR3_HTR3_Pos = 0x0
	// Bit mask of HTR3 field.
	ADC_ADC_HTR3_HTR3_Msk = 0x3ffffff

	// ADC_DIFSEL: ADC differential mode selection register
	// Position of DIFSEL field.
	ADC_ADC_DIFSEL_DIFSEL_Pos = 0x0
	// Bit mask of DIFSEL field.
	ADC_ADC_DIFSEL_DIFSEL_Msk = 0xfffff

	// ADC_CALFACT: ADC calibration factors register
	// Position of CALFACT_S field.
	ADC_ADC_CALFACT_CALFACT_S_Pos = 0x0
	// Bit mask of CALFACT_S field.
	ADC_ADC_CALFACT_CALFACT_S_Msk = 0x7ff
	// Position of CALFACT_D field.
	ADC_ADC_CALFACT_CALFACT_D_Pos = 0x10
	// Bit mask of CALFACT_D field.
	ADC_ADC_CALFACT_CALFACT_D_Msk = 0x7ff0000

	// ADC_CALFACT2: ADC calibration factor register 2
	// Position of LINCALFACT field.
	ADC_ADC_CALFACT2_LINCALFACT_Pos = 0x0
	// Bit mask of LINCALFACT field.
	ADC_ADC_CALFACT2_LINCALFACT_Msk = 0x3fffffff
)

// Bitfields for ADC2: ADC2
const (
	// ADC_ISR: ADC interrupt and status register
	// Position of ADRDY field.
	ADC2_ADC_ISR_ADRDY_Pos = 0x0
	// Bit mask of ADRDY field.
	ADC2_ADC_ISR_ADRDY_Msk = 0x1
	// Bit ADRDY.
	ADC2_ADC_ISR_ADRDY = 0x1
	// Position of EOSMP field.
	ADC2_ADC_ISR_EOSMP_Pos = 0x1
	// Bit mask of EOSMP field.
	ADC2_ADC_ISR_EOSMP_Msk = 0x2
	// Bit EOSMP.
	ADC2_ADC_ISR_EOSMP = 0x2
	// Position of EOC field.
	ADC2_ADC_ISR_EOC_Pos = 0x2
	// Bit mask of EOC field.
	ADC2_ADC_ISR_EOC_Msk = 0x4
	// Bit EOC.
	ADC2_ADC_ISR_EOC = 0x4
	// Position of EOS field.
	ADC2_ADC_ISR_EOS_Pos = 0x3
	// Bit mask of EOS field.
	ADC2_ADC_ISR_EOS_Msk = 0x8
	// Bit EOS.
	ADC2_ADC_ISR_EOS = 0x8
	// Position of OVR field.
	ADC2_ADC_ISR_OVR_Pos = 0x4
	// Bit mask of OVR field.
	ADC2_ADC_ISR_OVR_Msk = 0x10
	// Bit OVR.
	ADC2_ADC_ISR_OVR = 0x10
	// Position of JEOC field.
	ADC2_ADC_ISR_JEOC_Pos = 0x5
	// Bit mask of JEOC field.
	ADC2_ADC_ISR_JEOC_Msk = 0x20
	// Bit JEOC.
	ADC2_ADC_ISR_JEOC = 0x20
	// Position of JEOS field.
	ADC2_ADC_ISR_JEOS_Pos = 0x6
	// Bit mask of JEOS field.
	ADC2_ADC_ISR_JEOS_Msk = 0x40
	// Bit JEOS.
	ADC2_ADC_ISR_JEOS = 0x40
	// Position of AWD1 field.
	ADC2_ADC_ISR_AWD1_Pos = 0x7
	// Bit mask of AWD1 field.
	ADC2_ADC_ISR_AWD1_Msk = 0x80
	// Bit AWD1.
	ADC2_ADC_ISR_AWD1 = 0x80
	// Position of AWD2 field.
	ADC2_ADC_ISR_AWD2_Pos = 0x8
	// Bit mask of AWD2 field.
	ADC2_ADC_ISR_AWD2_Msk = 0x100
	// Bit AWD2.
	ADC2_ADC_ISR_AWD2 = 0x100
	// Position of AWD3 field.
	ADC2_ADC_ISR_AWD3_Pos = 0x9
	// Bit mask of AWD3 field.
	ADC2_ADC_ISR_AWD3_Msk = 0x200
	// Bit AWD3.
	ADC2_ADC_ISR_AWD3 = 0x200
	// Position of JQOVF field.
	ADC2_ADC_ISR_JQOVF_Pos = 0xa
	// Bit mask of JQOVF field.
	ADC2_ADC_ISR_JQOVF_Msk = 0x400
	// Bit JQOVF.
	ADC2_ADC_ISR_JQOVF = 0x400

	// ADC_IER: ADC interrupt enable register
	// Position of ADRDYIE field.
	ADC2_ADC_IER_ADRDYIE_Pos = 0x0
	// Bit mask of ADRDYIE field.
	ADC2_ADC_IER_ADRDYIE_Msk = 0x1
	// Bit ADRDYIE.
	ADC2_ADC_IER_ADRDYIE = 0x1
	// Position of EOSMPIE field.
	ADC2_ADC_IER_EOSMPIE_Pos = 0x1
	// Bit mask of EOSMPIE field.
	ADC2_ADC_IER_EOSMPIE_Msk = 0x2
	// Bit EOSMPIE.
	ADC2_ADC_IER_EOSMPIE = 0x2
	// Position of EOCIE field.
	ADC2_ADC_IER_EOCIE_Pos = 0x2
	// Bit mask of EOCIE field.
	ADC2_ADC_IER_EOCIE_Msk = 0x4
	// Bit EOCIE.
	ADC2_ADC_IER_EOCIE = 0x4
	// Position of EOSIE field.
	ADC2_ADC_IER_EOSIE_Pos = 0x3
	// Bit mask of EOSIE field.
	ADC2_ADC_IER_EOSIE_Msk = 0x8
	// Bit EOSIE.
	ADC2_ADC_IER_EOSIE = 0x8
	// Position of OVRIE field.
	ADC2_ADC_IER_OVRIE_Pos = 0x4
	// Bit mask of OVRIE field.
	ADC2_ADC_IER_OVRIE_Msk = 0x10
	// Bit OVRIE.
	ADC2_ADC_IER_OVRIE = 0x10
	// Position of JEOCIE field.
	ADC2_ADC_IER_JEOCIE_Pos = 0x5
	// Bit mask of JEOCIE field.
	ADC2_ADC_IER_JEOCIE_Msk = 0x20
	// Bit JEOCIE.
	ADC2_ADC_IER_JEOCIE = 0x20
	// Position of JEOSIE field.
	ADC2_ADC_IER_JEOSIE_Pos = 0x6
	// Bit mask of JEOSIE field.
	ADC2_ADC_IER_JEOSIE_Msk = 0x40
	// Bit JEOSIE.
	ADC2_ADC_IER_JEOSIE = 0x40
	// Position of AWD1IE field.
	ADC2_ADC_IER_AWD1IE_Pos = 0x7
	// Bit mask of AWD1IE field.
	ADC2_ADC_IER_AWD1IE_Msk = 0x80
	// Bit AWD1IE.
	ADC2_ADC_IER_AWD1IE = 0x80
	// Position of AWD2IE field.
	ADC2_ADC_IER_AWD2IE_Pos = 0x8
	// Bit mask of AWD2IE field.
	ADC2_ADC_IER_AWD2IE_Msk = 0x100
	// Bit AWD2IE.
	ADC2_ADC_IER_AWD2IE = 0x100
	// Position of AWD3IE field.
	ADC2_ADC_IER_AWD3IE_Pos = 0x9
	// Bit mask of AWD3IE field.
	ADC2_ADC_IER_AWD3IE_Msk = 0x200
	// Bit AWD3IE.
	ADC2_ADC_IER_AWD3IE = 0x200
	// Position of JQOVFIE field.
	ADC2_ADC_IER_JQOVFIE_Pos = 0xa
	// Bit mask of JQOVFIE field.
	ADC2_ADC_IER_JQOVFIE_Msk = 0x400
	// Bit JQOVFIE.
	ADC2_ADC_IER_JQOVFIE = 0x400

	// ADC_CR: ADC control register
	// Position of ADEN field.
	ADC2_ADC_CR_ADEN_Pos = 0x0
	// Bit mask of ADEN field.
	ADC2_ADC_CR_ADEN_Msk = 0x1
	// Bit ADEN.
	ADC2_ADC_CR_ADEN = 0x1
	// Position of ADDIS field.
	ADC2_ADC_CR_ADDIS_Pos = 0x1
	// Bit mask of ADDIS field.
	ADC2_ADC_CR_ADDIS_Msk = 0x2
	// Bit ADDIS.
	ADC2_ADC_CR_ADDIS = 0x2
	// Position of ADSTART field.
	ADC2_ADC_CR_ADSTART_Pos = 0x2
	// Bit mask of ADSTART field.
	ADC2_ADC_CR_ADSTART_Msk = 0x4
	// Bit ADSTART.
	ADC2_ADC_CR_ADSTART = 0x4
	// Position of JADSTART field.
	ADC2_ADC_CR_JADSTART_Pos = 0x3
	// Bit mask of JADSTART field.
	ADC2_ADC_CR_JADSTART_Msk = 0x8
	// Bit JADSTART.
	ADC2_ADC_CR_JADSTART = 0x8
	// Position of ADSTP field.
	ADC2_ADC_CR_ADSTP_Pos = 0x4
	// Bit mask of ADSTP field.
	ADC2_ADC_CR_ADSTP_Msk = 0x10
	// Bit ADSTP.
	ADC2_ADC_CR_ADSTP = 0x10
	// Position of JADSTP field.
	ADC2_ADC_CR_JADSTP_Pos = 0x5
	// Bit mask of JADSTP field.
	ADC2_ADC_CR_JADSTP_Msk = 0x20
	// Bit JADSTP.
	ADC2_ADC_CR_JADSTP = 0x20
	// Position of BOOST field.
	ADC2_ADC_CR_BOOST_Pos = 0x8
	// Bit mask of BOOST field.
	ADC2_ADC_CR_BOOST_Msk = 0x100
	// Bit BOOST.
	ADC2_ADC_CR_BOOST = 0x100
	// Position of ADCALLIN field.
	ADC2_ADC_CR_ADCALLIN_Pos = 0x10
	// Bit mask of ADCALLIN field.
	ADC2_ADC_CR_ADCALLIN_Msk = 0x10000
	// Bit ADCALLIN.
	ADC2_ADC_CR_ADCALLIN = 0x10000
	// Position of LINCALRDYW1 field.
	ADC2_ADC_CR_LINCALRDYW1_Pos = 0x16
	// Bit mask of LINCALRDYW1 field.
	ADC2_ADC_CR_LINCALRDYW1_Msk = 0x400000
	// Bit LINCALRDYW1.
	ADC2_ADC_CR_LINCALRDYW1 = 0x400000
	// Position of LINCALRDYW2 field.
	ADC2_ADC_CR_LINCALRDYW2_Pos = 0x17
	// Bit mask of LINCALRDYW2 field.
	ADC2_ADC_CR_LINCALRDYW2_Msk = 0x800000
	// Bit LINCALRDYW2.
	ADC2_ADC_CR_LINCALRDYW2 = 0x800000
	// Position of LINCALRDYW3 field.
	ADC2_ADC_CR_LINCALRDYW3_Pos = 0x18
	// Bit mask of LINCALRDYW3 field.
	ADC2_ADC_CR_LINCALRDYW3_Msk = 0x1000000
	// Bit LINCALRDYW3.
	ADC2_ADC_CR_LINCALRDYW3 = 0x1000000
	// Position of LINCALRDYW4 field.
	ADC2_ADC_CR_LINCALRDYW4_Pos = 0x19
	// Bit mask of LINCALRDYW4 field.
	ADC2_ADC_CR_LINCALRDYW4_Msk = 0x2000000
	// Bit LINCALRDYW4.
	ADC2_ADC_CR_LINCALRDYW4 = 0x2000000
	// Position of LINCALRDYW5 field.
	ADC2_ADC_CR_LINCALRDYW5_Pos = 0x1a
	// Bit mask of LINCALRDYW5 field.
	ADC2_ADC_CR_LINCALRDYW5_Msk = 0x4000000
	// Bit LINCALRDYW5.
	ADC2_ADC_CR_LINCALRDYW5 = 0x4000000
	// Position of LINCALRDYW6 field.
	ADC2_ADC_CR_LINCALRDYW6_Pos = 0x1b
	// Bit mask of LINCALRDYW6 field.
	ADC2_ADC_CR_LINCALRDYW6_Msk = 0x8000000
	// Bit LINCALRDYW6.
	ADC2_ADC_CR_LINCALRDYW6 = 0x8000000
	// Position of ADVREGEN field.
	ADC2_ADC_CR_ADVREGEN_Pos = 0x1c
	// Bit mask of ADVREGEN field.
	ADC2_ADC_CR_ADVREGEN_Msk = 0x10000000
	// Bit ADVREGEN.
	ADC2_ADC_CR_ADVREGEN = 0x10000000
	// Position of DEEPPWD field.
	ADC2_ADC_CR_DEEPPWD_Pos = 0x1d
	// Bit mask of DEEPPWD field.
	ADC2_ADC_CR_DEEPPWD_Msk = 0x20000000
	// Bit DEEPPWD.
	ADC2_ADC_CR_DEEPPWD = 0x20000000
	// Position of ADCALDIF field.
	ADC2_ADC_CR_ADCALDIF_Pos = 0x1e
	// Bit mask of ADCALDIF field.
	ADC2_ADC_CR_ADCALDIF_Msk = 0x40000000
	// Bit ADCALDIF.
	ADC2_ADC_CR_ADCALDIF = 0x40000000
	// Position of ADCAL field.
	ADC2_ADC_CR_ADCAL_Pos = 0x1f
	// Bit mask of ADCAL field.
	ADC2_ADC_CR_ADCAL_Msk = 0x80000000
	// Bit ADCAL.
	ADC2_ADC_CR_ADCAL = 0x80000000

	// ADC_CFGR: ADC configuration register
	// Position of DMNGT field.
	ADC2_ADC_CFGR_DMNGT_Pos = 0x0
	// Bit mask of DMNGT field.
	ADC2_ADC_CFGR_DMNGT_Msk = 0x3
	// Position of RES field.
	ADC2_ADC_CFGR_RES_Pos = 0x2
	// Bit mask of RES field.
	ADC2_ADC_CFGR_RES_Msk = 0x1c
	// Position of EXTSEL field.
	ADC2_ADC_CFGR_EXTSEL_Pos = 0x5
	// Bit mask of EXTSEL field.
	ADC2_ADC_CFGR_EXTSEL_Msk = 0x3e0
	// Position of EXTEN field.
	ADC2_ADC_CFGR_EXTEN_Pos = 0xa
	// Bit mask of EXTEN field.
	ADC2_ADC_CFGR_EXTEN_Msk = 0xc00
	// Position of OVRMOD field.
	ADC2_ADC_CFGR_OVRMOD_Pos = 0xc
	// Bit mask of OVRMOD field.
	ADC2_ADC_CFGR_OVRMOD_Msk = 0x1000
	// Bit OVRMOD.
	ADC2_ADC_CFGR_OVRMOD = 0x1000
	// Position of CONT field.
	ADC2_ADC_CFGR_CONT_Pos = 0xd
	// Bit mask of CONT field.
	ADC2_ADC_CFGR_CONT_Msk = 0x2000
	// Bit CONT.
	ADC2_ADC_CFGR_CONT = 0x2000
	// Position of AUTDLY field.
	ADC2_ADC_CFGR_AUTDLY_Pos = 0xe
	// Bit mask of AUTDLY field.
	ADC2_ADC_CFGR_AUTDLY_Msk = 0x4000
	// Bit AUTDLY.
	ADC2_ADC_CFGR_AUTDLY = 0x4000
	// Position of DISCEN field.
	ADC2_ADC_CFGR_DISCEN_Pos = 0x10
	// Bit mask of DISCEN field.
	ADC2_ADC_CFGR_DISCEN_Msk = 0x10000
	// Bit DISCEN.
	ADC2_ADC_CFGR_DISCEN = 0x10000
	// Position of DISCNUM field.
	ADC2_ADC_CFGR_DISCNUM_Pos = 0x11
	// Bit mask of DISCNUM field.
	ADC2_ADC_CFGR_DISCNUM_Msk = 0xe0000
	// Position of JDISCEN field.
	ADC2_ADC_CFGR_JDISCEN_Pos = 0x14
	// Bit mask of JDISCEN field.
	ADC2_ADC_CFGR_JDISCEN_Msk = 0x100000
	// Bit JDISCEN.
	ADC2_ADC_CFGR_JDISCEN = 0x100000
	// Position of JQM field.
	ADC2_ADC_CFGR_JQM_Pos = 0x15
	// Bit mask of JQM field.
	ADC2_ADC_CFGR_JQM_Msk = 0x200000
	// Bit JQM.
	ADC2_ADC_CFGR_JQM = 0x200000
	// Position of AWD1SGL field.
	ADC2_ADC_CFGR_AWD1SGL_Pos = 0x16
	// Bit mask of AWD1SGL field.
	ADC2_ADC_CFGR_AWD1SGL_Msk = 0x400000
	// Bit AWD1SGL.
	ADC2_ADC_CFGR_AWD1SGL = 0x400000
	// Position of AWD1EN field.
	ADC2_ADC_CFGR_AWD1EN_Pos = 0x17
	// Bit mask of AWD1EN field.
	ADC2_ADC_CFGR_AWD1EN_Msk = 0x800000
	// Bit AWD1EN.
	ADC2_ADC_CFGR_AWD1EN = 0x800000
	// Position of JAWD1EN field.
	ADC2_ADC_CFGR_JAWD1EN_Pos = 0x18
	// Bit mask of JAWD1EN field.
	ADC2_ADC_CFGR_JAWD1EN_Msk = 0x1000000
	// Bit JAWD1EN.
	ADC2_ADC_CFGR_JAWD1EN = 0x1000000
	// Position of JAUTO field.
	ADC2_ADC_CFGR_JAUTO_Pos = 0x19
	// Bit mask of JAUTO field.
	ADC2_ADC_CFGR_JAUTO_Msk = 0x2000000
	// Bit JAUTO.
	ADC2_ADC_CFGR_JAUTO = 0x2000000
	// Position of AWD1CH field.
	ADC2_ADC_CFGR_AWD1CH_Pos = 0x1a
	// Bit mask of AWD1CH field.
	ADC2_ADC_CFGR_AWD1CH_Msk = 0x7c000000
	// Position of JQDIS field.
	ADC2_ADC_CFGR_JQDIS_Pos = 0x1f
	// Bit mask of JQDIS field.
	ADC2_ADC_CFGR_JQDIS_Msk = 0x80000000
	// Bit JQDIS.
	ADC2_ADC_CFGR_JQDIS = 0x80000000

	// ADC_CFGR2: ADC configuration register 2
	// Position of ROVSE field.
	ADC2_ADC_CFGR2_ROVSE_Pos = 0x0
	// Bit mask of ROVSE field.
	ADC2_ADC_CFGR2_ROVSE_Msk = 0x1
	// Bit ROVSE.
	ADC2_ADC_CFGR2_ROVSE = 0x1
	// Position of JOVSE field.
	ADC2_ADC_CFGR2_JOVSE_Pos = 0x1
	// Bit mask of JOVSE field.
	ADC2_ADC_CFGR2_JOVSE_Msk = 0x2
	// Bit JOVSE.
	ADC2_ADC_CFGR2_JOVSE = 0x2
	// Position of OVSS field.
	ADC2_ADC_CFGR2_OVSS_Pos = 0x5
	// Bit mask of OVSS field.
	ADC2_ADC_CFGR2_OVSS_Msk = 0x1e0
	// Position of TROVS field.
	ADC2_ADC_CFGR2_TROVS_Pos = 0x9
	// Bit mask of TROVS field.
	ADC2_ADC_CFGR2_TROVS_Msk = 0x200
	// Bit TROVS.
	ADC2_ADC_CFGR2_TROVS = 0x200
	// Position of ROVSM field.
	ADC2_ADC_CFGR2_ROVSM_Pos = 0xa
	// Bit mask of ROVSM field.
	ADC2_ADC_CFGR2_ROVSM_Msk = 0x400
	// Bit ROVSM.
	ADC2_ADC_CFGR2_ROVSM = 0x400
	// Position of RSHIFT1 field.
	ADC2_ADC_CFGR2_RSHIFT1_Pos = 0xb
	// Bit mask of RSHIFT1 field.
	ADC2_ADC_CFGR2_RSHIFT1_Msk = 0x800
	// Bit RSHIFT1.
	ADC2_ADC_CFGR2_RSHIFT1 = 0x800
	// Position of RSHIFT2 field.
	ADC2_ADC_CFGR2_RSHIFT2_Pos = 0xc
	// Bit mask of RSHIFT2 field.
	ADC2_ADC_CFGR2_RSHIFT2_Msk = 0x1000
	// Bit RSHIFT2.
	ADC2_ADC_CFGR2_RSHIFT2 = 0x1000
	// Position of RSHIFT3 field.
	ADC2_ADC_CFGR2_RSHIFT3_Pos = 0xd
	// Bit mask of RSHIFT3 field.
	ADC2_ADC_CFGR2_RSHIFT3_Msk = 0x2000
	// Bit RSHIFT3.
	ADC2_ADC_CFGR2_RSHIFT3 = 0x2000
	// Position of RSHIFT4 field.
	ADC2_ADC_CFGR2_RSHIFT4_Pos = 0xe
	// Bit mask of RSHIFT4 field.
	ADC2_ADC_CFGR2_RSHIFT4_Msk = 0x4000
	// Bit RSHIFT4.
	ADC2_ADC_CFGR2_RSHIFT4 = 0x4000
	// Position of OSVR field.
	ADC2_ADC_CFGR2_OSVR_Pos = 0x10
	// Bit mask of OSVR field.
	ADC2_ADC_CFGR2_OSVR_Msk = 0x3ff0000
	// Position of LSHIFT field.
	ADC2_ADC_CFGR2_LSHIFT_Pos = 0x1c
	// Bit mask of LSHIFT field.
	ADC2_ADC_CFGR2_LSHIFT_Msk = 0xf0000000

	// ADC_SMPR1: ADC sample time register 1
	// Position of SMP0 field.
	ADC2_ADC_SMPR1_SMP0_Pos = 0x0
	// Bit mask of SMP0 field.
	ADC2_ADC_SMPR1_SMP0_Msk = 0x7
	// Position of SMP1 field.
	ADC2_ADC_SMPR1_SMP1_Pos = 0x3
	// Bit mask of SMP1 field.
	ADC2_ADC_SMPR1_SMP1_Msk = 0x38
	// Position of SMP2 field.
	ADC2_ADC_SMPR1_SMP2_Pos = 0x6
	// Bit mask of SMP2 field.
	ADC2_ADC_SMPR1_SMP2_Msk = 0x1c0
	// Position of SMP3 field.
	ADC2_ADC_SMPR1_SMP3_Pos = 0x9
	// Bit mask of SMP3 field.
	ADC2_ADC_SMPR1_SMP3_Msk = 0xe00
	// Position of SMP4 field.
	ADC2_ADC_SMPR1_SMP4_Pos = 0xc
	// Bit mask of SMP4 field.
	ADC2_ADC_SMPR1_SMP4_Msk = 0x7000
	// Position of SMP5 field.
	ADC2_ADC_SMPR1_SMP5_Pos = 0xf
	// Bit mask of SMP5 field.
	ADC2_ADC_SMPR1_SMP5_Msk = 0x38000
	// Position of SMP6 field.
	ADC2_ADC_SMPR1_SMP6_Pos = 0x12
	// Bit mask of SMP6 field.
	ADC2_ADC_SMPR1_SMP6_Msk = 0x1c0000
	// Position of SMP7 field.
	ADC2_ADC_SMPR1_SMP7_Pos = 0x15
	// Bit mask of SMP7 field.
	ADC2_ADC_SMPR1_SMP7_Msk = 0xe00000
	// Position of SMP8 field.
	ADC2_ADC_SMPR1_SMP8_Pos = 0x18
	// Bit mask of SMP8 field.
	ADC2_ADC_SMPR1_SMP8_Msk = 0x7000000
	// Position of SMP9 field.
	ADC2_ADC_SMPR1_SMP9_Pos = 0x1b
	// Bit mask of SMP9 field.
	ADC2_ADC_SMPR1_SMP9_Msk = 0x38000000

	// ADC_SMPR2: ADC sample time register 2
	// Position of SMP10 field.
	ADC2_ADC_SMPR2_SMP10_Pos = 0x0
	// Bit mask of SMP10 field.
	ADC2_ADC_SMPR2_SMP10_Msk = 0x7
	// Position of SMP11 field.
	ADC2_ADC_SMPR2_SMP11_Pos = 0x3
	// Bit mask of SMP11 field.
	ADC2_ADC_SMPR2_SMP11_Msk = 0x38
	// Position of SMP12 field.
	ADC2_ADC_SMPR2_SMP12_Pos = 0x6
	// Bit mask of SMP12 field.
	ADC2_ADC_SMPR2_SMP12_Msk = 0x1c0
	// Position of SMP13 field.
	ADC2_ADC_SMPR2_SMP13_Pos = 0x9
	// Bit mask of SMP13 field.
	ADC2_ADC_SMPR2_SMP13_Msk = 0xe00
	// Position of SMP14 field.
	ADC2_ADC_SMPR2_SMP14_Pos = 0xc
	// Bit mask of SMP14 field.
	ADC2_ADC_SMPR2_SMP14_Msk = 0x7000
	// Position of SMP15 field.
	ADC2_ADC_SMPR2_SMP15_Pos = 0xf
	// Bit mask of SMP15 field.
	ADC2_ADC_SMPR2_SMP15_Msk = 0x38000
	// Position of SMP16 field.
	ADC2_ADC_SMPR2_SMP16_Pos = 0x12
	// Bit mask of SMP16 field.
	ADC2_ADC_SMPR2_SMP16_Msk = 0x1c0000
	// Position of SMP17 field.
	ADC2_ADC_SMPR2_SMP17_Pos = 0x15
	// Bit mask of SMP17 field.
	ADC2_ADC_SMPR2_SMP17_Msk = 0xe00000
	// Position of SMP18 field.
	ADC2_ADC_SMPR2_SMP18_Pos = 0x18
	// Bit mask of SMP18 field.
	ADC2_ADC_SMPR2_SMP18_Msk = 0x7000000
	// Position of SMP19 field.
	ADC2_ADC_SMPR2_SMP19_Pos = 0x1b
	// Bit mask of SMP19 field.
	ADC2_ADC_SMPR2_SMP19_Msk = 0x38000000

	// ADC_PCSEL: ADC channel preselection register
	// Position of PCSEL0 field.
	ADC2_ADC_PCSEL_PCSEL0_Pos = 0x0
	// Bit mask of PCSEL0 field.
	ADC2_ADC_PCSEL_PCSEL0_Msk = 0x1
	// Bit PCSEL0.
	ADC2_ADC_PCSEL_PCSEL0 = 0x1
	// Position of PCSEL1 field.
	ADC2_ADC_PCSEL_PCSEL1_Pos = 0x1
	// Bit mask of PCSEL1 field.
	ADC2_ADC_PCSEL_PCSEL1_Msk = 0x2
	// Bit PCSEL1.
	ADC2_ADC_PCSEL_PCSEL1 = 0x2
	// Position of PCSEL2 field.
	ADC2_ADC_PCSEL_PCSEL2_Pos = 0x2
	// Bit mask of PCSEL2 field.
	ADC2_ADC_PCSEL_PCSEL2_Msk = 0x4
	// Bit PCSEL2.
	ADC2_ADC_PCSEL_PCSEL2 = 0x4
	// Position of PCSEL3 field.
	ADC2_ADC_PCSEL_PCSEL3_Pos = 0x3
	// Bit mask of PCSEL3 field.
	ADC2_ADC_PCSEL_PCSEL3_Msk = 0x8
	// Bit PCSEL3.
	ADC2_ADC_PCSEL_PCSEL3 = 0x8
	// Position of PCSEL4 field.
	ADC2_ADC_PCSEL_PCSEL4_Pos = 0x4
	// Bit mask of PCSEL4 field.
	ADC2_ADC_PCSEL_PCSEL4_Msk = 0x10
	// Bit PCSEL4.
	ADC2_ADC_PCSEL_PCSEL4 = 0x10
	// Position of PCSEL5 field.
	ADC2_ADC_PCSEL_PCSEL5_Pos = 0x5
	// Bit mask of PCSEL5 field.
	ADC2_ADC_PCSEL_PCSEL5_Msk = 0x20
	// Bit PCSEL5.
	ADC2_ADC_PCSEL_PCSEL5 = 0x20
	// Position of PCSEL6 field.
	ADC2_ADC_PCSEL_PCSEL6_Pos = 0x6
	// Bit mask of PCSEL6 field.
	ADC2_ADC_PCSEL_PCSEL6_Msk = 0x40
	// Bit PCSEL6.
	ADC2_ADC_PCSEL_PCSEL6 = 0x40
	// Position of PCSEL7 field.
	ADC2_ADC_PCSEL_PCSEL7_Pos = 0x7
	// Bit mask of PCSEL7 field.
	ADC2_ADC_PCSEL_PCSEL7_Msk = 0x80
	// Bit PCSEL7.
	ADC2_ADC_PCSEL_PCSEL7 = 0x80
	// Position of PCSEL8 field.
	ADC2_ADC_PCSEL_PCSEL8_Pos = 0x8
	// Bit mask of PCSEL8 field.
	ADC2_ADC_PCSEL_PCSEL8_Msk = 0x100
	// Bit PCSEL8.
	ADC2_ADC_PCSEL_PCSEL8 = 0x100
	// Position of PCSEL9 field.
	ADC2_ADC_PCSEL_PCSEL9_Pos = 0x9
	// Bit mask of PCSEL9 field.
	ADC2_ADC_PCSEL_PCSEL9_Msk = 0x200
	// Bit PCSEL9.
	ADC2_ADC_PCSEL_PCSEL9 = 0x200
	// Position of PCSEL10 field.
	ADC2_ADC_PCSEL_PCSEL10_Pos = 0xa
	// Bit mask of PCSEL10 field.
	ADC2_ADC_PCSEL_PCSEL10_Msk = 0x400
	// Bit PCSEL10.
	ADC2_ADC_PCSEL_PCSEL10 = 0x400
	// Position of PCSEL11 field.
	ADC2_ADC_PCSEL_PCSEL11_Pos = 0xb
	// Bit mask of PCSEL11 field.
	ADC2_ADC_PCSEL_PCSEL11_Msk = 0x800
	// Bit PCSEL11.
	ADC2_ADC_PCSEL_PCSEL11 = 0x800
	// Position of PCSEL12 field.
	ADC2_ADC_PCSEL_PCSEL12_Pos = 0xc
	// Bit mask of PCSEL12 field.
	ADC2_ADC_PCSEL_PCSEL12_Msk = 0x1000
	// Bit PCSEL12.
	ADC2_ADC_PCSEL_PCSEL12 = 0x1000
	// Position of PCSEL13 field.
	ADC2_ADC_PCSEL_PCSEL13_Pos = 0xd
	// Bit mask of PCSEL13 field.
	ADC2_ADC_PCSEL_PCSEL13_Msk = 0x2000
	// Bit PCSEL13.
	ADC2_ADC_PCSEL_PCSEL13 = 0x2000
	// Position of PCSEL14 field.
	ADC2_ADC_PCSEL_PCSEL14_Pos = 0xe
	// Bit mask of PCSEL14 field.
	ADC2_ADC_PCSEL_PCSEL14_Msk = 0x4000
	// Bit PCSEL14.
	ADC2_ADC_PCSEL_PCSEL14 = 0x4000
	// Position of PCSEL15 field.
	ADC2_ADC_PCSEL_PCSEL15_Pos = 0xf
	// Bit mask of PCSEL15 field.
	ADC2_ADC_PCSEL_PCSEL15_Msk = 0x8000
	// Bit PCSEL15.
	ADC2_ADC_PCSEL_PCSEL15 = 0x8000
	// Position of PCSEL16 field.
	ADC2_ADC_PCSEL_PCSEL16_Pos = 0x10
	// Bit mask of PCSEL16 field.
	ADC2_ADC_PCSEL_PCSEL16_Msk = 0x10000
	// Bit PCSEL16.
	ADC2_ADC_PCSEL_PCSEL16 = 0x10000
	// Position of PCSEL17 field.
	ADC2_ADC_PCSEL_PCSEL17_Pos = 0x11
	// Bit mask of PCSEL17 field.
	ADC2_ADC_PCSEL_PCSEL17_Msk = 0x20000
	// Bit PCSEL17.
	ADC2_ADC_PCSEL_PCSEL17 = 0x20000
	// Position of PCSEL18 field.
	ADC2_ADC_PCSEL_PCSEL18_Pos = 0x12
	// Bit mask of PCSEL18 field.
	ADC2_ADC_PCSEL_PCSEL18_Msk = 0x40000
	// Bit PCSEL18.
	ADC2_ADC_PCSEL_PCSEL18 = 0x40000
	// Position of PCSEL19 field.
	ADC2_ADC_PCSEL_PCSEL19_Pos = 0x13
	// Bit mask of PCSEL19 field.
	ADC2_ADC_PCSEL_PCSEL19_Msk = 0x80000
	// Bit PCSEL19.
	ADC2_ADC_PCSEL_PCSEL19 = 0x80000

	// ADC_LTR1: ADC watchdog threshold register 1
	// Position of LTR1 field.
	ADC2_ADC_LTR1_LTR1_Pos = 0x0
	// Bit mask of LTR1 field.
	ADC2_ADC_LTR1_LTR1_Msk = 0x3ffffff

	// ADC_HTR1: ADC watchdog threshold register 1
	// Position of HTR1 field.
	ADC2_ADC_HTR1_HTR1_Pos = 0x0
	// Bit mask of HTR1 field.
	ADC2_ADC_HTR1_HTR1_Msk = 0x3ffffff

	// ADC_SQR1: ADC regular sequence register 1
	// Position of L field.
	ADC2_ADC_SQR1_L_Pos = 0x0
	// Bit mask of L field.
	ADC2_ADC_SQR1_L_Msk = 0xf
	// Position of SQ1 field.
	ADC2_ADC_SQR1_SQ1_Pos = 0x6
	// Bit mask of SQ1 field.
	ADC2_ADC_SQR1_SQ1_Msk = 0x7c0
	// Position of SQ2 field.
	ADC2_ADC_SQR1_SQ2_Pos = 0xc
	// Bit mask of SQ2 field.
	ADC2_ADC_SQR1_SQ2_Msk = 0x1f000
	// Position of SQ3 field.
	ADC2_ADC_SQR1_SQ3_Pos = 0x12
	// Bit mask of SQ3 field.
	ADC2_ADC_SQR1_SQ3_Msk = 0x7c0000
	// Position of SQ4 field.
	ADC2_ADC_SQR1_SQ4_Pos = 0x18
	// Bit mask of SQ4 field.
	ADC2_ADC_SQR1_SQ4_Msk = 0x1f000000

	// ADC_SQR2: ADC regular sequence register 2
	// Position of SQ5 field.
	ADC2_ADC_SQR2_SQ5_Pos = 0x0
	// Bit mask of SQ5 field.
	ADC2_ADC_SQR2_SQ5_Msk = 0x1f
	// Position of SQ6 field.
	ADC2_ADC_SQR2_SQ6_Pos = 0x6
	// Bit mask of SQ6 field.
	ADC2_ADC_SQR2_SQ6_Msk = 0x7c0
	// Position of SQ7 field.
	ADC2_ADC_SQR2_SQ7_Pos = 0xc
	// Bit mask of SQ7 field.
	ADC2_ADC_SQR2_SQ7_Msk = 0x1f000
	// Position of SQ8 field.
	ADC2_ADC_SQR2_SQ8_Pos = 0x12
	// Bit mask of SQ8 field.
	ADC2_ADC_SQR2_SQ8_Msk = 0x7c0000
	// Position of SQ9 field.
	ADC2_ADC_SQR2_SQ9_Pos = 0x18
	// Bit mask of SQ9 field.
	ADC2_ADC_SQR2_SQ9_Msk = 0x1f000000

	// ADC_SQR3: ADC regular sequence register 3
	// Position of SQ10 field.
	ADC2_ADC_SQR3_SQ10_Pos = 0x0
	// Bit mask of SQ10 field.
	ADC2_ADC_SQR3_SQ10_Msk = 0x1f
	// Position of SQ11 field.
	ADC2_ADC_SQR3_SQ11_Pos = 0x6
	// Bit mask of SQ11 field.
	ADC2_ADC_SQR3_SQ11_Msk = 0x7c0
	// Position of SQ12 field.
	ADC2_ADC_SQR3_SQ12_Pos = 0xc
	// Bit mask of SQ12 field.
	ADC2_ADC_SQR3_SQ12_Msk = 0x1f000
	// Position of SQ13 field.
	ADC2_ADC_SQR3_SQ13_Pos = 0x12
	// Bit mask of SQ13 field.
	ADC2_ADC_SQR3_SQ13_Msk = 0x7c0000
	// Position of SQ14 field.
	ADC2_ADC_SQR3_SQ14_Pos = 0x18
	// Bit mask of SQ14 field.
	ADC2_ADC_SQR3_SQ14_Msk = 0x1f000000

	// ADC_SQR4: ADC regular sequence register 4
	// Position of SQ15 field.
	ADC2_ADC_SQR4_SQ15_Pos = 0x0
	// Bit mask of SQ15 field.
	ADC2_ADC_SQR4_SQ15_Msk = 0x1f
	// Position of SQ16 field.
	ADC2_ADC_SQR4_SQ16_Pos = 0x6
	// Bit mask of SQ16 field.
	ADC2_ADC_SQR4_SQ16_Msk = 0x7c0

	// ADC_DR: ADC regular Data Register
	// Position of RDATA field.
	ADC2_ADC_DR_RDATA_Pos = 0x0
	// Bit mask of RDATA field.
	ADC2_ADC_DR_RDATA_Msk = 0xffffffff

	// ADC_JSQR: ADC injected sequence register
	// Position of JL field.
	ADC2_ADC_JSQR_JL_Pos = 0x0
	// Bit mask of JL field.
	ADC2_ADC_JSQR_JL_Msk = 0x3
	// Position of JEXTSEL field.
	ADC2_ADC_JSQR_JEXTSEL_Pos = 0x2
	// Bit mask of JEXTSEL field.
	ADC2_ADC_JSQR_JEXTSEL_Msk = 0x7c
	// Position of JEXTEN field.
	ADC2_ADC_JSQR_JEXTEN_Pos = 0x7
	// Bit mask of JEXTEN field.
	ADC2_ADC_JSQR_JEXTEN_Msk = 0x180
	// Position of JSQ1 field.
	ADC2_ADC_JSQR_JSQ1_Pos = 0x9
	// Bit mask of JSQ1 field.
	ADC2_ADC_JSQR_JSQ1_Msk = 0x3e00
	// Position of JSQ2 field.
	ADC2_ADC_JSQR_JSQ2_Pos = 0xf
	// Bit mask of JSQ2 field.
	ADC2_ADC_JSQR_JSQ2_Msk = 0xf8000
	// Position of JSQ3 field.
	ADC2_ADC_JSQR_JSQ3_Pos = 0x15
	// Bit mask of JSQ3 field.
	ADC2_ADC_JSQR_JSQ3_Msk = 0x3e00000
	// Position of JSQ4 field.
	ADC2_ADC_JSQR_JSQ4_Pos = 0x1b
	// Bit mask of JSQ4 field.
	ADC2_ADC_JSQR_JSQ4_Msk = 0xf8000000

	// ADC_OFR1: ADC offset register
	// Position of OFFSET1 field.
	ADC2_ADC_OFR1_OFFSET1_Pos = 0x0
	// Bit mask of OFFSET1 field.
	ADC2_ADC_OFR1_OFFSET1_Msk = 0x3ffffff
	// Position of OFFSET1_CH field.
	ADC2_ADC_OFR1_OFFSET1_CH_Pos = 0x1a
	// Bit mask of OFFSET1_CH field.
	ADC2_ADC_OFR1_OFFSET1_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC2_ADC_OFR1_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC2_ADC_OFR1_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC2_ADC_OFR1_SSATE = 0x80000000

	// ADC_OFR2: ADC offset register
	// Position of OFFSET2 field.
	ADC2_ADC_OFR2_OFFSET2_Pos = 0x0
	// Bit mask of OFFSET2 field.
	ADC2_ADC_OFR2_OFFSET2_Msk = 0x3ffffff
	// Position of OFFSET2_CH field.
	ADC2_ADC_OFR2_OFFSET2_CH_Pos = 0x1a
	// Bit mask of OFFSET2_CH field.
	ADC2_ADC_OFR2_OFFSET2_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC2_ADC_OFR2_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC2_ADC_OFR2_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC2_ADC_OFR2_SSATE = 0x80000000

	// ADC_OFR3: ADC offset register
	// Position of OFFSET3 field.
	ADC2_ADC_OFR3_OFFSET3_Pos = 0x0
	// Bit mask of OFFSET3 field.
	ADC2_ADC_OFR3_OFFSET3_Msk = 0x3ffffff
	// Position of OFFSET3_CH field.
	ADC2_ADC_OFR3_OFFSET3_CH_Pos = 0x1a
	// Bit mask of OFFSET3_CH field.
	ADC2_ADC_OFR3_OFFSET3_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC2_ADC_OFR3_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC2_ADC_OFR3_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC2_ADC_OFR3_SSATE = 0x80000000

	// ADC_OFR4: ADC offset register
	// Position of OFFSET4 field.
	ADC2_ADC_OFR4_OFFSET4_Pos = 0x0
	// Bit mask of OFFSET4 field.
	ADC2_ADC_OFR4_OFFSET4_Msk = 0x3ffffff
	// Position of OFFSET4_CH field.
	ADC2_ADC_OFR4_OFFSET4_CH_Pos = 0x1a
	// Bit mask of OFFSET4_CH field.
	ADC2_ADC_OFR4_OFFSET4_CH_Msk = 0x7c000000
	// Position of SSATE field.
	ADC2_ADC_OFR4_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC2_ADC_OFR4_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC2_ADC_OFR4_SSATE = 0x80000000

	// ADC_JDR1: ADC injected data register
	// Position of JDATA field.
	ADC2_ADC_JDR1_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC2_ADC_JDR1_JDATA_Msk = 0xffffffff

	// ADC_JDR2: ADC injected data register
	// Position of JDATA field.
	ADC2_ADC_JDR2_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC2_ADC_JDR2_JDATA_Msk = 0xffffffff

	// ADC_JDR3: ADC injected data register
	// Position of JDATA field.
	ADC2_ADC_JDR3_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC2_ADC_JDR3_JDATA_Msk = 0xffffffff

	// ADC_JDR4: ADC injected data register
	// Position of JDATA field.
	ADC2_ADC_JDR4_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC2_ADC_JDR4_JDATA_Msk = 0xffffffff

	// ADC_AWD2CR: ADC analog watchdog 2 configuration register
	// Position of AWD2CH field.
	ADC2_ADC_AWD2CR_AWD2CH_Pos = 0x0
	// Bit mask of AWD2CH field.
	ADC2_ADC_AWD2CR_AWD2CH_Msk = 0xfffff

	// ADC_AWD3CR: ADC analog watchdog 3 configuration register
	// Position of AWD3CH field.
	ADC2_ADC_AWD3CR_AWD3CH_Pos = 0x0
	// Bit mask of AWD3CH field.
	ADC2_ADC_AWD3CR_AWD3CH_Msk = 0xfffff

	// ADC_LTR2: ADC watchdog lower threshold register 2
	// Position of LTR2 field.
	ADC2_ADC_LTR2_LTR2_Pos = 0x0
	// Bit mask of LTR2 field.
	ADC2_ADC_LTR2_LTR2_Msk = 0x3ffffff

	// ADC_HTR2: ADC watchdog higher threshold register 2
	// Position of HTR2 field.
	ADC2_ADC_HTR2_HTR2_Pos = 0x0
	// Bit mask of HTR2 field.
	ADC2_ADC_HTR2_HTR2_Msk = 0x3ffffff

	// ADC_LTR3: ADC watchdog lower threshold register 3
	// Position of LTR3 field.
	ADC2_ADC_LTR3_LTR3_Pos = 0x0
	// Bit mask of LTR3 field.
	ADC2_ADC_LTR3_LTR3_Msk = 0x3ffffff

	// ADC_HTR3: ADC watchdog higher threshold register 3
	// Position of HTR3 field.
	ADC2_ADC_HTR3_HTR3_Pos = 0x0
	// Bit mask of HTR3 field.
	ADC2_ADC_HTR3_HTR3_Msk = 0x3ffffff

	// ADC_DIFSEL: ADC differential mode selection register
	// Position of DIFSEL field.
	ADC2_ADC_DIFSEL_DIFSEL_Pos = 0x0
	// Bit mask of DIFSEL field.
	ADC2_ADC_DIFSEL_DIFSEL_Msk = 0xfffff

	// ADC_CALFACT: ADC calibration factors register
	// Position of CALFACT_S field.
	ADC2_ADC_CALFACT_CALFACT_S_Pos = 0x0
	// Bit mask of CALFACT_S field.
	ADC2_ADC_CALFACT_CALFACT_S_Msk = 0x7ff
	// Position of CALFACT_D field.
	ADC2_ADC_CALFACT_CALFACT_D_Pos = 0x10
	// Bit mask of CALFACT_D field.
	ADC2_ADC_CALFACT_CALFACT_D_Msk = 0x7ff0000

	// ADC_CALFACT2: ADC calibration factor register 2
	// Position of LINCALFACT field.
	ADC2_ADC_CALFACT2_LINCALFACT_Pos = 0x0
	// Bit mask of LINCALFACT field.
	ADC2_ADC_CALFACT2_LINCALFACT_Msk = 0x3fffffff

	// ADC2_OR: ADC2 option register
	// Position of VDDCOREEN field.
	ADC2_ADC2_OR_VDDCOREEN_Pos = 0x0
	// Bit mask of VDDCOREEN field.
	ADC2_ADC2_OR_VDDCOREEN_Msk = 0x1
	// Bit VDDCOREEN.
	ADC2_ADC2_OR_VDDCOREEN = 0x1
)

// Bitfields for AXIMC_Mx: AXIMC_Mx
const (
	// AXIMC_M0_FN_MOD2: AXIMC master 0 packing functionality register
	// Position of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXIMC_Mx_AXIMC_M0_FN_MOD2_BYPASS_MERGE = 0x1

	// AXIMC_M0_READ_QOS: AXIMC master 0 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M0_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M0_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M0_FN_MOD: AXIMC master 0 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M0_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M0_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M0_WRITE_QOS: AXIMC master 0 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M0_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M0_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M1_FN_MOD2: AXIMC master 1 packing functionality register
	// Position of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXIMC_Mx_AXIMC_M1_FN_MOD2_BYPASS_MERGE = 0x1

	// AXIMC_M1_READ_QOS: AXIMC master 1 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M1_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M1_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M1_WRITE_QOS: AXIMC master 1 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M1_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M1_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M1_FN_MOD: AXIMC master 1 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M1_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M1_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_PERIPH_ID_4: AXIMC peripheral ID4 register
	// Position of JEP106CON field.
	AXIMC_Mx_AXIMC_PERIPH_ID_4_JEP106CON_Pos = 0x0
	// Bit mask of JEP106CON field.
	AXIMC_Mx_AXIMC_PERIPH_ID_4_JEP106CON_Msk = 0xf
	// Position of K4COUNT field.
	AXIMC_Mx_AXIMC_PERIPH_ID_4_K4COUNT_Pos = 0x4
	// Bit mask of K4COUNT field.
	AXIMC_Mx_AXIMC_PERIPH_ID_4_K4COUNT_Msk = 0xf0

	// AXIMC_PERIPH_ID_5: AXIMC peripheral ID5 register
	// Position of PERIPH_ID_5 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_5_PERIPH_ID_5_Pos = 0x0
	// Bit mask of PERIPH_ID_5 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_5_PERIPH_ID_5_Msk = 0xff

	// AXIMC_PERIPH_ID_6: AXIMC peripheral ID6 register
	// Position of PERIPH_ID_6 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_6_PERIPH_ID_6_Pos = 0x0
	// Bit mask of PERIPH_ID_6 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_6_PERIPH_ID_6_Msk = 0xff

	// AXIMC_PERIPH_ID_7: AXIMC peripheral ID7 register
	// Position of PERIPH_ID_7 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_7_PERIPH_ID_7_Pos = 0x0
	// Bit mask of PERIPH_ID_7 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_7_PERIPH_ID_7_Msk = 0xff

	// AXIMC_PERIPH_ID_0: AXIMC peripheral ID0 register
	// Position of PERIPH_ID_0 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_0_PERIPH_ID_0_Pos = 0x0
	// Bit mask of PERIPH_ID_0 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_0_PERIPH_ID_0_Msk = 0xff

	// AXIMC_PERIPH_ID_1: AXIMC peripheral ID1 register
	// Position of PERIPH_ID_1 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_1_PERIPH_ID_1_Pos = 0x0
	// Bit mask of PERIPH_ID_1 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_1_PERIPH_ID_1_Msk = 0xff

	// AXIMC_PERIPH_ID_2: AXIMC peripheral ID2 register
	// Position of PERIPH_ID_2 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_2_PERIPH_ID_2_Pos = 0x0
	// Bit mask of PERIPH_ID_2 field.
	AXIMC_Mx_AXIMC_PERIPH_ID_2_PERIPH_ID_2_Msk = 0xff

	// AXIMC_PERIPH_ID_3: AXIMC peripheral ID3 register
	// Position of CUST_MOD_NUM field.
	AXIMC_Mx_AXIMC_PERIPH_ID_3_CUST_MOD_NUM_Pos = 0x0
	// Bit mask of CUST_MOD_NUM field.
	AXIMC_Mx_AXIMC_PERIPH_ID_3_CUST_MOD_NUM_Msk = 0xf
	// Position of REV_AND field.
	AXIMC_Mx_AXIMC_PERIPH_ID_3_REV_AND_Pos = 0x4
	// Bit mask of REV_AND field.
	AXIMC_Mx_AXIMC_PERIPH_ID_3_REV_AND_Msk = 0xf0

	// AXIMC_COMP_ID_0: AXIMC component ID0 register
	// Position of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_0_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_0_PREAMBLE_Msk = 0xff

	// AXIMC_COMP_ID_1: AXIMC component ID1 register
	// Position of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_1_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_1_PREAMBLE_Msk = 0xf
	// Position of CLASS field.
	AXIMC_Mx_AXIMC_COMP_ID_1_CLASS_Pos = 0x4
	// Bit mask of CLASS field.
	AXIMC_Mx_AXIMC_COMP_ID_1_CLASS_Msk = 0xf0

	// AXIMC_COMP_ID_2: AXIMC component ID2 register
	// Position of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_2_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_2_PREAMBLE_Msk = 0xff

	// AXIMC_COMP_ID_3: AXIMC component ID3 register
	// Position of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_3_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXIMC_Mx_AXIMC_COMP_ID_3_PREAMBLE_Msk = 0xff

	// AXIMC_M2_FN_MOD2: AXIMC master 2 packing functionality register
	// Position of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXIMC_Mx_AXIMC_M2_FN_MOD2_BYPASS_MERGE = 0x1

	// AXIMC_M2_READ_QOS: AXIMC master 2 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M2_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M2_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M2_WRITE_QOS: AXIMC master 2 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M2_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M2_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M2_FN_MOD: AXIMC master 2 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M2_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M2_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M5_FN_MOD2: AXIMC master 5 packing functionality register
	// Position of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXIMC_Mx_AXIMC_M5_FN_MOD2_BYPASS_MERGE = 0x1

	// AXIMC_M5_READ_QOS: AXIMC master 5 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M5_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M5_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M5_WRITE_QOS: AXIMC master 5 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M5_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M5_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M5_FN_MOD: AXIMC master 5 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M5_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M5_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M3_READ_QOS: AXIMC master 3 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M3_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M3_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M3_WRITE_QOS: AXIMC master 3 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M3_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M3_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M3_FN_MOD: AXIMC master 3 packing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M3_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M3_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M3_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M3_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M3_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M3_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M7_READ_QOS: AXIMC master 7 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M7_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M7_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M7_WRITE_QOS: AXIMC master 7 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M7_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M7_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M7_FN_MOD: AXIMC master 7 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M7_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M7_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M7_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M7_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M7_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M7_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M8_READ_QOS: AXIMC master 8 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M8_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M8_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M8_WRITE_QOS: AXIMC master 8 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M8_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M8_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M8_FN_MOD: AXIMC master 8 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M8_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M8_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M8_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M8_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M8_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M8_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M4_FN_MOD2: AXIMC master 4 packing functionality register
	// Position of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M4_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M4_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXIMC_Mx_AXIMC_M4_FN_MOD2_BYPASS_MERGE = 0x1

	// AXIMC_M4_READ_QOS: AXIMC master 4 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M4_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M4_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M4_WRITE_QOS: AXIMC master 4 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M4_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M4_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M4_FN_MOD: AXIMC master 4 packing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M4_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M4_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M4_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M4_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M4_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M4_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M9_READ_QOS: AXIMC master 9 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M9_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M9_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M9_WRITE_QOS: AXIMC master 9 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M9_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M9_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M9_FN_MOD: AXIMC master 9 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M9_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M9_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M9_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M9_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M9_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M9_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M10_READ_QOS: AXIMC master 10 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M10_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M10_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M10_WRITE_QOS: AXIMC master 10 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M10_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M10_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M10_FN_MOD: AXIMC master 10 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M10_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M10_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M10_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M10_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M10_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M10_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M6_FN_MOD2: AXIMC master 6 packing functionality register
	// Position of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXIMC_Mx_AXIMC_M6_FN_MOD2_BYPASS_MERGE = 0x1

	// AXIMC_M6_READ_QOS: AXIMC master 6 read priority register
	// Position of AR_QOS field.
	AXIMC_Mx_AXIMC_M6_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXIMC_Mx_AXIMC_M6_READ_QOS_AR_QOS_Msk = 0xf

	// AXIMC_M6_WRITE_QOS: AXIMC master 6 write priority register
	// Position of AW_QOS field.
	AXIMC_Mx_AXIMC_M6_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXIMC_Mx_AXIMC_M6_WRITE_QOS_AW_QOS_Msk = 0xf

	// AXIMC_M6_FN_MOD: AXIMC master 6 issuing capability override functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M6_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXIMC_Mx_AXIMC_M6_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// AXIMC_M0_FN_MOD_AHB: AXIMC master 0 AHB conversion override functionality register
	// Position of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0
	// Bit mask of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1
	// Bit RD_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M0_FN_MOD_AHB_RD_INC_OVERRIDE = 0x1
	// Position of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1
	// Bit mask of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M0_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2
	// Bit WR_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M0_FN_MOD_AHB_WR_INC_OVERRIDE = 0x2

	// AXIMC_M1_FN_MOD_AHB: AXIMC master 1 AHB conversion override functionality register
	// Position of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0
	// Bit mask of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1
	// Bit RD_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M1_FN_MOD_AHB_RD_INC_OVERRIDE = 0x1
	// Position of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1
	// Bit mask of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M1_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2
	// Bit WR_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M1_FN_MOD_AHB_WR_INC_OVERRIDE = 0x2

	// AXIMC_M2_FN_MOD_AHB: AXIMC master 2 AHB conversion override functionality register
	// Position of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0
	// Bit mask of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1
	// Bit RD_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M2_FN_MOD_AHB_RD_INC_OVERRIDE = 0x1
	// Position of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1
	// Bit mask of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M2_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2
	// Bit WR_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M2_FN_MOD_AHB_WR_INC_OVERRIDE = 0x2

	// AXIMC_M5_FN_MOD_AHB: AXIMC master 5 AHB conversion override functionality register
	// Position of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0
	// Bit mask of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1
	// Bit RD_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M5_FN_MOD_AHB_RD_INC_OVERRIDE = 0x1
	// Position of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1
	// Bit mask of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M5_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2
	// Bit WR_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M5_FN_MOD_AHB_WR_INC_OVERRIDE = 0x2

	// AXIMC_FN_MOD_LB: AXIMC long burst capability inhibition register
	// Position of FN_MOD_LB field.
	AXIMC_Mx_AXIMC_FN_MOD_LB_FN_MOD_LB_Pos = 0x0
	// Bit mask of FN_MOD_LB field.
	AXIMC_Mx_AXIMC_FN_MOD_LB_FN_MOD_LB_Msk = 0x1
	// Bit FN_MOD_LB.
	AXIMC_Mx_AXIMC_FN_MOD_LB_FN_MOD_LB = 0x1

	// AXIMC_M6_FN_MOD_AHB: AXIMC master 6 AHB conversion override functionality register
	// Position of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0
	// Bit mask of RD_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1
	// Bit RD_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M6_FN_MOD_AHB_RD_INC_OVERRIDE = 0x1
	// Position of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1
	// Bit mask of WR_INC_OVERRIDE field.
	AXIMC_Mx_AXIMC_M6_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2
	// Bit WR_INC_OVERRIDE.
	AXIMC_Mx_AXIMC_M6_FN_MOD_AHB_WR_INC_OVERRIDE = 0x2
)

// Bitfields for BSEC: BSEC2
const (
	// BSEC_OTP_CONFIG: BSEC OTP configuration register
	// Position of PWRUP field.
	BSEC2_BSEC_OTP_CONFIG_PWRUP_Pos = 0x0
	// Bit mask of PWRUP field.
	BSEC2_BSEC_OTP_CONFIG_PWRUP_Msk = 0x1
	// Bit PWRUP.
	BSEC2_BSEC_OTP_CONFIG_PWRUP = 0x1
	// Position of FRC field.
	BSEC2_BSEC_OTP_CONFIG_FRC_Pos = 0x1
	// Bit mask of FRC field.
	BSEC2_BSEC_OTP_CONFIG_FRC_Msk = 0x6
	// Position of PRGWIDTH field.
	BSEC2_BSEC_OTP_CONFIG_PRGWIDTH_Pos = 0x3
	// Bit mask of PRGWIDTH field.
	BSEC2_BSEC_OTP_CONFIG_PRGWIDTH_Msk = 0x78
	// Position of TREAD field.
	BSEC2_BSEC_OTP_CONFIG_TREAD_Pos = 0x7
	// Bit mask of TREAD field.
	BSEC2_BSEC_OTP_CONFIG_TREAD_Msk = 0x180

	// BSEC_OTP_CONTROL: BSEC OTP control register
	// Position of ADDR field.
	BSEC2_BSEC_OTP_CONTROL_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	BSEC2_BSEC_OTP_CONTROL_ADDR_Msk = 0x7f
	// Position of PROG field.
	BSEC2_BSEC_OTP_CONTROL_PROG_Pos = 0x8
	// Bit mask of PROG field.
	BSEC2_BSEC_OTP_CONTROL_PROG_Msk = 0x100
	// Bit PROG.
	BSEC2_BSEC_OTP_CONTROL_PROG = 0x100
	// Position of LOCK field.
	BSEC2_BSEC_OTP_CONTROL_LOCK_Pos = 0x9
	// Bit mask of LOCK field.
	BSEC2_BSEC_OTP_CONTROL_LOCK_Msk = 0x200
	// Bit LOCK.
	BSEC2_BSEC_OTP_CONTROL_LOCK = 0x200

	// BSEC_OTP_WRDATA: BSEC OTP write data register
	// Position of WRDATA field.
	BSEC2_BSEC_OTP_WRDATA_WRDATA_Pos = 0x0
	// Bit mask of WRDATA field.
	BSEC2_BSEC_OTP_WRDATA_WRDATA_Msk = 0xffffffff

	// BSEC_OTP_STATUS: BSEC OTP status register
	// Position of SECURE field.
	BSEC2_BSEC_OTP_STATUS_SECURE_Pos = 0x0
	// Bit mask of SECURE field.
	BSEC2_BSEC_OTP_STATUS_SECURE_Msk = 0x1
	// Bit SECURE.
	BSEC2_BSEC_OTP_STATUS_SECURE = 0x1
	// Position of FULLDBG field.
	BSEC2_BSEC_OTP_STATUS_FULLDBG_Pos = 0x1
	// Bit mask of FULLDBG field.
	BSEC2_BSEC_OTP_STATUS_FULLDBG_Msk = 0x2
	// Bit FULLDBG.
	BSEC2_BSEC_OTP_STATUS_FULLDBG = 0x2
	// Position of INVALID field.
	BSEC2_BSEC_OTP_STATUS_INVALID_Pos = 0x2
	// Bit mask of INVALID field.
	BSEC2_BSEC_OTP_STATUS_INVALID_Msk = 0x4
	// Bit INVALID.
	BSEC2_BSEC_OTP_STATUS_INVALID = 0x4
	// Position of BUSY field.
	BSEC2_BSEC_OTP_STATUS_BUSY_Pos = 0x3
	// Bit mask of BUSY field.
	BSEC2_BSEC_OTP_STATUS_BUSY_Msk = 0x8
	// Bit BUSY.
	BSEC2_BSEC_OTP_STATUS_BUSY = 0x8
	// Position of PROGFAIL field.
	BSEC2_BSEC_OTP_STATUS_PROGFAIL_Pos = 0x4
	// Bit mask of PROGFAIL field.
	BSEC2_BSEC_OTP_STATUS_PROGFAIL_Msk = 0x10
	// Bit PROGFAIL.
	BSEC2_BSEC_OTP_STATUS_PROGFAIL = 0x10
	// Position of PWRON field.
	BSEC2_BSEC_OTP_STATUS_PWRON_Pos = 0x5
	// Bit mask of PWRON field.
	BSEC2_BSEC_OTP_STATUS_PWRON_Msk = 0x20
	// Bit PWRON.
	BSEC2_BSEC_OTP_STATUS_PWRON = 0x20
	// Position of BIST1LOCK field.
	BSEC2_BSEC_OTP_STATUS_BIST1LOCK_Pos = 0x6
	// Bit mask of BIST1LOCK field.
	BSEC2_BSEC_OTP_STATUS_BIST1LOCK_Msk = 0x40
	// Bit BIST1LOCK.
	BSEC2_BSEC_OTP_STATUS_BIST1LOCK = 0x40
	// Position of BIST2LOCK field.
	BSEC2_BSEC_OTP_STATUS_BIST2LOCK_Pos = 0x7
	// Bit mask of BIST2LOCK field.
	BSEC2_BSEC_OTP_STATUS_BIST2LOCK_Msk = 0x80
	// Bit BIST2LOCK.
	BSEC2_BSEC_OTP_STATUS_BIST2LOCK = 0x80

	// BSEC_OTP_LOCK: BSEC OTP lock configuration register
	// Position of OTP field.
	BSEC2_BSEC_OTP_LOCK_OTP_Pos = 0x0
	// Bit mask of OTP field.
	BSEC2_BSEC_OTP_LOCK_OTP_Msk = 0x1
	// Bit OTP.
	BSEC2_BSEC_OTP_LOCK_OTP = 0x1
	// Position of ROMLOCK field.
	BSEC2_BSEC_OTP_LOCK_ROMLOCK_Pos = 0x1
	// Bit mask of ROMLOCK field.
	BSEC2_BSEC_OTP_LOCK_ROMLOCK_Msk = 0x2
	// Bit ROMLOCK.
	BSEC2_BSEC_OTP_LOCK_ROMLOCK = 0x2
	// Position of DENREG field.
	BSEC2_BSEC_OTP_LOCK_DENREG_Pos = 0x2
	// Bit mask of DENREG field.
	BSEC2_BSEC_OTP_LOCK_DENREG_Msk = 0x4
	// Bit DENREG.
	BSEC2_BSEC_OTP_LOCK_DENREG = 0x4
	// Position of GPLOCK field.
	BSEC2_BSEC_OTP_LOCK_GPLOCK_Pos = 0x4
	// Bit mask of GPLOCK field.
	BSEC2_BSEC_OTP_LOCK_GPLOCK_Msk = 0x10
	// Bit GPLOCK.
	BSEC2_BSEC_OTP_LOCK_GPLOCK = 0x10

	// BSEC_DENABLE: reset value depends on OTP secure mode according toTable18: BSEC_DENABLE default values after reset on page181.
	// Position of DFTEN field.
	BSEC2_BSEC_DENABLE_DFTEN_Pos = 0x0
	// Bit mask of DFTEN field.
	BSEC2_BSEC_DENABLE_DFTEN_Msk = 0x1
	// Bit DFTEN.
	BSEC2_BSEC_DENABLE_DFTEN = 0x1
	// Position of DBGEN field.
	BSEC2_BSEC_DENABLE_DBGEN_Pos = 0x1
	// Bit mask of DBGEN field.
	BSEC2_BSEC_DENABLE_DBGEN_Msk = 0x2
	// Bit DBGEN.
	BSEC2_BSEC_DENABLE_DBGEN = 0x2
	// Position of NIDEN field.
	BSEC2_BSEC_DENABLE_NIDEN_Pos = 0x2
	// Bit mask of NIDEN field.
	BSEC2_BSEC_DENABLE_NIDEN_Msk = 0x4
	// Bit NIDEN.
	BSEC2_BSEC_DENABLE_NIDEN = 0x4
	// Position of DEVICEEN field.
	BSEC2_BSEC_DENABLE_DEVICEEN_Pos = 0x3
	// Bit mask of DEVICEEN field.
	BSEC2_BSEC_DENABLE_DEVICEEN_Msk = 0x8
	// Bit DEVICEEN.
	BSEC2_BSEC_DENABLE_DEVICEEN = 0x8
	// Position of HDPEN field.
	BSEC2_BSEC_DENABLE_HDPEN_Pos = 0x4
	// Bit mask of HDPEN field.
	BSEC2_BSEC_DENABLE_HDPEN_Msk = 0x10
	// Bit HDPEN.
	BSEC2_BSEC_DENABLE_HDPEN = 0x10
	// Position of SPIDEN field.
	BSEC2_BSEC_DENABLE_SPIDEN_Pos = 0x5
	// Bit mask of SPIDEN field.
	BSEC2_BSEC_DENABLE_SPIDEN_Msk = 0x20
	// Bit SPIDEN.
	BSEC2_BSEC_DENABLE_SPIDEN = 0x20
	// Position of SPNIDEN field.
	BSEC2_BSEC_DENABLE_SPNIDEN_Pos = 0x6
	// Bit mask of SPNIDEN field.
	BSEC2_BSEC_DENABLE_SPNIDEN_Msk = 0x40
	// Bit SPNIDEN.
	BSEC2_BSEC_DENABLE_SPNIDEN = 0x40
	// Position of CP15SDISABLE field.
	BSEC2_BSEC_DENABLE_CP15SDISABLE_Pos = 0x7
	// Bit mask of CP15SDISABLE field.
	BSEC2_BSEC_DENABLE_CP15SDISABLE_Msk = 0x180
	// Position of CFGSDISABLE field.
	BSEC2_BSEC_DENABLE_CFGSDISABLE_Pos = 0x9
	// Bit mask of CFGSDISABLE field.
	BSEC2_BSEC_DENABLE_CFGSDISABLE_Msk = 0x200
	// Bit CFGSDISABLE.
	BSEC2_BSEC_DENABLE_CFGSDISABLE = 0x200
	// Position of DBGSWENABLE field.
	BSEC2_BSEC_DENABLE_DBGSWENABLE_Pos = 0xa
	// Bit mask of DBGSWENABLE field.
	BSEC2_BSEC_DENABLE_DBGSWENABLE_Msk = 0x400
	// Bit DBGSWENABLE.
	BSEC2_BSEC_DENABLE_DBGSWENABLE = 0x400

	// BSEC_OTP_DISTURBED0: BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95.
	// Position of DIS field.
	BSEC2_BSEC_OTP_DISTURBED0_DIS_Pos = 0x0
	// Bit mask of DIS field.
	BSEC2_BSEC_OTP_DISTURBED0_DIS_Msk = 0xffffffff

	// BSEC_OTP_DISTURBED1: BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95.
	// Position of DIS field.
	BSEC2_BSEC_OTP_DISTURBED1_DIS_Pos = 0x0
	// Bit mask of DIS field.
	BSEC2_BSEC_OTP_DISTURBED1_DIS_Msk = 0xffffffff

	// BSEC_OTP_DISTURBED2: BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95.
	// Position of DIS field.
	BSEC2_BSEC_OTP_DISTURBED2_DIS_Pos = 0x0
	// Bit mask of DIS field.
	BSEC2_BSEC_OTP_DISTURBED2_DIS_Msk = 0xffffffff

	// BSEC_OTP_ERROR0: BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC.
	// Position of ERR field.
	BSEC2_BSEC_OTP_ERROR0_ERR_Pos = 0x0
	// Bit mask of ERR field.
	BSEC2_BSEC_OTP_ERROR0_ERR_Msk = 0xffffffff

	// BSEC_OTP_ERROR1: BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC.
	// Position of ERR field.
	BSEC2_BSEC_OTP_ERROR1_ERR_Pos = 0x0
	// Bit mask of ERR field.
	BSEC2_BSEC_OTP_ERROR1_ERR_Msk = 0xffffffff

	// BSEC_OTP_ERROR2: BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC.
	// Position of ERR field.
	BSEC2_BSEC_OTP_ERROR2_ERR_Pos = 0x0
	// Bit mask of ERR field.
	BSEC2_BSEC_OTP_ERROR2_ERR_Msk = 0xffffffff

	// BSEC_OTP_WRLOCK0: BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178).
	// Position of WRLOCK field.
	BSEC2_BSEC_OTP_WRLOCK0_WRLOCK_Pos = 0x0
	// Bit mask of WRLOCK field.
	BSEC2_BSEC_OTP_WRLOCK0_WRLOCK_Msk = 0xffffffff

	// BSEC_OTP_WRLOCK1: BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178).
	// Position of WRLOCK field.
	BSEC2_BSEC_OTP_WRLOCK1_WRLOCK_Pos = 0x0
	// Bit mask of WRLOCK field.
	BSEC2_BSEC_OTP_WRLOCK1_WRLOCK_Msk = 0xffffffff

	// BSEC_OTP_WRLOCK2: BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178).
	// Position of WRLOCK field.
	BSEC2_BSEC_OTP_WRLOCK2_WRLOCK_Pos = 0x0
	// Bit mask of WRLOCK field.
	BSEC2_BSEC_OTP_WRLOCK2_WRLOCK_Msk = 0xffffffff

	// BSEC_OTP_SPLOCK0: BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored.
	// Position of SPLOCK field.
	BSEC2_BSEC_OTP_SPLOCK0_SPLOCK_Pos = 0x0
	// Bit mask of SPLOCK field.
	BSEC2_BSEC_OTP_SPLOCK0_SPLOCK_Msk = 0xffffffff

	// BSEC_OTP_SPLOCK1: BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored.
	// Position of SPLOCK field.
	BSEC2_BSEC_OTP_SPLOCK1_SPLOCK_Pos = 0x0
	// Bit mask of SPLOCK field.
	BSEC2_BSEC_OTP_SPLOCK1_SPLOCK_Msk = 0xffffffff

	// BSEC_OTP_SPLOCK2: BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored.
	// Position of SPLOCK field.
	BSEC2_BSEC_OTP_SPLOCK2_SPLOCK_Pos = 0x0
	// Bit mask of SPLOCK field.
	BSEC2_BSEC_OTP_SPLOCK2_SPLOCK_Msk = 0xffffffff

	// BSEC_OTP_SWLOCK0: BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented.
	// Position of SWLOCK field.
	BSEC2_BSEC_OTP_SWLOCK0_SWLOCK_Pos = 0x0
	// Bit mask of SWLOCK field.
	BSEC2_BSEC_OTP_SWLOCK0_SWLOCK_Msk = 0xffffffff

	// BSEC_OTP_SWLOCK1: BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented.
	// Position of SWLOCK field.
	BSEC2_BSEC_OTP_SWLOCK1_SWLOCK_Pos = 0x0
	// Bit mask of SWLOCK field.
	BSEC2_BSEC_OTP_SWLOCK1_SWLOCK_Msk = 0xffffffff

	// BSEC_OTP_SWLOCK2: BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented.
	// Position of SWLOCK field.
	BSEC2_BSEC_OTP_SWLOCK2_SWLOCK_Pos = 0x0
	// Bit mask of SWLOCK field.
	BSEC2_BSEC_OTP_SWLOCK2_SWLOCK_Msk = 0xffffffff

	// BSEC_OTP_SRLOCK0: BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect.
	// Position of SRLOCK field.
	BSEC2_BSEC_OTP_SRLOCK0_SRLOCK_Pos = 0x0
	// Bit mask of SRLOCK field.
	BSEC2_BSEC_OTP_SRLOCK0_SRLOCK_Msk = 0xffffffff

	// BSEC_OTP_SRLOCK1: BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect.
	// Position of SRLOCK field.
	BSEC2_BSEC_OTP_SRLOCK1_SRLOCK_Pos = 0x0
	// Bit mask of SRLOCK field.
	BSEC2_BSEC_OTP_SRLOCK1_SRLOCK_Msk = 0xffffffff

	// BSEC_OTP_SRLOCK2: BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect.
	// Position of SRLOCK field.
	BSEC2_BSEC_OTP_SRLOCK2_SRLOCK_Pos = 0x0
	// Bit mask of SRLOCK field.
	BSEC2_BSEC_OTP_SRLOCK2_SRLOCK_Msk = 0xffffffff

	// BSEC_JTAGIN: BSEC JTAG input register
	// Position of DATA field.
	BSEC2_BSEC_JTAGIN_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_JTAGIN_DATA_Msk = 0xffff

	// BSEC_JTAGOUT: BSEC JTAG output register
	// Position of DATA field.
	BSEC2_BSEC_JTAGOUT_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_JTAGOUT_DATA_Msk = 0xffff

	// BSEC_SCRATCH: BSEC scratch register
	// Position of DATA field.
	BSEC2_BSEC_SCRATCH_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_SCRATCH_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA0: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA0_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA0_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA1: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA1_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA1_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA2: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA2_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA2_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA3: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA3_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA3_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA4: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA4_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA4_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA5: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA5_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA5_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA6: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA6_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA6_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA7: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA7_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA7_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA8: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA8_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA8_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA9: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA9_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA9_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA10: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA10_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA10_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA11: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA11_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA11_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA12: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA12_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA12_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA13: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA13_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA13_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA14: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA14_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA14_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA15: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA15_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA15_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA16: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA16_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA16_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA17: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA17_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA17_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA18: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA18_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA18_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA19: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA19_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA19_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA20: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA20_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA20_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA21: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA21_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA21_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA22: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA22_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA22_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA23: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA23_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA23_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA24: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA24_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA24_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA25: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA25_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA25_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA26: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA26_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA26_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA27: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA27_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA27_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA28: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA28_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA28_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA29: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA29_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA29_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA30: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA30_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA30_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA31: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA31_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA31_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA32: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA32_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA32_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA33: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA33_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA33_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA34: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA34_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA34_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA35: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA35_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA35_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA36: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA36_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA36_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA37: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA37_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA37_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA38: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA38_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA38_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA39: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA39_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA39_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA40: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA40_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA40_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA41: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA41_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA41_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA42: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA42_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA42_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA43: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA43_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA43_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA44: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA44_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA44_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA45: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA45_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA45_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA46: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA46_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA46_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA47: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA47_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA47_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA48: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA48_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA48_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA49: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA49_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA49_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA50: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA50_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA50_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA51: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA51_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA51_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA52: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA52_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA52_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA53: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA53_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA53_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA54: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA54_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA54_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA55: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA55_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA55_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA56: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA56_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA56_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA57: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA57_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA57_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA58: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA58_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA58_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA59: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA59_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA59_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA60: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA60_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA60_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA61: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA61_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA61_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA62: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA62_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA62_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA63: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA63_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA63_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA64: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA64_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA64_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA65: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA65_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA65_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA66: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA66_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA66_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA67: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA67_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA67_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA68: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA68_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA68_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA69: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA69_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA69_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA70: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA70_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA70_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA71: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA71_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA71_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA72: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA72_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA72_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA73: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA73_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA73_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA74: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA74_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA74_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA75: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA75_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA75_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA76: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA76_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA76_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA77: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA77_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA77_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA78: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA78_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA78_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA79: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA79_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA79_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA80: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA80_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA80_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA81: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA81_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA81_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA82: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA82_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA82_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA83: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA83_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA83_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA84: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA84_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA84_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA85: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA85_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA85_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA86: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA86_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA86_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA87: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA87_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA87_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA88: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA88_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA88_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA89: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA89_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA89_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA90: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA90_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA90_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA91: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA91_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA91_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA92: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA92_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA92_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA93: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA93_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA93_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA94: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA94_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA94_DATA_Msk = 0xffffffff

	// BSEC_OTP_DATA95: Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.
	// Position of DATA field.
	BSEC2_BSEC_OTP_DATA95_DATA_Pos = 0x0
	// Bit mask of DATA field.
	BSEC2_BSEC_OTP_DATA95_DATA_Msk = 0xffffffff

	// BSEC_HWCFGR: BSEC hardware configuration register
	// Position of SIZE field.
	BSEC2_BSEC_HWCFGR_SIZE_Pos = 0x0
	// Bit mask of SIZE field.
	BSEC2_BSEC_HWCFGR_SIZE_Msk = 0xf
	// Position of ECC_USE field.
	BSEC2_BSEC_HWCFGR_ECC_USE_Pos = 0x4
	// Bit mask of ECC_USE field.
	BSEC2_BSEC_HWCFGR_ECC_USE_Msk = 0xf0

	// BSEC_VERR: BSEC version register
	// Position of MINREV field.
	BSEC2_BSEC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	BSEC2_BSEC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	BSEC2_BSEC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	BSEC2_BSEC_VERR_MAJREV_Msk = 0xf0

	// BSEC_IPIDR: BSEC identification register
	// Position of ID field.
	BSEC2_BSEC_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	BSEC2_BSEC_IPIDR_ID_Msk = 0xffffffff

	// BSEC_SIDR: BSEC size identification register
	// Position of SID field.
	BSEC2_BSEC_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	BSEC2_BSEC_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for CCU: CCU
const (
	// FCCAN_CCU_CREL: Clock calibration unit core release register
	// Position of DAY field.
	CCU_FCCAN_CCU_CREL_DAY_Pos = 0x0
	// Bit mask of DAY field.
	CCU_FCCAN_CCU_CREL_DAY_Msk = 0xff
	// Position of MON field.
	CCU_FCCAN_CCU_CREL_MON_Pos = 0x8
	// Bit mask of MON field.
	CCU_FCCAN_CCU_CREL_MON_Msk = 0xff00
	// Position of YEAR field.
	CCU_FCCAN_CCU_CREL_YEAR_Pos = 0x10
	// Bit mask of YEAR field.
	CCU_FCCAN_CCU_CREL_YEAR_Msk = 0xf0000
	// Position of SUBSTEP field.
	CCU_FCCAN_CCU_CREL_SUBSTEP_Pos = 0x14
	// Bit mask of SUBSTEP field.
	CCU_FCCAN_CCU_CREL_SUBSTEP_Msk = 0xf00000
	// Position of STEP field.
	CCU_FCCAN_CCU_CREL_STEP_Pos = 0x18
	// Bit mask of STEP field.
	CCU_FCCAN_CCU_CREL_STEP_Msk = 0xf000000
	// Position of REL field.
	CCU_FCCAN_CCU_CREL_REL_Pos = 0x1c
	// Bit mask of REL field.
	CCU_FCCAN_CCU_CREL_REL_Msk = 0xf0000000

	// FCCAN_CCU_CCFG: Calibration configuration register
	// Position of TQBT field.
	CCU_FCCAN_CCU_CCFG_TQBT_Pos = 0x0
	// Bit mask of TQBT field.
	CCU_FCCAN_CCU_CCFG_TQBT_Msk = 0x1f
	// Position of BCC field.
	CCU_FCCAN_CCU_CCFG_BCC_Pos = 0x6
	// Bit mask of BCC field.
	CCU_FCCAN_CCU_CCFG_BCC_Msk = 0x40
	// Bit BCC.
	CCU_FCCAN_CCU_CCFG_BCC = 0x40
	// Position of CFL field.
	CCU_FCCAN_CCU_CCFG_CFL_Pos = 0x7
	// Bit mask of CFL field.
	CCU_FCCAN_CCU_CCFG_CFL_Msk = 0x80
	// Bit CFL.
	CCU_FCCAN_CCU_CCFG_CFL = 0x80
	// Position of OCPM field.
	CCU_FCCAN_CCU_CCFG_OCPM_Pos = 0x8
	// Bit mask of OCPM field.
	CCU_FCCAN_CCU_CCFG_OCPM_Msk = 0xff00
	// Position of CDIV field.
	CCU_FCCAN_CCU_CCFG_CDIV_Pos = 0x10
	// Bit mask of CDIV field.
	CCU_FCCAN_CCU_CCFG_CDIV_Msk = 0xf0000
	// Position of SWR field.
	CCU_FCCAN_CCU_CCFG_SWR_Pos = 0x1f
	// Bit mask of SWR field.
	CCU_FCCAN_CCU_CCFG_SWR_Msk = 0x80000000
	// Bit SWR.
	CCU_FCCAN_CCU_CCFG_SWR = 0x80000000

	// FCCAN_CCU_CSTAT: Calibration status register
	// Position of OCPC field.
	CCU_FCCAN_CCU_CSTAT_OCPC_Pos = 0x0
	// Bit mask of OCPC field.
	CCU_FCCAN_CCU_CSTAT_OCPC_Msk = 0x3ffff
	// Position of TQC field.
	CCU_FCCAN_CCU_CSTAT_TQC_Pos = 0x12
	// Bit mask of TQC field.
	CCU_FCCAN_CCU_CSTAT_TQC_Msk = 0x1ffc0000
	// Position of CALS field.
	CCU_FCCAN_CCU_CSTAT_CALS_Pos = 0x1e
	// Bit mask of CALS field.
	CCU_FCCAN_CCU_CSTAT_CALS_Msk = 0xc0000000

	// FCCAN_CCU_CWD: The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CCU_CSTAT.CALS = 01), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CCU_CSTAT.CALS = 10) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CCU_CSTAT.CALS = 01). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CCU_IR.CWE. If enabled by CCU_IE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CCU_IR.CWE is reset.
	// Position of WDC field.
	CCU_FCCAN_CCU_CWD_WDC_Pos = 0x0
	// Bit mask of WDC field.
	CCU_FCCAN_CCU_CWD_WDC_Msk = 0xffff
	// Position of WDV field.
	CCU_FCCAN_CCU_CWD_WDV_Pos = 0x10
	// Bit mask of WDV field.
	CCU_FCCAN_CCU_CWD_WDV_Msk = 0xffff0000

	// FCCAN_CCU_IR: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of CCU_IE controls whether an interrupt is generated or not.
	// Position of CWE field.
	CCU_FCCAN_CCU_IR_CWE_Pos = 0x0
	// Bit mask of CWE field.
	CCU_FCCAN_CCU_IR_CWE_Msk = 0x1
	// Bit CWE.
	CCU_FCCAN_CCU_IR_CWE = 0x1
	// Position of CSC field.
	CCU_FCCAN_CCU_IR_CSC_Pos = 0x1
	// Bit mask of CSC field.
	CCU_FCCAN_CCU_IR_CSC_Msk = 0x2
	// Bit CSC.
	CCU_FCCAN_CCU_IR_CSC = 0x2

	// FCCAN_CCU_IE: The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line.
	// Position of CWEE field.
	CCU_FCCAN_CCU_IE_CWEE_Pos = 0x0
	// Bit mask of CWEE field.
	CCU_FCCAN_CCU_IE_CWEE_Msk = 0x1
	// Bit CWEE.
	CCU_FCCAN_CCU_IE_CWEE = 0x1
	// Position of CSCE field.
	CCU_FCCAN_CCU_IE_CSCE_Pos = 0x1
	// Bit mask of CSCE field.
	CCU_FCCAN_CCU_IE_CSCE_Msk = 0x2
	// Bit CSCE.
	CCU_FCCAN_CCU_IE_CSCE = 0x2
)

// Bitfields for CRC1: CRC1
const (
	// CRC_DR: CRC data register
	// Position of DR field.
	CRC1_CRC_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	CRC1_CRC_DR_DR_Msk = 0xffffffff

	// CRC_IDR: CRC independent data register
	// Position of IDR field.
	CRC1_CRC_IDR_IDR_Pos = 0x0
	// Bit mask of IDR field.
	CRC1_CRC_IDR_IDR_Msk = 0xffffffff

	// CRC_CR: CRC control register
	// Position of RESET field.
	CRC1_CRC_CR_RESET_Pos = 0x0
	// Bit mask of RESET field.
	CRC1_CRC_CR_RESET_Msk = 0x1
	// Bit RESET.
	CRC1_CRC_CR_RESET = 0x1
	// Position of POLYSIZE field.
	CRC1_CRC_CR_POLYSIZE_Pos = 0x3
	// Bit mask of POLYSIZE field.
	CRC1_CRC_CR_POLYSIZE_Msk = 0x18
	// Position of REV_IN field.
	CRC1_CRC_CR_REV_IN_Pos = 0x5
	// Bit mask of REV_IN field.
	CRC1_CRC_CR_REV_IN_Msk = 0x60
	// Position of REV_OUT field.
	CRC1_CRC_CR_REV_OUT_Pos = 0x7
	// Bit mask of REV_OUT field.
	CRC1_CRC_CR_REV_OUT_Msk = 0x80
	// Bit REV_OUT.
	CRC1_CRC_CR_REV_OUT = 0x80

	// CRC_INIT: CRC initial value
	// Position of CRC_INIT field.
	CRC1_CRC_INIT_CRC_INIT_Pos = 0x0
	// Bit mask of CRC_INIT field.
	CRC1_CRC_INIT_CRC_INIT_Msk = 0xffffffff

	// CRC_POL: CRC polynomial
	// Position of POL field.
	CRC1_CRC_POL_POL_Pos = 0x0
	// Bit mask of POL field.
	CRC1_CRC_POL_POL_Msk = 0xffffffff
)

// Bitfields for CRYP1: CRYP1
const (
	// CRYP_CR: CRYP control register
	// Position of ALGODIR field.
	CRYP1_CRYP_CR_ALGODIR_Pos = 0x2
	// Bit mask of ALGODIR field.
	CRYP1_CRYP_CR_ALGODIR_Msk = 0x4
	// Bit ALGODIR.
	CRYP1_CRYP_CR_ALGODIR = 0x4
	// Position of ALGOMODE field.
	CRYP1_CRYP_CR_ALGOMODE_Pos = 0x3
	// Bit mask of ALGOMODE field.
	CRYP1_CRYP_CR_ALGOMODE_Msk = 0x38
	// Position of DATATYPE field.
	CRYP1_CRYP_CR_DATATYPE_Pos = 0x6
	// Bit mask of DATATYPE field.
	CRYP1_CRYP_CR_DATATYPE_Msk = 0xc0
	// Position of KEYSIZE field.
	CRYP1_CRYP_CR_KEYSIZE_Pos = 0x8
	// Bit mask of KEYSIZE field.
	CRYP1_CRYP_CR_KEYSIZE_Msk = 0x300
	// Position of FFLUSH field.
	CRYP1_CRYP_CR_FFLUSH_Pos = 0xe
	// Bit mask of FFLUSH field.
	CRYP1_CRYP_CR_FFLUSH_Msk = 0x4000
	// Bit FFLUSH.
	CRYP1_CRYP_CR_FFLUSH = 0x4000
	// Position of CRYPEN field.
	CRYP1_CRYP_CR_CRYPEN_Pos = 0xf
	// Bit mask of CRYPEN field.
	CRYP1_CRYP_CR_CRYPEN_Msk = 0x8000
	// Bit CRYPEN.
	CRYP1_CRYP_CR_CRYPEN = 0x8000
	// Position of GCM_CCMPH field.
	CRYP1_CRYP_CR_GCM_CCMPH_Pos = 0x10
	// Bit mask of GCM_CCMPH field.
	CRYP1_CRYP_CR_GCM_CCMPH_Msk = 0x30000
	// Position of ALGOMODE3 field.
	CRYP1_CRYP_CR_ALGOMODE3_Pos = 0x13
	// Bit mask of ALGOMODE3 field.
	CRYP1_CRYP_CR_ALGOMODE3_Msk = 0x80000
	// Bit ALGOMODE3.
	CRYP1_CRYP_CR_ALGOMODE3 = 0x80000
	// Position of NPBLB field.
	CRYP1_CRYP_CR_NPBLB_Pos = 0x14
	// Bit mask of NPBLB field.
	CRYP1_CRYP_CR_NPBLB_Msk = 0xf00000

	// CRYP_SR: CRYP status register
	// Position of IFEM field.
	CRYP1_CRYP_SR_IFEM_Pos = 0x0
	// Bit mask of IFEM field.
	CRYP1_CRYP_SR_IFEM_Msk = 0x1
	// Bit IFEM.
	CRYP1_CRYP_SR_IFEM = 0x1
	// Position of IFNF field.
	CRYP1_CRYP_SR_IFNF_Pos = 0x1
	// Bit mask of IFNF field.
	CRYP1_CRYP_SR_IFNF_Msk = 0x2
	// Bit IFNF.
	CRYP1_CRYP_SR_IFNF = 0x2
	// Position of OFNE field.
	CRYP1_CRYP_SR_OFNE_Pos = 0x2
	// Bit mask of OFNE field.
	CRYP1_CRYP_SR_OFNE_Msk = 0x4
	// Bit OFNE.
	CRYP1_CRYP_SR_OFNE = 0x4
	// Position of OFFU field.
	CRYP1_CRYP_SR_OFFU_Pos = 0x3
	// Bit mask of OFFU field.
	CRYP1_CRYP_SR_OFFU_Msk = 0x8
	// Bit OFFU.
	CRYP1_CRYP_SR_OFFU = 0x8
	// Position of BUSY field.
	CRYP1_CRYP_SR_BUSY_Pos = 0x4
	// Bit mask of BUSY field.
	CRYP1_CRYP_SR_BUSY_Msk = 0x10
	// Bit BUSY.
	CRYP1_CRYP_SR_BUSY = 0x10

	// CRYP_DIN: The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data.
	// Position of DATAIN field.
	CRYP1_CRYP_DIN_DATAIN_Pos = 0x0
	// Bit mask of DATAIN field.
	CRYP1_CRYP_DIN_DATAIN_Msk = 0xffffffff

	// CRYP_DOUT: The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.
	// Position of DATAOUT field.
	CRYP1_CRYP_DOUT_DATAOUT_Pos = 0x0
	// Bit mask of DATAOUT field.
	CRYP1_CRYP_DOUT_DATAOUT_Msk = 0xffffffff

	// CRYP_DMACR: CRYP DMA control register
	// Position of DIEN field.
	CRYP1_CRYP_DMACR_DIEN_Pos = 0x0
	// Bit mask of DIEN field.
	CRYP1_CRYP_DMACR_DIEN_Msk = 0x1
	// Bit DIEN.
	CRYP1_CRYP_DMACR_DIEN = 0x1
	// Position of DOEN field.
	CRYP1_CRYP_DMACR_DOEN_Pos = 0x1
	// Bit mask of DOEN field.
	CRYP1_CRYP_DMACR_DOEN_Msk = 0x2
	// Bit DOEN.
	CRYP1_CRYP_DMACR_DOEN = 0x2

	// CRYP_IMSCR: The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.
	// Position of INIM field.
	CRYP1_CRYP_IMSCR_INIM_Pos = 0x0
	// Bit mask of INIM field.
	CRYP1_CRYP_IMSCR_INIM_Msk = 0x1
	// Bit INIM.
	CRYP1_CRYP_IMSCR_INIM = 0x1
	// Position of OUTIM field.
	CRYP1_CRYP_IMSCR_OUTIM_Pos = 0x1
	// Bit mask of OUTIM field.
	CRYP1_CRYP_IMSCR_OUTIM_Msk = 0x2
	// Bit OUTIM.
	CRYP1_CRYP_IMSCR_OUTIM = 0x2

	// CRYP_RISR: The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.
	// Position of INRIS field.
	CRYP1_CRYP_RISR_INRIS_Pos = 0x0
	// Bit mask of INRIS field.
	CRYP1_CRYP_RISR_INRIS_Msk = 0x1
	// Bit INRIS.
	CRYP1_CRYP_RISR_INRIS = 0x1
	// Position of OUTRIS field.
	CRYP1_CRYP_RISR_OUTRIS_Pos = 0x1
	// Bit mask of OUTRIS field.
	CRYP1_CRYP_RISR_OUTRIS_Msk = 0x2
	// Bit OUTRIS.
	CRYP1_CRYP_RISR_OUTRIS = 0x2

	// CRYP_MISR: The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.
	// Position of INMIS field.
	CRYP1_CRYP_MISR_INMIS_Pos = 0x0
	// Bit mask of INMIS field.
	CRYP1_CRYP_MISR_INMIS_Msk = 0x1
	// Bit INMIS.
	CRYP1_CRYP_MISR_INMIS = 0x1
	// Position of OUTMIS field.
	CRYP1_CRYP_MISR_OUTMIS_Pos = 0x1
	// Bit mask of OUTMIS field.
	CRYP1_CRYP_MISR_OUTMIS_Msk = 0x2
	// Bit OUTMIS.
	CRYP1_CRYP_MISR_OUTMIS = 0x2

	// CRYP_K0LR: CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register)
	// Position of K field.
	CRYP1_CRYP_K0LR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K0LR_K_Msk = 0xffffffff

	// CRYP_K0RR: Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
	// Position of K field.
	CRYP1_CRYP_K0RR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K0RR_K_Msk = 0xffffffff

	// CRYP_K1LR: Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
	// Position of K field.
	CRYP1_CRYP_K1LR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K1LR_K_Msk = 0xffffffff

	// CRYP_K1RR: Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
	// Position of K field.
	CRYP1_CRYP_K1RR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K1RR_K_Msk = 0xffffffff

	// CRYP_K2LR: Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
	// Position of K field.
	CRYP1_CRYP_K2LR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K2LR_K_Msk = 0xffffffff

	// CRYP_K2RR: Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
	// Position of K field.
	CRYP1_CRYP_K2RR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K2RR_K_Msk = 0xffffffff

	// CRYP_K3LR: Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
	// Position of K field.
	CRYP1_CRYP_K3LR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K3LR_K_Msk = 0xffffffff

	// CRYP_K3RR: Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
	// Position of K field.
	CRYP1_CRYP_K3RR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP1_CRYP_K3RR_K_Msk = 0xffffffff

	// CRYP_IV0LR: The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).
	// Position of IV31 field.
	CRYP1_CRYP_IV0LR_IV31_Pos = 0x0
	// Bit mask of IV31 field.
	CRYP1_CRYP_IV0LR_IV31_Msk = 0x1
	// Bit IV31.
	CRYP1_CRYP_IV0LR_IV31 = 0x1
	// Position of IV30 field.
	CRYP1_CRYP_IV0LR_IV30_Pos = 0x1
	// Bit mask of IV30 field.
	CRYP1_CRYP_IV0LR_IV30_Msk = 0x2
	// Bit IV30.
	CRYP1_CRYP_IV0LR_IV30 = 0x2
	// Position of IV29 field.
	CRYP1_CRYP_IV0LR_IV29_Pos = 0x2
	// Bit mask of IV29 field.
	CRYP1_CRYP_IV0LR_IV29_Msk = 0x4
	// Bit IV29.
	CRYP1_CRYP_IV0LR_IV29 = 0x4
	// Position of IV28 field.
	CRYP1_CRYP_IV0LR_IV28_Pos = 0x3
	// Bit mask of IV28 field.
	CRYP1_CRYP_IV0LR_IV28_Msk = 0x8
	// Bit IV28.
	CRYP1_CRYP_IV0LR_IV28 = 0x8
	// Position of IV27 field.
	CRYP1_CRYP_IV0LR_IV27_Pos = 0x4
	// Bit mask of IV27 field.
	CRYP1_CRYP_IV0LR_IV27_Msk = 0x10
	// Bit IV27.
	CRYP1_CRYP_IV0LR_IV27 = 0x10
	// Position of IV26 field.
	CRYP1_CRYP_IV0LR_IV26_Pos = 0x5
	// Bit mask of IV26 field.
	CRYP1_CRYP_IV0LR_IV26_Msk = 0x20
	// Bit IV26.
	CRYP1_CRYP_IV0LR_IV26 = 0x20
	// Position of IV25 field.
	CRYP1_CRYP_IV0LR_IV25_Pos = 0x6
	// Bit mask of IV25 field.
	CRYP1_CRYP_IV0LR_IV25_Msk = 0x40
	// Bit IV25.
	CRYP1_CRYP_IV0LR_IV25 = 0x40
	// Position of IV24 field.
	CRYP1_CRYP_IV0LR_IV24_Pos = 0x7
	// Bit mask of IV24 field.
	CRYP1_CRYP_IV0LR_IV24_Msk = 0x80
	// Bit IV24.
	CRYP1_CRYP_IV0LR_IV24 = 0x80
	// Position of IV23 field.
	CRYP1_CRYP_IV0LR_IV23_Pos = 0x8
	// Bit mask of IV23 field.
	CRYP1_CRYP_IV0LR_IV23_Msk = 0x100
	// Bit IV23.
	CRYP1_CRYP_IV0LR_IV23 = 0x100
	// Position of IV22 field.
	CRYP1_CRYP_IV0LR_IV22_Pos = 0x9
	// Bit mask of IV22 field.
	CRYP1_CRYP_IV0LR_IV22_Msk = 0x200
	// Bit IV22.
	CRYP1_CRYP_IV0LR_IV22 = 0x200
	// Position of IV21 field.
	CRYP1_CRYP_IV0LR_IV21_Pos = 0xa
	// Bit mask of IV21 field.
	CRYP1_CRYP_IV0LR_IV21_Msk = 0x400
	// Bit IV21.
	CRYP1_CRYP_IV0LR_IV21 = 0x400
	// Position of IV20 field.
	CRYP1_CRYP_IV0LR_IV20_Pos = 0xb
	// Bit mask of IV20 field.
	CRYP1_CRYP_IV0LR_IV20_Msk = 0x800
	// Bit IV20.
	CRYP1_CRYP_IV0LR_IV20 = 0x800
	// Position of IV19 field.
	CRYP1_CRYP_IV0LR_IV19_Pos = 0xc
	// Bit mask of IV19 field.
	CRYP1_CRYP_IV0LR_IV19_Msk = 0x1000
	// Bit IV19.
	CRYP1_CRYP_IV0LR_IV19 = 0x1000
	// Position of IV18 field.
	CRYP1_CRYP_IV0LR_IV18_Pos = 0xd
	// Bit mask of IV18 field.
	CRYP1_CRYP_IV0LR_IV18_Msk = 0x2000
	// Bit IV18.
	CRYP1_CRYP_IV0LR_IV18 = 0x2000
	// Position of IV17 field.
	CRYP1_CRYP_IV0LR_IV17_Pos = 0xe
	// Bit mask of IV17 field.
	CRYP1_CRYP_IV0LR_IV17_Msk = 0x4000
	// Bit IV17.
	CRYP1_CRYP_IV0LR_IV17 = 0x4000
	// Position of IV16 field.
	CRYP1_CRYP_IV0LR_IV16_Pos = 0xf
	// Bit mask of IV16 field.
	CRYP1_CRYP_IV0LR_IV16_Msk = 0x8000
	// Bit IV16.
	CRYP1_CRYP_IV0LR_IV16 = 0x8000
	// Position of IV15 field.
	CRYP1_CRYP_IV0LR_IV15_Pos = 0x10
	// Bit mask of IV15 field.
	CRYP1_CRYP_IV0LR_IV15_Msk = 0x10000
	// Bit IV15.
	CRYP1_CRYP_IV0LR_IV15 = 0x10000
	// Position of IV14 field.
	CRYP1_CRYP_IV0LR_IV14_Pos = 0x11
	// Bit mask of IV14 field.
	CRYP1_CRYP_IV0LR_IV14_Msk = 0x20000
	// Bit IV14.
	CRYP1_CRYP_IV0LR_IV14 = 0x20000
	// Position of IV13 field.
	CRYP1_CRYP_IV0LR_IV13_Pos = 0x12
	// Bit mask of IV13 field.
	CRYP1_CRYP_IV0LR_IV13_Msk = 0x40000
	// Bit IV13.
	CRYP1_CRYP_IV0LR_IV13 = 0x40000
	// Position of IV12 field.
	CRYP1_CRYP_IV0LR_IV12_Pos = 0x13
	// Bit mask of IV12 field.
	CRYP1_CRYP_IV0LR_IV12_Msk = 0x80000
	// Bit IV12.
	CRYP1_CRYP_IV0LR_IV12 = 0x80000
	// Position of IV11 field.
	CRYP1_CRYP_IV0LR_IV11_Pos = 0x14
	// Bit mask of IV11 field.
	CRYP1_CRYP_IV0LR_IV11_Msk = 0x100000
	// Bit IV11.
	CRYP1_CRYP_IV0LR_IV11 = 0x100000
	// Position of IV10 field.
	CRYP1_CRYP_IV0LR_IV10_Pos = 0x15
	// Bit mask of IV10 field.
	CRYP1_CRYP_IV0LR_IV10_Msk = 0x200000
	// Bit IV10.
	CRYP1_CRYP_IV0LR_IV10 = 0x200000
	// Position of IV9 field.
	CRYP1_CRYP_IV0LR_IV9_Pos = 0x16
	// Bit mask of IV9 field.
	CRYP1_CRYP_IV0LR_IV9_Msk = 0x400000
	// Bit IV9.
	CRYP1_CRYP_IV0LR_IV9 = 0x400000
	// Position of IV8 field.
	CRYP1_CRYP_IV0LR_IV8_Pos = 0x17
	// Bit mask of IV8 field.
	CRYP1_CRYP_IV0LR_IV8_Msk = 0x800000
	// Bit IV8.
	CRYP1_CRYP_IV0LR_IV8 = 0x800000
	// Position of IV7 field.
	CRYP1_CRYP_IV0LR_IV7_Pos = 0x18
	// Bit mask of IV7 field.
	CRYP1_CRYP_IV0LR_IV7_Msk = 0x1000000
	// Bit IV7.
	CRYP1_CRYP_IV0LR_IV7 = 0x1000000
	// Position of IV6 field.
	CRYP1_CRYP_IV0LR_IV6_Pos = 0x19
	// Bit mask of IV6 field.
	CRYP1_CRYP_IV0LR_IV6_Msk = 0x2000000
	// Bit IV6.
	CRYP1_CRYP_IV0LR_IV6 = 0x2000000
	// Position of IV5 field.
	CRYP1_CRYP_IV0LR_IV5_Pos = 0x1a
	// Bit mask of IV5 field.
	CRYP1_CRYP_IV0LR_IV5_Msk = 0x4000000
	// Bit IV5.
	CRYP1_CRYP_IV0LR_IV5 = 0x4000000
	// Position of IV4 field.
	CRYP1_CRYP_IV0LR_IV4_Pos = 0x1b
	// Bit mask of IV4 field.
	CRYP1_CRYP_IV0LR_IV4_Msk = 0x8000000
	// Bit IV4.
	CRYP1_CRYP_IV0LR_IV4 = 0x8000000
	// Position of IV3 field.
	CRYP1_CRYP_IV0LR_IV3_Pos = 0x1c
	// Bit mask of IV3 field.
	CRYP1_CRYP_IV0LR_IV3_Msk = 0x10000000
	// Bit IV3.
	CRYP1_CRYP_IV0LR_IV3 = 0x10000000
	// Position of IV2 field.
	CRYP1_CRYP_IV0LR_IV2_Pos = 0x1d
	// Bit mask of IV2 field.
	CRYP1_CRYP_IV0LR_IV2_Msk = 0x20000000
	// Bit IV2.
	CRYP1_CRYP_IV0LR_IV2 = 0x20000000
	// Position of IV1 field.
	CRYP1_CRYP_IV0LR_IV1_Pos = 0x1e
	// Bit mask of IV1 field.
	CRYP1_CRYP_IV0LR_IV1_Msk = 0x40000000
	// Bit IV1.
	CRYP1_CRYP_IV0LR_IV1 = 0x40000000
	// Position of IV0 field.
	CRYP1_CRYP_IV0LR_IV0_Pos = 0x1f
	// Bit mask of IV0 field.
	CRYP1_CRYP_IV0LR_IV0_Msk = 0x80000000
	// Bit IV0.
	CRYP1_CRYP_IV0LR_IV0 = 0x80000000

	// CRYP_IV0RR: Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
	// Position of IV63 field.
	CRYP1_CRYP_IV0RR_IV63_Pos = 0x0
	// Bit mask of IV63 field.
	CRYP1_CRYP_IV0RR_IV63_Msk = 0x1
	// Bit IV63.
	CRYP1_CRYP_IV0RR_IV63 = 0x1
	// Position of IV62 field.
	CRYP1_CRYP_IV0RR_IV62_Pos = 0x1
	// Bit mask of IV62 field.
	CRYP1_CRYP_IV0RR_IV62_Msk = 0x2
	// Bit IV62.
	CRYP1_CRYP_IV0RR_IV62 = 0x2
	// Position of IV61 field.
	CRYP1_CRYP_IV0RR_IV61_Pos = 0x2
	// Bit mask of IV61 field.
	CRYP1_CRYP_IV0RR_IV61_Msk = 0x4
	// Bit IV61.
	CRYP1_CRYP_IV0RR_IV61 = 0x4
	// Position of IV60 field.
	CRYP1_CRYP_IV0RR_IV60_Pos = 0x3
	// Bit mask of IV60 field.
	CRYP1_CRYP_IV0RR_IV60_Msk = 0x8
	// Bit IV60.
	CRYP1_CRYP_IV0RR_IV60 = 0x8
	// Position of IV59 field.
	CRYP1_CRYP_IV0RR_IV59_Pos = 0x4
	// Bit mask of IV59 field.
	CRYP1_CRYP_IV0RR_IV59_Msk = 0x10
	// Bit IV59.
	CRYP1_CRYP_IV0RR_IV59 = 0x10
	// Position of IV58 field.
	CRYP1_CRYP_IV0RR_IV58_Pos = 0x5
	// Bit mask of IV58 field.
	CRYP1_CRYP_IV0RR_IV58_Msk = 0x20
	// Bit IV58.
	CRYP1_CRYP_IV0RR_IV58 = 0x20
	// Position of IV57 field.
	CRYP1_CRYP_IV0RR_IV57_Pos = 0x6
	// Bit mask of IV57 field.
	CRYP1_CRYP_IV0RR_IV57_Msk = 0x40
	// Bit IV57.
	CRYP1_CRYP_IV0RR_IV57 = 0x40
	// Position of IV56 field.
	CRYP1_CRYP_IV0RR_IV56_Pos = 0x7
	// Bit mask of IV56 field.
	CRYP1_CRYP_IV0RR_IV56_Msk = 0x80
	// Bit IV56.
	CRYP1_CRYP_IV0RR_IV56 = 0x80
	// Position of IV55 field.
	CRYP1_CRYP_IV0RR_IV55_Pos = 0x8
	// Bit mask of IV55 field.
	CRYP1_CRYP_IV0RR_IV55_Msk = 0x100
	// Bit IV55.
	CRYP1_CRYP_IV0RR_IV55 = 0x100
	// Position of IV54 field.
	CRYP1_CRYP_IV0RR_IV54_Pos = 0x9
	// Bit mask of IV54 field.
	CRYP1_CRYP_IV0RR_IV54_Msk = 0x200
	// Bit IV54.
	CRYP1_CRYP_IV0RR_IV54 = 0x200
	// Position of IV53 field.
	CRYP1_CRYP_IV0RR_IV53_Pos = 0xa
	// Bit mask of IV53 field.
	CRYP1_CRYP_IV0RR_IV53_Msk = 0x400
	// Bit IV53.
	CRYP1_CRYP_IV0RR_IV53 = 0x400
	// Position of IV52 field.
	CRYP1_CRYP_IV0RR_IV52_Pos = 0xb
	// Bit mask of IV52 field.
	CRYP1_CRYP_IV0RR_IV52_Msk = 0x800
	// Bit IV52.
	CRYP1_CRYP_IV0RR_IV52 = 0x800
	// Position of IV51 field.
	CRYP1_CRYP_IV0RR_IV51_Pos = 0xc
	// Bit mask of IV51 field.
	CRYP1_CRYP_IV0RR_IV51_Msk = 0x1000
	// Bit IV51.
	CRYP1_CRYP_IV0RR_IV51 = 0x1000
	// Position of IV50 field.
	CRYP1_CRYP_IV0RR_IV50_Pos = 0xd
	// Bit mask of IV50 field.
	CRYP1_CRYP_IV0RR_IV50_Msk = 0x2000
	// Bit IV50.
	CRYP1_CRYP_IV0RR_IV50 = 0x2000
	// Position of IV49 field.
	CRYP1_CRYP_IV0RR_IV49_Pos = 0xe
	// Bit mask of IV49 field.
	CRYP1_CRYP_IV0RR_IV49_Msk = 0x4000
	// Bit IV49.
	CRYP1_CRYP_IV0RR_IV49 = 0x4000
	// Position of IV48 field.
	CRYP1_CRYP_IV0RR_IV48_Pos = 0xf
	// Bit mask of IV48 field.
	CRYP1_CRYP_IV0RR_IV48_Msk = 0x8000
	// Bit IV48.
	CRYP1_CRYP_IV0RR_IV48 = 0x8000
	// Position of IV47 field.
	CRYP1_CRYP_IV0RR_IV47_Pos = 0x10
	// Bit mask of IV47 field.
	CRYP1_CRYP_IV0RR_IV47_Msk = 0x10000
	// Bit IV47.
	CRYP1_CRYP_IV0RR_IV47 = 0x10000
	// Position of IV46 field.
	CRYP1_CRYP_IV0RR_IV46_Pos = 0x11
	// Bit mask of IV46 field.
	CRYP1_CRYP_IV0RR_IV46_Msk = 0x20000
	// Bit IV46.
	CRYP1_CRYP_IV0RR_IV46 = 0x20000
	// Position of IV45 field.
	CRYP1_CRYP_IV0RR_IV45_Pos = 0x12
	// Bit mask of IV45 field.
	CRYP1_CRYP_IV0RR_IV45_Msk = 0x40000
	// Bit IV45.
	CRYP1_CRYP_IV0RR_IV45 = 0x40000
	// Position of IV44 field.
	CRYP1_CRYP_IV0RR_IV44_Pos = 0x13
	// Bit mask of IV44 field.
	CRYP1_CRYP_IV0RR_IV44_Msk = 0x80000
	// Bit IV44.
	CRYP1_CRYP_IV0RR_IV44 = 0x80000
	// Position of IV43 field.
	CRYP1_CRYP_IV0RR_IV43_Pos = 0x14
	// Bit mask of IV43 field.
	CRYP1_CRYP_IV0RR_IV43_Msk = 0x100000
	// Bit IV43.
	CRYP1_CRYP_IV0RR_IV43 = 0x100000
	// Position of IV42 field.
	CRYP1_CRYP_IV0RR_IV42_Pos = 0x15
	// Bit mask of IV42 field.
	CRYP1_CRYP_IV0RR_IV42_Msk = 0x200000
	// Bit IV42.
	CRYP1_CRYP_IV0RR_IV42 = 0x200000
	// Position of IV41 field.
	CRYP1_CRYP_IV0RR_IV41_Pos = 0x16
	// Bit mask of IV41 field.
	CRYP1_CRYP_IV0RR_IV41_Msk = 0x400000
	// Bit IV41.
	CRYP1_CRYP_IV0RR_IV41 = 0x400000
	// Position of IV40 field.
	CRYP1_CRYP_IV0RR_IV40_Pos = 0x17
	// Bit mask of IV40 field.
	CRYP1_CRYP_IV0RR_IV40_Msk = 0x800000
	// Bit IV40.
	CRYP1_CRYP_IV0RR_IV40 = 0x800000
	// Position of IV39 field.
	CRYP1_CRYP_IV0RR_IV39_Pos = 0x18
	// Bit mask of IV39 field.
	CRYP1_CRYP_IV0RR_IV39_Msk = 0x1000000
	// Bit IV39.
	CRYP1_CRYP_IV0RR_IV39 = 0x1000000
	// Position of IV38 field.
	CRYP1_CRYP_IV0RR_IV38_Pos = 0x19
	// Bit mask of IV38 field.
	CRYP1_CRYP_IV0RR_IV38_Msk = 0x2000000
	// Bit IV38.
	CRYP1_CRYP_IV0RR_IV38 = 0x2000000
	// Position of IV37 field.
	CRYP1_CRYP_IV0RR_IV37_Pos = 0x1a
	// Bit mask of IV37 field.
	CRYP1_CRYP_IV0RR_IV37_Msk = 0x4000000
	// Bit IV37.
	CRYP1_CRYP_IV0RR_IV37 = 0x4000000
	// Position of IV36 field.
	CRYP1_CRYP_IV0RR_IV36_Pos = 0x1b
	// Bit mask of IV36 field.
	CRYP1_CRYP_IV0RR_IV36_Msk = 0x8000000
	// Bit IV36.
	CRYP1_CRYP_IV0RR_IV36 = 0x8000000
	// Position of IV35 field.
	CRYP1_CRYP_IV0RR_IV35_Pos = 0x1c
	// Bit mask of IV35 field.
	CRYP1_CRYP_IV0RR_IV35_Msk = 0x10000000
	// Bit IV35.
	CRYP1_CRYP_IV0RR_IV35 = 0x10000000
	// Position of IV34 field.
	CRYP1_CRYP_IV0RR_IV34_Pos = 0x1d
	// Bit mask of IV34 field.
	CRYP1_CRYP_IV0RR_IV34_Msk = 0x20000000
	// Bit IV34.
	CRYP1_CRYP_IV0RR_IV34 = 0x20000000
	// Position of IV33 field.
	CRYP1_CRYP_IV0RR_IV33_Pos = 0x1e
	// Bit mask of IV33 field.
	CRYP1_CRYP_IV0RR_IV33_Msk = 0x40000000
	// Bit IV33.
	CRYP1_CRYP_IV0RR_IV33 = 0x40000000
	// Position of IV32 field.
	CRYP1_CRYP_IV0RR_IV32_Pos = 0x1f
	// Bit mask of IV32 field.
	CRYP1_CRYP_IV0RR_IV32_Msk = 0x80000000
	// Bit IV32.
	CRYP1_CRYP_IV0RR_IV32 = 0x80000000

	// CRYP_IV1LR: Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
	// Position of IV95 field.
	CRYP1_CRYP_IV1LR_IV95_Pos = 0x0
	// Bit mask of IV95 field.
	CRYP1_CRYP_IV1LR_IV95_Msk = 0x1
	// Bit IV95.
	CRYP1_CRYP_IV1LR_IV95 = 0x1
	// Position of IV94 field.
	CRYP1_CRYP_IV1LR_IV94_Pos = 0x1
	// Bit mask of IV94 field.
	CRYP1_CRYP_IV1LR_IV94_Msk = 0x2
	// Bit IV94.
	CRYP1_CRYP_IV1LR_IV94 = 0x2
	// Position of IV93 field.
	CRYP1_CRYP_IV1LR_IV93_Pos = 0x2
	// Bit mask of IV93 field.
	CRYP1_CRYP_IV1LR_IV93_Msk = 0x4
	// Bit IV93.
	CRYP1_CRYP_IV1LR_IV93 = 0x4
	// Position of IV92 field.
	CRYP1_CRYP_IV1LR_IV92_Pos = 0x3
	// Bit mask of IV92 field.
	CRYP1_CRYP_IV1LR_IV92_Msk = 0x8
	// Bit IV92.
	CRYP1_CRYP_IV1LR_IV92 = 0x8
	// Position of IV91 field.
	CRYP1_CRYP_IV1LR_IV91_Pos = 0x4
	// Bit mask of IV91 field.
	CRYP1_CRYP_IV1LR_IV91_Msk = 0x10
	// Bit IV91.
	CRYP1_CRYP_IV1LR_IV91 = 0x10
	// Position of IV90 field.
	CRYP1_CRYP_IV1LR_IV90_Pos = 0x5
	// Bit mask of IV90 field.
	CRYP1_CRYP_IV1LR_IV90_Msk = 0x20
	// Bit IV90.
	CRYP1_CRYP_IV1LR_IV90 = 0x20
	// Position of IV89 field.
	CRYP1_CRYP_IV1LR_IV89_Pos = 0x6
	// Bit mask of IV89 field.
	CRYP1_CRYP_IV1LR_IV89_Msk = 0x40
	// Bit IV89.
	CRYP1_CRYP_IV1LR_IV89 = 0x40
	// Position of IV88 field.
	CRYP1_CRYP_IV1LR_IV88_Pos = 0x7
	// Bit mask of IV88 field.
	CRYP1_CRYP_IV1LR_IV88_Msk = 0x80
	// Bit IV88.
	CRYP1_CRYP_IV1LR_IV88 = 0x80
	// Position of IV87 field.
	CRYP1_CRYP_IV1LR_IV87_Pos = 0x8
	// Bit mask of IV87 field.
	CRYP1_CRYP_IV1LR_IV87_Msk = 0x100
	// Bit IV87.
	CRYP1_CRYP_IV1LR_IV87 = 0x100
	// Position of IV86 field.
	CRYP1_CRYP_IV1LR_IV86_Pos = 0x9
	// Bit mask of IV86 field.
	CRYP1_CRYP_IV1LR_IV86_Msk = 0x200
	// Bit IV86.
	CRYP1_CRYP_IV1LR_IV86 = 0x200
	// Position of IV85 field.
	CRYP1_CRYP_IV1LR_IV85_Pos = 0xa
	// Bit mask of IV85 field.
	CRYP1_CRYP_IV1LR_IV85_Msk = 0x400
	// Bit IV85.
	CRYP1_CRYP_IV1LR_IV85 = 0x400
	// Position of IV84 field.
	CRYP1_CRYP_IV1LR_IV84_Pos = 0xb
	// Bit mask of IV84 field.
	CRYP1_CRYP_IV1LR_IV84_Msk = 0x800
	// Bit IV84.
	CRYP1_CRYP_IV1LR_IV84 = 0x800
	// Position of IV83 field.
	CRYP1_CRYP_IV1LR_IV83_Pos = 0xc
	// Bit mask of IV83 field.
	CRYP1_CRYP_IV1LR_IV83_Msk = 0x1000
	// Bit IV83.
	CRYP1_CRYP_IV1LR_IV83 = 0x1000
	// Position of IV82 field.
	CRYP1_CRYP_IV1LR_IV82_Pos = 0xd
	// Bit mask of IV82 field.
	CRYP1_CRYP_IV1LR_IV82_Msk = 0x2000
	// Bit IV82.
	CRYP1_CRYP_IV1LR_IV82 = 0x2000
	// Position of IV81 field.
	CRYP1_CRYP_IV1LR_IV81_Pos = 0xe
	// Bit mask of IV81 field.
	CRYP1_CRYP_IV1LR_IV81_Msk = 0x4000
	// Bit IV81.
	CRYP1_CRYP_IV1LR_IV81 = 0x4000
	// Position of IV80 field.
	CRYP1_CRYP_IV1LR_IV80_Pos = 0xf
	// Bit mask of IV80 field.
	CRYP1_CRYP_IV1LR_IV80_Msk = 0x8000
	// Bit IV80.
	CRYP1_CRYP_IV1LR_IV80 = 0x8000
	// Position of IV79 field.
	CRYP1_CRYP_IV1LR_IV79_Pos = 0x10
	// Bit mask of IV79 field.
	CRYP1_CRYP_IV1LR_IV79_Msk = 0x10000
	// Bit IV79.
	CRYP1_CRYP_IV1LR_IV79 = 0x10000
	// Position of IV78 field.
	CRYP1_CRYP_IV1LR_IV78_Pos = 0x11
	// Bit mask of IV78 field.
	CRYP1_CRYP_IV1LR_IV78_Msk = 0x20000
	// Bit IV78.
	CRYP1_CRYP_IV1LR_IV78 = 0x20000
	// Position of IV77 field.
	CRYP1_CRYP_IV1LR_IV77_Pos = 0x12
	// Bit mask of IV77 field.
	CRYP1_CRYP_IV1LR_IV77_Msk = 0x40000
	// Bit IV77.
	CRYP1_CRYP_IV1LR_IV77 = 0x40000
	// Position of IV76 field.
	CRYP1_CRYP_IV1LR_IV76_Pos = 0x13
	// Bit mask of IV76 field.
	CRYP1_CRYP_IV1LR_IV76_Msk = 0x80000
	// Bit IV76.
	CRYP1_CRYP_IV1LR_IV76 = 0x80000
	// Position of IV75 field.
	CRYP1_CRYP_IV1LR_IV75_Pos = 0x14
	// Bit mask of IV75 field.
	CRYP1_CRYP_IV1LR_IV75_Msk = 0x100000
	// Bit IV75.
	CRYP1_CRYP_IV1LR_IV75 = 0x100000
	// Position of IV74 field.
	CRYP1_CRYP_IV1LR_IV74_Pos = 0x15
	// Bit mask of IV74 field.
	CRYP1_CRYP_IV1LR_IV74_Msk = 0x200000
	// Bit IV74.
	CRYP1_CRYP_IV1LR_IV74 = 0x200000
	// Position of IV73 field.
	CRYP1_CRYP_IV1LR_IV73_Pos = 0x16
	// Bit mask of IV73 field.
	CRYP1_CRYP_IV1LR_IV73_Msk = 0x400000
	// Bit IV73.
	CRYP1_CRYP_IV1LR_IV73 = 0x400000
	// Position of IV72 field.
	CRYP1_CRYP_IV1LR_IV72_Pos = 0x17
	// Bit mask of IV72 field.
	CRYP1_CRYP_IV1LR_IV72_Msk = 0x800000
	// Bit IV72.
	CRYP1_CRYP_IV1LR_IV72 = 0x800000
	// Position of IV71 field.
	CRYP1_CRYP_IV1LR_IV71_Pos = 0x18
	// Bit mask of IV71 field.
	CRYP1_CRYP_IV1LR_IV71_Msk = 0x1000000
	// Bit IV71.
	CRYP1_CRYP_IV1LR_IV71 = 0x1000000
	// Position of IV70 field.
	CRYP1_CRYP_IV1LR_IV70_Pos = 0x19
	// Bit mask of IV70 field.
	CRYP1_CRYP_IV1LR_IV70_Msk = 0x2000000
	// Bit IV70.
	CRYP1_CRYP_IV1LR_IV70 = 0x2000000
	// Position of IV69 field.
	CRYP1_CRYP_IV1LR_IV69_Pos = 0x1a
	// Bit mask of IV69 field.
	CRYP1_CRYP_IV1LR_IV69_Msk = 0x4000000
	// Bit IV69.
	CRYP1_CRYP_IV1LR_IV69 = 0x4000000
	// Position of IV68 field.
	CRYP1_CRYP_IV1LR_IV68_Pos = 0x1b
	// Bit mask of IV68 field.
	CRYP1_CRYP_IV1LR_IV68_Msk = 0x8000000
	// Bit IV68.
	CRYP1_CRYP_IV1LR_IV68 = 0x8000000
	// Position of IV67 field.
	CRYP1_CRYP_IV1LR_IV67_Pos = 0x1c
	// Bit mask of IV67 field.
	CRYP1_CRYP_IV1LR_IV67_Msk = 0x10000000
	// Bit IV67.
	CRYP1_CRYP_IV1LR_IV67 = 0x10000000
	// Position of IV66 field.
	CRYP1_CRYP_IV1LR_IV66_Pos = 0x1d
	// Bit mask of IV66 field.
	CRYP1_CRYP_IV1LR_IV66_Msk = 0x20000000
	// Bit IV66.
	CRYP1_CRYP_IV1LR_IV66 = 0x20000000
	// Position of IV65 field.
	CRYP1_CRYP_IV1LR_IV65_Pos = 0x1e
	// Bit mask of IV65 field.
	CRYP1_CRYP_IV1LR_IV65_Msk = 0x40000000
	// Bit IV65.
	CRYP1_CRYP_IV1LR_IV65 = 0x40000000
	// Position of IV64 field.
	CRYP1_CRYP_IV1LR_IV64_Pos = 0x1f
	// Bit mask of IV64 field.
	CRYP1_CRYP_IV1LR_IV64_Msk = 0x80000000
	// Bit IV64.
	CRYP1_CRYP_IV1LR_IV64 = 0x80000000

	// CRYP_IV1RR: Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
	// Position of IV127 field.
	CRYP1_CRYP_IV1RR_IV127_Pos = 0x0
	// Bit mask of IV127 field.
	CRYP1_CRYP_IV1RR_IV127_Msk = 0x1
	// Bit IV127.
	CRYP1_CRYP_IV1RR_IV127 = 0x1
	// Position of IV126 field.
	CRYP1_CRYP_IV1RR_IV126_Pos = 0x1
	// Bit mask of IV126 field.
	CRYP1_CRYP_IV1RR_IV126_Msk = 0x2
	// Bit IV126.
	CRYP1_CRYP_IV1RR_IV126 = 0x2
	// Position of IV125 field.
	CRYP1_CRYP_IV1RR_IV125_Pos = 0x2
	// Bit mask of IV125 field.
	CRYP1_CRYP_IV1RR_IV125_Msk = 0x4
	// Bit IV125.
	CRYP1_CRYP_IV1RR_IV125 = 0x4
	// Position of IV124 field.
	CRYP1_CRYP_IV1RR_IV124_Pos = 0x3
	// Bit mask of IV124 field.
	CRYP1_CRYP_IV1RR_IV124_Msk = 0x8
	// Bit IV124.
	CRYP1_CRYP_IV1RR_IV124 = 0x8
	// Position of IV123 field.
	CRYP1_CRYP_IV1RR_IV123_Pos = 0x4
	// Bit mask of IV123 field.
	CRYP1_CRYP_IV1RR_IV123_Msk = 0x10
	// Bit IV123.
	CRYP1_CRYP_IV1RR_IV123 = 0x10
	// Position of IV122 field.
	CRYP1_CRYP_IV1RR_IV122_Pos = 0x5
	// Bit mask of IV122 field.
	CRYP1_CRYP_IV1RR_IV122_Msk = 0x20
	// Bit IV122.
	CRYP1_CRYP_IV1RR_IV122 = 0x20
	// Position of IV121 field.
	CRYP1_CRYP_IV1RR_IV121_Pos = 0x6
	// Bit mask of IV121 field.
	CRYP1_CRYP_IV1RR_IV121_Msk = 0x40
	// Bit IV121.
	CRYP1_CRYP_IV1RR_IV121 = 0x40
	// Position of IV120 field.
	CRYP1_CRYP_IV1RR_IV120_Pos = 0x7
	// Bit mask of IV120 field.
	CRYP1_CRYP_IV1RR_IV120_Msk = 0x80
	// Bit IV120.
	CRYP1_CRYP_IV1RR_IV120 = 0x80
	// Position of IV119 field.
	CRYP1_CRYP_IV1RR_IV119_Pos = 0x8
	// Bit mask of IV119 field.
	CRYP1_CRYP_IV1RR_IV119_Msk = 0x100
	// Bit IV119.
	CRYP1_CRYP_IV1RR_IV119 = 0x100
	// Position of IV118 field.
	CRYP1_CRYP_IV1RR_IV118_Pos = 0x9
	// Bit mask of IV118 field.
	CRYP1_CRYP_IV1RR_IV118_Msk = 0x200
	// Bit IV118.
	CRYP1_CRYP_IV1RR_IV118 = 0x200
	// Position of IV117 field.
	CRYP1_CRYP_IV1RR_IV117_Pos = 0xa
	// Bit mask of IV117 field.
	CRYP1_CRYP_IV1RR_IV117_Msk = 0x400
	// Bit IV117.
	CRYP1_CRYP_IV1RR_IV117 = 0x400
	// Position of IV116 field.
	CRYP1_CRYP_IV1RR_IV116_Pos = 0xb
	// Bit mask of IV116 field.
	CRYP1_CRYP_IV1RR_IV116_Msk = 0x800
	// Bit IV116.
	CRYP1_CRYP_IV1RR_IV116 = 0x800
	// Position of IV115 field.
	CRYP1_CRYP_IV1RR_IV115_Pos = 0xc
	// Bit mask of IV115 field.
	CRYP1_CRYP_IV1RR_IV115_Msk = 0x1000
	// Bit IV115.
	CRYP1_CRYP_IV1RR_IV115 = 0x1000
	// Position of IV114 field.
	CRYP1_CRYP_IV1RR_IV114_Pos = 0xd
	// Bit mask of IV114 field.
	CRYP1_CRYP_IV1RR_IV114_Msk = 0x2000
	// Bit IV114.
	CRYP1_CRYP_IV1RR_IV114 = 0x2000
	// Position of IV113 field.
	CRYP1_CRYP_IV1RR_IV113_Pos = 0xe
	// Bit mask of IV113 field.
	CRYP1_CRYP_IV1RR_IV113_Msk = 0x4000
	// Bit IV113.
	CRYP1_CRYP_IV1RR_IV113 = 0x4000
	// Position of IV112 field.
	CRYP1_CRYP_IV1RR_IV112_Pos = 0xf
	// Bit mask of IV112 field.
	CRYP1_CRYP_IV1RR_IV112_Msk = 0x8000
	// Bit IV112.
	CRYP1_CRYP_IV1RR_IV112 = 0x8000
	// Position of IV111 field.
	CRYP1_CRYP_IV1RR_IV111_Pos = 0x10
	// Bit mask of IV111 field.
	CRYP1_CRYP_IV1RR_IV111_Msk = 0x10000
	// Bit IV111.
	CRYP1_CRYP_IV1RR_IV111 = 0x10000
	// Position of IV110 field.
	CRYP1_CRYP_IV1RR_IV110_Pos = 0x11
	// Bit mask of IV110 field.
	CRYP1_CRYP_IV1RR_IV110_Msk = 0x20000
	// Bit IV110.
	CRYP1_CRYP_IV1RR_IV110 = 0x20000
	// Position of IV109 field.
	CRYP1_CRYP_IV1RR_IV109_Pos = 0x12
	// Bit mask of IV109 field.
	CRYP1_CRYP_IV1RR_IV109_Msk = 0x40000
	// Bit IV109.
	CRYP1_CRYP_IV1RR_IV109 = 0x40000
	// Position of IV108 field.
	CRYP1_CRYP_IV1RR_IV108_Pos = 0x13
	// Bit mask of IV108 field.
	CRYP1_CRYP_IV1RR_IV108_Msk = 0x80000
	// Bit IV108.
	CRYP1_CRYP_IV1RR_IV108 = 0x80000
	// Position of IV107 field.
	CRYP1_CRYP_IV1RR_IV107_Pos = 0x14
	// Bit mask of IV107 field.
	CRYP1_CRYP_IV1RR_IV107_Msk = 0x100000
	// Bit IV107.
	CRYP1_CRYP_IV1RR_IV107 = 0x100000
	// Position of IV106 field.
	CRYP1_CRYP_IV1RR_IV106_Pos = 0x15
	// Bit mask of IV106 field.
	CRYP1_CRYP_IV1RR_IV106_Msk = 0x200000
	// Bit IV106.
	CRYP1_CRYP_IV1RR_IV106 = 0x200000
	// Position of IV105 field.
	CRYP1_CRYP_IV1RR_IV105_Pos = 0x16
	// Bit mask of IV105 field.
	CRYP1_CRYP_IV1RR_IV105_Msk = 0x400000
	// Bit IV105.
	CRYP1_CRYP_IV1RR_IV105 = 0x400000
	// Position of IV104 field.
	CRYP1_CRYP_IV1RR_IV104_Pos = 0x17
	// Bit mask of IV104 field.
	CRYP1_CRYP_IV1RR_IV104_Msk = 0x800000
	// Bit IV104.
	CRYP1_CRYP_IV1RR_IV104 = 0x800000
	// Position of IV103 field.
	CRYP1_CRYP_IV1RR_IV103_Pos = 0x18
	// Bit mask of IV103 field.
	CRYP1_CRYP_IV1RR_IV103_Msk = 0x1000000
	// Bit IV103.
	CRYP1_CRYP_IV1RR_IV103 = 0x1000000
	// Position of IV102 field.
	CRYP1_CRYP_IV1RR_IV102_Pos = 0x19
	// Bit mask of IV102 field.
	CRYP1_CRYP_IV1RR_IV102_Msk = 0x2000000
	// Bit IV102.
	CRYP1_CRYP_IV1RR_IV102 = 0x2000000
	// Position of IV101 field.
	CRYP1_CRYP_IV1RR_IV101_Pos = 0x1a
	// Bit mask of IV101 field.
	CRYP1_CRYP_IV1RR_IV101_Msk = 0x4000000
	// Bit IV101.
	CRYP1_CRYP_IV1RR_IV101 = 0x4000000
	// Position of IV100 field.
	CRYP1_CRYP_IV1RR_IV100_Pos = 0x1b
	// Bit mask of IV100 field.
	CRYP1_CRYP_IV1RR_IV100_Msk = 0x8000000
	// Bit IV100.
	CRYP1_CRYP_IV1RR_IV100 = 0x8000000
	// Position of IV99 field.
	CRYP1_CRYP_IV1RR_IV99_Pos = 0x1c
	// Bit mask of IV99 field.
	CRYP1_CRYP_IV1RR_IV99_Msk = 0x10000000
	// Bit IV99.
	CRYP1_CRYP_IV1RR_IV99 = 0x10000000
	// Position of IV98 field.
	CRYP1_CRYP_IV1RR_IV98_Pos = 0x1d
	// Bit mask of IV98 field.
	CRYP1_CRYP_IV1RR_IV98_Msk = 0x20000000
	// Bit IV98.
	CRYP1_CRYP_IV1RR_IV98 = 0x20000000
	// Position of IV97 field.
	CRYP1_CRYP_IV1RR_IV97_Pos = 0x1e
	// Bit mask of IV97 field.
	CRYP1_CRYP_IV1RR_IV97_Msk = 0x40000000
	// Bit IV97.
	CRYP1_CRYP_IV1RR_IV97 = 0x40000000
	// Position of IV96 field.
	CRYP1_CRYP_IV1RR_IV96_Pos = 0x1f
	// Bit mask of IV96 field.
	CRYP1_CRYP_IV1RR_IV96_Msk = 0x80000000
	// Bit IV96.
	CRYP1_CRYP_IV1RR_IV96 = 0x80000000

	// CRYP_CSGCMCCM0R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM0 field.
	CRYP1_CRYP_CSGCMCCM0R_CSGCMCCM0_Pos = 0x0
	// Bit mask of CSGCMCCM0 field.
	CRYP1_CRYP_CSGCMCCM0R_CSGCMCCM0_Msk = 0xffffffff

	// CRYP_CSGCMCCM1R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM1 field.
	CRYP1_CRYP_CSGCMCCM1R_CSGCMCCM1_Pos = 0x0
	// Bit mask of CSGCMCCM1 field.
	CRYP1_CRYP_CSGCMCCM1R_CSGCMCCM1_Msk = 0xffffffff

	// CRYP_CSGCMCCM2R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM2 field.
	CRYP1_CRYP_CSGCMCCM2R_CSGCMCCM2_Pos = 0x0
	// Bit mask of CSGCMCCM2 field.
	CRYP1_CRYP_CSGCMCCM2R_CSGCMCCM2_Msk = 0xffffffff

	// CRYP_CSGCMCCM3R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM3 field.
	CRYP1_CRYP_CSGCMCCM3R_CSGCMCCM3_Pos = 0x0
	// Bit mask of CSGCMCCM3 field.
	CRYP1_CRYP_CSGCMCCM3R_CSGCMCCM3_Msk = 0xffffffff

	// CRYP_CSGCMCCM4R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM4 field.
	CRYP1_CRYP_CSGCMCCM4R_CSGCMCCM4_Pos = 0x0
	// Bit mask of CSGCMCCM4 field.
	CRYP1_CRYP_CSGCMCCM4R_CSGCMCCM4_Msk = 0xffffffff

	// CRYP_CSGCMCCM5R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM5 field.
	CRYP1_CRYP_CSGCMCCM5R_CSGCMCCM5_Pos = 0x0
	// Bit mask of CSGCMCCM5 field.
	CRYP1_CRYP_CSGCMCCM5R_CSGCMCCM5_Msk = 0xffffffff

	// CRYP_CSGCMCCM6R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM6 field.
	CRYP1_CRYP_CSGCMCCM6R_CSGCMCCM6_Pos = 0x0
	// Bit mask of CSGCMCCM6 field.
	CRYP1_CRYP_CSGCMCCM6R_CSGCMCCM6_Msk = 0xffffffff

	// CRYP_CSGCMCCM7R: These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
	// Position of CSGCMCCM7 field.
	CRYP1_CRYP_CSGCMCCM7R_CSGCMCCM7_Pos = 0x0
	// Bit mask of CSGCMCCM7 field.
	CRYP1_CRYP_CSGCMCCM7R_CSGCMCCM7_Msk = 0xffffffff

	// CRYP_CSGCM0R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM0 field.
	CRYP1_CRYP_CSGCM0R_CSGCM0_Pos = 0x0
	// Bit mask of CSGCM0 field.
	CRYP1_CRYP_CSGCM0R_CSGCM0_Msk = 0xffffffff

	// CRYP_CSGCM1R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM1 field.
	CRYP1_CRYP_CSGCM1R_CSGCM1_Pos = 0x0
	// Bit mask of CSGCM1 field.
	CRYP1_CRYP_CSGCM1R_CSGCM1_Msk = 0xffffffff

	// CRYP_CSGCM2R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM2 field.
	CRYP1_CRYP_CSGCM2R_CSGCM2_Pos = 0x0
	// Bit mask of CSGCM2 field.
	CRYP1_CRYP_CSGCM2R_CSGCM2_Msk = 0xffffffff

	// CRYP_CSGCM3R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM3 field.
	CRYP1_CRYP_CSGCM3R_CSGCM3_Pos = 0x0
	// Bit mask of CSGCM3 field.
	CRYP1_CRYP_CSGCM3R_CSGCM3_Msk = 0xffffffff

	// CRYP_CSGCM4R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM4 field.
	CRYP1_CRYP_CSGCM4R_CSGCM4_Pos = 0x0
	// Bit mask of CSGCM4 field.
	CRYP1_CRYP_CSGCM4R_CSGCM4_Msk = 0xffffffff

	// CRYP_CSGCM5R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM5 field.
	CRYP1_CRYP_CSGCM5R_CSGCM5_Pos = 0x0
	// Bit mask of CSGCM5 field.
	CRYP1_CRYP_CSGCM5R_CSGCM5_Msk = 0xffffffff

	// CRYP_CSGCM6R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM6 field.
	CRYP1_CRYP_CSGCM6R_CSGCM6_Pos = 0x0
	// Bit mask of CSGCM6 field.
	CRYP1_CRYP_CSGCM6R_CSGCM6_Msk = 0xffffffff

	// CRYP_CSGCM7R: Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
	// Position of CSGCM7 field.
	CRYP1_CRYP_CSGCM7R_CSGCM7_Pos = 0x0
	// Bit mask of CSGCM7 field.
	CRYP1_CRYP_CSGCM7R_CSGCM7_Msk = 0xffffffff

	// CRYP_HWCFGR: CRYP hardware configuration register
	// Position of CFG1 field.
	CRYP1_CRYP_HWCFGR_CFG1_Pos = 0x0
	// Bit mask of CFG1 field.
	CRYP1_CRYP_HWCFGR_CFG1_Msk = 0xf
	// Position of CFG2 field.
	CRYP1_CRYP_HWCFGR_CFG2_Pos = 0x4
	// Bit mask of CFG2 field.
	CRYP1_CRYP_HWCFGR_CFG2_Msk = 0xf0
	// Position of CFG3 field.
	CRYP1_CRYP_HWCFGR_CFG3_Pos = 0x8
	// Bit mask of CFG3 field.
	CRYP1_CRYP_HWCFGR_CFG3_Msk = 0xf00
	// Position of CFG4 field.
	CRYP1_CRYP_HWCFGR_CFG4_Pos = 0xc
	// Bit mask of CFG4 field.
	CRYP1_CRYP_HWCFGR_CFG4_Msk = 0xf000

	// CRYP_VERR: CRYP HW Version Register
	// Position of VER field.
	CRYP1_CRYP_VERR_VER_Pos = 0x0
	// Bit mask of VER field.
	CRYP1_CRYP_VERR_VER_Msk = 0xff

	// CRYP_IPIDR: CRYP Identification
	// Position of ID field.
	CRYP1_CRYP_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	CRYP1_CRYP_IPIDR_ID_Msk = 0xffffffff

	// CRYP_MID: CRYP HW Magic ID
	// Position of MID field.
	CRYP1_CRYP_MID_MID_Pos = 0x0
	// Bit mask of MID field.
	CRYP1_CRYP_MID_MID_Msk = 0xffffffff
)

// Bitfields for DAC1: DAC1
const (
	// DAC_CR: DAC control register
	// Position of EN1 field.
	DAC1_DAC_CR_EN1_Pos = 0x0
	// Bit mask of EN1 field.
	DAC1_DAC_CR_EN1_Msk = 0x1
	// Bit EN1.
	DAC1_DAC_CR_EN1 = 0x1
	// Position of TEN1 field.
	DAC1_DAC_CR_TEN1_Pos = 0x1
	// Bit mask of TEN1 field.
	DAC1_DAC_CR_TEN1_Msk = 0x2
	// Bit TEN1.
	DAC1_DAC_CR_TEN1 = 0x2
	// Position of TSEL10 field.
	DAC1_DAC_CR_TSEL10_Pos = 0x2
	// Bit mask of TSEL10 field.
	DAC1_DAC_CR_TSEL10_Msk = 0x4
	// Bit TSEL10.
	DAC1_DAC_CR_TSEL10 = 0x4
	// Position of TSEL11 field.
	DAC1_DAC_CR_TSEL11_Pos = 0x3
	// Bit mask of TSEL11 field.
	DAC1_DAC_CR_TSEL11_Msk = 0x8
	// Bit TSEL11.
	DAC1_DAC_CR_TSEL11 = 0x8
	// Position of TSEL12 field.
	DAC1_DAC_CR_TSEL12_Pos = 0x4
	// Bit mask of TSEL12 field.
	DAC1_DAC_CR_TSEL12_Msk = 0x10
	// Bit TSEL12.
	DAC1_DAC_CR_TSEL12 = 0x10
	// Position of TSEL13 field.
	DAC1_DAC_CR_TSEL13_Pos = 0x5
	// Bit mask of TSEL13 field.
	DAC1_DAC_CR_TSEL13_Msk = 0x20
	// Bit TSEL13.
	DAC1_DAC_CR_TSEL13 = 0x20
	// Position of WAVE1 field.
	DAC1_DAC_CR_WAVE1_Pos = 0x6
	// Bit mask of WAVE1 field.
	DAC1_DAC_CR_WAVE1_Msk = 0xc0
	// Position of MAMP1 field.
	DAC1_DAC_CR_MAMP1_Pos = 0x8
	// Bit mask of MAMP1 field.
	DAC1_DAC_CR_MAMP1_Msk = 0xf00
	// Position of DMAEN1 field.
	DAC1_DAC_CR_DMAEN1_Pos = 0xc
	// Bit mask of DMAEN1 field.
	DAC1_DAC_CR_DMAEN1_Msk = 0x1000
	// Bit DMAEN1.
	DAC1_DAC_CR_DMAEN1 = 0x1000
	// Position of DMAUDRIE1 field.
	DAC1_DAC_CR_DMAUDRIE1_Pos = 0xd
	// Bit mask of DMAUDRIE1 field.
	DAC1_DAC_CR_DMAUDRIE1_Msk = 0x2000
	// Bit DMAUDRIE1.
	DAC1_DAC_CR_DMAUDRIE1 = 0x2000
	// Position of CEN1 field.
	DAC1_DAC_CR_CEN1_Pos = 0xe
	// Bit mask of CEN1 field.
	DAC1_DAC_CR_CEN1_Msk = 0x4000
	// Bit CEN1.
	DAC1_DAC_CR_CEN1 = 0x4000
	// Position of HFSEL field.
	DAC1_DAC_CR_HFSEL_Pos = 0xf
	// Bit mask of HFSEL field.
	DAC1_DAC_CR_HFSEL_Msk = 0x8000
	// Bit HFSEL.
	DAC1_DAC_CR_HFSEL = 0x8000
	// Position of EN2 field.
	DAC1_DAC_CR_EN2_Pos = 0x10
	// Bit mask of EN2 field.
	DAC1_DAC_CR_EN2_Msk = 0x10000
	// Bit EN2.
	DAC1_DAC_CR_EN2 = 0x10000
	// Position of TEN2 field.
	DAC1_DAC_CR_TEN2_Pos = 0x11
	// Bit mask of TEN2 field.
	DAC1_DAC_CR_TEN2_Msk = 0x20000
	// Bit TEN2.
	DAC1_DAC_CR_TEN2 = 0x20000
	// Position of TSEL20 field.
	DAC1_DAC_CR_TSEL20_Pos = 0x12
	// Bit mask of TSEL20 field.
	DAC1_DAC_CR_TSEL20_Msk = 0x40000
	// Bit TSEL20.
	DAC1_DAC_CR_TSEL20 = 0x40000
	// Position of TSEL21 field.
	DAC1_DAC_CR_TSEL21_Pos = 0x13
	// Bit mask of TSEL21 field.
	DAC1_DAC_CR_TSEL21_Msk = 0x80000
	// Bit TSEL21.
	DAC1_DAC_CR_TSEL21 = 0x80000
	// Position of TSEL22 field.
	DAC1_DAC_CR_TSEL22_Pos = 0x14
	// Bit mask of TSEL22 field.
	DAC1_DAC_CR_TSEL22_Msk = 0x100000
	// Bit TSEL22.
	DAC1_DAC_CR_TSEL22 = 0x100000
	// Position of TSEL23 field.
	DAC1_DAC_CR_TSEL23_Pos = 0x15
	// Bit mask of TSEL23 field.
	DAC1_DAC_CR_TSEL23_Msk = 0x200000
	// Bit TSEL23.
	DAC1_DAC_CR_TSEL23 = 0x200000
	// Position of WAVE2 field.
	DAC1_DAC_CR_WAVE2_Pos = 0x16
	// Bit mask of WAVE2 field.
	DAC1_DAC_CR_WAVE2_Msk = 0xc00000
	// Position of MAMP2 field.
	DAC1_DAC_CR_MAMP2_Pos = 0x18
	// Bit mask of MAMP2 field.
	DAC1_DAC_CR_MAMP2_Msk = 0xf000000
	// Position of DMAEN2 field.
	DAC1_DAC_CR_DMAEN2_Pos = 0x1c
	// Bit mask of DMAEN2 field.
	DAC1_DAC_CR_DMAEN2_Msk = 0x10000000
	// Bit DMAEN2.
	DAC1_DAC_CR_DMAEN2 = 0x10000000
	// Position of DMAUDRIE2 field.
	DAC1_DAC_CR_DMAUDRIE2_Pos = 0x1d
	// Bit mask of DMAUDRIE2 field.
	DAC1_DAC_CR_DMAUDRIE2_Msk = 0x20000000
	// Bit DMAUDRIE2.
	DAC1_DAC_CR_DMAUDRIE2 = 0x20000000
	// Position of CEN2 field.
	DAC1_DAC_CR_CEN2_Pos = 0x1e
	// Bit mask of CEN2 field.
	DAC1_DAC_CR_CEN2_Msk = 0x40000000
	// Bit CEN2.
	DAC1_DAC_CR_CEN2 = 0x40000000

	// DAC_SWTRGR: DAC software trigger register
	// Position of SWTRIG1 field.
	DAC1_DAC_SWTRGR_SWTRIG1_Pos = 0x0
	// Bit mask of SWTRIG1 field.
	DAC1_DAC_SWTRGR_SWTRIG1_Msk = 0x1
	// Bit SWTRIG1.
	DAC1_DAC_SWTRGR_SWTRIG1 = 0x1
	// Position of SWTRIG2 field.
	DAC1_DAC_SWTRGR_SWTRIG2_Pos = 0x1
	// Bit mask of SWTRIG2 field.
	DAC1_DAC_SWTRGR_SWTRIG2_Msk = 0x2
	// Bit SWTRIG2.
	DAC1_DAC_SWTRGR_SWTRIG2 = 0x2

	// DAC_DHR12R1: DAC channel1 12-bit right-aligned data holding register
	// Position of DACC1DHR field.
	DAC1_DAC_DHR12R1_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC1_DAC_DHR12R1_DACC1DHR_Msk = 0xfff

	// DAC_DHR12L1: DAC channel1 12-bit left aligned data holding register
	// Position of DACC1DHR field.
	DAC1_DAC_DHR12L1_DACC1DHR_Pos = 0x4
	// Bit mask of DACC1DHR field.
	DAC1_DAC_DHR12L1_DACC1DHR_Msk = 0xfff0

	// DAC_DHR8R1: DAC channel1 8-bit right aligned data holding register
	// Position of DACC1DHR field.
	DAC1_DAC_DHR8R1_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC1_DAC_DHR8R1_DACC1DHR_Msk = 0xff

	// DAC_DHR12R2: This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
	// Position of DACC2DHR field.
	DAC1_DAC_DHR12R2_DACC2DHR_Pos = 0x0
	// Bit mask of DACC2DHR field.
	DAC1_DAC_DHR12R2_DACC2DHR_Msk = 0xfff

	// DAC_DHR12L2: This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
	// Position of DACC2DHR field.
	DAC1_DAC_DHR12L2_DACC2DHR_Pos = 0x4
	// Bit mask of DACC2DHR field.
	DAC1_DAC_DHR12L2_DACC2DHR_Msk = 0xfff0

	// DAC_DHR8R2: This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
	// Position of DACC2DHR field.
	DAC1_DAC_DHR8R2_DACC2DHR_Pos = 0x0
	// Bit mask of DACC2DHR field.
	DAC1_DAC_DHR8R2_DACC2DHR_Msk = 0xff

	// DAC_DHR12RD: Dual DAC 12-bit right-aligned data holding register
	// Position of DACC1DHR field.
	DAC1_DAC_DHR12RD_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC1_DAC_DHR12RD_DACC1DHR_Msk = 0xfff
	// Position of DACC2DHR field.
	DAC1_DAC_DHR12RD_DACC2DHR_Pos = 0x10
	// Bit mask of DACC2DHR field.
	DAC1_DAC_DHR12RD_DACC2DHR_Msk = 0xfff0000

	// DAC_DHR12LD: Dual DAC 12-bit left aligned data holding register
	// Position of DACC1DHR field.
	DAC1_DAC_DHR12LD_DACC1DHR_Pos = 0x4
	// Bit mask of DACC1DHR field.
	DAC1_DAC_DHR12LD_DACC1DHR_Msk = 0xfff0
	// Position of DACC2DHR field.
	DAC1_DAC_DHR12LD_DACC2DHR_Pos = 0x14
	// Bit mask of DACC2DHR field.
	DAC1_DAC_DHR12LD_DACC2DHR_Msk = 0xfff00000

	// DAC_DHR8RD: Dual DAC 8-bit right aligned data holding register
	// Position of DACC1DHR field.
	DAC1_DAC_DHR8RD_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC1_DAC_DHR8RD_DACC1DHR_Msk = 0xff
	// Position of DACC2DHR field.
	DAC1_DAC_DHR8RD_DACC2DHR_Pos = 0x8
	// Bit mask of DACC2DHR field.
	DAC1_DAC_DHR8RD_DACC2DHR_Msk = 0xff00

	// DAC_DOR1: DAC channel1 data output register
	// Position of DACC1DOR field.
	DAC1_DAC_DOR1_DACC1DOR_Pos = 0x0
	// Bit mask of DACC1DOR field.
	DAC1_DAC_DOR1_DACC1DOR_Msk = 0xfff

	// DAC_DOR2: This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
	// Position of DACC2DOR field.
	DAC1_DAC_DOR2_DACC2DOR_Pos = 0x0
	// Bit mask of DACC2DOR field.
	DAC1_DAC_DOR2_DACC2DOR_Msk = 0xfff

	// DAC_SR: DAC status register
	// Position of DMAUDR1 field.
	DAC1_DAC_SR_DMAUDR1_Pos = 0xd
	// Bit mask of DMAUDR1 field.
	DAC1_DAC_SR_DMAUDR1_Msk = 0x2000
	// Bit DMAUDR1.
	DAC1_DAC_SR_DMAUDR1 = 0x2000
	// Position of CAL_FLAG1 field.
	DAC1_DAC_SR_CAL_FLAG1_Pos = 0xe
	// Bit mask of CAL_FLAG1 field.
	DAC1_DAC_SR_CAL_FLAG1_Msk = 0x4000
	// Bit CAL_FLAG1.
	DAC1_DAC_SR_CAL_FLAG1 = 0x4000
	// Position of BWST1 field.
	DAC1_DAC_SR_BWST1_Pos = 0xf
	// Bit mask of BWST1 field.
	DAC1_DAC_SR_BWST1_Msk = 0x8000
	// Bit BWST1.
	DAC1_DAC_SR_BWST1 = 0x8000
	// Position of DMAUDR2 field.
	DAC1_DAC_SR_DMAUDR2_Pos = 0x1d
	// Bit mask of DMAUDR2 field.
	DAC1_DAC_SR_DMAUDR2_Msk = 0x20000000
	// Bit DMAUDR2.
	DAC1_DAC_SR_DMAUDR2 = 0x20000000
	// Position of CAL_FLAG2 field.
	DAC1_DAC_SR_CAL_FLAG2_Pos = 0x1e
	// Bit mask of CAL_FLAG2 field.
	DAC1_DAC_SR_CAL_FLAG2_Msk = 0x40000000
	// Bit CAL_FLAG2.
	DAC1_DAC_SR_CAL_FLAG2 = 0x40000000
	// Position of BWST2 field.
	DAC1_DAC_SR_BWST2_Pos = 0x1f
	// Bit mask of BWST2 field.
	DAC1_DAC_SR_BWST2_Msk = 0x80000000
	// Bit BWST2.
	DAC1_DAC_SR_BWST2 = 0x80000000

	// DAC_CCR: DAC calibration control register
	// Position of OTRIM1 field.
	DAC1_DAC_CCR_OTRIM1_Pos = 0x0
	// Bit mask of OTRIM1 field.
	DAC1_DAC_CCR_OTRIM1_Msk = 0x1f
	// Position of OTRIM2 field.
	DAC1_DAC_CCR_OTRIM2_Pos = 0x10
	// Bit mask of OTRIM2 field.
	DAC1_DAC_CCR_OTRIM2_Msk = 0x1f0000

	// DAC_MCR: DAC mode control register
	// Position of MODE1 field.
	DAC1_DAC_MCR_MODE1_Pos = 0x0
	// Bit mask of MODE1 field.
	DAC1_DAC_MCR_MODE1_Msk = 0x7
	// Position of MODE2 field.
	DAC1_DAC_MCR_MODE2_Pos = 0x10
	// Bit mask of MODE2 field.
	DAC1_DAC_MCR_MODE2_Msk = 0x70000

	// DAC_SHSR1: DAC channel 1 sample and hold sample time register
	// Position of TSAMPLE1 field.
	DAC1_DAC_SHSR1_TSAMPLE1_Pos = 0x0
	// Bit mask of TSAMPLE1 field.
	DAC1_DAC_SHSR1_TSAMPLE1_Msk = 0x3ff

	// DAC_SHSR2: This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
	// Position of TSAMPLE2 field.
	DAC1_DAC_SHSR2_TSAMPLE2_Pos = 0x0
	// Bit mask of TSAMPLE2 field.
	DAC1_DAC_SHSR2_TSAMPLE2_Msk = 0x3ff

	// DAC_SHHR: DAC sample and hold time register
	// Position of THOLD1 field.
	DAC1_DAC_SHHR_THOLD1_Pos = 0x0
	// Bit mask of THOLD1 field.
	DAC1_DAC_SHHR_THOLD1_Msk = 0x3ff
	// Position of THOLD2 field.
	DAC1_DAC_SHHR_THOLD2_Pos = 0x10
	// Bit mask of THOLD2 field.
	DAC1_DAC_SHHR_THOLD2_Msk = 0x3ff0000

	// DAC_SHRR: DAC sample and hold refresh time register
	// Position of TREFRESH1 field.
	DAC1_DAC_SHRR_TREFRESH1_Pos = 0x0
	// Bit mask of TREFRESH1 field.
	DAC1_DAC_SHRR_TREFRESH1_Msk = 0xff
	// Position of TREFRESH2 field.
	DAC1_DAC_SHRR_TREFRESH2_Pos = 0x10
	// Bit mask of TREFRESH2 field.
	DAC1_DAC_SHRR_TREFRESH2_Msk = 0xff0000

	// DAC_HWCFGR0: DAC IP hardware configuration register
	// Position of DUAL field.
	DAC1_DAC_HWCFGR0_DUAL_Pos = 0x0
	// Bit mask of DUAL field.
	DAC1_DAC_HWCFGR0_DUAL_Msk = 0xf
	// Position of LFSR field.
	DAC1_DAC_HWCFGR0_LFSR_Pos = 0x4
	// Bit mask of LFSR field.
	DAC1_DAC_HWCFGR0_LFSR_Msk = 0xf0
	// Position of TRIANGLE field.
	DAC1_DAC_HWCFGR0_TRIANGLE_Pos = 0x8
	// Bit mask of TRIANGLE field.
	DAC1_DAC_HWCFGR0_TRIANGLE_Msk = 0xf00
	// Position of SAMPLE field.
	DAC1_DAC_HWCFGR0_SAMPLE_Pos = 0xc
	// Bit mask of SAMPLE field.
	DAC1_DAC_HWCFGR0_SAMPLE_Msk = 0xf000
	// Position of OR_CFG field.
	DAC1_DAC_HWCFGR0_OR_CFG_Pos = 0x10
	// Bit mask of OR_CFG field.
	DAC1_DAC_HWCFGR0_OR_CFG_Msk = 0xff0000

	// DAC_VERR: No
	// Position of MINREV field.
	DAC1_DAC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DAC1_DAC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DAC1_DAC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DAC1_DAC_VERR_MAJREV_Msk = 0xf0

	// DAC_IPIDR: No
	// Position of ID field.
	DAC1_DAC_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	DAC1_DAC_IPIDR_ID_Msk = 0xffffffff

	// DAC_SIDR: No
	// Position of SID field.
	DAC1_DAC_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	DAC1_DAC_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for DCMI: DCMI
const (
	// DCMI_CR: DCMI control register
	// Position of CAPTURE field.
	DCMI_DCMI_CR_CAPTURE_Pos = 0x0
	// Bit mask of CAPTURE field.
	DCMI_DCMI_CR_CAPTURE_Msk = 0x1
	// Bit CAPTURE.
	DCMI_DCMI_CR_CAPTURE = 0x1
	// Position of CM field.
	DCMI_DCMI_CR_CM_Pos = 0x1
	// Bit mask of CM field.
	DCMI_DCMI_CR_CM_Msk = 0x2
	// Bit CM.
	DCMI_DCMI_CR_CM = 0x2
	// Position of CROP field.
	DCMI_DCMI_CR_CROP_Pos = 0x2
	// Bit mask of CROP field.
	DCMI_DCMI_CR_CROP_Msk = 0x4
	// Bit CROP.
	DCMI_DCMI_CR_CROP = 0x4
	// Position of JPEG field.
	DCMI_DCMI_CR_JPEG_Pos = 0x3
	// Bit mask of JPEG field.
	DCMI_DCMI_CR_JPEG_Msk = 0x8
	// Bit JPEG.
	DCMI_DCMI_CR_JPEG = 0x8
	// Position of ESS field.
	DCMI_DCMI_CR_ESS_Pos = 0x4
	// Bit mask of ESS field.
	DCMI_DCMI_CR_ESS_Msk = 0x10
	// Bit ESS.
	DCMI_DCMI_CR_ESS = 0x10
	// Position of PCKPOL field.
	DCMI_DCMI_CR_PCKPOL_Pos = 0x5
	// Bit mask of PCKPOL field.
	DCMI_DCMI_CR_PCKPOL_Msk = 0x20
	// Bit PCKPOL.
	DCMI_DCMI_CR_PCKPOL = 0x20
	// Position of HSPOL field.
	DCMI_DCMI_CR_HSPOL_Pos = 0x6
	// Bit mask of HSPOL field.
	DCMI_DCMI_CR_HSPOL_Msk = 0x40
	// Bit HSPOL.
	DCMI_DCMI_CR_HSPOL = 0x40
	// Position of VSPOL field.
	DCMI_DCMI_CR_VSPOL_Pos = 0x7
	// Bit mask of VSPOL field.
	DCMI_DCMI_CR_VSPOL_Msk = 0x80
	// Bit VSPOL.
	DCMI_DCMI_CR_VSPOL = 0x80
	// Position of FCRC field.
	DCMI_DCMI_CR_FCRC_Pos = 0x8
	// Bit mask of FCRC field.
	DCMI_DCMI_CR_FCRC_Msk = 0x300
	// Position of EDM field.
	DCMI_DCMI_CR_EDM_Pos = 0xa
	// Bit mask of EDM field.
	DCMI_DCMI_CR_EDM_Msk = 0xc00
	// Position of ENABLE field.
	DCMI_DCMI_CR_ENABLE_Pos = 0xe
	// Bit mask of ENABLE field.
	DCMI_DCMI_CR_ENABLE_Msk = 0x4000
	// Bit ENABLE.
	DCMI_DCMI_CR_ENABLE = 0x4000
	// Position of BSM field.
	DCMI_DCMI_CR_BSM_Pos = 0x10
	// Bit mask of BSM field.
	DCMI_DCMI_CR_BSM_Msk = 0x30000
	// Position of OEBS field.
	DCMI_DCMI_CR_OEBS_Pos = 0x12
	// Bit mask of OEBS field.
	DCMI_DCMI_CR_OEBS_Msk = 0x40000
	// Bit OEBS.
	DCMI_DCMI_CR_OEBS = 0x40000
	// Position of LSM field.
	DCMI_DCMI_CR_LSM_Pos = 0x13
	// Bit mask of LSM field.
	DCMI_DCMI_CR_LSM_Msk = 0x80000
	// Bit LSM.
	DCMI_DCMI_CR_LSM = 0x80000
	// Position of OELS field.
	DCMI_DCMI_CR_OELS_Pos = 0x14
	// Bit mask of OELS field.
	DCMI_DCMI_CR_OELS_Msk = 0x100000
	// Bit OELS.
	DCMI_DCMI_CR_OELS = 0x100000

	// DCMI_SR: DCMI status register
	// Position of HSYNC field.
	DCMI_DCMI_SR_HSYNC_Pos = 0x0
	// Bit mask of HSYNC field.
	DCMI_DCMI_SR_HSYNC_Msk = 0x1
	// Bit HSYNC.
	DCMI_DCMI_SR_HSYNC = 0x1
	// Position of VSYNC field.
	DCMI_DCMI_SR_VSYNC_Pos = 0x1
	// Bit mask of VSYNC field.
	DCMI_DCMI_SR_VSYNC_Msk = 0x2
	// Bit VSYNC.
	DCMI_DCMI_SR_VSYNC = 0x2
	// Position of FNE field.
	DCMI_DCMI_SR_FNE_Pos = 0x2
	// Bit mask of FNE field.
	DCMI_DCMI_SR_FNE_Msk = 0x4
	// Bit FNE.
	DCMI_DCMI_SR_FNE = 0x4

	// DCMI_RIS: DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value.
	// Position of FRAME_RIS field.
	DCMI_DCMI_RIS_FRAME_RIS_Pos = 0x0
	// Bit mask of FRAME_RIS field.
	DCMI_DCMI_RIS_FRAME_RIS_Msk = 0x1
	// Bit FRAME_RIS.
	DCMI_DCMI_RIS_FRAME_RIS = 0x1
	// Position of OVR_RIS field.
	DCMI_DCMI_RIS_OVR_RIS_Pos = 0x1
	// Bit mask of OVR_RIS field.
	DCMI_DCMI_RIS_OVR_RIS_Msk = 0x2
	// Bit OVR_RIS.
	DCMI_DCMI_RIS_OVR_RIS = 0x2
	// Position of ERR_RIS field.
	DCMI_DCMI_RIS_ERR_RIS_Pos = 0x2
	// Bit mask of ERR_RIS field.
	DCMI_DCMI_RIS_ERR_RIS_Msk = 0x4
	// Bit ERR_RIS.
	DCMI_DCMI_RIS_ERR_RIS = 0x4
	// Position of VSYNC_RIS field.
	DCMI_DCMI_RIS_VSYNC_RIS_Pos = 0x3
	// Bit mask of VSYNC_RIS field.
	DCMI_DCMI_RIS_VSYNC_RIS_Msk = 0x8
	// Bit VSYNC_RIS.
	DCMI_DCMI_RIS_VSYNC_RIS = 0x8
	// Position of LINE_RIS field.
	DCMI_DCMI_RIS_LINE_RIS_Pos = 0x4
	// Bit mask of LINE_RIS field.
	DCMI_DCMI_RIS_LINE_RIS_Msk = 0x10
	// Bit LINE_RIS.
	DCMI_DCMI_RIS_LINE_RIS = 0x10

	// DCMI_IER: The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write.
	// Position of FRAME_IE field.
	DCMI_DCMI_IER_FRAME_IE_Pos = 0x0
	// Bit mask of FRAME_IE field.
	DCMI_DCMI_IER_FRAME_IE_Msk = 0x1
	// Bit FRAME_IE.
	DCMI_DCMI_IER_FRAME_IE = 0x1
	// Position of OVR_IE field.
	DCMI_DCMI_IER_OVR_IE_Pos = 0x1
	// Bit mask of OVR_IE field.
	DCMI_DCMI_IER_OVR_IE_Msk = 0x2
	// Bit OVR_IE.
	DCMI_DCMI_IER_OVR_IE = 0x2
	// Position of ERR_IE field.
	DCMI_DCMI_IER_ERR_IE_Pos = 0x2
	// Bit mask of ERR_IE field.
	DCMI_DCMI_IER_ERR_IE_Msk = 0x4
	// Bit ERR_IE.
	DCMI_DCMI_IER_ERR_IE = 0x4
	// Position of VSYNC_IE field.
	DCMI_DCMI_IER_VSYNC_IE_Pos = 0x3
	// Bit mask of VSYNC_IE field.
	DCMI_DCMI_IER_VSYNC_IE_Msk = 0x8
	// Bit VSYNC_IE.
	DCMI_DCMI_IER_VSYNC_IE = 0x8
	// Position of LINE_IE field.
	DCMI_DCMI_IER_LINE_IE_Pos = 0x4
	// Bit mask of LINE_IE field.
	DCMI_DCMI_IER_LINE_IE_Msk = 0x10
	// Bit LINE_IE.
	DCMI_DCMI_IER_LINE_IE = 0x10

	// DCMI_MIS: This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
	// Position of FRAME_MIS field.
	DCMI_DCMI_MIS_FRAME_MIS_Pos = 0x0
	// Bit mask of FRAME_MIS field.
	DCMI_DCMI_MIS_FRAME_MIS_Msk = 0x1
	// Bit FRAME_MIS.
	DCMI_DCMI_MIS_FRAME_MIS = 0x1
	// Position of OVR_MIS field.
	DCMI_DCMI_MIS_OVR_MIS_Pos = 0x1
	// Bit mask of OVR_MIS field.
	DCMI_DCMI_MIS_OVR_MIS_Msk = 0x2
	// Bit OVR_MIS.
	DCMI_DCMI_MIS_OVR_MIS = 0x2
	// Position of ERR_MIS field.
	DCMI_DCMI_MIS_ERR_MIS_Pos = 0x2
	// Bit mask of ERR_MIS field.
	DCMI_DCMI_MIS_ERR_MIS_Msk = 0x4
	// Bit ERR_MIS.
	DCMI_DCMI_MIS_ERR_MIS = 0x4
	// Position of VSYNC_MIS field.
	DCMI_DCMI_MIS_VSYNC_MIS_Pos = 0x3
	// Bit mask of VSYNC_MIS field.
	DCMI_DCMI_MIS_VSYNC_MIS_Msk = 0x8
	// Bit VSYNC_MIS.
	DCMI_DCMI_MIS_VSYNC_MIS = 0x8
	// Position of LINE_MIS field.
	DCMI_DCMI_MIS_LINE_MIS_Pos = 0x4
	// Bit mask of LINE_MIS field.
	DCMI_DCMI_MIS_LINE_MIS_Msk = 0x10
	// Bit LINE_MIS.
	DCMI_DCMI_MIS_LINE_MIS = 0x10

	// DCMI_ICR: The DCMI_ICR register is write-only.
	// Position of FRAME_ISC field.
	DCMI_DCMI_ICR_FRAME_ISC_Pos = 0x0
	// Bit mask of FRAME_ISC field.
	DCMI_DCMI_ICR_FRAME_ISC_Msk = 0x1
	// Bit FRAME_ISC.
	DCMI_DCMI_ICR_FRAME_ISC = 0x1
	// Position of OVR_ISC field.
	DCMI_DCMI_ICR_OVR_ISC_Pos = 0x1
	// Bit mask of OVR_ISC field.
	DCMI_DCMI_ICR_OVR_ISC_Msk = 0x2
	// Bit OVR_ISC.
	DCMI_DCMI_ICR_OVR_ISC = 0x2
	// Position of ERR_ISC field.
	DCMI_DCMI_ICR_ERR_ISC_Pos = 0x2
	// Bit mask of ERR_ISC field.
	DCMI_DCMI_ICR_ERR_ISC_Msk = 0x4
	// Bit ERR_ISC.
	DCMI_DCMI_ICR_ERR_ISC = 0x4
	// Position of VSYNC_ISC field.
	DCMI_DCMI_ICR_VSYNC_ISC_Pos = 0x3
	// Bit mask of VSYNC_ISC field.
	DCMI_DCMI_ICR_VSYNC_ISC_Msk = 0x8
	// Bit VSYNC_ISC.
	DCMI_DCMI_ICR_VSYNC_ISC = 0x8
	// Position of LINE_ISC field.
	DCMI_DCMI_ICR_LINE_ISC_Pos = 0x4
	// Bit mask of LINE_ISC field.
	DCMI_DCMI_ICR_LINE_ISC_Msk = 0x10
	// Bit LINE_ISC.
	DCMI_DCMI_ICR_LINE_ISC = 0x10

	// DCMI_ESCR: DCMI embedded synchronization code register
	// Position of FSC field.
	DCMI_DCMI_ESCR_FSC_Pos = 0x0
	// Bit mask of FSC field.
	DCMI_DCMI_ESCR_FSC_Msk = 0xff
	// Position of LSC field.
	DCMI_DCMI_ESCR_LSC_Pos = 0x8
	// Bit mask of LSC field.
	DCMI_DCMI_ESCR_LSC_Msk = 0xff00
	// Position of LEC field.
	DCMI_DCMI_ESCR_LEC_Pos = 0x10
	// Bit mask of LEC field.
	DCMI_DCMI_ESCR_LEC_Msk = 0xff0000
	// Position of FEC field.
	DCMI_DCMI_ESCR_FEC_Pos = 0x18
	// Bit mask of FEC field.
	DCMI_DCMI_ESCR_FEC_Msk = 0xff000000

	// DCMI_ESUR: DCMI embedded synchronization unmask register
	// Position of FSU field.
	DCMI_DCMI_ESUR_FSU_Pos = 0x0
	// Bit mask of FSU field.
	DCMI_DCMI_ESUR_FSU_Msk = 0xff
	// Position of LSU field.
	DCMI_DCMI_ESUR_LSU_Pos = 0x8
	// Bit mask of LSU field.
	DCMI_DCMI_ESUR_LSU_Msk = 0xff00
	// Position of LEU field.
	DCMI_DCMI_ESUR_LEU_Pos = 0x10
	// Bit mask of LEU field.
	DCMI_DCMI_ESUR_LEU_Msk = 0xff0000
	// Position of FEU field.
	DCMI_DCMI_ESUR_FEU_Pos = 0x18
	// Bit mask of FEU field.
	DCMI_DCMI_ESUR_FEU_Msk = 0xff000000

	// DCMI_CWSTRT: DCMI crop window start
	// Position of HOFFCNT field.
	DCMI_DCMI_CWSTRT_HOFFCNT_Pos = 0x0
	// Bit mask of HOFFCNT field.
	DCMI_DCMI_CWSTRT_HOFFCNT_Msk = 0x3fff
	// Position of VST field.
	DCMI_DCMI_CWSTRT_VST_Pos = 0x10
	// Bit mask of VST field.
	DCMI_DCMI_CWSTRT_VST_Msk = 0x1fff0000

	// DCMI_CWSIZE: DCMI crop window size
	// Position of CAPCNT field.
	DCMI_DCMI_CWSIZE_CAPCNT_Pos = 0x0
	// Bit mask of CAPCNT field.
	DCMI_DCMI_CWSIZE_CAPCNT_Msk = 0x3fff
	// Position of VLINE field.
	DCMI_DCMI_CWSIZE_VLINE_Pos = 0x10
	// Bit mask of VLINE field.
	DCMI_DCMI_CWSIZE_VLINE_Msk = 0x3fff0000

	// DCMI_DR: DCMI data register
	// Position of Byte0 field.
	DCMI_DCMI_DR_Byte0_Pos = 0x0
	// Bit mask of Byte0 field.
	DCMI_DCMI_DR_Byte0_Msk = 0xff
	// Position of Byte1 field.
	DCMI_DCMI_DR_Byte1_Pos = 0x8
	// Bit mask of Byte1 field.
	DCMI_DCMI_DR_Byte1_Msk = 0xff00
	// Position of Byte2 field.
	DCMI_DCMI_DR_Byte2_Pos = 0x10
	// Bit mask of Byte2 field.
	DCMI_DCMI_DR_Byte2_Msk = 0xff0000
	// Position of Byte3 field.
	DCMI_DCMI_DR_Byte3_Pos = 0x18
	// Bit mask of Byte3 field.
	DCMI_DCMI_DR_Byte3_Msk = 0xff000000
)

// Bitfields for DDRCTRL: DDRCTRL
const (
	// DDRCTRL_MSTR: DDRCTRL master register 0
	// Position of DDR3 field.
	DDRCTRL_DDRCTRL_MSTR_DDR3_Pos = 0x0
	// Bit mask of DDR3 field.
	DDRCTRL_DDRCTRL_MSTR_DDR3_Msk = 0x1
	// Bit DDR3.
	DDRCTRL_DDRCTRL_MSTR_DDR3 = 0x1
	// Position of LPDDR2 field.
	DDRCTRL_DDRCTRL_MSTR_LPDDR2_Pos = 0x2
	// Bit mask of LPDDR2 field.
	DDRCTRL_DDRCTRL_MSTR_LPDDR2_Msk = 0x4
	// Bit LPDDR2.
	DDRCTRL_DDRCTRL_MSTR_LPDDR2 = 0x4
	// Position of LPDDR3 field.
	DDRCTRL_DDRCTRL_MSTR_LPDDR3_Pos = 0x3
	// Bit mask of LPDDR3 field.
	DDRCTRL_DDRCTRL_MSTR_LPDDR3_Msk = 0x8
	// Bit LPDDR3.
	DDRCTRL_DDRCTRL_MSTR_LPDDR3 = 0x8
	// Position of BURSTCHOP field.
	DDRCTRL_DDRCTRL_MSTR_BURSTCHOP_Pos = 0x9
	// Bit mask of BURSTCHOP field.
	DDRCTRL_DDRCTRL_MSTR_BURSTCHOP_Msk = 0x200
	// Bit BURSTCHOP.
	DDRCTRL_DDRCTRL_MSTR_BURSTCHOP = 0x200
	// Position of EN_2T_TIMING_MODE field.
	DDRCTRL_DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos = 0xa
	// Bit mask of EN_2T_TIMING_MODE field.
	DDRCTRL_DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk = 0x400
	// Bit EN_2T_TIMING_MODE.
	DDRCTRL_DDRCTRL_MSTR_EN_2T_TIMING_MODE = 0x400
	// Position of DATA_BUS_WIDTH field.
	DDRCTRL_DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos = 0xc
	// Bit mask of DATA_BUS_WIDTH field.
	DDRCTRL_DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk = 0x3000
	// Position of DLL_OFF_MODE field.
	DDRCTRL_DDRCTRL_MSTR_DLL_OFF_MODE_Pos = 0xf
	// Bit mask of DLL_OFF_MODE field.
	DDRCTRL_DDRCTRL_MSTR_DLL_OFF_MODE_Msk = 0x8000
	// Bit DLL_OFF_MODE.
	DDRCTRL_DDRCTRL_MSTR_DLL_OFF_MODE = 0x8000
	// Position of BURST_RDWR field.
	DDRCTRL_DDRCTRL_MSTR_BURST_RDWR_Pos = 0x10
	// Bit mask of BURST_RDWR field.
	DDRCTRL_DDRCTRL_MSTR_BURST_RDWR_Msk = 0xf0000

	// DDRCTRL_STAT: DDRCTRL operating mode status register
	// Position of OPERATING_MODE field.
	DDRCTRL_DDRCTRL_STAT_OPERATING_MODE_Pos = 0x0
	// Bit mask of OPERATING_MODE field.
	DDRCTRL_DDRCTRL_STAT_OPERATING_MODE_Msk = 0x7
	// Position of SELFREF_TYPE field.
	DDRCTRL_DDRCTRL_STAT_SELFREF_TYPE_Pos = 0x4
	// Bit mask of SELFREF_TYPE field.
	DDRCTRL_DDRCTRL_STAT_SELFREF_TYPE_Msk = 0x30
	// Position of SELFREF_CAM_NOT_EMPTY field.
	DDRCTRL_DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos = 0xc
	// Bit mask of SELFREF_CAM_NOT_EMPTY field.
	DDRCTRL_DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk = 0x1000
	// Bit SELFREF_CAM_NOT_EMPTY.
	DDRCTRL_DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY = 0x1000

	// DDRCTRL_MRCTRL0: Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en
	// Position of MR_TYPE field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_TYPE_Pos = 0x0
	// Bit mask of MR_TYPE field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_TYPE_Msk = 0x1
	// Bit MR_TYPE.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_TYPE = 0x1
	// Position of MR_RANK field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_RANK_Pos = 0x4
	// Bit mask of MR_RANK field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_RANK_Msk = 0x10
	// Bit MR_RANK.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_RANK = 0x10
	// Position of MR_ADDR field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_ADDR_Pos = 0xc
	// Bit mask of MR_ADDR field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_ADDR_Msk = 0xf000
	// Position of MR_WR field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_WR_Pos = 0x1f
	// Bit mask of MR_WR field.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_WR_Msk = 0x80000000
	// Bit MR_WR.
	DDRCTRL_DDRCTRL_MRCTRL0_MR_WR = 0x80000000

	// DDRCTRL_MRCTRL1: DDRCTRL mode register read/write control register 1
	// Position of MR_DATA field.
	DDRCTRL_DDRCTRL_MRCTRL1_MR_DATA_Pos = 0x0
	// Bit mask of MR_DATA field.
	DDRCTRL_DDRCTRL_MRCTRL1_MR_DATA_Msk = 0xffff

	// DDRCTRL_MRSTAT: DDRCTRL mode register read/write status register
	// Position of MR_WR_BUSY field.
	DDRCTRL_DDRCTRL_MRSTAT_MR_WR_BUSY_Pos = 0x0
	// Bit mask of MR_WR_BUSY field.
	DDRCTRL_DDRCTRL_MRSTAT_MR_WR_BUSY_Msk = 0x1
	// Bit MR_WR_BUSY.
	DDRCTRL_DDRCTRL_MRSTAT_MR_WR_BUSY = 0x1

	// DDRCTRL_DERATEEN: DDRCTRL temperature derate enable register
	// Position of DERATE_ENABLE field.
	DDRCTRL_DDRCTRL_DERATEEN_DERATE_ENABLE_Pos = 0x0
	// Bit mask of DERATE_ENABLE field.
	DDRCTRL_DDRCTRL_DERATEEN_DERATE_ENABLE_Msk = 0x1
	// Bit DERATE_ENABLE.
	DDRCTRL_DDRCTRL_DERATEEN_DERATE_ENABLE = 0x1
	// Position of DERATE_VALUE field.
	DDRCTRL_DDRCTRL_DERATEEN_DERATE_VALUE_Pos = 0x1
	// Bit mask of DERATE_VALUE field.
	DDRCTRL_DDRCTRL_DERATEEN_DERATE_VALUE_Msk = 0x6
	// Position of DERATE_BYTE field.
	DDRCTRL_DDRCTRL_DERATEEN_DERATE_BYTE_Pos = 0x4
	// Bit mask of DERATE_BYTE field.
	DDRCTRL_DDRCTRL_DERATEEN_DERATE_BYTE_Msk = 0xf0

	// DDRCTRL_DERATEINT: DDRCTRL temperature derate interval register
	// Position of MR4_READ_INTERVAL field.
	DDRCTRL_DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos = 0x0
	// Bit mask of MR4_READ_INTERVAL field.
	DDRCTRL_DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk = 0xffffffff

	// DDRCTRL_PWRCTL: DDRCTRL low power control register
	// Position of SELFREF_EN field.
	DDRCTRL_DDRCTRL_PWRCTL_SELFREF_EN_Pos = 0x0
	// Bit mask of SELFREF_EN field.
	DDRCTRL_DDRCTRL_PWRCTL_SELFREF_EN_Msk = 0x1
	// Bit SELFREF_EN.
	DDRCTRL_DDRCTRL_PWRCTL_SELFREF_EN = 0x1
	// Position of POWERDOWN_EN field.
	DDRCTRL_DDRCTRL_PWRCTL_POWERDOWN_EN_Pos = 0x1
	// Bit mask of POWERDOWN_EN field.
	DDRCTRL_DDRCTRL_PWRCTL_POWERDOWN_EN_Msk = 0x2
	// Bit POWERDOWN_EN.
	DDRCTRL_DDRCTRL_PWRCTL_POWERDOWN_EN = 0x2
	// Position of DEEPPOWERDOWN_EN field.
	DDRCTRL_DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos = 0x2
	// Bit mask of DEEPPOWERDOWN_EN field.
	DDRCTRL_DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk = 0x4
	// Bit DEEPPOWERDOWN_EN.
	DDRCTRL_DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN = 0x4
	// Position of EN_DFI_DRAM_CLK_DISABLE field.
	DDRCTRL_DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos = 0x3
	// Bit mask of EN_DFI_DRAM_CLK_DISABLE field.
	DDRCTRL_DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk = 0x8
	// Bit EN_DFI_DRAM_CLK_DISABLE.
	DDRCTRL_DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE = 0x8
	// Position of SELFREF_SW field.
	DDRCTRL_DDRCTRL_PWRCTL_SELFREF_SW_Pos = 0x5
	// Bit mask of SELFREF_SW field.
	DDRCTRL_DDRCTRL_PWRCTL_SELFREF_SW_Msk = 0x20
	// Bit SELFREF_SW.
	DDRCTRL_DDRCTRL_PWRCTL_SELFREF_SW = 0x20
	// Position of DIS_CAM_DRAIN_SELFREF field.
	DDRCTRL_DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos = 0x7
	// Bit mask of DIS_CAM_DRAIN_SELFREF field.
	DDRCTRL_DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk = 0x80
	// Bit DIS_CAM_DRAIN_SELFREF.
	DDRCTRL_DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF = 0x80

	// DDRCTRL_PWRTMG: DDRCTRL low power timing register
	// Position of POWERDOWN_TO_X32 field.
	DDRCTRL_DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos = 0x0
	// Bit mask of POWERDOWN_TO_X32 field.
	DDRCTRL_DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk = 0x1f
	// Position of T_DPD_X4096 field.
	DDRCTRL_DDRCTRL_PWRTMG_T_DPD_X4096_Pos = 0x8
	// Bit mask of T_DPD_X4096 field.
	DDRCTRL_DDRCTRL_PWRTMG_T_DPD_X4096_Msk = 0xff00
	// Position of SELFREF_TO_X32 field.
	DDRCTRL_DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos = 0x10
	// Bit mask of SELFREF_TO_X32 field.
	DDRCTRL_DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk = 0xff0000

	// DDRCTRL_HWLPCTL: DDRCTRL hardware low power control register
	// Position of HW_LP_EN field.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_EN_Pos = 0x0
	// Bit mask of HW_LP_EN field.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_EN_Msk = 0x1
	// Bit HW_LP_EN.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_EN = 0x1
	// Position of HW_LP_EXIT_IDLE_EN field.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos = 0x1
	// Bit mask of HW_LP_EXIT_IDLE_EN field.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk = 0x2
	// Bit HW_LP_EXIT_IDLE_EN.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN = 0x2
	// Position of HW_LP_IDLE_X32 field.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos = 0x10
	// Bit mask of HW_LP_IDLE_X32 field.
	DDRCTRL_DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk = 0xfff0000

	// DDRCTRL_RFSHCTL0: DDRCTRL refresh control register 0
	// Position of PER_BANK_REFRESH field.
	DDRCTRL_DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos = 0x2
	// Bit mask of PER_BANK_REFRESH field.
	DDRCTRL_DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk = 0x4
	// Bit PER_BANK_REFRESH.
	DDRCTRL_DDRCTRL_RFSHCTL0_PER_BANK_REFRESH = 0x4
	// Position of REFRESH_BURST field.
	DDRCTRL_DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos = 0x4
	// Bit mask of REFRESH_BURST field.
	DDRCTRL_DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk = 0x1f0
	// Position of REFRESH_TO_X32 field.
	DDRCTRL_DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos = 0xc
	// Bit mask of REFRESH_TO_X32 field.
	DDRCTRL_DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk = 0x1f000
	// Position of REFRESH_MARGIN field.
	DDRCTRL_DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos = 0x14
	// Bit mask of REFRESH_MARGIN field.
	DDRCTRL_DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk = 0xf00000

	// DDRCTRL_RFSHCTL3: DDRCTRL refresh control register 3
	// Position of DIS_AUTO_REFRESH field.
	DDRCTRL_DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos = 0x0
	// Bit mask of DIS_AUTO_REFRESH field.
	DDRCTRL_DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk = 0x1
	// Bit DIS_AUTO_REFRESH.
	DDRCTRL_DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH = 0x1
	// Position of REFRESH_UPDATE_LEVEL field.
	DDRCTRL_DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos = 0x1
	// Bit mask of REFRESH_UPDATE_LEVEL field.
	DDRCTRL_DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk = 0x2
	// Bit REFRESH_UPDATE_LEVEL.
	DDRCTRL_DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL = 0x2

	// DDRCTRL_RFSHTMG: DDRCTRL refresh timing register
	// Position of T_RFC_MIN field.
	DDRCTRL_DDRCTRL_RFSHTMG_T_RFC_MIN_Pos = 0x0
	// Bit mask of T_RFC_MIN field.
	DDRCTRL_DDRCTRL_RFSHTMG_T_RFC_MIN_Msk = 0x3ff
	// Position of LPDDR3_TREFBW_EN field.
	DDRCTRL_DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos = 0xf
	// Bit mask of LPDDR3_TREFBW_EN field.
	DDRCTRL_DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk = 0x8000
	// Bit LPDDR3_TREFBW_EN.
	DDRCTRL_DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN = 0x8000
	// Position of T_RFC_NOM_X1_X32 field.
	DDRCTRL_DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos = 0x10
	// Bit mask of T_RFC_NOM_X1_X32 field.
	DDRCTRL_DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk = 0xfff0000
	// Position of T_RFC_NOM_X1_SEL field.
	DDRCTRL_DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos = 0x1f
	// Bit mask of T_RFC_NOM_X1_SEL field.
	DDRCTRL_DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk = 0x80000000
	// Bit T_RFC_NOM_X1_SEL.
	DDRCTRL_DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL = 0x80000000

	// DDRCTRL_CRCPARCTL0: DDRCTRL CRC parity control register 0
	// Position of DFI_ALERT_ERR_INT_EN field.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos = 0x0
	// Bit mask of DFI_ALERT_ERR_INT_EN field.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk = 0x1
	// Bit DFI_ALERT_ERR_INT_EN.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN = 0x1
	// Position of DFI_ALERT_ERR_INT_CLR field.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos = 0x1
	// Bit mask of DFI_ALERT_ERR_INT_CLR field.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk = 0x2
	// Bit DFI_ALERT_ERR_INT_CLR.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR = 0x2
	// Position of DFI_ALERT_ERR_CNT_CLR field.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos = 0x2
	// Bit mask of DFI_ALERT_ERR_CNT_CLR field.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk = 0x4
	// Bit DFI_ALERT_ERR_CNT_CLR.
	DDRCTRL_DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR = 0x4

	// DDRCTRL_CRCPARSTAT: DDRCTRL CRC parity status register
	// Position of DFI_ALERT_ERR_CNT field.
	DDRCTRL_DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos = 0x0
	// Bit mask of DFI_ALERT_ERR_CNT field.
	DDRCTRL_DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk = 0xffff
	// Position of DFI_ALERT_ERR_INT field.
	DDRCTRL_DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos = 0x10
	// Bit mask of DFI_ALERT_ERR_INT field.
	DDRCTRL_DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk = 0x10000
	// Bit DFI_ALERT_ERR_INT.
	DDRCTRL_DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT = 0x10000

	// DDRCTRL_INIT0: DDRCTRL SDRAM initialization register 0
	// Position of PRE_CKE_X1024 field.
	DDRCTRL_DDRCTRL_INIT0_PRE_CKE_X1024_Pos = 0x0
	// Bit mask of PRE_CKE_X1024 field.
	DDRCTRL_DDRCTRL_INIT0_PRE_CKE_X1024_Msk = 0xfff
	// Position of POST_CKE_X1024 field.
	DDRCTRL_DDRCTRL_INIT0_POST_CKE_X1024_Pos = 0x10
	// Bit mask of POST_CKE_X1024 field.
	DDRCTRL_DDRCTRL_INIT0_POST_CKE_X1024_Msk = 0x3ff0000
	// Position of SKIP_DRAM_INIT field.
	DDRCTRL_DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos = 0x1e
	// Bit mask of SKIP_DRAM_INIT field.
	DDRCTRL_DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk = 0xc0000000

	// DDRCTRL_INIT1: DDRCTRL SDRAM initialization register 1
	// Position of PRE_OCD_X32 field.
	DDRCTRL_DDRCTRL_INIT1_PRE_OCD_X32_Pos = 0x0
	// Bit mask of PRE_OCD_X32 field.
	DDRCTRL_DDRCTRL_INIT1_PRE_OCD_X32_Msk = 0xf
	// Position of DRAM_RSTN_X1024 field.
	DDRCTRL_DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos = 0x10
	// Bit mask of DRAM_RSTN_X1024 field.
	DDRCTRL_DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk = 0x1ff0000

	// DDRCTRL_INIT2: DDRCTRL SDRAM initialization register 2
	// Position of MIN_STABLE_CLOCK_X1 field.
	DDRCTRL_DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos = 0x0
	// Bit mask of MIN_STABLE_CLOCK_X1 field.
	DDRCTRL_DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk = 0xf
	// Position of IDLE_AFTER_RESET_X32 field.
	DDRCTRL_DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos = 0x8
	// Bit mask of IDLE_AFTER_RESET_X32 field.
	DDRCTRL_DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk = 0xff00

	// DDRCTRL_INIT3: DDRCTRL SDRAM initialization register 3
	// Position of EMR field.
	DDRCTRL_DDRCTRL_INIT3_EMR_Pos = 0x0
	// Bit mask of EMR field.
	DDRCTRL_DDRCTRL_INIT3_EMR_Msk = 0xffff
	// Position of MR field.
	DDRCTRL_DDRCTRL_INIT3_MR_Pos = 0x10
	// Bit mask of MR field.
	DDRCTRL_DDRCTRL_INIT3_MR_Msk = 0xffff0000

	// DDRCTRL_INIT4: DDRCTRL SDRAM initialization register 4
	// Position of EMR3 field.
	DDRCTRL_DDRCTRL_INIT4_EMR3_Pos = 0x0
	// Bit mask of EMR3 field.
	DDRCTRL_DDRCTRL_INIT4_EMR3_Msk = 0xffff
	// Position of EMR2 field.
	DDRCTRL_DDRCTRL_INIT4_EMR2_Pos = 0x10
	// Bit mask of EMR2 field.
	DDRCTRL_DDRCTRL_INIT4_EMR2_Msk = 0xffff0000

	// DDRCTRL_INIT5: DDRCTRL SDRAM initialization register 5
	// Position of MAX_AUTO_INIT_X1024 field.
	DDRCTRL_DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos = 0x0
	// Bit mask of MAX_AUTO_INIT_X1024 field.
	DDRCTRL_DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk = 0x3ff
	// Position of DEV_ZQINIT_X32 field.
	DDRCTRL_DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos = 0x10
	// Bit mask of DEV_ZQINIT_X32 field.
	DDRCTRL_DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk = 0xff0000

	// DDRCTRL_DIMMCTL: DDRCTRL DIMM control register
	// Position of DIMM_STAGGER_CS_EN field.
	DDRCTRL_DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos = 0x0
	// Bit mask of DIMM_STAGGER_CS_EN field.
	DDRCTRL_DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk = 0x1
	// Bit DIMM_STAGGER_CS_EN.
	DDRCTRL_DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN = 0x1
	// Position of DIMM_ADDR_MIRR_EN field.
	DDRCTRL_DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos = 0x1
	// Bit mask of DIMM_ADDR_MIRR_EN field.
	DDRCTRL_DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk = 0x2
	// Bit DIMM_ADDR_MIRR_EN.
	DDRCTRL_DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN = 0x2

	// DDRCTRL_DRAMTMG0: DDRCTRL SDRAM timing register 0
	// Position of T_RAS_MIN field.
	DDRCTRL_DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos = 0x0
	// Bit mask of T_RAS_MIN field.
	DDRCTRL_DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk = 0x3f
	// Position of T_RAS_MAX field.
	DDRCTRL_DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos = 0x8
	// Bit mask of T_RAS_MAX field.
	DDRCTRL_DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk = 0x7f00
	// Position of T_FAW field.
	DDRCTRL_DDRCTRL_DRAMTMG0_T_FAW_Pos = 0x10
	// Bit mask of T_FAW field.
	DDRCTRL_DDRCTRL_DRAMTMG0_T_FAW_Msk = 0x3f0000
	// Position of WR2PRE field.
	DDRCTRL_DDRCTRL_DRAMTMG0_WR2PRE_Pos = 0x18
	// Bit mask of WR2PRE field.
	DDRCTRL_DDRCTRL_DRAMTMG0_WR2PRE_Msk = 0x7f000000

	// DDRCTRL_DRAMTMG1: DDRCTRL SDRAM timing register 1
	// Position of T_RC field.
	DDRCTRL_DDRCTRL_DRAMTMG1_T_RC_Pos = 0x0
	// Bit mask of T_RC field.
	DDRCTRL_DDRCTRL_DRAMTMG1_T_RC_Msk = 0x7f
	// Position of RD2PRE field.
	DDRCTRL_DDRCTRL_DRAMTMG1_RD2PRE_Pos = 0x8
	// Bit mask of RD2PRE field.
	DDRCTRL_DDRCTRL_DRAMTMG1_RD2PRE_Msk = 0x3f00
	// Position of T_XP field.
	DDRCTRL_DDRCTRL_DRAMTMG1_T_XP_Pos = 0x10
	// Bit mask of T_XP field.
	DDRCTRL_DDRCTRL_DRAMTMG1_T_XP_Msk = 0x1f0000

	// DDRCTRL_DRAMTMG2: DDRCTRL SDRAM timing register 2
	// Position of WR2RD field.
	DDRCTRL_DDRCTRL_DRAMTMG2_WR2RD_Pos = 0x0
	// Bit mask of WR2RD field.
	DDRCTRL_DDRCTRL_DRAMTMG2_WR2RD_Msk = 0x3f
	// Position of RD2WR field.
	DDRCTRL_DDRCTRL_DRAMTMG2_RD2WR_Pos = 0x8
	// Bit mask of RD2WR field.
	DDRCTRL_DDRCTRL_DRAMTMG2_RD2WR_Msk = 0x3f00
	// Position of READ_LATENCY field.
	DDRCTRL_DDRCTRL_DRAMTMG2_READ_LATENCY_Pos = 0x10
	// Bit mask of READ_LATENCY field.
	DDRCTRL_DDRCTRL_DRAMTMG2_READ_LATENCY_Msk = 0x3f0000
	// Position of WRITE_LATENCY field.
	DDRCTRL_DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos = 0x18
	// Bit mask of WRITE_LATENCY field.
	DDRCTRL_DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk = 0x3f000000

	// DDRCTRL_DRAMTMG3: DDRCTRL SDRAM timing register 3
	// Position of T_MOD field.
	DDRCTRL_DDRCTRL_DRAMTMG3_T_MOD_Pos = 0x0
	// Bit mask of T_MOD field.
	DDRCTRL_DDRCTRL_DRAMTMG3_T_MOD_Msk = 0x3ff
	// Position of T_MRD field.
	DDRCTRL_DDRCTRL_DRAMTMG3_T_MRD_Pos = 0xc
	// Bit mask of T_MRD field.
	DDRCTRL_DDRCTRL_DRAMTMG3_T_MRD_Msk = 0x3f000
	// Position of T_MRW field.
	DDRCTRL_DDRCTRL_DRAMTMG3_T_MRW_Pos = 0x14
	// Bit mask of T_MRW field.
	DDRCTRL_DDRCTRL_DRAMTMG3_T_MRW_Msk = 0x3ff00000

	// DDRCTRL_DRAMTMG4: DDRCTRL SDRAM timing register 4
	// Position of T_RP field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_RP_Pos = 0x0
	// Bit mask of T_RP field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_RP_Msk = 0x1f
	// Position of T_RRD field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_RRD_Pos = 0x8
	// Bit mask of T_RRD field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_RRD_Msk = 0xf00
	// Position of T_CCD field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_CCD_Pos = 0x10
	// Bit mask of T_CCD field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_CCD_Msk = 0xf0000
	// Position of T_RCD field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_RCD_Pos = 0x18
	// Bit mask of T_RCD field.
	DDRCTRL_DDRCTRL_DRAMTMG4_T_RCD_Msk = 0x1f000000

	// DDRCTRL_DRAMTMG5: DDRCTRL SDRAM timing register 5
	// Position of T_CKE field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKE_Pos = 0x0
	// Bit mask of T_CKE field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKE_Msk = 0x1f
	// Position of T_CKESR field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKESR_Pos = 0x8
	// Bit mask of T_CKESR field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKESR_Msk = 0x3f00
	// Position of T_CKSRE field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKSRE_Pos = 0x10
	// Bit mask of T_CKSRE field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKSRE_Msk = 0xf0000
	// Position of T_CKSRX field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKSRX_Pos = 0x18
	// Bit mask of T_CKSRX field.
	DDRCTRL_DDRCTRL_DRAMTMG5_T_CKSRX_Msk = 0xf000000

	// DDRCTRL_DRAMTMG6: DDRCTRL SDRAM timing register 6
	// Position of T_CKCSX field.
	DDRCTRL_DDRCTRL_DRAMTMG6_T_CKCSX_Pos = 0x0
	// Bit mask of T_CKCSX field.
	DDRCTRL_DDRCTRL_DRAMTMG6_T_CKCSX_Msk = 0xf
	// Position of T_CKDPDX field.
	DDRCTRL_DDRCTRL_DRAMTMG6_T_CKDPDX_Pos = 0x10
	// Bit mask of T_CKDPDX field.
	DDRCTRL_DDRCTRL_DRAMTMG6_T_CKDPDX_Msk = 0xf0000
	// Position of T_CKDPDE field.
	DDRCTRL_DDRCTRL_DRAMTMG6_T_CKDPDE_Pos = 0x18
	// Bit mask of T_CKDPDE field.
	DDRCTRL_DDRCTRL_DRAMTMG6_T_CKDPDE_Msk = 0xf000000

	// DDRCTRL_DRAMTMG7: DDRCTRL SDRAM timing register 7
	// Position of T_CKPDX field.
	DDRCTRL_DDRCTRL_DRAMTMG7_T_CKPDX_Pos = 0x0
	// Bit mask of T_CKPDX field.
	DDRCTRL_DDRCTRL_DRAMTMG7_T_CKPDX_Msk = 0xf
	// Position of T_CKPDE field.
	DDRCTRL_DDRCTRL_DRAMTMG7_T_CKPDE_Pos = 0x8
	// Bit mask of T_CKPDE field.
	DDRCTRL_DDRCTRL_DRAMTMG7_T_CKPDE_Msk = 0xf00

	// DDRCTRL_DRAMTMG8: DDRCTRL SDRAM timing register 8
	// Position of T_XS_X32 field.
	DDRCTRL_DDRCTRL_DRAMTMG8_T_XS_X32_Pos = 0x0
	// Bit mask of T_XS_X32 field.
	DDRCTRL_DDRCTRL_DRAMTMG8_T_XS_X32_Msk = 0x7f
	// Position of T_XS_DLL_X32 field.
	DDRCTRL_DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos = 0x8
	// Bit mask of T_XS_DLL_X32 field.
	DDRCTRL_DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk = 0x7f00

	// DDRCTRL_DRAMTMG14: DDRCTRL SDRAM timing register 14
	// Position of T_XSR field.
	DDRCTRL_DDRCTRL_DRAMTMG14_T_XSR_Pos = 0x0
	// Bit mask of T_XSR field.
	DDRCTRL_DDRCTRL_DRAMTMG14_T_XSR_Msk = 0xfff

	// DDRCTRL_DRAMTMG15: DDRCTRL SDRAM timing register 15
	// Position of T_STAB_X32 field.
	DDRCTRL_DDRCTRL_DRAMTMG15_T_STAB_X32_Pos = 0x0
	// Bit mask of T_STAB_X32 field.
	DDRCTRL_DDRCTRL_DRAMTMG15_T_STAB_X32_Msk = 0xff
	// Position of EN_DFI_LP_T_STAB field.
	DDRCTRL_DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos = 0x1f
	// Bit mask of EN_DFI_LP_T_STAB field.
	DDRCTRL_DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk = 0x80000000
	// Bit EN_DFI_LP_T_STAB.
	DDRCTRL_DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB = 0x80000000

	// DDRCTRL_ZQCTL0: DDRCTRL ZQ control register 0
	// Position of T_ZQ_SHORT_NOP field.
	DDRCTRL_DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos = 0x0
	// Bit mask of T_ZQ_SHORT_NOP field.
	DDRCTRL_DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk = 0x3ff
	// Position of T_ZQ_LONG_NOP field.
	DDRCTRL_DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos = 0x10
	// Bit mask of T_ZQ_LONG_NOP field.
	DDRCTRL_DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk = 0x7ff0000
	// Position of ZQ_RESISTOR_SHARED field.
	DDRCTRL_DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos = 0x1d
	// Bit mask of ZQ_RESISTOR_SHARED field.
	DDRCTRL_DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk = 0x20000000
	// Bit ZQ_RESISTOR_SHARED.
	DDRCTRL_DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED = 0x20000000
	// Position of DIS_SRX_ZQCL field.
	DDRCTRL_DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos = 0x1e
	// Bit mask of DIS_SRX_ZQCL field.
	DDRCTRL_DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk = 0x40000000
	// Bit DIS_SRX_ZQCL.
	DDRCTRL_DDRCTRL_ZQCTL0_DIS_SRX_ZQCL = 0x40000000
	// Position of DIS_AUTO_ZQ field.
	DDRCTRL_DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos = 0x1f
	// Bit mask of DIS_AUTO_ZQ field.
	DDRCTRL_DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk = 0x80000000
	// Bit DIS_AUTO_ZQ.
	DDRCTRL_DDRCTRL_ZQCTL0_DIS_AUTO_ZQ = 0x80000000

	// DDRCTRL_ZQCTL1: DDRCTRL ZQ control register 1
	// Position of T_ZQ_SHORT_INTERVAL_X1024 field.
	DDRCTRL_DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos = 0x0
	// Bit mask of T_ZQ_SHORT_INTERVAL_X1024 field.
	DDRCTRL_DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk = 0xfffff
	// Position of T_ZQ_RESET_NOP field.
	DDRCTRL_DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos = 0x14
	// Bit mask of T_ZQ_RESET_NOP field.
	DDRCTRL_DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk = 0x3ff00000

	// DDRCTRL_ZQCTL2: DDRCTRL ZQ control register 2
	// Position of ZQ_RESET field.
	DDRCTRL_DDRCTRL_ZQCTL2_ZQ_RESET_Pos = 0x0
	// Bit mask of ZQ_RESET field.
	DDRCTRL_DDRCTRL_ZQCTL2_ZQ_RESET_Msk = 0x1
	// Bit ZQ_RESET.
	DDRCTRL_DDRCTRL_ZQCTL2_ZQ_RESET = 0x1

	// DDRCTRL_ZQSTAT: DDRCTRL ZQ status register
	// Position of ZQ_RESET_BUSY field.
	DDRCTRL_DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos = 0x0
	// Bit mask of ZQ_RESET_BUSY field.
	DDRCTRL_DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk = 0x1
	// Bit ZQ_RESET_BUSY.
	DDRCTRL_DDRCTRL_ZQSTAT_ZQ_RESET_BUSY = 0x1

	// DDRCTRL_DFITMG0: DDRCTRL DFI timing register 0
	// Position of DFI_TPHY_WRLAT field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos = 0x0
	// Bit mask of DFI_TPHY_WRLAT field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk = 0x3f
	// Position of DFI_TPHY_WRDATA field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos = 0x8
	// Bit mask of DFI_TPHY_WRDATA field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk = 0x3f00
	// Position of DFI_T_RDDATA_EN field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos = 0x10
	// Bit mask of DFI_T_RDDATA_EN field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk = 0x7f0000
	// Position of DFI_T_CTRL_DELAY field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos = 0x18
	// Bit mask of DFI_T_CTRL_DELAY field.
	DDRCTRL_DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk = 0x1f000000

	// DDRCTRL_DFITMG1: DDRCTRL DFI timing register 1
	// Position of DFI_T_DRAM_CLK_ENABLE field.
	DDRCTRL_DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos = 0x0
	// Bit mask of DFI_T_DRAM_CLK_ENABLE field.
	DDRCTRL_DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk = 0x1f
	// Position of DFI_T_DRAM_CLK_DISABLE field.
	DDRCTRL_DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos = 0x8
	// Bit mask of DFI_T_DRAM_CLK_DISABLE field.
	DDRCTRL_DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk = 0x1f00
	// Position of DFI_T_WRDATA_DELAY field.
	DDRCTRL_DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos = 0x10
	// Bit mask of DFI_T_WRDATA_DELAY field.
	DDRCTRL_DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk = 0x1f0000

	// DDRCTRL_DFILPCFG0: DDRCTRL low power configuration register 0
	// Position of DFI_LP_EN_PD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos = 0x0
	// Bit mask of DFI_LP_EN_PD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk = 0x1
	// Bit DFI_LP_EN_PD.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_PD = 0x1
	// Position of DFI_LP_WAKEUP_PD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos = 0x4
	// Bit mask of DFI_LP_WAKEUP_PD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk = 0xf0
	// Position of DFI_LP_EN_SR field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos = 0x8
	// Bit mask of DFI_LP_EN_SR field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk = 0x100
	// Bit DFI_LP_EN_SR.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_SR = 0x100
	// Position of DFI_LP_WAKEUP_SR field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos = 0xc
	// Bit mask of DFI_LP_WAKEUP_SR field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk = 0xf000
	// Position of DFI_LP_EN_DPD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos = 0x10
	// Bit mask of DFI_LP_EN_DPD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk = 0x10000
	// Bit DFI_LP_EN_DPD.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD = 0x10000
	// Position of DFI_LP_WAKEUP_DPD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos = 0x14
	// Bit mask of DFI_LP_WAKEUP_DPD field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk = 0xf00000
	// Position of DFI_TLP_RESP field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos = 0x18
	// Bit mask of DFI_TLP_RESP field.
	DDRCTRL_DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk = 0x1f000000

	// DDRCTRL_DFIUPD0: DDRCTRL DFI update register 0
	// Position of DFI_T_CTRLUP_MIN field.
	DDRCTRL_DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos = 0x0
	// Bit mask of DFI_T_CTRLUP_MIN field.
	DDRCTRL_DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk = 0x3ff
	// Position of DFI_T_CTRLUP_MAX field.
	DDRCTRL_DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos = 0x10
	// Bit mask of DFI_T_CTRLUP_MAX field.
	DDRCTRL_DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk = 0x3ff0000
	// Position of CTRLUPD_PRE_SRX field.
	DDRCTRL_DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos = 0x1d
	// Bit mask of CTRLUPD_PRE_SRX field.
	DDRCTRL_DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk = 0x20000000
	// Bit CTRLUPD_PRE_SRX.
	DDRCTRL_DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX = 0x20000000
	// Position of DIS_AUTO_CTRLUPD_SRX field.
	DDRCTRL_DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos = 0x1e
	// Bit mask of DIS_AUTO_CTRLUPD_SRX field.
	DDRCTRL_DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk = 0x40000000
	// Bit DIS_AUTO_CTRLUPD_SRX.
	DDRCTRL_DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX = 0x40000000
	// Position of DIS_AUTO_CTRLUPD field.
	DDRCTRL_DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos = 0x1f
	// Bit mask of DIS_AUTO_CTRLUPD field.
	DDRCTRL_DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk = 0x80000000
	// Bit DIS_AUTO_CTRLUPD.
	DDRCTRL_DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD = 0x80000000

	// DDRCTRL_DFIUPD1: DDRCTRL DFI update register 1
	// Position of DFI_T_CTRLUPD_INTERVAL_MAX_X1024 field.
	DDRCTRL_DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos = 0x0
	// Bit mask of DFI_T_CTRLUPD_INTERVAL_MAX_X1024 field.
	DDRCTRL_DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk = 0xff
	// Position of DFI_T_CTRLUPD_INTERVAL_MIN_X1024 field.
	DDRCTRL_DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos = 0x10
	// Bit mask of DFI_T_CTRLUPD_INTERVAL_MIN_X1024 field.
	DDRCTRL_DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk = 0xff0000

	// DDRCTRL_DFIUPD2: DDRCTRL DFI update register 2
	// Position of DFI_PHYUPD_EN field.
	DDRCTRL_DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos = 0x1f
	// Bit mask of DFI_PHYUPD_EN field.
	DDRCTRL_DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk = 0x80000000
	// Bit DFI_PHYUPD_EN.
	DDRCTRL_DDRCTRL_DFIUPD2_DFI_PHYUPD_EN = 0x80000000

	// DDRCTRL_DFIMISC: DDRCTRL DFI miscellaneous control register
	// Position of DFI_INIT_COMPLETE_EN field.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos = 0x0
	// Bit mask of DFI_INIT_COMPLETE_EN field.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk = 0x1
	// Bit DFI_INIT_COMPLETE_EN.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN = 0x1
	// Position of CTL_IDLE_EN field.
	DDRCTRL_DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos = 0x4
	// Bit mask of CTL_IDLE_EN field.
	DDRCTRL_DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk = 0x10
	// Bit CTL_IDLE_EN.
	DDRCTRL_DDRCTRL_DFIMISC_CTL_IDLE_EN = 0x10
	// Position of DFI_INIT_START field.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_INIT_START_Pos = 0x5
	// Bit mask of DFI_INIT_START field.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_INIT_START_Msk = 0x20
	// Bit DFI_INIT_START.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_INIT_START = 0x20
	// Position of DFI_FREQUENCY field.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos = 0x8
	// Bit mask of DFI_FREQUENCY field.
	DDRCTRL_DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk = 0x1f00

	// DDRCTRL_DFISTAT: DDRCTRL DFI status register
	// Position of DFI_INIT_COMPLETE field.
	DDRCTRL_DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos = 0x0
	// Bit mask of DFI_INIT_COMPLETE field.
	DDRCTRL_DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk = 0x1
	// Bit DFI_INIT_COMPLETE.
	DDRCTRL_DDRCTRL_DFISTAT_DFI_INIT_COMPLETE = 0x1
	// Position of DFI_LP_ACK field.
	DDRCTRL_DDRCTRL_DFISTAT_DFI_LP_ACK_Pos = 0x1
	// Bit mask of DFI_LP_ACK field.
	DDRCTRL_DDRCTRL_DFISTAT_DFI_LP_ACK_Msk = 0x2
	// Bit DFI_LP_ACK.
	DDRCTRL_DDRCTRL_DFISTAT_DFI_LP_ACK = 0x2

	// DDRCTRL_DFIPHYMSTR: DDRCTRL DFI PHY master register
	// Position of DFI_PHYMSTR_EN field.
	DDRCTRL_DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos = 0x0
	// Bit mask of DFI_PHYMSTR_EN field.
	DDRCTRL_DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk = 0x1
	// Bit DFI_PHYMSTR_EN.
	DDRCTRL_DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN = 0x1

	// DDRCTRL_ADDRMAP1: DDRCTRL address map register 1
	// Position of ADDRMAP_BANK_B0 field.
	DDRCTRL_DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos = 0x0
	// Bit mask of ADDRMAP_BANK_B0 field.
	DDRCTRL_DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk = 0x3f
	// Position of ADDRMAP_BANK_B1 field.
	DDRCTRL_DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos = 0x8
	// Bit mask of ADDRMAP_BANK_B1 field.
	DDRCTRL_DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk = 0x3f00
	// Position of ADDRMAP_BANK_B2 field.
	DDRCTRL_DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos = 0x10
	// Bit mask of ADDRMAP_BANK_B2 field.
	DDRCTRL_DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk = 0x3f0000

	// DDRCTRL_ADDRMAP2: DDRCTRL address map register 2
	// Position of ADDRMAP_COL_B2 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos = 0x0
	// Bit mask of ADDRMAP_COL_B2 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk = 0xf
	// Position of ADDRMAP_COL_B3 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos = 0x8
	// Bit mask of ADDRMAP_COL_B3 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk = 0xf00
	// Position of ADDRMAP_COL_B4 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos = 0x10
	// Bit mask of ADDRMAP_COL_B4 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk = 0xf0000
	// Position of ADDRMAP_COL_B5 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos = 0x18
	// Bit mask of ADDRMAP_COL_B5 field.
	DDRCTRL_DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk = 0xf000000

	// DDRCTRL_ADDRMAP3: DDRCTRL address map register 3
	// Position of ADDRMAP_COL_B6 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos = 0x0
	// Bit mask of ADDRMAP_COL_B6 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk = 0xf
	// Position of ADDRMAP_COL_B7 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos = 0x8
	// Bit mask of ADDRMAP_COL_B7 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk = 0x1f00
	// Position of ADDRMAP_COL_B8 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos = 0x10
	// Bit mask of ADDRMAP_COL_B8 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk = 0x1f0000
	// Position of ADDRMAP_COL_B9 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos = 0x18
	// Bit mask of ADDRMAP_COL_B9 field.
	DDRCTRL_DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk = 0x1f000000

	// DDRCTRL_ADDRMAP4: DDRCTRL address map register 4
	// Position of ADDRMAP_COL_B10 field.
	DDRCTRL_DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos = 0x0
	// Bit mask of ADDRMAP_COL_B10 field.
	DDRCTRL_DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk = 0x1f
	// Position of ADDRMAP_COL_B11 field.
	DDRCTRL_DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos = 0x8
	// Bit mask of ADDRMAP_COL_B11 field.
	DDRCTRL_DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk = 0x1f00

	// DDRCTRL_ADDRMAP5: DDRCTRL address map register 5
	// Position of ADDRMAP_ROW_B0 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos = 0x0
	// Bit mask of ADDRMAP_ROW_B0 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk = 0xf
	// Position of ADDRMAP_ROW_B1 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos = 0x8
	// Bit mask of ADDRMAP_ROW_B1 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk = 0xf00
	// Position of ADDRMAP_ROW_B2_10 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos = 0x10
	// Bit mask of ADDRMAP_ROW_B2_10 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk = 0xf0000
	// Position of ADDRMAP_ROW_B11 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos = 0x18
	// Bit mask of ADDRMAP_ROW_B11 field.
	DDRCTRL_DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk = 0xf000000

	// DDRCTRL_ADDRMAP6: DDRCTRL address register 6
	// Position of ADDRMAP_ROW_B12 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos = 0x0
	// Bit mask of ADDRMAP_ROW_B12 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk = 0xf
	// Position of ADDRMAP_ROW_B13 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos = 0x8
	// Bit mask of ADDRMAP_ROW_B13 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk = 0xf00
	// Position of ADDRMAP_ROW_B14 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos = 0x10
	// Bit mask of ADDRMAP_ROW_B14 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk = 0xf0000
	// Position of ADDRMAP_ROW_B15 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos = 0x18
	// Bit mask of ADDRMAP_ROW_B15 field.
	DDRCTRL_DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk = 0xf000000
	// Position of LPDDR3_6GB_12GB field.
	DDRCTRL_DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos = 0x1f
	// Bit mask of LPDDR3_6GB_12GB field.
	DDRCTRL_DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk = 0x80000000
	// Bit LPDDR3_6GB_12GB.
	DDRCTRL_DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB = 0x80000000

	// DDRCTRL_ADDRMAP9: DDRCTRL address map register 9
	// Position of ADDRMAP_ROW_B2 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos = 0x0
	// Bit mask of ADDRMAP_ROW_B2 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk = 0xf
	// Position of ADDRMAP_ROW_B3 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos = 0x8
	// Bit mask of ADDRMAP_ROW_B3 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk = 0xf00
	// Position of ADDRMAP_ROW_B4 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos = 0x10
	// Bit mask of ADDRMAP_ROW_B4 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk = 0xf0000
	// Position of ADDRMAP_ROW_B5 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos = 0x18
	// Bit mask of ADDRMAP_ROW_B5 field.
	DDRCTRL_DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk = 0xf000000

	// DDRCTRL_ADDRMAP10: DDRCTRL address map register 10
	// Position of ADDRMAP_ROW_B6 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos = 0x0
	// Bit mask of ADDRMAP_ROW_B6 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk = 0xf
	// Position of ADDRMAP_ROW_B7 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos = 0x8
	// Bit mask of ADDRMAP_ROW_B7 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk = 0xf00
	// Position of ADDRMAP_ROW_B8 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos = 0x10
	// Bit mask of ADDRMAP_ROW_B8 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk = 0xf0000
	// Position of ADDRMAP_ROW_B9 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos = 0x18
	// Bit mask of ADDRMAP_ROW_B9 field.
	DDRCTRL_DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk = 0xf000000

	// DDRCTRL_ADDRMAP11: DDRCTRL address map register 11
	// Position of ADDRMAP_ROW_B10 field.
	DDRCTRL_DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos = 0x0
	// Bit mask of ADDRMAP_ROW_B10 field.
	DDRCTRL_DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk = 0xf

	// DDRCTRL_ODTCFG: DDRCTRL ODT configuration register
	// Position of RD_ODT_DELAY field.
	DDRCTRL_DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos = 0x2
	// Bit mask of RD_ODT_DELAY field.
	DDRCTRL_DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk = 0x7c
	// Position of RD_ODT_HOLD field.
	DDRCTRL_DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos = 0x8
	// Bit mask of RD_ODT_HOLD field.
	DDRCTRL_DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk = 0xf00
	// Position of WR_ODT_DELAY field.
	DDRCTRL_DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos = 0x10
	// Bit mask of WR_ODT_DELAY field.
	DDRCTRL_DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk = 0x1f0000
	// Position of WR_ODT_HOLD field.
	DDRCTRL_DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos = 0x18
	// Bit mask of WR_ODT_HOLD field.
	DDRCTRL_DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk = 0xf000000

	// DDRCTRL_ODTMAP: DDRCTRL ODT/Rank map register
	// Position of RANK0_WR_ODT field.
	DDRCTRL_DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos = 0x0
	// Bit mask of RANK0_WR_ODT field.
	DDRCTRL_DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk = 0x1
	// Bit RANK0_WR_ODT.
	DDRCTRL_DDRCTRL_ODTMAP_RANK0_WR_ODT = 0x1
	// Position of RANK0_RD_ODT field.
	DDRCTRL_DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos = 0x4
	// Bit mask of RANK0_RD_ODT field.
	DDRCTRL_DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk = 0x10
	// Bit RANK0_RD_ODT.
	DDRCTRL_DDRCTRL_ODTMAP_RANK0_RD_ODT = 0x10

	// DDRCTRL_SCHED: DDRCTRL scheduler control register
	// Position of FORCE_LOW_PRI_N field.
	DDRCTRL_DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos = 0x0
	// Bit mask of FORCE_LOW_PRI_N field.
	DDRCTRL_DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk = 0x1
	// Bit FORCE_LOW_PRI_N.
	DDRCTRL_DDRCTRL_SCHED_FORCE_LOW_PRI_N = 0x1
	// Position of PREFER_WRITE field.
	DDRCTRL_DDRCTRL_SCHED_PREFER_WRITE_Pos = 0x1
	// Bit mask of PREFER_WRITE field.
	DDRCTRL_DDRCTRL_SCHED_PREFER_WRITE_Msk = 0x2
	// Bit PREFER_WRITE.
	DDRCTRL_DDRCTRL_SCHED_PREFER_WRITE = 0x2
	// Position of PAGECLOSE field.
	DDRCTRL_DDRCTRL_SCHED_PAGECLOSE_Pos = 0x2
	// Bit mask of PAGECLOSE field.
	DDRCTRL_DDRCTRL_SCHED_PAGECLOSE_Msk = 0x4
	// Bit PAGECLOSE.
	DDRCTRL_DDRCTRL_SCHED_PAGECLOSE = 0x4
	// Position of LPR_NUM_ENTRIES field.
	DDRCTRL_DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos = 0x8
	// Bit mask of LPR_NUM_ENTRIES field.
	DDRCTRL_DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk = 0xf00
	// Position of GO2CRITICAL_HYSTERESIS field.
	DDRCTRL_DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos = 0x10
	// Bit mask of GO2CRITICAL_HYSTERESIS field.
	DDRCTRL_DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk = 0xff0000
	// Position of RDWR_IDLE_GAP field.
	DDRCTRL_DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos = 0x18
	// Bit mask of RDWR_IDLE_GAP field.
	DDRCTRL_DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk = 0x7f000000

	// DDRCTRL_SCHED1: DDRCTRL scheduler control register 1
	// Position of PAGECLOSE_TIMER field.
	DDRCTRL_DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos = 0x0
	// Bit mask of PAGECLOSE_TIMER field.
	DDRCTRL_DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk = 0xff

	// DDRCTRL_PERFHPR1: DDRCTRL high priority read CAM register 1
	// Position of HPR_MAX_STARVE field.
	DDRCTRL_DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos = 0x0
	// Bit mask of HPR_MAX_STARVE field.
	DDRCTRL_DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk = 0xffff
	// Position of HPR_XACT_RUN_LENGTH field.
	DDRCTRL_DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos = 0x18
	// Bit mask of HPR_XACT_RUN_LENGTH field.
	DDRCTRL_DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk = 0xff000000

	// DDRCTRL_PERFLPR1: DDRCTRL low priority read CAM register 1
	// Position of LPR_MAX_STARVE field.
	DDRCTRL_DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos = 0x0
	// Bit mask of LPR_MAX_STARVE field.
	DDRCTRL_DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk = 0xffff
	// Position of LPR_XACT_RUN_LENGTH field.
	DDRCTRL_DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos = 0x18
	// Bit mask of LPR_XACT_RUN_LENGTH field.
	DDRCTRL_DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk = 0xff000000

	// DDRCTRL_PERFWR1: DDRCTRL write CAM register 1
	// Position of W_MAX_STARVE field.
	DDRCTRL_DDRCTRL_PERFWR1_W_MAX_STARVE_Pos = 0x0
	// Bit mask of W_MAX_STARVE field.
	DDRCTRL_DDRCTRL_PERFWR1_W_MAX_STARVE_Msk = 0xffff
	// Position of W_XACT_RUN_LENGTH field.
	DDRCTRL_DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos = 0x18
	// Bit mask of W_XACT_RUN_LENGTH field.
	DDRCTRL_DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk = 0xff000000

	// DDRCTRL_DBG0: DDRCTRL debug register 0
	// Position of DIS_WC field.
	DDRCTRL_DDRCTRL_DBG0_DIS_WC_Pos = 0x0
	// Bit mask of DIS_WC field.
	DDRCTRL_DDRCTRL_DBG0_DIS_WC_Msk = 0x1
	// Bit DIS_WC.
	DDRCTRL_DDRCTRL_DBG0_DIS_WC = 0x1
	// Position of DIS_COLLISION_PAGE_OPT field.
	DDRCTRL_DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos = 0x4
	// Bit mask of DIS_COLLISION_PAGE_OPT field.
	DDRCTRL_DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk = 0x10
	// Bit DIS_COLLISION_PAGE_OPT.
	DDRCTRL_DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT = 0x10

	// DDRCTRL_DBG1: DDRCTRL debug register 1
	// Position of DIS_DQ field.
	DDRCTRL_DDRCTRL_DBG1_DIS_DQ_Pos = 0x0
	// Bit mask of DIS_DQ field.
	DDRCTRL_DDRCTRL_DBG1_DIS_DQ_Msk = 0x1
	// Bit DIS_DQ.
	DDRCTRL_DDRCTRL_DBG1_DIS_DQ = 0x1
	// Position of DIS_HIF field.
	DDRCTRL_DDRCTRL_DBG1_DIS_HIF_Pos = 0x1
	// Bit mask of DIS_HIF field.
	DDRCTRL_DDRCTRL_DBG1_DIS_HIF_Msk = 0x2
	// Bit DIS_HIF.
	DDRCTRL_DDRCTRL_DBG1_DIS_HIF = 0x2

	// DDRCTRL_DBGCAM: DDRCTRL CAM debug register
	// Position of DBG_HPR_Q_DEPTH field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos = 0x0
	// Bit mask of DBG_HPR_Q_DEPTH field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk = 0x1f
	// Position of DBG_LPR_Q_DEPTH field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos = 0x8
	// Bit mask of DBG_LPR_Q_DEPTH field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk = 0x1f00
	// Position of DBG_W_Q_DEPTH field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos = 0x10
	// Bit mask of DBG_W_Q_DEPTH field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk = 0x1f0000
	// Position of DBG_STALL field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_STALL_Pos = 0x18
	// Bit mask of DBG_STALL field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_STALL_Msk = 0x1000000
	// Bit DBG_STALL.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_STALL = 0x1000000
	// Position of DBG_RD_Q_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos = 0x19
	// Bit mask of DBG_RD_Q_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk = 0x2000000
	// Bit DBG_RD_Q_EMPTY.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY = 0x2000000
	// Position of DBG_WR_Q_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos = 0x1a
	// Bit mask of DBG_WR_Q_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk = 0x4000000
	// Bit DBG_WR_Q_EMPTY.
	DDRCTRL_DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY = 0x4000000
	// Position of RD_DATA_PIPELINE_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos = 0x1c
	// Bit mask of RD_DATA_PIPELINE_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk = 0x10000000
	// Bit RD_DATA_PIPELINE_EMPTY.
	DDRCTRL_DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY = 0x10000000
	// Position of WR_DATA_PIPELINE_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos = 0x1d
	// Bit mask of WR_DATA_PIPELINE_EMPTY field.
	DDRCTRL_DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk = 0x20000000
	// Bit WR_DATA_PIPELINE_EMPTY.
	DDRCTRL_DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY = 0x20000000

	// DDRCTRL_DBGCMD: DDRCTRL command debug register
	// Position of RANK0_REFRESH field.
	DDRCTRL_DDRCTRL_DBGCMD_RANK0_REFRESH_Pos = 0x0
	// Bit mask of RANK0_REFRESH field.
	DDRCTRL_DDRCTRL_DBGCMD_RANK0_REFRESH_Msk = 0x1
	// Bit RANK0_REFRESH.
	DDRCTRL_DDRCTRL_DBGCMD_RANK0_REFRESH = 0x1
	// Position of ZQ_CALIB_SHORT field.
	DDRCTRL_DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos = 0x4
	// Bit mask of ZQ_CALIB_SHORT field.
	DDRCTRL_DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk = 0x10
	// Bit ZQ_CALIB_SHORT.
	DDRCTRL_DDRCTRL_DBGCMD_ZQ_CALIB_SHORT = 0x10
	// Position of CTRLUPD field.
	DDRCTRL_DDRCTRL_DBGCMD_CTRLUPD_Pos = 0x5
	// Bit mask of CTRLUPD field.
	DDRCTRL_DDRCTRL_DBGCMD_CTRLUPD_Msk = 0x20
	// Bit CTRLUPD.
	DDRCTRL_DDRCTRL_DBGCMD_CTRLUPD = 0x20

	// DDRCTRL_DBGSTAT: DDRCTRL status debug register
	// Position of RANK0_REFRESH_BUSY field.
	DDRCTRL_DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos = 0x0
	// Bit mask of RANK0_REFRESH_BUSY field.
	DDRCTRL_DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk = 0x1
	// Bit RANK0_REFRESH_BUSY.
	DDRCTRL_DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY = 0x1
	// Position of ZQ_CALIB_SHORT_BUSY field.
	DDRCTRL_DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos = 0x4
	// Bit mask of ZQ_CALIB_SHORT_BUSY field.
	DDRCTRL_DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk = 0x10
	// Bit ZQ_CALIB_SHORT_BUSY.
	DDRCTRL_DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY = 0x10
	// Position of CTRLUPD_BUSY field.
	DDRCTRL_DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos = 0x5
	// Bit mask of CTRLUPD_BUSY field.
	DDRCTRL_DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk = 0x20
	// Bit CTRLUPD_BUSY.
	DDRCTRL_DDRCTRL_DBGSTAT_CTRLUPD_BUSY = 0x20

	// DDRCTRL_SWCTL: DDRCTRL software register programming control enable
	// Position of SW_DONE field.
	DDRCTRL_DDRCTRL_SWCTL_SW_DONE_Pos = 0x0
	// Bit mask of SW_DONE field.
	DDRCTRL_DDRCTRL_SWCTL_SW_DONE_Msk = 0x1
	// Bit SW_DONE.
	DDRCTRL_DDRCTRL_SWCTL_SW_DONE = 0x1

	// DDRCTRL_SWSTAT: DDRCTRL software register programming control status
	// Position of SW_DONE_ACK field.
	DDRCTRL_DDRCTRL_SWSTAT_SW_DONE_ACK_Pos = 0x0
	// Bit mask of SW_DONE_ACK field.
	DDRCTRL_DDRCTRL_SWSTAT_SW_DONE_ACK_Msk = 0x1
	// Bit SW_DONE_ACK.
	DDRCTRL_DDRCTRL_SWSTAT_SW_DONE_ACK = 0x1

	// DDRCTRL_POISONCFG: AXI Poison configuration register common for all AXI ports.
	// Position of WR_POISON_SLVERR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos = 0x0
	// Bit mask of WR_POISON_SLVERR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk = 0x1
	// Bit WR_POISON_SLVERR_EN.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN = 0x1
	// Position of WR_POISON_INTR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos = 0x4
	// Bit mask of WR_POISON_INTR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk = 0x10
	// Bit WR_POISON_INTR_EN.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_INTR_EN = 0x10
	// Position of WR_POISON_INTR_CLR field.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos = 0x8
	// Bit mask of WR_POISON_INTR_CLR field.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk = 0x100
	// Bit WR_POISON_INTR_CLR.
	DDRCTRL_DDRCTRL_POISONCFG_WR_POISON_INTR_CLR = 0x100
	// Position of RD_POISON_SLVERR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos = 0x10
	// Bit mask of RD_POISON_SLVERR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk = 0x10000
	// Bit RD_POISON_SLVERR_EN.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN = 0x10000
	// Position of RD_POISON_INTR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos = 0x14
	// Bit mask of RD_POISON_INTR_EN field.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk = 0x100000
	// Bit RD_POISON_INTR_EN.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_INTR_EN = 0x100000
	// Position of RD_POISON_INTR_CLR field.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos = 0x18
	// Bit mask of RD_POISON_INTR_CLR field.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk = 0x1000000
	// Bit RD_POISON_INTR_CLR.
	DDRCTRL_DDRCTRL_POISONCFG_RD_POISON_INTR_CLR = 0x1000000

	// DDRCTRL_POISONSTAT: DDRCTRL AXI Poison status register
	// Position of WR_POISON_INTR_0 field.
	DDRCTRL_DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos = 0x0
	// Bit mask of WR_POISON_INTR_0 field.
	DDRCTRL_DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk = 0x1
	// Bit WR_POISON_INTR_0.
	DDRCTRL_DDRCTRL_POISONSTAT_WR_POISON_INTR_0 = 0x1
	// Position of WR_POISON_INTR_1 field.
	DDRCTRL_DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos = 0x1
	// Bit mask of WR_POISON_INTR_1 field.
	DDRCTRL_DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk = 0x2
	// Bit WR_POISON_INTR_1.
	DDRCTRL_DDRCTRL_POISONSTAT_WR_POISON_INTR_1 = 0x2
	// Position of RD_POISON_INTR_0 field.
	DDRCTRL_DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos = 0x10
	// Bit mask of RD_POISON_INTR_0 field.
	DDRCTRL_DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk = 0x10000
	// Bit RD_POISON_INTR_0.
	DDRCTRL_DDRCTRL_POISONSTAT_RD_POISON_INTR_0 = 0x10000
	// Position of RD_POISON_INTR_1 field.
	DDRCTRL_DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos = 0x11
	// Bit mask of RD_POISON_INTR_1 field.
	DDRCTRL_DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk = 0x20000
	// Bit RD_POISON_INTR_1.
	DDRCTRL_DDRCTRL_POISONSTAT_RD_POISON_INTR_1 = 0x20000

	// DDRCTRL_PSTAT: DDRCTRL port status register
	// Position of RD_PORT_BUSY_0 field.
	DDRCTRL_DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos = 0x0
	// Bit mask of RD_PORT_BUSY_0 field.
	DDRCTRL_DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk = 0x1
	// Bit RD_PORT_BUSY_0.
	DDRCTRL_DDRCTRL_PSTAT_RD_PORT_BUSY_0 = 0x1
	// Position of RD_PORT_BUSY_1 field.
	DDRCTRL_DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos = 0x1
	// Bit mask of RD_PORT_BUSY_1 field.
	DDRCTRL_DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk = 0x2
	// Bit RD_PORT_BUSY_1.
	DDRCTRL_DDRCTRL_PSTAT_RD_PORT_BUSY_1 = 0x2
	// Position of WR_PORT_BUSY_0 field.
	DDRCTRL_DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos = 0x10
	// Bit mask of WR_PORT_BUSY_0 field.
	DDRCTRL_DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk = 0x10000
	// Bit WR_PORT_BUSY_0.
	DDRCTRL_DDRCTRL_PSTAT_WR_PORT_BUSY_0 = 0x10000
	// Position of WR_PORT_BUSY_1 field.
	DDRCTRL_DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos = 0x11
	// Bit mask of WR_PORT_BUSY_1 field.
	DDRCTRL_DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk = 0x20000
	// Bit WR_PORT_BUSY_1.
	DDRCTRL_DDRCTRL_PSTAT_WR_PORT_BUSY_1 = 0x20000

	// DDRCTRL_PCCFG: DDRCTRL port common configuration register
	// Position of GO2CRITICAL_EN field.
	DDRCTRL_DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos = 0x0
	// Bit mask of GO2CRITICAL_EN field.
	DDRCTRL_DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk = 0x1
	// Bit GO2CRITICAL_EN.
	DDRCTRL_DDRCTRL_PCCFG_GO2CRITICAL_EN = 0x1
	// Position of PAGEMATCH_LIMIT field.
	DDRCTRL_DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos = 0x4
	// Bit mask of PAGEMATCH_LIMIT field.
	DDRCTRL_DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk = 0x10
	// Bit PAGEMATCH_LIMIT.
	DDRCTRL_DDRCTRL_PCCFG_PAGEMATCH_LIMIT = 0x10
	// Position of BL_EXP_MODE field.
	DDRCTRL_DDRCTRL_PCCFG_BL_EXP_MODE_Pos = 0x8
	// Bit mask of BL_EXP_MODE field.
	DDRCTRL_DDRCTRL_PCCFG_BL_EXP_MODE_Msk = 0x100
	// Bit BL_EXP_MODE.
	DDRCTRL_DDRCTRL_PCCFG_BL_EXP_MODE = 0x100

	// DDRCTRL_PCFGR_0: DDRCTRL port 0 configuration read register
	// Position of RD_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos = 0x0
	// Bit mask of RD_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk = 0x3ff
	// Position of RD_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos = 0xc
	// Bit mask of RD_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk = 0x1000
	// Bit RD_PORT_AGING_EN.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_AGING_EN = 0x1000
	// Position of RD_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos = 0xd
	// Bit mask of RD_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk = 0x2000
	// Bit RD_PORT_URGENT_EN.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN = 0x2000
	// Position of RD_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos = 0xe
	// Bit mask of RD_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk = 0x4000
	// Bit RD_PORT_PAGEMATCH_EN.
	DDRCTRL_DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN = 0x4000
	// Position of RDWR_ORDERED_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos = 0x10
	// Bit mask of RDWR_ORDERED_EN field.
	DDRCTRL_DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk = 0x10000
	// Bit RDWR_ORDERED_EN.
	DDRCTRL_DDRCTRL_PCFGR_0_RDWR_ORDERED_EN = 0x10000

	// DDRCTRL_PCFGW_0: DDRCTRL port 0 configuration write register
	// Position of WR_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos = 0x0
	// Bit mask of WR_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk = 0x3ff
	// Position of WR_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos = 0xc
	// Bit mask of WR_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk = 0x1000
	// Bit WR_PORT_AGING_EN.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_AGING_EN = 0x1000
	// Position of WR_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos = 0xd
	// Bit mask of WR_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk = 0x2000
	// Bit WR_PORT_URGENT_EN.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN = 0x2000
	// Position of WR_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos = 0xe
	// Bit mask of WR_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk = 0x4000
	// Bit WR_PORT_PAGEMATCH_EN.
	DDRCTRL_DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN = 0x4000

	// DDRCTRL_PCTRL_0: DDRCTRL port 0 control register
	// Position of PORT_EN field.
	DDRCTRL_DDRCTRL_PCTRL_0_PORT_EN_Pos = 0x0
	// Bit mask of PORT_EN field.
	DDRCTRL_DDRCTRL_PCTRL_0_PORT_EN_Msk = 0x1
	// Bit PORT_EN.
	DDRCTRL_DDRCTRL_PCTRL_0_PORT_EN = 0x1

	// DDRCTRL_PCFGQOS0_0: DDRCTRL port 0 read Q0S configuration register 0
	// Position of RQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos = 0x0
	// Bit mask of RQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk = 0xf
	// Position of RQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos = 0x8
	// Bit mask of RQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk = 0xf00
	// Position of RQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos = 0x10
	// Bit mask of RQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk = 0x30000
	// Position of RQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos = 0x14
	// Bit mask of RQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk = 0x300000
	// Position of RQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos = 0x18
	// Bit mask of RQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk = 0x3000000

	// DDRCTRL_PCFGQOS1_0: DDRCTRL port 0 read Q0S configuration register 1
	// Position of RQOS_MAP_TIMEOUTB field.
	DDRCTRL_DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos = 0x0
	// Bit mask of RQOS_MAP_TIMEOUTB field.
	DDRCTRL_DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk = 0x7ff
	// Position of RQOS_MAP_TIMEOUTR field.
	DDRCTRL_DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos = 0x10
	// Bit mask of RQOS_MAP_TIMEOUTR field.
	DDRCTRL_DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk = 0x7ff0000

	// DDRCTRL_PCFGWQOS0_0: DDRCTRL port 0 write Q0S configuration register 0
	// Position of WQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos = 0x0
	// Bit mask of WQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk = 0xf
	// Position of WQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos = 0x8
	// Bit mask of WQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk = 0xf00
	// Position of WQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos = 0x10
	// Bit mask of WQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk = 0x30000
	// Position of WQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos = 0x14
	// Bit mask of WQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk = 0x300000
	// Position of WQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos = 0x18
	// Bit mask of WQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk = 0x3000000

	// DDRCTRL_PCFGWQOS1_0: DDRCTRL port 0 write Q0S configuration register 1
	// Position of WQOS_MAP_TIMEOUT1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos = 0x0
	// Bit mask of WQOS_MAP_TIMEOUT1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk = 0x7ff
	// Position of WQOS_MAP_TIMEOUT2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos = 0x10
	// Bit mask of WQOS_MAP_TIMEOUT2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk = 0x7ff0000

	// DDRCTRL_PCFGR_1: DDRCTRL port 1 configuration read register
	// Position of RD_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos = 0x0
	// Bit mask of RD_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk = 0x3ff
	// Position of RD_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos = 0xc
	// Bit mask of RD_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk = 0x1000
	// Bit RD_PORT_AGING_EN.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_AGING_EN = 0x1000
	// Position of RD_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos = 0xd
	// Bit mask of RD_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk = 0x2000
	// Bit RD_PORT_URGENT_EN.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN = 0x2000
	// Position of RD_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos = 0xe
	// Bit mask of RD_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk = 0x4000
	// Bit RD_PORT_PAGEMATCH_EN.
	DDRCTRL_DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN = 0x4000
	// Position of RDWR_ORDERED_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos = 0x10
	// Bit mask of RDWR_ORDERED_EN field.
	DDRCTRL_DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk = 0x10000
	// Bit RDWR_ORDERED_EN.
	DDRCTRL_DDRCTRL_PCFGR_1_RDWR_ORDERED_EN = 0x10000

	// DDRCTRL_PCFGW_1: DDRCTRL port 1 configuration write register
	// Position of WR_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos = 0x0
	// Bit mask of WR_PORT_PRIORITY field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk = 0x3ff
	// Position of WR_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos = 0xc
	// Bit mask of WR_PORT_AGING_EN field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk = 0x1000
	// Bit WR_PORT_AGING_EN.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_AGING_EN = 0x1000
	// Position of WR_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos = 0xd
	// Bit mask of WR_PORT_URGENT_EN field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk = 0x2000
	// Bit WR_PORT_URGENT_EN.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN = 0x2000
	// Position of WR_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos = 0xe
	// Bit mask of WR_PORT_PAGEMATCH_EN field.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk = 0x4000
	// Bit WR_PORT_PAGEMATCH_EN.
	DDRCTRL_DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN = 0x4000

	// DDRCTRL_PCTRL_1: DDRCTRL port 1 control register
	// Position of PORT_EN field.
	DDRCTRL_DDRCTRL_PCTRL_1_PORT_EN_Pos = 0x0
	// Bit mask of PORT_EN field.
	DDRCTRL_DDRCTRL_PCTRL_1_PORT_EN_Msk = 0x1
	// Bit PORT_EN.
	DDRCTRL_DDRCTRL_PCTRL_1_PORT_EN = 0x1

	// DDRCTRL_PCFGQOS0_1: DDRCTRL port 1 read Q0S configuration register 0
	// Position of RQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos = 0x0
	// Bit mask of RQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk = 0xf
	// Position of RQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos = 0x8
	// Bit mask of RQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk = 0xf00
	// Position of RQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos = 0x10
	// Bit mask of RQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk = 0x30000
	// Position of RQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos = 0x14
	// Bit mask of RQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk = 0x300000
	// Position of RQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos = 0x18
	// Bit mask of RQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk = 0x3000000

	// DDRCTRL_PCFGQOS1_1: DDRCTRL port 1 read Q0S configuration register 1
	// Position of RQOS_MAP_TIMEOUTB field.
	DDRCTRL_DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos = 0x0
	// Bit mask of RQOS_MAP_TIMEOUTB field.
	DDRCTRL_DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk = 0x7ff
	// Position of RQOS_MAP_TIMEOUTR field.
	DDRCTRL_DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos = 0x10
	// Bit mask of RQOS_MAP_TIMEOUTR field.
	DDRCTRL_DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk = 0x7ff0000

	// DDRCTRL_PCFGWQOS0_1: DDRCTRL port 1 write Q0S configuration register 0
	// Position of WQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos = 0x0
	// Bit mask of WQOS_MAP_LEVEL1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk = 0xf
	// Position of WQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos = 0x8
	// Bit mask of WQOS_MAP_LEVEL2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk = 0xf00
	// Position of WQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos = 0x10
	// Bit mask of WQOS_MAP_REGION0 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk = 0x30000
	// Position of WQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos = 0x14
	// Bit mask of WQOS_MAP_REGION1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk = 0x300000
	// Position of WQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos = 0x18
	// Bit mask of WQOS_MAP_REGION2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk = 0x3000000

	// DDRCTRL_PCFGWQOS1_1: DDRCTRL port 1 write Q0S configuration register 1
	// Position of WQOS_MAP_TIMEOUT1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos = 0x0
	// Bit mask of WQOS_MAP_TIMEOUT1 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk = 0x7ff
	// Position of WQOS_MAP_TIMEOUT2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos = 0x10
	// Bit mask of WQOS_MAP_TIMEOUT2 field.
	DDRCTRL_DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk = 0x7ff0000
)

// Bitfields for DDRPERFM: DDRPERFM
const (
	// DDRPERFM_CTL: Write-only register. A read request returns all zeros.
	// Position of START field.
	DDRPERFM_DDRPERFM_CTL_START_Pos = 0x0
	// Bit mask of START field.
	DDRPERFM_DDRPERFM_CTL_START_Msk = 0x1
	// Bit START.
	DDRPERFM_DDRPERFM_CTL_START = 0x1
	// Position of STOP field.
	DDRPERFM_DDRPERFM_CTL_STOP_Pos = 0x1
	// Bit mask of STOP field.
	DDRPERFM_DDRPERFM_CTL_STOP_Msk = 0x2
	// Bit STOP.
	DDRPERFM_DDRPERFM_CTL_STOP = 0x2

	// DDRPERFM_CFG: DDRPERFM configurationl register
	// Position of EN field.
	DDRPERFM_DDRPERFM_CFG_EN_Pos = 0x0
	// Bit mask of EN field.
	DDRPERFM_DDRPERFM_CFG_EN_Msk = 0xf
	// Position of SEL field.
	DDRPERFM_DDRPERFM_CFG_SEL_Pos = 0x10
	// Bit mask of SEL field.
	DDRPERFM_DDRPERFM_CFG_SEL_Msk = 0x30000

	// DDRPERFM_STATUS: DDRPERFM status register
	// Position of COVF field.
	DDRPERFM_DDRPERFM_STATUS_COVF_Pos = 0x0
	// Bit mask of COVF field.
	DDRPERFM_DDRPERFM_STATUS_COVF_Msk = 0xf
	// Position of BUSY field.
	DDRPERFM_DDRPERFM_STATUS_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	DDRPERFM_DDRPERFM_STATUS_BUSY_Msk = 0x10000
	// Bit BUSY.
	DDRPERFM_DDRPERFM_STATUS_BUSY = 0x10000
	// Position of TOVF field.
	DDRPERFM_DDRPERFM_STATUS_TOVF_Pos = 0x1f
	// Bit mask of TOVF field.
	DDRPERFM_DDRPERFM_STATUS_TOVF_Msk = 0x80000000
	// Bit TOVF.
	DDRPERFM_DDRPERFM_STATUS_TOVF = 0x80000000

	// DDRPERFM_CCR: Write-only register. A read request returns all zeros
	// Position of CCLR field.
	DDRPERFM_DDRPERFM_CCR_CCLR_Pos = 0x0
	// Bit mask of CCLR field.
	DDRPERFM_DDRPERFM_CCR_CCLR_Msk = 0xf
	// Position of TCLR field.
	DDRPERFM_DDRPERFM_CCR_TCLR_Pos = 0x1f
	// Bit mask of TCLR field.
	DDRPERFM_DDRPERFM_CCR_TCLR_Msk = 0x80000000
	// Bit TCLR.
	DDRPERFM_DDRPERFM_CCR_TCLR = 0x80000000

	// DDRPERFM_IER: DDRPERFM interrupt enable register
	// Position of OVFIE field.
	DDRPERFM_DDRPERFM_IER_OVFIE_Pos = 0x0
	// Bit mask of OVFIE field.
	DDRPERFM_DDRPERFM_IER_OVFIE_Msk = 0x1
	// Bit OVFIE.
	DDRPERFM_DDRPERFM_IER_OVFIE = 0x1

	// DDRPERFM_ISR: DDRPERFM interrupt status register
	// Position of OVFF field.
	DDRPERFM_DDRPERFM_ISR_OVFF_Pos = 0x0
	// Bit mask of OVFF field.
	DDRPERFM_DDRPERFM_ISR_OVFF_Msk = 0x1
	// Bit OVFF.
	DDRPERFM_DDRPERFM_ISR_OVFF = 0x1

	// DDRPERFM_ICR: Write-only register. A read request returns all zeros
	// Position of OVF field.
	DDRPERFM_DDRPERFM_ICR_OVF_Pos = 0x0
	// Bit mask of OVF field.
	DDRPERFM_DDRPERFM_ICR_OVF_Msk = 0x1
	// Bit OVF.
	DDRPERFM_DDRPERFM_ICR_OVF = 0x1

	// DDRPERFM_TCNT: DDRPERFM time counter register
	// Position of CNT field.
	DDRPERFM_DDRPERFM_TCNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	DDRPERFM_DDRPERFM_TCNT_CNT_Msk = 0xffffffff

	// DDRPERFM_CNT0: DDRPERFM event counter 0 register
	// Position of CNT field.
	DDRPERFM_DDRPERFM_CNT0_CNT_Pos = 0x0
	// Bit mask of CNT field.
	DDRPERFM_DDRPERFM_CNT0_CNT_Msk = 0xffffffff

	// DDRPERFM_CNT1: DDRPERFM event counter 1 register
	// Position of CNT field.
	DDRPERFM_DDRPERFM_CNT1_CNT_Pos = 0x0
	// Bit mask of CNT field.
	DDRPERFM_DDRPERFM_CNT1_CNT_Msk = 0xffffffff

	// DDRPERFM_CNT2: DDRPERFM event counter 2 register
	// Position of CNT field.
	DDRPERFM_DDRPERFM_CNT2_CNT_Pos = 0x0
	// Bit mask of CNT field.
	DDRPERFM_DDRPERFM_CNT2_CNT_Msk = 0xffffffff

	// DDRPERFM_CNT3: DDRPERFM event counter 3 register
	// Position of CNT field.
	DDRPERFM_DDRPERFM_CNT3_CNT_Pos = 0x0
	// Bit mask of CNT field.
	DDRPERFM_DDRPERFM_CNT3_CNT_Msk = 0xffffffff

	// DDRPERFM_HWCFG: DDRPERFM hardware configuration register
	// Position of NCNT field.
	DDRPERFM_DDRPERFM_HWCFG_NCNT_Pos = 0x0
	// Bit mask of NCNT field.
	DDRPERFM_DDRPERFM_HWCFG_NCNT_Msk = 0xf

	// DDRPERFM_VER: DDRPERFM version register
	// Position of MINREV field.
	DDRPERFM_DDRPERFM_VER_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DDRPERFM_DDRPERFM_VER_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DDRPERFM_DDRPERFM_VER_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DDRPERFM_DDRPERFM_VER_MAJREV_Msk = 0xf0

	// DDRPERFM_ID: DDRPERFM ID register
	// Position of ID field.
	DDRPERFM_DDRPERFM_ID_ID_Pos = 0x0
	// Bit mask of ID field.
	DDRPERFM_DDRPERFM_ID_ID_Msk = 0xffffffff

	// DDRPERFM_SID: DDRPERFM magic ID register
	// Position of SID field.
	DDRPERFM_DDRPERFM_SID_SID_Pos = 0x0
	// Bit mask of SID field.
	DDRPERFM_DDRPERFM_SID_SID_Msk = 0xffffffff
)

// Bitfields for DDRPHYC: DDRPHYC
const (
	// DDRPHYC_RIDR: DDRPHYC revision ID register
	// Position of PUBMNR field.
	DDRPHYC_DDRPHYC_RIDR_PUBMNR_Pos = 0x0
	// Bit mask of PUBMNR field.
	DDRPHYC_DDRPHYC_RIDR_PUBMNR_Msk = 0xf
	// Position of PUBMDR field.
	DDRPHYC_DDRPHYC_RIDR_PUBMDR_Pos = 0x4
	// Bit mask of PUBMDR field.
	DDRPHYC_DDRPHYC_RIDR_PUBMDR_Msk = 0xf0
	// Position of PUBMJR field.
	DDRPHYC_DDRPHYC_RIDR_PUBMJR_Pos = 0x8
	// Bit mask of PUBMJR field.
	DDRPHYC_DDRPHYC_RIDR_PUBMJR_Msk = 0xf00
	// Position of PHYMNR field.
	DDRPHYC_DDRPHYC_RIDR_PHYMNR_Pos = 0xc
	// Bit mask of PHYMNR field.
	DDRPHYC_DDRPHYC_RIDR_PHYMNR_Msk = 0xf000
	// Position of PHYMDR field.
	DDRPHYC_DDRPHYC_RIDR_PHYMDR_Pos = 0x10
	// Bit mask of PHYMDR field.
	DDRPHYC_DDRPHYC_RIDR_PHYMDR_Msk = 0xf0000
	// Position of PHYMJR field.
	DDRPHYC_DDRPHYC_RIDR_PHYMJR_Pos = 0x14
	// Bit mask of PHYMJR field.
	DDRPHYC_DDRPHYC_RIDR_PHYMJR_Msk = 0xf00000
	// Position of UDRID field.
	DDRPHYC_DDRPHYC_RIDR_UDRID_Pos = 0x18
	// Bit mask of UDRID field.
	DDRPHYC_DDRPHYC_RIDR_UDRID_Msk = 0xff000000

	// DDRPHYC_PIR: DDRPHYC PHY initialization register
	// Position of INIT field.
	DDRPHYC_DDRPHYC_PIR_INIT_Pos = 0x0
	// Bit mask of INIT field.
	DDRPHYC_DDRPHYC_PIR_INIT_Msk = 0x1
	// Bit INIT.
	DDRPHYC_DDRPHYC_PIR_INIT = 0x1
	// Position of DLLSRST field.
	DDRPHYC_DDRPHYC_PIR_DLLSRST_Pos = 0x1
	// Bit mask of DLLSRST field.
	DDRPHYC_DDRPHYC_PIR_DLLSRST_Msk = 0x2
	// Bit DLLSRST.
	DDRPHYC_DDRPHYC_PIR_DLLSRST = 0x2
	// Position of DLLLOCK field.
	DDRPHYC_DDRPHYC_PIR_DLLLOCK_Pos = 0x2
	// Bit mask of DLLLOCK field.
	DDRPHYC_DDRPHYC_PIR_DLLLOCK_Msk = 0x4
	// Bit DLLLOCK.
	DDRPHYC_DDRPHYC_PIR_DLLLOCK = 0x4
	// Position of ZCAL field.
	DDRPHYC_DDRPHYC_PIR_ZCAL_Pos = 0x3
	// Bit mask of ZCAL field.
	DDRPHYC_DDRPHYC_PIR_ZCAL_Msk = 0x8
	// Bit ZCAL.
	DDRPHYC_DDRPHYC_PIR_ZCAL = 0x8
	// Position of ITMSRST field.
	DDRPHYC_DDRPHYC_PIR_ITMSRST_Pos = 0x4
	// Bit mask of ITMSRST field.
	DDRPHYC_DDRPHYC_PIR_ITMSRST_Msk = 0x10
	// Bit ITMSRST.
	DDRPHYC_DDRPHYC_PIR_ITMSRST = 0x10
	// Position of DRAMRST field.
	DDRPHYC_DDRPHYC_PIR_DRAMRST_Pos = 0x5
	// Bit mask of DRAMRST field.
	DDRPHYC_DDRPHYC_PIR_DRAMRST_Msk = 0x20
	// Bit DRAMRST.
	DDRPHYC_DDRPHYC_PIR_DRAMRST = 0x20
	// Position of DRAMINIT field.
	DDRPHYC_DDRPHYC_PIR_DRAMINIT_Pos = 0x6
	// Bit mask of DRAMINIT field.
	DDRPHYC_DDRPHYC_PIR_DRAMINIT_Msk = 0x40
	// Bit DRAMINIT.
	DDRPHYC_DDRPHYC_PIR_DRAMINIT = 0x40
	// Position of QSTRN field.
	DDRPHYC_DDRPHYC_PIR_QSTRN_Pos = 0x7
	// Bit mask of QSTRN field.
	DDRPHYC_DDRPHYC_PIR_QSTRN_Msk = 0x80
	// Bit QSTRN.
	DDRPHYC_DDRPHYC_PIR_QSTRN = 0x80
	// Position of RVTRN field.
	DDRPHYC_DDRPHYC_PIR_RVTRN_Pos = 0x8
	// Bit mask of RVTRN field.
	DDRPHYC_DDRPHYC_PIR_RVTRN_Msk = 0x100
	// Bit RVTRN.
	DDRPHYC_DDRPHYC_PIR_RVTRN = 0x100
	// Position of ICPC field.
	DDRPHYC_DDRPHYC_PIR_ICPC_Pos = 0x10
	// Bit mask of ICPC field.
	DDRPHYC_DDRPHYC_PIR_ICPC_Msk = 0x10000
	// Bit ICPC.
	DDRPHYC_DDRPHYC_PIR_ICPC = 0x10000
	// Position of DLLBYP field.
	DDRPHYC_DDRPHYC_PIR_DLLBYP_Pos = 0x11
	// Bit mask of DLLBYP field.
	DDRPHYC_DDRPHYC_PIR_DLLBYP_Msk = 0x20000
	// Bit DLLBYP.
	DDRPHYC_DDRPHYC_PIR_DLLBYP = 0x20000
	// Position of CTLDINIT field.
	DDRPHYC_DDRPHYC_PIR_CTLDINIT_Pos = 0x12
	// Bit mask of CTLDINIT field.
	DDRPHYC_DDRPHYC_PIR_CTLDINIT_Msk = 0x40000
	// Bit CTLDINIT.
	DDRPHYC_DDRPHYC_PIR_CTLDINIT = 0x40000
	// Position of CLRSR field.
	DDRPHYC_DDRPHYC_PIR_CLRSR_Pos = 0x1c
	// Bit mask of CLRSR field.
	DDRPHYC_DDRPHYC_PIR_CLRSR_Msk = 0x10000000
	// Bit CLRSR.
	DDRPHYC_DDRPHYC_PIR_CLRSR = 0x10000000
	// Position of LOCKBYP field.
	DDRPHYC_DDRPHYC_PIR_LOCKBYP_Pos = 0x1d
	// Bit mask of LOCKBYP field.
	DDRPHYC_DDRPHYC_PIR_LOCKBYP_Msk = 0x20000000
	// Bit LOCKBYP.
	DDRPHYC_DDRPHYC_PIR_LOCKBYP = 0x20000000
	// Position of ZCALBYP field.
	DDRPHYC_DDRPHYC_PIR_ZCALBYP_Pos = 0x1e
	// Bit mask of ZCALBYP field.
	DDRPHYC_DDRPHYC_PIR_ZCALBYP_Msk = 0x40000000
	// Bit ZCALBYP.
	DDRPHYC_DDRPHYC_PIR_ZCALBYP = 0x40000000
	// Position of INITBYP field.
	DDRPHYC_DDRPHYC_PIR_INITBYP_Pos = 0x1f
	// Bit mask of INITBYP field.
	DDRPHYC_DDRPHYC_PIR_INITBYP_Msk = 0x80000000
	// Bit INITBYP.
	DDRPHYC_DDRPHYC_PIR_INITBYP = 0x80000000

	// DDRPHYC_PGCR: DDRPHYC PHY global control register
	// Position of ITMDMD field.
	DDRPHYC_DDRPHYC_PGCR_ITMDMD_Pos = 0x0
	// Bit mask of ITMDMD field.
	DDRPHYC_DDRPHYC_PGCR_ITMDMD_Msk = 0x1
	// Bit ITMDMD.
	DDRPHYC_DDRPHYC_PGCR_ITMDMD = 0x1
	// Position of DQSCFG field.
	DDRPHYC_DDRPHYC_PGCR_DQSCFG_Pos = 0x1
	// Bit mask of DQSCFG field.
	DDRPHYC_DDRPHYC_PGCR_DQSCFG_Msk = 0x2
	// Bit DQSCFG.
	DDRPHYC_DDRPHYC_PGCR_DQSCFG = 0x2
	// Position of DFTCMP field.
	DDRPHYC_DDRPHYC_PGCR_DFTCMP_Pos = 0x2
	// Bit mask of DFTCMP field.
	DDRPHYC_DDRPHYC_PGCR_DFTCMP_Msk = 0x4
	// Bit DFTCMP.
	DDRPHYC_DDRPHYC_PGCR_DFTCMP = 0x4
	// Position of DFTLMT field.
	DDRPHYC_DDRPHYC_PGCR_DFTLMT_Pos = 0x3
	// Bit mask of DFTLMT field.
	DDRPHYC_DDRPHYC_PGCR_DFTLMT_Msk = 0x18
	// Position of DTOSEL field.
	DDRPHYC_DDRPHYC_PGCR_DTOSEL_Pos = 0x5
	// Bit mask of DTOSEL field.
	DDRPHYC_DDRPHYC_PGCR_DTOSEL_Msk = 0x1e0
	// Position of CKEN field.
	DDRPHYC_DDRPHYC_PGCR_CKEN_Pos = 0x9
	// Bit mask of CKEN field.
	DDRPHYC_DDRPHYC_PGCR_CKEN_Msk = 0xe00
	// Position of CKDV field.
	DDRPHYC_DDRPHYC_PGCR_CKDV_Pos = 0xc
	// Bit mask of CKDV field.
	DDRPHYC_DDRPHYC_PGCR_CKDV_Msk = 0x3000
	// Position of CKINV field.
	DDRPHYC_DDRPHYC_PGCR_CKINV_Pos = 0xe
	// Bit mask of CKINV field.
	DDRPHYC_DDRPHYC_PGCR_CKINV_Msk = 0x4000
	// Bit CKINV.
	DDRPHYC_DDRPHYC_PGCR_CKINV = 0x4000
	// Position of IOLB field.
	DDRPHYC_DDRPHYC_PGCR_IOLB_Pos = 0xf
	// Bit mask of IOLB field.
	DDRPHYC_DDRPHYC_PGCR_IOLB_Msk = 0x8000
	// Bit IOLB.
	DDRPHYC_DDRPHYC_PGCR_IOLB = 0x8000
	// Position of IODDRM field.
	DDRPHYC_DDRPHYC_PGCR_IODDRM_Pos = 0x10
	// Bit mask of IODDRM field.
	DDRPHYC_DDRPHYC_PGCR_IODDRM_Msk = 0x30000
	// Position of RANKEN field.
	DDRPHYC_DDRPHYC_PGCR_RANKEN_Pos = 0x12
	// Bit mask of RANKEN field.
	DDRPHYC_DDRPHYC_PGCR_RANKEN_Msk = 0x3c0000
	// Position of ZKSEL field.
	DDRPHYC_DDRPHYC_PGCR_ZKSEL_Pos = 0x16
	// Bit mask of ZKSEL field.
	DDRPHYC_DDRPHYC_PGCR_ZKSEL_Msk = 0xc00000
	// Position of PDDISDX field.
	DDRPHYC_DDRPHYC_PGCR_PDDISDX_Pos = 0x18
	// Bit mask of PDDISDX field.
	DDRPHYC_DDRPHYC_PGCR_PDDISDX_Msk = 0x1000000
	// Bit PDDISDX.
	DDRPHYC_DDRPHYC_PGCR_PDDISDX = 0x1000000
	// Position of RFSHDT field.
	DDRPHYC_DDRPHYC_PGCR_RFSHDT_Pos = 0x19
	// Bit mask of RFSHDT field.
	DDRPHYC_DDRPHYC_PGCR_RFSHDT_Msk = 0x1e000000
	// Position of LBDQSS field.
	DDRPHYC_DDRPHYC_PGCR_LBDQSS_Pos = 0x1d
	// Bit mask of LBDQSS field.
	DDRPHYC_DDRPHYC_PGCR_LBDQSS_Msk = 0x20000000
	// Bit LBDQSS.
	DDRPHYC_DDRPHYC_PGCR_LBDQSS = 0x20000000
	// Position of LBGDQS field.
	DDRPHYC_DDRPHYC_PGCR_LBGDQS_Pos = 0x1e
	// Bit mask of LBGDQS field.
	DDRPHYC_DDRPHYC_PGCR_LBGDQS_Msk = 0x40000000
	// Bit LBGDQS.
	DDRPHYC_DDRPHYC_PGCR_LBGDQS = 0x40000000
	// Position of LBMODE field.
	DDRPHYC_DDRPHYC_PGCR_LBMODE_Pos = 0x1f
	// Bit mask of LBMODE field.
	DDRPHYC_DDRPHYC_PGCR_LBMODE_Msk = 0x80000000
	// Bit LBMODE.
	DDRPHYC_DDRPHYC_PGCR_LBMODE = 0x80000000

	// DDRPHYC_PGSR: DDRPHYC PHY global status register
	// Position of IDONE field.
	DDRPHYC_DDRPHYC_PGSR_IDONE_Pos = 0x0
	// Bit mask of IDONE field.
	DDRPHYC_DDRPHYC_PGSR_IDONE_Msk = 0x1
	// Bit IDONE.
	DDRPHYC_DDRPHYC_PGSR_IDONE = 0x1
	// Position of DLDONE field.
	DDRPHYC_DDRPHYC_PGSR_DLDONE_Pos = 0x1
	// Bit mask of DLDONE field.
	DDRPHYC_DDRPHYC_PGSR_DLDONE_Msk = 0x2
	// Bit DLDONE.
	DDRPHYC_DDRPHYC_PGSR_DLDONE = 0x2
	// Position of ZCDDONE field.
	DDRPHYC_DDRPHYC_PGSR_ZCDDONE_Pos = 0x2
	// Bit mask of ZCDDONE field.
	DDRPHYC_DDRPHYC_PGSR_ZCDDONE_Msk = 0x4
	// Bit ZCDDONE.
	DDRPHYC_DDRPHYC_PGSR_ZCDDONE = 0x4
	// Position of DIDONE field.
	DDRPHYC_DDRPHYC_PGSR_DIDONE_Pos = 0x3
	// Bit mask of DIDONE field.
	DDRPHYC_DDRPHYC_PGSR_DIDONE_Msk = 0x8
	// Bit DIDONE.
	DDRPHYC_DDRPHYC_PGSR_DIDONE = 0x8
	// Position of DTDONE field.
	DDRPHYC_DDRPHYC_PGSR_DTDONE_Pos = 0x4
	// Bit mask of DTDONE field.
	DDRPHYC_DDRPHYC_PGSR_DTDONE_Msk = 0x10
	// Bit DTDONE.
	DDRPHYC_DDRPHYC_PGSR_DTDONE = 0x10
	// Position of DTERR field.
	DDRPHYC_DDRPHYC_PGSR_DTERR_Pos = 0x5
	// Bit mask of DTERR field.
	DDRPHYC_DDRPHYC_PGSR_DTERR_Msk = 0x20
	// Bit DTERR.
	DDRPHYC_DDRPHYC_PGSR_DTERR = 0x20
	// Position of DTIERR field.
	DDRPHYC_DDRPHYC_PGSR_DTIERR_Pos = 0x6
	// Bit mask of DTIERR field.
	DDRPHYC_DDRPHYC_PGSR_DTIERR_Msk = 0x40
	// Bit DTIERR.
	DDRPHYC_DDRPHYC_PGSR_DTIERR = 0x40
	// Position of DFTERR field.
	DDRPHYC_DDRPHYC_PGSR_DFTERR_Pos = 0x7
	// Bit mask of DFTERR field.
	DDRPHYC_DDRPHYC_PGSR_DFTERR_Msk = 0x80
	// Bit DFTERR.
	DDRPHYC_DDRPHYC_PGSR_DFTERR = 0x80
	// Position of RVERR field.
	DDRPHYC_DDRPHYC_PGSR_RVERR_Pos = 0x8
	// Bit mask of RVERR field.
	DDRPHYC_DDRPHYC_PGSR_RVERR_Msk = 0x100
	// Bit RVERR.
	DDRPHYC_DDRPHYC_PGSR_RVERR = 0x100
	// Position of RVEIRR field.
	DDRPHYC_DDRPHYC_PGSR_RVEIRR_Pos = 0x9
	// Bit mask of RVEIRR field.
	DDRPHYC_DDRPHYC_PGSR_RVEIRR_Msk = 0x200
	// Bit RVEIRR.
	DDRPHYC_DDRPHYC_PGSR_RVEIRR = 0x200
	// Position of TQ field.
	DDRPHYC_DDRPHYC_PGSR_TQ_Pos = 0x1f
	// Bit mask of TQ field.
	DDRPHYC_DDRPHYC_PGSR_TQ_Msk = 0x80000000
	// Bit TQ.
	DDRPHYC_DDRPHYC_PGSR_TQ = 0x80000000

	// DDRPHYC_DLLGCR: DDRPHYC DDR global control register
	// Position of DRES field.
	DDRPHYC_DDRPHYC_DLLGCR_DRES_Pos = 0x0
	// Bit mask of DRES field.
	DDRPHYC_DDRPHYC_DLLGCR_DRES_Msk = 0x3
	// Position of IPUMP field.
	DDRPHYC_DDRPHYC_DLLGCR_IPUMP_Pos = 0x2
	// Bit mask of IPUMP field.
	DDRPHYC_DDRPHYC_DLLGCR_IPUMP_Msk = 0x1c
	// Position of TESTEN field.
	DDRPHYC_DDRPHYC_DLLGCR_TESTEN_Pos = 0x5
	// Bit mask of TESTEN field.
	DDRPHYC_DDRPHYC_DLLGCR_TESTEN_Msk = 0x20
	// Bit TESTEN.
	DDRPHYC_DDRPHYC_DLLGCR_TESTEN = 0x20
	// Position of DTC field.
	DDRPHYC_DDRPHYC_DLLGCR_DTC_Pos = 0x6
	// Bit mask of DTC field.
	DDRPHYC_DDRPHYC_DLLGCR_DTC_Msk = 0x1c0
	// Position of ATC field.
	DDRPHYC_DDRPHYC_DLLGCR_ATC_Pos = 0x9
	// Bit mask of ATC field.
	DDRPHYC_DDRPHYC_DLLGCR_ATC_Msk = 0x600
	// Position of TESTSW field.
	DDRPHYC_DDRPHYC_DLLGCR_TESTSW_Pos = 0xb
	// Bit mask of TESTSW field.
	DDRPHYC_DDRPHYC_DLLGCR_TESTSW_Msk = 0x800
	// Bit TESTSW.
	DDRPHYC_DDRPHYC_DLLGCR_TESTSW = 0x800
	// Position of MBIAS field.
	DDRPHYC_DDRPHYC_DLLGCR_MBIAS_Pos = 0xc
	// Bit mask of MBIAS field.
	DDRPHYC_DDRPHYC_DLLGCR_MBIAS_Msk = 0xff000
	// Position of SBIAS2_0 field.
	DDRPHYC_DDRPHYC_DLLGCR_SBIAS2_0_Pos = 0x14
	// Bit mask of SBIAS2_0 field.
	DDRPHYC_DDRPHYC_DLLGCR_SBIAS2_0_Msk = 0x700000
	// Position of BPS200 field.
	DDRPHYC_DDRPHYC_DLLGCR_BPS200_Pos = 0x17
	// Bit mask of BPS200 field.
	DDRPHYC_DDRPHYC_DLLGCR_BPS200_Msk = 0x800000
	// Bit BPS200.
	DDRPHYC_DDRPHYC_DLLGCR_BPS200 = 0x800000
	// Position of SBIAS5_3 field.
	DDRPHYC_DDRPHYC_DLLGCR_SBIAS5_3_Pos = 0x18
	// Bit mask of SBIAS5_3 field.
	DDRPHYC_DDRPHYC_DLLGCR_SBIAS5_3_Msk = 0x7000000
	// Position of FDTRMSL field.
	DDRPHYC_DDRPHYC_DLLGCR_FDTRMSL_Pos = 0x1b
	// Bit mask of FDTRMSL field.
	DDRPHYC_DDRPHYC_DLLGCR_FDTRMSL_Msk = 0x18000000
	// Position of LOCKDET field.
	DDRPHYC_DDRPHYC_DLLGCR_LOCKDET_Pos = 0x1d
	// Bit mask of LOCKDET field.
	DDRPHYC_DDRPHYC_DLLGCR_LOCKDET_Msk = 0x20000000
	// Bit LOCKDET.
	DDRPHYC_DDRPHYC_DLLGCR_LOCKDET = 0x20000000
	// Position of DLLRSVD2 field.
	DDRPHYC_DDRPHYC_DLLGCR_DLLRSVD2_Pos = 0x1e
	// Bit mask of DLLRSVD2 field.
	DDRPHYC_DDRPHYC_DLLGCR_DLLRSVD2_Msk = 0xc0000000

	// DDRPHYC_ACDLLCR: DDRPHYC AC DLL control register
	// Position of MFBDLY field.
	DDRPHYC_DDRPHYC_ACDLLCR_MFBDLY_Pos = 0x6
	// Bit mask of MFBDLY field.
	DDRPHYC_DDRPHYC_ACDLLCR_MFBDLY_Msk = 0x1c0
	// Position of MFWDLY field.
	DDRPHYC_DDRPHYC_ACDLLCR_MFWDLY_Pos = 0x9
	// Bit mask of MFWDLY field.
	DDRPHYC_DDRPHYC_ACDLLCR_MFWDLY_Msk = 0xe00
	// Position of ATESTEN field.
	DDRPHYC_DDRPHYC_ACDLLCR_ATESTEN_Pos = 0x12
	// Bit mask of ATESTEN field.
	DDRPHYC_DDRPHYC_ACDLLCR_ATESTEN_Msk = 0x40000
	// Bit ATESTEN.
	DDRPHYC_DDRPHYC_ACDLLCR_ATESTEN = 0x40000
	// Position of DLLSRST field.
	DDRPHYC_DDRPHYC_ACDLLCR_DLLSRST_Pos = 0x1e
	// Bit mask of DLLSRST field.
	DDRPHYC_DDRPHYC_ACDLLCR_DLLSRST_Msk = 0x40000000
	// Bit DLLSRST.
	DDRPHYC_DDRPHYC_ACDLLCR_DLLSRST = 0x40000000
	// Position of DLLDIS field.
	DDRPHYC_DDRPHYC_ACDLLCR_DLLDIS_Pos = 0x1f
	// Bit mask of DLLDIS field.
	DDRPHYC_DDRPHYC_ACDLLCR_DLLDIS_Msk = 0x80000000
	// Bit DLLDIS.
	DDRPHYC_DDRPHYC_ACDLLCR_DLLDIS = 0x80000000

	// DDRPHYC_PTR0: DDRPHYC PT register 0
	// Position of TDLLSRST field.
	DDRPHYC_DDRPHYC_PTR0_TDLLSRST_Pos = 0x0
	// Bit mask of TDLLSRST field.
	DDRPHYC_DDRPHYC_PTR0_TDLLSRST_Msk = 0x3f
	// Position of TDLLLOCK field.
	DDRPHYC_DDRPHYC_PTR0_TDLLLOCK_Pos = 0x6
	// Bit mask of TDLLLOCK field.
	DDRPHYC_DDRPHYC_PTR0_TDLLLOCK_Msk = 0x3ffc0
	// Position of TITMSRST field.
	DDRPHYC_DDRPHYC_PTR0_TITMSRST_Pos = 0x12
	// Bit mask of TITMSRST field.
	DDRPHYC_DDRPHYC_PTR0_TITMSRST_Msk = 0x3c0000

	// DDRPHYC_PTR1: DDRPHYC PT register 1
	// Position of TDINIT0 field.
	DDRPHYC_DDRPHYC_PTR1_TDINIT0_Pos = 0x0
	// Bit mask of TDINIT0 field.
	DDRPHYC_DDRPHYC_PTR1_TDINIT0_Msk = 0x7ffff
	// Position of TDINIT1 field.
	DDRPHYC_DDRPHYC_PTR1_TDINIT1_Pos = 0x13
	// Bit mask of TDINIT1 field.
	DDRPHYC_DDRPHYC_PTR1_TDINIT1_Msk = 0x7f80000

	// DDRPHYC_PTR2: DDRPHYC PT register 2
	// Position of TDINIT2 field.
	DDRPHYC_DDRPHYC_PTR2_TDINIT2_Pos = 0x0
	// Bit mask of TDINIT2 field.
	DDRPHYC_DDRPHYC_PTR2_TDINIT2_Msk = 0x1ffff
	// Position of TDINIT3 field.
	DDRPHYC_DDRPHYC_PTR2_TDINIT3_Pos = 0x11
	// Bit mask of TDINIT3 field.
	DDRPHYC_DDRPHYC_PTR2_TDINIT3_Msk = 0x7fe0000

	// DDRPHYC_ACIOCR: DDRPHYC ACIOC register
	// Position of ACIOM field.
	DDRPHYC_DDRPHYC_ACIOCR_ACIOM_Pos = 0x0
	// Bit mask of ACIOM field.
	DDRPHYC_DDRPHYC_ACIOCR_ACIOM_Msk = 0x1
	// Bit ACIOM.
	DDRPHYC_DDRPHYC_ACIOCR_ACIOM = 0x1
	// Position of ACOE field.
	DDRPHYC_DDRPHYC_ACIOCR_ACOE_Pos = 0x1
	// Bit mask of ACOE field.
	DDRPHYC_DDRPHYC_ACIOCR_ACOE_Msk = 0x2
	// Bit ACOE.
	DDRPHYC_DDRPHYC_ACIOCR_ACOE = 0x2
	// Position of ACODT field.
	DDRPHYC_DDRPHYC_ACIOCR_ACODT_Pos = 0x2
	// Bit mask of ACODT field.
	DDRPHYC_DDRPHYC_ACIOCR_ACODT_Msk = 0x4
	// Bit ACODT.
	DDRPHYC_DDRPHYC_ACIOCR_ACODT = 0x4
	// Position of ACPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_ACPDD_Pos = 0x3
	// Bit mask of ACPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_ACPDD_Msk = 0x8
	// Bit ACPDD.
	DDRPHYC_DDRPHYC_ACIOCR_ACPDD = 0x8
	// Position of ACPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_ACPDR_Pos = 0x4
	// Bit mask of ACPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_ACPDR_Msk = 0x10
	// Bit ACPDR.
	DDRPHYC_DDRPHYC_ACIOCR_ACPDR = 0x10
	// Position of CKODT field.
	DDRPHYC_DDRPHYC_ACIOCR_CKODT_Pos = 0x5
	// Bit mask of CKODT field.
	DDRPHYC_DDRPHYC_ACIOCR_CKODT_Msk = 0xe0
	// Position of CKPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_CKPDD_Pos = 0x8
	// Bit mask of CKPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_CKPDD_Msk = 0x700
	// Position of CKPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_CKPDR_Pos = 0xb
	// Bit mask of CKPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_CKPDR_Msk = 0x3800
	// Position of RANKODT field.
	DDRPHYC_DDRPHYC_ACIOCR_RANKODT_Pos = 0xe
	// Bit mask of RANKODT field.
	DDRPHYC_DDRPHYC_ACIOCR_RANKODT_Msk = 0x4000
	// Bit RANKODT.
	DDRPHYC_DDRPHYC_ACIOCR_RANKODT = 0x4000
	// Position of CSPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_CSPDD_Pos = 0x12
	// Bit mask of CSPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_CSPDD_Msk = 0x40000
	// Bit CSPDD.
	DDRPHYC_DDRPHYC_ACIOCR_CSPDD = 0x40000
	// Position of RANKPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_RANKPDR_Pos = 0x16
	// Bit mask of RANKPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_RANKPDR_Msk = 0x400000
	// Bit RANKPDR.
	DDRPHYC_DDRPHYC_ACIOCR_RANKPDR = 0x400000
	// Position of RSTODT field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTODT_Pos = 0x1a
	// Bit mask of RSTODT field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTODT_Msk = 0x4000000
	// Bit RSTODT.
	DDRPHYC_DDRPHYC_ACIOCR_RSTODT = 0x4000000
	// Position of RSTPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTPDD_Pos = 0x1b
	// Bit mask of RSTPDD field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTPDD_Msk = 0x8000000
	// Bit RSTPDD.
	DDRPHYC_DDRPHYC_ACIOCR_RSTPDD = 0x8000000
	// Position of RSTPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTPDR_Pos = 0x1c
	// Bit mask of RSTPDR field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTPDR_Msk = 0x10000000
	// Bit RSTPDR.
	DDRPHYC_DDRPHYC_ACIOCR_RSTPDR = 0x10000000
	// Position of RSTIOM field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTIOM_Pos = 0x1d
	// Bit mask of RSTIOM field.
	DDRPHYC_DDRPHYC_ACIOCR_RSTIOM_Msk = 0x20000000
	// Bit RSTIOM.
	DDRPHYC_DDRPHYC_ACIOCR_RSTIOM = 0x20000000
	// Position of ACSR field.
	DDRPHYC_DDRPHYC_ACIOCR_ACSR_Pos = 0x1e
	// Bit mask of ACSR field.
	DDRPHYC_DDRPHYC_ACIOCR_ACSR_Msk = 0xc0000000

	// DDRPHYC_DXCCR: DDRPHYC DXCC register
	// Position of DXODT field.
	DDRPHYC_DDRPHYC_DXCCR_DXODT_Pos = 0x0
	// Bit mask of DXODT field.
	DDRPHYC_DDRPHYC_DXCCR_DXODT_Msk = 0x1
	// Bit DXODT.
	DDRPHYC_DDRPHYC_DXCCR_DXODT = 0x1
	// Position of DXIOM field.
	DDRPHYC_DDRPHYC_DXCCR_DXIOM_Pos = 0x1
	// Bit mask of DXIOM field.
	DDRPHYC_DDRPHYC_DXCCR_DXIOM_Msk = 0x2
	// Bit DXIOM.
	DDRPHYC_DDRPHYC_DXCCR_DXIOM = 0x2
	// Position of DXPDD field.
	DDRPHYC_DDRPHYC_DXCCR_DXPDD_Pos = 0x2
	// Bit mask of DXPDD field.
	DDRPHYC_DDRPHYC_DXCCR_DXPDD_Msk = 0x4
	// Bit DXPDD.
	DDRPHYC_DDRPHYC_DXCCR_DXPDD = 0x4
	// Position of DXPDR field.
	DDRPHYC_DDRPHYC_DXCCR_DXPDR_Pos = 0x3
	// Bit mask of DXPDR field.
	DDRPHYC_DDRPHYC_DXCCR_DXPDR_Msk = 0x8
	// Bit DXPDR.
	DDRPHYC_DDRPHYC_DXCCR_DXPDR = 0x8
	// Position of DQSRES field.
	DDRPHYC_DDRPHYC_DXCCR_DQSRES_Pos = 0x4
	// Bit mask of DQSRES field.
	DDRPHYC_DDRPHYC_DXCCR_DQSRES_Msk = 0xf0
	// Position of DQSNRES field.
	DDRPHYC_DDRPHYC_DXCCR_DQSNRES_Pos = 0x8
	// Bit mask of DQSNRES field.
	DDRPHYC_DDRPHYC_DXCCR_DQSNRES_Msk = 0xf00
	// Position of DQSNRST field.
	DDRPHYC_DDRPHYC_DXCCR_DQSNRST_Pos = 0xe
	// Bit mask of DQSNRST field.
	DDRPHYC_DDRPHYC_DXCCR_DQSNRST_Msk = 0x4000
	// Bit DQSNRST.
	DDRPHYC_DDRPHYC_DXCCR_DQSNRST = 0x4000
	// Position of RVSEL field.
	DDRPHYC_DDRPHYC_DXCCR_RVSEL_Pos = 0xf
	// Bit mask of RVSEL field.
	DDRPHYC_DDRPHYC_DXCCR_RVSEL_Msk = 0x8000
	// Bit RVSEL.
	DDRPHYC_DDRPHYC_DXCCR_RVSEL = 0x8000
	// Position of AWDT field.
	DDRPHYC_DDRPHYC_DXCCR_AWDT_Pos = 0x10
	// Bit mask of AWDT field.
	DDRPHYC_DDRPHYC_DXCCR_AWDT_Msk = 0x10000
	// Bit AWDT.
	DDRPHYC_DDRPHYC_DXCCR_AWDT = 0x10000

	// DDRPHYC_DSGCR: DDRPHYC DSGC register
	// Position of PUREN field.
	DDRPHYC_DDRPHYC_DSGCR_PUREN_Pos = 0x0
	// Bit mask of PUREN field.
	DDRPHYC_DDRPHYC_DSGCR_PUREN_Msk = 0x1
	// Bit PUREN.
	DDRPHYC_DDRPHYC_DSGCR_PUREN = 0x1
	// Position of BDISEN field.
	DDRPHYC_DDRPHYC_DSGCR_BDISEN_Pos = 0x1
	// Bit mask of BDISEN field.
	DDRPHYC_DDRPHYC_DSGCR_BDISEN_Msk = 0x2
	// Bit BDISEN.
	DDRPHYC_DDRPHYC_DSGCR_BDISEN = 0x2
	// Position of ZUEN field.
	DDRPHYC_DDRPHYC_DSGCR_ZUEN_Pos = 0x2
	// Bit mask of ZUEN field.
	DDRPHYC_DDRPHYC_DSGCR_ZUEN_Msk = 0x4
	// Bit ZUEN.
	DDRPHYC_DDRPHYC_DSGCR_ZUEN = 0x4
	// Position of LPIOPD field.
	DDRPHYC_DDRPHYC_DSGCR_LPIOPD_Pos = 0x3
	// Bit mask of LPIOPD field.
	DDRPHYC_DDRPHYC_DSGCR_LPIOPD_Msk = 0x8
	// Bit LPIOPD.
	DDRPHYC_DDRPHYC_DSGCR_LPIOPD = 0x8
	// Position of LPDLLPD field.
	DDRPHYC_DDRPHYC_DSGCR_LPDLLPD_Pos = 0x4
	// Bit mask of LPDLLPD field.
	DDRPHYC_DDRPHYC_DSGCR_LPDLLPD_Msk = 0x10
	// Bit LPDLLPD.
	DDRPHYC_DDRPHYC_DSGCR_LPDLLPD = 0x10
	// Position of DQSGX field.
	DDRPHYC_DDRPHYC_DSGCR_DQSGX_Pos = 0x5
	// Bit mask of DQSGX field.
	DDRPHYC_DDRPHYC_DSGCR_DQSGX_Msk = 0xe0
	// Position of DQSGE field.
	DDRPHYC_DDRPHYC_DSGCR_DQSGE_Pos = 0x8
	// Bit mask of DQSGE field.
	DDRPHYC_DDRPHYC_DSGCR_DQSGE_Msk = 0x700
	// Position of NOBUB field.
	DDRPHYC_DDRPHYC_DSGCR_NOBUB_Pos = 0xb
	// Bit mask of NOBUB field.
	DDRPHYC_DDRPHYC_DSGCR_NOBUB_Msk = 0x800
	// Bit NOBUB.
	DDRPHYC_DDRPHYC_DSGCR_NOBUB = 0x800
	// Position of FXDLAT field.
	DDRPHYC_DDRPHYC_DSGCR_FXDLAT_Pos = 0xc
	// Bit mask of FXDLAT field.
	DDRPHYC_DDRPHYC_DSGCR_FXDLAT_Msk = 0x1000
	// Bit FXDLAT.
	DDRPHYC_DDRPHYC_DSGCR_FXDLAT = 0x1000
	// Position of CKEPDD field.
	DDRPHYC_DDRPHYC_DSGCR_CKEPDD_Pos = 0x10
	// Bit mask of CKEPDD field.
	DDRPHYC_DDRPHYC_DSGCR_CKEPDD_Msk = 0x10000
	// Bit CKEPDD.
	DDRPHYC_DDRPHYC_DSGCR_CKEPDD = 0x10000
	// Position of ODTPDD field.
	DDRPHYC_DDRPHYC_DSGCR_ODTPDD_Pos = 0x14
	// Bit mask of ODTPDD field.
	DDRPHYC_DDRPHYC_DSGCR_ODTPDD_Msk = 0x100000
	// Bit ODTPDD.
	DDRPHYC_DDRPHYC_DSGCR_ODTPDD = 0x100000
	// Position of NL2PD field.
	DDRPHYC_DDRPHYC_DSGCR_NL2PD_Pos = 0x18
	// Bit mask of NL2PD field.
	DDRPHYC_DDRPHYC_DSGCR_NL2PD_Msk = 0x1000000
	// Bit NL2PD.
	DDRPHYC_DDRPHYC_DSGCR_NL2PD = 0x1000000
	// Position of NL2OE field.
	DDRPHYC_DDRPHYC_DSGCR_NL2OE_Pos = 0x19
	// Bit mask of NL2OE field.
	DDRPHYC_DDRPHYC_DSGCR_NL2OE_Msk = 0x2000000
	// Bit NL2OE.
	DDRPHYC_DDRPHYC_DSGCR_NL2OE = 0x2000000
	// Position of TPDPD field.
	DDRPHYC_DDRPHYC_DSGCR_TPDPD_Pos = 0x1a
	// Bit mask of TPDPD field.
	DDRPHYC_DDRPHYC_DSGCR_TPDPD_Msk = 0x4000000
	// Bit TPDPD.
	DDRPHYC_DDRPHYC_DSGCR_TPDPD = 0x4000000
	// Position of TPDOE field.
	DDRPHYC_DDRPHYC_DSGCR_TPDOE_Pos = 0x1b
	// Bit mask of TPDOE field.
	DDRPHYC_DDRPHYC_DSGCR_TPDOE_Msk = 0x8000000
	// Bit TPDOE.
	DDRPHYC_DDRPHYC_DSGCR_TPDOE = 0x8000000
	// Position of CKOE field.
	DDRPHYC_DDRPHYC_DSGCR_CKOE_Pos = 0x1c
	// Bit mask of CKOE field.
	DDRPHYC_DDRPHYC_DSGCR_CKOE_Msk = 0x10000000
	// Bit CKOE.
	DDRPHYC_DDRPHYC_DSGCR_CKOE = 0x10000000
	// Position of ODTOE field.
	DDRPHYC_DDRPHYC_DSGCR_ODTOE_Pos = 0x1d
	// Bit mask of ODTOE field.
	DDRPHYC_DDRPHYC_DSGCR_ODTOE_Msk = 0x20000000
	// Bit ODTOE.
	DDRPHYC_DDRPHYC_DSGCR_ODTOE = 0x20000000
	// Position of RSTOE field.
	DDRPHYC_DDRPHYC_DSGCR_RSTOE_Pos = 0x1e
	// Bit mask of RSTOE field.
	DDRPHYC_DDRPHYC_DSGCR_RSTOE_Msk = 0x40000000
	// Bit RSTOE.
	DDRPHYC_DDRPHYC_DSGCR_RSTOE = 0x40000000
	// Position of CKEOE field.
	DDRPHYC_DDRPHYC_DSGCR_CKEOE_Pos = 0x1f
	// Bit mask of CKEOE field.
	DDRPHYC_DDRPHYC_DSGCR_CKEOE_Msk = 0x80000000
	// Bit CKEOE.
	DDRPHYC_DDRPHYC_DSGCR_CKEOE = 0x80000000

	// DDRPHYC_DCR: DDRPHYC DC register
	// Position of DDRMD field.
	DDRPHYC_DDRPHYC_DCR_DDRMD_Pos = 0x0
	// Bit mask of DDRMD field.
	DDRPHYC_DDRPHYC_DCR_DDRMD_Msk = 0x7
	// Position of DDR8BNK field.
	DDRPHYC_DDRPHYC_DCR_DDR8BNK_Pos = 0x3
	// Bit mask of DDR8BNK field.
	DDRPHYC_DDRPHYC_DCR_DDR8BNK_Msk = 0x8
	// Bit DDR8BNK.
	DDRPHYC_DDRPHYC_DCR_DDR8BNK = 0x8
	// Position of PDQ field.
	DDRPHYC_DDRPHYC_DCR_PDQ_Pos = 0x4
	// Bit mask of PDQ field.
	DDRPHYC_DDRPHYC_DCR_PDQ_Msk = 0x70
	// Position of MPRDQ field.
	DDRPHYC_DDRPHYC_DCR_MPRDQ_Pos = 0x7
	// Bit mask of MPRDQ field.
	DDRPHYC_DDRPHYC_DCR_MPRDQ_Msk = 0x80
	// Bit MPRDQ.
	DDRPHYC_DDRPHYC_DCR_MPRDQ = 0x80
	// Position of DDRTYPE field.
	DDRPHYC_DDRPHYC_DCR_DDRTYPE_Pos = 0x8
	// Bit mask of DDRTYPE field.
	DDRPHYC_DDRPHYC_DCR_DDRTYPE_Msk = 0x300
	// Position of NOSRA field.
	DDRPHYC_DDRPHYC_DCR_NOSRA_Pos = 0x1b
	// Bit mask of NOSRA field.
	DDRPHYC_DDRPHYC_DCR_NOSRA_Msk = 0x8000000
	// Bit NOSRA.
	DDRPHYC_DDRPHYC_DCR_NOSRA = 0x8000000
	// Position of DDR2T field.
	DDRPHYC_DDRPHYC_DCR_DDR2T_Pos = 0x1c
	// Bit mask of DDR2T field.
	DDRPHYC_DDRPHYC_DCR_DDR2T_Msk = 0x10000000
	// Bit DDR2T.
	DDRPHYC_DDRPHYC_DCR_DDR2T = 0x10000000
	// Position of UDIMM field.
	DDRPHYC_DDRPHYC_DCR_UDIMM_Pos = 0x1d
	// Bit mask of UDIMM field.
	DDRPHYC_DDRPHYC_DCR_UDIMM_Msk = 0x20000000
	// Bit UDIMM.
	DDRPHYC_DDRPHYC_DCR_UDIMM = 0x20000000
	// Position of RDIMM field.
	DDRPHYC_DDRPHYC_DCR_RDIMM_Pos = 0x1e
	// Bit mask of RDIMM field.
	DDRPHYC_DDRPHYC_DCR_RDIMM_Msk = 0x40000000
	// Bit RDIMM.
	DDRPHYC_DDRPHYC_DCR_RDIMM = 0x40000000
	// Position of TPD field.
	DDRPHYC_DDRPHYC_DCR_TPD_Pos = 0x1f
	// Bit mask of TPD field.
	DDRPHYC_DDRPHYC_DCR_TPD_Msk = 0x80000000
	// Bit TPD.
	DDRPHYC_DDRPHYC_DCR_TPD = 0x80000000

	// DDRPHYC_DTPR0: DDRPHYC DTP register 0
	// Position of TMRD field.
	DDRPHYC_DDRPHYC_DTPR0_TMRD_Pos = 0x0
	// Bit mask of TMRD field.
	DDRPHYC_DDRPHYC_DTPR0_TMRD_Msk = 0x3
	// Position of TRTP field.
	DDRPHYC_DDRPHYC_DTPR0_TRTP_Pos = 0x2
	// Bit mask of TRTP field.
	DDRPHYC_DDRPHYC_DTPR0_TRTP_Msk = 0x1c
	// Position of TWTR field.
	DDRPHYC_DDRPHYC_DTPR0_TWTR_Pos = 0x5
	// Bit mask of TWTR field.
	DDRPHYC_DDRPHYC_DTPR0_TWTR_Msk = 0xe0
	// Position of TRP field.
	DDRPHYC_DDRPHYC_DTPR0_TRP_Pos = 0x8
	// Bit mask of TRP field.
	DDRPHYC_DDRPHYC_DTPR0_TRP_Msk = 0xf00
	// Position of TRCD field.
	DDRPHYC_DDRPHYC_DTPR0_TRCD_Pos = 0xc
	// Bit mask of TRCD field.
	DDRPHYC_DDRPHYC_DTPR0_TRCD_Msk = 0xf000
	// Position of TRAS field.
	DDRPHYC_DDRPHYC_DTPR0_TRAS_Pos = 0x10
	// Bit mask of TRAS field.
	DDRPHYC_DDRPHYC_DTPR0_TRAS_Msk = 0x1f0000
	// Position of TRRD field.
	DDRPHYC_DDRPHYC_DTPR0_TRRD_Pos = 0x15
	// Bit mask of TRRD field.
	DDRPHYC_DDRPHYC_DTPR0_TRRD_Msk = 0x1e00000
	// Position of TRC field.
	DDRPHYC_DDRPHYC_DTPR0_TRC_Pos = 0x19
	// Bit mask of TRC field.
	DDRPHYC_DDRPHYC_DTPR0_TRC_Msk = 0x7e000000
	// Position of TCCD field.
	DDRPHYC_DDRPHYC_DTPR0_TCCD_Pos = 0x1f
	// Bit mask of TCCD field.
	DDRPHYC_DDRPHYC_DTPR0_TCCD_Msk = 0x80000000
	// Bit TCCD.
	DDRPHYC_DDRPHYC_DTPR0_TCCD = 0x80000000

	// DDRPHYC_DTPR1: DDRPHYC DTP register 1
	// Position of TAOND field.
	DDRPHYC_DDRPHYC_DTPR1_TAOND_Pos = 0x0
	// Bit mask of TAOND field.
	DDRPHYC_DDRPHYC_DTPR1_TAOND_Msk = 0x3
	// Position of TRTW field.
	DDRPHYC_DDRPHYC_DTPR1_TRTW_Pos = 0x2
	// Bit mask of TRTW field.
	DDRPHYC_DDRPHYC_DTPR1_TRTW_Msk = 0x4
	// Bit TRTW.
	DDRPHYC_DDRPHYC_DTPR1_TRTW = 0x4
	// Position of TFAW field.
	DDRPHYC_DDRPHYC_DTPR1_TFAW_Pos = 0x3
	// Bit mask of TFAW field.
	DDRPHYC_DDRPHYC_DTPR1_TFAW_Msk = 0x1f8
	// Position of TMOD field.
	DDRPHYC_DDRPHYC_DTPR1_TMOD_Pos = 0x9
	// Bit mask of TMOD field.
	DDRPHYC_DDRPHYC_DTPR1_TMOD_Msk = 0x600
	// Position of TRTODT field.
	DDRPHYC_DDRPHYC_DTPR1_TRTODT_Pos = 0xb
	// Bit mask of TRTODT field.
	DDRPHYC_DDRPHYC_DTPR1_TRTODT_Msk = 0x800
	// Bit TRTODT.
	DDRPHYC_DDRPHYC_DTPR1_TRTODT = 0x800
	// Position of TRFC field.
	DDRPHYC_DDRPHYC_DTPR1_TRFC_Pos = 0x10
	// Bit mask of TRFC field.
	DDRPHYC_DDRPHYC_DTPR1_TRFC_Msk = 0xff0000
	// Position of TDQSCKMIN field.
	DDRPHYC_DDRPHYC_DTPR1_TDQSCKMIN_Pos = 0x18
	// Bit mask of TDQSCKMIN field.
	DDRPHYC_DDRPHYC_DTPR1_TDQSCKMIN_Msk = 0x7000000
	// Position of TDQSCKMAX field.
	DDRPHYC_DDRPHYC_DTPR1_TDQSCKMAX_Pos = 0x1b
	// Bit mask of TDQSCKMAX field.
	DDRPHYC_DDRPHYC_DTPR1_TDQSCKMAX_Msk = 0x38000000

	// DDRPHYC_DTPR2: DDRPHYC DTP register 2
	// Position of TXS field.
	DDRPHYC_DDRPHYC_DTPR2_TXS_Pos = 0x0
	// Bit mask of TXS field.
	DDRPHYC_DDRPHYC_DTPR2_TXS_Msk = 0x3ff
	// Position of TXP field.
	DDRPHYC_DDRPHYC_DTPR2_TXP_Pos = 0xa
	// Bit mask of TXP field.
	DDRPHYC_DDRPHYC_DTPR2_TXP_Msk = 0x7c00
	// Position of TCKE field.
	DDRPHYC_DDRPHYC_DTPR2_TCKE_Pos = 0xf
	// Bit mask of TCKE field.
	DDRPHYC_DDRPHYC_DTPR2_TCKE_Msk = 0x78000
	// Position of TDLLK field.
	DDRPHYC_DDRPHYC_DTPR2_TDLLK_Pos = 0x13
	// Bit mask of TDLLK field.
	DDRPHYC_DDRPHYC_DTPR2_TDLLK_Msk = 0x1ff80000

	// DDRPHYC_DDR3_MR0: DDRPHYC MR0 register for DDR3
	// Position of BL field.
	DDRPHYC_DDRPHYC_DDR3_MR0_BL_Pos = 0x0
	// Bit mask of BL field.
	DDRPHYC_DDRPHYC_DDR3_MR0_BL_Msk = 0x3
	// Position of CL0 field.
	DDRPHYC_DDRPHYC_DDR3_MR0_CL0_Pos = 0x2
	// Bit mask of CL0 field.
	DDRPHYC_DDRPHYC_DDR3_MR0_CL0_Msk = 0x4
	// Bit CL0.
	DDRPHYC_DDRPHYC_DDR3_MR0_CL0 = 0x4
	// Position of BT field.
	DDRPHYC_DDRPHYC_DDR3_MR0_BT_Pos = 0x3
	// Bit mask of BT field.
	DDRPHYC_DDRPHYC_DDR3_MR0_BT_Msk = 0x8
	// Bit BT.
	DDRPHYC_DDRPHYC_DDR3_MR0_BT = 0x8
	// Position of CL field.
	DDRPHYC_DDRPHYC_DDR3_MR0_CL_Pos = 0x4
	// Bit mask of CL field.
	DDRPHYC_DDRPHYC_DDR3_MR0_CL_Msk = 0x70
	// Position of TM field.
	DDRPHYC_DDRPHYC_DDR3_MR0_TM_Pos = 0x7
	// Bit mask of TM field.
	DDRPHYC_DDRPHYC_DDR3_MR0_TM_Msk = 0x80
	// Bit TM.
	DDRPHYC_DDRPHYC_DDR3_MR0_TM = 0x80
	// Position of DR field.
	DDRPHYC_DDRPHYC_DDR3_MR0_DR_Pos = 0x8
	// Bit mask of DR field.
	DDRPHYC_DDRPHYC_DDR3_MR0_DR_Msk = 0x100
	// Bit DR.
	DDRPHYC_DDRPHYC_DDR3_MR0_DR = 0x100
	// Position of WR field.
	DDRPHYC_DDRPHYC_DDR3_MR0_WR_Pos = 0x9
	// Bit mask of WR field.
	DDRPHYC_DDRPHYC_DDR3_MR0_WR_Msk = 0xe00
	// Position of PD field.
	DDRPHYC_DDRPHYC_DDR3_MR0_PD_Pos = 0xc
	// Bit mask of PD field.
	DDRPHYC_DDRPHYC_DDR3_MR0_PD_Msk = 0x1000
	// Bit PD.
	DDRPHYC_DDRPHYC_DDR3_MR0_PD = 0x1000
	// Position of RSVD field.
	DDRPHYC_DDRPHYC_DDR3_MR0_RSVD_Pos = 0xd
	// Bit mask of RSVD field.
	DDRPHYC_DDRPHYC_DDR3_MR0_RSVD_Msk = 0xe000

	// DDRPHYC_DDR3_MR1: DDRPHYC MR1 register for DDR3
	// Position of DE field.
	DDRPHYC_DDRPHYC_DDR3_MR1_DE_Pos = 0x0
	// Bit mask of DE field.
	DDRPHYC_DDRPHYC_DDR3_MR1_DE_Msk = 0x1
	// Bit DE.
	DDRPHYC_DDRPHYC_DDR3_MR1_DE = 0x1
	// Position of DIC0 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_DIC0_Pos = 0x1
	// Bit mask of DIC0 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_DIC0_Msk = 0x2
	// Bit DIC0.
	DDRPHYC_DDRPHYC_DDR3_MR1_DIC0 = 0x2
	// Position of RTT0 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT0_Pos = 0x2
	// Bit mask of RTT0 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT0_Msk = 0x4
	// Bit RTT0.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT0 = 0x4
	// Position of AL field.
	DDRPHYC_DDRPHYC_DDR3_MR1_AL_Pos = 0x3
	// Bit mask of AL field.
	DDRPHYC_DDRPHYC_DDR3_MR1_AL_Msk = 0x18
	// Position of DIC1 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_DIC1_Pos = 0x5
	// Bit mask of DIC1 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_DIC1_Msk = 0x20
	// Bit DIC1.
	DDRPHYC_DDRPHYC_DDR3_MR1_DIC1 = 0x20
	// Position of RTT1 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT1_Pos = 0x6
	// Bit mask of RTT1 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT1_Msk = 0x40
	// Bit RTT1.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT1 = 0x40
	// Position of LEVEL field.
	DDRPHYC_DDRPHYC_DDR3_MR1_LEVEL_Pos = 0x7
	// Bit mask of LEVEL field.
	DDRPHYC_DDRPHYC_DDR3_MR1_LEVEL_Msk = 0x80
	// Bit LEVEL.
	DDRPHYC_DDRPHYC_DDR3_MR1_LEVEL = 0x80
	// Position of RTT2 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT2_Pos = 0x9
	// Bit mask of RTT2 field.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT2_Msk = 0x200
	// Bit RTT2.
	DDRPHYC_DDRPHYC_DDR3_MR1_RTT2 = 0x200
	// Position of TDQS field.
	DDRPHYC_DDRPHYC_DDR3_MR1_TDQS_Pos = 0xb
	// Bit mask of TDQS field.
	DDRPHYC_DDRPHYC_DDR3_MR1_TDQS_Msk = 0x800
	// Bit TDQS.
	DDRPHYC_DDRPHYC_DDR3_MR1_TDQS = 0x800
	// Position of QOFF field.
	DDRPHYC_DDRPHYC_DDR3_MR1_QOFF_Pos = 0xc
	// Bit mask of QOFF field.
	DDRPHYC_DDRPHYC_DDR3_MR1_QOFF_Msk = 0x1000
	// Bit QOFF.
	DDRPHYC_DDRPHYC_DDR3_MR1_QOFF = 0x1000

	// DDRPHYC_DDR3_MR2: DDRPHYC MR2 register for DDR3
	// Position of PASR field.
	DDRPHYC_DDRPHYC_DDR3_MR2_PASR_Pos = 0x0
	// Bit mask of PASR field.
	DDRPHYC_DDRPHYC_DDR3_MR2_PASR_Msk = 0x7
	// Position of CWL field.
	DDRPHYC_DDRPHYC_DDR3_MR2_CWL_Pos = 0x3
	// Bit mask of CWL field.
	DDRPHYC_DDRPHYC_DDR3_MR2_CWL_Msk = 0x38
	// Position of ASR field.
	DDRPHYC_DDRPHYC_DDR3_MR2_ASR_Pos = 0x6
	// Bit mask of ASR field.
	DDRPHYC_DDRPHYC_DDR3_MR2_ASR_Msk = 0x40
	// Bit ASR.
	DDRPHYC_DDRPHYC_DDR3_MR2_ASR = 0x40
	// Position of SRT field.
	DDRPHYC_DDRPHYC_DDR3_MR2_SRT_Pos = 0x7
	// Bit mask of SRT field.
	DDRPHYC_DDRPHYC_DDR3_MR2_SRT_Msk = 0x80
	// Bit SRT.
	DDRPHYC_DDRPHYC_DDR3_MR2_SRT = 0x80
	// Position of RTTWR field.
	DDRPHYC_DDRPHYC_DDR3_MR2_RTTWR_Pos = 0x9
	// Bit mask of RTTWR field.
	DDRPHYC_DDRPHYC_DDR3_MR2_RTTWR_Msk = 0x600

	// DDRPHYC_DDR3_MR3: DDRPHYC MR3 register for DDR3
	// Position of MPRLOC field.
	DDRPHYC_DDRPHYC_DDR3_MR3_MPRLOC_Pos = 0x0
	// Bit mask of MPRLOC field.
	DDRPHYC_DDRPHYC_DDR3_MR3_MPRLOC_Msk = 0x3
	// Position of MPR field.
	DDRPHYC_DDRPHYC_DDR3_MR3_MPR_Pos = 0x2
	// Bit mask of MPR field.
	DDRPHYC_DDRPHYC_DDR3_MR3_MPR_Msk = 0x4
	// Bit MPR.
	DDRPHYC_DDRPHYC_DDR3_MR3_MPR = 0x4

	// DDRPHYC_ODTCR: DDRPHYC ODTC register
	// Position of RDODT field.
	DDRPHYC_DDRPHYC_ODTCR_RDODT_Pos = 0x0
	// Bit mask of RDODT field.
	DDRPHYC_DDRPHYC_ODTCR_RDODT_Msk = 0x1
	// Bit RDODT.
	DDRPHYC_DDRPHYC_ODTCR_RDODT = 0x1
	// Position of WRODT field.
	DDRPHYC_DDRPHYC_ODTCR_WRODT_Pos = 0x10
	// Bit mask of WRODT field.
	DDRPHYC_DDRPHYC_ODTCR_WRODT_Msk = 0x10000
	// Bit WRODT.
	DDRPHYC_DDRPHYC_ODTCR_WRODT = 0x10000

	// DDRPHYC_DTAR: DDRPHYC DTA register
	// Position of DTCOL field.
	DDRPHYC_DDRPHYC_DTAR_DTCOL_Pos = 0x0
	// Bit mask of DTCOL field.
	DDRPHYC_DDRPHYC_DTAR_DTCOL_Msk = 0xfff
	// Position of DTROW field.
	DDRPHYC_DDRPHYC_DTAR_DTROW_Pos = 0xc
	// Bit mask of DTROW field.
	DDRPHYC_DDRPHYC_DTAR_DTROW_Msk = 0xffff000
	// Position of DTBANK field.
	DDRPHYC_DDRPHYC_DTAR_DTBANK_Pos = 0x1c
	// Bit mask of DTBANK field.
	DDRPHYC_DDRPHYC_DTAR_DTBANK_Msk = 0x70000000
	// Position of DTMPR field.
	DDRPHYC_DDRPHYC_DTAR_DTMPR_Pos = 0x1f
	// Bit mask of DTMPR field.
	DDRPHYC_DDRPHYC_DTAR_DTMPR_Msk = 0x80000000
	// Bit DTMPR.
	DDRPHYC_DDRPHYC_DTAR_DTMPR = 0x80000000

	// DDRPHYC_DTDR0: DDRPHYC DTD register 0
	// Position of DTBYTE0 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE0_Pos = 0x0
	// Bit mask of DTBYTE0 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE0_Msk = 0xff
	// Position of DTBYTE1 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE1_Pos = 0x8
	// Bit mask of DTBYTE1 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE1_Msk = 0xff00
	// Position of DTBYTE2 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE2_Pos = 0x10
	// Bit mask of DTBYTE2 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE2_Msk = 0xff0000
	// Position of DTBYTE3 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE3_Pos = 0x18
	// Bit mask of DTBYTE3 field.
	DDRPHYC_DDRPHYC_DTDR0_DTBYTE3_Msk = 0xff000000

	// DDRPHYC_DTDR1: DDRPHYC DTD register 1
	// Position of DTBYTE4 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE4_Pos = 0x0
	// Bit mask of DTBYTE4 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE4_Msk = 0xff
	// Position of DTBYTE5 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE5_Pos = 0x8
	// Bit mask of DTBYTE5 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE5_Msk = 0xff00
	// Position of DTBYTE6 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE6_Pos = 0x10
	// Bit mask of DTBYTE6 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE6_Msk = 0xff0000
	// Position of DTBYTE7 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE7_Pos = 0x18
	// Bit mask of DTBYTE7 field.
	DDRPHYC_DDRPHYC_DTDR1_DTBYTE7_Msk = 0xff000000

	// DDRPHYC_GPR0: DDRPHYC general purpose register 0
	// Position of GPR0 field.
	DDRPHYC_DDRPHYC_GPR0_GPR0_Pos = 0x0
	// Bit mask of GPR0 field.
	DDRPHYC_DDRPHYC_GPR0_GPR0_Msk = 0xffffffff

	// DDRPHYC_GPR1: DDRPHYC general purpose register 1
	// Position of GPR1 field.
	DDRPHYC_DDRPHYC_GPR1_GPR1_Pos = 0x0
	// Bit mask of GPR1 field.
	DDRPHYC_DDRPHYC_GPR1_GPR1_Msk = 0xffffffff

	// DDRPHYC_ZQ0CR0: DDRPHYC ZQ0C register 0
	// Position of ZDATA field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZDATA_Pos = 0x0
	// Bit mask of ZDATA field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZDATA_Msk = 0xfffff
	// Position of ZDEN field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZDEN_Pos = 0x1c
	// Bit mask of ZDEN field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZDEN_Msk = 0x10000000
	// Bit ZDEN.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZDEN = 0x10000000
	// Position of ZCALBYP field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZCALBYP_Pos = 0x1d
	// Bit mask of ZCALBYP field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZCALBYP_Msk = 0x20000000
	// Bit ZCALBYP.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZCALBYP = 0x20000000
	// Position of ZCAL field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZCAL_Pos = 0x1e
	// Bit mask of ZCAL field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZCAL_Msk = 0x40000000
	// Bit ZCAL.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZCAL = 0x40000000
	// Position of ZQPD field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZQPD_Pos = 0x1f
	// Bit mask of ZQPD field.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZQPD_Msk = 0x80000000
	// Bit ZQPD.
	DDRPHYC_DDRPHYC_ZQ0CR0_ZQPD = 0x80000000

	// DDRPHYC_ZQ0CR1: DDRPHYC ZQ0CR1 register
	// Position of ZPROG field.
	DDRPHYC_DDRPHYC_ZQ0CR1_ZPROG_Pos = 0x0
	// Bit mask of ZPROG field.
	DDRPHYC_DDRPHYC_ZQ0CR1_ZPROG_Msk = 0xff

	// DDRPHYC_ZQ0SR0: DDRPHYC ZQ0S register 0
	// Position of ZCTRL field.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZCTRL_Pos = 0x0
	// Bit mask of ZCTRL field.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZCTRL_Msk = 0xfffff
	// Position of ZERR field.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZERR_Pos = 0x1e
	// Bit mask of ZERR field.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZERR_Msk = 0x40000000
	// Bit ZERR.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZERR = 0x40000000
	// Position of ZDONE field.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZDONE_Pos = 0x1f
	// Bit mask of ZDONE field.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZDONE_Msk = 0x80000000
	// Bit ZDONE.
	DDRPHYC_DDRPHYC_ZQ0SR0_ZDONE = 0x80000000

	// DDRPHYC_ZQ0SR1: DDRPHYC ZQ0S register 1
	// Position of ZPD field.
	DDRPHYC_DDRPHYC_ZQ0SR1_ZPD_Pos = 0x0
	// Bit mask of ZPD field.
	DDRPHYC_DDRPHYC_ZQ0SR1_ZPD_Msk = 0x3
	// Position of ZPU field.
	DDRPHYC_DDRPHYC_ZQ0SR1_ZPU_Pos = 0x2
	// Bit mask of ZPU field.
	DDRPHYC_DDRPHYC_ZQ0SR1_ZPU_Msk = 0xc
	// Position of OPD field.
	DDRPHYC_DDRPHYC_ZQ0SR1_OPD_Pos = 0x4
	// Bit mask of OPD field.
	DDRPHYC_DDRPHYC_ZQ0SR1_OPD_Msk = 0x30
	// Position of OPU field.
	DDRPHYC_DDRPHYC_ZQ0SR1_OPU_Pos = 0x6
	// Bit mask of OPU field.
	DDRPHYC_DDRPHYC_ZQ0SR1_OPU_Msk = 0xc0

	// DDRPHYC_DX0GCR: DDRPHYC byte lane 0 GC register
	// Position of DXEN field.
	DDRPHYC_DDRPHYC_DX0GCR_DXEN_Pos = 0x0
	// Bit mask of DXEN field.
	DDRPHYC_DDRPHYC_DX0GCR_DXEN_Msk = 0x1
	// Bit DXEN.
	DDRPHYC_DDRPHYC_DX0GCR_DXEN = 0x1
	// Position of DQSODT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQSODT_Pos = 0x1
	// Bit mask of DQSODT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQSODT_Msk = 0x2
	// Bit DQSODT.
	DDRPHYC_DDRPHYC_DX0GCR_DQSODT = 0x2
	// Position of DQODT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQODT_Pos = 0x2
	// Bit mask of DQODT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQODT_Msk = 0x4
	// Bit DQODT.
	DDRPHYC_DDRPHYC_DX0GCR_DQODT = 0x4
	// Position of DXIOM field.
	DDRPHYC_DDRPHYC_DX0GCR_DXIOM_Pos = 0x3
	// Bit mask of DXIOM field.
	DDRPHYC_DDRPHYC_DX0GCR_DXIOM_Msk = 0x8
	// Bit DXIOM.
	DDRPHYC_DDRPHYC_DX0GCR_DXIOM = 0x8
	// Position of DXPDD field.
	DDRPHYC_DDRPHYC_DX0GCR_DXPDD_Pos = 0x4
	// Bit mask of DXPDD field.
	DDRPHYC_DDRPHYC_DX0GCR_DXPDD_Msk = 0x10
	// Bit DXPDD.
	DDRPHYC_DDRPHYC_DX0GCR_DXPDD = 0x10
	// Position of DXPDR field.
	DDRPHYC_DDRPHYC_DX0GCR_DXPDR_Pos = 0x5
	// Bit mask of DXPDR field.
	DDRPHYC_DDRPHYC_DX0GCR_DXPDR_Msk = 0x20
	// Bit DXPDR.
	DDRPHYC_DDRPHYC_DX0GCR_DXPDR = 0x20
	// Position of DQSRPD field.
	DDRPHYC_DDRPHYC_DX0GCR_DQSRPD_Pos = 0x6
	// Bit mask of DQSRPD field.
	DDRPHYC_DDRPHYC_DX0GCR_DQSRPD_Msk = 0x40
	// Bit DQSRPD.
	DDRPHYC_DDRPHYC_DX0GCR_DQSRPD = 0x40
	// Position of DSEN field.
	DDRPHYC_DDRPHYC_DX0GCR_DSEN_Pos = 0x7
	// Bit mask of DSEN field.
	DDRPHYC_DDRPHYC_DX0GCR_DSEN_Msk = 0x180
	// Position of DQSRTT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQSRTT_Pos = 0x9
	// Bit mask of DQSRTT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQSRTT_Msk = 0x200
	// Bit DQSRTT.
	DDRPHYC_DDRPHYC_DX0GCR_DQSRTT = 0x200
	// Position of DQRTT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQRTT_Pos = 0xa
	// Bit mask of DQRTT field.
	DDRPHYC_DDRPHYC_DX0GCR_DQRTT_Msk = 0x400
	// Bit DQRTT.
	DDRPHYC_DDRPHYC_DX0GCR_DQRTT = 0x400
	// Position of RTTOH field.
	DDRPHYC_DDRPHYC_DX0GCR_RTTOH_Pos = 0xb
	// Bit mask of RTTOH field.
	DDRPHYC_DDRPHYC_DX0GCR_RTTOH_Msk = 0x1800
	// Position of RTTOAL field.
	DDRPHYC_DDRPHYC_DX0GCR_RTTOAL_Pos = 0xd
	// Bit mask of RTTOAL field.
	DDRPHYC_DDRPHYC_DX0GCR_RTTOAL_Msk = 0x2000
	// Bit RTTOAL.
	DDRPHYC_DDRPHYC_DX0GCR_RTTOAL = 0x2000
	// Position of R0RVSL field.
	DDRPHYC_DDRPHYC_DX0GCR_R0RVSL_Pos = 0xe
	// Bit mask of R0RVSL field.
	DDRPHYC_DDRPHYC_DX0GCR_R0RVSL_Msk = 0x1c000

	// DDRPHYC_DX0GSR0: DDRPHYC byte lane 0 GS register 0
	// Position of DTDONE field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTDONE_Pos = 0x0
	// Bit mask of DTDONE field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTDONE_Msk = 0x1
	// Bit DTDONE.
	DDRPHYC_DDRPHYC_DX0GSR0_DTDONE = 0x1
	// Position of DTERR field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTERR_Pos = 0x4
	// Bit mask of DTERR field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTERR_Msk = 0x10
	// Bit DTERR.
	DDRPHYC_DDRPHYC_DX0GSR0_DTERR = 0x10
	// Position of DTIERR field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTIERR_Pos = 0x8
	// Bit mask of DTIERR field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTIERR_Msk = 0x100
	// Bit DTIERR.
	DDRPHYC_DDRPHYC_DX0GSR0_DTIERR = 0x100
	// Position of DTPASS field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTPASS_Pos = 0xd
	// Bit mask of DTPASS field.
	DDRPHYC_DDRPHYC_DX0GSR0_DTPASS_Msk = 0xe000

	// DDRPHYC_DX0GSR1: DDRPHYC byte lane 0 GS register 1
	// Position of DFTERR field.
	DDRPHYC_DDRPHYC_DX0GSR1_DFTERR_Pos = 0x0
	// Bit mask of DFTERR field.
	DDRPHYC_DDRPHYC_DX0GSR1_DFTERR_Msk = 0x1
	// Bit DFTERR.
	DDRPHYC_DDRPHYC_DX0GSR1_DFTERR = 0x1
	// Position of DQSDFT field.
	DDRPHYC_DDRPHYC_DX0GSR1_DQSDFT_Pos = 0x4
	// Bit mask of DQSDFT field.
	DDRPHYC_DDRPHYC_DX0GSR1_DQSDFT_Msk = 0x30
	// Position of RVERR field.
	DDRPHYC_DDRPHYC_DX0GSR1_RVERR_Pos = 0xc
	// Bit mask of RVERR field.
	DDRPHYC_DDRPHYC_DX0GSR1_RVERR_Msk = 0x1000
	// Bit RVERR.
	DDRPHYC_DDRPHYC_DX0GSR1_RVERR = 0x1000
	// Position of RVIERR field.
	DDRPHYC_DDRPHYC_DX0GSR1_RVIERR_Pos = 0x10
	// Bit mask of RVIERR field.
	DDRPHYC_DDRPHYC_DX0GSR1_RVIERR_Msk = 0x10000
	// Bit RVIERR.
	DDRPHYC_DDRPHYC_DX0GSR1_RVIERR = 0x10000
	// Position of RVPASS field.
	DDRPHYC_DDRPHYC_DX0GSR1_RVPASS_Pos = 0x14
	// Bit mask of RVPASS field.
	DDRPHYC_DDRPHYC_DX0GSR1_RVPASS_Msk = 0x700000

	// DDRPHYC_DX0DLLCR: DDRPHYC byte lane 0 DLLC register
	// Position of SFBDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SFBDLY_Pos = 0x0
	// Bit mask of SFBDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SFBDLY_Msk = 0x7
	// Position of SFWDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SFWDLY_Pos = 0x3
	// Bit mask of SFWDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SFWDLY_Msk = 0x38
	// Position of MFBDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_MFBDLY_Pos = 0x6
	// Bit mask of MFBDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_MFBDLY_Msk = 0x1c0
	// Position of MFWDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_MFWDLY_Pos = 0x9
	// Bit mask of MFWDLY field.
	DDRPHYC_DDRPHYC_DX0DLLCR_MFWDLY_Msk = 0xe00
	// Position of SSTART field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SSTART_Pos = 0xc
	// Bit mask of SSTART field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SSTART_Msk = 0x3000
	// Position of SDPHASE field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SDPHASE_Pos = 0xe
	// Bit mask of SDPHASE field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SDPHASE_Msk = 0x3c000
	// Position of ATESTEN field.
	DDRPHYC_DDRPHYC_DX0DLLCR_ATESTEN_Pos = 0x12
	// Bit mask of ATESTEN field.
	DDRPHYC_DDRPHYC_DX0DLLCR_ATESTEN_Msk = 0x40000
	// Bit ATESTEN.
	DDRPHYC_DDRPHYC_DX0DLLCR_ATESTEN = 0x40000
	// Position of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SDLBMODE_Pos = 0x13
	// Bit mask of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX0DLLCR_SDLBMODE_Msk = 0x80000
	// Bit SDLBMODE.
	DDRPHYC_DDRPHYC_DX0DLLCR_SDLBMODE = 0x80000
	// Position of DLLSRST field.
	DDRPHYC_DDRPHYC_DX0DLLCR_DLLSRST_Pos = 0x1e
	// Bit mask of DLLSRST field.
	DDRPHYC_DDRPHYC_DX0DLLCR_DLLSRST_Msk = 0x40000000
	// Bit DLLSRST.
	DDRPHYC_DDRPHYC_DX0DLLCR_DLLSRST = 0x40000000
	// Position of DLLDIS field.
	DDRPHYC_DDRPHYC_DX0DLLCR_DLLDIS_Pos = 0x1f
	// Bit mask of DLLDIS field.
	DDRPHYC_DDRPHYC_DX0DLLCR_DLLDIS_Msk = 0x80000000
	// Bit DLLDIS.
	DDRPHYC_DDRPHYC_DX0DLLCR_DLLDIS = 0x80000000

	// DDRPHYC_DX0DQTR: DDRPHYC byte lane 0 DQT register
	// Position of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY0_Pos = 0x0
	// Bit mask of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY0_Msk = 0xf
	// Position of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY1_Pos = 0x4
	// Bit mask of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY1_Msk = 0xf0
	// Position of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY2_Pos = 0x8
	// Bit mask of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY2_Msk = 0xf00
	// Position of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY3_Pos = 0xc
	// Bit mask of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY3_Msk = 0xf000
	// Position of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY4_Pos = 0x10
	// Bit mask of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY4_Msk = 0xf0000
	// Position of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY5_Pos = 0x14
	// Bit mask of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY5_Msk = 0xf00000
	// Position of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY6_Pos = 0x18
	// Bit mask of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY6_Msk = 0xf000000
	// Position of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY7_Pos = 0x1c
	// Bit mask of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX0DQTR_DQDLY7_Msk = 0xf0000000

	// DDRPHYC_DX0DQSTR: DDRPHYC byte lane 0 DQST register
	// Position of R0DGSL field.
	DDRPHYC_DDRPHYC_DX0DQSTR_R0DGSL_Pos = 0x0
	// Bit mask of R0DGSL field.
	DDRPHYC_DDRPHYC_DX0DQSTR_R0DGSL_Msk = 0x7
	// Position of R0DGPS field.
	DDRPHYC_DDRPHYC_DX0DQSTR_R0DGPS_Pos = 0xc
	// Bit mask of R0DGPS field.
	DDRPHYC_DDRPHYC_DX0DQSTR_R0DGPS_Msk = 0x3000
	// Position of DQSDLY field.
	DDRPHYC_DDRPHYC_DX0DQSTR_DQSDLY_Pos = 0x14
	// Bit mask of DQSDLY field.
	DDRPHYC_DDRPHYC_DX0DQSTR_DQSDLY_Msk = 0x700000
	// Position of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX0DQSTR_DQSNDLY_Pos = 0x17
	// Bit mask of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX0DQSTR_DQSNDLY_Msk = 0x3800000
	// Position of DMDLY field.
	DDRPHYC_DDRPHYC_DX0DQSTR_DMDLY_Pos = 0x1a
	// Bit mask of DMDLY field.
	DDRPHYC_DDRPHYC_DX0DQSTR_DMDLY_Msk = 0x3c000000

	// DDRPHYC_DX1GCR: DDRPHYC byte lane 1 GC register
	// Position of DXEN field.
	DDRPHYC_DDRPHYC_DX1GCR_DXEN_Pos = 0x0
	// Bit mask of DXEN field.
	DDRPHYC_DDRPHYC_DX1GCR_DXEN_Msk = 0x1
	// Bit DXEN.
	DDRPHYC_DDRPHYC_DX1GCR_DXEN = 0x1
	// Position of DQSODT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQSODT_Pos = 0x1
	// Bit mask of DQSODT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQSODT_Msk = 0x2
	// Bit DQSODT.
	DDRPHYC_DDRPHYC_DX1GCR_DQSODT = 0x2
	// Position of DQODT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQODT_Pos = 0x2
	// Bit mask of DQODT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQODT_Msk = 0x4
	// Bit DQODT.
	DDRPHYC_DDRPHYC_DX1GCR_DQODT = 0x4
	// Position of DXIOM field.
	DDRPHYC_DDRPHYC_DX1GCR_DXIOM_Pos = 0x3
	// Bit mask of DXIOM field.
	DDRPHYC_DDRPHYC_DX1GCR_DXIOM_Msk = 0x8
	// Bit DXIOM.
	DDRPHYC_DDRPHYC_DX1GCR_DXIOM = 0x8
	// Position of DXPDD field.
	DDRPHYC_DDRPHYC_DX1GCR_DXPDD_Pos = 0x4
	// Bit mask of DXPDD field.
	DDRPHYC_DDRPHYC_DX1GCR_DXPDD_Msk = 0x10
	// Bit DXPDD.
	DDRPHYC_DDRPHYC_DX1GCR_DXPDD = 0x10
	// Position of DXPDR field.
	DDRPHYC_DDRPHYC_DX1GCR_DXPDR_Pos = 0x5
	// Bit mask of DXPDR field.
	DDRPHYC_DDRPHYC_DX1GCR_DXPDR_Msk = 0x20
	// Bit DXPDR.
	DDRPHYC_DDRPHYC_DX1GCR_DXPDR = 0x20
	// Position of DQSRPD field.
	DDRPHYC_DDRPHYC_DX1GCR_DQSRPD_Pos = 0x6
	// Bit mask of DQSRPD field.
	DDRPHYC_DDRPHYC_DX1GCR_DQSRPD_Msk = 0x40
	// Bit DQSRPD.
	DDRPHYC_DDRPHYC_DX1GCR_DQSRPD = 0x40
	// Position of DSEN field.
	DDRPHYC_DDRPHYC_DX1GCR_DSEN_Pos = 0x7
	// Bit mask of DSEN field.
	DDRPHYC_DDRPHYC_DX1GCR_DSEN_Msk = 0x180
	// Position of DQSRTT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQSRTT_Pos = 0x9
	// Bit mask of DQSRTT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQSRTT_Msk = 0x200
	// Bit DQSRTT.
	DDRPHYC_DDRPHYC_DX1GCR_DQSRTT = 0x200
	// Position of DQRTT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQRTT_Pos = 0xa
	// Bit mask of DQRTT field.
	DDRPHYC_DDRPHYC_DX1GCR_DQRTT_Msk = 0x400
	// Bit DQRTT.
	DDRPHYC_DDRPHYC_DX1GCR_DQRTT = 0x400
	// Position of RTTOH field.
	DDRPHYC_DDRPHYC_DX1GCR_RTTOH_Pos = 0xb
	// Bit mask of RTTOH field.
	DDRPHYC_DDRPHYC_DX1GCR_RTTOH_Msk = 0x1800
	// Position of RTTOAL field.
	DDRPHYC_DDRPHYC_DX1GCR_RTTOAL_Pos = 0xd
	// Bit mask of RTTOAL field.
	DDRPHYC_DDRPHYC_DX1GCR_RTTOAL_Msk = 0x2000
	// Bit RTTOAL.
	DDRPHYC_DDRPHYC_DX1GCR_RTTOAL = 0x2000
	// Position of R0RVSL field.
	DDRPHYC_DDRPHYC_DX1GCR_R0RVSL_Pos = 0xe
	// Bit mask of R0RVSL field.
	DDRPHYC_DDRPHYC_DX1GCR_R0RVSL_Msk = 0x1c000

	// DDRPHYC_DX1GSR0: DDRPHYC byte lane 1 GS register 0
	// Position of DTDONE field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTDONE_Pos = 0x0
	// Bit mask of DTDONE field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTDONE_Msk = 0x1
	// Bit DTDONE.
	DDRPHYC_DDRPHYC_DX1GSR0_DTDONE = 0x1
	// Position of DTERR field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTERR_Pos = 0x4
	// Bit mask of DTERR field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTERR_Msk = 0x10
	// Bit DTERR.
	DDRPHYC_DDRPHYC_DX1GSR0_DTERR = 0x10
	// Position of DTIERR field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTIERR_Pos = 0x8
	// Bit mask of DTIERR field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTIERR_Msk = 0x100
	// Bit DTIERR.
	DDRPHYC_DDRPHYC_DX1GSR0_DTIERR = 0x100
	// Position of DTPASS field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTPASS_Pos = 0xd
	// Bit mask of DTPASS field.
	DDRPHYC_DDRPHYC_DX1GSR0_DTPASS_Msk = 0xe000

	// DDRPHYC_DX1GSR1: DDRPHYC byte lane 1 GS register 1
	// Position of DFTERR field.
	DDRPHYC_DDRPHYC_DX1GSR1_DFTERR_Pos = 0x0
	// Bit mask of DFTERR field.
	DDRPHYC_DDRPHYC_DX1GSR1_DFTERR_Msk = 0x1
	// Bit DFTERR.
	DDRPHYC_DDRPHYC_DX1GSR1_DFTERR = 0x1
	// Position of DQSDFT field.
	DDRPHYC_DDRPHYC_DX1GSR1_DQSDFT_Pos = 0x4
	// Bit mask of DQSDFT field.
	DDRPHYC_DDRPHYC_DX1GSR1_DQSDFT_Msk = 0x30
	// Position of RVERR field.
	DDRPHYC_DDRPHYC_DX1GSR1_RVERR_Pos = 0xc
	// Bit mask of RVERR field.
	DDRPHYC_DDRPHYC_DX1GSR1_RVERR_Msk = 0x1000
	// Bit RVERR.
	DDRPHYC_DDRPHYC_DX1GSR1_RVERR = 0x1000
	// Position of RVIERR field.
	DDRPHYC_DDRPHYC_DX1GSR1_RVIERR_Pos = 0x10
	// Bit mask of RVIERR field.
	DDRPHYC_DDRPHYC_DX1GSR1_RVIERR_Msk = 0x10000
	// Bit RVIERR.
	DDRPHYC_DDRPHYC_DX1GSR1_RVIERR = 0x10000
	// Position of RVPASS field.
	DDRPHYC_DDRPHYC_DX1GSR1_RVPASS_Pos = 0x14
	// Bit mask of RVPASS field.
	DDRPHYC_DDRPHYC_DX1GSR1_RVPASS_Msk = 0x700000

	// DDRPHYC_DX1DLLCR: DDRPHYC byte lane 1 DLLC register
	// Position of SFBDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SFBDLY_Pos = 0x0
	// Bit mask of SFBDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SFBDLY_Msk = 0x7
	// Position of SFWDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SFWDLY_Pos = 0x3
	// Bit mask of SFWDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SFWDLY_Msk = 0x38
	// Position of MFBDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_MFBDLY_Pos = 0x6
	// Bit mask of MFBDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_MFBDLY_Msk = 0x1c0
	// Position of MFWDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_MFWDLY_Pos = 0x9
	// Bit mask of MFWDLY field.
	DDRPHYC_DDRPHYC_DX1DLLCR_MFWDLY_Msk = 0xe00
	// Position of SSTART field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SSTART_Pos = 0xc
	// Bit mask of SSTART field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SSTART_Msk = 0x3000
	// Position of SDPHASE field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SDPHASE_Pos = 0xe
	// Bit mask of SDPHASE field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SDPHASE_Msk = 0x3c000
	// Position of ATESTEN field.
	DDRPHYC_DDRPHYC_DX1DLLCR_ATESTEN_Pos = 0x12
	// Bit mask of ATESTEN field.
	DDRPHYC_DDRPHYC_DX1DLLCR_ATESTEN_Msk = 0x40000
	// Bit ATESTEN.
	DDRPHYC_DDRPHYC_DX1DLLCR_ATESTEN = 0x40000
	// Position of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SDLBMODE_Pos = 0x13
	// Bit mask of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX1DLLCR_SDLBMODE_Msk = 0x80000
	// Bit SDLBMODE.
	DDRPHYC_DDRPHYC_DX1DLLCR_SDLBMODE = 0x80000
	// Position of DLLSRST field.
	DDRPHYC_DDRPHYC_DX1DLLCR_DLLSRST_Pos = 0x1e
	// Bit mask of DLLSRST field.
	DDRPHYC_DDRPHYC_DX1DLLCR_DLLSRST_Msk = 0x40000000
	// Bit DLLSRST.
	DDRPHYC_DDRPHYC_DX1DLLCR_DLLSRST = 0x40000000
	// Position of DLLDIS field.
	DDRPHYC_DDRPHYC_DX1DLLCR_DLLDIS_Pos = 0x1f
	// Bit mask of DLLDIS field.
	DDRPHYC_DDRPHYC_DX1DLLCR_DLLDIS_Msk = 0x80000000
	// Bit DLLDIS.
	DDRPHYC_DDRPHYC_DX1DLLCR_DLLDIS = 0x80000000

	// DDRPHYC_DX1DQTR: DDRPHYC byte lane 1 DQT register
	// Position of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY0_Pos = 0x0
	// Bit mask of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY0_Msk = 0xf
	// Position of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY1_Pos = 0x4
	// Bit mask of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY1_Msk = 0xf0
	// Position of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY2_Pos = 0x8
	// Bit mask of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY2_Msk = 0xf00
	// Position of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY3_Pos = 0xc
	// Bit mask of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY3_Msk = 0xf000
	// Position of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY4_Pos = 0x10
	// Bit mask of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY4_Msk = 0xf0000
	// Position of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY5_Pos = 0x14
	// Bit mask of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY5_Msk = 0xf00000
	// Position of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY6_Pos = 0x18
	// Bit mask of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY6_Msk = 0xf000000
	// Position of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY7_Pos = 0x1c
	// Bit mask of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX1DQTR_DQDLY7_Msk = 0xf0000000

	// DDRPHYC_DX1DQSTR: DDRPHYC byte lane 1 DQST register
	// Position of R0DGSL field.
	DDRPHYC_DDRPHYC_DX1DQSTR_R0DGSL_Pos = 0x0
	// Bit mask of R0DGSL field.
	DDRPHYC_DDRPHYC_DX1DQSTR_R0DGSL_Msk = 0x7
	// Position of R0DGPS field.
	DDRPHYC_DDRPHYC_DX1DQSTR_R0DGPS_Pos = 0xc
	// Bit mask of R0DGPS field.
	DDRPHYC_DDRPHYC_DX1DQSTR_R0DGPS_Msk = 0x3000
	// Position of DQSDLY field.
	DDRPHYC_DDRPHYC_DX1DQSTR_DQSDLY_Pos = 0x14
	// Bit mask of DQSDLY field.
	DDRPHYC_DDRPHYC_DX1DQSTR_DQSDLY_Msk = 0x700000
	// Position of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX1DQSTR_DQSNDLY_Pos = 0x17
	// Bit mask of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX1DQSTR_DQSNDLY_Msk = 0x3800000
	// Position of DMDLY field.
	DDRPHYC_DDRPHYC_DX1DQSTR_DMDLY_Pos = 0x1a
	// Bit mask of DMDLY field.
	DDRPHYC_DDRPHYC_DX1DQSTR_DMDLY_Msk = 0x3c000000

	// DDRPHYC_DX2GCR: DDRPHYC byte lane 2 GC register
	// Position of DXEN field.
	DDRPHYC_DDRPHYC_DX2GCR_DXEN_Pos = 0x0
	// Bit mask of DXEN field.
	DDRPHYC_DDRPHYC_DX2GCR_DXEN_Msk = 0x1
	// Bit DXEN.
	DDRPHYC_DDRPHYC_DX2GCR_DXEN = 0x1
	// Position of DQSODT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQSODT_Pos = 0x1
	// Bit mask of DQSODT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQSODT_Msk = 0x2
	// Bit DQSODT.
	DDRPHYC_DDRPHYC_DX2GCR_DQSODT = 0x2
	// Position of DQODT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQODT_Pos = 0x2
	// Bit mask of DQODT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQODT_Msk = 0x4
	// Bit DQODT.
	DDRPHYC_DDRPHYC_DX2GCR_DQODT = 0x4
	// Position of DXIOM field.
	DDRPHYC_DDRPHYC_DX2GCR_DXIOM_Pos = 0x3
	// Bit mask of DXIOM field.
	DDRPHYC_DDRPHYC_DX2GCR_DXIOM_Msk = 0x8
	// Bit DXIOM.
	DDRPHYC_DDRPHYC_DX2GCR_DXIOM = 0x8
	// Position of DXPDD field.
	DDRPHYC_DDRPHYC_DX2GCR_DXPDD_Pos = 0x4
	// Bit mask of DXPDD field.
	DDRPHYC_DDRPHYC_DX2GCR_DXPDD_Msk = 0x10
	// Bit DXPDD.
	DDRPHYC_DDRPHYC_DX2GCR_DXPDD = 0x10
	// Position of DXPDR field.
	DDRPHYC_DDRPHYC_DX2GCR_DXPDR_Pos = 0x5
	// Bit mask of DXPDR field.
	DDRPHYC_DDRPHYC_DX2GCR_DXPDR_Msk = 0x20
	// Bit DXPDR.
	DDRPHYC_DDRPHYC_DX2GCR_DXPDR = 0x20
	// Position of DQSRPD field.
	DDRPHYC_DDRPHYC_DX2GCR_DQSRPD_Pos = 0x6
	// Bit mask of DQSRPD field.
	DDRPHYC_DDRPHYC_DX2GCR_DQSRPD_Msk = 0x40
	// Bit DQSRPD.
	DDRPHYC_DDRPHYC_DX2GCR_DQSRPD = 0x40
	// Position of DSEN field.
	DDRPHYC_DDRPHYC_DX2GCR_DSEN_Pos = 0x7
	// Bit mask of DSEN field.
	DDRPHYC_DDRPHYC_DX2GCR_DSEN_Msk = 0x180
	// Position of DQSRTT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQSRTT_Pos = 0x9
	// Bit mask of DQSRTT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQSRTT_Msk = 0x200
	// Bit DQSRTT.
	DDRPHYC_DDRPHYC_DX2GCR_DQSRTT = 0x200
	// Position of DQRTT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQRTT_Pos = 0xa
	// Bit mask of DQRTT field.
	DDRPHYC_DDRPHYC_DX2GCR_DQRTT_Msk = 0x400
	// Bit DQRTT.
	DDRPHYC_DDRPHYC_DX2GCR_DQRTT = 0x400
	// Position of RTTOH field.
	DDRPHYC_DDRPHYC_DX2GCR_RTTOH_Pos = 0xb
	// Bit mask of RTTOH field.
	DDRPHYC_DDRPHYC_DX2GCR_RTTOH_Msk = 0x1800
	// Position of RTTOAL field.
	DDRPHYC_DDRPHYC_DX2GCR_RTTOAL_Pos = 0xd
	// Bit mask of RTTOAL field.
	DDRPHYC_DDRPHYC_DX2GCR_RTTOAL_Msk = 0x2000
	// Bit RTTOAL.
	DDRPHYC_DDRPHYC_DX2GCR_RTTOAL = 0x2000
	// Position of R0RVSL field.
	DDRPHYC_DDRPHYC_DX2GCR_R0RVSL_Pos = 0xe
	// Bit mask of R0RVSL field.
	DDRPHYC_DDRPHYC_DX2GCR_R0RVSL_Msk = 0x1c000

	// DDRPHYC_DX2GSR0: DDRPHYC byte lane 2 GS register 0
	// Position of DTDONE field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTDONE_Pos = 0x0
	// Bit mask of DTDONE field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTDONE_Msk = 0x1
	// Bit DTDONE.
	DDRPHYC_DDRPHYC_DX2GSR0_DTDONE = 0x1
	// Position of DTERR field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTERR_Pos = 0x4
	// Bit mask of DTERR field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTERR_Msk = 0x10
	// Bit DTERR.
	DDRPHYC_DDRPHYC_DX2GSR0_DTERR = 0x10
	// Position of DTIERR field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTIERR_Pos = 0x8
	// Bit mask of DTIERR field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTIERR_Msk = 0x100
	// Bit DTIERR.
	DDRPHYC_DDRPHYC_DX2GSR0_DTIERR = 0x100
	// Position of DTPASS field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTPASS_Pos = 0xd
	// Bit mask of DTPASS field.
	DDRPHYC_DDRPHYC_DX2GSR0_DTPASS_Msk = 0xe000

	// DDRPHYC_DX2GSR1: DDRPHYC byte lane 2 GS register 1
	// Position of DFTERR field.
	DDRPHYC_DDRPHYC_DX2GSR1_DFTERR_Pos = 0x0
	// Bit mask of DFTERR field.
	DDRPHYC_DDRPHYC_DX2GSR1_DFTERR_Msk = 0x1
	// Bit DFTERR.
	DDRPHYC_DDRPHYC_DX2GSR1_DFTERR = 0x1
	// Position of DQSDFT field.
	DDRPHYC_DDRPHYC_DX2GSR1_DQSDFT_Pos = 0x4
	// Bit mask of DQSDFT field.
	DDRPHYC_DDRPHYC_DX2GSR1_DQSDFT_Msk = 0x30
	// Position of RVERR field.
	DDRPHYC_DDRPHYC_DX2GSR1_RVERR_Pos = 0xc
	// Bit mask of RVERR field.
	DDRPHYC_DDRPHYC_DX2GSR1_RVERR_Msk = 0x1000
	// Bit RVERR.
	DDRPHYC_DDRPHYC_DX2GSR1_RVERR = 0x1000
	// Position of RVIERR field.
	DDRPHYC_DDRPHYC_DX2GSR1_RVIERR_Pos = 0x10
	// Bit mask of RVIERR field.
	DDRPHYC_DDRPHYC_DX2GSR1_RVIERR_Msk = 0x10000
	// Bit RVIERR.
	DDRPHYC_DDRPHYC_DX2GSR1_RVIERR = 0x10000
	// Position of RVPASS field.
	DDRPHYC_DDRPHYC_DX2GSR1_RVPASS_Pos = 0x14
	// Bit mask of RVPASS field.
	DDRPHYC_DDRPHYC_DX2GSR1_RVPASS_Msk = 0x700000

	// DDRPHYC_DX2DLLCR: DDRPHYC byte lane 2 DLLC register
	// Position of SFBDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SFBDLY_Pos = 0x0
	// Bit mask of SFBDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SFBDLY_Msk = 0x7
	// Position of SFWDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SFWDLY_Pos = 0x3
	// Bit mask of SFWDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SFWDLY_Msk = 0x38
	// Position of MFBDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_MFBDLY_Pos = 0x6
	// Bit mask of MFBDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_MFBDLY_Msk = 0x1c0
	// Position of MFWDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_MFWDLY_Pos = 0x9
	// Bit mask of MFWDLY field.
	DDRPHYC_DDRPHYC_DX2DLLCR_MFWDLY_Msk = 0xe00
	// Position of SSTART field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SSTART_Pos = 0xc
	// Bit mask of SSTART field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SSTART_Msk = 0x3000
	// Position of SDPHASE field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SDPHASE_Pos = 0xe
	// Bit mask of SDPHASE field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SDPHASE_Msk = 0x3c000
	// Position of ATESTEN field.
	DDRPHYC_DDRPHYC_DX2DLLCR_ATESTEN_Pos = 0x12
	// Bit mask of ATESTEN field.
	DDRPHYC_DDRPHYC_DX2DLLCR_ATESTEN_Msk = 0x40000
	// Bit ATESTEN.
	DDRPHYC_DDRPHYC_DX2DLLCR_ATESTEN = 0x40000
	// Position of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SDLBMODE_Pos = 0x13
	// Bit mask of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX2DLLCR_SDLBMODE_Msk = 0x80000
	// Bit SDLBMODE.
	DDRPHYC_DDRPHYC_DX2DLLCR_SDLBMODE = 0x80000
	// Position of DLLSRST field.
	DDRPHYC_DDRPHYC_DX2DLLCR_DLLSRST_Pos = 0x1e
	// Bit mask of DLLSRST field.
	DDRPHYC_DDRPHYC_DX2DLLCR_DLLSRST_Msk = 0x40000000
	// Bit DLLSRST.
	DDRPHYC_DDRPHYC_DX2DLLCR_DLLSRST = 0x40000000
	// Position of DLLDIS field.
	DDRPHYC_DDRPHYC_DX2DLLCR_DLLDIS_Pos = 0x1f
	// Bit mask of DLLDIS field.
	DDRPHYC_DDRPHYC_DX2DLLCR_DLLDIS_Msk = 0x80000000
	// Bit DLLDIS.
	DDRPHYC_DDRPHYC_DX2DLLCR_DLLDIS = 0x80000000

	// DDRPHYC_DX2DQTR: DDRPHYC byte lane 2 DQT register
	// Position of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY0_Pos = 0x0
	// Bit mask of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY0_Msk = 0xf
	// Position of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY1_Pos = 0x4
	// Bit mask of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY1_Msk = 0xf0
	// Position of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY2_Pos = 0x8
	// Bit mask of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY2_Msk = 0xf00
	// Position of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY3_Pos = 0xc
	// Bit mask of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY3_Msk = 0xf000
	// Position of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY4_Pos = 0x10
	// Bit mask of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY4_Msk = 0xf0000
	// Position of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY5_Pos = 0x14
	// Bit mask of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY5_Msk = 0xf00000
	// Position of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY6_Pos = 0x18
	// Bit mask of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY6_Msk = 0xf000000
	// Position of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY7_Pos = 0x1c
	// Bit mask of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX2DQTR_DQDLY7_Msk = 0xf0000000

	// DDRPHYC_DX2DQSTR: DDRPHYC byte lane 2 DQST register
	// Position of R0DGSL field.
	DDRPHYC_DDRPHYC_DX2DQSTR_R0DGSL_Pos = 0x0
	// Bit mask of R0DGSL field.
	DDRPHYC_DDRPHYC_DX2DQSTR_R0DGSL_Msk = 0x7
	// Position of R0DGPS field.
	DDRPHYC_DDRPHYC_DX2DQSTR_R0DGPS_Pos = 0xc
	// Bit mask of R0DGPS field.
	DDRPHYC_DDRPHYC_DX2DQSTR_R0DGPS_Msk = 0x3000
	// Position of DQSDLY field.
	DDRPHYC_DDRPHYC_DX2DQSTR_DQSDLY_Pos = 0x14
	// Bit mask of DQSDLY field.
	DDRPHYC_DDRPHYC_DX2DQSTR_DQSDLY_Msk = 0x700000
	// Position of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX2DQSTR_DQSNDLY_Pos = 0x17
	// Bit mask of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX2DQSTR_DQSNDLY_Msk = 0x3800000
	// Position of DMDLY field.
	DDRPHYC_DDRPHYC_DX2DQSTR_DMDLY_Pos = 0x1a
	// Bit mask of DMDLY field.
	DDRPHYC_DDRPHYC_DX2DQSTR_DMDLY_Msk = 0x3c000000

	// DDRPHYC_DX3GCR: DDRPHYC byte lane 3 GC register
	// Position of DXEN field.
	DDRPHYC_DDRPHYC_DX3GCR_DXEN_Pos = 0x0
	// Bit mask of DXEN field.
	DDRPHYC_DDRPHYC_DX3GCR_DXEN_Msk = 0x1
	// Bit DXEN.
	DDRPHYC_DDRPHYC_DX3GCR_DXEN = 0x1
	// Position of DQSODT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQSODT_Pos = 0x1
	// Bit mask of DQSODT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQSODT_Msk = 0x2
	// Bit DQSODT.
	DDRPHYC_DDRPHYC_DX3GCR_DQSODT = 0x2
	// Position of DQODT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQODT_Pos = 0x2
	// Bit mask of DQODT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQODT_Msk = 0x4
	// Bit DQODT.
	DDRPHYC_DDRPHYC_DX3GCR_DQODT = 0x4
	// Position of DXIOM field.
	DDRPHYC_DDRPHYC_DX3GCR_DXIOM_Pos = 0x3
	// Bit mask of DXIOM field.
	DDRPHYC_DDRPHYC_DX3GCR_DXIOM_Msk = 0x8
	// Bit DXIOM.
	DDRPHYC_DDRPHYC_DX3GCR_DXIOM = 0x8
	// Position of DXPDD field.
	DDRPHYC_DDRPHYC_DX3GCR_DXPDD_Pos = 0x4
	// Bit mask of DXPDD field.
	DDRPHYC_DDRPHYC_DX3GCR_DXPDD_Msk = 0x10
	// Bit DXPDD.
	DDRPHYC_DDRPHYC_DX3GCR_DXPDD = 0x10
	// Position of DXPDR field.
	DDRPHYC_DDRPHYC_DX3GCR_DXPDR_Pos = 0x5
	// Bit mask of DXPDR field.
	DDRPHYC_DDRPHYC_DX3GCR_DXPDR_Msk = 0x20
	// Bit DXPDR.
	DDRPHYC_DDRPHYC_DX3GCR_DXPDR = 0x20
	// Position of DQSRPD field.
	DDRPHYC_DDRPHYC_DX3GCR_DQSRPD_Pos = 0x6
	// Bit mask of DQSRPD field.
	DDRPHYC_DDRPHYC_DX3GCR_DQSRPD_Msk = 0x40
	// Bit DQSRPD.
	DDRPHYC_DDRPHYC_DX3GCR_DQSRPD = 0x40
	// Position of DSEN field.
	DDRPHYC_DDRPHYC_DX3GCR_DSEN_Pos = 0x7
	// Bit mask of DSEN field.
	DDRPHYC_DDRPHYC_DX3GCR_DSEN_Msk = 0x180
	// Position of DQSRTT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQSRTT_Pos = 0x9
	// Bit mask of DQSRTT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQSRTT_Msk = 0x200
	// Bit DQSRTT.
	DDRPHYC_DDRPHYC_DX3GCR_DQSRTT = 0x200
	// Position of DQRTT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQRTT_Pos = 0xa
	// Bit mask of DQRTT field.
	DDRPHYC_DDRPHYC_DX3GCR_DQRTT_Msk = 0x400
	// Bit DQRTT.
	DDRPHYC_DDRPHYC_DX3GCR_DQRTT = 0x400
	// Position of RTTOH field.
	DDRPHYC_DDRPHYC_DX3GCR_RTTOH_Pos = 0xb
	// Bit mask of RTTOH field.
	DDRPHYC_DDRPHYC_DX3GCR_RTTOH_Msk = 0x1800
	// Position of RTTOAL field.
	DDRPHYC_DDRPHYC_DX3GCR_RTTOAL_Pos = 0xd
	// Bit mask of RTTOAL field.
	DDRPHYC_DDRPHYC_DX3GCR_RTTOAL_Msk = 0x2000
	// Bit RTTOAL.
	DDRPHYC_DDRPHYC_DX3GCR_RTTOAL = 0x2000
	// Position of R0RVSL field.
	DDRPHYC_DDRPHYC_DX3GCR_R0RVSL_Pos = 0xe
	// Bit mask of R0RVSL field.
	DDRPHYC_DDRPHYC_DX3GCR_R0RVSL_Msk = 0x1c000

	// DDRPHYC_DX3GSR0: DDRPHYC byte lane 3 GS register 0
	// Position of DTDONE field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTDONE_Pos = 0x0
	// Bit mask of DTDONE field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTDONE_Msk = 0x1
	// Bit DTDONE.
	DDRPHYC_DDRPHYC_DX3GSR0_DTDONE = 0x1
	// Position of DTERR field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTERR_Pos = 0x4
	// Bit mask of DTERR field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTERR_Msk = 0x10
	// Bit DTERR.
	DDRPHYC_DDRPHYC_DX3GSR0_DTERR = 0x10
	// Position of DTIERR field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTIERR_Pos = 0x8
	// Bit mask of DTIERR field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTIERR_Msk = 0x100
	// Bit DTIERR.
	DDRPHYC_DDRPHYC_DX3GSR0_DTIERR = 0x100
	// Position of DTPASS field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTPASS_Pos = 0xd
	// Bit mask of DTPASS field.
	DDRPHYC_DDRPHYC_DX3GSR0_DTPASS_Msk = 0xe000

	// DDRPHYC_DX3GSR1: DDRPHYC byte lane 3 GS register 1
	// Position of DFTERR field.
	DDRPHYC_DDRPHYC_DX3GSR1_DFTERR_Pos = 0x0
	// Bit mask of DFTERR field.
	DDRPHYC_DDRPHYC_DX3GSR1_DFTERR_Msk = 0x1
	// Bit DFTERR.
	DDRPHYC_DDRPHYC_DX3GSR1_DFTERR = 0x1
	// Position of DQSDFT field.
	DDRPHYC_DDRPHYC_DX3GSR1_DQSDFT_Pos = 0x4
	// Bit mask of DQSDFT field.
	DDRPHYC_DDRPHYC_DX3GSR1_DQSDFT_Msk = 0x30
	// Position of RVERR field.
	DDRPHYC_DDRPHYC_DX3GSR1_RVERR_Pos = 0xc
	// Bit mask of RVERR field.
	DDRPHYC_DDRPHYC_DX3GSR1_RVERR_Msk = 0x1000
	// Bit RVERR.
	DDRPHYC_DDRPHYC_DX3GSR1_RVERR = 0x1000
	// Position of RVIERR field.
	DDRPHYC_DDRPHYC_DX3GSR1_RVIERR_Pos = 0x10
	// Bit mask of RVIERR field.
	DDRPHYC_DDRPHYC_DX3GSR1_RVIERR_Msk = 0x10000
	// Bit RVIERR.
	DDRPHYC_DDRPHYC_DX3GSR1_RVIERR = 0x10000
	// Position of RVPASS field.
	DDRPHYC_DDRPHYC_DX3GSR1_RVPASS_Pos = 0x14
	// Bit mask of RVPASS field.
	DDRPHYC_DDRPHYC_DX3GSR1_RVPASS_Msk = 0x700000

	// DDRPHYC_DX3DLLCR: DDRPHYC byte lane 3 DLLC register
	// Position of SFBDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SFBDLY_Pos = 0x0
	// Bit mask of SFBDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SFBDLY_Msk = 0x7
	// Position of SFWDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SFWDLY_Pos = 0x3
	// Bit mask of SFWDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SFWDLY_Msk = 0x38
	// Position of MFBDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_MFBDLY_Pos = 0x6
	// Bit mask of MFBDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_MFBDLY_Msk = 0x1c0
	// Position of MFWDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_MFWDLY_Pos = 0x9
	// Bit mask of MFWDLY field.
	DDRPHYC_DDRPHYC_DX3DLLCR_MFWDLY_Msk = 0xe00
	// Position of SSTART field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SSTART_Pos = 0xc
	// Bit mask of SSTART field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SSTART_Msk = 0x3000
	// Position of SDPHASE field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SDPHASE_Pos = 0xe
	// Bit mask of SDPHASE field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SDPHASE_Msk = 0x3c000
	// Position of ATESTEN field.
	DDRPHYC_DDRPHYC_DX3DLLCR_ATESTEN_Pos = 0x12
	// Bit mask of ATESTEN field.
	DDRPHYC_DDRPHYC_DX3DLLCR_ATESTEN_Msk = 0x40000
	// Bit ATESTEN.
	DDRPHYC_DDRPHYC_DX3DLLCR_ATESTEN = 0x40000
	// Position of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SDLBMODE_Pos = 0x13
	// Bit mask of SDLBMODE field.
	DDRPHYC_DDRPHYC_DX3DLLCR_SDLBMODE_Msk = 0x80000
	// Bit SDLBMODE.
	DDRPHYC_DDRPHYC_DX3DLLCR_SDLBMODE = 0x80000
	// Position of DLLSRST field.
	DDRPHYC_DDRPHYC_DX3DLLCR_DLLSRST_Pos = 0x1e
	// Bit mask of DLLSRST field.
	DDRPHYC_DDRPHYC_DX3DLLCR_DLLSRST_Msk = 0x40000000
	// Bit DLLSRST.
	DDRPHYC_DDRPHYC_DX3DLLCR_DLLSRST = 0x40000000
	// Position of DLLDIS field.
	DDRPHYC_DDRPHYC_DX3DLLCR_DLLDIS_Pos = 0x1f
	// Bit mask of DLLDIS field.
	DDRPHYC_DDRPHYC_DX3DLLCR_DLLDIS_Msk = 0x80000000
	// Bit DLLDIS.
	DDRPHYC_DDRPHYC_DX3DLLCR_DLLDIS = 0x80000000

	// DDRPHYC_DX3DQTR: DDRPHYC byte lane 3 DQT register
	// Position of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY0_Pos = 0x0
	// Bit mask of DQDLY0 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY0_Msk = 0xf
	// Position of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY1_Pos = 0x4
	// Bit mask of DQDLY1 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY1_Msk = 0xf0
	// Position of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY2_Pos = 0x8
	// Bit mask of DQDLY2 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY2_Msk = 0xf00
	// Position of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY3_Pos = 0xc
	// Bit mask of DQDLY3 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY3_Msk = 0xf000
	// Position of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY4_Pos = 0x10
	// Bit mask of DQDLY4 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY4_Msk = 0xf0000
	// Position of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY5_Pos = 0x14
	// Bit mask of DQDLY5 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY5_Msk = 0xf00000
	// Position of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY6_Pos = 0x18
	// Bit mask of DQDLY6 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY6_Msk = 0xf000000
	// Position of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY7_Pos = 0x1c
	// Bit mask of DQDLY7 field.
	DDRPHYC_DDRPHYC_DX3DQTR_DQDLY7_Msk = 0xf0000000

	// DDRPHYC_DX3DQSTR: DDRPHYC byte lane 3 DQST register
	// Position of R0DGSL field.
	DDRPHYC_DDRPHYC_DX3DQSTR_R0DGSL_Pos = 0x0
	// Bit mask of R0DGSL field.
	DDRPHYC_DDRPHYC_DX3DQSTR_R0DGSL_Msk = 0x7
	// Position of R0DGPS field.
	DDRPHYC_DDRPHYC_DX3DQSTR_R0DGPS_Pos = 0xc
	// Bit mask of R0DGPS field.
	DDRPHYC_DDRPHYC_DX3DQSTR_R0DGPS_Msk = 0x3000
	// Position of DQSDLY field.
	DDRPHYC_DDRPHYC_DX3DQSTR_DQSDLY_Pos = 0x14
	// Bit mask of DQSDLY field.
	DDRPHYC_DDRPHYC_DX3DQSTR_DQSDLY_Msk = 0x700000
	// Position of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX3DQSTR_DQSNDLY_Pos = 0x17
	// Bit mask of DQSNDLY field.
	DDRPHYC_DDRPHYC_DX3DQSTR_DQSNDLY_Msk = 0x3800000
	// Position of DMDLY field.
	DDRPHYC_DDRPHYC_DX3DQSTR_DMDLY_Pos = 0x1a
	// Bit mask of DMDLY field.
	DDRPHYC_DDRPHYC_DX3DQSTR_DMDLY_Msk = 0x3c000000
)

// Bitfields for DFSDM1: DFSDM1
const (
	// DFSDM_CH0CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH0CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH0CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH0CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH0CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH0CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH0CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH0CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH0CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH0CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH0CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH0CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH0CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH0CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH0CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH0CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH0CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH0CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH0CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH0CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH0CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH0CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH0CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH0CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH0CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH0CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH0CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH0CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH0CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH0CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH0CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH0CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH0CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH0CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH0AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH0AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH0AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH0AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH0AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH0AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH0AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH0AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH0AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH0WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH0WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH0WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH0DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH0DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH0DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH0DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH0DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH0DLYR: DFSDM channel 0 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH0DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH0DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_CH1CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH1CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH1CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH1CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH1CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH1CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH1CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH1CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH1CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH1CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH1CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH1CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH1CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH1CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH1CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH1CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH1CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH1CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH1CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH1CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH1CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH1CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH1CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH1CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH1CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH1CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH1CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH1CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH1CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH1CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH1CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH1CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH1CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH1CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH1AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH1AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH1AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH1AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH1AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH1AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH1AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH1AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH1AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH1WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH1WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH1WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH1DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH1DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH1DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH1DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH1DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH1DLYR: DFSDM channel 1 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH1DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH1DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_CH2CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH2CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH2CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH2CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH2CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH2CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH2CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH2CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH2CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH2CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH2CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH2CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH2CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH2CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH2CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH2CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH2CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH2CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH2CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH2CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH2CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH2CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH2CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH2CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH2CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH2CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH2CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH2CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH2CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH2CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH2CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH2CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH2CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH2CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH2AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH2AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH2AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH2AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH2AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH2AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH2AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH2AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH2AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH2WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH2WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH2WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH2DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH2DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH2DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH2DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH2DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH2DLYR: DFSDM channel 2 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH2DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH2DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_CH3CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH3CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH3CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH3CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH3CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH3CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH3CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH3CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH3CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH3CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH3CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH3CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH3CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH3CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH3CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH3CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH3CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH3CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH3CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH3CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH3CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH3CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH3CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH3CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH3CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH3CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH3CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH3CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH3CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH3CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH3CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH3CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH3CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH3CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH3AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH3AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH3AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH3AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH3AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH3AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH3AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH3AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH3AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH3WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH3WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH3WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH3DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH3DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH3DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH3DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH3DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH3DLYR: DFSDM channel 3 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH3DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH3DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_CH4CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH4CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH4CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH4CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH4CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH4CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH4CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH4CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH4CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH4CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH4CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH4CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH4CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH4CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH4CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH4CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH4CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH4CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH4CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH4CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH4CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH4CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH4CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH4CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH4CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH4CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH4CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH4CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH4CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH4CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH4CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH4CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH4CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH4CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH4AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH4AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH4AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH4AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH4AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH4AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH4AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH4AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH4AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH4WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH4WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH4WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH4DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH4DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH4DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH4DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH4DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH4DLYR: DFSDM channel 4 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH4DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH4DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_CH5CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH5CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH5CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH5CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH5CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH5CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH5CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH5CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH5CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH5CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH5CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH5CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH5CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH5CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH5CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH5CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH5CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH5CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH5CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH5CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH5CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH5CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH5CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH5CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH5CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH5CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH5CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH5CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH5CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH5CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH5CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH5CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH5CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH5CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH5AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH5AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH5AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH5AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH5AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH5AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH5AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH5AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH5AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH5WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH5WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH5WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH5DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH5DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH5DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH5DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH5DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH5DLYR: DFSDM channel 5 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH5DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH5DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_CH6CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH6CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH6CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH6CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH6CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH6CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH6CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH6CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH6CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH6CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH6CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH6CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH6CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH6CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH6CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH6CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH6CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH6CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH6CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH6CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH6CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH6CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH6CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH6CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH6CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH6CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH6CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH6CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH6CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH6CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH6CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH6CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH6CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH6CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH6AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH6AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH6AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH6AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH6AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH6AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH6AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH6AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH6AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH6WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH6WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH6WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH6DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH6DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH6DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH6DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH6DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH6DLYR: DFSDM channel 6 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH6DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH6DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_CH7CFGR1: This register specifies the parameters used by channel y.
	// Position of SITP field.
	DFSDM1_DFSDM_CH7CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM1_DFSDM_CH7CFGR1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM1_DFSDM_CH7CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM1_DFSDM_CH7CFGR1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM1_DFSDM_CH7CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM1_DFSDM_CH7CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM1_DFSDM_CH7CFGR1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM1_DFSDM_CH7CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM1_DFSDM_CH7CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM1_DFSDM_CH7CFGR1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM1_DFSDM_CH7CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM1_DFSDM_CH7CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM1_DFSDM_CH7CFGR1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM1_DFSDM_CH7CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM1_DFSDM_CH7CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM1_DFSDM_CH7CFGR1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM1_DFSDM_CH7CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM1_DFSDM_CH7CFGR1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM1_DFSDM_CH7CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM1_DFSDM_CH7CFGR1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM1_DFSDM_CH7CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM1_DFSDM_CH7CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM1_DFSDM_CH7CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM1_DFSDM_CH7CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM1_DFSDM_CH7CFGR1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM1_DFSDM_CH7CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM1_DFSDM_CH7CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM1_DFSDM_CH7CFGR1_DFSDMEN = 0x80000000

	// DFSDM_CH7CFGR2: This register specifies the parameters used by channel y.
	// Position of DTRBS field.
	DFSDM1_DFSDM_CH7CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM1_DFSDM_CH7CFGR2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM1_DFSDM_CH7CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM1_DFSDM_CH7CFGR2_OFFSET_Msk = 0xffffff00

	// DFSDM_CH7AWSCDR: Short-circuit detector and analog watchdog settings for channel y.
	// Position of SCDT field.
	DFSDM1_DFSDM_CH7AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM1_DFSDM_CH7AWSCDR_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM1_DFSDM_CH7AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM1_DFSDM_CH7AWSCDR_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM1_DFSDM_CH7AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM1_DFSDM_CH7AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM1_DFSDM_CH7AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM1_DFSDM_CH7AWSCDR_AWFORD_Msk = 0xc00000

	// DFSDM_CH7WDATR: This register contains the data resulting from the analog watchdog filter associated to the input channel y.
	// Position of WDATA field.
	DFSDM1_DFSDM_CH7WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM1_DFSDM_CH7WDATR_WDATA_Msk = 0xffff

	// DFSDM_CH7DATINR: This register contains 16-bit input data to be processed by DFSDM filter module.
	// Position of INDAT0 field.
	DFSDM1_DFSDM_CH7DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM1_DFSDM_CH7DATINR_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM1_DFSDM_CH7DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM1_DFSDM_CH7DATINR_INDAT1_Msk = 0xffff0000

	// DFSDM_CH7DLYR: DFSDM channel 7 delay register
	// Position of PLSSKP field.
	DFSDM1_DFSDM_CH7DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM1_DFSDM_CH7DLYR_PLSSKP_Msk = 0x3f

	// DFSDM_FLT0CR1: DFSDM filter 0 control register 1
	// Position of DFEN field.
	DFSDM1_DFSDM_FLT0CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM1_DFSDM_FLT0CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM1_DFSDM_FLT0CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM1_DFSDM_FLT0CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM1_DFSDM_FLT0CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM1_DFSDM_FLT0CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM1_DFSDM_FLT0CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM1_DFSDM_FLT0CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM1_DFSDM_FLT0CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM1_DFSDM_FLT0CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM1_DFSDM_FLT0CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM1_DFSDM_FLT0CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM1_DFSDM_FLT0CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM1_DFSDM_FLT0CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM1_DFSDM_FLT0CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM1_DFSDM_FLT0CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM1_DFSDM_FLT0CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM1_DFSDM_FLT0CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM1_DFSDM_FLT0CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM1_DFSDM_FLT0CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM1_DFSDM_FLT0CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM1_DFSDM_FLT0CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM1_DFSDM_FLT0CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM1_DFSDM_FLT0CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM1_DFSDM_FLT0CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM1_DFSDM_FLT0CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM1_DFSDM_FLT0CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM1_DFSDM_FLT0CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM1_DFSDM_FLT0CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM1_DFSDM_FLT0CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM1_DFSDM_FLT0CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM1_DFSDM_FLT0CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM1_DFSDM_FLT0CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM1_DFSDM_FLT0CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM1_DFSDM_FLT0CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM1_DFSDM_FLT0CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM1_DFSDM_FLT0CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM1_DFSDM_FLT0CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM1_DFSDM_FLT0CR1_AWFSEL = 0x40000000

	// DFSDM_FLT0CR2: DFSDM filter 0 control register 2
	// Position of JEOCIE field.
	DFSDM1_DFSDM_FLT0CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM1_DFSDM_FLT0CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM1_DFSDM_FLT0CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM1_DFSDM_FLT0CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM1_DFSDM_FLT0CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM1_DFSDM_FLT0CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM1_DFSDM_FLT0CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM1_DFSDM_FLT0CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM1_DFSDM_FLT0CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM1_DFSDM_FLT0CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM1_DFSDM_FLT0CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM1_DFSDM_FLT0CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM1_DFSDM_FLT0CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM1_DFSDM_FLT0CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM1_DFSDM_FLT0CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM1_DFSDM_FLT0CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM1_DFSDM_FLT0CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM1_DFSDM_FLT0CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM1_DFSDM_FLT0CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM1_DFSDM_FLT0CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM1_DFSDM_FLT0CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM1_DFSDM_FLT0CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM1_DFSDM_FLT0CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM1_DFSDM_FLT0CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM1_DFSDM_FLT0CR2_AWDCH_Msk = 0xff0000

	// DFSDM_FLT0ISR: DFSDM filter 0 interrupt and status register
	// Position of JEOCF field.
	DFSDM1_DFSDM_FLT0ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM1_DFSDM_FLT0ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM1_DFSDM_FLT0ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM1_DFSDM_FLT0ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM1_DFSDM_FLT0ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM1_DFSDM_FLT0ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM1_DFSDM_FLT0ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM1_DFSDM_FLT0ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM1_DFSDM_FLT0ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM1_DFSDM_FLT0ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM1_DFSDM_FLT0ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM1_DFSDM_FLT0ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM1_DFSDM_FLT0ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM1_DFSDM_FLT0ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM1_DFSDM_FLT0ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM1_DFSDM_FLT0ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM1_DFSDM_FLT0ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM1_DFSDM_FLT0ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM1_DFSDM_FLT0ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM1_DFSDM_FLT0ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM1_DFSDM_FLT0ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM1_DFSDM_FLT0ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM1_DFSDM_FLT0ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM1_DFSDM_FLT0ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM1_DFSDM_FLT0ISR_SCDF_Msk = 0xff000000

	// DFSDM_FLT0ICR: DFSDM filter 0 interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM1_DFSDM_FLT0ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM1_DFSDM_FLT0ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM1_DFSDM_FLT0ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM1_DFSDM_FLT0ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM1_DFSDM_FLT0ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM1_DFSDM_FLT0ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM1_DFSDM_FLT0ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM1_DFSDM_FLT0ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM1_DFSDM_FLT0ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM1_DFSDM_FLT0ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM_FLT0JCHGR: DFSDM filter 0 injected channel group selection register
	// Position of JCHG field.
	DFSDM1_DFSDM_FLT0JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM1_DFSDM_FLT0JCHGR_JCHG_Msk = 0xff

	// DFSDM_FLT0FCR: DFSDM filter 0 control register
	// Position of IOSR field.
	DFSDM1_DFSDM_FLT0FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM1_DFSDM_FLT0FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM1_DFSDM_FLT0FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM1_DFSDM_FLT0FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM1_DFSDM_FLT0FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM1_DFSDM_FLT0FCR_FORD_Msk = 0xe0000000

	// DFSDM_FLT0JDATAR: DFSDM filter 0 data register for injected group
	// Position of JDATACH field.
	DFSDM1_DFSDM_FLT0JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM1_DFSDM_FLT0JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM1_DFSDM_FLT0JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM1_DFSDM_FLT0JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM_FLT0RDATAR: DFSDM filter 0 data register for the regular channel
	// Position of RDATACH field.
	DFSDM1_DFSDM_FLT0RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM1_DFSDM_FLT0RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM1_DFSDM_FLT0RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM1_DFSDM_FLT0RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM1_DFSDM_FLT0RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM1_DFSDM_FLT0RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM1_DFSDM_FLT0RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM_FLT0AWHTR: DFSDM filter 0 analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM1_DFSDM_FLT0AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM1_DFSDM_FLT0AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM1_DFSDM_FLT0AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM1_DFSDM_FLT0AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM_FLT0AWLTR: DFSDM filter 0 analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM1_DFSDM_FLT0AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM1_DFSDM_FLT0AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM1_DFSDM_FLT0AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM1_DFSDM_FLT0AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM_FLT0AWSR: DFSDM filter 0 analog watchdog status register
	// Position of AWLTF field.
	DFSDM1_DFSDM_FLT0AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM1_DFSDM_FLT0AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM1_DFSDM_FLT0AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM1_DFSDM_FLT0AWSR_AWHTF_Msk = 0xff00

	// DFSDM_FLT0AWCFR: DFSDM filter 0 analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM1_DFSDM_FLT0AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM1_DFSDM_FLT0AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM1_DFSDM_FLT0AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM1_DFSDM_FLT0AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM_FLT0EXMAX: DFSDM filter 0 extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM1_DFSDM_FLT0EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM1_DFSDM_FLT0EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM1_DFSDM_FLT0EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM1_DFSDM_FLT0EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM_FLT0EXMIN: DFSDM filter 0 extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM1_DFSDM_FLT0EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM1_DFSDM_FLT0EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM1_DFSDM_FLT0EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM1_DFSDM_FLT0EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM_FLT0CNVTIMR: DFSDM filter 0 conversion timer register
	// Position of CNVCNT field.
	DFSDM1_DFSDM_FLT0CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM1_DFSDM_FLT0CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM_FLT1CR1: DFSDM filter 1 control register 1
	// Position of DFEN field.
	DFSDM1_DFSDM_FLT1CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM1_DFSDM_FLT1CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM1_DFSDM_FLT1CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM1_DFSDM_FLT1CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM1_DFSDM_FLT1CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM1_DFSDM_FLT1CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM1_DFSDM_FLT1CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM1_DFSDM_FLT1CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM1_DFSDM_FLT1CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM1_DFSDM_FLT1CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM1_DFSDM_FLT1CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM1_DFSDM_FLT1CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM1_DFSDM_FLT1CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM1_DFSDM_FLT1CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM1_DFSDM_FLT1CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM1_DFSDM_FLT1CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM1_DFSDM_FLT1CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM1_DFSDM_FLT1CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM1_DFSDM_FLT1CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM1_DFSDM_FLT1CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM1_DFSDM_FLT1CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM1_DFSDM_FLT1CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM1_DFSDM_FLT1CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM1_DFSDM_FLT1CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM1_DFSDM_FLT1CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM1_DFSDM_FLT1CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM1_DFSDM_FLT1CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM1_DFSDM_FLT1CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM1_DFSDM_FLT1CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM1_DFSDM_FLT1CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM1_DFSDM_FLT1CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM1_DFSDM_FLT1CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM1_DFSDM_FLT1CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM1_DFSDM_FLT1CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM1_DFSDM_FLT1CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM1_DFSDM_FLT1CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM1_DFSDM_FLT1CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM1_DFSDM_FLT1CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM1_DFSDM_FLT1CR1_AWFSEL = 0x40000000

	// DFSDM_FLT1CR2: DFSDM filter 1 control register 2
	// Position of JEOCIE field.
	DFSDM1_DFSDM_FLT1CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM1_DFSDM_FLT1CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM1_DFSDM_FLT1CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM1_DFSDM_FLT1CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM1_DFSDM_FLT1CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM1_DFSDM_FLT1CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM1_DFSDM_FLT1CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM1_DFSDM_FLT1CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM1_DFSDM_FLT1CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM1_DFSDM_FLT1CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM1_DFSDM_FLT1CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM1_DFSDM_FLT1CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM1_DFSDM_FLT1CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM1_DFSDM_FLT1CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM1_DFSDM_FLT1CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM1_DFSDM_FLT1CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM1_DFSDM_FLT1CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM1_DFSDM_FLT1CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM1_DFSDM_FLT1CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM1_DFSDM_FLT1CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM1_DFSDM_FLT1CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM1_DFSDM_FLT1CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM1_DFSDM_FLT1CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM1_DFSDM_FLT1CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM1_DFSDM_FLT1CR2_AWDCH_Msk = 0xff0000

	// DFSDM_FLT1ISR: DFSDM filter 1 interrupt and status register
	// Position of JEOCF field.
	DFSDM1_DFSDM_FLT1ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM1_DFSDM_FLT1ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM1_DFSDM_FLT1ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM1_DFSDM_FLT1ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM1_DFSDM_FLT1ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM1_DFSDM_FLT1ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM1_DFSDM_FLT1ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM1_DFSDM_FLT1ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM1_DFSDM_FLT1ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM1_DFSDM_FLT1ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM1_DFSDM_FLT1ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM1_DFSDM_FLT1ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM1_DFSDM_FLT1ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM1_DFSDM_FLT1ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM1_DFSDM_FLT1ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM1_DFSDM_FLT1ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM1_DFSDM_FLT1ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM1_DFSDM_FLT1ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM1_DFSDM_FLT1ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM1_DFSDM_FLT1ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM1_DFSDM_FLT1ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM1_DFSDM_FLT1ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM1_DFSDM_FLT1ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM1_DFSDM_FLT1ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM1_DFSDM_FLT1ISR_SCDF_Msk = 0xff000000

	// DFSDM_FLT1ICR: DFSDM filter 1 interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM1_DFSDM_FLT1ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM1_DFSDM_FLT1ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM1_DFSDM_FLT1ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM1_DFSDM_FLT1ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM1_DFSDM_FLT1ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM1_DFSDM_FLT1ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM1_DFSDM_FLT1ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM1_DFSDM_FLT1ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM1_DFSDM_FLT1ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM1_DFSDM_FLT1ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM_FLT1JCHGR: DFSDM filter 1 injected channel group selection register
	// Position of JCHG field.
	DFSDM1_DFSDM_FLT1JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM1_DFSDM_FLT1JCHGR_JCHG_Msk = 0xff

	// DFSDM_FLT1FCR: DFSDM filter 1 control register
	// Position of IOSR field.
	DFSDM1_DFSDM_FLT1FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM1_DFSDM_FLT1FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM1_DFSDM_FLT1FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM1_DFSDM_FLT1FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM1_DFSDM_FLT1FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM1_DFSDM_FLT1FCR_FORD_Msk = 0xe0000000

	// DFSDM_FLT1JDATAR: DFSDM filter 1 data register for injected group
	// Position of JDATACH field.
	DFSDM1_DFSDM_FLT1JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM1_DFSDM_FLT1JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM1_DFSDM_FLT1JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM1_DFSDM_FLT1JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM_FLT1RDATAR: DFSDM filter 1 data register for the regular channel
	// Position of RDATACH field.
	DFSDM1_DFSDM_FLT1RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM1_DFSDM_FLT1RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM1_DFSDM_FLT1RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM1_DFSDM_FLT1RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM1_DFSDM_FLT1RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM1_DFSDM_FLT1RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM1_DFSDM_FLT1RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM_FLT1AWHTR: DFSDM filter 1 analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM1_DFSDM_FLT1AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM1_DFSDM_FLT1AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM1_DFSDM_FLT1AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM1_DFSDM_FLT1AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM_FLT1AWLTR: DFSDM filter 1 analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM1_DFSDM_FLT1AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM1_DFSDM_FLT1AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM1_DFSDM_FLT1AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM1_DFSDM_FLT1AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM_FLT1AWSR: DFSDM filter 1 analog watchdog status register
	// Position of AWLTF field.
	DFSDM1_DFSDM_FLT1AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM1_DFSDM_FLT1AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM1_DFSDM_FLT1AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM1_DFSDM_FLT1AWSR_AWHTF_Msk = 0xff00

	// DFSDM_FLT1AWCFR: DFSDM filter 1 analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM1_DFSDM_FLT1AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM1_DFSDM_FLT1AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM1_DFSDM_FLT1AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM1_DFSDM_FLT1AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM_FLT1EXMAX: DFSDM filter 1 extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM1_DFSDM_FLT1EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM1_DFSDM_FLT1EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM1_DFSDM_FLT1EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM1_DFSDM_FLT1EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM_FLT1EXMIN: DFSDM filter 1 extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM1_DFSDM_FLT1EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM1_DFSDM_FLT1EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM1_DFSDM_FLT1EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM1_DFSDM_FLT1EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM_FLT1CNVTIMR: DFSDM filter 1 conversion timer register
	// Position of CNVCNT field.
	DFSDM1_DFSDM_FLT1CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM1_DFSDM_FLT1CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM_FLT2CR1: DFSDM filter 2 control register 1
	// Position of DFEN field.
	DFSDM1_DFSDM_FLT2CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM1_DFSDM_FLT2CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM1_DFSDM_FLT2CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM1_DFSDM_FLT2CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM1_DFSDM_FLT2CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM1_DFSDM_FLT2CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM1_DFSDM_FLT2CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM1_DFSDM_FLT2CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM1_DFSDM_FLT2CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM1_DFSDM_FLT2CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM1_DFSDM_FLT2CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM1_DFSDM_FLT2CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM1_DFSDM_FLT2CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM1_DFSDM_FLT2CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM1_DFSDM_FLT2CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM1_DFSDM_FLT2CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM1_DFSDM_FLT2CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM1_DFSDM_FLT2CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM1_DFSDM_FLT2CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM1_DFSDM_FLT2CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM1_DFSDM_FLT2CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM1_DFSDM_FLT2CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM1_DFSDM_FLT2CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM1_DFSDM_FLT2CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM1_DFSDM_FLT2CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM1_DFSDM_FLT2CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM1_DFSDM_FLT2CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM1_DFSDM_FLT2CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM1_DFSDM_FLT2CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM1_DFSDM_FLT2CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM1_DFSDM_FLT2CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM1_DFSDM_FLT2CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM1_DFSDM_FLT2CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM1_DFSDM_FLT2CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM1_DFSDM_FLT2CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM1_DFSDM_FLT2CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM1_DFSDM_FLT2CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM1_DFSDM_FLT2CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM1_DFSDM_FLT2CR1_AWFSEL = 0x40000000

	// DFSDM_FLT2CR2: DFSDM filter 2 control register 2
	// Position of JEOCIE field.
	DFSDM1_DFSDM_FLT2CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM1_DFSDM_FLT2CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM1_DFSDM_FLT2CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM1_DFSDM_FLT2CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM1_DFSDM_FLT2CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM1_DFSDM_FLT2CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM1_DFSDM_FLT2CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM1_DFSDM_FLT2CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM1_DFSDM_FLT2CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM1_DFSDM_FLT2CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM1_DFSDM_FLT2CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM1_DFSDM_FLT2CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM1_DFSDM_FLT2CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM1_DFSDM_FLT2CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM1_DFSDM_FLT2CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM1_DFSDM_FLT2CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM1_DFSDM_FLT2CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM1_DFSDM_FLT2CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM1_DFSDM_FLT2CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM1_DFSDM_FLT2CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM1_DFSDM_FLT2CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM1_DFSDM_FLT2CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM1_DFSDM_FLT2CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM1_DFSDM_FLT2CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM1_DFSDM_FLT2CR2_AWDCH_Msk = 0xff0000

	// DFSDM_FLT2ISR: DFSDM filter 2 interrupt and status register
	// Position of JEOCF field.
	DFSDM1_DFSDM_FLT2ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM1_DFSDM_FLT2ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM1_DFSDM_FLT2ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM1_DFSDM_FLT2ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM1_DFSDM_FLT2ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM1_DFSDM_FLT2ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM1_DFSDM_FLT2ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM1_DFSDM_FLT2ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM1_DFSDM_FLT2ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM1_DFSDM_FLT2ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM1_DFSDM_FLT2ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM1_DFSDM_FLT2ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM1_DFSDM_FLT2ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM1_DFSDM_FLT2ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM1_DFSDM_FLT2ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM1_DFSDM_FLT2ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM1_DFSDM_FLT2ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM1_DFSDM_FLT2ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM1_DFSDM_FLT2ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM1_DFSDM_FLT2ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM1_DFSDM_FLT2ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM1_DFSDM_FLT2ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM1_DFSDM_FLT2ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM1_DFSDM_FLT2ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM1_DFSDM_FLT2ISR_SCDF_Msk = 0xff000000

	// DFSDM_FLT2ICR: DFSDM filter 2 interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM1_DFSDM_FLT2ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM1_DFSDM_FLT2ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM1_DFSDM_FLT2ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM1_DFSDM_FLT2ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM1_DFSDM_FLT2ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM1_DFSDM_FLT2ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM1_DFSDM_FLT2ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM1_DFSDM_FLT2ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM1_DFSDM_FLT2ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM1_DFSDM_FLT2ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM_FLT2JCHGR: DFSDM filter 2 injected channel group selection register
	// Position of JCHG field.
	DFSDM1_DFSDM_FLT2JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM1_DFSDM_FLT2JCHGR_JCHG_Msk = 0xff

	// DFSDM_FLT2FCR: DFSDM filter 2 control register
	// Position of IOSR field.
	DFSDM1_DFSDM_FLT2FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM1_DFSDM_FLT2FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM1_DFSDM_FLT2FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM1_DFSDM_FLT2FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM1_DFSDM_FLT2FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM1_DFSDM_FLT2FCR_FORD_Msk = 0xe0000000

	// DFSDM_FLT2JDATAR: DFSDM filter 2 data register for injected group
	// Position of JDATACH field.
	DFSDM1_DFSDM_FLT2JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM1_DFSDM_FLT2JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM1_DFSDM_FLT2JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM1_DFSDM_FLT2JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM_FLT2RDATAR: DFSDM filter 2 data register for the regular channel
	// Position of RDATACH field.
	DFSDM1_DFSDM_FLT2RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM1_DFSDM_FLT2RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM1_DFSDM_FLT2RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM1_DFSDM_FLT2RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM1_DFSDM_FLT2RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM1_DFSDM_FLT2RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM1_DFSDM_FLT2RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM_FLT2AWHTR: DFSDM filter 2 analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM1_DFSDM_FLT2AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM1_DFSDM_FLT2AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM1_DFSDM_FLT2AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM1_DFSDM_FLT2AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM_FLT2AWLTR: DFSDM filter 2 analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM1_DFSDM_FLT2AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM1_DFSDM_FLT2AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM1_DFSDM_FLT2AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM1_DFSDM_FLT2AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM_FLT2AWSR: DFSDM filter 2 analog watchdog status register
	// Position of AWLTF field.
	DFSDM1_DFSDM_FLT2AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM1_DFSDM_FLT2AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM1_DFSDM_FLT2AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM1_DFSDM_FLT2AWSR_AWHTF_Msk = 0xff00

	// DFSDM_FLT2AWCFR: DFSDM filter 2 analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM1_DFSDM_FLT2AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM1_DFSDM_FLT2AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM1_DFSDM_FLT2AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM1_DFSDM_FLT2AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM_FLT2EXMAX: DFSDM filter 2 extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM1_DFSDM_FLT2EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM1_DFSDM_FLT2EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM1_DFSDM_FLT2EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM1_DFSDM_FLT2EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM_FLT2EXMIN: DFSDM filter 2 extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM1_DFSDM_FLT2EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM1_DFSDM_FLT2EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM1_DFSDM_FLT2EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM1_DFSDM_FLT2EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM_FLT2CNVTIMR: DFSDM filter 2 conversion timer register
	// Position of CNVCNT field.
	DFSDM1_DFSDM_FLT2CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM1_DFSDM_FLT2CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM_FLT3CR1: DFSDM filter 3 control register 1
	// Position of DFEN field.
	DFSDM1_DFSDM_FLT3CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM1_DFSDM_FLT3CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM1_DFSDM_FLT3CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM1_DFSDM_FLT3CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM1_DFSDM_FLT3CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM1_DFSDM_FLT3CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM1_DFSDM_FLT3CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM1_DFSDM_FLT3CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM1_DFSDM_FLT3CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM1_DFSDM_FLT3CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM1_DFSDM_FLT3CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM1_DFSDM_FLT3CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM1_DFSDM_FLT3CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM1_DFSDM_FLT3CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM1_DFSDM_FLT3CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM1_DFSDM_FLT3CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM1_DFSDM_FLT3CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM1_DFSDM_FLT3CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM1_DFSDM_FLT3CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM1_DFSDM_FLT3CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM1_DFSDM_FLT3CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM1_DFSDM_FLT3CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM1_DFSDM_FLT3CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM1_DFSDM_FLT3CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM1_DFSDM_FLT3CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM1_DFSDM_FLT3CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM1_DFSDM_FLT3CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM1_DFSDM_FLT3CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM1_DFSDM_FLT3CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM1_DFSDM_FLT3CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM1_DFSDM_FLT3CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM1_DFSDM_FLT3CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM1_DFSDM_FLT3CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM1_DFSDM_FLT3CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM1_DFSDM_FLT3CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM1_DFSDM_FLT3CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM1_DFSDM_FLT3CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM1_DFSDM_FLT3CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM1_DFSDM_FLT3CR1_AWFSEL = 0x40000000

	// DFSDM_FLT3CR2: DFSDM filter 3 control register 2
	// Position of JEOCIE field.
	DFSDM1_DFSDM_FLT3CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM1_DFSDM_FLT3CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM1_DFSDM_FLT3CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM1_DFSDM_FLT3CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM1_DFSDM_FLT3CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM1_DFSDM_FLT3CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM1_DFSDM_FLT3CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM1_DFSDM_FLT3CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM1_DFSDM_FLT3CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM1_DFSDM_FLT3CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM1_DFSDM_FLT3CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM1_DFSDM_FLT3CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM1_DFSDM_FLT3CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM1_DFSDM_FLT3CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM1_DFSDM_FLT3CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM1_DFSDM_FLT3CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM1_DFSDM_FLT3CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM1_DFSDM_FLT3CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM1_DFSDM_FLT3CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM1_DFSDM_FLT3CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM1_DFSDM_FLT3CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM1_DFSDM_FLT3CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM1_DFSDM_FLT3CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM1_DFSDM_FLT3CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM1_DFSDM_FLT3CR2_AWDCH_Msk = 0xff0000

	// DFSDM_FLT3ISR: DFSDM filter 3 interrupt and status register
	// Position of JEOCF field.
	DFSDM1_DFSDM_FLT3ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM1_DFSDM_FLT3ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM1_DFSDM_FLT3ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM1_DFSDM_FLT3ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM1_DFSDM_FLT3ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM1_DFSDM_FLT3ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM1_DFSDM_FLT3ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM1_DFSDM_FLT3ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM1_DFSDM_FLT3ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM1_DFSDM_FLT3ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM1_DFSDM_FLT3ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM1_DFSDM_FLT3ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM1_DFSDM_FLT3ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM1_DFSDM_FLT3ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM1_DFSDM_FLT3ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM1_DFSDM_FLT3ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM1_DFSDM_FLT3ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM1_DFSDM_FLT3ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM1_DFSDM_FLT3ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM1_DFSDM_FLT3ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM1_DFSDM_FLT3ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM1_DFSDM_FLT3ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM1_DFSDM_FLT3ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM1_DFSDM_FLT3ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM1_DFSDM_FLT3ISR_SCDF_Msk = 0xff000000

	// DFSDM_FLT3ICR: DFSDM filter 3 interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM1_DFSDM_FLT3ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM1_DFSDM_FLT3ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM1_DFSDM_FLT3ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM1_DFSDM_FLT3ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM1_DFSDM_FLT3ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM1_DFSDM_FLT3ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM1_DFSDM_FLT3ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM1_DFSDM_FLT3ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM1_DFSDM_FLT3ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM1_DFSDM_FLT3ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM_FLT3JCHGR: DFSDM filter 3 injected channel group selection register
	// Position of JCHG field.
	DFSDM1_DFSDM_FLT3JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM1_DFSDM_FLT3JCHGR_JCHG_Msk = 0xff

	// DFSDM_FLT3FCR: DFSDM filter 3 control register
	// Position of IOSR field.
	DFSDM1_DFSDM_FLT3FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM1_DFSDM_FLT3FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM1_DFSDM_FLT3FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM1_DFSDM_FLT3FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM1_DFSDM_FLT3FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM1_DFSDM_FLT3FCR_FORD_Msk = 0xe0000000

	// DFSDM_FLT3JDATAR: DFSDM filter 3 data register for injected group
	// Position of JDATACH field.
	DFSDM1_DFSDM_FLT3JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM1_DFSDM_FLT3JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM1_DFSDM_FLT3JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM1_DFSDM_FLT3JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM_FLT3RDATAR: DFSDM filter 3 data register for the regular channel
	// Position of RDATACH field.
	DFSDM1_DFSDM_FLT3RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM1_DFSDM_FLT3RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM1_DFSDM_FLT3RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM1_DFSDM_FLT3RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM1_DFSDM_FLT3RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM1_DFSDM_FLT3RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM1_DFSDM_FLT3RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM_FLT3AWHTR: DFSDM filter 3 analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM1_DFSDM_FLT3AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM1_DFSDM_FLT3AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM1_DFSDM_FLT3AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM1_DFSDM_FLT3AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM_FLT3AWLTR: DFSDM filter 3 analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM1_DFSDM_FLT3AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM1_DFSDM_FLT3AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM1_DFSDM_FLT3AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM1_DFSDM_FLT3AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM_FLT3AWSR: DFSDM filter 3 analog watchdog status register
	// Position of AWLTF field.
	DFSDM1_DFSDM_FLT3AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM1_DFSDM_FLT3AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM1_DFSDM_FLT3AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM1_DFSDM_FLT3AWSR_AWHTF_Msk = 0xff00

	// DFSDM_FLT3AWCFR: DFSDM filter 3 analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM1_DFSDM_FLT3AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM1_DFSDM_FLT3AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM1_DFSDM_FLT3AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM1_DFSDM_FLT3AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM_FLT3EXMAX: DFSDM filter 3 extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM1_DFSDM_FLT3EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM1_DFSDM_FLT3EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM1_DFSDM_FLT3EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM1_DFSDM_FLT3EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM_FLT3EXMIN: DFSDM filter 3 extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM1_DFSDM_FLT3EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM1_DFSDM_FLT3EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM1_DFSDM_FLT3EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM1_DFSDM_FLT3EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM_FLT3CNVTIMR: DFSDM filter 3 conversion timer register
	// Position of CNVCNT field.
	DFSDM1_DFSDM_FLT3CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM1_DFSDM_FLT3CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM_FLT4CR1: DFSDM filter 4 control register 1
	// Position of DFEN field.
	DFSDM1_DFSDM_FLT4CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM1_DFSDM_FLT4CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM1_DFSDM_FLT4CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM1_DFSDM_FLT4CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM1_DFSDM_FLT4CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM1_DFSDM_FLT4CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM1_DFSDM_FLT4CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM1_DFSDM_FLT4CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM1_DFSDM_FLT4CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM1_DFSDM_FLT4CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM1_DFSDM_FLT4CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM1_DFSDM_FLT4CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM1_DFSDM_FLT4CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM1_DFSDM_FLT4CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM1_DFSDM_FLT4CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM1_DFSDM_FLT4CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM1_DFSDM_FLT4CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM1_DFSDM_FLT4CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM1_DFSDM_FLT4CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM1_DFSDM_FLT4CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM1_DFSDM_FLT4CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM1_DFSDM_FLT4CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM1_DFSDM_FLT4CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM1_DFSDM_FLT4CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM1_DFSDM_FLT4CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM1_DFSDM_FLT4CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM1_DFSDM_FLT4CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM1_DFSDM_FLT4CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM1_DFSDM_FLT4CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM1_DFSDM_FLT4CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM1_DFSDM_FLT4CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM1_DFSDM_FLT4CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM1_DFSDM_FLT4CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM1_DFSDM_FLT4CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM1_DFSDM_FLT4CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM1_DFSDM_FLT4CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM1_DFSDM_FLT4CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM1_DFSDM_FLT4CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM1_DFSDM_FLT4CR1_AWFSEL = 0x40000000

	// DFSDM_FLT4CR2: DFSDM filter 4 control register 2
	// Position of JEOCIE field.
	DFSDM1_DFSDM_FLT4CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM1_DFSDM_FLT4CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM1_DFSDM_FLT4CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM1_DFSDM_FLT4CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM1_DFSDM_FLT4CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM1_DFSDM_FLT4CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM1_DFSDM_FLT4CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM1_DFSDM_FLT4CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM1_DFSDM_FLT4CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM1_DFSDM_FLT4CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM1_DFSDM_FLT4CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM1_DFSDM_FLT4CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM1_DFSDM_FLT4CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM1_DFSDM_FLT4CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM1_DFSDM_FLT4CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM1_DFSDM_FLT4CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM1_DFSDM_FLT4CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM1_DFSDM_FLT4CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM1_DFSDM_FLT4CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM1_DFSDM_FLT4CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM1_DFSDM_FLT4CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM1_DFSDM_FLT4CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM1_DFSDM_FLT4CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM1_DFSDM_FLT4CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM1_DFSDM_FLT4CR2_AWDCH_Msk = 0xff0000

	// DFSDM_FLT4ISR: DFSDM filter 4 interrupt and status register
	// Position of JEOCF field.
	DFSDM1_DFSDM_FLT4ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM1_DFSDM_FLT4ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM1_DFSDM_FLT4ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM1_DFSDM_FLT4ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM1_DFSDM_FLT4ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM1_DFSDM_FLT4ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM1_DFSDM_FLT4ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM1_DFSDM_FLT4ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM1_DFSDM_FLT4ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM1_DFSDM_FLT4ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM1_DFSDM_FLT4ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM1_DFSDM_FLT4ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM1_DFSDM_FLT4ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM1_DFSDM_FLT4ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM1_DFSDM_FLT4ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM1_DFSDM_FLT4ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM1_DFSDM_FLT4ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM1_DFSDM_FLT4ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM1_DFSDM_FLT4ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM1_DFSDM_FLT4ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM1_DFSDM_FLT4ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM1_DFSDM_FLT4ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM1_DFSDM_FLT4ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM1_DFSDM_FLT4ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM1_DFSDM_FLT4ISR_SCDF_Msk = 0xff000000

	// DFSDM_FLT4ICR: DFSDM filter 4 interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM1_DFSDM_FLT4ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM1_DFSDM_FLT4ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM1_DFSDM_FLT4ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM1_DFSDM_FLT4ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM1_DFSDM_FLT4ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM1_DFSDM_FLT4ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM1_DFSDM_FLT4ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM1_DFSDM_FLT4ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM1_DFSDM_FLT4ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM1_DFSDM_FLT4ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM_FLT4JCHGR: DFSDM filter 4 injected channel group selection register
	// Position of JCHG field.
	DFSDM1_DFSDM_FLT4JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM1_DFSDM_FLT4JCHGR_JCHG_Msk = 0xff

	// DFSDM_FLT4FCR: DFSDM filter 4 control register
	// Position of IOSR field.
	DFSDM1_DFSDM_FLT4FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM1_DFSDM_FLT4FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM1_DFSDM_FLT4FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM1_DFSDM_FLT4FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM1_DFSDM_FLT4FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM1_DFSDM_FLT4FCR_FORD_Msk = 0xe0000000

	// DFSDM_FLT4JDATAR: DFSDM filter 4 data register for injected group
	// Position of JDATACH field.
	DFSDM1_DFSDM_FLT4JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM1_DFSDM_FLT4JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM1_DFSDM_FLT4JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM1_DFSDM_FLT4JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM_FLT4RDATAR: DFSDM filter 4 data register for the regular channel
	// Position of RDATACH field.
	DFSDM1_DFSDM_FLT4RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM1_DFSDM_FLT4RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM1_DFSDM_FLT4RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM1_DFSDM_FLT4RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM1_DFSDM_FLT4RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM1_DFSDM_FLT4RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM1_DFSDM_FLT4RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM_FLT4AWHTR: DFSDM filter 4 analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM1_DFSDM_FLT4AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM1_DFSDM_FLT4AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM1_DFSDM_FLT4AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM1_DFSDM_FLT4AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM_FLT4AWLTR: DFSDM filter 4 analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM1_DFSDM_FLT4AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM1_DFSDM_FLT4AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM1_DFSDM_FLT4AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM1_DFSDM_FLT4AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM_FLT4AWSR: DFSDM filter 4 analog watchdog status register
	// Position of AWLTF field.
	DFSDM1_DFSDM_FLT4AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM1_DFSDM_FLT4AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM1_DFSDM_FLT4AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM1_DFSDM_FLT4AWSR_AWHTF_Msk = 0xff00

	// DFSDM_FLT4AWCFR: DFSDM filter 4 analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM1_DFSDM_FLT4AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM1_DFSDM_FLT4AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM1_DFSDM_FLT4AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM1_DFSDM_FLT4AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM_FLT4EXMAX: DFSDM filter 4 extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM1_DFSDM_FLT4EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM1_DFSDM_FLT4EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM1_DFSDM_FLT4EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM1_DFSDM_FLT4EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM_FLT4EXMIN: DFSDM filter 4 extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM1_DFSDM_FLT4EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM1_DFSDM_FLT4EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM1_DFSDM_FLT4EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM1_DFSDM_FLT4EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM_FLT4CNVTIMR: DFSDM filter 4 conversion timer register
	// Position of CNVCNT field.
	DFSDM1_DFSDM_FLT4CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM1_DFSDM_FLT4CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM_FLT5CR1: DFSDM filter 5 control register 1
	// Position of DFEN field.
	DFSDM1_DFSDM_FLT5CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM1_DFSDM_FLT5CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM1_DFSDM_FLT5CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM1_DFSDM_FLT5CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM1_DFSDM_FLT5CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM1_DFSDM_FLT5CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM1_DFSDM_FLT5CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM1_DFSDM_FLT5CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM1_DFSDM_FLT5CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM1_DFSDM_FLT5CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM1_DFSDM_FLT5CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM1_DFSDM_FLT5CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM1_DFSDM_FLT5CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM1_DFSDM_FLT5CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM1_DFSDM_FLT5CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM1_DFSDM_FLT5CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM1_DFSDM_FLT5CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM1_DFSDM_FLT5CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM1_DFSDM_FLT5CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM1_DFSDM_FLT5CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM1_DFSDM_FLT5CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM1_DFSDM_FLT5CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM1_DFSDM_FLT5CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM1_DFSDM_FLT5CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM1_DFSDM_FLT5CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM1_DFSDM_FLT5CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM1_DFSDM_FLT5CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM1_DFSDM_FLT5CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM1_DFSDM_FLT5CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM1_DFSDM_FLT5CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM1_DFSDM_FLT5CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM1_DFSDM_FLT5CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM1_DFSDM_FLT5CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM1_DFSDM_FLT5CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM1_DFSDM_FLT5CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM1_DFSDM_FLT5CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM1_DFSDM_FLT5CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM1_DFSDM_FLT5CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM1_DFSDM_FLT5CR1_AWFSEL = 0x40000000

	// DFSDM_FLT5CR2: DFSDM filter 5 control register 2
	// Position of JEOCIE field.
	DFSDM1_DFSDM_FLT5CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM1_DFSDM_FLT5CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM1_DFSDM_FLT5CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM1_DFSDM_FLT5CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM1_DFSDM_FLT5CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM1_DFSDM_FLT5CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM1_DFSDM_FLT5CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM1_DFSDM_FLT5CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM1_DFSDM_FLT5CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM1_DFSDM_FLT5CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM1_DFSDM_FLT5CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM1_DFSDM_FLT5CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM1_DFSDM_FLT5CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM1_DFSDM_FLT5CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM1_DFSDM_FLT5CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM1_DFSDM_FLT5CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM1_DFSDM_FLT5CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM1_DFSDM_FLT5CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM1_DFSDM_FLT5CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM1_DFSDM_FLT5CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM1_DFSDM_FLT5CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM1_DFSDM_FLT5CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM1_DFSDM_FLT5CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM1_DFSDM_FLT5CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM1_DFSDM_FLT5CR2_AWDCH_Msk = 0xff0000

	// DFSDM_FLT5ISR: DFSDM filter 5 interrupt and status register
	// Position of JEOCF field.
	DFSDM1_DFSDM_FLT5ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM1_DFSDM_FLT5ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM1_DFSDM_FLT5ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM1_DFSDM_FLT5ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM1_DFSDM_FLT5ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM1_DFSDM_FLT5ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM1_DFSDM_FLT5ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM1_DFSDM_FLT5ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM1_DFSDM_FLT5ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM1_DFSDM_FLT5ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM1_DFSDM_FLT5ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM1_DFSDM_FLT5ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM1_DFSDM_FLT5ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM1_DFSDM_FLT5ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM1_DFSDM_FLT5ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM1_DFSDM_FLT5ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM1_DFSDM_FLT5ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM1_DFSDM_FLT5ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM1_DFSDM_FLT5ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM1_DFSDM_FLT5ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM1_DFSDM_FLT5ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM1_DFSDM_FLT5ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM1_DFSDM_FLT5ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM1_DFSDM_FLT5ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM1_DFSDM_FLT5ISR_SCDF_Msk = 0xff000000

	// DFSDM_FLT5ICR: DFSDM filter 5 interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM1_DFSDM_FLT5ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM1_DFSDM_FLT5ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM1_DFSDM_FLT5ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM1_DFSDM_FLT5ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM1_DFSDM_FLT5ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM1_DFSDM_FLT5ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM1_DFSDM_FLT5ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM1_DFSDM_FLT5ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM1_DFSDM_FLT5ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM1_DFSDM_FLT5ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM_FLT5JCHGR: DFSDM filter 5 injected channel group selection register
	// Position of JCHG field.
	DFSDM1_DFSDM_FLT5JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM1_DFSDM_FLT5JCHGR_JCHG_Msk = 0xff

	// DFSDM_FLT5FCR: DFSDM filter 5 control register
	// Position of IOSR field.
	DFSDM1_DFSDM_FLT5FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM1_DFSDM_FLT5FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM1_DFSDM_FLT5FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM1_DFSDM_FLT5FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM1_DFSDM_FLT5FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM1_DFSDM_FLT5FCR_FORD_Msk = 0xe0000000

	// DFSDM_FLT5JDATAR: DFSDM filter 5 data register for injected group
	// Position of JDATACH field.
	DFSDM1_DFSDM_FLT5JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM1_DFSDM_FLT5JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM1_DFSDM_FLT5JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM1_DFSDM_FLT5JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM_FLT5RDATAR: DFSDM filter 5 data register for the regular channel
	// Position of RDATACH field.
	DFSDM1_DFSDM_FLT5RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM1_DFSDM_FLT5RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM1_DFSDM_FLT5RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM1_DFSDM_FLT5RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM1_DFSDM_FLT5RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM1_DFSDM_FLT5RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM1_DFSDM_FLT5RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM_FLT5AWHTR: DFSDM filter 5 analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM1_DFSDM_FLT5AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM1_DFSDM_FLT5AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM1_DFSDM_FLT5AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM1_DFSDM_FLT5AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM_FLT5AWLTR: DFSDM filter 5 analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM1_DFSDM_FLT5AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM1_DFSDM_FLT5AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM1_DFSDM_FLT5AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM1_DFSDM_FLT5AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM_FLT5AWSR: DFSDM filter 5 analog watchdog status register
	// Position of AWLTF field.
	DFSDM1_DFSDM_FLT5AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM1_DFSDM_FLT5AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM1_DFSDM_FLT5AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM1_DFSDM_FLT5AWSR_AWHTF_Msk = 0xff00

	// DFSDM_FLT5AWCFR: DFSDM filter 5 analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM1_DFSDM_FLT5AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM1_DFSDM_FLT5AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM1_DFSDM_FLT5AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM1_DFSDM_FLT5AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM_FLT5EXMAX: DFSDM filter 5 extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM1_DFSDM_FLT5EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM1_DFSDM_FLT5EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM1_DFSDM_FLT5EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM1_DFSDM_FLT5EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM_FLT5EXMIN: DFSDM filter 5 extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM1_DFSDM_FLT5EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM1_DFSDM_FLT5EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM1_DFSDM_FLT5EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM1_DFSDM_FLT5EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM_FLT5CNVTIMR: DFSDM filter 5 conversion timer register
	// Position of CNVCNT field.
	DFSDM1_DFSDM_FLT5CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM1_DFSDM_FLT5CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM_HWCFGR: This register specifies the hardware configuration of DFSDM peripheral.
	// Position of NBT field.
	DFSDM1_DFSDM_HWCFGR_NBT_Pos = 0x0
	// Bit mask of NBT field.
	DFSDM1_DFSDM_HWCFGR_NBT_Msk = 0xff
	// Position of NBF field.
	DFSDM1_DFSDM_HWCFGR_NBF_Pos = 0x8
	// Bit mask of NBF field.
	DFSDM1_DFSDM_HWCFGR_NBF_Msk = 0xff00

	// DFSDM_VERR: This register specifies the version of DFSDM peripheral.
	// Position of MINREV field.
	DFSDM1_DFSDM_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DFSDM1_DFSDM_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DFSDM1_DFSDM_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DFSDM1_DFSDM_VERR_MAJREV_Msk = 0xf0

	// DFSDM_IPIDR: This register specifies the identification of DFSDM peripheral.
	// Position of ID field.
	DFSDM1_DFSDM_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	DFSDM1_DFSDM_IPIDR_ID_Msk = 0xffffffff

	// DFSDM_SIDR: This register specifies the size allocated to DFSDM registers.
	// Position of SID field.
	DFSDM1_DFSDM_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	DFSDM1_DFSDM_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for DLYBQS: DLYBQS
const (
	// DLYB_CR: DLYB control register
	// Position of DEN field.
	DLYB_DLYB_CR_DEN_Pos = 0x0
	// Bit mask of DEN field.
	DLYB_DLYB_CR_DEN_Msk = 0x1
	// Bit DEN.
	DLYB_DLYB_CR_DEN = 0x1
	// Position of SEN field.
	DLYB_DLYB_CR_SEN_Pos = 0x1
	// Bit mask of SEN field.
	DLYB_DLYB_CR_SEN_Msk = 0x2
	// Bit SEN.
	DLYB_DLYB_CR_SEN = 0x2

	// DLYB_CFGR: DLYB configuration register
	// Position of SEL field.
	DLYB_DLYB_CFGR_SEL_Pos = 0x0
	// Bit mask of SEL field.
	DLYB_DLYB_CFGR_SEL_Msk = 0xf
	// Position of UNIT field.
	DLYB_DLYB_CFGR_UNIT_Pos = 0x8
	// Bit mask of UNIT field.
	DLYB_DLYB_CFGR_UNIT_Msk = 0x7f00
	// Position of LNG field.
	DLYB_DLYB_CFGR_LNG_Pos = 0x10
	// Bit mask of LNG field.
	DLYB_DLYB_CFGR_LNG_Msk = 0xfff0000
	// Position of LNGF field.
	DLYB_DLYB_CFGR_LNGF_Pos = 0x1f
	// Bit mask of LNGF field.
	DLYB_DLYB_CFGR_LNGF_Msk = 0x80000000
	// Bit LNGF.
	DLYB_DLYB_CFGR_LNGF = 0x80000000

	// DLYB_VERR: DLYB IP version register
	// Position of MINREV field.
	DLYB_DLYB_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DLYB_DLYB_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DLYB_DLYB_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DLYB_DLYB_VERR_MAJREV_Msk = 0xf0

	// DLYB_IPIDR: DLYB IP identification register
	// Position of ID field.
	DLYB_DLYB_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	DLYB_DLYB_IPIDR_ID_Msk = 0xffffffff

	// DLYB_SIDR: DLYB size ID register
	// Position of SID field.
	DLYB_DLYB_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	DLYB_DLYB_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for DLYBSD1: DLYBSD1
const (
	// DLYB_CR: DLYB control register
	// Position of DEN field.
	DLYBSD1_DLYB_CR_DEN_Pos = 0x0
	// Bit mask of DEN field.
	DLYBSD1_DLYB_CR_DEN_Msk = 0x1
	// Bit DEN.
	DLYBSD1_DLYB_CR_DEN = 0x1
	// Position of SEN field.
	DLYBSD1_DLYB_CR_SEN_Pos = 0x1
	// Bit mask of SEN field.
	DLYBSD1_DLYB_CR_SEN_Msk = 0x2
	// Bit SEN.
	DLYBSD1_DLYB_CR_SEN = 0x2

	// DLYB_CFGR: DLYB configuration register
	// Position of SEL field.
	DLYBSD1_DLYB_CFGR_SEL_Pos = 0x0
	// Bit mask of SEL field.
	DLYBSD1_DLYB_CFGR_SEL_Msk = 0xf
	// Position of UNIT field.
	DLYBSD1_DLYB_CFGR_UNIT_Pos = 0x8
	// Bit mask of UNIT field.
	DLYBSD1_DLYB_CFGR_UNIT_Msk = 0x7f00
	// Position of LNG field.
	DLYBSD1_DLYB_CFGR_LNG_Pos = 0x10
	// Bit mask of LNG field.
	DLYBSD1_DLYB_CFGR_LNG_Msk = 0xfff0000
	// Position of LNGF field.
	DLYBSD1_DLYB_CFGR_LNGF_Pos = 0x1f
	// Bit mask of LNGF field.
	DLYBSD1_DLYB_CFGR_LNGF_Msk = 0x80000000
	// Bit LNGF.
	DLYBSD1_DLYB_CFGR_LNGF = 0x80000000

	// DLYB_VERR: DLYB IP version register
	// Position of MINREV field.
	DLYBSD1_DLYB_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DLYBSD1_DLYB_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DLYBSD1_DLYB_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DLYBSD1_DLYB_VERR_MAJREV_Msk = 0xf0

	// DLYB_IPIDR: DLYB IP identification register
	// Position of ID field.
	DLYBSD1_DLYB_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	DLYBSD1_DLYB_IPIDR_ID_Msk = 0xffffffff

	// DLYB_SIDR: DLYB size ID register
	// Position of SID field.
	DLYBSD1_DLYB_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	DLYBSD1_DLYB_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for DMA1: DMA1
const (
	// DMA_LISR: DMA low interrupt status register
	// Position of FEIF0 field.
	DMA1_DMA_LISR_FEIF0_Pos = 0x0
	// Bit mask of FEIF0 field.
	DMA1_DMA_LISR_FEIF0_Msk = 0x1
	// Bit FEIF0.
	DMA1_DMA_LISR_FEIF0 = 0x1
	// Position of DMEIF0 field.
	DMA1_DMA_LISR_DMEIF0_Pos = 0x2
	// Bit mask of DMEIF0 field.
	DMA1_DMA_LISR_DMEIF0_Msk = 0x4
	// Bit DMEIF0.
	DMA1_DMA_LISR_DMEIF0 = 0x4
	// Position of TEIF0 field.
	DMA1_DMA_LISR_TEIF0_Pos = 0x3
	// Bit mask of TEIF0 field.
	DMA1_DMA_LISR_TEIF0_Msk = 0x8
	// Bit TEIF0.
	DMA1_DMA_LISR_TEIF0 = 0x8
	// Position of HTIF0 field.
	DMA1_DMA_LISR_HTIF0_Pos = 0x4
	// Bit mask of HTIF0 field.
	DMA1_DMA_LISR_HTIF0_Msk = 0x10
	// Bit HTIF0.
	DMA1_DMA_LISR_HTIF0 = 0x10
	// Position of TCIF0 field.
	DMA1_DMA_LISR_TCIF0_Pos = 0x5
	// Bit mask of TCIF0 field.
	DMA1_DMA_LISR_TCIF0_Msk = 0x20
	// Bit TCIF0.
	DMA1_DMA_LISR_TCIF0 = 0x20
	// Position of FEIF1 field.
	DMA1_DMA_LISR_FEIF1_Pos = 0x6
	// Bit mask of FEIF1 field.
	DMA1_DMA_LISR_FEIF1_Msk = 0x40
	// Bit FEIF1.
	DMA1_DMA_LISR_FEIF1 = 0x40
	// Position of DMEIF1 field.
	DMA1_DMA_LISR_DMEIF1_Pos = 0x8
	// Bit mask of DMEIF1 field.
	DMA1_DMA_LISR_DMEIF1_Msk = 0x100
	// Bit DMEIF1.
	DMA1_DMA_LISR_DMEIF1 = 0x100
	// Position of TEIF1 field.
	DMA1_DMA_LISR_TEIF1_Pos = 0x9
	// Bit mask of TEIF1 field.
	DMA1_DMA_LISR_TEIF1_Msk = 0x200
	// Bit TEIF1.
	DMA1_DMA_LISR_TEIF1 = 0x200
	// Position of HTIF1 field.
	DMA1_DMA_LISR_HTIF1_Pos = 0xa
	// Bit mask of HTIF1 field.
	DMA1_DMA_LISR_HTIF1_Msk = 0x400
	// Bit HTIF1.
	DMA1_DMA_LISR_HTIF1 = 0x400
	// Position of TCIF1 field.
	DMA1_DMA_LISR_TCIF1_Pos = 0xb
	// Bit mask of TCIF1 field.
	DMA1_DMA_LISR_TCIF1_Msk = 0x800
	// Bit TCIF1.
	DMA1_DMA_LISR_TCIF1 = 0x800
	// Position of FEIF2 field.
	DMA1_DMA_LISR_FEIF2_Pos = 0x10
	// Bit mask of FEIF2 field.
	DMA1_DMA_LISR_FEIF2_Msk = 0x10000
	// Bit FEIF2.
	DMA1_DMA_LISR_FEIF2 = 0x10000
	// Position of DMEIF2 field.
	DMA1_DMA_LISR_DMEIF2_Pos = 0x12
	// Bit mask of DMEIF2 field.
	DMA1_DMA_LISR_DMEIF2_Msk = 0x40000
	// Bit DMEIF2.
	DMA1_DMA_LISR_DMEIF2 = 0x40000
	// Position of TEIF2 field.
	DMA1_DMA_LISR_TEIF2_Pos = 0x13
	// Bit mask of TEIF2 field.
	DMA1_DMA_LISR_TEIF2_Msk = 0x80000
	// Bit TEIF2.
	DMA1_DMA_LISR_TEIF2 = 0x80000
	// Position of HTIF2 field.
	DMA1_DMA_LISR_HTIF2_Pos = 0x14
	// Bit mask of HTIF2 field.
	DMA1_DMA_LISR_HTIF2_Msk = 0x100000
	// Bit HTIF2.
	DMA1_DMA_LISR_HTIF2 = 0x100000
	// Position of TCIF2 field.
	DMA1_DMA_LISR_TCIF2_Pos = 0x15
	// Bit mask of TCIF2 field.
	DMA1_DMA_LISR_TCIF2_Msk = 0x200000
	// Bit TCIF2.
	DMA1_DMA_LISR_TCIF2 = 0x200000
	// Position of FEIF3 field.
	DMA1_DMA_LISR_FEIF3_Pos = 0x16
	// Bit mask of FEIF3 field.
	DMA1_DMA_LISR_FEIF3_Msk = 0x400000
	// Bit FEIF3.
	DMA1_DMA_LISR_FEIF3 = 0x400000
	// Position of DMEIF3 field.
	DMA1_DMA_LISR_DMEIF3_Pos = 0x18
	// Bit mask of DMEIF3 field.
	DMA1_DMA_LISR_DMEIF3_Msk = 0x1000000
	// Bit DMEIF3.
	DMA1_DMA_LISR_DMEIF3 = 0x1000000
	// Position of TEIF3 field.
	DMA1_DMA_LISR_TEIF3_Pos = 0x19
	// Bit mask of TEIF3 field.
	DMA1_DMA_LISR_TEIF3_Msk = 0x2000000
	// Bit TEIF3.
	DMA1_DMA_LISR_TEIF3 = 0x2000000
	// Position of HTIF3 field.
	DMA1_DMA_LISR_HTIF3_Pos = 0x1a
	// Bit mask of HTIF3 field.
	DMA1_DMA_LISR_HTIF3_Msk = 0x4000000
	// Bit HTIF3.
	DMA1_DMA_LISR_HTIF3 = 0x4000000
	// Position of TCIF3 field.
	DMA1_DMA_LISR_TCIF3_Pos = 0x1b
	// Bit mask of TCIF3 field.
	DMA1_DMA_LISR_TCIF3_Msk = 0x8000000
	// Bit TCIF3.
	DMA1_DMA_LISR_TCIF3 = 0x8000000

	// DMA_HISR: DMA high interrupt status register
	// Position of FEIF4 field.
	DMA1_DMA_HISR_FEIF4_Pos = 0x0
	// Bit mask of FEIF4 field.
	DMA1_DMA_HISR_FEIF4_Msk = 0x1
	// Bit FEIF4.
	DMA1_DMA_HISR_FEIF4 = 0x1
	// Position of DMEIF4 field.
	DMA1_DMA_HISR_DMEIF4_Pos = 0x2
	// Bit mask of DMEIF4 field.
	DMA1_DMA_HISR_DMEIF4_Msk = 0x4
	// Bit DMEIF4.
	DMA1_DMA_HISR_DMEIF4 = 0x4
	// Position of TEIF4 field.
	DMA1_DMA_HISR_TEIF4_Pos = 0x3
	// Bit mask of TEIF4 field.
	DMA1_DMA_HISR_TEIF4_Msk = 0x8
	// Bit TEIF4.
	DMA1_DMA_HISR_TEIF4 = 0x8
	// Position of HTIF4 field.
	DMA1_DMA_HISR_HTIF4_Pos = 0x4
	// Bit mask of HTIF4 field.
	DMA1_DMA_HISR_HTIF4_Msk = 0x10
	// Bit HTIF4.
	DMA1_DMA_HISR_HTIF4 = 0x10
	// Position of TCIF4 field.
	DMA1_DMA_HISR_TCIF4_Pos = 0x5
	// Bit mask of TCIF4 field.
	DMA1_DMA_HISR_TCIF4_Msk = 0x20
	// Bit TCIF4.
	DMA1_DMA_HISR_TCIF4 = 0x20
	// Position of FEIF5 field.
	DMA1_DMA_HISR_FEIF5_Pos = 0x6
	// Bit mask of FEIF5 field.
	DMA1_DMA_HISR_FEIF5_Msk = 0x40
	// Bit FEIF5.
	DMA1_DMA_HISR_FEIF5 = 0x40
	// Position of DMEIF5 field.
	DMA1_DMA_HISR_DMEIF5_Pos = 0x8
	// Bit mask of DMEIF5 field.
	DMA1_DMA_HISR_DMEIF5_Msk = 0x100
	// Bit DMEIF5.
	DMA1_DMA_HISR_DMEIF5 = 0x100
	// Position of TEIF5 field.
	DMA1_DMA_HISR_TEIF5_Pos = 0x9
	// Bit mask of TEIF5 field.
	DMA1_DMA_HISR_TEIF5_Msk = 0x200
	// Bit TEIF5.
	DMA1_DMA_HISR_TEIF5 = 0x200
	// Position of HTIF5 field.
	DMA1_DMA_HISR_HTIF5_Pos = 0xa
	// Bit mask of HTIF5 field.
	DMA1_DMA_HISR_HTIF5_Msk = 0x400
	// Bit HTIF5.
	DMA1_DMA_HISR_HTIF5 = 0x400
	// Position of TCIF5 field.
	DMA1_DMA_HISR_TCIF5_Pos = 0xb
	// Bit mask of TCIF5 field.
	DMA1_DMA_HISR_TCIF5_Msk = 0x800
	// Bit TCIF5.
	DMA1_DMA_HISR_TCIF5 = 0x800
	// Position of FEIF6 field.
	DMA1_DMA_HISR_FEIF6_Pos = 0x10
	// Bit mask of FEIF6 field.
	DMA1_DMA_HISR_FEIF6_Msk = 0x10000
	// Bit FEIF6.
	DMA1_DMA_HISR_FEIF6 = 0x10000
	// Position of DMEIF6 field.
	DMA1_DMA_HISR_DMEIF6_Pos = 0x12
	// Bit mask of DMEIF6 field.
	DMA1_DMA_HISR_DMEIF6_Msk = 0x40000
	// Bit DMEIF6.
	DMA1_DMA_HISR_DMEIF6 = 0x40000
	// Position of TEIF6 field.
	DMA1_DMA_HISR_TEIF6_Pos = 0x13
	// Bit mask of TEIF6 field.
	DMA1_DMA_HISR_TEIF6_Msk = 0x80000
	// Bit TEIF6.
	DMA1_DMA_HISR_TEIF6 = 0x80000
	// Position of HTIF6 field.
	DMA1_DMA_HISR_HTIF6_Pos = 0x14
	// Bit mask of HTIF6 field.
	DMA1_DMA_HISR_HTIF6_Msk = 0x100000
	// Bit HTIF6.
	DMA1_DMA_HISR_HTIF6 = 0x100000
	// Position of TCIF6 field.
	DMA1_DMA_HISR_TCIF6_Pos = 0x15
	// Bit mask of TCIF6 field.
	DMA1_DMA_HISR_TCIF6_Msk = 0x200000
	// Bit TCIF6.
	DMA1_DMA_HISR_TCIF6 = 0x200000
	// Position of FEIF7 field.
	DMA1_DMA_HISR_FEIF7_Pos = 0x16
	// Bit mask of FEIF7 field.
	DMA1_DMA_HISR_FEIF7_Msk = 0x400000
	// Bit FEIF7.
	DMA1_DMA_HISR_FEIF7 = 0x400000
	// Position of DMEIF7 field.
	DMA1_DMA_HISR_DMEIF7_Pos = 0x18
	// Bit mask of DMEIF7 field.
	DMA1_DMA_HISR_DMEIF7_Msk = 0x1000000
	// Bit DMEIF7.
	DMA1_DMA_HISR_DMEIF7 = 0x1000000
	// Position of TEIF7 field.
	DMA1_DMA_HISR_TEIF7_Pos = 0x19
	// Bit mask of TEIF7 field.
	DMA1_DMA_HISR_TEIF7_Msk = 0x2000000
	// Bit TEIF7.
	DMA1_DMA_HISR_TEIF7 = 0x2000000
	// Position of HTIF7 field.
	DMA1_DMA_HISR_HTIF7_Pos = 0x1a
	// Bit mask of HTIF7 field.
	DMA1_DMA_HISR_HTIF7_Msk = 0x4000000
	// Bit HTIF7.
	DMA1_DMA_HISR_HTIF7 = 0x4000000
	// Position of TCIF7 field.
	DMA1_DMA_HISR_TCIF7_Pos = 0x1b
	// Bit mask of TCIF7 field.
	DMA1_DMA_HISR_TCIF7_Msk = 0x8000000
	// Bit TCIF7.
	DMA1_DMA_HISR_TCIF7 = 0x8000000

	// DMA_LIFCR: DMA low interrupt flag clear register
	// Position of CFEIF0 field.
	DMA1_DMA_LIFCR_CFEIF0_Pos = 0x0
	// Bit mask of CFEIF0 field.
	DMA1_DMA_LIFCR_CFEIF0_Msk = 0x1
	// Bit CFEIF0.
	DMA1_DMA_LIFCR_CFEIF0 = 0x1
	// Position of CDMEIF0 field.
	DMA1_DMA_LIFCR_CDMEIF0_Pos = 0x2
	// Bit mask of CDMEIF0 field.
	DMA1_DMA_LIFCR_CDMEIF0_Msk = 0x4
	// Bit CDMEIF0.
	DMA1_DMA_LIFCR_CDMEIF0 = 0x4
	// Position of CTEIF0 field.
	DMA1_DMA_LIFCR_CTEIF0_Pos = 0x3
	// Bit mask of CTEIF0 field.
	DMA1_DMA_LIFCR_CTEIF0_Msk = 0x8
	// Bit CTEIF0.
	DMA1_DMA_LIFCR_CTEIF0 = 0x8
	// Position of CHTIF0 field.
	DMA1_DMA_LIFCR_CHTIF0_Pos = 0x4
	// Bit mask of CHTIF0 field.
	DMA1_DMA_LIFCR_CHTIF0_Msk = 0x10
	// Bit CHTIF0.
	DMA1_DMA_LIFCR_CHTIF0 = 0x10
	// Position of CTCIF0 field.
	DMA1_DMA_LIFCR_CTCIF0_Pos = 0x5
	// Bit mask of CTCIF0 field.
	DMA1_DMA_LIFCR_CTCIF0_Msk = 0x20
	// Bit CTCIF0.
	DMA1_DMA_LIFCR_CTCIF0 = 0x20
	// Position of CFEIF1 field.
	DMA1_DMA_LIFCR_CFEIF1_Pos = 0x6
	// Bit mask of CFEIF1 field.
	DMA1_DMA_LIFCR_CFEIF1_Msk = 0x40
	// Bit CFEIF1.
	DMA1_DMA_LIFCR_CFEIF1 = 0x40
	// Position of CDMEIF1 field.
	DMA1_DMA_LIFCR_CDMEIF1_Pos = 0x8
	// Bit mask of CDMEIF1 field.
	DMA1_DMA_LIFCR_CDMEIF1_Msk = 0x100
	// Bit CDMEIF1.
	DMA1_DMA_LIFCR_CDMEIF1 = 0x100
	// Position of CTEIF1 field.
	DMA1_DMA_LIFCR_CTEIF1_Pos = 0x9
	// Bit mask of CTEIF1 field.
	DMA1_DMA_LIFCR_CTEIF1_Msk = 0x200
	// Bit CTEIF1.
	DMA1_DMA_LIFCR_CTEIF1 = 0x200
	// Position of CHTIF1 field.
	DMA1_DMA_LIFCR_CHTIF1_Pos = 0xa
	// Bit mask of CHTIF1 field.
	DMA1_DMA_LIFCR_CHTIF1_Msk = 0x400
	// Bit CHTIF1.
	DMA1_DMA_LIFCR_CHTIF1 = 0x400
	// Position of CTCIF1 field.
	DMA1_DMA_LIFCR_CTCIF1_Pos = 0xb
	// Bit mask of CTCIF1 field.
	DMA1_DMA_LIFCR_CTCIF1_Msk = 0x800
	// Bit CTCIF1.
	DMA1_DMA_LIFCR_CTCIF1 = 0x800
	// Position of CFEIF2 field.
	DMA1_DMA_LIFCR_CFEIF2_Pos = 0x10
	// Bit mask of CFEIF2 field.
	DMA1_DMA_LIFCR_CFEIF2_Msk = 0x10000
	// Bit CFEIF2.
	DMA1_DMA_LIFCR_CFEIF2 = 0x10000
	// Position of CDMEIF2 field.
	DMA1_DMA_LIFCR_CDMEIF2_Pos = 0x12
	// Bit mask of CDMEIF2 field.
	DMA1_DMA_LIFCR_CDMEIF2_Msk = 0x40000
	// Bit CDMEIF2.
	DMA1_DMA_LIFCR_CDMEIF2 = 0x40000
	// Position of CTEIF2 field.
	DMA1_DMA_LIFCR_CTEIF2_Pos = 0x13
	// Bit mask of CTEIF2 field.
	DMA1_DMA_LIFCR_CTEIF2_Msk = 0x80000
	// Bit CTEIF2.
	DMA1_DMA_LIFCR_CTEIF2 = 0x80000
	// Position of CHTIF2 field.
	DMA1_DMA_LIFCR_CHTIF2_Pos = 0x14
	// Bit mask of CHTIF2 field.
	DMA1_DMA_LIFCR_CHTIF2_Msk = 0x100000
	// Bit CHTIF2.
	DMA1_DMA_LIFCR_CHTIF2 = 0x100000
	// Position of CTCIF2 field.
	DMA1_DMA_LIFCR_CTCIF2_Pos = 0x15
	// Bit mask of CTCIF2 field.
	DMA1_DMA_LIFCR_CTCIF2_Msk = 0x200000
	// Bit CTCIF2.
	DMA1_DMA_LIFCR_CTCIF2 = 0x200000
	// Position of CFEIF3 field.
	DMA1_DMA_LIFCR_CFEIF3_Pos = 0x16
	// Bit mask of CFEIF3 field.
	DMA1_DMA_LIFCR_CFEIF3_Msk = 0x400000
	// Bit CFEIF3.
	DMA1_DMA_LIFCR_CFEIF3 = 0x400000
	// Position of CDMEIF3 field.
	DMA1_DMA_LIFCR_CDMEIF3_Pos = 0x18
	// Bit mask of CDMEIF3 field.
	DMA1_DMA_LIFCR_CDMEIF3_Msk = 0x1000000
	// Bit CDMEIF3.
	DMA1_DMA_LIFCR_CDMEIF3 = 0x1000000
	// Position of CTEIF3 field.
	DMA1_DMA_LIFCR_CTEIF3_Pos = 0x19
	// Bit mask of CTEIF3 field.
	DMA1_DMA_LIFCR_CTEIF3_Msk = 0x2000000
	// Bit CTEIF3.
	DMA1_DMA_LIFCR_CTEIF3 = 0x2000000
	// Position of CHTIF3 field.
	DMA1_DMA_LIFCR_CHTIF3_Pos = 0x1a
	// Bit mask of CHTIF3 field.
	DMA1_DMA_LIFCR_CHTIF3_Msk = 0x4000000
	// Bit CHTIF3.
	DMA1_DMA_LIFCR_CHTIF3 = 0x4000000
	// Position of CTCIF3 field.
	DMA1_DMA_LIFCR_CTCIF3_Pos = 0x1b
	// Bit mask of CTCIF3 field.
	DMA1_DMA_LIFCR_CTCIF3_Msk = 0x8000000
	// Bit CTCIF3.
	DMA1_DMA_LIFCR_CTCIF3 = 0x8000000

	// DMA_HIFCR: DMA high interrupt flag clear register
	// Position of CFEIF4 field.
	DMA1_DMA_HIFCR_CFEIF4_Pos = 0x0
	// Bit mask of CFEIF4 field.
	DMA1_DMA_HIFCR_CFEIF4_Msk = 0x1
	// Bit CFEIF4.
	DMA1_DMA_HIFCR_CFEIF4 = 0x1
	// Position of CDMEIF4 field.
	DMA1_DMA_HIFCR_CDMEIF4_Pos = 0x2
	// Bit mask of CDMEIF4 field.
	DMA1_DMA_HIFCR_CDMEIF4_Msk = 0x4
	// Bit CDMEIF4.
	DMA1_DMA_HIFCR_CDMEIF4 = 0x4
	// Position of CTEIF4 field.
	DMA1_DMA_HIFCR_CTEIF4_Pos = 0x3
	// Bit mask of CTEIF4 field.
	DMA1_DMA_HIFCR_CTEIF4_Msk = 0x8
	// Bit CTEIF4.
	DMA1_DMA_HIFCR_CTEIF4 = 0x8
	// Position of CHTIF4 field.
	DMA1_DMA_HIFCR_CHTIF4_Pos = 0x4
	// Bit mask of CHTIF4 field.
	DMA1_DMA_HIFCR_CHTIF4_Msk = 0x10
	// Bit CHTIF4.
	DMA1_DMA_HIFCR_CHTIF4 = 0x10
	// Position of CTCIF4 field.
	DMA1_DMA_HIFCR_CTCIF4_Pos = 0x5
	// Bit mask of CTCIF4 field.
	DMA1_DMA_HIFCR_CTCIF4_Msk = 0x20
	// Bit CTCIF4.
	DMA1_DMA_HIFCR_CTCIF4 = 0x20
	// Position of CFEIF5 field.
	DMA1_DMA_HIFCR_CFEIF5_Pos = 0x6
	// Bit mask of CFEIF5 field.
	DMA1_DMA_HIFCR_CFEIF5_Msk = 0x40
	// Bit CFEIF5.
	DMA1_DMA_HIFCR_CFEIF5 = 0x40
	// Position of CDMEIF5 field.
	DMA1_DMA_HIFCR_CDMEIF5_Pos = 0x8
	// Bit mask of CDMEIF5 field.
	DMA1_DMA_HIFCR_CDMEIF5_Msk = 0x100
	// Bit CDMEIF5.
	DMA1_DMA_HIFCR_CDMEIF5 = 0x100
	// Position of CTEIF5 field.
	DMA1_DMA_HIFCR_CTEIF5_Pos = 0x9
	// Bit mask of CTEIF5 field.
	DMA1_DMA_HIFCR_CTEIF5_Msk = 0x200
	// Bit CTEIF5.
	DMA1_DMA_HIFCR_CTEIF5 = 0x200
	// Position of CHTIF5 field.
	DMA1_DMA_HIFCR_CHTIF5_Pos = 0xa
	// Bit mask of CHTIF5 field.
	DMA1_DMA_HIFCR_CHTIF5_Msk = 0x400
	// Bit CHTIF5.
	DMA1_DMA_HIFCR_CHTIF5 = 0x400
	// Position of CTCIF5 field.
	DMA1_DMA_HIFCR_CTCIF5_Pos = 0xb
	// Bit mask of CTCIF5 field.
	DMA1_DMA_HIFCR_CTCIF5_Msk = 0x800
	// Bit CTCIF5.
	DMA1_DMA_HIFCR_CTCIF5 = 0x800
	// Position of CFEIF6 field.
	DMA1_DMA_HIFCR_CFEIF6_Pos = 0x10
	// Bit mask of CFEIF6 field.
	DMA1_DMA_HIFCR_CFEIF6_Msk = 0x10000
	// Bit CFEIF6.
	DMA1_DMA_HIFCR_CFEIF6 = 0x10000
	// Position of CDMEIF6 field.
	DMA1_DMA_HIFCR_CDMEIF6_Pos = 0x12
	// Bit mask of CDMEIF6 field.
	DMA1_DMA_HIFCR_CDMEIF6_Msk = 0x40000
	// Bit CDMEIF6.
	DMA1_DMA_HIFCR_CDMEIF6 = 0x40000
	// Position of CTEIF6 field.
	DMA1_DMA_HIFCR_CTEIF6_Pos = 0x13
	// Bit mask of CTEIF6 field.
	DMA1_DMA_HIFCR_CTEIF6_Msk = 0x80000
	// Bit CTEIF6.
	DMA1_DMA_HIFCR_CTEIF6 = 0x80000
	// Position of CHTIF6 field.
	DMA1_DMA_HIFCR_CHTIF6_Pos = 0x14
	// Bit mask of CHTIF6 field.
	DMA1_DMA_HIFCR_CHTIF6_Msk = 0x100000
	// Bit CHTIF6.
	DMA1_DMA_HIFCR_CHTIF6 = 0x100000
	// Position of CTCIF6 field.
	DMA1_DMA_HIFCR_CTCIF6_Pos = 0x15
	// Bit mask of CTCIF6 field.
	DMA1_DMA_HIFCR_CTCIF6_Msk = 0x200000
	// Bit CTCIF6.
	DMA1_DMA_HIFCR_CTCIF6 = 0x200000
	// Position of CFEIF7 field.
	DMA1_DMA_HIFCR_CFEIF7_Pos = 0x16
	// Bit mask of CFEIF7 field.
	DMA1_DMA_HIFCR_CFEIF7_Msk = 0x400000
	// Bit CFEIF7.
	DMA1_DMA_HIFCR_CFEIF7 = 0x400000
	// Position of CDMEIF7 field.
	DMA1_DMA_HIFCR_CDMEIF7_Pos = 0x18
	// Bit mask of CDMEIF7 field.
	DMA1_DMA_HIFCR_CDMEIF7_Msk = 0x1000000
	// Bit CDMEIF7.
	DMA1_DMA_HIFCR_CDMEIF7 = 0x1000000
	// Position of CTEIF7 field.
	DMA1_DMA_HIFCR_CTEIF7_Pos = 0x19
	// Bit mask of CTEIF7 field.
	DMA1_DMA_HIFCR_CTEIF7_Msk = 0x2000000
	// Bit CTEIF7.
	DMA1_DMA_HIFCR_CTEIF7 = 0x2000000
	// Position of CHTIF7 field.
	DMA1_DMA_HIFCR_CHTIF7_Pos = 0x1a
	// Bit mask of CHTIF7 field.
	DMA1_DMA_HIFCR_CHTIF7_Msk = 0x4000000
	// Bit CHTIF7.
	DMA1_DMA_HIFCR_CHTIF7 = 0x4000000
	// Position of CTCIF7 field.
	DMA1_DMA_HIFCR_CTCIF7_Pos = 0x1b
	// Bit mask of CTCIF7 field.
	DMA1_DMA_HIFCR_CTCIF7_Msk = 0x8000000
	// Bit CTCIF7.
	DMA1_DMA_HIFCR_CTCIF7 = 0x8000000

	// DMA_S0CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S0CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S0CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S0CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S0CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S0CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S0CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S0CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S0CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S0CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S0CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S0CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S0CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S0CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S0CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S0CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S0CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S0CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S0CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S0CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S0CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S0CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S0CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S0CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S0CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S0CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S0CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S0CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S0CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S0CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S0CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S0CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S0CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S0CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S0CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S0CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S0CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S0CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S0CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S0CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S0CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S0CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S0CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S0CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S0CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S0CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S0CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S0CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S0CR_MBURST_Msk = 0x1800000

	// DMA_S0NDTR: DMA stream 0 number of data register
	// Position of NDT field.
	DMA1_DMA_S0NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S0NDTR_NDT_Msk = 0xffff

	// DMA_S0PAR: DMA stream 0 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S0PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S0PAR_PAR_Msk = 0xffffffff

	// DMA_S0M0AR: DMA stream 0 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S0M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S0M0AR_M0A_Msk = 0xffffffff

	// DMA_S0M1AR: DMA stream 0 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S0M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S0M1AR_M1A_Msk = 0xffffffff

	// DMA_S0FCR: DMA stream 0 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S0FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S0FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S0FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S0FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S0FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S0FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S0FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S0FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S0FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S0FCR_FEIE = 0x80

	// DMA_S1CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S1CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S1CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S1CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S1CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S1CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S1CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S1CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S1CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S1CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S1CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S1CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S1CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S1CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S1CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S1CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S1CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S1CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S1CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S1CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S1CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S1CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S1CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S1CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S1CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S1CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S1CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S1CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S1CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S1CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S1CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S1CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S1CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S1CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S1CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S1CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S1CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S1CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S1CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S1CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S1CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S1CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S1CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S1CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S1CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S1CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S1CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S1CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S1CR_MBURST_Msk = 0x1800000

	// DMA_S1NDTR: DMA stream 1 number of data register
	// Position of NDT field.
	DMA1_DMA_S1NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S1NDTR_NDT_Msk = 0xffff

	// DMA_S1PAR: DMA stream 1 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S1PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S1PAR_PAR_Msk = 0xffffffff

	// DMA_S1M0AR: DMA stream 1 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S1M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S1M0AR_M0A_Msk = 0xffffffff

	// DMA_S1M1AR: DMA stream 1 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S1M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S1M1AR_M1A_Msk = 0xffffffff

	// DMA_S1FCR: DMA stream 1 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S1FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S1FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S1FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S1FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S1FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S1FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S1FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S1FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S1FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S1FCR_FEIE = 0x80

	// DMA_S2CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S2CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S2CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S2CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S2CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S2CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S2CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S2CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S2CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S2CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S2CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S2CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S2CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S2CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S2CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S2CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S2CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S2CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S2CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S2CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S2CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S2CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S2CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S2CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S2CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S2CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S2CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S2CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S2CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S2CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S2CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S2CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S2CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S2CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S2CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S2CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S2CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S2CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S2CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S2CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S2CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S2CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S2CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S2CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S2CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S2CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S2CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S2CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S2CR_MBURST_Msk = 0x1800000

	// DMA_S2NDTR: DMA stream 2 number of data register
	// Position of NDT field.
	DMA1_DMA_S2NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S2NDTR_NDT_Msk = 0xffff

	// DMA_S2PAR: DMA stream 2 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S2PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S2PAR_PAR_Msk = 0xffffffff

	// DMA_S2M0AR: DMA stream 2 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S2M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S2M0AR_M0A_Msk = 0xffffffff

	// DMA_S2M1AR: DMA stream 2 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S2M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S2M1AR_M1A_Msk = 0xffffffff

	// DMA_S2FCR: DMA stream 2 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S2FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S2FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S2FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S2FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S2FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S2FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S2FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S2FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S2FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S2FCR_FEIE = 0x80

	// DMA_S3CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S3CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S3CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S3CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S3CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S3CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S3CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S3CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S3CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S3CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S3CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S3CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S3CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S3CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S3CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S3CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S3CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S3CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S3CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S3CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S3CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S3CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S3CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S3CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S3CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S3CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S3CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S3CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S3CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S3CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S3CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S3CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S3CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S3CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S3CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S3CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S3CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S3CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S3CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S3CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S3CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S3CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S3CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S3CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S3CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S3CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S3CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S3CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S3CR_MBURST_Msk = 0x1800000

	// DMA_S3NDTR: DMA stream 3 number of data register
	// Position of NDT field.
	DMA1_DMA_S3NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S3NDTR_NDT_Msk = 0xffff

	// DMA_S3PAR: DMA stream 3 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S3PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S3PAR_PAR_Msk = 0xffffffff

	// DMA_S3M0AR: DMA stream 3 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S3M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S3M0AR_M0A_Msk = 0xffffffff

	// DMA_S3M1AR: DMA stream 3 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S3M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S3M1AR_M1A_Msk = 0xffffffff

	// DMA_S3FCR: DMA stream 3 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S3FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S3FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S3FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S3FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S3FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S3FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S3FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S3FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S3FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S3FCR_FEIE = 0x80

	// DMA_S4CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S4CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S4CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S4CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S4CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S4CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S4CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S4CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S4CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S4CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S4CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S4CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S4CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S4CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S4CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S4CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S4CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S4CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S4CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S4CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S4CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S4CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S4CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S4CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S4CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S4CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S4CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S4CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S4CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S4CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S4CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S4CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S4CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S4CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S4CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S4CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S4CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S4CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S4CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S4CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S4CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S4CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S4CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S4CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S4CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S4CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S4CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S4CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S4CR_MBURST_Msk = 0x1800000

	// DMA_S4NDTR: DMA stream 4 number of data register
	// Position of NDT field.
	DMA1_DMA_S4NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S4NDTR_NDT_Msk = 0xffff

	// DMA_S4PAR: DMA stream 4 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S4PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S4PAR_PAR_Msk = 0xffffffff

	// DMA_S4M0AR: DMA stream 4 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S4M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S4M0AR_M0A_Msk = 0xffffffff

	// DMA_S4M1AR: DMA stream 4 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S4M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S4M1AR_M1A_Msk = 0xffffffff

	// DMA_S4FCR: DMA stream 4 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S4FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S4FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S4FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S4FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S4FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S4FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S4FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S4FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S4FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S4FCR_FEIE = 0x80

	// DMA_S5CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S5CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S5CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S5CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S5CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S5CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S5CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S5CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S5CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S5CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S5CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S5CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S5CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S5CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S5CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S5CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S5CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S5CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S5CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S5CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S5CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S5CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S5CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S5CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S5CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S5CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S5CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S5CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S5CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S5CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S5CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S5CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S5CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S5CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S5CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S5CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S5CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S5CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S5CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S5CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S5CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S5CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S5CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S5CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S5CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S5CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S5CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S5CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S5CR_MBURST_Msk = 0x1800000

	// DMA_S5NDTR: DMA stream 5 number of data register
	// Position of NDT field.
	DMA1_DMA_S5NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S5NDTR_NDT_Msk = 0xffff

	// DMA_S5PAR: DMA stream 5 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S5PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S5PAR_PAR_Msk = 0xffffffff

	// DMA_S5M0AR: DMA stream 5 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S5M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S5M0AR_M0A_Msk = 0xffffffff

	// DMA_S5M1AR: DMA stream 5 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S5M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S5M1AR_M1A_Msk = 0xffffffff

	// DMA_S5FCR: DMA stream 5 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S5FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S5FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S5FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S5FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S5FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S5FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S5FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S5FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S5FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S5FCR_FEIE = 0x80

	// DMA_S6CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S6CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S6CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S6CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S6CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S6CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S6CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S6CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S6CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S6CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S6CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S6CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S6CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S6CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S6CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S6CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S6CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S6CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S6CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S6CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S6CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S6CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S6CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S6CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S6CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S6CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S6CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S6CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S6CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S6CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S6CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S6CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S6CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S6CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S6CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S6CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S6CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S6CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S6CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S6CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S6CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S6CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S6CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S6CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S6CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S6CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S6CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S6CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S6CR_MBURST_Msk = 0x1800000

	// DMA_S6NDTR: DMA stream 6 number of data register
	// Position of NDT field.
	DMA1_DMA_S6NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S6NDTR_NDT_Msk = 0xffff

	// DMA_S6PAR: DMA stream 6 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S6PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S6PAR_PAR_Msk = 0xffffffff

	// DMA_S6M0AR: DMA stream 6 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S6M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S6M0AR_M0A_Msk = 0xffffffff

	// DMA_S6M1AR: DMA stream 6 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S6M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S6M1AR_M1A_Msk = 0xffffffff

	// DMA_S6FCR: DMA stream 6 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S6FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S6FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S6FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S6FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S6FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S6FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S6FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S6FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S6FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S6FCR_FEIE = 0x80

	// DMA_S7CR: This register is used to configure the concerned stream.
	// Position of EN field.
	DMA1_DMA_S7CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA1_DMA_S7CR_EN_Msk = 0x1
	// Bit EN.
	DMA1_DMA_S7CR_EN = 0x1
	// Position of DMEIE field.
	DMA1_DMA_S7CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA1_DMA_S7CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA1_DMA_S7CR_DMEIE = 0x2
	// Position of TEIE field.
	DMA1_DMA_S7CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA1_DMA_S7CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA1_DMA_S7CR_TEIE = 0x4
	// Position of HTIE field.
	DMA1_DMA_S7CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA1_DMA_S7CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA1_DMA_S7CR_HTIE = 0x8
	// Position of TCIE field.
	DMA1_DMA_S7CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA1_DMA_S7CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA1_DMA_S7CR_TCIE = 0x10
	// Position of PFCTRL field.
	DMA1_DMA_S7CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA1_DMA_S7CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA1_DMA_S7CR_PFCTRL = 0x20
	// Position of DIR field.
	DMA1_DMA_S7CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA1_DMA_S7CR_DIR_Msk = 0xc0
	// Position of CIRC field.
	DMA1_DMA_S7CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA1_DMA_S7CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA1_DMA_S7CR_CIRC = 0x100
	// Position of PINC field.
	DMA1_DMA_S7CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA1_DMA_S7CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA1_DMA_S7CR_PINC = 0x200
	// Position of MINC field.
	DMA1_DMA_S7CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA1_DMA_S7CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA1_DMA_S7CR_MINC = 0x400
	// Position of PSIZE field.
	DMA1_DMA_S7CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA1_DMA_S7CR_PSIZE_Msk = 0x1800
	// Position of MSIZE field.
	DMA1_DMA_S7CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA1_DMA_S7CR_MSIZE_Msk = 0x6000
	// Position of PINCOS field.
	DMA1_DMA_S7CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA1_DMA_S7CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA1_DMA_S7CR_PINCOS = 0x8000
	// Position of PL field.
	DMA1_DMA_S7CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA1_DMA_S7CR_PL_Msk = 0x30000
	// Position of DBM field.
	DMA1_DMA_S7CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA1_DMA_S7CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA1_DMA_S7CR_DBM = 0x40000
	// Position of CT field.
	DMA1_DMA_S7CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA1_DMA_S7CR_CT_Msk = 0x80000
	// Bit CT.
	DMA1_DMA_S7CR_CT = 0x80000
	// Position of PBURST field.
	DMA1_DMA_S7CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA1_DMA_S7CR_PBURST_Msk = 0x600000
	// Position of MBURST field.
	DMA1_DMA_S7CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA1_DMA_S7CR_MBURST_Msk = 0x1800000

	// DMA_S7NDTR: DMA stream 7 number of data register
	// Position of NDT field.
	DMA1_DMA_S7NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA1_DMA_S7NDTR_NDT_Msk = 0xffff

	// DMA_S7PAR: DMA stream 7 peripheral address register
	// Position of PAR field.
	DMA1_DMA_S7PAR_PAR_Pos = 0x0
	// Bit mask of PAR field.
	DMA1_DMA_S7PAR_PAR_Msk = 0xffffffff

	// DMA_S7M0AR: DMA stream 7 memory 0 address register
	// Position of M0A field.
	DMA1_DMA_S7M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA1_DMA_S7M0AR_M0A_Msk = 0xffffffff

	// DMA_S7M1AR: DMA stream 7 memory 1 address register
	// Position of M1A field.
	DMA1_DMA_S7M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA1_DMA_S7M1AR_M1A_Msk = 0xffffffff

	// DMA_S7FCR: DMA stream 7 FIFO control register
	// Position of FTH field.
	DMA1_DMA_S7FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA1_DMA_S7FCR_FTH_Msk = 0x3
	// Position of DMDIS field.
	DMA1_DMA_S7FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA1_DMA_S7FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA1_DMA_S7FCR_DMDIS = 0x4
	// Position of FS field.
	DMA1_DMA_S7FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA1_DMA_S7FCR_FS_Msk = 0x38
	// Position of FEIE field.
	DMA1_DMA_S7FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA1_DMA_S7FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA1_DMA_S7FCR_FEIE = 0x80

	// DMA_HWCFGR2: DMA hardware configuration 2register
	// Position of FIFO_SIZE field.
	DMA1_DMA_HWCFGR2_FIFO_SIZE_Pos = 0x0
	// Bit mask of FIFO_SIZE field.
	DMA1_DMA_HWCFGR2_FIFO_SIZE_Msk = 0x3
	// Position of WRITE_BUFFERABLE field.
	DMA1_DMA_HWCFGR2_WRITE_BUFFERABLE_Pos = 0x4
	// Bit mask of WRITE_BUFFERABLE field.
	DMA1_DMA_HWCFGR2_WRITE_BUFFERABLE_Msk = 0x10
	// Bit WRITE_BUFFERABLE.
	DMA1_DMA_HWCFGR2_WRITE_BUFFERABLE = 0x10
	// Position of CHSEL_WIDTH field.
	DMA1_DMA_HWCFGR2_CHSEL_WIDTH_Pos = 0x8
	// Bit mask of CHSEL_WIDTH field.
	DMA1_DMA_HWCFGR2_CHSEL_WIDTH_Msk = 0x700

	// DMA_HWCFGR1: DMA hardware configuration 1 register
	// Position of DMA_DEF0 field.
	DMA1_DMA_HWCFGR1_DMA_DEF0_Pos = 0x0
	// Bit mask of DMA_DEF0 field.
	DMA1_DMA_HWCFGR1_DMA_DEF0_Msk = 0x3
	// Position of DMA_DEF1 field.
	DMA1_DMA_HWCFGR1_DMA_DEF1_Pos = 0x4
	// Bit mask of DMA_DEF1 field.
	DMA1_DMA_HWCFGR1_DMA_DEF1_Msk = 0x30
	// Position of DMA_DEF2 field.
	DMA1_DMA_HWCFGR1_DMA_DEF2_Pos = 0x8
	// Bit mask of DMA_DEF2 field.
	DMA1_DMA_HWCFGR1_DMA_DEF2_Msk = 0x300
	// Position of DMA_DEF3 field.
	DMA1_DMA_HWCFGR1_DMA_DEF3_Pos = 0xc
	// Bit mask of DMA_DEF3 field.
	DMA1_DMA_HWCFGR1_DMA_DEF3_Msk = 0x3000
	// Position of DMA_DEF4 field.
	DMA1_DMA_HWCFGR1_DMA_DEF4_Pos = 0x10
	// Bit mask of DMA_DEF4 field.
	DMA1_DMA_HWCFGR1_DMA_DEF4_Msk = 0x30000
	// Position of DMA_DEF5 field.
	DMA1_DMA_HWCFGR1_DMA_DEF5_Pos = 0x14
	// Bit mask of DMA_DEF5 field.
	DMA1_DMA_HWCFGR1_DMA_DEF5_Msk = 0x300000
	// Position of DMA_DEF6 field.
	DMA1_DMA_HWCFGR1_DMA_DEF6_Pos = 0x18
	// Bit mask of DMA_DEF6 field.
	DMA1_DMA_HWCFGR1_DMA_DEF6_Msk = 0x3000000
	// Position of DMA_DEF7 field.
	DMA1_DMA_HWCFGR1_DMA_DEF7_Pos = 0x1c
	// Bit mask of DMA_DEF7 field.
	DMA1_DMA_HWCFGR1_DMA_DEF7_Msk = 0x30000000

	// DMA_VERR: This register identifies the version of the IP.
	// Position of MINREV field.
	DMA1_DMA_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DMA1_DMA_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DMA1_DMA_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DMA1_DMA_VERR_MAJREV_Msk = 0xf0

	// DMA_IPDR: DMA IP identification register
	// Position of ID field.
	DMA1_DMA_IPDR_ID_Pos = 0x0
	// Bit mask of ID field.
	DMA1_DMA_IPDR_ID_Msk = 0xffffffff

	// DMA_SIDR: DMA size identification register
	// Position of SID field.
	DMA1_DMA_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	DMA1_DMA_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for DMAMUX1: DMAMUX1
const (
	// DMAMUX_C0CR: DMAMUX request line multiplexer channel 0 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C0CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C0CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C0CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C0CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C0CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C0CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C0CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C0CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C0CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C0CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C0CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C0CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C0CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C0CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C0CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C0CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C0CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C1CR: DMAMUX request line multiplexer channel 1 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C1CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C1CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C1CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C1CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C1CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C1CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C1CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C1CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C1CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C1CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C1CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C1CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C1CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C1CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C1CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C1CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C1CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C2CR: DMAMUX request line multiplexer channel 2 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C2CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C2CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C2CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C2CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C2CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C2CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C2CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C2CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C2CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C2CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C2CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C2CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C2CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C2CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C2CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C2CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C2CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C3CR: DMAMUX request line multiplexer channel 3 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C3CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C3CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C3CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C3CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C3CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C3CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C3CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C3CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C3CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C3CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C3CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C3CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C3CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C3CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C3CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C3CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C3CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C4CR: DMAMUX request line multiplexer channel 4 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C4CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C4CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C4CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C4CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C4CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C4CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C4CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C4CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C4CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C4CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C4CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C4CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C4CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C4CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C4CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C4CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C4CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C5CR: DMAMUX request line multiplexer channel 5 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C5CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C5CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C5CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C5CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C5CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C5CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C5CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C5CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C5CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C5CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C5CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C5CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C5CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C5CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C5CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C5CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C5CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C6CR: DMAMUX request line multiplexer channel 6 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C6CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C6CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C6CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C6CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C6CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C6CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C6CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C6CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C6CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C6CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C6CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C6CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C6CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C6CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C6CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C6CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C6CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C7CR: DMAMUX request line multiplexer channel 7 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C7CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C7CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C7CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C7CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C7CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C7CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C7CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C7CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C7CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C7CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C7CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C7CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C7CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C7CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C7CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C7CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C7CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C8CR: DMAMUX request line multiplexer channel 8 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C8CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C8CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C8CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C8CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C8CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C8CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C8CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C8CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C8CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C8CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C8CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C8CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C8CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C8CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C8CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C8CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C8CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C9CR: DMAMUX request line multiplexer channel 9 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C9CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C9CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C9CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C9CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C9CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C9CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C9CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C9CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C9CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C9CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C9CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C9CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C9CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C9CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C9CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C9CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C9CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C10CR: DMAMUX request line multiplexer channel 10 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C10CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C10CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C10CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C10CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C10CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C10CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C10CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C10CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C10CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C10CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C10CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C10CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C10CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C10CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C10CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C10CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C10CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C11CR: DMAMUX request line multiplexer channel 11 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C11CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C11CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C11CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C11CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C11CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C11CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C11CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C11CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C11CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C11CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C11CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C11CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C11CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C11CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C11CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C11CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C11CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C12CR: DMAMUX request line multiplexer channel 12 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C12CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C12CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C12CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C12CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C12CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C12CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C12CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C12CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C12CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C12CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C12CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C12CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C12CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C12CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C12CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C12CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C12CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C13CR: DMAMUX request line multiplexer channel 13 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C13CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C13CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C13CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C13CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C13CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C13CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C13CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C13CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C13CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C13CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C13CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C13CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C13CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C13CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C13CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C13CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C13CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C14CR: DMAMUX request line multiplexer channel 14 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C14CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C14CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C14CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C14CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C14CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C14CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C14CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C14CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C14CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C14CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C14CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C14CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C14CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C14CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C14CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C14CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C14CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_C15CR: DMAMUX request line multiplexer channel 15 configuration register
	// Position of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C15CR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX1_DMAMUX_C15CR_DMAREQ_ID_Msk = 0x7f
	// Position of SOIE field.
	DMAMUX1_DMAMUX_C15CR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX1_DMAMUX_C15CR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX1_DMAMUX_C15CR_SOIE = 0x100
	// Position of EGE field.
	DMAMUX1_DMAMUX_C15CR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX1_DMAMUX_C15CR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX1_DMAMUX_C15CR_EGE = 0x200
	// Position of SE field.
	DMAMUX1_DMAMUX_C15CR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX1_DMAMUX_C15CR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX1_DMAMUX_C15CR_SE = 0x10000
	// Position of SPOL field.
	DMAMUX1_DMAMUX_C15CR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX1_DMAMUX_C15CR_SPOL_Msk = 0x60000
	// Position of NBREQ field.
	DMAMUX1_DMAMUX_C15CR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX1_DMAMUX_C15CR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX1_DMAMUX_C15CR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX1_DMAMUX_C15CR_SYNC_ID_Msk = 0x7000000

	// DMAMUX_CSR: DMAMUX request line multiplexer interrupt channel status register
	// Position of SOF0 field.
	DMAMUX1_DMAMUX_CSR_SOF0_Pos = 0x0
	// Bit mask of SOF0 field.
	DMAMUX1_DMAMUX_CSR_SOF0_Msk = 0x1
	// Bit SOF0.
	DMAMUX1_DMAMUX_CSR_SOF0 = 0x1
	// Position of SOF1 field.
	DMAMUX1_DMAMUX_CSR_SOF1_Pos = 0x1
	// Bit mask of SOF1 field.
	DMAMUX1_DMAMUX_CSR_SOF1_Msk = 0x2
	// Bit SOF1.
	DMAMUX1_DMAMUX_CSR_SOF1 = 0x2
	// Position of SOF2 field.
	DMAMUX1_DMAMUX_CSR_SOF2_Pos = 0x2
	// Bit mask of SOF2 field.
	DMAMUX1_DMAMUX_CSR_SOF2_Msk = 0x4
	// Bit SOF2.
	DMAMUX1_DMAMUX_CSR_SOF2 = 0x4
	// Position of SOF3 field.
	DMAMUX1_DMAMUX_CSR_SOF3_Pos = 0x3
	// Bit mask of SOF3 field.
	DMAMUX1_DMAMUX_CSR_SOF3_Msk = 0x8
	// Bit SOF3.
	DMAMUX1_DMAMUX_CSR_SOF3 = 0x8
	// Position of SOF4 field.
	DMAMUX1_DMAMUX_CSR_SOF4_Pos = 0x4
	// Bit mask of SOF4 field.
	DMAMUX1_DMAMUX_CSR_SOF4_Msk = 0x10
	// Bit SOF4.
	DMAMUX1_DMAMUX_CSR_SOF4 = 0x10
	// Position of SOF5 field.
	DMAMUX1_DMAMUX_CSR_SOF5_Pos = 0x5
	// Bit mask of SOF5 field.
	DMAMUX1_DMAMUX_CSR_SOF5_Msk = 0x20
	// Bit SOF5.
	DMAMUX1_DMAMUX_CSR_SOF5 = 0x20
	// Position of SOF6 field.
	DMAMUX1_DMAMUX_CSR_SOF6_Pos = 0x6
	// Bit mask of SOF6 field.
	DMAMUX1_DMAMUX_CSR_SOF6_Msk = 0x40
	// Bit SOF6.
	DMAMUX1_DMAMUX_CSR_SOF6 = 0x40
	// Position of SOF7 field.
	DMAMUX1_DMAMUX_CSR_SOF7_Pos = 0x7
	// Bit mask of SOF7 field.
	DMAMUX1_DMAMUX_CSR_SOF7_Msk = 0x80
	// Bit SOF7.
	DMAMUX1_DMAMUX_CSR_SOF7 = 0x80
	// Position of SOF8 field.
	DMAMUX1_DMAMUX_CSR_SOF8_Pos = 0x8
	// Bit mask of SOF8 field.
	DMAMUX1_DMAMUX_CSR_SOF8_Msk = 0x100
	// Bit SOF8.
	DMAMUX1_DMAMUX_CSR_SOF8 = 0x100
	// Position of SOF9 field.
	DMAMUX1_DMAMUX_CSR_SOF9_Pos = 0x9
	// Bit mask of SOF9 field.
	DMAMUX1_DMAMUX_CSR_SOF9_Msk = 0x200
	// Bit SOF9.
	DMAMUX1_DMAMUX_CSR_SOF9 = 0x200
	// Position of SOF10 field.
	DMAMUX1_DMAMUX_CSR_SOF10_Pos = 0xa
	// Bit mask of SOF10 field.
	DMAMUX1_DMAMUX_CSR_SOF10_Msk = 0x400
	// Bit SOF10.
	DMAMUX1_DMAMUX_CSR_SOF10 = 0x400
	// Position of SOF11 field.
	DMAMUX1_DMAMUX_CSR_SOF11_Pos = 0xb
	// Bit mask of SOF11 field.
	DMAMUX1_DMAMUX_CSR_SOF11_Msk = 0x800
	// Bit SOF11.
	DMAMUX1_DMAMUX_CSR_SOF11 = 0x800
	// Position of SOF12 field.
	DMAMUX1_DMAMUX_CSR_SOF12_Pos = 0xc
	// Bit mask of SOF12 field.
	DMAMUX1_DMAMUX_CSR_SOF12_Msk = 0x1000
	// Bit SOF12.
	DMAMUX1_DMAMUX_CSR_SOF12 = 0x1000
	// Position of SOF13 field.
	DMAMUX1_DMAMUX_CSR_SOF13_Pos = 0xd
	// Bit mask of SOF13 field.
	DMAMUX1_DMAMUX_CSR_SOF13_Msk = 0x2000
	// Bit SOF13.
	DMAMUX1_DMAMUX_CSR_SOF13 = 0x2000
	// Position of SOF14 field.
	DMAMUX1_DMAMUX_CSR_SOF14_Pos = 0xe
	// Bit mask of SOF14 field.
	DMAMUX1_DMAMUX_CSR_SOF14_Msk = 0x4000
	// Bit SOF14.
	DMAMUX1_DMAMUX_CSR_SOF14 = 0x4000
	// Position of SOF15 field.
	DMAMUX1_DMAMUX_CSR_SOF15_Pos = 0xf
	// Bit mask of SOF15 field.
	DMAMUX1_DMAMUX_CSR_SOF15_Msk = 0x8000
	// Bit SOF15.
	DMAMUX1_DMAMUX_CSR_SOF15 = 0x8000

	// DMAMUX_CFR: DMAMUX request line multiplexer interrupt clear flag register
	// Position of CSOF0 field.
	DMAMUX1_DMAMUX_CFR_CSOF0_Pos = 0x0
	// Bit mask of CSOF0 field.
	DMAMUX1_DMAMUX_CFR_CSOF0_Msk = 0x1
	// Bit CSOF0.
	DMAMUX1_DMAMUX_CFR_CSOF0 = 0x1
	// Position of CSOF1 field.
	DMAMUX1_DMAMUX_CFR_CSOF1_Pos = 0x1
	// Bit mask of CSOF1 field.
	DMAMUX1_DMAMUX_CFR_CSOF1_Msk = 0x2
	// Bit CSOF1.
	DMAMUX1_DMAMUX_CFR_CSOF1 = 0x2
	// Position of CSOF2 field.
	DMAMUX1_DMAMUX_CFR_CSOF2_Pos = 0x2
	// Bit mask of CSOF2 field.
	DMAMUX1_DMAMUX_CFR_CSOF2_Msk = 0x4
	// Bit CSOF2.
	DMAMUX1_DMAMUX_CFR_CSOF2 = 0x4
	// Position of CSOF3 field.
	DMAMUX1_DMAMUX_CFR_CSOF3_Pos = 0x3
	// Bit mask of CSOF3 field.
	DMAMUX1_DMAMUX_CFR_CSOF3_Msk = 0x8
	// Bit CSOF3.
	DMAMUX1_DMAMUX_CFR_CSOF3 = 0x8
	// Position of CSOF4 field.
	DMAMUX1_DMAMUX_CFR_CSOF4_Pos = 0x4
	// Bit mask of CSOF4 field.
	DMAMUX1_DMAMUX_CFR_CSOF4_Msk = 0x10
	// Bit CSOF4.
	DMAMUX1_DMAMUX_CFR_CSOF4 = 0x10
	// Position of CSOF5 field.
	DMAMUX1_DMAMUX_CFR_CSOF5_Pos = 0x5
	// Bit mask of CSOF5 field.
	DMAMUX1_DMAMUX_CFR_CSOF5_Msk = 0x20
	// Bit CSOF5.
	DMAMUX1_DMAMUX_CFR_CSOF5 = 0x20
	// Position of CSOF6 field.
	DMAMUX1_DMAMUX_CFR_CSOF6_Pos = 0x6
	// Bit mask of CSOF6 field.
	DMAMUX1_DMAMUX_CFR_CSOF6_Msk = 0x40
	// Bit CSOF6.
	DMAMUX1_DMAMUX_CFR_CSOF6 = 0x40
	// Position of CSOF7 field.
	DMAMUX1_DMAMUX_CFR_CSOF7_Pos = 0x7
	// Bit mask of CSOF7 field.
	DMAMUX1_DMAMUX_CFR_CSOF7_Msk = 0x80
	// Bit CSOF7.
	DMAMUX1_DMAMUX_CFR_CSOF7 = 0x80
	// Position of CSOF8 field.
	DMAMUX1_DMAMUX_CFR_CSOF8_Pos = 0x8
	// Bit mask of CSOF8 field.
	DMAMUX1_DMAMUX_CFR_CSOF8_Msk = 0x100
	// Bit CSOF8.
	DMAMUX1_DMAMUX_CFR_CSOF8 = 0x100
	// Position of CSOF9 field.
	DMAMUX1_DMAMUX_CFR_CSOF9_Pos = 0x9
	// Bit mask of CSOF9 field.
	DMAMUX1_DMAMUX_CFR_CSOF9_Msk = 0x200
	// Bit CSOF9.
	DMAMUX1_DMAMUX_CFR_CSOF9 = 0x200
	// Position of CSOF10 field.
	DMAMUX1_DMAMUX_CFR_CSOF10_Pos = 0xa
	// Bit mask of CSOF10 field.
	DMAMUX1_DMAMUX_CFR_CSOF10_Msk = 0x400
	// Bit CSOF10.
	DMAMUX1_DMAMUX_CFR_CSOF10 = 0x400
	// Position of CSOF11 field.
	DMAMUX1_DMAMUX_CFR_CSOF11_Pos = 0xb
	// Bit mask of CSOF11 field.
	DMAMUX1_DMAMUX_CFR_CSOF11_Msk = 0x800
	// Bit CSOF11.
	DMAMUX1_DMAMUX_CFR_CSOF11 = 0x800
	// Position of CSOF12 field.
	DMAMUX1_DMAMUX_CFR_CSOF12_Pos = 0xc
	// Bit mask of CSOF12 field.
	DMAMUX1_DMAMUX_CFR_CSOF12_Msk = 0x1000
	// Bit CSOF12.
	DMAMUX1_DMAMUX_CFR_CSOF12 = 0x1000
	// Position of CSOF13 field.
	DMAMUX1_DMAMUX_CFR_CSOF13_Pos = 0xd
	// Bit mask of CSOF13 field.
	DMAMUX1_DMAMUX_CFR_CSOF13_Msk = 0x2000
	// Bit CSOF13.
	DMAMUX1_DMAMUX_CFR_CSOF13 = 0x2000
	// Position of CSOF14 field.
	DMAMUX1_DMAMUX_CFR_CSOF14_Pos = 0xe
	// Bit mask of CSOF14 field.
	DMAMUX1_DMAMUX_CFR_CSOF14_Msk = 0x4000
	// Bit CSOF14.
	DMAMUX1_DMAMUX_CFR_CSOF14 = 0x4000
	// Position of CSOF15 field.
	DMAMUX1_DMAMUX_CFR_CSOF15_Pos = 0xf
	// Bit mask of CSOF15 field.
	DMAMUX1_DMAMUX_CFR_CSOF15_Msk = 0x8000
	// Bit CSOF15.
	DMAMUX1_DMAMUX_CFR_CSOF15 = 0x8000

	// DMAMUX_RG0CR: DMAMUX request generator channel 0 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG0CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG0CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG0CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG0CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG0CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG0CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG0CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG0CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG0CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG0CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG0CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG0CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RG1CR: DMAMUX request generator channel 1 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG1CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG1CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG1CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG1CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG1CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG1CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG1CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG1CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG1CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG1CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG1CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG1CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RG2CR: DMAMUX request generator channel 2 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG2CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG2CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG2CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG2CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG2CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG2CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG2CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG2CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG2CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG2CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG2CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG2CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RG3CR: DMAMUX request generator channel 3 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG3CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG3CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG3CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG3CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG3CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG3CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG3CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG3CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG3CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG3CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG3CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG3CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RG4CR: DMAMUX request generator channel 4 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG4CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG4CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG4CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG4CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG4CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG4CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG4CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG4CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG4CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG4CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG4CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG4CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RG5CR: DMAMUX request generator channel 5 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG5CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG5CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG5CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG5CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG5CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG5CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG5CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG5CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG5CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG5CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG5CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG5CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RG6CR: DMAMUX request generator channel 6 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG6CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG6CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG6CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG6CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG6CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG6CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG6CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG6CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG6CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG6CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG6CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG6CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RG7CR: DMAMUX request generator channel 7 configuration register
	// Position of SIG_ID field.
	DMAMUX1_DMAMUX_RG7CR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX1_DMAMUX_RG7CR_SIG_ID_Msk = 0x7
	// Position of OIE field.
	DMAMUX1_DMAMUX_RG7CR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX1_DMAMUX_RG7CR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX1_DMAMUX_RG7CR_OIE = 0x100
	// Position of GE field.
	DMAMUX1_DMAMUX_RG7CR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX1_DMAMUX_RG7CR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX1_DMAMUX_RG7CR_GE = 0x10000
	// Position of GPOL field.
	DMAMUX1_DMAMUX_RG7CR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX1_DMAMUX_RG7CR_GPOL_Msk = 0x60000
	// Position of GNBREQ field.
	DMAMUX1_DMAMUX_RG7CR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX1_DMAMUX_RG7CR_GNBREQ_Msk = 0xf80000

	// DMAMUX_RGSR: DMAMUX request generator interrupt status register
	// Position of OF0 field.
	DMAMUX1_DMAMUX_RGSR_OF0_Pos = 0x0
	// Bit mask of OF0 field.
	DMAMUX1_DMAMUX_RGSR_OF0_Msk = 0x1
	// Bit OF0.
	DMAMUX1_DMAMUX_RGSR_OF0 = 0x1
	// Position of OF1 field.
	DMAMUX1_DMAMUX_RGSR_OF1_Pos = 0x1
	// Bit mask of OF1 field.
	DMAMUX1_DMAMUX_RGSR_OF1_Msk = 0x2
	// Bit OF1.
	DMAMUX1_DMAMUX_RGSR_OF1 = 0x2
	// Position of OF2 field.
	DMAMUX1_DMAMUX_RGSR_OF2_Pos = 0x2
	// Bit mask of OF2 field.
	DMAMUX1_DMAMUX_RGSR_OF2_Msk = 0x4
	// Bit OF2.
	DMAMUX1_DMAMUX_RGSR_OF2 = 0x4
	// Position of OF3 field.
	DMAMUX1_DMAMUX_RGSR_OF3_Pos = 0x3
	// Bit mask of OF3 field.
	DMAMUX1_DMAMUX_RGSR_OF3_Msk = 0x8
	// Bit OF3.
	DMAMUX1_DMAMUX_RGSR_OF3 = 0x8
	// Position of OF4 field.
	DMAMUX1_DMAMUX_RGSR_OF4_Pos = 0x4
	// Bit mask of OF4 field.
	DMAMUX1_DMAMUX_RGSR_OF4_Msk = 0x10
	// Bit OF4.
	DMAMUX1_DMAMUX_RGSR_OF4 = 0x10
	// Position of OF5 field.
	DMAMUX1_DMAMUX_RGSR_OF5_Pos = 0x5
	// Bit mask of OF5 field.
	DMAMUX1_DMAMUX_RGSR_OF5_Msk = 0x20
	// Bit OF5.
	DMAMUX1_DMAMUX_RGSR_OF5 = 0x20
	// Position of OF6 field.
	DMAMUX1_DMAMUX_RGSR_OF6_Pos = 0x6
	// Bit mask of OF6 field.
	DMAMUX1_DMAMUX_RGSR_OF6_Msk = 0x40
	// Bit OF6.
	DMAMUX1_DMAMUX_RGSR_OF6 = 0x40
	// Position of OF7 field.
	DMAMUX1_DMAMUX_RGSR_OF7_Pos = 0x7
	// Bit mask of OF7 field.
	DMAMUX1_DMAMUX_RGSR_OF7_Msk = 0x80
	// Bit OF7.
	DMAMUX1_DMAMUX_RGSR_OF7 = 0x80

	// DMAMUX_RGCFR: DMAMUX request generator interrupt clear flag register
	// Position of COF0 field.
	DMAMUX1_DMAMUX_RGCFR_COF0_Pos = 0x0
	// Bit mask of COF0 field.
	DMAMUX1_DMAMUX_RGCFR_COF0_Msk = 0x1
	// Bit COF0.
	DMAMUX1_DMAMUX_RGCFR_COF0 = 0x1
	// Position of COF1 field.
	DMAMUX1_DMAMUX_RGCFR_COF1_Pos = 0x1
	// Bit mask of COF1 field.
	DMAMUX1_DMAMUX_RGCFR_COF1_Msk = 0x2
	// Bit COF1.
	DMAMUX1_DMAMUX_RGCFR_COF1 = 0x2
	// Position of COF2 field.
	DMAMUX1_DMAMUX_RGCFR_COF2_Pos = 0x2
	// Bit mask of COF2 field.
	DMAMUX1_DMAMUX_RGCFR_COF2_Msk = 0x4
	// Bit COF2.
	DMAMUX1_DMAMUX_RGCFR_COF2 = 0x4
	// Position of COF3 field.
	DMAMUX1_DMAMUX_RGCFR_COF3_Pos = 0x3
	// Bit mask of COF3 field.
	DMAMUX1_DMAMUX_RGCFR_COF3_Msk = 0x8
	// Bit COF3.
	DMAMUX1_DMAMUX_RGCFR_COF3 = 0x8
	// Position of COF4 field.
	DMAMUX1_DMAMUX_RGCFR_COF4_Pos = 0x4
	// Bit mask of COF4 field.
	DMAMUX1_DMAMUX_RGCFR_COF4_Msk = 0x10
	// Bit COF4.
	DMAMUX1_DMAMUX_RGCFR_COF4 = 0x10
	// Position of COF5 field.
	DMAMUX1_DMAMUX_RGCFR_COF5_Pos = 0x5
	// Bit mask of COF5 field.
	DMAMUX1_DMAMUX_RGCFR_COF5_Msk = 0x20
	// Bit COF5.
	DMAMUX1_DMAMUX_RGCFR_COF5 = 0x20
	// Position of COF6 field.
	DMAMUX1_DMAMUX_RGCFR_COF6_Pos = 0x6
	// Bit mask of COF6 field.
	DMAMUX1_DMAMUX_RGCFR_COF6_Msk = 0x40
	// Bit COF6.
	DMAMUX1_DMAMUX_RGCFR_COF6 = 0x40
	// Position of COF7 field.
	DMAMUX1_DMAMUX_RGCFR_COF7_Pos = 0x7
	// Bit mask of COF7 field.
	DMAMUX1_DMAMUX_RGCFR_COF7_Msk = 0x80
	// Bit COF7.
	DMAMUX1_DMAMUX_RGCFR_COF7 = 0x80

	// DMAMUX_HWCFGR2: DMAMUX hardware configuration 2 register
	// Position of NUM_DMA_EXT_REQ field.
	DMAMUX1_DMAMUX_HWCFGR2_NUM_DMA_EXT_REQ_Pos = 0x0
	// Bit mask of NUM_DMA_EXT_REQ field.
	DMAMUX1_DMAMUX_HWCFGR2_NUM_DMA_EXT_REQ_Msk = 0xff

	// DMAMUX_HWCFGR1: DMAMUX hardware configuration 1 register
	// Position of NUM_DMA_STREAMS field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_STREAMS_Pos = 0x0
	// Bit mask of NUM_DMA_STREAMS field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_STREAMS_Msk = 0xff
	// Position of NUM_DMA_PERIPH_REQ field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_PERIPH_REQ_Pos = 0x8
	// Bit mask of NUM_DMA_PERIPH_REQ field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_PERIPH_REQ_Msk = 0xff00
	// Position of NUM_DMA_TRIG field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_TRIG_Pos = 0x10
	// Bit mask of NUM_DMA_TRIG field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_TRIG_Msk = 0xff0000
	// Position of NUM_DMA_REQGEN field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_REQGEN_Pos = 0x18
	// Bit mask of NUM_DMA_REQGEN field.
	DMAMUX1_DMAMUX_HWCFGR1_NUM_DMA_REQGEN_Msk = 0xff000000

	// DMAMUX_VERR: This register identifies the IP version.
	// Position of MINREV field.
	DMAMUX1_DMAMUX_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DMAMUX1_DMAMUX_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DMAMUX1_DMAMUX_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DMAMUX1_DMAMUX_VERR_MAJREV_Msk = 0xf0

	// DMAMUX_IPIDR: This register identifies the IP.
	// Position of ID field.
	DMAMUX1_DMAMUX_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	DMAMUX1_DMAMUX_IPIDR_ID_Msk = 0xffffffff

	// DMAMUX_SIDR: DMAMUX size identification register
	// Position of SID field.
	DMAMUX1_DMAMUX_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	DMAMUX1_DMAMUX_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for DSIHOST1: DSIHOST1
const (
	// DSI_VR: DSI Host version register
	// Position of VERSION field.
	DSIHOST1_DSI_VR_VERSION_Pos = 0x0
	// Bit mask of VERSION field.
	DSIHOST1_DSI_VR_VERSION_Msk = 0xffffffff

	// DSI_CR: DSI Host control register
	// Position of EN field.
	DSIHOST1_DSI_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DSIHOST1_DSI_CR_EN_Msk = 0x1
	// Bit EN.
	DSIHOST1_DSI_CR_EN = 0x1

	// DSI_CCR: DSI Host clock control register
	// Position of TXECKDIV field.
	DSIHOST1_DSI_CCR_TXECKDIV_Pos = 0x0
	// Bit mask of TXECKDIV field.
	DSIHOST1_DSI_CCR_TXECKDIV_Msk = 0xff
	// Position of TOCKDIV field.
	DSIHOST1_DSI_CCR_TOCKDIV_Pos = 0x8
	// Bit mask of TOCKDIV field.
	DSIHOST1_DSI_CCR_TOCKDIV_Msk = 0xff00

	// DSI_LVCIDR: DSI Host LTDC VCID register
	// Position of VCID field.
	DSIHOST1_DSI_LVCIDR_VCID_Pos = 0x0
	// Bit mask of VCID field.
	DSIHOST1_DSI_LVCIDR_VCID_Msk = 0x3

	// DSI_LCOLCR: DSI Host LTDC color coding register
	// Position of COLC field.
	DSIHOST1_DSI_LCOLCR_COLC_Pos = 0x0
	// Bit mask of COLC field.
	DSIHOST1_DSI_LCOLCR_COLC_Msk = 0xf
	// Position of LPE field.
	DSIHOST1_DSI_LCOLCR_LPE_Pos = 0x8
	// Bit mask of LPE field.
	DSIHOST1_DSI_LCOLCR_LPE_Msk = 0x100
	// Bit LPE.
	DSIHOST1_DSI_LCOLCR_LPE = 0x100

	// DSI_LPCR: DSI Host LTDC polarity configuration register
	// Position of DEP field.
	DSIHOST1_DSI_LPCR_DEP_Pos = 0x0
	// Bit mask of DEP field.
	DSIHOST1_DSI_LPCR_DEP_Msk = 0x1
	// Bit DEP.
	DSIHOST1_DSI_LPCR_DEP = 0x1
	// Position of VSP field.
	DSIHOST1_DSI_LPCR_VSP_Pos = 0x1
	// Bit mask of VSP field.
	DSIHOST1_DSI_LPCR_VSP_Msk = 0x2
	// Bit VSP.
	DSIHOST1_DSI_LPCR_VSP = 0x2
	// Position of HSP field.
	DSIHOST1_DSI_LPCR_HSP_Pos = 0x2
	// Bit mask of HSP field.
	DSIHOST1_DSI_LPCR_HSP_Msk = 0x4
	// Bit HSP.
	DSIHOST1_DSI_LPCR_HSP = 0x4

	// DSI_LPMCR: DSI Host low-power mode configuration register
	// Position of VLPSIZE field.
	DSIHOST1_DSI_LPMCR_VLPSIZE_Pos = 0x0
	// Bit mask of VLPSIZE field.
	DSIHOST1_DSI_LPMCR_VLPSIZE_Msk = 0xff
	// Position of LPSIZE field.
	DSIHOST1_DSI_LPMCR_LPSIZE_Pos = 0x10
	// Bit mask of LPSIZE field.
	DSIHOST1_DSI_LPMCR_LPSIZE_Msk = 0xff0000

	// DSI_PCR: DSI Host protocol configuration register
	// Position of ETTXE field.
	DSIHOST1_DSI_PCR_ETTXE_Pos = 0x0
	// Bit mask of ETTXE field.
	DSIHOST1_DSI_PCR_ETTXE_Msk = 0x1
	// Bit ETTXE.
	DSIHOST1_DSI_PCR_ETTXE = 0x1
	// Position of ETRXE field.
	DSIHOST1_DSI_PCR_ETRXE_Pos = 0x1
	// Bit mask of ETRXE field.
	DSIHOST1_DSI_PCR_ETRXE_Msk = 0x2
	// Bit ETRXE.
	DSIHOST1_DSI_PCR_ETRXE = 0x2
	// Position of BTAE field.
	DSIHOST1_DSI_PCR_BTAE_Pos = 0x2
	// Bit mask of BTAE field.
	DSIHOST1_DSI_PCR_BTAE_Msk = 0x4
	// Bit BTAE.
	DSIHOST1_DSI_PCR_BTAE = 0x4
	// Position of ECCRXE field.
	DSIHOST1_DSI_PCR_ECCRXE_Pos = 0x3
	// Bit mask of ECCRXE field.
	DSIHOST1_DSI_PCR_ECCRXE_Msk = 0x8
	// Bit ECCRXE.
	DSIHOST1_DSI_PCR_ECCRXE = 0x8
	// Position of CRCRXE field.
	DSIHOST1_DSI_PCR_CRCRXE_Pos = 0x4
	// Bit mask of CRCRXE field.
	DSIHOST1_DSI_PCR_CRCRXE_Msk = 0x10
	// Bit CRCRXE.
	DSIHOST1_DSI_PCR_CRCRXE = 0x10

	// DSI_GVCIDR: DSI Host generic VCID register
	// Position of VCID field.
	DSIHOST1_DSI_GVCIDR_VCID_Pos = 0x0
	// Bit mask of VCID field.
	DSIHOST1_DSI_GVCIDR_VCID_Msk = 0x3

	// DSI_MCR: DSI Host mode configuration register
	// Position of CMDM field.
	DSIHOST1_DSI_MCR_CMDM_Pos = 0x0
	// Bit mask of CMDM field.
	DSIHOST1_DSI_MCR_CMDM_Msk = 0x1
	// Bit CMDM.
	DSIHOST1_DSI_MCR_CMDM = 0x1

	// DSI_VMCR: DSI Host video mode configuration register
	// Position of VMT field.
	DSIHOST1_DSI_VMCR_VMT_Pos = 0x0
	// Bit mask of VMT field.
	DSIHOST1_DSI_VMCR_VMT_Msk = 0x3
	// Position of LPVSAE field.
	DSIHOST1_DSI_VMCR_LPVSAE_Pos = 0x8
	// Bit mask of LPVSAE field.
	DSIHOST1_DSI_VMCR_LPVSAE_Msk = 0x100
	// Bit LPVSAE.
	DSIHOST1_DSI_VMCR_LPVSAE = 0x100
	// Position of LPVBPE field.
	DSIHOST1_DSI_VMCR_LPVBPE_Pos = 0x9
	// Bit mask of LPVBPE field.
	DSIHOST1_DSI_VMCR_LPVBPE_Msk = 0x200
	// Bit LPVBPE.
	DSIHOST1_DSI_VMCR_LPVBPE = 0x200
	// Position of LPVFPE field.
	DSIHOST1_DSI_VMCR_LPVFPE_Pos = 0xa
	// Bit mask of LPVFPE field.
	DSIHOST1_DSI_VMCR_LPVFPE_Msk = 0x400
	// Bit LPVFPE.
	DSIHOST1_DSI_VMCR_LPVFPE = 0x400
	// Position of LPVAE field.
	DSIHOST1_DSI_VMCR_LPVAE_Pos = 0xb
	// Bit mask of LPVAE field.
	DSIHOST1_DSI_VMCR_LPVAE_Msk = 0x800
	// Bit LPVAE.
	DSIHOST1_DSI_VMCR_LPVAE = 0x800
	// Position of LPHBPE field.
	DSIHOST1_DSI_VMCR_LPHBPE_Pos = 0xc
	// Bit mask of LPHBPE field.
	DSIHOST1_DSI_VMCR_LPHBPE_Msk = 0x1000
	// Bit LPHBPE.
	DSIHOST1_DSI_VMCR_LPHBPE = 0x1000
	// Position of LPHFPE field.
	DSIHOST1_DSI_VMCR_LPHFPE_Pos = 0xd
	// Bit mask of LPHFPE field.
	DSIHOST1_DSI_VMCR_LPHFPE_Msk = 0x2000
	// Bit LPHFPE.
	DSIHOST1_DSI_VMCR_LPHFPE = 0x2000
	// Position of FBTAAE field.
	DSIHOST1_DSI_VMCR_FBTAAE_Pos = 0xe
	// Bit mask of FBTAAE field.
	DSIHOST1_DSI_VMCR_FBTAAE_Msk = 0x4000
	// Bit FBTAAE.
	DSIHOST1_DSI_VMCR_FBTAAE = 0x4000
	// Position of LPCE field.
	DSIHOST1_DSI_VMCR_LPCE_Pos = 0xf
	// Bit mask of LPCE field.
	DSIHOST1_DSI_VMCR_LPCE_Msk = 0x8000
	// Bit LPCE.
	DSIHOST1_DSI_VMCR_LPCE = 0x8000
	// Position of PGE field.
	DSIHOST1_DSI_VMCR_PGE_Pos = 0x10
	// Bit mask of PGE field.
	DSIHOST1_DSI_VMCR_PGE_Msk = 0x10000
	// Bit PGE.
	DSIHOST1_DSI_VMCR_PGE = 0x10000
	// Position of PGM field.
	DSIHOST1_DSI_VMCR_PGM_Pos = 0x14
	// Bit mask of PGM field.
	DSIHOST1_DSI_VMCR_PGM_Msk = 0x100000
	// Bit PGM.
	DSIHOST1_DSI_VMCR_PGM = 0x100000
	// Position of PGO field.
	DSIHOST1_DSI_VMCR_PGO_Pos = 0x18
	// Bit mask of PGO field.
	DSIHOST1_DSI_VMCR_PGO_Msk = 0x1000000
	// Bit PGO.
	DSIHOST1_DSI_VMCR_PGO = 0x1000000

	// DSI_VPCR: DSI Host video packet configuration register
	// Position of VPSIZE field.
	DSIHOST1_DSI_VPCR_VPSIZE_Pos = 0x0
	// Bit mask of VPSIZE field.
	DSIHOST1_DSI_VPCR_VPSIZE_Msk = 0x3fff

	// DSI_VCCR: DSI Host video chunks configuration register
	// Position of NUMC field.
	DSIHOST1_DSI_VCCR_NUMC_Pos = 0x0
	// Bit mask of NUMC field.
	DSIHOST1_DSI_VCCR_NUMC_Msk = 0x1fff

	// DSI_VNPCR: DSI Host video null packet configuration register
	// Position of NPSIZE field.
	DSIHOST1_DSI_VNPCR_NPSIZE_Pos = 0x0
	// Bit mask of NPSIZE field.
	DSIHOST1_DSI_VNPCR_NPSIZE_Msk = 0x1fff

	// DSI_VHSACR: DSI Host video HSA configuration register
	// Position of HSA field.
	DSIHOST1_DSI_VHSACR_HSA_Pos = 0x0
	// Bit mask of HSA field.
	DSIHOST1_DSI_VHSACR_HSA_Msk = 0xfff

	// DSI_VHBPCR: DSI Host video HBP configuration register
	// Position of HBP field.
	DSIHOST1_DSI_VHBPCR_HBP_Pos = 0x0
	// Bit mask of HBP field.
	DSIHOST1_DSI_VHBPCR_HBP_Msk = 0xfff

	// DSI_VLCR: DSI Host video line configuration register
	// Position of HLINE field.
	DSIHOST1_DSI_VLCR_HLINE_Pos = 0x0
	// Bit mask of HLINE field.
	DSIHOST1_DSI_VLCR_HLINE_Msk = 0x7fff

	// DSI_VVSACR: DSI Host video VSA configuration register
	// Position of VSA field.
	DSIHOST1_DSI_VVSACR_VSA_Pos = 0x0
	// Bit mask of VSA field.
	DSIHOST1_DSI_VVSACR_VSA_Msk = 0x3ff

	// DSI_VVBPCR: DSI Host video VBP configuration register
	// Position of VBP field.
	DSIHOST1_DSI_VVBPCR_VBP_Pos = 0x0
	// Bit mask of VBP field.
	DSIHOST1_DSI_VVBPCR_VBP_Msk = 0x3ff

	// DSI_VVFPCR: DSI Host video VFP configuration register
	// Position of VFP field.
	DSIHOST1_DSI_VVFPCR_VFP_Pos = 0x0
	// Bit mask of VFP field.
	DSIHOST1_DSI_VVFPCR_VFP_Msk = 0x3ff

	// DSI_VVACR: DSI Host video VA configuration register
	// Position of VA field.
	DSIHOST1_DSI_VVACR_VA_Pos = 0x0
	// Bit mask of VA field.
	DSIHOST1_DSI_VVACR_VA_Msk = 0x3fff

	// DSI_LCCR: DSI Host LTDC command configuration register
	// Position of CMDSIZE field.
	DSIHOST1_DSI_LCCR_CMDSIZE_Pos = 0x0
	// Bit mask of CMDSIZE field.
	DSIHOST1_DSI_LCCR_CMDSIZE_Msk = 0xffff

	// DSI_CMCR: DSI Host command mode configuration register
	// Position of TEARE field.
	DSIHOST1_DSI_CMCR_TEARE_Pos = 0x0
	// Bit mask of TEARE field.
	DSIHOST1_DSI_CMCR_TEARE_Msk = 0x1
	// Bit TEARE.
	DSIHOST1_DSI_CMCR_TEARE = 0x1
	// Position of ARE field.
	DSIHOST1_DSI_CMCR_ARE_Pos = 0x1
	// Bit mask of ARE field.
	DSIHOST1_DSI_CMCR_ARE_Msk = 0x2
	// Bit ARE.
	DSIHOST1_DSI_CMCR_ARE = 0x2
	// Position of GSW0TX field.
	DSIHOST1_DSI_CMCR_GSW0TX_Pos = 0x8
	// Bit mask of GSW0TX field.
	DSIHOST1_DSI_CMCR_GSW0TX_Msk = 0x100
	// Bit GSW0TX.
	DSIHOST1_DSI_CMCR_GSW0TX = 0x100
	// Position of GSW1TX field.
	DSIHOST1_DSI_CMCR_GSW1TX_Pos = 0x9
	// Bit mask of GSW1TX field.
	DSIHOST1_DSI_CMCR_GSW1TX_Msk = 0x200
	// Bit GSW1TX.
	DSIHOST1_DSI_CMCR_GSW1TX = 0x200
	// Position of GSW2TX field.
	DSIHOST1_DSI_CMCR_GSW2TX_Pos = 0xa
	// Bit mask of GSW2TX field.
	DSIHOST1_DSI_CMCR_GSW2TX_Msk = 0x400
	// Bit GSW2TX.
	DSIHOST1_DSI_CMCR_GSW2TX = 0x400
	// Position of GSR0TX field.
	DSIHOST1_DSI_CMCR_GSR0TX_Pos = 0xb
	// Bit mask of GSR0TX field.
	DSIHOST1_DSI_CMCR_GSR0TX_Msk = 0x800
	// Bit GSR0TX.
	DSIHOST1_DSI_CMCR_GSR0TX = 0x800
	// Position of GSR1TX field.
	DSIHOST1_DSI_CMCR_GSR1TX_Pos = 0xc
	// Bit mask of GSR1TX field.
	DSIHOST1_DSI_CMCR_GSR1TX_Msk = 0x1000
	// Bit GSR1TX.
	DSIHOST1_DSI_CMCR_GSR1TX = 0x1000
	// Position of GSR2TX field.
	DSIHOST1_DSI_CMCR_GSR2TX_Pos = 0xd
	// Bit mask of GSR2TX field.
	DSIHOST1_DSI_CMCR_GSR2TX_Msk = 0x2000
	// Bit GSR2TX.
	DSIHOST1_DSI_CMCR_GSR2TX = 0x2000
	// Position of GLWTX field.
	DSIHOST1_DSI_CMCR_GLWTX_Pos = 0xe
	// Bit mask of GLWTX field.
	DSIHOST1_DSI_CMCR_GLWTX_Msk = 0x4000
	// Bit GLWTX.
	DSIHOST1_DSI_CMCR_GLWTX = 0x4000
	// Position of DSW0TX field.
	DSIHOST1_DSI_CMCR_DSW0TX_Pos = 0x10
	// Bit mask of DSW0TX field.
	DSIHOST1_DSI_CMCR_DSW0TX_Msk = 0x10000
	// Bit DSW0TX.
	DSIHOST1_DSI_CMCR_DSW0TX = 0x10000
	// Position of DSW1TX field.
	DSIHOST1_DSI_CMCR_DSW1TX_Pos = 0x11
	// Bit mask of DSW1TX field.
	DSIHOST1_DSI_CMCR_DSW1TX_Msk = 0x20000
	// Bit DSW1TX.
	DSIHOST1_DSI_CMCR_DSW1TX = 0x20000
	// Position of DSR0TX field.
	DSIHOST1_DSI_CMCR_DSR0TX_Pos = 0x12
	// Bit mask of DSR0TX field.
	DSIHOST1_DSI_CMCR_DSR0TX_Msk = 0x40000
	// Bit DSR0TX.
	DSIHOST1_DSI_CMCR_DSR0TX = 0x40000
	// Position of DLWTX field.
	DSIHOST1_DSI_CMCR_DLWTX_Pos = 0x13
	// Bit mask of DLWTX field.
	DSIHOST1_DSI_CMCR_DLWTX_Msk = 0x80000
	// Bit DLWTX.
	DSIHOST1_DSI_CMCR_DLWTX = 0x80000
	// Position of MRDPS field.
	DSIHOST1_DSI_CMCR_MRDPS_Pos = 0x18
	// Bit mask of MRDPS field.
	DSIHOST1_DSI_CMCR_MRDPS_Msk = 0x1000000
	// Bit MRDPS.
	DSIHOST1_DSI_CMCR_MRDPS = 0x1000000

	// DSI_GHCR: DSI Host generic header configuration register
	// Position of DT field.
	DSIHOST1_DSI_GHCR_DT_Pos = 0x0
	// Bit mask of DT field.
	DSIHOST1_DSI_GHCR_DT_Msk = 0x3f
	// Position of VCID field.
	DSIHOST1_DSI_GHCR_VCID_Pos = 0x6
	// Bit mask of VCID field.
	DSIHOST1_DSI_GHCR_VCID_Msk = 0xc0
	// Position of WCLSB field.
	DSIHOST1_DSI_GHCR_WCLSB_Pos = 0x8
	// Bit mask of WCLSB field.
	DSIHOST1_DSI_GHCR_WCLSB_Msk = 0xff00
	// Position of WCMSB field.
	DSIHOST1_DSI_GHCR_WCMSB_Pos = 0x10
	// Bit mask of WCMSB field.
	DSIHOST1_DSI_GHCR_WCMSB_Msk = 0xff0000

	// DSI_GPDR: DSI Host generic payload data register
	// Position of DATA1 field.
	DSIHOST1_DSI_GPDR_DATA1_Pos = 0x0
	// Bit mask of DATA1 field.
	DSIHOST1_DSI_GPDR_DATA1_Msk = 0xff
	// Position of DATA2 field.
	DSIHOST1_DSI_GPDR_DATA2_Pos = 0x8
	// Bit mask of DATA2 field.
	DSIHOST1_DSI_GPDR_DATA2_Msk = 0xff00
	// Position of DATA3 field.
	DSIHOST1_DSI_GPDR_DATA3_Pos = 0x10
	// Bit mask of DATA3 field.
	DSIHOST1_DSI_GPDR_DATA3_Msk = 0xff0000
	// Position of DATA4 field.
	DSIHOST1_DSI_GPDR_DATA4_Pos = 0x18
	// Bit mask of DATA4 field.
	DSIHOST1_DSI_GPDR_DATA4_Msk = 0xff000000

	// DSI_GPSR: DSI Host generic packet status register
	// Position of CMDFE field.
	DSIHOST1_DSI_GPSR_CMDFE_Pos = 0x0
	// Bit mask of CMDFE field.
	DSIHOST1_DSI_GPSR_CMDFE_Msk = 0x1
	// Bit CMDFE.
	DSIHOST1_DSI_GPSR_CMDFE = 0x1
	// Position of CMDFF field.
	DSIHOST1_DSI_GPSR_CMDFF_Pos = 0x1
	// Bit mask of CMDFF field.
	DSIHOST1_DSI_GPSR_CMDFF_Msk = 0x2
	// Bit CMDFF.
	DSIHOST1_DSI_GPSR_CMDFF = 0x2
	// Position of PWRFE field.
	DSIHOST1_DSI_GPSR_PWRFE_Pos = 0x2
	// Bit mask of PWRFE field.
	DSIHOST1_DSI_GPSR_PWRFE_Msk = 0x4
	// Bit PWRFE.
	DSIHOST1_DSI_GPSR_PWRFE = 0x4
	// Position of PWRFF field.
	DSIHOST1_DSI_GPSR_PWRFF_Pos = 0x3
	// Bit mask of PWRFF field.
	DSIHOST1_DSI_GPSR_PWRFF_Msk = 0x8
	// Bit PWRFF.
	DSIHOST1_DSI_GPSR_PWRFF = 0x8
	// Position of PRDFE field.
	DSIHOST1_DSI_GPSR_PRDFE_Pos = 0x4
	// Bit mask of PRDFE field.
	DSIHOST1_DSI_GPSR_PRDFE_Msk = 0x10
	// Bit PRDFE.
	DSIHOST1_DSI_GPSR_PRDFE = 0x10
	// Position of PRDFF field.
	DSIHOST1_DSI_GPSR_PRDFF_Pos = 0x5
	// Bit mask of PRDFF field.
	DSIHOST1_DSI_GPSR_PRDFF_Msk = 0x20
	// Bit PRDFF.
	DSIHOST1_DSI_GPSR_PRDFF = 0x20
	// Position of RCB field.
	DSIHOST1_DSI_GPSR_RCB_Pos = 0x6
	// Bit mask of RCB field.
	DSIHOST1_DSI_GPSR_RCB_Msk = 0x40
	// Bit RCB.
	DSIHOST1_DSI_GPSR_RCB = 0x40

	// DSI_TCCR0: DSI Host timeout counter configuration register 0
	// Position of LPRX_TOCNT field.
	DSIHOST1_DSI_TCCR0_LPRX_TOCNT_Pos = 0x0
	// Bit mask of LPRX_TOCNT field.
	DSIHOST1_DSI_TCCR0_LPRX_TOCNT_Msk = 0xffff
	// Position of HSTX_TOCNT field.
	DSIHOST1_DSI_TCCR0_HSTX_TOCNT_Pos = 0x10
	// Bit mask of HSTX_TOCNT field.
	DSIHOST1_DSI_TCCR0_HSTX_TOCNT_Msk = 0xffff0000

	// DSI_TCCR1: DSI Host timeout counter configuration register 1
	// Position of HSRD_TOCNT field.
	DSIHOST1_DSI_TCCR1_HSRD_TOCNT_Pos = 0x0
	// Bit mask of HSRD_TOCNT field.
	DSIHOST1_DSI_TCCR1_HSRD_TOCNT_Msk = 0xffff

	// DSI_TCCR2: DSI Host timeout counter configuration register 2
	// Position of LPRD_TOCNT field.
	DSIHOST1_DSI_TCCR2_LPRD_TOCNT_Pos = 0x0
	// Bit mask of LPRD_TOCNT field.
	DSIHOST1_DSI_TCCR2_LPRD_TOCNT_Msk = 0xffff

	// DSI_TCCR3: DSI Host timeout counter configuration register 3
	// Position of HSWR_TOCNT field.
	DSIHOST1_DSI_TCCR3_HSWR_TOCNT_Pos = 0x0
	// Bit mask of HSWR_TOCNT field.
	DSIHOST1_DSI_TCCR3_HSWR_TOCNT_Msk = 0xffff
	// Position of PM field.
	DSIHOST1_DSI_TCCR3_PM_Pos = 0x18
	// Bit mask of PM field.
	DSIHOST1_DSI_TCCR3_PM_Msk = 0x1000000
	// Bit PM.
	DSIHOST1_DSI_TCCR3_PM = 0x1000000

	// DSI_TCCR4: DSI Host timeout counter configuration register 4
	// Position of LPWR_TOCNT field.
	DSIHOST1_DSI_TCCR4_LPWR_TOCNT_Pos = 0x0
	// Bit mask of LPWR_TOCNT field.
	DSIHOST1_DSI_TCCR4_LPWR_TOCNT_Msk = 0xffff

	// DSI_TCCR5: DSI Host timeout counter configuration register 5
	// Position of BTA_TOCNT field.
	DSIHOST1_DSI_TCCR5_BTA_TOCNT_Pos = 0x0
	// Bit mask of BTA_TOCNT field.
	DSIHOST1_DSI_TCCR5_BTA_TOCNT_Msk = 0xffff

	// DSI_CLCR: DSI Host clock lane configuration register
	// Position of DPCC field.
	DSIHOST1_DSI_CLCR_DPCC_Pos = 0x0
	// Bit mask of DPCC field.
	DSIHOST1_DSI_CLCR_DPCC_Msk = 0x1
	// Bit DPCC.
	DSIHOST1_DSI_CLCR_DPCC = 0x1
	// Position of ACR field.
	DSIHOST1_DSI_CLCR_ACR_Pos = 0x1
	// Bit mask of ACR field.
	DSIHOST1_DSI_CLCR_ACR_Msk = 0x2
	// Bit ACR.
	DSIHOST1_DSI_CLCR_ACR = 0x2

	// DSI_CLTCR: DSI Host clock lane timer configuration register
	// Position of LP2HS_TIME field.
	DSIHOST1_DSI_CLTCR_LP2HS_TIME_Pos = 0x0
	// Bit mask of LP2HS_TIME field.
	DSIHOST1_DSI_CLTCR_LP2HS_TIME_Msk = 0x3ff
	// Position of HS2LP_TIME field.
	DSIHOST1_DSI_CLTCR_HS2LP_TIME_Pos = 0x10
	// Bit mask of HS2LP_TIME field.
	DSIHOST1_DSI_CLTCR_HS2LP_TIME_Msk = 0x3ff0000

	// DSI_DLTCR: DSI Host data lane timer configuration register
	// Position of LP2HS_TIME field.
	DSIHOST1_DSI_DLTCR_LP2HS_TIME_Pos = 0x0
	// Bit mask of LP2HS_TIME field.
	DSIHOST1_DSI_DLTCR_LP2HS_TIME_Msk = 0x3ff
	// Position of HS2LP_TIME field.
	DSIHOST1_DSI_DLTCR_HS2LP_TIME_Pos = 0x10
	// Bit mask of HS2LP_TIME field.
	DSIHOST1_DSI_DLTCR_HS2LP_TIME_Msk = 0x3ff0000

	// DSI_PCTLR: DSI Host PHY control register
	// Position of DEN field.
	DSIHOST1_DSI_PCTLR_DEN_Pos = 0x1
	// Bit mask of DEN field.
	DSIHOST1_DSI_PCTLR_DEN_Msk = 0x2
	// Bit DEN.
	DSIHOST1_DSI_PCTLR_DEN = 0x2
	// Position of CKE field.
	DSIHOST1_DSI_PCTLR_CKE_Pos = 0x2
	// Bit mask of CKE field.
	DSIHOST1_DSI_PCTLR_CKE_Msk = 0x4
	// Bit CKE.
	DSIHOST1_DSI_PCTLR_CKE = 0x4

	// DSI_PCONFR: DSI Host PHY configuration register
	// Position of NL field.
	DSIHOST1_DSI_PCONFR_NL_Pos = 0x0
	// Bit mask of NL field.
	DSIHOST1_DSI_PCONFR_NL_Msk = 0x3
	// Position of SW_TIME field.
	DSIHOST1_DSI_PCONFR_SW_TIME_Pos = 0x8
	// Bit mask of SW_TIME field.
	DSIHOST1_DSI_PCONFR_SW_TIME_Msk = 0xff00

	// DSI_PUCR: DSI Host PHY ULPS control register
	// Position of URCL field.
	DSIHOST1_DSI_PUCR_URCL_Pos = 0x0
	// Bit mask of URCL field.
	DSIHOST1_DSI_PUCR_URCL_Msk = 0x1
	// Bit URCL.
	DSIHOST1_DSI_PUCR_URCL = 0x1
	// Position of UECL field.
	DSIHOST1_DSI_PUCR_UECL_Pos = 0x1
	// Bit mask of UECL field.
	DSIHOST1_DSI_PUCR_UECL_Msk = 0x2
	// Bit UECL.
	DSIHOST1_DSI_PUCR_UECL = 0x2
	// Position of URDL field.
	DSIHOST1_DSI_PUCR_URDL_Pos = 0x2
	// Bit mask of URDL field.
	DSIHOST1_DSI_PUCR_URDL_Msk = 0x4
	// Bit URDL.
	DSIHOST1_DSI_PUCR_URDL = 0x4
	// Position of UEDL field.
	DSIHOST1_DSI_PUCR_UEDL_Pos = 0x3
	// Bit mask of UEDL field.
	DSIHOST1_DSI_PUCR_UEDL_Msk = 0x8
	// Bit UEDL.
	DSIHOST1_DSI_PUCR_UEDL = 0x8

	// DSI_PTTCR: DSI Host PHY TX triggers configuration register
	// Position of TX_TRIG field.
	DSIHOST1_DSI_PTTCR_TX_TRIG_Pos = 0x0
	// Bit mask of TX_TRIG field.
	DSIHOST1_DSI_PTTCR_TX_TRIG_Msk = 0xf

	// DSI_PSR: DSI Host PHY status register
	// Position of PD field.
	DSIHOST1_DSI_PSR_PD_Pos = 0x1
	// Bit mask of PD field.
	DSIHOST1_DSI_PSR_PD_Msk = 0x2
	// Bit PD.
	DSIHOST1_DSI_PSR_PD = 0x2
	// Position of PSSC field.
	DSIHOST1_DSI_PSR_PSSC_Pos = 0x2
	// Bit mask of PSSC field.
	DSIHOST1_DSI_PSR_PSSC_Msk = 0x4
	// Bit PSSC.
	DSIHOST1_DSI_PSR_PSSC = 0x4
	// Position of UANC field.
	DSIHOST1_DSI_PSR_UANC_Pos = 0x3
	// Bit mask of UANC field.
	DSIHOST1_DSI_PSR_UANC_Msk = 0x8
	// Bit UANC.
	DSIHOST1_DSI_PSR_UANC = 0x8
	// Position of PSS0 field.
	DSIHOST1_DSI_PSR_PSS0_Pos = 0x4
	// Bit mask of PSS0 field.
	DSIHOST1_DSI_PSR_PSS0_Msk = 0x10
	// Bit PSS0.
	DSIHOST1_DSI_PSR_PSS0 = 0x10
	// Position of UAN0 field.
	DSIHOST1_DSI_PSR_UAN0_Pos = 0x5
	// Bit mask of UAN0 field.
	DSIHOST1_DSI_PSR_UAN0_Msk = 0x20
	// Bit UAN0.
	DSIHOST1_DSI_PSR_UAN0 = 0x20
	// Position of RUE0 field.
	DSIHOST1_DSI_PSR_RUE0_Pos = 0x6
	// Bit mask of RUE0 field.
	DSIHOST1_DSI_PSR_RUE0_Msk = 0x40
	// Bit RUE0.
	DSIHOST1_DSI_PSR_RUE0 = 0x40
	// Position of PSS1 field.
	DSIHOST1_DSI_PSR_PSS1_Pos = 0x7
	// Bit mask of PSS1 field.
	DSIHOST1_DSI_PSR_PSS1_Msk = 0x80
	// Bit PSS1.
	DSIHOST1_DSI_PSR_PSS1 = 0x80
	// Position of UAN1 field.
	DSIHOST1_DSI_PSR_UAN1_Pos = 0x8
	// Bit mask of UAN1 field.
	DSIHOST1_DSI_PSR_UAN1_Msk = 0x100
	// Bit UAN1.
	DSIHOST1_DSI_PSR_UAN1 = 0x100

	// DSI_ISR0: DSI Host interrupt and status register 0
	// Position of AE0 field.
	DSIHOST1_DSI_ISR0_AE0_Pos = 0x0
	// Bit mask of AE0 field.
	DSIHOST1_DSI_ISR0_AE0_Msk = 0x1
	// Bit AE0.
	DSIHOST1_DSI_ISR0_AE0 = 0x1
	// Position of AE1 field.
	DSIHOST1_DSI_ISR0_AE1_Pos = 0x1
	// Bit mask of AE1 field.
	DSIHOST1_DSI_ISR0_AE1_Msk = 0x2
	// Bit AE1.
	DSIHOST1_DSI_ISR0_AE1 = 0x2
	// Position of AE2 field.
	DSIHOST1_DSI_ISR0_AE2_Pos = 0x2
	// Bit mask of AE2 field.
	DSIHOST1_DSI_ISR0_AE2_Msk = 0x4
	// Bit AE2.
	DSIHOST1_DSI_ISR0_AE2 = 0x4
	// Position of AE3 field.
	DSIHOST1_DSI_ISR0_AE3_Pos = 0x3
	// Bit mask of AE3 field.
	DSIHOST1_DSI_ISR0_AE3_Msk = 0x8
	// Bit AE3.
	DSIHOST1_DSI_ISR0_AE3 = 0x8
	// Position of AE4 field.
	DSIHOST1_DSI_ISR0_AE4_Pos = 0x4
	// Bit mask of AE4 field.
	DSIHOST1_DSI_ISR0_AE4_Msk = 0x10
	// Bit AE4.
	DSIHOST1_DSI_ISR0_AE4 = 0x10
	// Position of AE5 field.
	DSIHOST1_DSI_ISR0_AE5_Pos = 0x5
	// Bit mask of AE5 field.
	DSIHOST1_DSI_ISR0_AE5_Msk = 0x20
	// Bit AE5.
	DSIHOST1_DSI_ISR0_AE5 = 0x20
	// Position of AE6 field.
	DSIHOST1_DSI_ISR0_AE6_Pos = 0x6
	// Bit mask of AE6 field.
	DSIHOST1_DSI_ISR0_AE6_Msk = 0x40
	// Bit AE6.
	DSIHOST1_DSI_ISR0_AE6 = 0x40
	// Position of AE7 field.
	DSIHOST1_DSI_ISR0_AE7_Pos = 0x7
	// Bit mask of AE7 field.
	DSIHOST1_DSI_ISR0_AE7_Msk = 0x80
	// Bit AE7.
	DSIHOST1_DSI_ISR0_AE7 = 0x80
	// Position of AE8 field.
	DSIHOST1_DSI_ISR0_AE8_Pos = 0x8
	// Bit mask of AE8 field.
	DSIHOST1_DSI_ISR0_AE8_Msk = 0x100
	// Bit AE8.
	DSIHOST1_DSI_ISR0_AE8 = 0x100
	// Position of AE9 field.
	DSIHOST1_DSI_ISR0_AE9_Pos = 0x9
	// Bit mask of AE9 field.
	DSIHOST1_DSI_ISR0_AE9_Msk = 0x200
	// Bit AE9.
	DSIHOST1_DSI_ISR0_AE9 = 0x200
	// Position of AE10 field.
	DSIHOST1_DSI_ISR0_AE10_Pos = 0xa
	// Bit mask of AE10 field.
	DSIHOST1_DSI_ISR0_AE10_Msk = 0x400
	// Bit AE10.
	DSIHOST1_DSI_ISR0_AE10 = 0x400
	// Position of AE11 field.
	DSIHOST1_DSI_ISR0_AE11_Pos = 0xb
	// Bit mask of AE11 field.
	DSIHOST1_DSI_ISR0_AE11_Msk = 0x800
	// Bit AE11.
	DSIHOST1_DSI_ISR0_AE11 = 0x800
	// Position of AE12 field.
	DSIHOST1_DSI_ISR0_AE12_Pos = 0xc
	// Bit mask of AE12 field.
	DSIHOST1_DSI_ISR0_AE12_Msk = 0x1000
	// Bit AE12.
	DSIHOST1_DSI_ISR0_AE12 = 0x1000
	// Position of AE13 field.
	DSIHOST1_DSI_ISR0_AE13_Pos = 0xd
	// Bit mask of AE13 field.
	DSIHOST1_DSI_ISR0_AE13_Msk = 0x2000
	// Bit AE13.
	DSIHOST1_DSI_ISR0_AE13 = 0x2000
	// Position of AE14 field.
	DSIHOST1_DSI_ISR0_AE14_Pos = 0xe
	// Bit mask of AE14 field.
	DSIHOST1_DSI_ISR0_AE14_Msk = 0x4000
	// Bit AE14.
	DSIHOST1_DSI_ISR0_AE14 = 0x4000
	// Position of AE15 field.
	DSIHOST1_DSI_ISR0_AE15_Pos = 0xf
	// Bit mask of AE15 field.
	DSIHOST1_DSI_ISR0_AE15_Msk = 0x8000
	// Bit AE15.
	DSIHOST1_DSI_ISR0_AE15 = 0x8000
	// Position of PE0 field.
	DSIHOST1_DSI_ISR0_PE0_Pos = 0x10
	// Bit mask of PE0 field.
	DSIHOST1_DSI_ISR0_PE0_Msk = 0x10000
	// Bit PE0.
	DSIHOST1_DSI_ISR0_PE0 = 0x10000
	// Position of PE1 field.
	DSIHOST1_DSI_ISR0_PE1_Pos = 0x11
	// Bit mask of PE1 field.
	DSIHOST1_DSI_ISR0_PE1_Msk = 0x20000
	// Bit PE1.
	DSIHOST1_DSI_ISR0_PE1 = 0x20000
	// Position of PE2 field.
	DSIHOST1_DSI_ISR0_PE2_Pos = 0x12
	// Bit mask of PE2 field.
	DSIHOST1_DSI_ISR0_PE2_Msk = 0x40000
	// Bit PE2.
	DSIHOST1_DSI_ISR0_PE2 = 0x40000
	// Position of PE3 field.
	DSIHOST1_DSI_ISR0_PE3_Pos = 0x13
	// Bit mask of PE3 field.
	DSIHOST1_DSI_ISR0_PE3_Msk = 0x80000
	// Bit PE3.
	DSIHOST1_DSI_ISR0_PE3 = 0x80000
	// Position of PE4 field.
	DSIHOST1_DSI_ISR0_PE4_Pos = 0x14
	// Bit mask of PE4 field.
	DSIHOST1_DSI_ISR0_PE4_Msk = 0x100000
	// Bit PE4.
	DSIHOST1_DSI_ISR0_PE4 = 0x100000

	// DSI_ISR1: DSI Host interrupt and status register 1
	// Position of TOHSTX field.
	DSIHOST1_DSI_ISR1_TOHSTX_Pos = 0x0
	// Bit mask of TOHSTX field.
	DSIHOST1_DSI_ISR1_TOHSTX_Msk = 0x1
	// Bit TOHSTX.
	DSIHOST1_DSI_ISR1_TOHSTX = 0x1
	// Position of TOLPRX field.
	DSIHOST1_DSI_ISR1_TOLPRX_Pos = 0x1
	// Bit mask of TOLPRX field.
	DSIHOST1_DSI_ISR1_TOLPRX_Msk = 0x2
	// Bit TOLPRX.
	DSIHOST1_DSI_ISR1_TOLPRX = 0x2
	// Position of ECCSE field.
	DSIHOST1_DSI_ISR1_ECCSE_Pos = 0x2
	// Bit mask of ECCSE field.
	DSIHOST1_DSI_ISR1_ECCSE_Msk = 0x4
	// Bit ECCSE.
	DSIHOST1_DSI_ISR1_ECCSE = 0x4
	// Position of ECCME field.
	DSIHOST1_DSI_ISR1_ECCME_Pos = 0x3
	// Bit mask of ECCME field.
	DSIHOST1_DSI_ISR1_ECCME_Msk = 0x8
	// Bit ECCME.
	DSIHOST1_DSI_ISR1_ECCME = 0x8
	// Position of CRCE field.
	DSIHOST1_DSI_ISR1_CRCE_Pos = 0x4
	// Bit mask of CRCE field.
	DSIHOST1_DSI_ISR1_CRCE_Msk = 0x10
	// Bit CRCE.
	DSIHOST1_DSI_ISR1_CRCE = 0x10
	// Position of PSE field.
	DSIHOST1_DSI_ISR1_PSE_Pos = 0x5
	// Bit mask of PSE field.
	DSIHOST1_DSI_ISR1_PSE_Msk = 0x20
	// Bit PSE.
	DSIHOST1_DSI_ISR1_PSE = 0x20
	// Position of EOTPE field.
	DSIHOST1_DSI_ISR1_EOTPE_Pos = 0x6
	// Bit mask of EOTPE field.
	DSIHOST1_DSI_ISR1_EOTPE_Msk = 0x40
	// Bit EOTPE.
	DSIHOST1_DSI_ISR1_EOTPE = 0x40
	// Position of LPWRE field.
	DSIHOST1_DSI_ISR1_LPWRE_Pos = 0x7
	// Bit mask of LPWRE field.
	DSIHOST1_DSI_ISR1_LPWRE_Msk = 0x80
	// Bit LPWRE.
	DSIHOST1_DSI_ISR1_LPWRE = 0x80
	// Position of GCWRE field.
	DSIHOST1_DSI_ISR1_GCWRE_Pos = 0x8
	// Bit mask of GCWRE field.
	DSIHOST1_DSI_ISR1_GCWRE_Msk = 0x100
	// Bit GCWRE.
	DSIHOST1_DSI_ISR1_GCWRE = 0x100
	// Position of GPWRE field.
	DSIHOST1_DSI_ISR1_GPWRE_Pos = 0x9
	// Bit mask of GPWRE field.
	DSIHOST1_DSI_ISR1_GPWRE_Msk = 0x200
	// Bit GPWRE.
	DSIHOST1_DSI_ISR1_GPWRE = 0x200
	// Position of GPTXE field.
	DSIHOST1_DSI_ISR1_GPTXE_Pos = 0xa
	// Bit mask of GPTXE field.
	DSIHOST1_DSI_ISR1_GPTXE_Msk = 0x400
	// Bit GPTXE.
	DSIHOST1_DSI_ISR1_GPTXE = 0x400
	// Position of GPRDE field.
	DSIHOST1_DSI_ISR1_GPRDE_Pos = 0xb
	// Bit mask of GPRDE field.
	DSIHOST1_DSI_ISR1_GPRDE_Msk = 0x800
	// Bit GPRDE.
	DSIHOST1_DSI_ISR1_GPRDE = 0x800
	// Position of GPRXE field.
	DSIHOST1_DSI_ISR1_GPRXE_Pos = 0xc
	// Bit mask of GPRXE field.
	DSIHOST1_DSI_ISR1_GPRXE_Msk = 0x1000
	// Bit GPRXE.
	DSIHOST1_DSI_ISR1_GPRXE = 0x1000

	// DSI_IER0: DSI Host interrupt enable register 0
	// Position of AE0IE field.
	DSIHOST1_DSI_IER0_AE0IE_Pos = 0x0
	// Bit mask of AE0IE field.
	DSIHOST1_DSI_IER0_AE0IE_Msk = 0x1
	// Bit AE0IE.
	DSIHOST1_DSI_IER0_AE0IE = 0x1
	// Position of AE1IE field.
	DSIHOST1_DSI_IER0_AE1IE_Pos = 0x1
	// Bit mask of AE1IE field.
	DSIHOST1_DSI_IER0_AE1IE_Msk = 0x2
	// Bit AE1IE.
	DSIHOST1_DSI_IER0_AE1IE = 0x2
	// Position of AE2IE field.
	DSIHOST1_DSI_IER0_AE2IE_Pos = 0x2
	// Bit mask of AE2IE field.
	DSIHOST1_DSI_IER0_AE2IE_Msk = 0x4
	// Bit AE2IE.
	DSIHOST1_DSI_IER0_AE2IE = 0x4
	// Position of AE3IE field.
	DSIHOST1_DSI_IER0_AE3IE_Pos = 0x3
	// Bit mask of AE3IE field.
	DSIHOST1_DSI_IER0_AE3IE_Msk = 0x8
	// Bit AE3IE.
	DSIHOST1_DSI_IER0_AE3IE = 0x8
	// Position of AE4IE field.
	DSIHOST1_DSI_IER0_AE4IE_Pos = 0x4
	// Bit mask of AE4IE field.
	DSIHOST1_DSI_IER0_AE4IE_Msk = 0x10
	// Bit AE4IE.
	DSIHOST1_DSI_IER0_AE4IE = 0x10
	// Position of AE5IE field.
	DSIHOST1_DSI_IER0_AE5IE_Pos = 0x5
	// Bit mask of AE5IE field.
	DSIHOST1_DSI_IER0_AE5IE_Msk = 0x20
	// Bit AE5IE.
	DSIHOST1_DSI_IER0_AE5IE = 0x20
	// Position of AE6IE field.
	DSIHOST1_DSI_IER0_AE6IE_Pos = 0x6
	// Bit mask of AE6IE field.
	DSIHOST1_DSI_IER0_AE6IE_Msk = 0x40
	// Bit AE6IE.
	DSIHOST1_DSI_IER0_AE6IE = 0x40
	// Position of AE7IE field.
	DSIHOST1_DSI_IER0_AE7IE_Pos = 0x7
	// Bit mask of AE7IE field.
	DSIHOST1_DSI_IER0_AE7IE_Msk = 0x80
	// Bit AE7IE.
	DSIHOST1_DSI_IER0_AE7IE = 0x80
	// Position of AE8IE field.
	DSIHOST1_DSI_IER0_AE8IE_Pos = 0x8
	// Bit mask of AE8IE field.
	DSIHOST1_DSI_IER0_AE8IE_Msk = 0x100
	// Bit AE8IE.
	DSIHOST1_DSI_IER0_AE8IE = 0x100
	// Position of AE9IE field.
	DSIHOST1_DSI_IER0_AE9IE_Pos = 0x9
	// Bit mask of AE9IE field.
	DSIHOST1_DSI_IER0_AE9IE_Msk = 0x200
	// Bit AE9IE.
	DSIHOST1_DSI_IER0_AE9IE = 0x200
	// Position of AE10IE field.
	DSIHOST1_DSI_IER0_AE10IE_Pos = 0xa
	// Bit mask of AE10IE field.
	DSIHOST1_DSI_IER0_AE10IE_Msk = 0x400
	// Bit AE10IE.
	DSIHOST1_DSI_IER0_AE10IE = 0x400
	// Position of AE11IE field.
	DSIHOST1_DSI_IER0_AE11IE_Pos = 0xb
	// Bit mask of AE11IE field.
	DSIHOST1_DSI_IER0_AE11IE_Msk = 0x800
	// Bit AE11IE.
	DSIHOST1_DSI_IER0_AE11IE = 0x800
	// Position of AE12IE field.
	DSIHOST1_DSI_IER0_AE12IE_Pos = 0xc
	// Bit mask of AE12IE field.
	DSIHOST1_DSI_IER0_AE12IE_Msk = 0x1000
	// Bit AE12IE.
	DSIHOST1_DSI_IER0_AE12IE = 0x1000
	// Position of AE13IE field.
	DSIHOST1_DSI_IER0_AE13IE_Pos = 0xd
	// Bit mask of AE13IE field.
	DSIHOST1_DSI_IER0_AE13IE_Msk = 0x2000
	// Bit AE13IE.
	DSIHOST1_DSI_IER0_AE13IE = 0x2000
	// Position of AE14IE field.
	DSIHOST1_DSI_IER0_AE14IE_Pos = 0xe
	// Bit mask of AE14IE field.
	DSIHOST1_DSI_IER0_AE14IE_Msk = 0x4000
	// Bit AE14IE.
	DSIHOST1_DSI_IER0_AE14IE = 0x4000
	// Position of AE15IE field.
	DSIHOST1_DSI_IER0_AE15IE_Pos = 0xf
	// Bit mask of AE15IE field.
	DSIHOST1_DSI_IER0_AE15IE_Msk = 0x8000
	// Bit AE15IE.
	DSIHOST1_DSI_IER0_AE15IE = 0x8000
	// Position of PE0IE field.
	DSIHOST1_DSI_IER0_PE0IE_Pos = 0x10
	// Bit mask of PE0IE field.
	DSIHOST1_DSI_IER0_PE0IE_Msk = 0x10000
	// Bit PE0IE.
	DSIHOST1_DSI_IER0_PE0IE = 0x10000
	// Position of PE1IE field.
	DSIHOST1_DSI_IER0_PE1IE_Pos = 0x11
	// Bit mask of PE1IE field.
	DSIHOST1_DSI_IER0_PE1IE_Msk = 0x20000
	// Bit PE1IE.
	DSIHOST1_DSI_IER0_PE1IE = 0x20000
	// Position of PE2IE field.
	DSIHOST1_DSI_IER0_PE2IE_Pos = 0x12
	// Bit mask of PE2IE field.
	DSIHOST1_DSI_IER0_PE2IE_Msk = 0x40000
	// Bit PE2IE.
	DSIHOST1_DSI_IER0_PE2IE = 0x40000
	// Position of PE3IE field.
	DSIHOST1_DSI_IER0_PE3IE_Pos = 0x13
	// Bit mask of PE3IE field.
	DSIHOST1_DSI_IER0_PE3IE_Msk = 0x80000
	// Bit PE3IE.
	DSIHOST1_DSI_IER0_PE3IE = 0x80000
	// Position of PE4IE field.
	DSIHOST1_DSI_IER0_PE4IE_Pos = 0x14
	// Bit mask of PE4IE field.
	DSIHOST1_DSI_IER0_PE4IE_Msk = 0x100000
	// Bit PE4IE.
	DSIHOST1_DSI_IER0_PE4IE = 0x100000

	// DSI_IER1: DSI Host interrupt enable register 1
	// Position of TOHSTXIE field.
	DSIHOST1_DSI_IER1_TOHSTXIE_Pos = 0x0
	// Bit mask of TOHSTXIE field.
	DSIHOST1_DSI_IER1_TOHSTXIE_Msk = 0x1
	// Bit TOHSTXIE.
	DSIHOST1_DSI_IER1_TOHSTXIE = 0x1
	// Position of TOLPRXIE field.
	DSIHOST1_DSI_IER1_TOLPRXIE_Pos = 0x1
	// Bit mask of TOLPRXIE field.
	DSIHOST1_DSI_IER1_TOLPRXIE_Msk = 0x2
	// Bit TOLPRXIE.
	DSIHOST1_DSI_IER1_TOLPRXIE = 0x2
	// Position of ECCSEIE field.
	DSIHOST1_DSI_IER1_ECCSEIE_Pos = 0x2
	// Bit mask of ECCSEIE field.
	DSIHOST1_DSI_IER1_ECCSEIE_Msk = 0x4
	// Bit ECCSEIE.
	DSIHOST1_DSI_IER1_ECCSEIE = 0x4
	// Position of ECCMEIE field.
	DSIHOST1_DSI_IER1_ECCMEIE_Pos = 0x3
	// Bit mask of ECCMEIE field.
	DSIHOST1_DSI_IER1_ECCMEIE_Msk = 0x8
	// Bit ECCMEIE.
	DSIHOST1_DSI_IER1_ECCMEIE = 0x8
	// Position of CRCEIE field.
	DSIHOST1_DSI_IER1_CRCEIE_Pos = 0x4
	// Bit mask of CRCEIE field.
	DSIHOST1_DSI_IER1_CRCEIE_Msk = 0x10
	// Bit CRCEIE.
	DSIHOST1_DSI_IER1_CRCEIE = 0x10
	// Position of PSEIE field.
	DSIHOST1_DSI_IER1_PSEIE_Pos = 0x5
	// Bit mask of PSEIE field.
	DSIHOST1_DSI_IER1_PSEIE_Msk = 0x20
	// Bit PSEIE.
	DSIHOST1_DSI_IER1_PSEIE = 0x20
	// Position of EOTPEIE field.
	DSIHOST1_DSI_IER1_EOTPEIE_Pos = 0x6
	// Bit mask of EOTPEIE field.
	DSIHOST1_DSI_IER1_EOTPEIE_Msk = 0x40
	// Bit EOTPEIE.
	DSIHOST1_DSI_IER1_EOTPEIE = 0x40
	// Position of LPWREIE field.
	DSIHOST1_DSI_IER1_LPWREIE_Pos = 0x7
	// Bit mask of LPWREIE field.
	DSIHOST1_DSI_IER1_LPWREIE_Msk = 0x80
	// Bit LPWREIE.
	DSIHOST1_DSI_IER1_LPWREIE = 0x80
	// Position of GCWREIE field.
	DSIHOST1_DSI_IER1_GCWREIE_Pos = 0x8
	// Bit mask of GCWREIE field.
	DSIHOST1_DSI_IER1_GCWREIE_Msk = 0x100
	// Bit GCWREIE.
	DSIHOST1_DSI_IER1_GCWREIE = 0x100
	// Position of GPWREIE field.
	DSIHOST1_DSI_IER1_GPWREIE_Pos = 0x9
	// Bit mask of GPWREIE field.
	DSIHOST1_DSI_IER1_GPWREIE_Msk = 0x200
	// Bit GPWREIE.
	DSIHOST1_DSI_IER1_GPWREIE = 0x200
	// Position of GPTXEIE field.
	DSIHOST1_DSI_IER1_GPTXEIE_Pos = 0xa
	// Bit mask of GPTXEIE field.
	DSIHOST1_DSI_IER1_GPTXEIE_Msk = 0x400
	// Bit GPTXEIE.
	DSIHOST1_DSI_IER1_GPTXEIE = 0x400
	// Position of GPRDEIE field.
	DSIHOST1_DSI_IER1_GPRDEIE_Pos = 0xb
	// Bit mask of GPRDEIE field.
	DSIHOST1_DSI_IER1_GPRDEIE_Msk = 0x800
	// Bit GPRDEIE.
	DSIHOST1_DSI_IER1_GPRDEIE = 0x800
	// Position of GPRXEIE field.
	DSIHOST1_DSI_IER1_GPRXEIE_Pos = 0xc
	// Bit mask of GPRXEIE field.
	DSIHOST1_DSI_IER1_GPRXEIE_Msk = 0x1000
	// Bit GPRXEIE.
	DSIHOST1_DSI_IER1_GPRXEIE = 0x1000

	// DSI_FIR0: DSI Host force interrupt register 0
	// Position of FAE0 field.
	DSIHOST1_DSI_FIR0_FAE0_Pos = 0x0
	// Bit mask of FAE0 field.
	DSIHOST1_DSI_FIR0_FAE0_Msk = 0x1
	// Bit FAE0.
	DSIHOST1_DSI_FIR0_FAE0 = 0x1
	// Position of FAE1 field.
	DSIHOST1_DSI_FIR0_FAE1_Pos = 0x1
	// Bit mask of FAE1 field.
	DSIHOST1_DSI_FIR0_FAE1_Msk = 0x2
	// Bit FAE1.
	DSIHOST1_DSI_FIR0_FAE1 = 0x2
	// Position of FAE2 field.
	DSIHOST1_DSI_FIR0_FAE2_Pos = 0x2
	// Bit mask of FAE2 field.
	DSIHOST1_DSI_FIR0_FAE2_Msk = 0x4
	// Bit FAE2.
	DSIHOST1_DSI_FIR0_FAE2 = 0x4
	// Position of FAE3 field.
	DSIHOST1_DSI_FIR0_FAE3_Pos = 0x3
	// Bit mask of FAE3 field.
	DSIHOST1_DSI_FIR0_FAE3_Msk = 0x8
	// Bit FAE3.
	DSIHOST1_DSI_FIR0_FAE3 = 0x8
	// Position of FAE4 field.
	DSIHOST1_DSI_FIR0_FAE4_Pos = 0x4
	// Bit mask of FAE4 field.
	DSIHOST1_DSI_FIR0_FAE4_Msk = 0x10
	// Bit FAE4.
	DSIHOST1_DSI_FIR0_FAE4 = 0x10
	// Position of FAE5 field.
	DSIHOST1_DSI_FIR0_FAE5_Pos = 0x5
	// Bit mask of FAE5 field.
	DSIHOST1_DSI_FIR0_FAE5_Msk = 0x20
	// Bit FAE5.
	DSIHOST1_DSI_FIR0_FAE5 = 0x20
	// Position of FAE6 field.
	DSIHOST1_DSI_FIR0_FAE6_Pos = 0x6
	// Bit mask of FAE6 field.
	DSIHOST1_DSI_FIR0_FAE6_Msk = 0x40
	// Bit FAE6.
	DSIHOST1_DSI_FIR0_FAE6 = 0x40
	// Position of FAE7 field.
	DSIHOST1_DSI_FIR0_FAE7_Pos = 0x7
	// Bit mask of FAE7 field.
	DSIHOST1_DSI_FIR0_FAE7_Msk = 0x80
	// Bit FAE7.
	DSIHOST1_DSI_FIR0_FAE7 = 0x80
	// Position of FAE8 field.
	DSIHOST1_DSI_FIR0_FAE8_Pos = 0x8
	// Bit mask of FAE8 field.
	DSIHOST1_DSI_FIR0_FAE8_Msk = 0x100
	// Bit FAE8.
	DSIHOST1_DSI_FIR0_FAE8 = 0x100
	// Position of FAE9 field.
	DSIHOST1_DSI_FIR0_FAE9_Pos = 0x9
	// Bit mask of FAE9 field.
	DSIHOST1_DSI_FIR0_FAE9_Msk = 0x200
	// Bit FAE9.
	DSIHOST1_DSI_FIR0_FAE9 = 0x200
	// Position of FAE10 field.
	DSIHOST1_DSI_FIR0_FAE10_Pos = 0xa
	// Bit mask of FAE10 field.
	DSIHOST1_DSI_FIR0_FAE10_Msk = 0x400
	// Bit FAE10.
	DSIHOST1_DSI_FIR0_FAE10 = 0x400
	// Position of FAE11 field.
	DSIHOST1_DSI_FIR0_FAE11_Pos = 0xb
	// Bit mask of FAE11 field.
	DSIHOST1_DSI_FIR0_FAE11_Msk = 0x800
	// Bit FAE11.
	DSIHOST1_DSI_FIR0_FAE11 = 0x800
	// Position of FAE12 field.
	DSIHOST1_DSI_FIR0_FAE12_Pos = 0xc
	// Bit mask of FAE12 field.
	DSIHOST1_DSI_FIR0_FAE12_Msk = 0x1000
	// Bit FAE12.
	DSIHOST1_DSI_FIR0_FAE12 = 0x1000
	// Position of FAE13 field.
	DSIHOST1_DSI_FIR0_FAE13_Pos = 0xd
	// Bit mask of FAE13 field.
	DSIHOST1_DSI_FIR0_FAE13_Msk = 0x2000
	// Bit FAE13.
	DSIHOST1_DSI_FIR0_FAE13 = 0x2000
	// Position of FAE14 field.
	DSIHOST1_DSI_FIR0_FAE14_Pos = 0xe
	// Bit mask of FAE14 field.
	DSIHOST1_DSI_FIR0_FAE14_Msk = 0x4000
	// Bit FAE14.
	DSIHOST1_DSI_FIR0_FAE14 = 0x4000
	// Position of FAE15 field.
	DSIHOST1_DSI_FIR0_FAE15_Pos = 0xf
	// Bit mask of FAE15 field.
	DSIHOST1_DSI_FIR0_FAE15_Msk = 0x8000
	// Bit FAE15.
	DSIHOST1_DSI_FIR0_FAE15 = 0x8000
	// Position of FPE0 field.
	DSIHOST1_DSI_FIR0_FPE0_Pos = 0x10
	// Bit mask of FPE0 field.
	DSIHOST1_DSI_FIR0_FPE0_Msk = 0x10000
	// Bit FPE0.
	DSIHOST1_DSI_FIR0_FPE0 = 0x10000
	// Position of FPE1 field.
	DSIHOST1_DSI_FIR0_FPE1_Pos = 0x11
	// Bit mask of FPE1 field.
	DSIHOST1_DSI_FIR0_FPE1_Msk = 0x20000
	// Bit FPE1.
	DSIHOST1_DSI_FIR0_FPE1 = 0x20000
	// Position of FPE2 field.
	DSIHOST1_DSI_FIR0_FPE2_Pos = 0x12
	// Bit mask of FPE2 field.
	DSIHOST1_DSI_FIR0_FPE2_Msk = 0x40000
	// Bit FPE2.
	DSIHOST1_DSI_FIR0_FPE2 = 0x40000
	// Position of FPE3 field.
	DSIHOST1_DSI_FIR0_FPE3_Pos = 0x13
	// Bit mask of FPE3 field.
	DSIHOST1_DSI_FIR0_FPE3_Msk = 0x80000
	// Bit FPE3.
	DSIHOST1_DSI_FIR0_FPE3 = 0x80000
	// Position of FPE4 field.
	DSIHOST1_DSI_FIR0_FPE4_Pos = 0x14
	// Bit mask of FPE4 field.
	DSIHOST1_DSI_FIR0_FPE4_Msk = 0x100000
	// Bit FPE4.
	DSIHOST1_DSI_FIR0_FPE4 = 0x100000

	// DSI_FIR1: DSI Host force interrupt register 1
	// Position of FTOHSTX field.
	DSIHOST1_DSI_FIR1_FTOHSTX_Pos = 0x0
	// Bit mask of FTOHSTX field.
	DSIHOST1_DSI_FIR1_FTOHSTX_Msk = 0x1
	// Bit FTOHSTX.
	DSIHOST1_DSI_FIR1_FTOHSTX = 0x1
	// Position of FTOLPRX field.
	DSIHOST1_DSI_FIR1_FTOLPRX_Pos = 0x1
	// Bit mask of FTOLPRX field.
	DSIHOST1_DSI_FIR1_FTOLPRX_Msk = 0x2
	// Bit FTOLPRX.
	DSIHOST1_DSI_FIR1_FTOLPRX = 0x2
	// Position of FECCSE field.
	DSIHOST1_DSI_FIR1_FECCSE_Pos = 0x2
	// Bit mask of FECCSE field.
	DSIHOST1_DSI_FIR1_FECCSE_Msk = 0x4
	// Bit FECCSE.
	DSIHOST1_DSI_FIR1_FECCSE = 0x4
	// Position of FECCME field.
	DSIHOST1_DSI_FIR1_FECCME_Pos = 0x3
	// Bit mask of FECCME field.
	DSIHOST1_DSI_FIR1_FECCME_Msk = 0x8
	// Bit FECCME.
	DSIHOST1_DSI_FIR1_FECCME = 0x8
	// Position of FCRCE field.
	DSIHOST1_DSI_FIR1_FCRCE_Pos = 0x4
	// Bit mask of FCRCE field.
	DSIHOST1_DSI_FIR1_FCRCE_Msk = 0x10
	// Bit FCRCE.
	DSIHOST1_DSI_FIR1_FCRCE = 0x10
	// Position of FPSE field.
	DSIHOST1_DSI_FIR1_FPSE_Pos = 0x5
	// Bit mask of FPSE field.
	DSIHOST1_DSI_FIR1_FPSE_Msk = 0x20
	// Bit FPSE.
	DSIHOST1_DSI_FIR1_FPSE = 0x20
	// Position of FEOTPE field.
	DSIHOST1_DSI_FIR1_FEOTPE_Pos = 0x6
	// Bit mask of FEOTPE field.
	DSIHOST1_DSI_FIR1_FEOTPE_Msk = 0x40
	// Bit FEOTPE.
	DSIHOST1_DSI_FIR1_FEOTPE = 0x40
	// Position of FLPWRE field.
	DSIHOST1_DSI_FIR1_FLPWRE_Pos = 0x7
	// Bit mask of FLPWRE field.
	DSIHOST1_DSI_FIR1_FLPWRE_Msk = 0x80
	// Bit FLPWRE.
	DSIHOST1_DSI_FIR1_FLPWRE = 0x80
	// Position of FGCWRE field.
	DSIHOST1_DSI_FIR1_FGCWRE_Pos = 0x8
	// Bit mask of FGCWRE field.
	DSIHOST1_DSI_FIR1_FGCWRE_Msk = 0x100
	// Bit FGCWRE.
	DSIHOST1_DSI_FIR1_FGCWRE = 0x100
	// Position of FGPWRE field.
	DSIHOST1_DSI_FIR1_FGPWRE_Pos = 0x9
	// Bit mask of FGPWRE field.
	DSIHOST1_DSI_FIR1_FGPWRE_Msk = 0x200
	// Bit FGPWRE.
	DSIHOST1_DSI_FIR1_FGPWRE = 0x200
	// Position of FGPTXE field.
	DSIHOST1_DSI_FIR1_FGPTXE_Pos = 0xa
	// Bit mask of FGPTXE field.
	DSIHOST1_DSI_FIR1_FGPTXE_Msk = 0x400
	// Bit FGPTXE.
	DSIHOST1_DSI_FIR1_FGPTXE = 0x400
	// Position of FGPRDE field.
	DSIHOST1_DSI_FIR1_FGPRDE_Pos = 0xb
	// Bit mask of FGPRDE field.
	DSIHOST1_DSI_FIR1_FGPRDE_Msk = 0x800
	// Bit FGPRDE.
	DSIHOST1_DSI_FIR1_FGPRDE = 0x800
	// Position of FGPRXE field.
	DSIHOST1_DSI_FIR1_FGPRXE_Pos = 0xc
	// Bit mask of FGPRXE field.
	DSIHOST1_DSI_FIR1_FGPRXE_Msk = 0x1000
	// Bit FGPRXE.
	DSIHOST1_DSI_FIR1_FGPRXE = 0x1000

	// DSI_DLTRCR: DSI Host data lane timer read configuration register
	// Position of MRD_TIME field.
	DSIHOST1_DSI_DLTRCR_MRD_TIME_Pos = 0x0
	// Bit mask of MRD_TIME field.
	DSIHOST1_DSI_DLTRCR_MRD_TIME_Msk = 0x7fff

	// DSI_VSCR: DSI Host video shadow control register
	// Position of EN field.
	DSIHOST1_DSI_VSCR_EN_Pos = 0x0
	// Bit mask of EN field.
	DSIHOST1_DSI_VSCR_EN_Msk = 0x1
	// Bit EN.
	DSIHOST1_DSI_VSCR_EN = 0x1
	// Position of UR field.
	DSIHOST1_DSI_VSCR_UR_Pos = 0x8
	// Bit mask of UR field.
	DSIHOST1_DSI_VSCR_UR_Msk = 0x100
	// Bit UR.
	DSIHOST1_DSI_VSCR_UR = 0x100

	// DSI_LCVCIDR: DSI Host LTDC current VCID register
	// Position of VCID field.
	DSIHOST1_DSI_LCVCIDR_VCID_Pos = 0x0
	// Bit mask of VCID field.
	DSIHOST1_DSI_LCVCIDR_VCID_Msk = 0x3

	// DSI_LCCCR: DSI Host LTDC current color coding register
	// Position of COLC field.
	DSIHOST1_DSI_LCCCR_COLC_Pos = 0x0
	// Bit mask of COLC field.
	DSIHOST1_DSI_LCCCR_COLC_Msk = 0xf
	// Position of LPE field.
	DSIHOST1_DSI_LCCCR_LPE_Pos = 0x8
	// Bit mask of LPE field.
	DSIHOST1_DSI_LCCCR_LPE_Msk = 0x100
	// Bit LPE.
	DSIHOST1_DSI_LCCCR_LPE = 0x100

	// DSI_LPMCCR: DSI Host low-power mode current configuration register
	// Position of VLPSIZE field.
	DSIHOST1_DSI_LPMCCR_VLPSIZE_Pos = 0x0
	// Bit mask of VLPSIZE field.
	DSIHOST1_DSI_LPMCCR_VLPSIZE_Msk = 0xff
	// Position of LPSIZE field.
	DSIHOST1_DSI_LPMCCR_LPSIZE_Pos = 0x10
	// Bit mask of LPSIZE field.
	DSIHOST1_DSI_LPMCCR_LPSIZE_Msk = 0xff0000

	// DSI_VMCCR: DSI Host video mode current configuration register
	// Position of VMT field.
	DSIHOST1_DSI_VMCCR_VMT_Pos = 0x0
	// Bit mask of VMT field.
	DSIHOST1_DSI_VMCCR_VMT_Msk = 0x3
	// Position of LPVSAE field.
	DSIHOST1_DSI_VMCCR_LPVSAE_Pos = 0x2
	// Bit mask of LPVSAE field.
	DSIHOST1_DSI_VMCCR_LPVSAE_Msk = 0x4
	// Bit LPVSAE.
	DSIHOST1_DSI_VMCCR_LPVSAE = 0x4
	// Position of LPVBPE field.
	DSIHOST1_DSI_VMCCR_LPVBPE_Pos = 0x3
	// Bit mask of LPVBPE field.
	DSIHOST1_DSI_VMCCR_LPVBPE_Msk = 0x8
	// Bit LPVBPE.
	DSIHOST1_DSI_VMCCR_LPVBPE = 0x8
	// Position of LPVFPE field.
	DSIHOST1_DSI_VMCCR_LPVFPE_Pos = 0x4
	// Bit mask of LPVFPE field.
	DSIHOST1_DSI_VMCCR_LPVFPE_Msk = 0x10
	// Bit LPVFPE.
	DSIHOST1_DSI_VMCCR_LPVFPE = 0x10
	// Position of LPVAE field.
	DSIHOST1_DSI_VMCCR_LPVAE_Pos = 0x5
	// Bit mask of LPVAE field.
	DSIHOST1_DSI_VMCCR_LPVAE_Msk = 0x20
	// Bit LPVAE.
	DSIHOST1_DSI_VMCCR_LPVAE = 0x20
	// Position of LPHBPE field.
	DSIHOST1_DSI_VMCCR_LPHBPE_Pos = 0x6
	// Bit mask of LPHBPE field.
	DSIHOST1_DSI_VMCCR_LPHBPE_Msk = 0x40
	// Bit LPHBPE.
	DSIHOST1_DSI_VMCCR_LPHBPE = 0x40
	// Position of LPHFE field.
	DSIHOST1_DSI_VMCCR_LPHFE_Pos = 0x7
	// Bit mask of LPHFE field.
	DSIHOST1_DSI_VMCCR_LPHFE_Msk = 0x80
	// Bit LPHFE.
	DSIHOST1_DSI_VMCCR_LPHFE = 0x80
	// Position of FBTAAE field.
	DSIHOST1_DSI_VMCCR_FBTAAE_Pos = 0x8
	// Bit mask of FBTAAE field.
	DSIHOST1_DSI_VMCCR_FBTAAE_Msk = 0x100
	// Bit FBTAAE.
	DSIHOST1_DSI_VMCCR_FBTAAE = 0x100
	// Position of LPCE field.
	DSIHOST1_DSI_VMCCR_LPCE_Pos = 0x9
	// Bit mask of LPCE field.
	DSIHOST1_DSI_VMCCR_LPCE_Msk = 0x200
	// Bit LPCE.
	DSIHOST1_DSI_VMCCR_LPCE = 0x200

	// DSI_VPCCR: DSI Host video packet current configuration register
	// Position of VPSIZE field.
	DSIHOST1_DSI_VPCCR_VPSIZE_Pos = 0x0
	// Bit mask of VPSIZE field.
	DSIHOST1_DSI_VPCCR_VPSIZE_Msk = 0x3fff

	// DSI_VCCCR: DSI Host video chunks current configuration register
	// Position of NUMC field.
	DSIHOST1_DSI_VCCCR_NUMC_Pos = 0x0
	// Bit mask of NUMC field.
	DSIHOST1_DSI_VCCCR_NUMC_Msk = 0x1fff

	// DSI_VNPCCR: DSI Host video null packet current configuration register
	// Position of NPSIZE field.
	DSIHOST1_DSI_VNPCCR_NPSIZE_Pos = 0x0
	// Bit mask of NPSIZE field.
	DSIHOST1_DSI_VNPCCR_NPSIZE_Msk = 0x1fff

	// DSI_VHSACCR: DSI Host video HSA current configuration register
	// Position of HSA field.
	DSIHOST1_DSI_VHSACCR_HSA_Pos = 0x0
	// Bit mask of HSA field.
	DSIHOST1_DSI_VHSACCR_HSA_Msk = 0xfff

	// DSI_VHBPCCR: DSI Host video HBP current configuration register
	// Position of HBP field.
	DSIHOST1_DSI_VHBPCCR_HBP_Pos = 0x0
	// Bit mask of HBP field.
	DSIHOST1_DSI_VHBPCCR_HBP_Msk = 0xfff

	// DSI_VLCCR: DSI Host video line current configuration register
	// Position of HLINE field.
	DSIHOST1_DSI_VLCCR_HLINE_Pos = 0x0
	// Bit mask of HLINE field.
	DSIHOST1_DSI_VLCCR_HLINE_Msk = 0x7fff

	// DSI_VVSACCR: DSI Host video VSA current configuration register
	// Position of VSA field.
	DSIHOST1_DSI_VVSACCR_VSA_Pos = 0x0
	// Bit mask of VSA field.
	DSIHOST1_DSI_VVSACCR_VSA_Msk = 0x3ff

	// DSI_VVBPCCR: DSI Host video VBP current configuration register
	// Position of VBP field.
	DSIHOST1_DSI_VVBPCCR_VBP_Pos = 0x0
	// Bit mask of VBP field.
	DSIHOST1_DSI_VVBPCCR_VBP_Msk = 0x3ff

	// DSI_VVFPCCR: DSI Host video VFP current configuration register
	// Position of VFP field.
	DSIHOST1_DSI_VVFPCCR_VFP_Pos = 0x0
	// Bit mask of VFP field.
	DSIHOST1_DSI_VVFPCCR_VFP_Msk = 0x3ff

	// DSI_VVACCR: DSI Host video VA current configuration register
	// Position of VA field.
	DSIHOST1_DSI_VVACCR_VA_Pos = 0x0
	// Bit mask of VA field.
	DSIHOST1_DSI_VVACCR_VA_Msk = 0x3fff

	// DSI_WCFGR: DSI wrapper configuration register
	// Position of DSIM field.
	DSIHOST1_DSI_WCFGR_DSIM_Pos = 0x0
	// Bit mask of DSIM field.
	DSIHOST1_DSI_WCFGR_DSIM_Msk = 0x1
	// Bit DSIM.
	DSIHOST1_DSI_WCFGR_DSIM = 0x1
	// Position of COLMUX field.
	DSIHOST1_DSI_WCFGR_COLMUX_Pos = 0x1
	// Bit mask of COLMUX field.
	DSIHOST1_DSI_WCFGR_COLMUX_Msk = 0xe
	// Position of TESRC field.
	DSIHOST1_DSI_WCFGR_TESRC_Pos = 0x4
	// Bit mask of TESRC field.
	DSIHOST1_DSI_WCFGR_TESRC_Msk = 0x10
	// Bit TESRC.
	DSIHOST1_DSI_WCFGR_TESRC = 0x10
	// Position of TEPOL field.
	DSIHOST1_DSI_WCFGR_TEPOL_Pos = 0x5
	// Bit mask of TEPOL field.
	DSIHOST1_DSI_WCFGR_TEPOL_Msk = 0x20
	// Bit TEPOL.
	DSIHOST1_DSI_WCFGR_TEPOL = 0x20
	// Position of AR field.
	DSIHOST1_DSI_WCFGR_AR_Pos = 0x6
	// Bit mask of AR field.
	DSIHOST1_DSI_WCFGR_AR_Msk = 0x40
	// Bit AR.
	DSIHOST1_DSI_WCFGR_AR = 0x40
	// Position of VSPOL field.
	DSIHOST1_DSI_WCFGR_VSPOL_Pos = 0x7
	// Bit mask of VSPOL field.
	DSIHOST1_DSI_WCFGR_VSPOL_Msk = 0x80
	// Bit VSPOL.
	DSIHOST1_DSI_WCFGR_VSPOL = 0x80

	// DSI_WCR: DSI wrapper control register
	// Position of COLM field.
	DSIHOST1_DSI_WCR_COLM_Pos = 0x0
	// Bit mask of COLM field.
	DSIHOST1_DSI_WCR_COLM_Msk = 0x1
	// Bit COLM.
	DSIHOST1_DSI_WCR_COLM = 0x1
	// Position of SHTDN field.
	DSIHOST1_DSI_WCR_SHTDN_Pos = 0x1
	// Bit mask of SHTDN field.
	DSIHOST1_DSI_WCR_SHTDN_Msk = 0x2
	// Bit SHTDN.
	DSIHOST1_DSI_WCR_SHTDN = 0x2
	// Position of LTDCEN field.
	DSIHOST1_DSI_WCR_LTDCEN_Pos = 0x2
	// Bit mask of LTDCEN field.
	DSIHOST1_DSI_WCR_LTDCEN_Msk = 0x4
	// Bit LTDCEN.
	DSIHOST1_DSI_WCR_LTDCEN = 0x4
	// Position of DSIEN field.
	DSIHOST1_DSI_WCR_DSIEN_Pos = 0x3
	// Bit mask of DSIEN field.
	DSIHOST1_DSI_WCR_DSIEN_Msk = 0x8
	// Bit DSIEN.
	DSIHOST1_DSI_WCR_DSIEN = 0x8

	// DSI_WIER: DSI wrapper interrupt enable register
	// Position of TEIE field.
	DSIHOST1_DSI_WIER_TEIE_Pos = 0x0
	// Bit mask of TEIE field.
	DSIHOST1_DSI_WIER_TEIE_Msk = 0x1
	// Bit TEIE.
	DSIHOST1_DSI_WIER_TEIE = 0x1
	// Position of ERIE field.
	DSIHOST1_DSI_WIER_ERIE_Pos = 0x1
	// Bit mask of ERIE field.
	DSIHOST1_DSI_WIER_ERIE_Msk = 0x2
	// Bit ERIE.
	DSIHOST1_DSI_WIER_ERIE = 0x2
	// Position of PLLLIE field.
	DSIHOST1_DSI_WIER_PLLLIE_Pos = 0x9
	// Bit mask of PLLLIE field.
	DSIHOST1_DSI_WIER_PLLLIE_Msk = 0x200
	// Bit PLLLIE.
	DSIHOST1_DSI_WIER_PLLLIE = 0x200
	// Position of PLLUIE field.
	DSIHOST1_DSI_WIER_PLLUIE_Pos = 0xa
	// Bit mask of PLLUIE field.
	DSIHOST1_DSI_WIER_PLLUIE_Msk = 0x400
	// Bit PLLUIE.
	DSIHOST1_DSI_WIER_PLLUIE = 0x400
	// Position of RRIE field.
	DSIHOST1_DSI_WIER_RRIE_Pos = 0xd
	// Bit mask of RRIE field.
	DSIHOST1_DSI_WIER_RRIE_Msk = 0x2000
	// Bit RRIE.
	DSIHOST1_DSI_WIER_RRIE = 0x2000

	// DSI_WISR: DSI wrapper interrupt and status register
	// Position of TEIF field.
	DSIHOST1_DSI_WISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	DSIHOST1_DSI_WISR_TEIF_Msk = 0x1
	// Bit TEIF.
	DSIHOST1_DSI_WISR_TEIF = 0x1
	// Position of ERIF field.
	DSIHOST1_DSI_WISR_ERIF_Pos = 0x1
	// Bit mask of ERIF field.
	DSIHOST1_DSI_WISR_ERIF_Msk = 0x2
	// Bit ERIF.
	DSIHOST1_DSI_WISR_ERIF = 0x2
	// Position of BUSY field.
	DSIHOST1_DSI_WISR_BUSY_Pos = 0x2
	// Bit mask of BUSY field.
	DSIHOST1_DSI_WISR_BUSY_Msk = 0x4
	// Bit BUSY.
	DSIHOST1_DSI_WISR_BUSY = 0x4
	// Position of PLLLS field.
	DSIHOST1_DSI_WISR_PLLLS_Pos = 0x8
	// Bit mask of PLLLS field.
	DSIHOST1_DSI_WISR_PLLLS_Msk = 0x100
	// Bit PLLLS.
	DSIHOST1_DSI_WISR_PLLLS = 0x100
	// Position of PLLLIF field.
	DSIHOST1_DSI_WISR_PLLLIF_Pos = 0x9
	// Bit mask of PLLLIF field.
	DSIHOST1_DSI_WISR_PLLLIF_Msk = 0x200
	// Bit PLLLIF.
	DSIHOST1_DSI_WISR_PLLLIF = 0x200
	// Position of PLLUIF field.
	DSIHOST1_DSI_WISR_PLLUIF_Pos = 0xa
	// Bit mask of PLLUIF field.
	DSIHOST1_DSI_WISR_PLLUIF_Msk = 0x400
	// Bit PLLUIF.
	DSIHOST1_DSI_WISR_PLLUIF = 0x400
	// Position of RRS field.
	DSIHOST1_DSI_WISR_RRS_Pos = 0xc
	// Bit mask of RRS field.
	DSIHOST1_DSI_WISR_RRS_Msk = 0x1000
	// Bit RRS.
	DSIHOST1_DSI_WISR_RRS = 0x1000
	// Position of RRIF field.
	DSIHOST1_DSI_WISR_RRIF_Pos = 0xd
	// Bit mask of RRIF field.
	DSIHOST1_DSI_WISR_RRIF_Msk = 0x2000
	// Bit RRIF.
	DSIHOST1_DSI_WISR_RRIF = 0x2000

	// DSI_WIFCR: DSI wrapper interrupt flag clear register
	// Position of CTEIF field.
	DSIHOST1_DSI_WIFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	DSIHOST1_DSI_WIFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	DSIHOST1_DSI_WIFCR_CTEIF = 0x1
	// Position of CERIF field.
	DSIHOST1_DSI_WIFCR_CERIF_Pos = 0x1
	// Bit mask of CERIF field.
	DSIHOST1_DSI_WIFCR_CERIF_Msk = 0x2
	// Bit CERIF.
	DSIHOST1_DSI_WIFCR_CERIF = 0x2
	// Position of CPLLLIF field.
	DSIHOST1_DSI_WIFCR_CPLLLIF_Pos = 0x9
	// Bit mask of CPLLLIF field.
	DSIHOST1_DSI_WIFCR_CPLLLIF_Msk = 0x200
	// Bit CPLLLIF.
	DSIHOST1_DSI_WIFCR_CPLLLIF = 0x200
	// Position of CPLLUIF field.
	DSIHOST1_DSI_WIFCR_CPLLUIF_Pos = 0xa
	// Bit mask of CPLLUIF field.
	DSIHOST1_DSI_WIFCR_CPLLUIF_Msk = 0x400
	// Bit CPLLUIF.
	DSIHOST1_DSI_WIFCR_CPLLUIF = 0x400
	// Position of CRRIF field.
	DSIHOST1_DSI_WIFCR_CRRIF_Pos = 0xd
	// Bit mask of CRRIF field.
	DSIHOST1_DSI_WIFCR_CRRIF_Msk = 0x2000
	// Bit CRRIF.
	DSIHOST1_DSI_WIFCR_CRRIF = 0x2000

	// DSI_WPCR0: DSI wrapper PHY configuration register 0
	// Position of UIX4 field.
	DSIHOST1_DSI_WPCR0_UIX4_Pos = 0x0
	// Bit mask of UIX4 field.
	DSIHOST1_DSI_WPCR0_UIX4_Msk = 0x3f
	// Position of SWCL field.
	DSIHOST1_DSI_WPCR0_SWCL_Pos = 0x6
	// Bit mask of SWCL field.
	DSIHOST1_DSI_WPCR0_SWCL_Msk = 0x40
	// Bit SWCL.
	DSIHOST1_DSI_WPCR0_SWCL = 0x40
	// Position of SWDL0 field.
	DSIHOST1_DSI_WPCR0_SWDL0_Pos = 0x7
	// Bit mask of SWDL0 field.
	DSIHOST1_DSI_WPCR0_SWDL0_Msk = 0x80
	// Bit SWDL0.
	DSIHOST1_DSI_WPCR0_SWDL0 = 0x80
	// Position of SWDL1 field.
	DSIHOST1_DSI_WPCR0_SWDL1_Pos = 0x8
	// Bit mask of SWDL1 field.
	DSIHOST1_DSI_WPCR0_SWDL1_Msk = 0x100
	// Bit SWDL1.
	DSIHOST1_DSI_WPCR0_SWDL1 = 0x100
	// Position of HSICL field.
	DSIHOST1_DSI_WPCR0_HSICL_Pos = 0x9
	// Bit mask of HSICL field.
	DSIHOST1_DSI_WPCR0_HSICL_Msk = 0x200
	// Bit HSICL.
	DSIHOST1_DSI_WPCR0_HSICL = 0x200
	// Position of HSIDL0 field.
	DSIHOST1_DSI_WPCR0_HSIDL0_Pos = 0xa
	// Bit mask of HSIDL0 field.
	DSIHOST1_DSI_WPCR0_HSIDL0_Msk = 0x400
	// Bit HSIDL0.
	DSIHOST1_DSI_WPCR0_HSIDL0 = 0x400
	// Position of HSIDL1 field.
	DSIHOST1_DSI_WPCR0_HSIDL1_Pos = 0xb
	// Bit mask of HSIDL1 field.
	DSIHOST1_DSI_WPCR0_HSIDL1_Msk = 0x800
	// Bit HSIDL1.
	DSIHOST1_DSI_WPCR0_HSIDL1 = 0x800
	// Position of FTXSMCL field.
	DSIHOST1_DSI_WPCR0_FTXSMCL_Pos = 0xc
	// Bit mask of FTXSMCL field.
	DSIHOST1_DSI_WPCR0_FTXSMCL_Msk = 0x1000
	// Bit FTXSMCL.
	DSIHOST1_DSI_WPCR0_FTXSMCL = 0x1000
	// Position of FTXSMDL field.
	DSIHOST1_DSI_WPCR0_FTXSMDL_Pos = 0xd
	// Bit mask of FTXSMDL field.
	DSIHOST1_DSI_WPCR0_FTXSMDL_Msk = 0x2000
	// Bit FTXSMDL.
	DSIHOST1_DSI_WPCR0_FTXSMDL = 0x2000
	// Position of CDOFFDL field.
	DSIHOST1_DSI_WPCR0_CDOFFDL_Pos = 0xe
	// Bit mask of CDOFFDL field.
	DSIHOST1_DSI_WPCR0_CDOFFDL_Msk = 0x4000
	// Bit CDOFFDL.
	DSIHOST1_DSI_WPCR0_CDOFFDL = 0x4000
	// Position of TDDL field.
	DSIHOST1_DSI_WPCR0_TDDL_Pos = 0x10
	// Bit mask of TDDL field.
	DSIHOST1_DSI_WPCR0_TDDL_Msk = 0x10000
	// Bit TDDL.
	DSIHOST1_DSI_WPCR0_TDDL = 0x10000

	// DSI_WPCR1: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).
	// Position of SKEWCL field.
	DSIHOST1_DSI_WPCR1_SKEWCL_Pos = 0x0
	// Bit mask of SKEWCL field.
	DSIHOST1_DSI_WPCR1_SKEWCL_Msk = 0x3
	// Position of SKEWDL field.
	DSIHOST1_DSI_WPCR1_SKEWDL_Pos = 0x2
	// Bit mask of SKEWDL field.
	DSIHOST1_DSI_WPCR1_SKEWDL_Msk = 0xc
	// Position of LPTXSRCL field.
	DSIHOST1_DSI_WPCR1_LPTXSRCL_Pos = 0x6
	// Bit mask of LPTXSRCL field.
	DSIHOST1_DSI_WPCR1_LPTXSRCL_Msk = 0xc0
	// Position of LPTXSRDL field.
	DSIHOST1_DSI_WPCR1_LPTXSRDL_Pos = 0x8
	// Bit mask of LPTXSRDL field.
	DSIHOST1_DSI_WPCR1_LPTXSRDL_Msk = 0x300
	// Position of SDDCCL field.
	DSIHOST1_DSI_WPCR1_SDDCCL_Pos = 0xc
	// Bit mask of SDDCCL field.
	DSIHOST1_DSI_WPCR1_SDDCCL_Msk = 0x1000
	// Bit SDDCCL.
	DSIHOST1_DSI_WPCR1_SDDCCL = 0x1000
	// Position of SDDCDL field.
	DSIHOST1_DSI_WPCR1_SDDCDL_Pos = 0xd
	// Bit mask of SDDCDL field.
	DSIHOST1_DSI_WPCR1_SDDCDL_Msk = 0x2000
	// Bit SDDCDL.
	DSIHOST1_DSI_WPCR1_SDDCDL = 0x2000
	// Position of HSTXSRUCL field.
	DSIHOST1_DSI_WPCR1_HSTXSRUCL_Pos = 0x10
	// Bit mask of HSTXSRUCL field.
	DSIHOST1_DSI_WPCR1_HSTXSRUCL_Msk = 0x10000
	// Bit HSTXSRUCL.
	DSIHOST1_DSI_WPCR1_HSTXSRUCL = 0x10000
	// Position of HSTXSRDCL field.
	DSIHOST1_DSI_WPCR1_HSTXSRDCL_Pos = 0x11
	// Bit mask of HSTXSRDCL field.
	DSIHOST1_DSI_WPCR1_HSTXSRDCL_Msk = 0x20000
	// Bit HSTXSRDCL.
	DSIHOST1_DSI_WPCR1_HSTXSRDCL = 0x20000
	// Position of HSTXSRUDL field.
	DSIHOST1_DSI_WPCR1_HSTXSRUDL_Pos = 0x12
	// Bit mask of HSTXSRUDL field.
	DSIHOST1_DSI_WPCR1_HSTXSRUDL_Msk = 0x40000
	// Bit HSTXSRUDL.
	DSIHOST1_DSI_WPCR1_HSTXSRUDL = 0x40000
	// Position of HSTXSRDDL field.
	DSIHOST1_DSI_WPCR1_HSTXSRDDL_Pos = 0x13
	// Bit mask of HSTXSRDDL field.
	DSIHOST1_DSI_WPCR1_HSTXSRDDL_Msk = 0x80000
	// Bit HSTXSRDDL.
	DSIHOST1_DSI_WPCR1_HSTXSRDDL = 0x80000

	// DSI_WRPCR: DSI wrapper regulator and PLL control register
	// Position of PLLEN field.
	DSIHOST1_DSI_WRPCR_PLLEN_Pos = 0x0
	// Bit mask of PLLEN field.
	DSIHOST1_DSI_WRPCR_PLLEN_Msk = 0x1
	// Bit PLLEN.
	DSIHOST1_DSI_WRPCR_PLLEN = 0x1
	// Position of NDIV field.
	DSIHOST1_DSI_WRPCR_NDIV_Pos = 0x2
	// Bit mask of NDIV field.
	DSIHOST1_DSI_WRPCR_NDIV_Msk = 0x1fc
	// Position of IDF field.
	DSIHOST1_DSI_WRPCR_IDF_Pos = 0xb
	// Bit mask of IDF field.
	DSIHOST1_DSI_WRPCR_IDF_Msk = 0x7800
	// Position of ODF field.
	DSIHOST1_DSI_WRPCR_ODF_Pos = 0x10
	// Bit mask of ODF field.
	DSIHOST1_DSI_WRPCR_ODF_Msk = 0x30000
	// Position of REGEN field.
	DSIHOST1_DSI_WRPCR_REGEN_Pos = 0x18
	// Bit mask of REGEN field.
	DSIHOST1_DSI_WRPCR_REGEN_Msk = 0x1000000
	// Bit REGEN.
	DSIHOST1_DSI_WRPCR_REGEN = 0x1000000
	// Position of BGREN field.
	DSIHOST1_DSI_WRPCR_BGREN_Pos = 0x1c
	// Bit mask of BGREN field.
	DSIHOST1_DSI_WRPCR_BGREN_Msk = 0x10000000
	// Bit BGREN.
	DSIHOST1_DSI_WRPCR_BGREN = 0x10000000

	// DSI_HWCFGR: DSI Host hardware configuration register
	// Position of TECHNO field.
	DSIHOST1_DSI_HWCFGR_TECHNO_Pos = 0x0
	// Bit mask of TECHNO field.
	DSIHOST1_DSI_HWCFGR_TECHNO_Msk = 0xf
	// Position of FIFOSIZE field.
	DSIHOST1_DSI_HWCFGR_FIFOSIZE_Pos = 0x4
	// Bit mask of FIFOSIZE field.
	DSIHOST1_DSI_HWCFGR_FIFOSIZE_Msk = 0xfff0

	// DSI_VERR: DSI Host version register
	// Position of MINREV field.
	DSIHOST1_DSI_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	DSIHOST1_DSI_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	DSIHOST1_DSI_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	DSIHOST1_DSI_VERR_MAJREV_Msk = 0xf0

	// DSI_IPIDR: DSI Host identification register
	// Position of ID field.
	DSIHOST1_DSI_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	DSIHOST1_DSI_IPIDR_ID_Msk = 0xffffffff

	// DSI_SIDR: DSI Host size identification register
	// Position of SID field.
	DSIHOST1_DSI_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	DSIHOST1_DSI_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for DTS: DTS register block
const (
	// DTS_CFGR1: DTS_CFGR1 is the configuration register for temperature sensor 1.
	// Position of TS1_EN field.
	DTS_DTS_CFGR1_TS1_EN_Pos = 0x0
	// Bit mask of TS1_EN field.
	DTS_DTS_CFGR1_TS1_EN_Msk = 0x1
	// Bit TS1_EN.
	DTS_DTS_CFGR1_TS1_EN = 0x1
	// Position of TS1_START field.
	DTS_DTS_CFGR1_TS1_START_Pos = 0x4
	// Bit mask of TS1_START field.
	DTS_DTS_CFGR1_TS1_START_Msk = 0x10
	// Bit TS1_START.
	DTS_DTS_CFGR1_TS1_START = 0x10
	// Position of TS1_INTRIG_SEL field.
	DTS_DTS_CFGR1_TS1_INTRIG_SEL_Pos = 0x8
	// Bit mask of TS1_INTRIG_SEL field.
	DTS_DTS_CFGR1_TS1_INTRIG_SEL_Msk = 0xf00
	// Position of TS1_SMP_TIME field.
	DTS_DTS_CFGR1_TS1_SMP_TIME_Pos = 0x10
	// Bit mask of TS1_SMP_TIME field.
	DTS_DTS_CFGR1_TS1_SMP_TIME_Msk = 0xf0000
	// Position of REFCLK_SEL field.
	DTS_DTS_CFGR1_REFCLK_SEL_Pos = 0x14
	// Bit mask of REFCLK_SEL field.
	DTS_DTS_CFGR1_REFCLK_SEL_Msk = 0x100000
	// Bit REFCLK_SEL.
	DTS_DTS_CFGR1_REFCLK_SEL = 0x100000
	// Position of Q_MEAS_opt field.
	DTS_DTS_CFGR1_Q_MEAS_opt_Pos = 0x15
	// Bit mask of Q_MEAS_opt field.
	DTS_DTS_CFGR1_Q_MEAS_opt_Msk = 0x200000
	// Bit Q_MEAS_opt.
	DTS_DTS_CFGR1_Q_MEAS_opt = 0x200000
	// Position of HSREF_CLK_DIV field.
	DTS_DTS_CFGR1_HSREF_CLK_DIV_Pos = 0x18
	// Bit mask of HSREF_CLK_DIV field.
	DTS_DTS_CFGR1_HSREF_CLK_DIV_Msk = 0x7f000000

	// DTS_T0VALR1: DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed.
	// Position of TS1_FMT0 field.
	DTS_DTS_T0VALR1_TS1_FMT0_Pos = 0x0
	// Bit mask of TS1_FMT0 field.
	DTS_DTS_T0VALR1_TS1_FMT0_Msk = 0xffff
	// Position of TS1_T0 field.
	DTS_DTS_T0VALR1_TS1_T0_Pos = 0x10
	// Bit mask of TS1_T0 field.
	DTS_DTS_T0VALR1_TS1_T0_Msk = 0x30000

	// DTS_RAMPVALR: The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed.
	// Position of TS1_RAMP_COEFF field.
	DTS_DTS_RAMPVALR_TS1_RAMP_COEFF_Pos = 0x0
	// Bit mask of TS1_RAMP_COEFF field.
	DTS_DTS_RAMPVALR_TS1_RAMP_COEFF_Msk = 0xffff

	// DTS_ITR1: DTS_ITR1 contains the threshold values for sensor 1.
	// Position of TS1_LITTHD field.
	DTS_DTS_ITR1_TS1_LITTHD_Pos = 0x0
	// Bit mask of TS1_LITTHD field.
	DTS_DTS_ITR1_TS1_LITTHD_Msk = 0xffff
	// Position of TS1_HITTHD field.
	DTS_DTS_ITR1_TS1_HITTHD_Pos = 0x10
	// Bit mask of TS1_HITTHD field.
	DTS_DTS_ITR1_TS1_HITTHD_Msk = 0xffff0000

	// DTS_DR: The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency.
	// Position of TS1_MFREQ field.
	DTS_DTS_DR_TS1_MFREQ_Pos = 0x0
	// Bit mask of TS1_MFREQ field.
	DTS_DTS_DR_TS1_MFREQ_Msk = 0xffff

	// DTS_SR: Temperature sensor status register
	// Position of TS1_ITEF field.
	DTS_DTS_SR_TS1_ITEF_Pos = 0x0
	// Bit mask of TS1_ITEF field.
	DTS_DTS_SR_TS1_ITEF_Msk = 0x1
	// Bit TS1_ITEF.
	DTS_DTS_SR_TS1_ITEF = 0x1
	// Position of TS1_ITLF field.
	DTS_DTS_SR_TS1_ITLF_Pos = 0x1
	// Bit mask of TS1_ITLF field.
	DTS_DTS_SR_TS1_ITLF_Msk = 0x2
	// Bit TS1_ITLF.
	DTS_DTS_SR_TS1_ITLF = 0x2
	// Position of TS1_ITHF field.
	DTS_DTS_SR_TS1_ITHF_Pos = 0x2
	// Bit mask of TS1_ITHF field.
	DTS_DTS_SR_TS1_ITHF_Msk = 0x4
	// Bit TS1_ITHF.
	DTS_DTS_SR_TS1_ITHF = 0x4
	// Position of TS1_AITEF field.
	DTS_DTS_SR_TS1_AITEF_Pos = 0x4
	// Bit mask of TS1_AITEF field.
	DTS_DTS_SR_TS1_AITEF_Msk = 0x10
	// Bit TS1_AITEF.
	DTS_DTS_SR_TS1_AITEF = 0x10
	// Position of TS1_AITLF field.
	DTS_DTS_SR_TS1_AITLF_Pos = 0x5
	// Bit mask of TS1_AITLF field.
	DTS_DTS_SR_TS1_AITLF_Msk = 0x20
	// Bit TS1_AITLF.
	DTS_DTS_SR_TS1_AITLF = 0x20
	// Position of TS1_AITHF field.
	DTS_DTS_SR_TS1_AITHF_Pos = 0x6
	// Bit mask of TS1_AITHF field.
	DTS_DTS_SR_TS1_AITHF_Msk = 0x40
	// Bit TS1_AITHF.
	DTS_DTS_SR_TS1_AITHF = 0x40
	// Position of TS1_RDY field.
	DTS_DTS_SR_TS1_RDY_Pos = 0xf
	// Bit mask of TS1_RDY field.
	DTS_DTS_SR_TS1_RDY_Msk = 0x8000
	// Bit TS1_RDY.
	DTS_DTS_SR_TS1_RDY = 0x8000

	// DTS_ITENR: Temperature sensor interrupt enable register
	// Position of TS1_ITEEN field.
	DTS_DTS_ITENR_TS1_ITEEN_Pos = 0x0
	// Bit mask of TS1_ITEEN field.
	DTS_DTS_ITENR_TS1_ITEEN_Msk = 0x1
	// Bit TS1_ITEEN.
	DTS_DTS_ITENR_TS1_ITEEN = 0x1
	// Position of TS1_ITLEN field.
	DTS_DTS_ITENR_TS1_ITLEN_Pos = 0x1
	// Bit mask of TS1_ITLEN field.
	DTS_DTS_ITENR_TS1_ITLEN_Msk = 0x2
	// Bit TS1_ITLEN.
	DTS_DTS_ITENR_TS1_ITLEN = 0x2
	// Position of TS1_ITHEN field.
	DTS_DTS_ITENR_TS1_ITHEN_Pos = 0x2
	// Bit mask of TS1_ITHEN field.
	DTS_DTS_ITENR_TS1_ITHEN_Msk = 0x4
	// Bit TS1_ITHEN.
	DTS_DTS_ITENR_TS1_ITHEN = 0x4
	// Position of TS1_AITEEN field.
	DTS_DTS_ITENR_TS1_AITEEN_Pos = 0x4
	// Bit mask of TS1_AITEEN field.
	DTS_DTS_ITENR_TS1_AITEEN_Msk = 0x10
	// Bit TS1_AITEEN.
	DTS_DTS_ITENR_TS1_AITEEN = 0x10
	// Position of TS1_AITLEN field.
	DTS_DTS_ITENR_TS1_AITLEN_Pos = 0x5
	// Bit mask of TS1_AITLEN field.
	DTS_DTS_ITENR_TS1_AITLEN_Msk = 0x20
	// Bit TS1_AITLEN.
	DTS_DTS_ITENR_TS1_AITLEN = 0x20
	// Position of TS1_AITHEN field.
	DTS_DTS_ITENR_TS1_AITHEN_Pos = 0x6
	// Bit mask of TS1_AITHEN field.
	DTS_DTS_ITENR_TS1_AITHEN_Msk = 0x40
	// Bit TS1_AITHEN.
	DTS_DTS_ITENR_TS1_AITHEN = 0x40

	// DTS_ICIFR: DTS_ICIFR is the control register for the interrupt flags.
	// Position of TS1_CITEF field.
	DTS_DTS_ICIFR_TS1_CITEF_Pos = 0x0
	// Bit mask of TS1_CITEF field.
	DTS_DTS_ICIFR_TS1_CITEF_Msk = 0x1
	// Bit TS1_CITEF.
	DTS_DTS_ICIFR_TS1_CITEF = 0x1
	// Position of TS1_CITLF field.
	DTS_DTS_ICIFR_TS1_CITLF_Pos = 0x1
	// Bit mask of TS1_CITLF field.
	DTS_DTS_ICIFR_TS1_CITLF_Msk = 0x2
	// Bit TS1_CITLF.
	DTS_DTS_ICIFR_TS1_CITLF = 0x2
	// Position of TS1_CITHF field.
	DTS_DTS_ICIFR_TS1_CITHF_Pos = 0x2
	// Bit mask of TS1_CITHF field.
	DTS_DTS_ICIFR_TS1_CITHF_Msk = 0x4
	// Bit TS1_CITHF.
	DTS_DTS_ICIFR_TS1_CITHF = 0x4
	// Position of TS1_CAITEF field.
	DTS_DTS_ICIFR_TS1_CAITEF_Pos = 0x4
	// Bit mask of TS1_CAITEF field.
	DTS_DTS_ICIFR_TS1_CAITEF_Msk = 0x10
	// Bit TS1_CAITEF.
	DTS_DTS_ICIFR_TS1_CAITEF = 0x10
	// Position of TS1_CAITLF field.
	DTS_DTS_ICIFR_TS1_CAITLF_Pos = 0x5
	// Bit mask of TS1_CAITLF field.
	DTS_DTS_ICIFR_TS1_CAITLF_Msk = 0x20
	// Bit TS1_CAITLF.
	DTS_DTS_ICIFR_TS1_CAITLF = 0x20
	// Position of TS1_CAITHF field.
	DTS_DTS_ICIFR_TS1_CAITHF_Pos = 0x6
	// Bit mask of TS1_CAITHF field.
	DTS_DTS_ICIFR_TS1_CAITHF_Msk = 0x40
	// Bit TS1_CAITHF.
	DTS_DTS_ICIFR_TS1_CAITHF = 0x40

	// DTS_OR: The DTS_OR contains general-purpose option bits.
	// Position of TS_Op0 field.
	DTS_DTS_OR_TS_Op0_Pos = 0x0
	// Bit mask of TS_Op0 field.
	DTS_DTS_OR_TS_Op0_Msk = 0x1
	// Bit TS_Op0.
	DTS_DTS_OR_TS_Op0 = 0x1
	// Position of TS_Op1 field.
	DTS_DTS_OR_TS_Op1_Pos = 0x1
	// Bit mask of TS_Op1 field.
	DTS_DTS_OR_TS_Op1_Msk = 0x2
	// Bit TS_Op1.
	DTS_DTS_OR_TS_Op1 = 0x2
	// Position of TS_Op2 field.
	DTS_DTS_OR_TS_Op2_Pos = 0x2
	// Bit mask of TS_Op2 field.
	DTS_DTS_OR_TS_Op2_Msk = 0x4
	// Bit TS_Op2.
	DTS_DTS_OR_TS_Op2 = 0x4
	// Position of TS_Op3 field.
	DTS_DTS_OR_TS_Op3_Pos = 0x3
	// Bit mask of TS_Op3 field.
	DTS_DTS_OR_TS_Op3_Msk = 0x8
	// Bit TS_Op3.
	DTS_DTS_OR_TS_Op3 = 0x8
	// Position of TS_Op4 field.
	DTS_DTS_OR_TS_Op4_Pos = 0x4
	// Bit mask of TS_Op4 field.
	DTS_DTS_OR_TS_Op4_Msk = 0x10
	// Bit TS_Op4.
	DTS_DTS_OR_TS_Op4 = 0x10
	// Position of TS_Op5 field.
	DTS_DTS_OR_TS_Op5_Pos = 0x5
	// Bit mask of TS_Op5 field.
	DTS_DTS_OR_TS_Op5_Msk = 0x20
	// Bit TS_Op5.
	DTS_DTS_OR_TS_Op5 = 0x20
	// Position of TS_Op6 field.
	DTS_DTS_OR_TS_Op6_Pos = 0x6
	// Bit mask of TS_Op6 field.
	DTS_DTS_OR_TS_Op6_Msk = 0x40
	// Bit TS_Op6.
	DTS_DTS_OR_TS_Op6 = 0x40
	// Position of TS_Op7 field.
	DTS_DTS_OR_TS_Op7_Pos = 0x7
	// Bit mask of TS_Op7 field.
	DTS_DTS_OR_TS_Op7_Msk = 0x80
	// Bit TS_Op7.
	DTS_DTS_OR_TS_Op7 = 0x80
	// Position of TS_Op8 field.
	DTS_DTS_OR_TS_Op8_Pos = 0x8
	// Bit mask of TS_Op8 field.
	DTS_DTS_OR_TS_Op8_Msk = 0x100
	// Bit TS_Op8.
	DTS_DTS_OR_TS_Op8 = 0x100
	// Position of TS_Op9 field.
	DTS_DTS_OR_TS_Op9_Pos = 0x9
	// Bit mask of TS_Op9 field.
	DTS_DTS_OR_TS_Op9_Msk = 0x200
	// Bit TS_Op9.
	DTS_DTS_OR_TS_Op9 = 0x200
	// Position of TS_Op10 field.
	DTS_DTS_OR_TS_Op10_Pos = 0xa
	// Bit mask of TS_Op10 field.
	DTS_DTS_OR_TS_Op10_Msk = 0x400
	// Bit TS_Op10.
	DTS_DTS_OR_TS_Op10 = 0x400
	// Position of TS_Op11 field.
	DTS_DTS_OR_TS_Op11_Pos = 0xb
	// Bit mask of TS_Op11 field.
	DTS_DTS_OR_TS_Op11_Msk = 0x800
	// Bit TS_Op11.
	DTS_DTS_OR_TS_Op11 = 0x800
	// Position of TS_Op12 field.
	DTS_DTS_OR_TS_Op12_Pos = 0xc
	// Bit mask of TS_Op12 field.
	DTS_DTS_OR_TS_Op12_Msk = 0x1000
	// Bit TS_Op12.
	DTS_DTS_OR_TS_Op12 = 0x1000
	// Position of TS_Op13 field.
	DTS_DTS_OR_TS_Op13_Pos = 0xd
	// Bit mask of TS_Op13 field.
	DTS_DTS_OR_TS_Op13_Msk = 0x2000
	// Bit TS_Op13.
	DTS_DTS_OR_TS_Op13 = 0x2000
	// Position of TS_Op14 field.
	DTS_DTS_OR_TS_Op14_Pos = 0xe
	// Bit mask of TS_Op14 field.
	DTS_DTS_OR_TS_Op14_Msk = 0x4000
	// Bit TS_Op14.
	DTS_DTS_OR_TS_Op14 = 0x4000
	// Position of TS_Op15 field.
	DTS_DTS_OR_TS_Op15_Pos = 0xf
	// Bit mask of TS_Op15 field.
	DTS_DTS_OR_TS_Op15_Msk = 0x8000
	// Bit TS_Op15.
	DTS_DTS_OR_TS_Op15 = 0x8000
	// Position of TS_Op16 field.
	DTS_DTS_OR_TS_Op16_Pos = 0x10
	// Bit mask of TS_Op16 field.
	DTS_DTS_OR_TS_Op16_Msk = 0x10000
	// Bit TS_Op16.
	DTS_DTS_OR_TS_Op16 = 0x10000
	// Position of TS_Op17 field.
	DTS_DTS_OR_TS_Op17_Pos = 0x11
	// Bit mask of TS_Op17 field.
	DTS_DTS_OR_TS_Op17_Msk = 0x20000
	// Bit TS_Op17.
	DTS_DTS_OR_TS_Op17 = 0x20000
	// Position of TS_Op18 field.
	DTS_DTS_OR_TS_Op18_Pos = 0x12
	// Bit mask of TS_Op18 field.
	DTS_DTS_OR_TS_Op18_Msk = 0x40000
	// Bit TS_Op18.
	DTS_DTS_OR_TS_Op18 = 0x40000
	// Position of TS_Op19 field.
	DTS_DTS_OR_TS_Op19_Pos = 0x13
	// Bit mask of TS_Op19 field.
	DTS_DTS_OR_TS_Op19_Msk = 0x80000
	// Bit TS_Op19.
	DTS_DTS_OR_TS_Op19 = 0x80000
	// Position of TS_Op20 field.
	DTS_DTS_OR_TS_Op20_Pos = 0x14
	// Bit mask of TS_Op20 field.
	DTS_DTS_OR_TS_Op20_Msk = 0x100000
	// Bit TS_Op20.
	DTS_DTS_OR_TS_Op20 = 0x100000
	// Position of TS_Op21 field.
	DTS_DTS_OR_TS_Op21_Pos = 0x15
	// Bit mask of TS_Op21 field.
	DTS_DTS_OR_TS_Op21_Msk = 0x200000
	// Bit TS_Op21.
	DTS_DTS_OR_TS_Op21 = 0x200000
	// Position of TS_Op22 field.
	DTS_DTS_OR_TS_Op22_Pos = 0x16
	// Bit mask of TS_Op22 field.
	DTS_DTS_OR_TS_Op22_Msk = 0x400000
	// Bit TS_Op22.
	DTS_DTS_OR_TS_Op22 = 0x400000
	// Position of TS_Op23 field.
	DTS_DTS_OR_TS_Op23_Pos = 0x17
	// Bit mask of TS_Op23 field.
	DTS_DTS_OR_TS_Op23_Msk = 0x800000
	// Bit TS_Op23.
	DTS_DTS_OR_TS_Op23 = 0x800000
	// Position of TS_Op24 field.
	DTS_DTS_OR_TS_Op24_Pos = 0x18
	// Bit mask of TS_Op24 field.
	DTS_DTS_OR_TS_Op24_Msk = 0x1000000
	// Bit TS_Op24.
	DTS_DTS_OR_TS_Op24 = 0x1000000
	// Position of TS_Op25 field.
	DTS_DTS_OR_TS_Op25_Pos = 0x19
	// Bit mask of TS_Op25 field.
	DTS_DTS_OR_TS_Op25_Msk = 0x2000000
	// Bit TS_Op25.
	DTS_DTS_OR_TS_Op25 = 0x2000000
	// Position of TS_Op26 field.
	DTS_DTS_OR_TS_Op26_Pos = 0x1a
	// Bit mask of TS_Op26 field.
	DTS_DTS_OR_TS_Op26_Msk = 0x4000000
	// Bit TS_Op26.
	DTS_DTS_OR_TS_Op26 = 0x4000000
	// Position of TS_Op27 field.
	DTS_DTS_OR_TS_Op27_Pos = 0x1b
	// Bit mask of TS_Op27 field.
	DTS_DTS_OR_TS_Op27_Msk = 0x8000000
	// Bit TS_Op27.
	DTS_DTS_OR_TS_Op27 = 0x8000000
	// Position of TS_Op28 field.
	DTS_DTS_OR_TS_Op28_Pos = 0x1c
	// Bit mask of TS_Op28 field.
	DTS_DTS_OR_TS_Op28_Msk = 0x10000000
	// Bit TS_Op28.
	DTS_DTS_OR_TS_Op28 = 0x10000000
	// Position of TS_Op29 field.
	DTS_DTS_OR_TS_Op29_Pos = 0x1d
	// Bit mask of TS_Op29 field.
	DTS_DTS_OR_TS_Op29_Msk = 0x20000000
	// Bit TS_Op29.
	DTS_DTS_OR_TS_Op29 = 0x20000000
	// Position of TS_Op30 field.
	DTS_DTS_OR_TS_Op30_Pos = 0x1e
	// Bit mask of TS_Op30 field.
	DTS_DTS_OR_TS_Op30_Msk = 0x40000000
	// Bit TS_Op30.
	DTS_DTS_OR_TS_Op30 = 0x40000000
	// Position of TS_Op31 field.
	DTS_DTS_OR_TS_Op31_Pos = 0x1f
	// Bit mask of TS_Op31 field.
	DTS_DTS_OR_TS_Op31_Msk = 0x80000000
	// Bit TS_Op31.
	DTS_DTS_OR_TS_Op31 = 0x80000000
)

// Bitfields for ETH_MAC_MMC: ETH_MAC_MMC
const (
	// ETH_MACCR: The MAC Configuration Register establishes the operating mode of the MAC.
	// Position of RE field.
	Ethernet_ETH_MACCR_RE_Pos = 0x0
	// Bit mask of RE field.
	Ethernet_ETH_MACCR_RE_Msk = 0x1
	// Bit RE.
	Ethernet_ETH_MACCR_RE = 0x1
	// Position of TE field.
	Ethernet_ETH_MACCR_TE_Pos = 0x1
	// Bit mask of TE field.
	Ethernet_ETH_MACCR_TE_Msk = 0x2
	// Bit TE.
	Ethernet_ETH_MACCR_TE = 0x2
	// Position of PRELEN field.
	Ethernet_ETH_MACCR_PRELEN_Pos = 0x2
	// Bit mask of PRELEN field.
	Ethernet_ETH_MACCR_PRELEN_Msk = 0xc
	// Position of DC field.
	Ethernet_ETH_MACCR_DC_Pos = 0x4
	// Bit mask of DC field.
	Ethernet_ETH_MACCR_DC_Msk = 0x10
	// Bit DC.
	Ethernet_ETH_MACCR_DC = 0x10
	// Position of BL field.
	Ethernet_ETH_MACCR_BL_Pos = 0x5
	// Bit mask of BL field.
	Ethernet_ETH_MACCR_BL_Msk = 0x60
	// Position of DR field.
	Ethernet_ETH_MACCR_DR_Pos = 0x8
	// Bit mask of DR field.
	Ethernet_ETH_MACCR_DR_Msk = 0x100
	// Bit DR.
	Ethernet_ETH_MACCR_DR = 0x100
	// Position of DCRS field.
	Ethernet_ETH_MACCR_DCRS_Pos = 0x9
	// Bit mask of DCRS field.
	Ethernet_ETH_MACCR_DCRS_Msk = 0x200
	// Bit DCRS.
	Ethernet_ETH_MACCR_DCRS = 0x200
	// Position of DO field.
	Ethernet_ETH_MACCR_DO_Pos = 0xa
	// Bit mask of DO field.
	Ethernet_ETH_MACCR_DO_Msk = 0x400
	// Bit DO.
	Ethernet_ETH_MACCR_DO = 0x400
	// Position of ECRSFD field.
	Ethernet_ETH_MACCR_ECRSFD_Pos = 0xb
	// Bit mask of ECRSFD field.
	Ethernet_ETH_MACCR_ECRSFD_Msk = 0x800
	// Bit ECRSFD.
	Ethernet_ETH_MACCR_ECRSFD = 0x800
	// Position of LM field.
	Ethernet_ETH_MACCR_LM_Pos = 0xc
	// Bit mask of LM field.
	Ethernet_ETH_MACCR_LM_Msk = 0x1000
	// Bit LM.
	Ethernet_ETH_MACCR_LM = 0x1000
	// Position of DM field.
	Ethernet_ETH_MACCR_DM_Pos = 0xd
	// Bit mask of DM field.
	Ethernet_ETH_MACCR_DM_Msk = 0x2000
	// Bit DM.
	Ethernet_ETH_MACCR_DM = 0x2000
	// Position of FES field.
	Ethernet_ETH_MACCR_FES_Pos = 0xe
	// Bit mask of FES field.
	Ethernet_ETH_MACCR_FES_Msk = 0x4000
	// Bit FES.
	Ethernet_ETH_MACCR_FES = 0x4000
	// Position of PS field.
	Ethernet_ETH_MACCR_PS_Pos = 0xf
	// Bit mask of PS field.
	Ethernet_ETH_MACCR_PS_Msk = 0x8000
	// Bit PS.
	Ethernet_ETH_MACCR_PS = 0x8000
	// Position of JE field.
	Ethernet_ETH_MACCR_JE_Pos = 0x10
	// Bit mask of JE field.
	Ethernet_ETH_MACCR_JE_Msk = 0x10000
	// Bit JE.
	Ethernet_ETH_MACCR_JE = 0x10000
	// Position of JD field.
	Ethernet_ETH_MACCR_JD_Pos = 0x11
	// Bit mask of JD field.
	Ethernet_ETH_MACCR_JD_Msk = 0x20000
	// Bit JD.
	Ethernet_ETH_MACCR_JD = 0x20000
	// Position of BE field.
	Ethernet_ETH_MACCR_BE_Pos = 0x12
	// Bit mask of BE field.
	Ethernet_ETH_MACCR_BE_Msk = 0x40000
	// Bit BE.
	Ethernet_ETH_MACCR_BE = 0x40000
	// Position of WD field.
	Ethernet_ETH_MACCR_WD_Pos = 0x13
	// Bit mask of WD field.
	Ethernet_ETH_MACCR_WD_Msk = 0x80000
	// Bit WD.
	Ethernet_ETH_MACCR_WD = 0x80000
	// Position of ACS field.
	Ethernet_ETH_MACCR_ACS_Pos = 0x14
	// Bit mask of ACS field.
	Ethernet_ETH_MACCR_ACS_Msk = 0x100000
	// Bit ACS.
	Ethernet_ETH_MACCR_ACS = 0x100000
	// Position of CST field.
	Ethernet_ETH_MACCR_CST_Pos = 0x15
	// Bit mask of CST field.
	Ethernet_ETH_MACCR_CST_Msk = 0x200000
	// Bit CST.
	Ethernet_ETH_MACCR_CST = 0x200000
	// Position of S2KP field.
	Ethernet_ETH_MACCR_S2KP_Pos = 0x16
	// Bit mask of S2KP field.
	Ethernet_ETH_MACCR_S2KP_Msk = 0x400000
	// Bit S2KP.
	Ethernet_ETH_MACCR_S2KP = 0x400000
	// Position of GPSLCE field.
	Ethernet_ETH_MACCR_GPSLCE_Pos = 0x17
	// Bit mask of GPSLCE field.
	Ethernet_ETH_MACCR_GPSLCE_Msk = 0x800000
	// Bit GPSLCE.
	Ethernet_ETH_MACCR_GPSLCE = 0x800000
	// Position of IPG field.
	Ethernet_ETH_MACCR_IPG_Pos = 0x18
	// Bit mask of IPG field.
	Ethernet_ETH_MACCR_IPG_Msk = 0x7000000
	// Position of IPC field.
	Ethernet_ETH_MACCR_IPC_Pos = 0x1b
	// Bit mask of IPC field.
	Ethernet_ETH_MACCR_IPC_Msk = 0x8000000
	// Bit IPC.
	Ethernet_ETH_MACCR_IPC = 0x8000000
	// Position of SARC field.
	Ethernet_ETH_MACCR_SARC_Pos = 0x1c
	// Bit mask of SARC field.
	Ethernet_ETH_MACCR_SARC_Msk = 0x70000000
	// Position of ARPEN field.
	Ethernet_ETH_MACCR_ARPEN_Pos = 0x1f
	// Bit mask of ARPEN field.
	Ethernet_ETH_MACCR_ARPEN_Msk = 0x80000000
	// Bit ARPEN.
	Ethernet_ETH_MACCR_ARPEN = 0x80000000

	// ETH_MACECR: The MAC Extended Configuration Register establishes the operating mode of the MAC.
	// Position of GPSL field.
	Ethernet_ETH_MACECR_GPSL_Pos = 0x0
	// Bit mask of GPSL field.
	Ethernet_ETH_MACECR_GPSL_Msk = 0x3fff
	// Position of DCRCC field.
	Ethernet_ETH_MACECR_DCRCC_Pos = 0x10
	// Bit mask of DCRCC field.
	Ethernet_ETH_MACECR_DCRCC_Msk = 0x10000
	// Bit DCRCC.
	Ethernet_ETH_MACECR_DCRCC = 0x10000
	// Position of SPEN field.
	Ethernet_ETH_MACECR_SPEN_Pos = 0x11
	// Bit mask of SPEN field.
	Ethernet_ETH_MACECR_SPEN_Msk = 0x20000
	// Bit SPEN.
	Ethernet_ETH_MACECR_SPEN = 0x20000
	// Position of USP field.
	Ethernet_ETH_MACECR_USP_Pos = 0x12
	// Bit mask of USP field.
	Ethernet_ETH_MACECR_USP_Msk = 0x40000
	// Bit USP.
	Ethernet_ETH_MACECR_USP = 0x40000
	// Position of EIPGEN field.
	Ethernet_ETH_MACECR_EIPGEN_Pos = 0x18
	// Bit mask of EIPGEN field.
	Ethernet_ETH_MACECR_EIPGEN_Msk = 0x1000000
	// Bit EIPGEN.
	Ethernet_ETH_MACECR_EIPGEN = 0x1000000
	// Position of EIPG field.
	Ethernet_ETH_MACECR_EIPG_Pos = 0x19
	// Bit mask of EIPG field.
	Ethernet_ETH_MACECR_EIPG_Msk = 0x3e000000

	// ETH_MACPFR: The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets.
	// Position of PR field.
	Ethernet_ETH_MACPFR_PR_Pos = 0x0
	// Bit mask of PR field.
	Ethernet_ETH_MACPFR_PR_Msk = 0x1
	// Bit PR.
	Ethernet_ETH_MACPFR_PR = 0x1
	// Position of HUC field.
	Ethernet_ETH_MACPFR_HUC_Pos = 0x1
	// Bit mask of HUC field.
	Ethernet_ETH_MACPFR_HUC_Msk = 0x2
	// Bit HUC.
	Ethernet_ETH_MACPFR_HUC = 0x2
	// Position of HMC field.
	Ethernet_ETH_MACPFR_HMC_Pos = 0x2
	// Bit mask of HMC field.
	Ethernet_ETH_MACPFR_HMC_Msk = 0x4
	// Bit HMC.
	Ethernet_ETH_MACPFR_HMC = 0x4
	// Position of DAIF field.
	Ethernet_ETH_MACPFR_DAIF_Pos = 0x3
	// Bit mask of DAIF field.
	Ethernet_ETH_MACPFR_DAIF_Msk = 0x8
	// Bit DAIF.
	Ethernet_ETH_MACPFR_DAIF = 0x8
	// Position of PM field.
	Ethernet_ETH_MACPFR_PM_Pos = 0x4
	// Bit mask of PM field.
	Ethernet_ETH_MACPFR_PM_Msk = 0x10
	// Bit PM.
	Ethernet_ETH_MACPFR_PM = 0x10
	// Position of DBF field.
	Ethernet_ETH_MACPFR_DBF_Pos = 0x5
	// Bit mask of DBF field.
	Ethernet_ETH_MACPFR_DBF_Msk = 0x20
	// Bit DBF.
	Ethernet_ETH_MACPFR_DBF = 0x20
	// Position of PCF field.
	Ethernet_ETH_MACPFR_PCF_Pos = 0x6
	// Bit mask of PCF field.
	Ethernet_ETH_MACPFR_PCF_Msk = 0xc0
	// Position of SAIF field.
	Ethernet_ETH_MACPFR_SAIF_Pos = 0x8
	// Bit mask of SAIF field.
	Ethernet_ETH_MACPFR_SAIF_Msk = 0x100
	// Bit SAIF.
	Ethernet_ETH_MACPFR_SAIF = 0x100
	// Position of SAF field.
	Ethernet_ETH_MACPFR_SAF_Pos = 0x9
	// Bit mask of SAF field.
	Ethernet_ETH_MACPFR_SAF_Msk = 0x200
	// Bit SAF.
	Ethernet_ETH_MACPFR_SAF = 0x200
	// Position of HPF field.
	Ethernet_ETH_MACPFR_HPF_Pos = 0xa
	// Bit mask of HPF field.
	Ethernet_ETH_MACPFR_HPF_Msk = 0x400
	// Bit HPF.
	Ethernet_ETH_MACPFR_HPF = 0x400
	// Position of VTFE field.
	Ethernet_ETH_MACPFR_VTFE_Pos = 0x10
	// Bit mask of VTFE field.
	Ethernet_ETH_MACPFR_VTFE_Msk = 0x10000
	// Bit VTFE.
	Ethernet_ETH_MACPFR_VTFE = 0x10000
	// Position of IPFE field.
	Ethernet_ETH_MACPFR_IPFE_Pos = 0x14
	// Bit mask of IPFE field.
	Ethernet_ETH_MACPFR_IPFE_Msk = 0x100000
	// Bit IPFE.
	Ethernet_ETH_MACPFR_IPFE = 0x100000
	// Position of DNTU field.
	Ethernet_ETH_MACPFR_DNTU_Pos = 0x15
	// Bit mask of DNTU field.
	Ethernet_ETH_MACPFR_DNTU_Msk = 0x200000
	// Bit DNTU.
	Ethernet_ETH_MACPFR_DNTU = 0x200000
	// Position of RA field.
	Ethernet_ETH_MACPFR_RA_Pos = 0x1f
	// Bit mask of RA field.
	Ethernet_ETH_MACPFR_RA_Msk = 0x80000000
	// Bit RA.
	Ethernet_ETH_MACPFR_RA = 0x80000000

	// ETH_MACWTR: The Watchdog Timeout register controls the watchdog timeout for received packets.
	// Position of WTO field.
	Ethernet_ETH_MACWTR_WTO_Pos = 0x0
	// Bit mask of WTO field.
	Ethernet_ETH_MACWTR_WTO_Msk = 0xf
	// Position of PWE field.
	Ethernet_ETH_MACWTR_PWE_Pos = 0x8
	// Bit mask of PWE field.
	Ethernet_ETH_MACWTR_PWE_Msk = 0x100
	// Bit PWE.
	Ethernet_ETH_MACWTR_PWE = 0x100

	// ETH_MACHT0R: The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
	// Position of HT31T0 field.
	Ethernet_ETH_MACHT0R_HT31T0_Pos = 0x0
	// Bit mask of HT31T0 field.
	Ethernet_ETH_MACHT0R_HT31T0_Msk = 0xffffffff

	// ETH_MACHT1R: The Hash Table Register 1contains the last 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
	// Position of HT63T32 field.
	Ethernet_ETH_MACHT1R_HT63T32_Pos = 0x0
	// Bit mask of HT63T32 field.
	Ethernet_ETH_MACHT1R_HT63T32_Msk = 0xffffffff

	// ETH_MACVTR: The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets.
	// Position of VL field.
	Ethernet_ETH_MACVTR_VL_Pos = 0x0
	// Bit mask of VL field.
	Ethernet_ETH_MACVTR_VL_Msk = 0xffff
	// Position of ETV field.
	Ethernet_ETH_MACVTR_ETV_Pos = 0x10
	// Bit mask of ETV field.
	Ethernet_ETH_MACVTR_ETV_Msk = 0x10000
	// Bit ETV.
	Ethernet_ETH_MACVTR_ETV = 0x10000
	// Position of VTIM field.
	Ethernet_ETH_MACVTR_VTIM_Pos = 0x11
	// Bit mask of VTIM field.
	Ethernet_ETH_MACVTR_VTIM_Msk = 0x20000
	// Bit VTIM.
	Ethernet_ETH_MACVTR_VTIM = 0x20000
	// Position of ESVL field.
	Ethernet_ETH_MACVTR_ESVL_Pos = 0x12
	// Bit mask of ESVL field.
	Ethernet_ETH_MACVTR_ESVL_Msk = 0x40000
	// Bit ESVL.
	Ethernet_ETH_MACVTR_ESVL = 0x40000
	// Position of ERSVLM field.
	Ethernet_ETH_MACVTR_ERSVLM_Pos = 0x13
	// Bit mask of ERSVLM field.
	Ethernet_ETH_MACVTR_ERSVLM_Msk = 0x80000
	// Bit ERSVLM.
	Ethernet_ETH_MACVTR_ERSVLM = 0x80000
	// Position of DOVLTC field.
	Ethernet_ETH_MACVTR_DOVLTC_Pos = 0x14
	// Bit mask of DOVLTC field.
	Ethernet_ETH_MACVTR_DOVLTC_Msk = 0x100000
	// Bit DOVLTC.
	Ethernet_ETH_MACVTR_DOVLTC = 0x100000
	// Position of EVLS field.
	Ethernet_ETH_MACVTR_EVLS_Pos = 0x15
	// Bit mask of EVLS field.
	Ethernet_ETH_MACVTR_EVLS_Msk = 0x600000
	// Position of EVLRXS field.
	Ethernet_ETH_MACVTR_EVLRXS_Pos = 0x18
	// Bit mask of EVLRXS field.
	Ethernet_ETH_MACVTR_EVLRXS_Msk = 0x1000000
	// Bit EVLRXS.
	Ethernet_ETH_MACVTR_EVLRXS = 0x1000000
	// Position of VTHM field.
	Ethernet_ETH_MACVTR_VTHM_Pos = 0x19
	// Bit mask of VTHM field.
	Ethernet_ETH_MACVTR_VTHM_Msk = 0x2000000
	// Bit VTHM.
	Ethernet_ETH_MACVTR_VTHM = 0x2000000
	// Position of EDVLP field.
	Ethernet_ETH_MACVTR_EDVLP_Pos = 0x1a
	// Bit mask of EDVLP field.
	Ethernet_ETH_MACVTR_EDVLP_Msk = 0x4000000
	// Bit EDVLP.
	Ethernet_ETH_MACVTR_EDVLP = 0x4000000
	// Position of ERIVLT field.
	Ethernet_ETH_MACVTR_ERIVLT_Pos = 0x1b
	// Bit mask of ERIVLT field.
	Ethernet_ETH_MACVTR_ERIVLT_Msk = 0x8000000
	// Bit ERIVLT.
	Ethernet_ETH_MACVTR_ERIVLT = 0x8000000
	// Position of EIVLS field.
	Ethernet_ETH_MACVTR_EIVLS_Pos = 0x1c
	// Bit mask of EIVLS field.
	Ethernet_ETH_MACVTR_EIVLS_Msk = 0x30000000
	// Position of EIVLRXS field.
	Ethernet_ETH_MACVTR_EIVLRXS_Pos = 0x1f
	// Bit mask of EIVLRXS field.
	Ethernet_ETH_MACVTR_EIVLRXS_Msk = 0x80000000
	// Bit EIVLRXS.
	Ethernet_ETH_MACVTR_EIVLRXS = 0x80000000

	// ETH_MACVHTR: When the ERSVLM bit of ETH_MACHT1R register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For Hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of ETH_MACVTR register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of 1000 selects Bit 8 of the VLAN Hash table. The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3). Perform bitwise reversal for the value obtained in step 1. Take the upper four bits from the value obtained in step 2. If the VLAN Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written.
	// Position of VLHT field.
	Ethernet_ETH_MACVHTR_VLHT_Pos = 0x0
	// Bit mask of VLHT field.
	Ethernet_ETH_MACVHTR_VLHT_Msk = 0xffff

	// ETH_MACVIR: The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls.
	// Position of VLT field.
	Ethernet_ETH_MACVIR_VLT_Pos = 0x0
	// Bit mask of VLT field.
	Ethernet_ETH_MACVIR_VLT_Msk = 0xffff
	// Position of VLC field.
	Ethernet_ETH_MACVIR_VLC_Pos = 0x10
	// Bit mask of VLC field.
	Ethernet_ETH_MACVIR_VLC_Msk = 0x30000
	// Position of VLP field.
	Ethernet_ETH_MACVIR_VLP_Pos = 0x12
	// Bit mask of VLP field.
	Ethernet_ETH_MACVIR_VLP_Msk = 0x40000
	// Bit VLP.
	Ethernet_ETH_MACVIR_VLP = 0x40000
	// Position of CSVL field.
	Ethernet_ETH_MACVIR_CSVL_Pos = 0x13
	// Bit mask of CSVL field.
	Ethernet_ETH_MACVIR_CSVL_Msk = 0x80000
	// Bit CSVL.
	Ethernet_ETH_MACVIR_CSVL = 0x80000
	// Position of VLTI field.
	Ethernet_ETH_MACVIR_VLTI_Pos = 0x14
	// Bit mask of VLTI field.
	Ethernet_ETH_MACVIR_VLTI_Msk = 0x100000
	// Bit VLTI.
	Ethernet_ETH_MACVIR_VLTI = 0x100000

	// ETH_MACIVIR: The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls.
	// Position of VLT field.
	Ethernet_ETH_MACIVIR_VLT_Pos = 0x0
	// Bit mask of VLT field.
	Ethernet_ETH_MACIVIR_VLT_Msk = 0xffff
	// Position of VLC field.
	Ethernet_ETH_MACIVIR_VLC_Pos = 0x10
	// Bit mask of VLC field.
	Ethernet_ETH_MACIVIR_VLC_Msk = 0x30000
	// Position of VLP field.
	Ethernet_ETH_MACIVIR_VLP_Pos = 0x12
	// Bit mask of VLP field.
	Ethernet_ETH_MACIVIR_VLP_Msk = 0x40000
	// Bit VLP.
	Ethernet_ETH_MACIVIR_VLP = 0x40000
	// Position of CSVL field.
	Ethernet_ETH_MACIVIR_CSVL_Pos = 0x13
	// Bit mask of CSVL field.
	Ethernet_ETH_MACIVIR_CSVL_Msk = 0x80000
	// Bit CSVL.
	Ethernet_ETH_MACIVIR_CSVL = 0x80000
	// Position of VLTI field.
	Ethernet_ETH_MACIVIR_VLTI_Pos = 0x14
	// Bit mask of VLTI field.
	Ethernet_ETH_MACIVIR_VLTI_Msk = 0x100000
	// Bit VLTI.
	Ethernet_ETH_MACIVIR_VLTI = 0x100000

	// ETH_MACQ0TxFCR: The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register.
	// Position of FCB_BPA field.
	Ethernet_ETH_MACQ0TxFCR_FCB_BPA_Pos = 0x0
	// Bit mask of FCB_BPA field.
	Ethernet_ETH_MACQ0TxFCR_FCB_BPA_Msk = 0x1
	// Bit FCB_BPA.
	Ethernet_ETH_MACQ0TxFCR_FCB_BPA = 0x1
	// Position of TFE field.
	Ethernet_ETH_MACQ0TxFCR_TFE_Pos = 0x1
	// Bit mask of TFE field.
	Ethernet_ETH_MACQ0TxFCR_TFE_Msk = 0x2
	// Bit TFE.
	Ethernet_ETH_MACQ0TxFCR_TFE = 0x2
	// Position of PLT field.
	Ethernet_ETH_MACQ0TxFCR_PLT_Pos = 0x4
	// Bit mask of PLT field.
	Ethernet_ETH_MACQ0TxFCR_PLT_Msk = 0x70
	// Position of DZPQ field.
	Ethernet_ETH_MACQ0TxFCR_DZPQ_Pos = 0x7
	// Bit mask of DZPQ field.
	Ethernet_ETH_MACQ0TxFCR_DZPQ_Msk = 0x80
	// Bit DZPQ.
	Ethernet_ETH_MACQ0TxFCR_DZPQ = 0x80
	// Position of PT field.
	Ethernet_ETH_MACQ0TxFCR_PT_Pos = 0x10
	// Bit mask of PT field.
	Ethernet_ETH_MACQ0TxFCR_PT_Msk = 0xffff0000

	// ETH_MACRxFCR: The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet.
	// Position of RFE field.
	Ethernet_ETH_MACRxFCR_RFE_Pos = 0x0
	// Bit mask of RFE field.
	Ethernet_ETH_MACRxFCR_RFE_Msk = 0x1
	// Bit RFE.
	Ethernet_ETH_MACRxFCR_RFE = 0x1
	// Position of UP field.
	Ethernet_ETH_MACRxFCR_UP_Pos = 0x1
	// Bit mask of UP field.
	Ethernet_ETH_MACRxFCR_UP_Msk = 0x2
	// Bit UP.
	Ethernet_ETH_MACRxFCR_UP = 0x2

	// ETH_MACTxQPMR: The transmit queue priority mapping 0 register contains the priority values assigned to Tx queue 0 and tx queue 1.
	// Position of PSTQ0 field.
	Ethernet_ETH_MACTxQPMR_PSTQ0_Pos = 0x0
	// Bit mask of PSTQ0 field.
	Ethernet_ETH_MACTxQPMR_PSTQ0_Msk = 0xff
	// Position of PSTQ1 field.
	Ethernet_ETH_MACTxQPMR_PSTQ1_Pos = 0x8
	// Bit mask of PSTQ1 field.
	Ethernet_ETH_MACTxQPMR_PSTQ1_Msk = 0xff00

	// ETH_MACRxQC0R: The Receive Queue Control 0 register controls the queue management in the MAC Receiver.
	// Position of RXQ0EN field.
	Ethernet_ETH_MACRxQC0R_RXQ0EN_Pos = 0x0
	// Bit mask of RXQ0EN field.
	Ethernet_ETH_MACRxQC0R_RXQ0EN_Msk = 0x3
	// Position of RXQ1EN field.
	Ethernet_ETH_MACRxQC0R_RXQ1EN_Pos = 0x2
	// Bit mask of RXQ1EN field.
	Ethernet_ETH_MACRxQC0R_RXQ1EN_Msk = 0xc

	// ETH_MACRxQC1R: The Receive Queue Control 1 register controls queue 1 management in the MAC receiver.
	// Position of AVCPQ field.
	Ethernet_ETH_MACRxQC1R_AVCPQ_Pos = 0x0
	// Bit mask of AVCPQ field.
	Ethernet_ETH_MACRxQC1R_AVCPQ_Msk = 0x7
	// Position of AVPTPQ field.
	Ethernet_ETH_MACRxQC1R_AVPTPQ_Pos = 0x4
	// Bit mask of AVPTPQ field.
	Ethernet_ETH_MACRxQC1R_AVPTPQ_Msk = 0x70
	// Position of UPQ field.
	Ethernet_ETH_MACRxQC1R_UPQ_Pos = 0xc
	// Bit mask of UPQ field.
	Ethernet_ETH_MACRxQC1R_UPQ_Msk = 0x7000
	// Position of MCBCQ field.
	Ethernet_ETH_MACRxQC1R_MCBCQ_Pos = 0x10
	// Bit mask of MCBCQ field.
	Ethernet_ETH_MACRxQC1R_MCBCQ_Msk = 0x70000
	// Position of MCBCQEN field.
	Ethernet_ETH_MACRxQC1R_MCBCQEN_Pos = 0x14
	// Bit mask of MCBCQEN field.
	Ethernet_ETH_MACRxQC1R_MCBCQEN_Msk = 0x100000
	// Bit MCBCQEN.
	Ethernet_ETH_MACRxQC1R_MCBCQEN = 0x100000
	// Position of TACPQE field.
	Ethernet_ETH_MACRxQC1R_TACPQE_Pos = 0x15
	// Bit mask of TACPQE field.
	Ethernet_ETH_MACRxQC1R_TACPQE_Msk = 0x200000
	// Bit TACPQE.
	Ethernet_ETH_MACRxQC1R_TACPQE = 0x200000

	// ETH_MACRxQC2R: This register controls the routing of tagged packets based on the USP (user priority) field of the received packets to the Rx queue 0 and 1.
	// Position of PSRQ0 field.
	Ethernet_ETH_MACRxQC2R_PSRQ0_Pos = 0x0
	// Bit mask of PSRQ0 field.
	Ethernet_ETH_MACRxQC2R_PSRQ0_Msk = 0xff
	// Position of PSRQ1 field.
	Ethernet_ETH_MACRxQC2R_PSRQ1_Pos = 0x8
	// Bit mask of PSRQ1 field.
	Ethernet_ETH_MACRxQC2R_PSRQ1_Msk = 0xff00

	// ETH_MACISR: The Interrupt Status register contains the status of interrupts.
	// Position of RGSMIIIS field.
	Ethernet_ETH_MACISR_RGSMIIIS_Pos = 0x0
	// Bit mask of RGSMIIIS field.
	Ethernet_ETH_MACISR_RGSMIIIS_Msk = 0x1
	// Bit RGSMIIIS.
	Ethernet_ETH_MACISR_RGSMIIIS = 0x1
	// Position of PHYIS field.
	Ethernet_ETH_MACISR_PHYIS_Pos = 0x3
	// Bit mask of PHYIS field.
	Ethernet_ETH_MACISR_PHYIS_Msk = 0x8
	// Bit PHYIS.
	Ethernet_ETH_MACISR_PHYIS = 0x8
	// Position of PMTIS field.
	Ethernet_ETH_MACISR_PMTIS_Pos = 0x4
	// Bit mask of PMTIS field.
	Ethernet_ETH_MACISR_PMTIS_Msk = 0x10
	// Bit PMTIS.
	Ethernet_ETH_MACISR_PMTIS = 0x10
	// Position of LPIIS field.
	Ethernet_ETH_MACISR_LPIIS_Pos = 0x5
	// Bit mask of LPIIS field.
	Ethernet_ETH_MACISR_LPIIS_Msk = 0x20
	// Bit LPIIS.
	Ethernet_ETH_MACISR_LPIIS = 0x20
	// Position of MMCIS field.
	Ethernet_ETH_MACISR_MMCIS_Pos = 0x8
	// Bit mask of MMCIS field.
	Ethernet_ETH_MACISR_MMCIS_Msk = 0x100
	// Bit MMCIS.
	Ethernet_ETH_MACISR_MMCIS = 0x100
	// Position of MMCRXIS field.
	Ethernet_ETH_MACISR_MMCRXIS_Pos = 0x9
	// Bit mask of MMCRXIS field.
	Ethernet_ETH_MACISR_MMCRXIS_Msk = 0x200
	// Bit MMCRXIS.
	Ethernet_ETH_MACISR_MMCRXIS = 0x200
	// Position of MMCTXIS field.
	Ethernet_ETH_MACISR_MMCTXIS_Pos = 0xa
	// Bit mask of MMCTXIS field.
	Ethernet_ETH_MACISR_MMCTXIS_Msk = 0x400
	// Bit MMCTXIS.
	Ethernet_ETH_MACISR_MMCTXIS = 0x400
	// Position of TSIS field.
	Ethernet_ETH_MACISR_TSIS_Pos = 0xc
	// Bit mask of TSIS field.
	Ethernet_ETH_MACISR_TSIS_Msk = 0x1000
	// Bit TSIS.
	Ethernet_ETH_MACISR_TSIS = 0x1000
	// Position of TXSTSIS field.
	Ethernet_ETH_MACISR_TXSTSIS_Pos = 0xd
	// Bit mask of TXSTSIS field.
	Ethernet_ETH_MACISR_TXSTSIS_Msk = 0x2000
	// Bit TXSTSIS.
	Ethernet_ETH_MACISR_TXSTSIS = 0x2000
	// Position of RXSTSIS field.
	Ethernet_ETH_MACISR_RXSTSIS_Pos = 0xe
	// Bit mask of RXSTSIS field.
	Ethernet_ETH_MACISR_RXSTSIS_Msk = 0x4000
	// Bit RXSTSIS.
	Ethernet_ETH_MACISR_RXSTSIS = 0x4000

	// ETH_MACIER: The Interrupt Enable register contains the masks for generating the interrupts.
	// Position of RGSMIIIE field.
	Ethernet_ETH_MACIER_RGSMIIIE_Pos = 0x0
	// Bit mask of RGSMIIIE field.
	Ethernet_ETH_MACIER_RGSMIIIE_Msk = 0x1
	// Bit RGSMIIIE.
	Ethernet_ETH_MACIER_RGSMIIIE = 0x1
	// Position of PHYIE field.
	Ethernet_ETH_MACIER_PHYIE_Pos = 0x3
	// Bit mask of PHYIE field.
	Ethernet_ETH_MACIER_PHYIE_Msk = 0x8
	// Bit PHYIE.
	Ethernet_ETH_MACIER_PHYIE = 0x8
	// Position of PMTIE field.
	Ethernet_ETH_MACIER_PMTIE_Pos = 0x4
	// Bit mask of PMTIE field.
	Ethernet_ETH_MACIER_PMTIE_Msk = 0x10
	// Bit PMTIE.
	Ethernet_ETH_MACIER_PMTIE = 0x10
	// Position of LPIIE field.
	Ethernet_ETH_MACIER_LPIIE_Pos = 0x5
	// Bit mask of LPIIE field.
	Ethernet_ETH_MACIER_LPIIE_Msk = 0x20
	// Bit LPIIE.
	Ethernet_ETH_MACIER_LPIIE = 0x20
	// Position of TSIE field.
	Ethernet_ETH_MACIER_TSIE_Pos = 0xc
	// Bit mask of TSIE field.
	Ethernet_ETH_MACIER_TSIE_Msk = 0x1000
	// Bit TSIE.
	Ethernet_ETH_MACIER_TSIE = 0x1000
	// Position of TXSTSIE field.
	Ethernet_ETH_MACIER_TXSTSIE_Pos = 0xd
	// Bit mask of TXSTSIE field.
	Ethernet_ETH_MACIER_TXSTSIE_Msk = 0x2000
	// Bit TXSTSIE.
	Ethernet_ETH_MACIER_TXSTSIE = 0x2000
	// Position of RXSTSIE field.
	Ethernet_ETH_MACIER_RXSTSIE_Pos = 0xe
	// Bit mask of RXSTSIE field.
	Ethernet_ETH_MACIER_RXSTSIE_Msk = 0x4000
	// Bit RXSTSIE.
	Ethernet_ETH_MACIER_RXSTSIE = 0x4000

	// ETH_MACRxTxSR: The Receive Transmit Status register contains the Receive and Transmit Error status.
	// Position of TJT field.
	Ethernet_ETH_MACRxTxSR_TJT_Pos = 0x0
	// Bit mask of TJT field.
	Ethernet_ETH_MACRxTxSR_TJT_Msk = 0x1
	// Bit TJT.
	Ethernet_ETH_MACRxTxSR_TJT = 0x1
	// Position of NCARR field.
	Ethernet_ETH_MACRxTxSR_NCARR_Pos = 0x1
	// Bit mask of NCARR field.
	Ethernet_ETH_MACRxTxSR_NCARR_Msk = 0x2
	// Bit NCARR.
	Ethernet_ETH_MACRxTxSR_NCARR = 0x2
	// Position of LCARR field.
	Ethernet_ETH_MACRxTxSR_LCARR_Pos = 0x2
	// Bit mask of LCARR field.
	Ethernet_ETH_MACRxTxSR_LCARR_Msk = 0x4
	// Bit LCARR.
	Ethernet_ETH_MACRxTxSR_LCARR = 0x4
	// Position of EXDEF field.
	Ethernet_ETH_MACRxTxSR_EXDEF_Pos = 0x3
	// Bit mask of EXDEF field.
	Ethernet_ETH_MACRxTxSR_EXDEF_Msk = 0x8
	// Bit EXDEF.
	Ethernet_ETH_MACRxTxSR_EXDEF = 0x8
	// Position of LCOL field.
	Ethernet_ETH_MACRxTxSR_LCOL_Pos = 0x4
	// Bit mask of LCOL field.
	Ethernet_ETH_MACRxTxSR_LCOL_Msk = 0x10
	// Bit LCOL.
	Ethernet_ETH_MACRxTxSR_LCOL = 0x10
	// Position of EXCOL field.
	Ethernet_ETH_MACRxTxSR_EXCOL_Pos = 0x5
	// Bit mask of EXCOL field.
	Ethernet_ETH_MACRxTxSR_EXCOL_Msk = 0x20
	// Bit EXCOL.
	Ethernet_ETH_MACRxTxSR_EXCOL = 0x20
	// Position of RWT field.
	Ethernet_ETH_MACRxTxSR_RWT_Pos = 0x8
	// Bit mask of RWT field.
	Ethernet_ETH_MACRxTxSR_RWT_Msk = 0x100
	// Bit RWT.
	Ethernet_ETH_MACRxTxSR_RWT = 0x100

	// ETH_MACPCSR: The PMT Control and Status Register is present only when you select the PMT module in coreConsultant.
	// Position of PWRDWN field.
	Ethernet_ETH_MACPCSR_PWRDWN_Pos = 0x0
	// Bit mask of PWRDWN field.
	Ethernet_ETH_MACPCSR_PWRDWN_Msk = 0x1
	// Bit PWRDWN.
	Ethernet_ETH_MACPCSR_PWRDWN = 0x1
	// Position of MGKPKTEN field.
	Ethernet_ETH_MACPCSR_MGKPKTEN_Pos = 0x1
	// Bit mask of MGKPKTEN field.
	Ethernet_ETH_MACPCSR_MGKPKTEN_Msk = 0x2
	// Bit MGKPKTEN.
	Ethernet_ETH_MACPCSR_MGKPKTEN = 0x2
	// Position of RWKPKTEN field.
	Ethernet_ETH_MACPCSR_RWKPKTEN_Pos = 0x2
	// Bit mask of RWKPKTEN field.
	Ethernet_ETH_MACPCSR_RWKPKTEN_Msk = 0x4
	// Bit RWKPKTEN.
	Ethernet_ETH_MACPCSR_RWKPKTEN = 0x4
	// Position of MGKPRCVD field.
	Ethernet_ETH_MACPCSR_MGKPRCVD_Pos = 0x5
	// Bit mask of MGKPRCVD field.
	Ethernet_ETH_MACPCSR_MGKPRCVD_Msk = 0x20
	// Bit MGKPRCVD.
	Ethernet_ETH_MACPCSR_MGKPRCVD = 0x20
	// Position of RWKPRCVD field.
	Ethernet_ETH_MACPCSR_RWKPRCVD_Pos = 0x6
	// Bit mask of RWKPRCVD field.
	Ethernet_ETH_MACPCSR_RWKPRCVD_Msk = 0x40
	// Bit RWKPRCVD.
	Ethernet_ETH_MACPCSR_RWKPRCVD = 0x40
	// Position of GLBLUCAST field.
	Ethernet_ETH_MACPCSR_GLBLUCAST_Pos = 0x9
	// Bit mask of GLBLUCAST field.
	Ethernet_ETH_MACPCSR_GLBLUCAST_Msk = 0x200
	// Bit GLBLUCAST.
	Ethernet_ETH_MACPCSR_GLBLUCAST = 0x200
	// Position of RWKPFE field.
	Ethernet_ETH_MACPCSR_RWKPFE_Pos = 0xa
	// Bit mask of RWKPFE field.
	Ethernet_ETH_MACPCSR_RWKPFE_Msk = 0x400
	// Bit RWKPFE.
	Ethernet_ETH_MACPCSR_RWKPFE = 0x400
	// Position of RWKPTR field.
	Ethernet_ETH_MACPCSR_RWKPTR_Pos = 0x18
	// Bit mask of RWKPTR field.
	Ethernet_ETH_MACPCSR_RWKPTR_Msk = 0x1f000000
	// Position of RWKFILTRST field.
	Ethernet_ETH_MACPCSR_RWKFILTRST_Pos = 0x1f
	// Bit mask of RWKFILTRST field.
	Ethernet_ETH_MACPCSR_RWKFILTRST_Msk = 0x80000000
	// Bit RWKFILTRST.
	Ethernet_ETH_MACPCSR_RWKFILTRST = 0x80000000

	// ETH_MACRWKPFR: The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
	// Position of TLPIEN field.
	Ethernet_ETH_MACRWKPFR_TLPIEN_Pos = 0x0
	// Bit mask of TLPIEN field.
	Ethernet_ETH_MACRWKPFR_TLPIEN_Msk = 0x1
	// Bit TLPIEN.
	Ethernet_ETH_MACRWKPFR_TLPIEN = 0x1
	// Position of TLPIEX field.
	Ethernet_ETH_MACRWKPFR_TLPIEX_Pos = 0x1
	// Bit mask of TLPIEX field.
	Ethernet_ETH_MACRWKPFR_TLPIEX_Msk = 0x2
	// Bit TLPIEX.
	Ethernet_ETH_MACRWKPFR_TLPIEX = 0x2
	// Position of RLPIEN field.
	Ethernet_ETH_MACRWKPFR_RLPIEN_Pos = 0x2
	// Bit mask of RLPIEN field.
	Ethernet_ETH_MACRWKPFR_RLPIEN_Msk = 0x4
	// Bit RLPIEN.
	Ethernet_ETH_MACRWKPFR_RLPIEN = 0x4
	// Position of RLPIEX field.
	Ethernet_ETH_MACRWKPFR_RLPIEX_Pos = 0x3
	// Bit mask of RLPIEX field.
	Ethernet_ETH_MACRWKPFR_RLPIEX_Msk = 0x8
	// Bit RLPIEX.
	Ethernet_ETH_MACRWKPFR_RLPIEX = 0x8
	// Position of TLPIST field.
	Ethernet_ETH_MACRWKPFR_TLPIST_Pos = 0x8
	// Bit mask of TLPIST field.
	Ethernet_ETH_MACRWKPFR_TLPIST_Msk = 0x100
	// Bit TLPIST.
	Ethernet_ETH_MACRWKPFR_TLPIST = 0x100
	// Position of RLPIST field.
	Ethernet_ETH_MACRWKPFR_RLPIST_Pos = 0x9
	// Bit mask of RLPIST field.
	Ethernet_ETH_MACRWKPFR_RLPIST_Msk = 0x200
	// Bit RLPIST.
	Ethernet_ETH_MACRWKPFR_RLPIST = 0x200
	// Position of LPIEN field.
	Ethernet_ETH_MACRWKPFR_LPIEN_Pos = 0x10
	// Bit mask of LPIEN field.
	Ethernet_ETH_MACRWKPFR_LPIEN_Msk = 0x10000
	// Bit LPIEN.
	Ethernet_ETH_MACRWKPFR_LPIEN = 0x10000
	// Position of PLS field.
	Ethernet_ETH_MACRWKPFR_PLS_Pos = 0x11
	// Bit mask of PLS field.
	Ethernet_ETH_MACRWKPFR_PLS_Msk = 0x20000
	// Bit PLS.
	Ethernet_ETH_MACRWKPFR_PLS = 0x20000
	// Position of PLSEN field.
	Ethernet_ETH_MACRWKPFR_PLSEN_Pos = 0x12
	// Bit mask of PLSEN field.
	Ethernet_ETH_MACRWKPFR_PLSEN_Msk = 0x40000
	// Bit PLSEN.
	Ethernet_ETH_MACRWKPFR_PLSEN = 0x40000
	// Position of LPITXA field.
	Ethernet_ETH_MACRWKPFR_LPITXA_Pos = 0x13
	// Bit mask of LPITXA field.
	Ethernet_ETH_MACRWKPFR_LPITXA_Msk = 0x80000
	// Bit LPITXA.
	Ethernet_ETH_MACRWKPFR_LPITXA = 0x80000
	// Position of LPITE field.
	Ethernet_ETH_MACRWKPFR_LPITE_Pos = 0x14
	// Bit mask of LPITE field.
	Ethernet_ETH_MACRWKPFR_LPITE_Msk = 0x100000
	// Bit LPITE.
	Ethernet_ETH_MACRWKPFR_LPITE = 0x100000

	// ETH_MACLCSR: The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
	// Position of TLPIEN field.
	Ethernet_ETH_MACLCSR_TLPIEN_Pos = 0x0
	// Bit mask of TLPIEN field.
	Ethernet_ETH_MACLCSR_TLPIEN_Msk = 0x1
	// Bit TLPIEN.
	Ethernet_ETH_MACLCSR_TLPIEN = 0x1
	// Position of TLPIEX field.
	Ethernet_ETH_MACLCSR_TLPIEX_Pos = 0x1
	// Bit mask of TLPIEX field.
	Ethernet_ETH_MACLCSR_TLPIEX_Msk = 0x2
	// Bit TLPIEX.
	Ethernet_ETH_MACLCSR_TLPIEX = 0x2
	// Position of RLPIEN field.
	Ethernet_ETH_MACLCSR_RLPIEN_Pos = 0x2
	// Bit mask of RLPIEN field.
	Ethernet_ETH_MACLCSR_RLPIEN_Msk = 0x4
	// Bit RLPIEN.
	Ethernet_ETH_MACLCSR_RLPIEN = 0x4
	// Position of RLPIEX field.
	Ethernet_ETH_MACLCSR_RLPIEX_Pos = 0x3
	// Bit mask of RLPIEX field.
	Ethernet_ETH_MACLCSR_RLPIEX_Msk = 0x8
	// Bit RLPIEX.
	Ethernet_ETH_MACLCSR_RLPIEX = 0x8
	// Position of TLPIST field.
	Ethernet_ETH_MACLCSR_TLPIST_Pos = 0x8
	// Bit mask of TLPIST field.
	Ethernet_ETH_MACLCSR_TLPIST_Msk = 0x100
	// Bit TLPIST.
	Ethernet_ETH_MACLCSR_TLPIST = 0x100
	// Position of RLPIST field.
	Ethernet_ETH_MACLCSR_RLPIST_Pos = 0x9
	// Bit mask of RLPIST field.
	Ethernet_ETH_MACLCSR_RLPIST_Msk = 0x200
	// Bit RLPIST.
	Ethernet_ETH_MACLCSR_RLPIST = 0x200
	// Position of LPIEN field.
	Ethernet_ETH_MACLCSR_LPIEN_Pos = 0x10
	// Bit mask of LPIEN field.
	Ethernet_ETH_MACLCSR_LPIEN_Msk = 0x10000
	// Bit LPIEN.
	Ethernet_ETH_MACLCSR_LPIEN = 0x10000
	// Position of PLS field.
	Ethernet_ETH_MACLCSR_PLS_Pos = 0x11
	// Bit mask of PLS field.
	Ethernet_ETH_MACLCSR_PLS_Msk = 0x20000
	// Bit PLS.
	Ethernet_ETH_MACLCSR_PLS = 0x20000
	// Position of PLSEN field.
	Ethernet_ETH_MACLCSR_PLSEN_Pos = 0x12
	// Bit mask of PLSEN field.
	Ethernet_ETH_MACLCSR_PLSEN_Msk = 0x40000
	// Bit PLSEN.
	Ethernet_ETH_MACLCSR_PLSEN = 0x40000
	// Position of LPITXA field.
	Ethernet_ETH_MACLCSR_LPITXA_Pos = 0x13
	// Bit mask of LPITXA field.
	Ethernet_ETH_MACLCSR_LPITXA_Msk = 0x80000
	// Bit LPITXA.
	Ethernet_ETH_MACLCSR_LPITXA = 0x80000
	// Position of LPITE field.
	Ethernet_ETH_MACLCSR_LPITE_Pos = 0x14
	// Bit mask of LPITE field.
	Ethernet_ETH_MACLCSR_LPITE_Msk = 0x100000
	// Bit LPITE.
	Ethernet_ETH_MACLCSR_LPITE = 0x100000

	// ETH_MACLTCR: The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.
	// Position of TWT field.
	Ethernet_ETH_MACLTCR_TWT_Pos = 0x0
	// Bit mask of TWT field.
	Ethernet_ETH_MACLTCR_TWT_Msk = 0xffff
	// Position of LST field.
	Ethernet_ETH_MACLTCR_LST_Pos = 0x10
	// Bit mask of LST field.
	Ethernet_ETH_MACLTCR_LST_Msk = 0x3ff0000

	// ETH_MACLETR: The LPI Entry Timer Register is used to store the LPI Idle Timer Value in Micro-Seconds.
	// Position of LPIET field.
	Ethernet_ETH_MACLETR_LPIET_Pos = 0x3
	// Bit mask of LPIET field.
	Ethernet_ETH_MACLETR_LPIET_Msk = 0xffff8

	// ETH_MAC1USTCR: This register controls the generation of the Reference time (1-microsecond tick) for all the LPI timers. This timer has to be programmed by the software initially.
	// Position of TIC_1US_CNTR field.
	Ethernet_ETH_MAC1USTCR_TIC_1US_CNTR_Pos = 0x0
	// Bit mask of TIC_1US_CNTR field.
	Ethernet_ETH_MAC1USTCR_TIC_1US_CNTR_Msk = 0xfff

	// ETH_MACPHYCSR: The PHY Interface Control and Status register indicates the status signals received by the, RGMII interface from the PHY.
	// Position of TC field.
	Ethernet_ETH_MACPHYCSR_TC_Pos = 0x0
	// Bit mask of TC field.
	Ethernet_ETH_MACPHYCSR_TC_Msk = 0x1
	// Bit TC.
	Ethernet_ETH_MACPHYCSR_TC = 0x1
	// Position of LUD field.
	Ethernet_ETH_MACPHYCSR_LUD_Pos = 0x1
	// Bit mask of LUD field.
	Ethernet_ETH_MACPHYCSR_LUD_Msk = 0x2
	// Bit LUD.
	Ethernet_ETH_MACPHYCSR_LUD = 0x2
	// Position of LNKMOD field.
	Ethernet_ETH_MACPHYCSR_LNKMOD_Pos = 0x10
	// Bit mask of LNKMOD field.
	Ethernet_ETH_MACPHYCSR_LNKMOD_Msk = 0x10000
	// Bit LNKMOD.
	Ethernet_ETH_MACPHYCSR_LNKMOD = 0x10000
	// Position of LNKSPEED field.
	Ethernet_ETH_MACPHYCSR_LNKSPEED_Pos = 0x11
	// Bit mask of LNKSPEED field.
	Ethernet_ETH_MACPHYCSR_LNKSPEED_Msk = 0x60000
	// Position of LNKSTS field.
	Ethernet_ETH_MACPHYCSR_LNKSTS_Pos = 0x13
	// Bit mask of LNKSTS field.
	Ethernet_ETH_MACPHYCSR_LNKSTS_Msk = 0x80000
	// Bit LNKSTS.
	Ethernet_ETH_MACPHYCSR_LNKSTS = 0x80000
	// Position of JABTO field.
	Ethernet_ETH_MACPHYCSR_JABTO_Pos = 0x14
	// Bit mask of JABTO field.
	Ethernet_ETH_MACPHYCSR_JABTO_Msk = 0x100000
	// Bit JABTO.
	Ethernet_ETH_MACPHYCSR_JABTO = 0x100000
	// Position of FALSCARDET field.
	Ethernet_ETH_MACPHYCSR_FALSCARDET_Pos = 0x15
	// Bit mask of FALSCARDET field.
	Ethernet_ETH_MACPHYCSR_FALSCARDET_Msk = 0x200000
	// Bit FALSCARDET.
	Ethernet_ETH_MACPHYCSR_FALSCARDET = 0x200000

	// ETH_MACVR: The version register identifies the version of the Ethernet peripheral.
	// Position of SNPSVER field.
	Ethernet_ETH_MACVR_SNPSVER_Pos = 0x0
	// Bit mask of SNPSVER field.
	Ethernet_ETH_MACVR_SNPSVER_Msk = 0xff
	// Position of USERVER field.
	Ethernet_ETH_MACVR_USERVER_Pos = 0x8
	// Bit mask of USERVER field.
	Ethernet_ETH_MACVR_USERVER_Msk = 0xff00

	// ETH_MACDR: The Debug register provides the debug status of various MAC blocks.
	// Position of RPESTS field.
	Ethernet_ETH_MACDR_RPESTS_Pos = 0x0
	// Bit mask of RPESTS field.
	Ethernet_ETH_MACDR_RPESTS_Msk = 0x1
	// Bit RPESTS.
	Ethernet_ETH_MACDR_RPESTS = 0x1
	// Position of RFCFCSTS field.
	Ethernet_ETH_MACDR_RFCFCSTS_Pos = 0x1
	// Bit mask of RFCFCSTS field.
	Ethernet_ETH_MACDR_RFCFCSTS_Msk = 0x6
	// Position of TPESTS field.
	Ethernet_ETH_MACDR_TPESTS_Pos = 0x10
	// Bit mask of TPESTS field.
	Ethernet_ETH_MACDR_TPESTS_Msk = 0x10000
	// Bit TPESTS.
	Ethernet_ETH_MACDR_TPESTS = 0x10000
	// Position of TFCSTS field.
	Ethernet_ETH_MACDR_TFCSTS_Pos = 0x11
	// Bit mask of TFCSTS field.
	Ethernet_ETH_MACDR_TFCSTS_Msk = 0x60000

	// ETH_MACHWF1R: This register indicates the presence of second set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
	// Position of RXFIFOSIZE field.
	Ethernet_ETH_MACHWF1R_RXFIFOSIZE_Pos = 0x0
	// Bit mask of RXFIFOSIZE field.
	Ethernet_ETH_MACHWF1R_RXFIFOSIZE_Msk = 0x1f
	// Position of TXFIFOSIZE field.
	Ethernet_ETH_MACHWF1R_TXFIFOSIZE_Pos = 0x6
	// Bit mask of TXFIFOSIZE field.
	Ethernet_ETH_MACHWF1R_TXFIFOSIZE_Msk = 0x7c0
	// Position of OSTEN field.
	Ethernet_ETH_MACHWF1R_OSTEN_Pos = 0xb
	// Bit mask of OSTEN field.
	Ethernet_ETH_MACHWF1R_OSTEN_Msk = 0x800
	// Bit OSTEN.
	Ethernet_ETH_MACHWF1R_OSTEN = 0x800
	// Position of PTOEN field.
	Ethernet_ETH_MACHWF1R_PTOEN_Pos = 0xc
	// Bit mask of PTOEN field.
	Ethernet_ETH_MACHWF1R_PTOEN_Msk = 0x1000
	// Bit PTOEN.
	Ethernet_ETH_MACHWF1R_PTOEN = 0x1000
	// Position of ADVTHWORD field.
	Ethernet_ETH_MACHWF1R_ADVTHWORD_Pos = 0xd
	// Bit mask of ADVTHWORD field.
	Ethernet_ETH_MACHWF1R_ADVTHWORD_Msk = 0x2000
	// Bit ADVTHWORD.
	Ethernet_ETH_MACHWF1R_ADVTHWORD = 0x2000
	// Position of ADDR64 field.
	Ethernet_ETH_MACHWF1R_ADDR64_Pos = 0xe
	// Bit mask of ADDR64 field.
	Ethernet_ETH_MACHWF1R_ADDR64_Msk = 0xc000
	// Position of DCBEN field.
	Ethernet_ETH_MACHWF1R_DCBEN_Pos = 0x10
	// Bit mask of DCBEN field.
	Ethernet_ETH_MACHWF1R_DCBEN_Msk = 0x10000
	// Bit DCBEN.
	Ethernet_ETH_MACHWF1R_DCBEN = 0x10000
	// Position of SPHEN field.
	Ethernet_ETH_MACHWF1R_SPHEN_Pos = 0x11
	// Bit mask of SPHEN field.
	Ethernet_ETH_MACHWF1R_SPHEN_Msk = 0x20000
	// Bit SPHEN.
	Ethernet_ETH_MACHWF1R_SPHEN = 0x20000
	// Position of TSOEN field.
	Ethernet_ETH_MACHWF1R_TSOEN_Pos = 0x12
	// Bit mask of TSOEN field.
	Ethernet_ETH_MACHWF1R_TSOEN_Msk = 0x40000
	// Bit TSOEN.
	Ethernet_ETH_MACHWF1R_TSOEN = 0x40000
	// Position of DBGMEMA field.
	Ethernet_ETH_MACHWF1R_DBGMEMA_Pos = 0x13
	// Bit mask of DBGMEMA field.
	Ethernet_ETH_MACHWF1R_DBGMEMA_Msk = 0x80000
	// Bit DBGMEMA.
	Ethernet_ETH_MACHWF1R_DBGMEMA = 0x80000
	// Position of AVSEL field.
	Ethernet_ETH_MACHWF1R_AVSEL_Pos = 0x14
	// Bit mask of AVSEL field.
	Ethernet_ETH_MACHWF1R_AVSEL_Msk = 0x100000
	// Bit AVSEL.
	Ethernet_ETH_MACHWF1R_AVSEL = 0x100000
	// Position of HASHTBLSZ field.
	Ethernet_ETH_MACHWF1R_HASHTBLSZ_Pos = 0x18
	// Bit mask of HASHTBLSZ field.
	Ethernet_ETH_MACHWF1R_HASHTBLSZ_Msk = 0x3000000
	// Position of L3L4FNUM field.
	Ethernet_ETH_MACHWF1R_L3L4FNUM_Pos = 0x1b
	// Bit mask of L3L4FNUM field.
	Ethernet_ETH_MACHWF1R_L3L4FNUM_Msk = 0x78000000

	// ETH_MACHWF2R: This register indicates the presence of third set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
	// Position of RXQCNT field.
	Ethernet_ETH_MACHWF2R_RXQCNT_Pos = 0x0
	// Bit mask of RXQCNT field.
	Ethernet_ETH_MACHWF2R_RXQCNT_Msk = 0xf
	// Position of TXQCNT field.
	Ethernet_ETH_MACHWF2R_TXQCNT_Pos = 0x6
	// Bit mask of TXQCNT field.
	Ethernet_ETH_MACHWF2R_TXQCNT_Msk = 0x3c0
	// Position of RXCHCNT field.
	Ethernet_ETH_MACHWF2R_RXCHCNT_Pos = 0xc
	// Bit mask of RXCHCNT field.
	Ethernet_ETH_MACHWF2R_RXCHCNT_Msk = 0xf000
	// Position of TXCHCNT field.
	Ethernet_ETH_MACHWF2R_TXCHCNT_Pos = 0x12
	// Bit mask of TXCHCNT field.
	Ethernet_ETH_MACHWF2R_TXCHCNT_Msk = 0x3c0000
	// Position of PPSOUTNUM field.
	Ethernet_ETH_MACHWF2R_PPSOUTNUM_Pos = 0x18
	// Bit mask of PPSOUTNUM field.
	Ethernet_ETH_MACHWF2R_PPSOUTNUM_Msk = 0x7000000
	// Position of AUXSNAPNUM field.
	Ethernet_ETH_MACHWF2R_AUXSNAPNUM_Pos = 0x1c
	// Bit mask of AUXSNAPNUM field.
	Ethernet_ETH_MACHWF2R_AUXSNAPNUM_Msk = 0x70000000

	// ETH_MACMDIOAR: The MDIO Address register controls the management cycles to external PHY through a management interface.
	// Position of GB field.
	Ethernet_ETH_MACMDIOAR_GB_Pos = 0x0
	// Bit mask of GB field.
	Ethernet_ETH_MACMDIOAR_GB_Msk = 0x1
	// Bit GB.
	Ethernet_ETH_MACMDIOAR_GB = 0x1
	// Position of C45E field.
	Ethernet_ETH_MACMDIOAR_C45E_Pos = 0x1
	// Bit mask of C45E field.
	Ethernet_ETH_MACMDIOAR_C45E_Msk = 0x2
	// Bit C45E.
	Ethernet_ETH_MACMDIOAR_C45E = 0x2
	// Position of GOC field.
	Ethernet_ETH_MACMDIOAR_GOC_Pos = 0x2
	// Bit mask of GOC field.
	Ethernet_ETH_MACMDIOAR_GOC_Msk = 0xc
	// Position of SKAP field.
	Ethernet_ETH_MACMDIOAR_SKAP_Pos = 0x4
	// Bit mask of SKAP field.
	Ethernet_ETH_MACMDIOAR_SKAP_Msk = 0x10
	// Bit SKAP.
	Ethernet_ETH_MACMDIOAR_SKAP = 0x10
	// Position of CR field.
	Ethernet_ETH_MACMDIOAR_CR_Pos = 0x8
	// Bit mask of CR field.
	Ethernet_ETH_MACMDIOAR_CR_Msk = 0xf00
	// Position of NTC field.
	Ethernet_ETH_MACMDIOAR_NTC_Pos = 0xc
	// Bit mask of NTC field.
	Ethernet_ETH_MACMDIOAR_NTC_Msk = 0x7000
	// Position of RDA field.
	Ethernet_ETH_MACMDIOAR_RDA_Pos = 0x10
	// Bit mask of RDA field.
	Ethernet_ETH_MACMDIOAR_RDA_Msk = 0x1f0000
	// Position of PA field.
	Ethernet_ETH_MACMDIOAR_PA_Pos = 0x15
	// Bit mask of PA field.
	Ethernet_ETH_MACMDIOAR_PA_Msk = 0x3e00000
	// Position of BTB field.
	Ethernet_ETH_MACMDIOAR_BTB_Pos = 0x1a
	// Bit mask of BTB field.
	Ethernet_ETH_MACMDIOAR_BTB_Msk = 0x4000000
	// Bit BTB.
	Ethernet_ETH_MACMDIOAR_BTB = 0x4000000
	// Position of PSE field.
	Ethernet_ETH_MACMDIOAR_PSE_Pos = 0x1b
	// Bit mask of PSE field.
	Ethernet_ETH_MACMDIOAR_PSE_Msk = 0x8000000
	// Bit PSE.
	Ethernet_ETH_MACMDIOAR_PSE = 0x8000000

	// ETH_MACMDIODR: The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in ETH_MACMDIOAR. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register.
	// Position of GD field.
	Ethernet_ETH_MACMDIODR_GD_Pos = 0x0
	// Bit mask of GD field.
	Ethernet_ETH_MACMDIODR_GD_Msk = 0xffff
	// Position of RA field.
	Ethernet_ETH_MACMDIODR_RA_Pos = 0x10
	// Bit mask of RA field.
	Ethernet_ETH_MACMDIODR_RA_Msk = 0xffff0000

	// ETH_MACA0HR: The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the GMII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the GMII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.
	// Position of ADDRHI field.
	Ethernet_ETH_MACA0HR_ADDRHI_Pos = 0x0
	// Bit mask of ADDRHI field.
	Ethernet_ETH_MACA0HR_ADDRHI_Msk = 0xffff
	// Position of AE field.
	Ethernet_ETH_MACA0HR_AE_Pos = 0x1f
	// Bit mask of AE field.
	Ethernet_ETH_MACA0HR_AE_Msk = 0x80000000
	// Bit AE.
	Ethernet_ETH_MACA0HR_AE = 0x80000000

	// ETH_MACA0LR: The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
	// Position of ADDRLO field.
	Ethernet_ETH_MACA0LR_ADDRLO_Pos = 0x0
	// Bit mask of ADDRLO field.
	Ethernet_ETH_MACA0LR_ADDRLO_Msk = 0xffffffff

	// ETH_MACA1HR: The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.
	// Position of ADDRHI field.
	Ethernet_ETH_MACA1HR_ADDRHI_Pos = 0x0
	// Bit mask of ADDRHI field.
	Ethernet_ETH_MACA1HR_ADDRHI_Msk = 0xffff
	// Position of MBC field.
	Ethernet_ETH_MACA1HR_MBC_Pos = 0x18
	// Bit mask of MBC field.
	Ethernet_ETH_MACA1HR_MBC_Msk = 0x3f000000
	// Position of SA field.
	Ethernet_ETH_MACA1HR_SA_Pos = 0x1e
	// Bit mask of SA field.
	Ethernet_ETH_MACA1HR_SA_Msk = 0x40000000
	// Bit SA.
	Ethernet_ETH_MACA1HR_SA = 0x40000000
	// Position of AE field.
	Ethernet_ETH_MACA1HR_AE_Pos = 0x1f
	// Bit mask of AE field.
	Ethernet_ETH_MACA1HR_AE_Msk = 0x80000000
	// Bit AE.
	Ethernet_ETH_MACA1HR_AE = 0x80000000

	// ETH_MACA1LR: The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
	// Position of ADDRLO field.
	Ethernet_ETH_MACA1LR_ADDRLO_Pos = 0x0
	// Bit mask of ADDRLO field.
	Ethernet_ETH_MACA1LR_ADDRLO_Msk = 0xffffffff

	// ETH_MACA2HR: The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.
	// Position of ADDRHI field.
	Ethernet_ETH_MACA2HR_ADDRHI_Pos = 0x0
	// Bit mask of ADDRHI field.
	Ethernet_ETH_MACA2HR_ADDRHI_Msk = 0xffff
	// Position of MBC field.
	Ethernet_ETH_MACA2HR_MBC_Pos = 0x18
	// Bit mask of MBC field.
	Ethernet_ETH_MACA2HR_MBC_Msk = 0x3f000000
	// Position of SA field.
	Ethernet_ETH_MACA2HR_SA_Pos = 0x1e
	// Bit mask of SA field.
	Ethernet_ETH_MACA2HR_SA_Msk = 0x40000000
	// Bit SA.
	Ethernet_ETH_MACA2HR_SA = 0x40000000
	// Position of AE field.
	Ethernet_ETH_MACA2HR_AE_Pos = 0x1f
	// Bit mask of AE field.
	Ethernet_ETH_MACA2HR_AE_Msk = 0x80000000
	// Bit AE.
	Ethernet_ETH_MACA2HR_AE = 0x80000000

	// ETH_MACA2LR: The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
	// Position of ADDRLO field.
	Ethernet_ETH_MACA2LR_ADDRLO_Pos = 0x0
	// Bit mask of ADDRLO field.
	Ethernet_ETH_MACA2LR_ADDRLO_Msk = 0xffffffff

	// ETH_MACA3HR: The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.
	// Position of ADDRHI field.
	Ethernet_ETH_MACA3HR_ADDRHI_Pos = 0x0
	// Bit mask of ADDRHI field.
	Ethernet_ETH_MACA3HR_ADDRHI_Msk = 0xffff
	// Position of MBC field.
	Ethernet_ETH_MACA3HR_MBC_Pos = 0x18
	// Bit mask of MBC field.
	Ethernet_ETH_MACA3HR_MBC_Msk = 0x3f000000
	// Position of SA field.
	Ethernet_ETH_MACA3HR_SA_Pos = 0x1e
	// Bit mask of SA field.
	Ethernet_ETH_MACA3HR_SA_Msk = 0x40000000
	// Bit SA.
	Ethernet_ETH_MACA3HR_SA = 0x40000000
	// Position of AE field.
	Ethernet_ETH_MACA3HR_AE_Pos = 0x1f
	// Bit mask of AE field.
	Ethernet_ETH_MACA3HR_AE_Msk = 0x80000000
	// Bit AE.
	Ethernet_ETH_MACA3HR_AE = 0x80000000

	// ETH_MACA3LR: The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
	// Position of ADDRLO field.
	Ethernet_ETH_MACA3LR_ADDRLO_Pos = 0x0
	// Bit mask of ADDRLO field.
	Ethernet_ETH_MACA3LR_ADDRLO_Msk = 0xffffffff

	// MMC_CONTROL: This register configures the MMC operating mode.
	// Position of CNTRST field.
	Ethernet_MMC_CONTROL_CNTRST_Pos = 0x0
	// Bit mask of CNTRST field.
	Ethernet_MMC_CONTROL_CNTRST_Msk = 0x1
	// Bit CNTRST.
	Ethernet_MMC_CONTROL_CNTRST = 0x1
	// Position of CNTSTOPRO field.
	Ethernet_MMC_CONTROL_CNTSTOPRO_Pos = 0x1
	// Bit mask of CNTSTOPRO field.
	Ethernet_MMC_CONTROL_CNTSTOPRO_Msk = 0x2
	// Bit CNTSTOPRO.
	Ethernet_MMC_CONTROL_CNTSTOPRO = 0x2
	// Position of RSTONRD field.
	Ethernet_MMC_CONTROL_RSTONRD_Pos = 0x2
	// Bit mask of RSTONRD field.
	Ethernet_MMC_CONTROL_RSTONRD_Msk = 0x4
	// Bit RSTONRD.
	Ethernet_MMC_CONTROL_RSTONRD = 0x4
	// Position of CNTFREEZ field.
	Ethernet_MMC_CONTROL_CNTFREEZ_Pos = 0x3
	// Bit mask of CNTFREEZ field.
	Ethernet_MMC_CONTROL_CNTFREEZ_Msk = 0x8
	// Bit CNTFREEZ.
	Ethernet_MMC_CONTROL_CNTFREEZ = 0x8
	// Position of CNTPRST field.
	Ethernet_MMC_CONTROL_CNTPRST_Pos = 0x4
	// Bit mask of CNTPRST field.
	Ethernet_MMC_CONTROL_CNTPRST_Msk = 0x10
	// Bit CNTPRST.
	Ethernet_MMC_CONTROL_CNTPRST = 0x10
	// Position of CNTPRSTLVL field.
	Ethernet_MMC_CONTROL_CNTPRSTLVL_Pos = 0x5
	// Bit mask of CNTPRSTLVL field.
	Ethernet_MMC_CONTROL_CNTPRSTLVL_Msk = 0x20
	// Bit CNTPRSTLVL.
	Ethernet_MMC_CONTROL_CNTPRSTLVL = 0x20
	// Position of UCDBC field.
	Ethernet_MMC_CONTROL_UCDBC_Pos = 0x8
	// Bit mask of UCDBC field.
	Ethernet_MMC_CONTROL_UCDBC_Msk = 0x100
	// Bit UCDBC.
	Ethernet_MMC_CONTROL_UCDBC = 0x100

	// MMC_RX_INTERRUPT: This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter). Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.
	// Position of RXCRCERPIS field.
	Ethernet_MMC_RX_INTERRUPT_RXCRCERPIS_Pos = 0x5
	// Bit mask of RXCRCERPIS field.
	Ethernet_MMC_RX_INTERRUPT_RXCRCERPIS_Msk = 0x20
	// Bit RXCRCERPIS.
	Ethernet_MMC_RX_INTERRUPT_RXCRCERPIS = 0x20
	// Position of RXALGNERPIS field.
	Ethernet_MMC_RX_INTERRUPT_RXALGNERPIS_Pos = 0x6
	// Bit mask of RXALGNERPIS field.
	Ethernet_MMC_RX_INTERRUPT_RXALGNERPIS_Msk = 0x40
	// Bit RXALGNERPIS.
	Ethernet_MMC_RX_INTERRUPT_RXALGNERPIS = 0x40
	// Position of RXUCGPIS field.
	Ethernet_MMC_RX_INTERRUPT_RXUCGPIS_Pos = 0x11
	// Bit mask of RXUCGPIS field.
	Ethernet_MMC_RX_INTERRUPT_RXUCGPIS_Msk = 0x20000
	// Bit RXUCGPIS.
	Ethernet_MMC_RX_INTERRUPT_RXUCGPIS = 0x20000
	// Position of RXLPIUSCIS field.
	Ethernet_MMC_RX_INTERRUPT_RXLPIUSCIS_Pos = 0x1a
	// Bit mask of RXLPIUSCIS field.
	Ethernet_MMC_RX_INTERRUPT_RXLPIUSCIS_Msk = 0x4000000
	// Bit RXLPIUSCIS.
	Ethernet_MMC_RX_INTERRUPT_RXLPIUSCIS = 0x4000000
	// Position of RXLPITRCIS field.
	Ethernet_MMC_RX_INTERRUPT_RXLPITRCIS_Pos = 0x1b
	// Bit mask of RXLPITRCIS field.
	Ethernet_MMC_RX_INTERRUPT_RXLPITRCIS_Msk = 0x8000000
	// Bit RXLPITRCIS.
	Ethernet_MMC_RX_INTERRUPT_RXLPITRCIS = 0x8000000

	// MMC_TX_INTERRUPT: This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.
	// Position of TXSCOLGPIS field.
	Ethernet_MMC_TX_INTERRUPT_TXSCOLGPIS_Pos = 0xe
	// Bit mask of TXSCOLGPIS field.
	Ethernet_MMC_TX_INTERRUPT_TXSCOLGPIS_Msk = 0x4000
	// Bit TXSCOLGPIS.
	Ethernet_MMC_TX_INTERRUPT_TXSCOLGPIS = 0x4000
	// Position of TXMCOLGPIS field.
	Ethernet_MMC_TX_INTERRUPT_TXMCOLGPIS_Pos = 0xf
	// Bit mask of TXMCOLGPIS field.
	Ethernet_MMC_TX_INTERRUPT_TXMCOLGPIS_Msk = 0x8000
	// Bit TXMCOLGPIS.
	Ethernet_MMC_TX_INTERRUPT_TXMCOLGPIS = 0x8000
	// Position of TXGPKTIS field.
	Ethernet_MMC_TX_INTERRUPT_TXGPKTIS_Pos = 0x15
	// Bit mask of TXGPKTIS field.
	Ethernet_MMC_TX_INTERRUPT_TXGPKTIS_Msk = 0x200000
	// Bit TXGPKTIS.
	Ethernet_MMC_TX_INTERRUPT_TXGPKTIS = 0x200000
	// Position of TXLPIUSCIS field.
	Ethernet_MMC_TX_INTERRUPT_TXLPIUSCIS_Pos = 0x1a
	// Bit mask of TXLPIUSCIS field.
	Ethernet_MMC_TX_INTERRUPT_TXLPIUSCIS_Msk = 0x4000000
	// Bit TXLPIUSCIS.
	Ethernet_MMC_TX_INTERRUPT_TXLPIUSCIS = 0x4000000
	// Position of TXLPITRCIS field.
	Ethernet_MMC_TX_INTERRUPT_TXLPITRCIS_Pos = 0x1b
	// Bit mask of TXLPITRCIS field.
	Ethernet_MMC_TX_INTERRUPT_TXLPITRCIS_Msk = 0x8000000
	// Bit TXLPITRCIS.
	Ethernet_MMC_TX_INTERRUPT_TXLPITRCIS = 0x8000000

	// MMC_RX_INTERRUPT_MASK: The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values.
	// Position of RXCRCERPIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Pos = 0x5
	// Bit mask of RXCRCERPIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Msk = 0x20
	// Bit RXCRCERPIM.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXCRCERPIM = 0x20
	// Position of RXALGNERPIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Pos = 0x6
	// Bit mask of RXALGNERPIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Msk = 0x40
	// Bit RXALGNERPIM.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXALGNERPIM = 0x40
	// Position of RXUCGPIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Pos = 0x11
	// Bit mask of RXUCGPIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Msk = 0x20000
	// Bit RXUCGPIM.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXUCGPIM = 0x20000
	// Position of RXLPIUSCIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Pos = 0x1a
	// Bit mask of RXLPIUSCIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Msk = 0x4000000
	// Bit RXLPIUSCIM.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM = 0x4000000
	// Position of RXLPITRCIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Pos = 0x1b
	// Bit mask of RXLPITRCIM field.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Msk = 0x8000000
	// Bit RXLPITRCIM.
	Ethernet_MMC_RX_INTERRUPT_MASK_RXLPITRCIM = 0x8000000

	// MMC_TX_INTERRUPT_MASK: This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide. This register is present only when any one of the MMC Transmit Counters is selected during core configuration.
	// Position of TXSCOLGPIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Pos = 0xe
	// Bit mask of TXSCOLGPIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Msk = 0x4000
	// Bit TXSCOLGPIM.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM = 0x4000
	// Position of TXMCOLGPIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Pos = 0xf
	// Bit mask of TXMCOLGPIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Msk = 0x8000
	// Bit TXMCOLGPIM.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM = 0x8000
	// Position of TXGPKTIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Pos = 0x15
	// Bit mask of TXGPKTIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Msk = 0x200000
	// Bit TXGPKTIM.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXGPKTIM = 0x200000
	// Position of TXLPIUSCIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Pos = 0x1a
	// Bit mask of TXLPIUSCIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Msk = 0x4000000
	// Bit TXLPIUSCIM.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM = 0x4000000
	// Position of TXLPITRCIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Pos = 0x1b
	// Bit mask of TXLPITRCIM field.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Msk = 0x8000000
	// Bit TXLPITRCIM.
	Ethernet_MMC_TX_INTERRUPT_MASK_TXLPITRCIM = 0x8000000

	// TX_SINGLE_COLLISION_GOOD_PACKETS: This register provides the number of successfully transmitted packets by Ethernet peripheral after a single collision in the half-duplex mode.
	// Position of TXSNGLCOLG field.
	Ethernet_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Pos = 0x0
	// Bit mask of TXSNGLCOLG field.
	Ethernet_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Msk = 0xffffffff

	// TX_MULTIPLE_COLLISION_GOOD_PACKETS: This register provides the number of successfully transmitted packets by Ethernet peripheral after multiple collisions in the half-duplex mode.
	// Position of TXMULTCOLG field.
	Ethernet_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Pos = 0x0
	// Bit mask of TXMULTCOLG field.
	Ethernet_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Msk = 0xffffffff

	// TX_PACKET_COUNT_GOOD: This register provides the number of good packets transmitted by Ethernet peripheral.
	// Position of TXPKTG field.
	Ethernet_TX_PACKET_COUNT_GOOD_TXPKTG_Pos = 0x0
	// Bit mask of TXPKTG field.
	Ethernet_TX_PACKET_COUNT_GOOD_TXPKTG_Msk = 0xffffffff

	// RX_CRC_ERROR_PACKETS: This register provides the number of packets received by Ethernet peripheral with CRC error.
	// Position of RXCRCERR field.
	Ethernet_RX_CRC_ERROR_PACKETS_RXCRCERR_Pos = 0x0
	// Bit mask of RXCRCERR field.
	Ethernet_RX_CRC_ERROR_PACKETS_RXCRCERR_Msk = 0xffffffff

	// RX_ALIGNMENT_ERROR_PACKETS: This register provides the number of packets received by Ethernet peripheral with alignment (dribble) error. It is valid only in 10/100 mode.
	// Position of RXALGNERR field.
	Ethernet_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Pos = 0x0
	// Bit mask of RXALGNERR field.
	Ethernet_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Msk = 0xffffffff

	// RX_UNICAST_PACKETS_GOOD: This register provides the number of good unicast packets received by Ethernet peripheral.
	// Position of RXUCASTG field.
	Ethernet_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Pos = 0x0
	// Bit mask of RXUCASTG field.
	Ethernet_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Msk = 0xffffffff

	// TX_LPI_USEC_CNTR: This register provides the number of microseconds Tx LPI is asserted by Ethernet peripheral.
	// Position of TXLPIUSC field.
	Ethernet_TX_LPI_USEC_CNTR_TXLPIUSC_Pos = 0x0
	// Bit mask of TXLPIUSC field.
	Ethernet_TX_LPI_USEC_CNTR_TXLPIUSC_Msk = 0xffffffff

	// TX_LPI_TRAN_CNTR: This register provides the number of times Ethernet peripheral has entered Tx LPI.
	// Position of TXLPITRC field.
	Ethernet_TX_LPI_TRAN_CNTR_TXLPITRC_Pos = 0x0
	// Bit mask of TXLPITRC field.
	Ethernet_TX_LPI_TRAN_CNTR_TXLPITRC_Msk = 0xffffffff

	// RX_LPI_USEC_CNTR: This register provides the number of microseconds Rx LPI is sampled by Ethernet peripheral.
	// Position of RXLPIUSC field.
	Ethernet_RX_LPI_USEC_CNTR_RXLPIUSC_Pos = 0x0
	// Bit mask of RXLPIUSC field.
	Ethernet_RX_LPI_USEC_CNTR_RXLPIUSC_Msk = 0xffffffff

	// RX_LPI_TRAN_CNTR: This register provides the number of times Ethernet peripheral has entered Rx LPI.
	// Position of RXLPITRC field.
	Ethernet_RX_LPI_TRAN_CNTR_RXLPITRC_Pos = 0x0
	// Bit mask of RXLPITRC field.
	Ethernet_RX_LPI_TRAN_CNTR_RXLPITRC_Msk = 0xffffffff

	// ETH_MACL3L4C0R: The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.
	// Position of L3PEN0 field.
	Ethernet_ETH_MACL3L4C0R_L3PEN0_Pos = 0x0
	// Bit mask of L3PEN0 field.
	Ethernet_ETH_MACL3L4C0R_L3PEN0_Msk = 0x1
	// Bit L3PEN0.
	Ethernet_ETH_MACL3L4C0R_L3PEN0 = 0x1
	// Position of L3SAM0 field.
	Ethernet_ETH_MACL3L4C0R_L3SAM0_Pos = 0x2
	// Bit mask of L3SAM0 field.
	Ethernet_ETH_MACL3L4C0R_L3SAM0_Msk = 0x4
	// Bit L3SAM0.
	Ethernet_ETH_MACL3L4C0R_L3SAM0 = 0x4
	// Position of L3SAIM0 field.
	Ethernet_ETH_MACL3L4C0R_L3SAIM0_Pos = 0x3
	// Bit mask of L3SAIM0 field.
	Ethernet_ETH_MACL3L4C0R_L3SAIM0_Msk = 0x8
	// Bit L3SAIM0.
	Ethernet_ETH_MACL3L4C0R_L3SAIM0 = 0x8
	// Position of L3DAM0 field.
	Ethernet_ETH_MACL3L4C0R_L3DAM0_Pos = 0x4
	// Bit mask of L3DAM0 field.
	Ethernet_ETH_MACL3L4C0R_L3DAM0_Msk = 0x10
	// Bit L3DAM0.
	Ethernet_ETH_MACL3L4C0R_L3DAM0 = 0x10
	// Position of L3DAIM0 field.
	Ethernet_ETH_MACL3L4C0R_L3DAIM0_Pos = 0x5
	// Bit mask of L3DAIM0 field.
	Ethernet_ETH_MACL3L4C0R_L3DAIM0_Msk = 0x20
	// Bit L3DAIM0.
	Ethernet_ETH_MACL3L4C0R_L3DAIM0 = 0x20
	// Position of L3HSBM0 field.
	Ethernet_ETH_MACL3L4C0R_L3HSBM0_Pos = 0x6
	// Bit mask of L3HSBM0 field.
	Ethernet_ETH_MACL3L4C0R_L3HSBM0_Msk = 0x7c0
	// Position of L3HDBM0 field.
	Ethernet_ETH_MACL3L4C0R_L3HDBM0_Pos = 0xb
	// Bit mask of L3HDBM0 field.
	Ethernet_ETH_MACL3L4C0R_L3HDBM0_Msk = 0xf800
	// Position of L4PEN0 field.
	Ethernet_ETH_MACL3L4C0R_L4PEN0_Pos = 0x10
	// Bit mask of L4PEN0 field.
	Ethernet_ETH_MACL3L4C0R_L4PEN0_Msk = 0x10000
	// Bit L4PEN0.
	Ethernet_ETH_MACL3L4C0R_L4PEN0 = 0x10000
	// Position of L4SPM0 field.
	Ethernet_ETH_MACL3L4C0R_L4SPM0_Pos = 0x12
	// Bit mask of L4SPM0 field.
	Ethernet_ETH_MACL3L4C0R_L4SPM0_Msk = 0x40000
	// Bit L4SPM0.
	Ethernet_ETH_MACL3L4C0R_L4SPM0 = 0x40000
	// Position of L4SPIM0 field.
	Ethernet_ETH_MACL3L4C0R_L4SPIM0_Pos = 0x13
	// Bit mask of L4SPIM0 field.
	Ethernet_ETH_MACL3L4C0R_L4SPIM0_Msk = 0x80000
	// Bit L4SPIM0.
	Ethernet_ETH_MACL3L4C0R_L4SPIM0 = 0x80000
	// Position of L4DPM0 field.
	Ethernet_ETH_MACL3L4C0R_L4DPM0_Pos = 0x14
	// Bit mask of L4DPM0 field.
	Ethernet_ETH_MACL3L4C0R_L4DPM0_Msk = 0x100000
	// Bit L4DPM0.
	Ethernet_ETH_MACL3L4C0R_L4DPM0 = 0x100000
	// Position of L4DPIM0 field.
	Ethernet_ETH_MACL3L4C0R_L4DPIM0_Pos = 0x15
	// Bit mask of L4DPIM0 field.
	Ethernet_ETH_MACL3L4C0R_L4DPIM0_Msk = 0x200000
	// Bit L4DPIM0.
	Ethernet_ETH_MACL3L4C0R_L4DPIM0 = 0x200000

	// ETH_MACL4A0R: Layer4 address filter 0 register
	// Position of L4SP0 field.
	Ethernet_ETH_MACL4A0R_L4SP0_Pos = 0x0
	// Bit mask of L4SP0 field.
	Ethernet_ETH_MACL4A0R_L4SP0_Msk = 0xffff
	// Position of L4DP0 field.
	Ethernet_ETH_MACL4A0R_L4DP0_Pos = 0x10
	// Bit mask of L4DP0 field.
	Ethernet_ETH_MACL4A0R_L4DP0_Msk = 0xffff0000

	// ETH_MACL3A00R: For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
	// Position of L3A00 field.
	Ethernet_ETH_MACL3A00R_L3A00_Pos = 0x0
	// Bit mask of L3A00 field.
	Ethernet_ETH_MACL3A00R_L3A00_Msk = 0xffffffff

	// ETH_MACL3A10R: For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.
	// Position of L3A10 field.
	Ethernet_ETH_MACL3A10R_L3A10_Pos = 0x0
	// Bit mask of L3A10 field.
	Ethernet_ETH_MACL3A10R_L3A10_Msk = 0xffffffff

	// ETH_MACL3A20: The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.
	// Position of L3A20 field.
	Ethernet_ETH_MACL3A20_L3A20_Pos = 0x0
	// Bit mask of L3A20 field.
	Ethernet_ETH_MACL3A20_L3A20_Msk = 0xffffffff

	// ETH_MACL3A30: The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.
	// Position of L3A30 field.
	Ethernet_ETH_MACL3A30_L3A30_Pos = 0x0
	// Bit mask of L3A30 field.
	Ethernet_ETH_MACL3A30_L3A30_Msk = 0xffffffff

	// ETH_MACL3L4C1R: The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.
	// Position of L3PEN1 field.
	Ethernet_ETH_MACL3L4C1R_L3PEN1_Pos = 0x0
	// Bit mask of L3PEN1 field.
	Ethernet_ETH_MACL3L4C1R_L3PEN1_Msk = 0x1
	// Bit L3PEN1.
	Ethernet_ETH_MACL3L4C1R_L3PEN1 = 0x1
	// Position of L3SAM1 field.
	Ethernet_ETH_MACL3L4C1R_L3SAM1_Pos = 0x2
	// Bit mask of L3SAM1 field.
	Ethernet_ETH_MACL3L4C1R_L3SAM1_Msk = 0x4
	// Bit L3SAM1.
	Ethernet_ETH_MACL3L4C1R_L3SAM1 = 0x4
	// Position of L3SAIM1 field.
	Ethernet_ETH_MACL3L4C1R_L3SAIM1_Pos = 0x3
	// Bit mask of L3SAIM1 field.
	Ethernet_ETH_MACL3L4C1R_L3SAIM1_Msk = 0x8
	// Bit L3SAIM1.
	Ethernet_ETH_MACL3L4C1R_L3SAIM1 = 0x8
	// Position of L3DAM1 field.
	Ethernet_ETH_MACL3L4C1R_L3DAM1_Pos = 0x4
	// Bit mask of L3DAM1 field.
	Ethernet_ETH_MACL3L4C1R_L3DAM1_Msk = 0x10
	// Bit L3DAM1.
	Ethernet_ETH_MACL3L4C1R_L3DAM1 = 0x10
	// Position of L3DAIM1 field.
	Ethernet_ETH_MACL3L4C1R_L3DAIM1_Pos = 0x5
	// Bit mask of L3DAIM1 field.
	Ethernet_ETH_MACL3L4C1R_L3DAIM1_Msk = 0x20
	// Bit L3DAIM1.
	Ethernet_ETH_MACL3L4C1R_L3DAIM1 = 0x20
	// Position of L3HSBM1 field.
	Ethernet_ETH_MACL3L4C1R_L3HSBM1_Pos = 0x6
	// Bit mask of L3HSBM1 field.
	Ethernet_ETH_MACL3L4C1R_L3HSBM1_Msk = 0x7c0
	// Position of L3HDBM1 field.
	Ethernet_ETH_MACL3L4C1R_L3HDBM1_Pos = 0xb
	// Bit mask of L3HDBM1 field.
	Ethernet_ETH_MACL3L4C1R_L3HDBM1_Msk = 0xf800
	// Position of L4PEN1 field.
	Ethernet_ETH_MACL3L4C1R_L4PEN1_Pos = 0x10
	// Bit mask of L4PEN1 field.
	Ethernet_ETH_MACL3L4C1R_L4PEN1_Msk = 0x10000
	// Bit L4PEN1.
	Ethernet_ETH_MACL3L4C1R_L4PEN1 = 0x10000
	// Position of L4SPM1 field.
	Ethernet_ETH_MACL3L4C1R_L4SPM1_Pos = 0x12
	// Bit mask of L4SPM1 field.
	Ethernet_ETH_MACL3L4C1R_L4SPM1_Msk = 0x40000
	// Bit L4SPM1.
	Ethernet_ETH_MACL3L4C1R_L4SPM1 = 0x40000
	// Position of L4SPIM1 field.
	Ethernet_ETH_MACL3L4C1R_L4SPIM1_Pos = 0x13
	// Bit mask of L4SPIM1 field.
	Ethernet_ETH_MACL3L4C1R_L4SPIM1_Msk = 0x80000
	// Bit L4SPIM1.
	Ethernet_ETH_MACL3L4C1R_L4SPIM1 = 0x80000
	// Position of L4DPM1 field.
	Ethernet_ETH_MACL3L4C1R_L4DPM1_Pos = 0x14
	// Bit mask of L4DPM1 field.
	Ethernet_ETH_MACL3L4C1R_L4DPM1_Msk = 0x100000
	// Bit L4DPM1.
	Ethernet_ETH_MACL3L4C1R_L4DPM1 = 0x100000
	// Position of L4DPIM1 field.
	Ethernet_ETH_MACL3L4C1R_L4DPIM1_Pos = 0x15
	// Bit mask of L4DPIM1 field.
	Ethernet_ETH_MACL3L4C1R_L4DPIM1_Msk = 0x200000
	// Bit L4DPIM1.
	Ethernet_ETH_MACL3L4C1R_L4DPIM1 = 0x200000

	// ETH_MACL4A1R: The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core. You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.
	// Position of L4SP1 field.
	Ethernet_ETH_MACL4A1R_L4SP1_Pos = 0x0
	// Bit mask of L4SP1 field.
	Ethernet_ETH_MACL4A1R_L4SP1_Msk = 0xffff
	// Position of L4DP1 field.
	Ethernet_ETH_MACL4A1R_L4DP1_Pos = 0x10
	// Bit mask of L4DP1 field.
	Ethernet_ETH_MACL4A1R_L4DP1_Msk = 0xffff0000

	// ETH_MACL3A01R: For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
	// Position of L3A01 field.
	Ethernet_ETH_MACL3A01R_L3A01_Pos = 0x0
	// Bit mask of L3A01 field.
	Ethernet_ETH_MACL3A01R_L3A01_Msk = 0xffffffff

	// ETH_MACL3A11R: For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.
	// Position of L3A11 field.
	Ethernet_ETH_MACL3A11R_L3A11_Pos = 0x0
	// Bit mask of L3A11 field.
	Ethernet_ETH_MACL3A11R_L3A11_Msk = 0xffffffff

	// ETH_MACL3A21R: The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.
	// Position of L3A21 field.
	Ethernet_ETH_MACL3A21R_L3A21_Pos = 0x0
	// Bit mask of L3A21 field.
	Ethernet_ETH_MACL3A21R_L3A21_Msk = 0xffffffff

	// ETH_MACL3A31R: The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.
	// Position of L3A31 field.
	Ethernet_ETH_MACL3A31R_L3A31_Pos = 0x0
	// Bit mask of L3A31 field.
	Ethernet_ETH_MACL3A31R_L3A31_Msk = 0xffffffff

	// ETH_MACARPAR: The ARP Address register contains the IPv4 Destination Address of the MAC.
	// Position of ARPPA field.
	Ethernet_ETH_MACARPAR_ARPPA_Pos = 0x0
	// Bit mask of ARPPA field.
	Ethernet_ETH_MACARPAR_ARPPA_Msk = 0xffffffff

	// ETH_MACTSCR: This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver.
	// Position of TSENA field.
	Ethernet_ETH_MACTSCR_TSENA_Pos = 0x0
	// Bit mask of TSENA field.
	Ethernet_ETH_MACTSCR_TSENA_Msk = 0x1
	// Bit TSENA.
	Ethernet_ETH_MACTSCR_TSENA = 0x1
	// Position of TSCFUPDT field.
	Ethernet_ETH_MACTSCR_TSCFUPDT_Pos = 0x1
	// Bit mask of TSCFUPDT field.
	Ethernet_ETH_MACTSCR_TSCFUPDT_Msk = 0x2
	// Bit TSCFUPDT.
	Ethernet_ETH_MACTSCR_TSCFUPDT = 0x2
	// Position of TSINIT field.
	Ethernet_ETH_MACTSCR_TSINIT_Pos = 0x2
	// Bit mask of TSINIT field.
	Ethernet_ETH_MACTSCR_TSINIT_Msk = 0x4
	// Bit TSINIT.
	Ethernet_ETH_MACTSCR_TSINIT = 0x4
	// Position of TSUPDT field.
	Ethernet_ETH_MACTSCR_TSUPDT_Pos = 0x3
	// Bit mask of TSUPDT field.
	Ethernet_ETH_MACTSCR_TSUPDT_Msk = 0x8
	// Bit TSUPDT.
	Ethernet_ETH_MACTSCR_TSUPDT = 0x8
	// Position of TSADDREG field.
	Ethernet_ETH_MACTSCR_TSADDREG_Pos = 0x5
	// Bit mask of TSADDREG field.
	Ethernet_ETH_MACTSCR_TSADDREG_Msk = 0x20
	// Bit TSADDREG.
	Ethernet_ETH_MACTSCR_TSADDREG = 0x20
	// Position of TSENALL field.
	Ethernet_ETH_MACTSCR_TSENALL_Pos = 0x8
	// Bit mask of TSENALL field.
	Ethernet_ETH_MACTSCR_TSENALL_Msk = 0x100
	// Bit TSENALL.
	Ethernet_ETH_MACTSCR_TSENALL = 0x100
	// Position of TSCTRLSSR field.
	Ethernet_ETH_MACTSCR_TSCTRLSSR_Pos = 0x9
	// Bit mask of TSCTRLSSR field.
	Ethernet_ETH_MACTSCR_TSCTRLSSR_Msk = 0x200
	// Bit TSCTRLSSR.
	Ethernet_ETH_MACTSCR_TSCTRLSSR = 0x200
	// Position of TSVER2ENA field.
	Ethernet_ETH_MACTSCR_TSVER2ENA_Pos = 0xa
	// Bit mask of TSVER2ENA field.
	Ethernet_ETH_MACTSCR_TSVER2ENA_Msk = 0x400
	// Bit TSVER2ENA.
	Ethernet_ETH_MACTSCR_TSVER2ENA = 0x400
	// Position of TSIPENA field.
	Ethernet_ETH_MACTSCR_TSIPENA_Pos = 0xb
	// Bit mask of TSIPENA field.
	Ethernet_ETH_MACTSCR_TSIPENA_Msk = 0x800
	// Bit TSIPENA.
	Ethernet_ETH_MACTSCR_TSIPENA = 0x800
	// Position of TSIPV6ENA field.
	Ethernet_ETH_MACTSCR_TSIPV6ENA_Pos = 0xc
	// Bit mask of TSIPV6ENA field.
	Ethernet_ETH_MACTSCR_TSIPV6ENA_Msk = 0x1000
	// Bit TSIPV6ENA.
	Ethernet_ETH_MACTSCR_TSIPV6ENA = 0x1000
	// Position of TSIPV4ENA field.
	Ethernet_ETH_MACTSCR_TSIPV4ENA_Pos = 0xd
	// Bit mask of TSIPV4ENA field.
	Ethernet_ETH_MACTSCR_TSIPV4ENA_Msk = 0x2000
	// Bit TSIPV4ENA.
	Ethernet_ETH_MACTSCR_TSIPV4ENA = 0x2000
	// Position of TSEVNTENA field.
	Ethernet_ETH_MACTSCR_TSEVNTENA_Pos = 0xe
	// Bit mask of TSEVNTENA field.
	Ethernet_ETH_MACTSCR_TSEVNTENA_Msk = 0x4000
	// Bit TSEVNTENA.
	Ethernet_ETH_MACTSCR_TSEVNTENA = 0x4000
	// Position of TSMSTRENA field.
	Ethernet_ETH_MACTSCR_TSMSTRENA_Pos = 0xf
	// Bit mask of TSMSTRENA field.
	Ethernet_ETH_MACTSCR_TSMSTRENA_Msk = 0x8000
	// Bit TSMSTRENA.
	Ethernet_ETH_MACTSCR_TSMSTRENA = 0x8000
	// Position of SNAPTYPSEL field.
	Ethernet_ETH_MACTSCR_SNAPTYPSEL_Pos = 0x10
	// Bit mask of SNAPTYPSEL field.
	Ethernet_ETH_MACTSCR_SNAPTYPSEL_Msk = 0x30000
	// Position of TSENMACADDR field.
	Ethernet_ETH_MACTSCR_TSENMACADDR_Pos = 0x12
	// Bit mask of TSENMACADDR field.
	Ethernet_ETH_MACTSCR_TSENMACADDR_Msk = 0x40000
	// Bit TSENMACADDR.
	Ethernet_ETH_MACTSCR_TSENMACADDR = 0x40000
	// Position of CSC field.
	Ethernet_ETH_MACTSCR_CSC_Pos = 0x13
	// Bit mask of CSC field.
	Ethernet_ETH_MACTSCR_CSC_Msk = 0x80000
	// Bit CSC.
	Ethernet_ETH_MACTSCR_CSC = 0x80000
	// Position of TXTSSTSM field.
	Ethernet_ETH_MACTSCR_TXTSSTSM_Pos = 0x18
	// Bit mask of TXTSSTSM field.
	Ethernet_ETH_MACTSCR_TXTSSTSM_Msk = 0x1000000
	// Bit TXTSSTSM.
	Ethernet_ETH_MACTSCR_TXTSSTSM = 0x1000000
	// Position of AV8021ASMEN field.
	Ethernet_ETH_MACTSCR_AV8021ASMEN_Pos = 0x1c
	// Bit mask of AV8021ASMEN field.
	Ethernet_ETH_MACTSCR_AV8021ASMEN_Msk = 0x10000000
	// Bit AV8021ASMEN.
	Ethernet_ETH_MACTSCR_AV8021ASMEN = 0x10000000

	// ETH_MACSSIR: The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.
	// Position of SNSINC field.
	Ethernet_ETH_MACSSIR_SNSINC_Pos = 0x8
	// Bit mask of SNSINC field.
	Ethernet_ETH_MACSSIR_SNSINC_Msk = 0xff00
	// Position of SSINC field.
	Ethernet_ETH_MACSSIR_SSINC_Pos = 0x10
	// Bit mask of SSINC field.
	Ethernet_ETH_MACSSIR_SSINC_Msk = 0xff0000

	// ETH_MACSTSR: The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from HCLK to CSR clock). This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.
	// Position of TSS field.
	Ethernet_ETH_MACSTSR_TSS_Pos = 0x0
	// Bit mask of TSS field.
	Ethernet_ETH_MACSTSR_TSS_Msk = 0xffffffff

	// ETH_MACSTNR: The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.
	// Position of TSSS field.
	Ethernet_ETH_MACSTNR_TSSS_Pos = 0x0
	// Bit mask of TSSS field.
	Ethernet_ETH_MACSTNR_TSSS_Msk = 0x7fffffff

	// ETH_MACSTSUR: The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in ETH_MACTSCR register. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.
	// Position of TSS field.
	Ethernet_ETH_MACSTSUR_TSS_Pos = 0x0
	// Bit mask of TSS field.
	Ethernet_ETH_MACSTSUR_TSS_Msk = 0xffffffff

	// ETH_MACSTNUR: This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input.
	// Position of TSSS field.
	Ethernet_ETH_MACSTNUR_TSSS_Pos = 0x0
	// Bit mask of TSSS field.
	Ethernet_ETH_MACSTNUR_TSSS_Msk = 0x7fffffff
	// Position of ADDSUB field.
	Ethernet_ETH_MACSTNUR_ADDSUB_Pos = 0x1f
	// Bit mask of ADDSUB field.
	Ethernet_ETH_MACSTNUR_ADDSUB_Msk = 0x80000000
	// Bit ADDSUB.
	Ethernet_ETH_MACSTNUR_ADDSUB = 0x80000000

	// ETH_MACTSAR: The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the ETH_MACTSCR register). The content of this register is added to a 32-bit accumulator in every clock cycle (of HCLK) and the system time is updated whenever the accumulator overflows.
	// Position of TSAR field.
	Ethernet_ETH_MACTSAR_TSAR_Pos = 0x0
	// Bit mask of TSAR field.
	Ethernet_ETH_MACTSAR_TSAR_Msk = 0xffffffff

	// ETH_MACTSSR: The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[27:25] gets cleared when the application reads this register.
	// Position of TSSOVF field.
	Ethernet_ETH_MACTSSR_TSSOVF_Pos = 0x0
	// Bit mask of TSSOVF field.
	Ethernet_ETH_MACTSSR_TSSOVF_Msk = 0x1
	// Bit TSSOVF.
	Ethernet_ETH_MACTSSR_TSSOVF = 0x1
	// Position of TSTARGT0 field.
	Ethernet_ETH_MACTSSR_TSTARGT0_Pos = 0x1
	// Bit mask of TSTARGT0 field.
	Ethernet_ETH_MACTSSR_TSTARGT0_Msk = 0x2
	// Bit TSTARGT0.
	Ethernet_ETH_MACTSSR_TSTARGT0 = 0x2
	// Position of AUXTSTRIG field.
	Ethernet_ETH_MACTSSR_AUXTSTRIG_Pos = 0x2
	// Bit mask of AUXTSTRIG field.
	Ethernet_ETH_MACTSSR_AUXTSTRIG_Msk = 0x4
	// Bit AUXTSTRIG.
	Ethernet_ETH_MACTSSR_AUXTSTRIG = 0x4
	// Position of TSTRGTERR0 field.
	Ethernet_ETH_MACTSSR_TSTRGTERR0_Pos = 0x3
	// Bit mask of TSTRGTERR0 field.
	Ethernet_ETH_MACTSSR_TSTRGTERR0_Msk = 0x8
	// Bit TSTRGTERR0.
	Ethernet_ETH_MACTSSR_TSTRGTERR0 = 0x8
	// Position of TXTSSIS field.
	Ethernet_ETH_MACTSSR_TXTSSIS_Pos = 0xf
	// Bit mask of TXTSSIS field.
	Ethernet_ETH_MACTSSR_TXTSSIS_Msk = 0x8000
	// Bit TXTSSIS.
	Ethernet_ETH_MACTSSR_TXTSSIS = 0x8000
	// Position of ATSSTN field.
	Ethernet_ETH_MACTSSR_ATSSTN_Pos = 0x10
	// Bit mask of ATSSTN field.
	Ethernet_ETH_MACTSSR_ATSSTN_Msk = 0xf0000
	// Position of ATSSTM field.
	Ethernet_ETH_MACTSSR_ATSSTM_Pos = 0x18
	// Bit mask of ATSSTM field.
	Ethernet_ETH_MACTSSR_ATSSTM_Msk = 0x1000000
	// Bit ATSSTM.
	Ethernet_ETH_MACTSSR_ATSSTM = 0x1000000
	// Position of ATSNS field.
	Ethernet_ETH_MACTSSR_ATSNS_Pos = 0x19
	// Bit mask of ATSNS field.
	Ethernet_ETH_MACTSSR_ATSNS_Msk = 0x3e000000

	// ETH_MACTxTSSNR: This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled.
	// Position of TXTSSLO field.
	Ethernet_ETH_MACTxTSSNR_TXTSSLO_Pos = 0x0
	// Bit mask of TXTSSLO field.
	Ethernet_ETH_MACTxTSSNR_TXTSSLO_Msk = 0x7fffffff
	// Position of TXTSSMIS field.
	Ethernet_ETH_MACTxTSSNR_TXTSSMIS_Pos = 0x1f
	// Bit mask of TXTSSMIS field.
	Ethernet_ETH_MACTxTSSNR_TXTSSMIS_Msk = 0x80000000
	// Bit TXTSSMIS.
	Ethernet_ETH_MACTxTSSNR_TXTSSMIS = 0x80000000

	// ETH_MACTxTSSSR: The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted.
	// Position of TXTSSHI field.
	Ethernet_ETH_MACTxTSSSR_TXTSSHI_Pos = 0x0
	// Bit mask of TXTSSHI field.
	Ethernet_ETH_MACTxTSSSR_TXTSSHI_Msk = 0xffffffff

	// ETH_MACACR: The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot.
	// Position of ATSFC field.
	Ethernet_ETH_MACACR_ATSFC_Pos = 0x0
	// Bit mask of ATSFC field.
	Ethernet_ETH_MACACR_ATSFC_Msk = 0x1
	// Bit ATSFC.
	Ethernet_ETH_MACACR_ATSFC = 0x1
	// Position of ATSEN0 field.
	Ethernet_ETH_MACACR_ATSEN0_Pos = 0x4
	// Bit mask of ATSEN0 field.
	Ethernet_ETH_MACACR_ATSEN0_Msk = 0x10
	// Bit ATSEN0.
	Ethernet_ETH_MACACR_ATSEN0 = 0x10
	// Position of ATSEN1 field.
	Ethernet_ETH_MACACR_ATSEN1_Pos = 0x5
	// Bit mask of ATSEN1 field.
	Ethernet_ETH_MACACR_ATSEN1_Msk = 0x20
	// Bit ATSEN1.
	Ethernet_ETH_MACACR_ATSEN1 = 0x20
	// Position of ATSEN2 field.
	Ethernet_ETH_MACACR_ATSEN2_Pos = 0x6
	// Bit mask of ATSEN2 field.
	Ethernet_ETH_MACACR_ATSEN2_Msk = 0x40
	// Bit ATSEN2.
	Ethernet_ETH_MACACR_ATSEN2 = 0x40
	// Position of ATSEN3 field.
	Ethernet_ETH_MACACR_ATSEN3_Pos = 0x7
	// Bit mask of ATSEN3 field.
	Ethernet_ETH_MACACR_ATSEN3_Msk = 0x80
	// Bit ATSEN3.
	Ethernet_ETH_MACACR_ATSEN3 = 0x80

	// ETH_MACATSNR: The Auxiliary Timestamp Nanoseconds register, along with ETH_MACATSSR, gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4 words. You can store multiple snapshots in this FIFO. Bits[29:25] in ETH_MACTSSR indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read.
	// Position of AUXTSLO field.
	Ethernet_ETH_MACATSNR_AUXTSLO_Pos = 0x0
	// Bit mask of AUXTSLO field.
	Ethernet_ETH_MACATSNR_AUXTSLO_Msk = 0x7fffffff

	// ETH_MACATSSR: The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register.
	// Position of AUXTSHI field.
	Ethernet_ETH_MACATSSR_AUXTSHI_Pos = 0x0
	// Bit mask of AUXTSHI field.
	Ethernet_ETH_MACATSSR_AUXTSHI_Msk = 0xffffffff

	// ETH_MACTSIACR: The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages.
	// Position of OSTIAC field.
	Ethernet_ETH_MACTSIACR_OSTIAC_Pos = 0x0
	// Bit mask of OSTIAC field.
	Ethernet_ETH_MACTSIACR_OSTIAC_Msk = 0xffffffff

	// ETH_MACTSEACR: The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages.
	// Position of OSTEAC field.
	Ethernet_ETH_MACTSEACR_OSTEAC_Pos = 0x0
	// Bit mask of OSTEAC field.
	Ethernet_ETH_MACTSEACR_OSTEAC_Msk = 0xffffffff

	// ETH_MACTSICNR: This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path.
	// Position of TSIC field.
	Ethernet_ETH_MACTSICNR_TSIC_Pos = 0x0
	// Bit mask of TSIC field.
	Ethernet_ETH_MACTSICNR_TSIC_Msk = 0xffffffff

	// ETH_MACTSECNR: This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path.
	// Position of TSEC field.
	Ethernet_ETH_MACTSECNR_TSEC_Pos = 0x0
	// Bit mask of TSEC field.
	Ethernet_ETH_MACTSECNR_TSEC_Msk = 0xffffffff

	// ETH_MACPPSCR: The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected.
	// Position of PPSCTRL field.
	Ethernet_ETH_MACPPSCR_PPSCTRL_Pos = 0x0
	// Bit mask of PPSCTRL field.
	Ethernet_ETH_MACPPSCR_PPSCTRL_Msk = 0xf
	// Position of PPSEN0 field.
	Ethernet_ETH_MACPPSCR_PPSEN0_Pos = 0x4
	// Bit mask of PPSEN0 field.
	Ethernet_ETH_MACPPSCR_PPSEN0_Msk = 0x10
	// Bit PPSEN0.
	Ethernet_ETH_MACPPSCR_PPSEN0 = 0x10
	// Position of TRGTMODSEL0 field.
	Ethernet_ETH_MACPPSCR_TRGTMODSEL0_Pos = 0x5
	// Bit mask of TRGTMODSEL0 field.
	Ethernet_ETH_MACPPSCR_TRGTMODSEL0_Msk = 0x60

	// ETH_MACPPSTTSR: The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of ETH_MACTSSR] when the system time exceeds the value programmed in these registers.
	// Position of TSTRH0 field.
	Ethernet_ETH_MACPPSTTSR_TSTRH0_Pos = 0x0
	// Bit mask of TSTRH0 field.
	Ethernet_ETH_MACPPSTTSR_TSTRH0_Msk = 0xffffffff

	// ETH_MACPPSTTNR: The PPS Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected.
	// Position of TTSL0 field.
	Ethernet_ETH_MACPPSTTNR_TTSL0_Pos = 0x0
	// Bit mask of TTSL0 field.
	Ethernet_ETH_MACPPSTTNR_TTSL0_Msk = 0x7fffffff
	// Position of TRGTBUSY0 field.
	Ethernet_ETH_MACPPSTTNR_TRGTBUSY0_Pos = 0x1f
	// Bit mask of TRGTBUSY0 field.
	Ethernet_ETH_MACPPSTTNR_TRGTBUSY0_Msk = 0x80000000
	// Bit TRGTBUSY0.
	Ethernet_ETH_MACPPSTTNR_TRGTBUSY0 = 0x80000000

	// ETH_MACPPSIR: The PPS Interval register contains the number of units of sub-second increment value between the rising edges of PPS signal output (ptp_pps_o[0]).
	// Position of PPSINT0 field.
	Ethernet_ETH_MACPPSIR_PPSINT0_Pos = 0x0
	// Bit mask of PPSINT0 field.
	Ethernet_ETH_MACPPSIR_PPSINT0_Msk = 0xffffffff

	// ETH_MACPPSWR: The PPS Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS signal output (ptp_pps_o).
	// Position of PPSWIDTH0 field.
	Ethernet_ETH_MACPPSWR_PPSWIDTH0_Pos = 0x0
	// Bit mask of PPSWIDTH0 field.
	Ethernet_ETH_MACPPSWR_PPSWIDTH0_Msk = 0xffffffff

	// ETH_MACPOCR: This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected.
	// Position of PTOEN field.
	Ethernet_ETH_MACPOCR_PTOEN_Pos = 0x0
	// Bit mask of PTOEN field.
	Ethernet_ETH_MACPOCR_PTOEN_Msk = 0x1
	// Bit PTOEN.
	Ethernet_ETH_MACPOCR_PTOEN = 0x1
	// Position of ASYNCEN field.
	Ethernet_ETH_MACPOCR_ASYNCEN_Pos = 0x1
	// Bit mask of ASYNCEN field.
	Ethernet_ETH_MACPOCR_ASYNCEN_Msk = 0x2
	// Bit ASYNCEN.
	Ethernet_ETH_MACPOCR_ASYNCEN = 0x2
	// Position of APDREQEN field.
	Ethernet_ETH_MACPOCR_APDREQEN_Pos = 0x2
	// Bit mask of APDREQEN field.
	Ethernet_ETH_MACPOCR_APDREQEN_Msk = 0x4
	// Bit APDREQEN.
	Ethernet_ETH_MACPOCR_APDREQEN = 0x4
	// Position of ASYNCTRIG field.
	Ethernet_ETH_MACPOCR_ASYNCTRIG_Pos = 0x4
	// Bit mask of ASYNCTRIG field.
	Ethernet_ETH_MACPOCR_ASYNCTRIG_Msk = 0x10
	// Bit ASYNCTRIG.
	Ethernet_ETH_MACPOCR_ASYNCTRIG = 0x10
	// Position of APDREQTRIG field.
	Ethernet_ETH_MACPOCR_APDREQTRIG_Pos = 0x5
	// Bit mask of APDREQTRIG field.
	Ethernet_ETH_MACPOCR_APDREQTRIG_Msk = 0x20
	// Bit APDREQTRIG.
	Ethernet_ETH_MACPOCR_APDREQTRIG = 0x20
	// Position of DRRDIS field.
	Ethernet_ETH_MACPOCR_DRRDIS_Pos = 0x6
	// Bit mask of DRRDIS field.
	Ethernet_ETH_MACPOCR_DRRDIS_Msk = 0x40
	// Bit DRRDIS.
	Ethernet_ETH_MACPOCR_DRRDIS = 0x40
	// Position of DN field.
	Ethernet_ETH_MACPOCR_DN_Pos = 0x8
	// Bit mask of DN field.
	Ethernet_ETH_MACPOCR_DN_Msk = 0xff00

	// ETH_MACSPI0R: This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.
	// Position of SPI0 field.
	Ethernet_ETH_MACSPI0R_SPI0_Pos = 0x0
	// Bit mask of SPI0 field.
	Ethernet_ETH_MACSPI0R_SPI0_Msk = 0xffffffff

	// ETH_MACSPI1R: This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.
	// Position of SPI1 field.
	Ethernet_ETH_MACSPI1R_SPI1_Pos = 0x0
	// Bit mask of SPI1 field.
	Ethernet_ETH_MACSPI1R_SPI1_Msk = 0xffffffff

	// ETH_MACSPI2R: This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node.
	// Position of SPI2 field.
	Ethernet_ETH_MACSPI2R_SPI2_Pos = 0x0
	// Bit mask of SPI2 field.
	Ethernet_ETH_MACSPI2R_SPI2_Msk = 0xffff

	// ETH_MACLMIR: This register contains the periodic intervals for automatic PTP packet generation.
	// Position of LSI field.
	Ethernet_ETH_MACLMIR_LSI_Pos = 0x0
	// Bit mask of LSI field.
	Ethernet_ETH_MACLMIR_LSI_Msk = 0xff
	// Position of DRSYNCR field.
	Ethernet_ETH_MACLMIR_DRSYNCR_Pos = 0x8
	// Bit mask of DRSYNCR field.
	Ethernet_ETH_MACLMIR_DRSYNCR_Msk = 0x700
	// Position of LMPDRI field.
	Ethernet_ETH_MACLMIR_LMPDRI_Pos = 0x18
	// Bit mask of LMPDRI field.
	Ethernet_ETH_MACLMIR_LMPDRI_Msk = 0xff000000
)

// Bitfields for ETZPC: ETZPC
const (
	// ETZPC_TZMA0_SIZE: ETZPC ROM secure size definition
	// Position of R0SIZE field.
	ETZPC_ETZPC_TZMA0_SIZE_R0SIZE_Pos = 0x0
	// Bit mask of R0SIZE field.
	ETZPC_ETZPC_TZMA0_SIZE_R0SIZE_Msk = 0x3ff
	// Position of LOCK field.
	ETZPC_ETZPC_TZMA0_SIZE_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	ETZPC_ETZPC_TZMA0_SIZE_LOCK_Msk = 0x80000000
	// Bit LOCK.
	ETZPC_ETZPC_TZMA0_SIZE_LOCK = 0x80000000

	// ETZPC_TZMA1_SIZE: ETZPC RAM secure size definition
	// Position of R0SIZE field.
	ETZPC_ETZPC_TZMA1_SIZE_R0SIZE_Pos = 0x0
	// Bit mask of R0SIZE field.
	ETZPC_ETZPC_TZMA1_SIZE_R0SIZE_Msk = 0x3ff
	// Position of LOCK field.
	ETZPC_ETZPC_TZMA1_SIZE_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	ETZPC_ETZPC_TZMA1_SIZE_LOCK_Msk = 0x80000000
	// Bit LOCK.
	ETZPC_ETZPC_TZMA1_SIZE_LOCK = 0x80000000

	// ETZPC_DECPROT0: Register reset values
	// Position of DECPROT0 field.
	ETZPC_ETZPC_DECPROT0_DECPROT0_Pos = 0x0
	// Bit mask of DECPROT0 field.
	ETZPC_ETZPC_DECPROT0_DECPROT0_Msk = 0x3
	// Position of DECPROT1 field.
	ETZPC_ETZPC_DECPROT0_DECPROT1_Pos = 0x2
	// Bit mask of DECPROT1 field.
	ETZPC_ETZPC_DECPROT0_DECPROT1_Msk = 0xc
	// Position of DECPROT2 field.
	ETZPC_ETZPC_DECPROT0_DECPROT2_Pos = 0x4
	// Bit mask of DECPROT2 field.
	ETZPC_ETZPC_DECPROT0_DECPROT2_Msk = 0x30
	// Position of DECPROT3 field.
	ETZPC_ETZPC_DECPROT0_DECPROT3_Pos = 0x6
	// Bit mask of DECPROT3 field.
	ETZPC_ETZPC_DECPROT0_DECPROT3_Msk = 0xc0
	// Position of DECPROT4 field.
	ETZPC_ETZPC_DECPROT0_DECPROT4_Pos = 0x8
	// Bit mask of DECPROT4 field.
	ETZPC_ETZPC_DECPROT0_DECPROT4_Msk = 0x300
	// Position of DECPROT5 field.
	ETZPC_ETZPC_DECPROT0_DECPROT5_Pos = 0xa
	// Bit mask of DECPROT5 field.
	ETZPC_ETZPC_DECPROT0_DECPROT5_Msk = 0xc00
	// Position of DECPROT6 field.
	ETZPC_ETZPC_DECPROT0_DECPROT6_Pos = 0xc
	// Bit mask of DECPROT6 field.
	ETZPC_ETZPC_DECPROT0_DECPROT6_Msk = 0x3000
	// Position of DECPROT7 field.
	ETZPC_ETZPC_DECPROT0_DECPROT7_Pos = 0xe
	// Bit mask of DECPROT7 field.
	ETZPC_ETZPC_DECPROT0_DECPROT7_Msk = 0xc000
	// Position of DECPROT8 field.
	ETZPC_ETZPC_DECPROT0_DECPROT8_Pos = 0x10
	// Bit mask of DECPROT8 field.
	ETZPC_ETZPC_DECPROT0_DECPROT8_Msk = 0x30000
	// Position of DECPROT9 field.
	ETZPC_ETZPC_DECPROT0_DECPROT9_Pos = 0x12
	// Bit mask of DECPROT9 field.
	ETZPC_ETZPC_DECPROT0_DECPROT9_Msk = 0xc0000
	// Position of DECPROT10 field.
	ETZPC_ETZPC_DECPROT0_DECPROT10_Pos = 0x14
	// Bit mask of DECPROT10 field.
	ETZPC_ETZPC_DECPROT0_DECPROT10_Msk = 0x300000
	// Position of DECPROT11 field.
	ETZPC_ETZPC_DECPROT0_DECPROT11_Pos = 0x16
	// Bit mask of DECPROT11 field.
	ETZPC_ETZPC_DECPROT0_DECPROT11_Msk = 0xc00000
	// Position of DECPROT12 field.
	ETZPC_ETZPC_DECPROT0_DECPROT12_Pos = 0x18
	// Bit mask of DECPROT12 field.
	ETZPC_ETZPC_DECPROT0_DECPROT12_Msk = 0x3000000
	// Position of DECPROT13 field.
	ETZPC_ETZPC_DECPROT0_DECPROT13_Pos = 0x1a
	// Bit mask of DECPROT13 field.
	ETZPC_ETZPC_DECPROT0_DECPROT13_Msk = 0xc000000
	// Position of DECPROT14 field.
	ETZPC_ETZPC_DECPROT0_DECPROT14_Pos = 0x1c
	// Bit mask of DECPROT14 field.
	ETZPC_ETZPC_DECPROT0_DECPROT14_Msk = 0x30000000
	// Position of DECPROT15 field.
	ETZPC_ETZPC_DECPROT0_DECPROT15_Pos = 0x1e
	// Bit mask of DECPROT15 field.
	ETZPC_ETZPC_DECPROT0_DECPROT15_Msk = 0xc0000000

	// ETZPC_DECPROT1: Register reset values
	// Position of DECPROT0 field.
	ETZPC_ETZPC_DECPROT1_DECPROT0_Pos = 0x0
	// Bit mask of DECPROT0 field.
	ETZPC_ETZPC_DECPROT1_DECPROT0_Msk = 0x3
	// Position of DECPROT1 field.
	ETZPC_ETZPC_DECPROT1_DECPROT1_Pos = 0x2
	// Bit mask of DECPROT1 field.
	ETZPC_ETZPC_DECPROT1_DECPROT1_Msk = 0xc
	// Position of DECPROT2 field.
	ETZPC_ETZPC_DECPROT1_DECPROT2_Pos = 0x4
	// Bit mask of DECPROT2 field.
	ETZPC_ETZPC_DECPROT1_DECPROT2_Msk = 0x30
	// Position of DECPROT3 field.
	ETZPC_ETZPC_DECPROT1_DECPROT3_Pos = 0x6
	// Bit mask of DECPROT3 field.
	ETZPC_ETZPC_DECPROT1_DECPROT3_Msk = 0xc0
	// Position of DECPROT4 field.
	ETZPC_ETZPC_DECPROT1_DECPROT4_Pos = 0x8
	// Bit mask of DECPROT4 field.
	ETZPC_ETZPC_DECPROT1_DECPROT4_Msk = 0x300
	// Position of DECPROT5 field.
	ETZPC_ETZPC_DECPROT1_DECPROT5_Pos = 0xa
	// Bit mask of DECPROT5 field.
	ETZPC_ETZPC_DECPROT1_DECPROT5_Msk = 0xc00
	// Position of DECPROT6 field.
	ETZPC_ETZPC_DECPROT1_DECPROT6_Pos = 0xc
	// Bit mask of DECPROT6 field.
	ETZPC_ETZPC_DECPROT1_DECPROT6_Msk = 0x3000
	// Position of DECPROT7 field.
	ETZPC_ETZPC_DECPROT1_DECPROT7_Pos = 0xe
	// Bit mask of DECPROT7 field.
	ETZPC_ETZPC_DECPROT1_DECPROT7_Msk = 0xc000
	// Position of DECPROT8 field.
	ETZPC_ETZPC_DECPROT1_DECPROT8_Pos = 0x10
	// Bit mask of DECPROT8 field.
	ETZPC_ETZPC_DECPROT1_DECPROT8_Msk = 0x30000
	// Position of DECPROT9 field.
	ETZPC_ETZPC_DECPROT1_DECPROT9_Pos = 0x12
	// Bit mask of DECPROT9 field.
	ETZPC_ETZPC_DECPROT1_DECPROT9_Msk = 0xc0000
	// Position of DECPROT10 field.
	ETZPC_ETZPC_DECPROT1_DECPROT10_Pos = 0x14
	// Bit mask of DECPROT10 field.
	ETZPC_ETZPC_DECPROT1_DECPROT10_Msk = 0x300000
	// Position of DECPROT11 field.
	ETZPC_ETZPC_DECPROT1_DECPROT11_Pos = 0x16
	// Bit mask of DECPROT11 field.
	ETZPC_ETZPC_DECPROT1_DECPROT11_Msk = 0xc00000
	// Position of DECPROT12 field.
	ETZPC_ETZPC_DECPROT1_DECPROT12_Pos = 0x18
	// Bit mask of DECPROT12 field.
	ETZPC_ETZPC_DECPROT1_DECPROT12_Msk = 0x3000000
	// Position of DECPROT13 field.
	ETZPC_ETZPC_DECPROT1_DECPROT13_Pos = 0x1a
	// Bit mask of DECPROT13 field.
	ETZPC_ETZPC_DECPROT1_DECPROT13_Msk = 0xc000000
	// Position of DECPROT14 field.
	ETZPC_ETZPC_DECPROT1_DECPROT14_Pos = 0x1c
	// Bit mask of DECPROT14 field.
	ETZPC_ETZPC_DECPROT1_DECPROT14_Msk = 0x30000000
	// Position of DECPROT15 field.
	ETZPC_ETZPC_DECPROT1_DECPROT15_Pos = 0x1e
	// Bit mask of DECPROT15 field.
	ETZPC_ETZPC_DECPROT1_DECPROT15_Msk = 0xc0000000

	// ETZPC_DECPROT2: Register reset values
	// Position of DECPROT0 field.
	ETZPC_ETZPC_DECPROT2_DECPROT0_Pos = 0x0
	// Bit mask of DECPROT0 field.
	ETZPC_ETZPC_DECPROT2_DECPROT0_Msk = 0x3
	// Position of DECPROT1 field.
	ETZPC_ETZPC_DECPROT2_DECPROT1_Pos = 0x2
	// Bit mask of DECPROT1 field.
	ETZPC_ETZPC_DECPROT2_DECPROT1_Msk = 0xc
	// Position of DECPROT2 field.
	ETZPC_ETZPC_DECPROT2_DECPROT2_Pos = 0x4
	// Bit mask of DECPROT2 field.
	ETZPC_ETZPC_DECPROT2_DECPROT2_Msk = 0x30
	// Position of DECPROT3 field.
	ETZPC_ETZPC_DECPROT2_DECPROT3_Pos = 0x6
	// Bit mask of DECPROT3 field.
	ETZPC_ETZPC_DECPROT2_DECPROT3_Msk = 0xc0
	// Position of DECPROT4 field.
	ETZPC_ETZPC_DECPROT2_DECPROT4_Pos = 0x8
	// Bit mask of DECPROT4 field.
	ETZPC_ETZPC_DECPROT2_DECPROT4_Msk = 0x300
	// Position of DECPROT5 field.
	ETZPC_ETZPC_DECPROT2_DECPROT5_Pos = 0xa
	// Bit mask of DECPROT5 field.
	ETZPC_ETZPC_DECPROT2_DECPROT5_Msk = 0xc00
	// Position of DECPROT6 field.
	ETZPC_ETZPC_DECPROT2_DECPROT6_Pos = 0xc
	// Bit mask of DECPROT6 field.
	ETZPC_ETZPC_DECPROT2_DECPROT6_Msk = 0x3000
	// Position of DECPROT7 field.
	ETZPC_ETZPC_DECPROT2_DECPROT7_Pos = 0xe
	// Bit mask of DECPROT7 field.
	ETZPC_ETZPC_DECPROT2_DECPROT7_Msk = 0xc000
	// Position of DECPROT8 field.
	ETZPC_ETZPC_DECPROT2_DECPROT8_Pos = 0x10
	// Bit mask of DECPROT8 field.
	ETZPC_ETZPC_DECPROT2_DECPROT8_Msk = 0x30000
	// Position of DECPROT9 field.
	ETZPC_ETZPC_DECPROT2_DECPROT9_Pos = 0x12
	// Bit mask of DECPROT9 field.
	ETZPC_ETZPC_DECPROT2_DECPROT9_Msk = 0xc0000
	// Position of DECPROT10 field.
	ETZPC_ETZPC_DECPROT2_DECPROT10_Pos = 0x14
	// Bit mask of DECPROT10 field.
	ETZPC_ETZPC_DECPROT2_DECPROT10_Msk = 0x300000
	// Position of DECPROT11 field.
	ETZPC_ETZPC_DECPROT2_DECPROT11_Pos = 0x16
	// Bit mask of DECPROT11 field.
	ETZPC_ETZPC_DECPROT2_DECPROT11_Msk = 0xc00000
	// Position of DECPROT12 field.
	ETZPC_ETZPC_DECPROT2_DECPROT12_Pos = 0x18
	// Bit mask of DECPROT12 field.
	ETZPC_ETZPC_DECPROT2_DECPROT12_Msk = 0x3000000
	// Position of DECPROT13 field.
	ETZPC_ETZPC_DECPROT2_DECPROT13_Pos = 0x1a
	// Bit mask of DECPROT13 field.
	ETZPC_ETZPC_DECPROT2_DECPROT13_Msk = 0xc000000
	// Position of DECPROT14 field.
	ETZPC_ETZPC_DECPROT2_DECPROT14_Pos = 0x1c
	// Bit mask of DECPROT14 field.
	ETZPC_ETZPC_DECPROT2_DECPROT14_Msk = 0x30000000
	// Position of DECPROT15 field.
	ETZPC_ETZPC_DECPROT2_DECPROT15_Pos = 0x1e
	// Bit mask of DECPROT15 field.
	ETZPC_ETZPC_DECPROT2_DECPROT15_Msk = 0xc0000000

	// ETZPC_DECPROT3: Register reset values
	// Position of DECPROT0 field.
	ETZPC_ETZPC_DECPROT3_DECPROT0_Pos = 0x0
	// Bit mask of DECPROT0 field.
	ETZPC_ETZPC_DECPROT3_DECPROT0_Msk = 0x3
	// Position of DECPROT1 field.
	ETZPC_ETZPC_DECPROT3_DECPROT1_Pos = 0x2
	// Bit mask of DECPROT1 field.
	ETZPC_ETZPC_DECPROT3_DECPROT1_Msk = 0xc
	// Position of DECPROT2 field.
	ETZPC_ETZPC_DECPROT3_DECPROT2_Pos = 0x4
	// Bit mask of DECPROT2 field.
	ETZPC_ETZPC_DECPROT3_DECPROT2_Msk = 0x30
	// Position of DECPROT3 field.
	ETZPC_ETZPC_DECPROT3_DECPROT3_Pos = 0x6
	// Bit mask of DECPROT3 field.
	ETZPC_ETZPC_DECPROT3_DECPROT3_Msk = 0xc0
	// Position of DECPROT4 field.
	ETZPC_ETZPC_DECPROT3_DECPROT4_Pos = 0x8
	// Bit mask of DECPROT4 field.
	ETZPC_ETZPC_DECPROT3_DECPROT4_Msk = 0x300
	// Position of DECPROT5 field.
	ETZPC_ETZPC_DECPROT3_DECPROT5_Pos = 0xa
	// Bit mask of DECPROT5 field.
	ETZPC_ETZPC_DECPROT3_DECPROT5_Msk = 0xc00
	// Position of DECPROT6 field.
	ETZPC_ETZPC_DECPROT3_DECPROT6_Pos = 0xc
	// Bit mask of DECPROT6 field.
	ETZPC_ETZPC_DECPROT3_DECPROT6_Msk = 0x3000
	// Position of DECPROT7 field.
	ETZPC_ETZPC_DECPROT3_DECPROT7_Pos = 0xe
	// Bit mask of DECPROT7 field.
	ETZPC_ETZPC_DECPROT3_DECPROT7_Msk = 0xc000
	// Position of DECPROT8 field.
	ETZPC_ETZPC_DECPROT3_DECPROT8_Pos = 0x10
	// Bit mask of DECPROT8 field.
	ETZPC_ETZPC_DECPROT3_DECPROT8_Msk = 0x30000
	// Position of DECPROT9 field.
	ETZPC_ETZPC_DECPROT3_DECPROT9_Pos = 0x12
	// Bit mask of DECPROT9 field.
	ETZPC_ETZPC_DECPROT3_DECPROT9_Msk = 0xc0000
	// Position of DECPROT10 field.
	ETZPC_ETZPC_DECPROT3_DECPROT10_Pos = 0x14
	// Bit mask of DECPROT10 field.
	ETZPC_ETZPC_DECPROT3_DECPROT10_Msk = 0x300000
	// Position of DECPROT11 field.
	ETZPC_ETZPC_DECPROT3_DECPROT11_Pos = 0x16
	// Bit mask of DECPROT11 field.
	ETZPC_ETZPC_DECPROT3_DECPROT11_Msk = 0xc00000
	// Position of DECPROT12 field.
	ETZPC_ETZPC_DECPROT3_DECPROT12_Pos = 0x18
	// Bit mask of DECPROT12 field.
	ETZPC_ETZPC_DECPROT3_DECPROT12_Msk = 0x3000000
	// Position of DECPROT13 field.
	ETZPC_ETZPC_DECPROT3_DECPROT13_Pos = 0x1a
	// Bit mask of DECPROT13 field.
	ETZPC_ETZPC_DECPROT3_DECPROT13_Msk = 0xc000000
	// Position of DECPROT14 field.
	ETZPC_ETZPC_DECPROT3_DECPROT14_Pos = 0x1c
	// Bit mask of DECPROT14 field.
	ETZPC_ETZPC_DECPROT3_DECPROT14_Msk = 0x30000000
	// Position of DECPROT15 field.
	ETZPC_ETZPC_DECPROT3_DECPROT15_Pos = 0x1e
	// Bit mask of DECPROT15 field.
	ETZPC_ETZPC_DECPROT3_DECPROT15_Msk = 0xc0000000

	// ETZPC_DECPROT4: Register reset values
	// Position of DECPROT0 field.
	ETZPC_ETZPC_DECPROT4_DECPROT0_Pos = 0x0
	// Bit mask of DECPROT0 field.
	ETZPC_ETZPC_DECPROT4_DECPROT0_Msk = 0x3
	// Position of DECPROT1 field.
	ETZPC_ETZPC_DECPROT4_DECPROT1_Pos = 0x2
	// Bit mask of DECPROT1 field.
	ETZPC_ETZPC_DECPROT4_DECPROT1_Msk = 0xc
	// Position of DECPROT2 field.
	ETZPC_ETZPC_DECPROT4_DECPROT2_Pos = 0x4
	// Bit mask of DECPROT2 field.
	ETZPC_ETZPC_DECPROT4_DECPROT2_Msk = 0x30
	// Position of DECPROT3 field.
	ETZPC_ETZPC_DECPROT4_DECPROT3_Pos = 0x6
	// Bit mask of DECPROT3 field.
	ETZPC_ETZPC_DECPROT4_DECPROT3_Msk = 0xc0
	// Position of DECPROT4 field.
	ETZPC_ETZPC_DECPROT4_DECPROT4_Pos = 0x8
	// Bit mask of DECPROT4 field.
	ETZPC_ETZPC_DECPROT4_DECPROT4_Msk = 0x300
	// Position of DECPROT5 field.
	ETZPC_ETZPC_DECPROT4_DECPROT5_Pos = 0xa
	// Bit mask of DECPROT5 field.
	ETZPC_ETZPC_DECPROT4_DECPROT5_Msk = 0xc00
	// Position of DECPROT6 field.
	ETZPC_ETZPC_DECPROT4_DECPROT6_Pos = 0xc
	// Bit mask of DECPROT6 field.
	ETZPC_ETZPC_DECPROT4_DECPROT6_Msk = 0x3000
	// Position of DECPROT7 field.
	ETZPC_ETZPC_DECPROT4_DECPROT7_Pos = 0xe
	// Bit mask of DECPROT7 field.
	ETZPC_ETZPC_DECPROT4_DECPROT7_Msk = 0xc000
	// Position of DECPROT8 field.
	ETZPC_ETZPC_DECPROT4_DECPROT8_Pos = 0x10
	// Bit mask of DECPROT8 field.
	ETZPC_ETZPC_DECPROT4_DECPROT8_Msk = 0x30000
	// Position of DECPROT9 field.
	ETZPC_ETZPC_DECPROT4_DECPROT9_Pos = 0x12
	// Bit mask of DECPROT9 field.
	ETZPC_ETZPC_DECPROT4_DECPROT9_Msk = 0xc0000
	// Position of DECPROT10 field.
	ETZPC_ETZPC_DECPROT4_DECPROT10_Pos = 0x14
	// Bit mask of DECPROT10 field.
	ETZPC_ETZPC_DECPROT4_DECPROT10_Msk = 0x300000
	// Position of DECPROT11 field.
	ETZPC_ETZPC_DECPROT4_DECPROT11_Pos = 0x16
	// Bit mask of DECPROT11 field.
	ETZPC_ETZPC_DECPROT4_DECPROT11_Msk = 0xc00000
	// Position of DECPROT12 field.
	ETZPC_ETZPC_DECPROT4_DECPROT12_Pos = 0x18
	// Bit mask of DECPROT12 field.
	ETZPC_ETZPC_DECPROT4_DECPROT12_Msk = 0x3000000
	// Position of DECPROT13 field.
	ETZPC_ETZPC_DECPROT4_DECPROT13_Pos = 0x1a
	// Bit mask of DECPROT13 field.
	ETZPC_ETZPC_DECPROT4_DECPROT13_Msk = 0xc000000
	// Position of DECPROT14 field.
	ETZPC_ETZPC_DECPROT4_DECPROT14_Pos = 0x1c
	// Bit mask of DECPROT14 field.
	ETZPC_ETZPC_DECPROT4_DECPROT14_Msk = 0x30000000
	// Position of DECPROT15 field.
	ETZPC_ETZPC_DECPROT4_DECPROT15_Pos = 0x1e
	// Bit mask of DECPROT15 field.
	ETZPC_ETZPC_DECPROT4_DECPROT15_Msk = 0xc0000000

	// ETZPC_DECPROT5: Register reset values
	// Position of DECPROT0 field.
	ETZPC_ETZPC_DECPROT5_DECPROT0_Pos = 0x0
	// Bit mask of DECPROT0 field.
	ETZPC_ETZPC_DECPROT5_DECPROT0_Msk = 0x3
	// Position of DECPROT1 field.
	ETZPC_ETZPC_DECPROT5_DECPROT1_Pos = 0x2
	// Bit mask of DECPROT1 field.
	ETZPC_ETZPC_DECPROT5_DECPROT1_Msk = 0xc
	// Position of DECPROT2 field.
	ETZPC_ETZPC_DECPROT5_DECPROT2_Pos = 0x4
	// Bit mask of DECPROT2 field.
	ETZPC_ETZPC_DECPROT5_DECPROT2_Msk = 0x30
	// Position of DECPROT3 field.
	ETZPC_ETZPC_DECPROT5_DECPROT3_Pos = 0x6
	// Bit mask of DECPROT3 field.
	ETZPC_ETZPC_DECPROT5_DECPROT3_Msk = 0xc0
	// Position of DECPROT4 field.
	ETZPC_ETZPC_DECPROT5_DECPROT4_Pos = 0x8
	// Bit mask of DECPROT4 field.
	ETZPC_ETZPC_DECPROT5_DECPROT4_Msk = 0x300
	// Position of DECPROT5 field.
	ETZPC_ETZPC_DECPROT5_DECPROT5_Pos = 0xa
	// Bit mask of DECPROT5 field.
	ETZPC_ETZPC_DECPROT5_DECPROT5_Msk = 0xc00
	// Position of DECPROT6 field.
	ETZPC_ETZPC_DECPROT5_DECPROT6_Pos = 0xc
	// Bit mask of DECPROT6 field.
	ETZPC_ETZPC_DECPROT5_DECPROT6_Msk = 0x3000
	// Position of DECPROT7 field.
	ETZPC_ETZPC_DECPROT5_DECPROT7_Pos = 0xe
	// Bit mask of DECPROT7 field.
	ETZPC_ETZPC_DECPROT5_DECPROT7_Msk = 0xc000
	// Position of DECPROT8 field.
	ETZPC_ETZPC_DECPROT5_DECPROT8_Pos = 0x10
	// Bit mask of DECPROT8 field.
	ETZPC_ETZPC_DECPROT5_DECPROT8_Msk = 0x30000
	// Position of DECPROT9 field.
	ETZPC_ETZPC_DECPROT5_DECPROT9_Pos = 0x12
	// Bit mask of DECPROT9 field.
	ETZPC_ETZPC_DECPROT5_DECPROT9_Msk = 0xc0000
	// Position of DECPROT10 field.
	ETZPC_ETZPC_DECPROT5_DECPROT10_Pos = 0x14
	// Bit mask of DECPROT10 field.
	ETZPC_ETZPC_DECPROT5_DECPROT10_Msk = 0x300000
	// Position of DECPROT11 field.
	ETZPC_ETZPC_DECPROT5_DECPROT11_Pos = 0x16
	// Bit mask of DECPROT11 field.
	ETZPC_ETZPC_DECPROT5_DECPROT11_Msk = 0xc00000
	// Position of DECPROT12 field.
	ETZPC_ETZPC_DECPROT5_DECPROT12_Pos = 0x18
	// Bit mask of DECPROT12 field.
	ETZPC_ETZPC_DECPROT5_DECPROT12_Msk = 0x3000000
	// Position of DECPROT13 field.
	ETZPC_ETZPC_DECPROT5_DECPROT13_Pos = 0x1a
	// Bit mask of DECPROT13 field.
	ETZPC_ETZPC_DECPROT5_DECPROT13_Msk = 0xc000000
	// Position of DECPROT14 field.
	ETZPC_ETZPC_DECPROT5_DECPROT14_Pos = 0x1c
	// Bit mask of DECPROT14 field.
	ETZPC_ETZPC_DECPROT5_DECPROT14_Msk = 0x30000000
	// Position of DECPROT15 field.
	ETZPC_ETZPC_DECPROT5_DECPROT15_Pos = 0x1e
	// Bit mask of DECPROT15 field.
	ETZPC_ETZPC_DECPROT5_DECPROT15_Msk = 0xc0000000

	// ETZPC_DECPROT_LOCK0: ETZPC decprot lock 0 register
	// Position of LOCK0 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK0_Pos = 0x0
	// Bit mask of LOCK0 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK0_Msk = 0x1
	// Bit LOCK0.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK0 = 0x1
	// Position of LOCK1 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK1_Pos = 0x1
	// Bit mask of LOCK1 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK1_Msk = 0x2
	// Bit LOCK1.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK1 = 0x2
	// Position of LOCK2 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK2_Pos = 0x2
	// Bit mask of LOCK2 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK2_Msk = 0x4
	// Bit LOCK2.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK2 = 0x4
	// Position of LOCK3 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK3_Pos = 0x3
	// Bit mask of LOCK3 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK3_Msk = 0x8
	// Bit LOCK3.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK3 = 0x8
	// Position of LOCK4 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK4_Pos = 0x4
	// Bit mask of LOCK4 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK4_Msk = 0x10
	// Bit LOCK4.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK4 = 0x10
	// Position of LOCK5 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK5_Pos = 0x5
	// Bit mask of LOCK5 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK5_Msk = 0x20
	// Bit LOCK5.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK5 = 0x20
	// Position of LOCK6 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK6_Pos = 0x6
	// Bit mask of LOCK6 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK6_Msk = 0x40
	// Bit LOCK6.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK6 = 0x40
	// Position of LOCK7 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK7_Pos = 0x7
	// Bit mask of LOCK7 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK7_Msk = 0x80
	// Bit LOCK7.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK7 = 0x80
	// Position of LOCK8 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK8_Pos = 0x8
	// Bit mask of LOCK8 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK8_Msk = 0x100
	// Bit LOCK8.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK8 = 0x100
	// Position of LOCK9 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK9_Pos = 0x9
	// Bit mask of LOCK9 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK9_Msk = 0x200
	// Bit LOCK9.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK9 = 0x200
	// Position of LOCK10 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK10_Pos = 0xa
	// Bit mask of LOCK10 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK10_Msk = 0x400
	// Bit LOCK10.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK10 = 0x400
	// Position of LOCK11 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK11_Pos = 0xb
	// Bit mask of LOCK11 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK11_Msk = 0x800
	// Bit LOCK11.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK11 = 0x800
	// Position of LOCK12 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK12_Pos = 0xc
	// Bit mask of LOCK12 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK12_Msk = 0x1000
	// Bit LOCK12.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK12 = 0x1000
	// Position of LOCK13 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK13_Pos = 0xd
	// Bit mask of LOCK13 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK13_Msk = 0x2000
	// Bit LOCK13.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK13 = 0x2000
	// Position of LOCK14 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK14_Pos = 0xe
	// Bit mask of LOCK14 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK14_Msk = 0x4000
	// Bit LOCK14.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK14 = 0x4000
	// Position of LOCK15 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK15_Pos = 0xf
	// Bit mask of LOCK15 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK15_Msk = 0x8000
	// Bit LOCK15.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK15 = 0x8000
	// Position of LOCK16 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK16_Pos = 0x10
	// Bit mask of LOCK16 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK16_Msk = 0x10000
	// Bit LOCK16.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK16 = 0x10000
	// Position of LOCK17 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK17_Pos = 0x11
	// Bit mask of LOCK17 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK17_Msk = 0x20000
	// Bit LOCK17.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK17 = 0x20000
	// Position of LOCK18 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK18_Pos = 0x12
	// Bit mask of LOCK18 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK18_Msk = 0x40000
	// Bit LOCK18.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK18 = 0x40000
	// Position of LOCK19 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK19_Pos = 0x13
	// Bit mask of LOCK19 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK19_Msk = 0x80000
	// Bit LOCK19.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK19 = 0x80000
	// Position of LOCK20 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK20_Pos = 0x14
	// Bit mask of LOCK20 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK20_Msk = 0x100000
	// Bit LOCK20.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK20 = 0x100000
	// Position of LOCK21 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK21_Pos = 0x15
	// Bit mask of LOCK21 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK21_Msk = 0x200000
	// Bit LOCK21.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK21 = 0x200000
	// Position of LOCK22 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK22_Pos = 0x16
	// Bit mask of LOCK22 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK22_Msk = 0x400000
	// Bit LOCK22.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK22 = 0x400000
	// Position of LOCK23 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK23_Pos = 0x17
	// Bit mask of LOCK23 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK23_Msk = 0x800000
	// Bit LOCK23.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK23 = 0x800000
	// Position of LOCK24 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK24_Pos = 0x18
	// Bit mask of LOCK24 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK24_Msk = 0x1000000
	// Bit LOCK24.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK24 = 0x1000000
	// Position of LOCK25 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK25_Pos = 0x19
	// Bit mask of LOCK25 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK25_Msk = 0x2000000
	// Bit LOCK25.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK25 = 0x2000000
	// Position of LOCK26 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK26_Pos = 0x1a
	// Bit mask of LOCK26 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK26_Msk = 0x4000000
	// Bit LOCK26.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK26 = 0x4000000
	// Position of LOCK27 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK27_Pos = 0x1b
	// Bit mask of LOCK27 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK27_Msk = 0x8000000
	// Bit LOCK27.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK27 = 0x8000000
	// Position of LOCK28 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK28_Pos = 0x1c
	// Bit mask of LOCK28 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK28_Msk = 0x10000000
	// Bit LOCK28.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK28 = 0x10000000
	// Position of LOCK29 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK29_Pos = 0x1d
	// Bit mask of LOCK29 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK29_Msk = 0x20000000
	// Bit LOCK29.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK29 = 0x20000000
	// Position of LOCK30 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK30_Pos = 0x1e
	// Bit mask of LOCK30 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK30_Msk = 0x40000000
	// Bit LOCK30.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK30 = 0x40000000
	// Position of LOCK31 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK31_Pos = 0x1f
	// Bit mask of LOCK31 field.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK31_Msk = 0x80000000
	// Bit LOCK31.
	ETZPC_ETZPC_DECPROT_LOCK0_LOCK31 = 0x80000000

	// ETZPC_DECPROT_LOCK1: ETZPC decprot lock 1 register
	// Position of LOCK0 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK0_Pos = 0x0
	// Bit mask of LOCK0 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK0_Msk = 0x1
	// Bit LOCK0.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK0 = 0x1
	// Position of LOCK1 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK1_Pos = 0x1
	// Bit mask of LOCK1 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK1_Msk = 0x2
	// Bit LOCK1.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK1 = 0x2
	// Position of LOCK2 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK2_Pos = 0x2
	// Bit mask of LOCK2 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK2_Msk = 0x4
	// Bit LOCK2.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK2 = 0x4
	// Position of LOCK3 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK3_Pos = 0x3
	// Bit mask of LOCK3 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK3_Msk = 0x8
	// Bit LOCK3.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK3 = 0x8
	// Position of LOCK4 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK4_Pos = 0x4
	// Bit mask of LOCK4 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK4_Msk = 0x10
	// Bit LOCK4.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK4 = 0x10
	// Position of LOCK5 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK5_Pos = 0x5
	// Bit mask of LOCK5 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK5_Msk = 0x20
	// Bit LOCK5.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK5 = 0x20
	// Position of LOCK6 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK6_Pos = 0x6
	// Bit mask of LOCK6 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK6_Msk = 0x40
	// Bit LOCK6.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK6 = 0x40
	// Position of LOCK7 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK7_Pos = 0x7
	// Bit mask of LOCK7 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK7_Msk = 0x80
	// Bit LOCK7.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK7 = 0x80
	// Position of LOCK8 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK8_Pos = 0x8
	// Bit mask of LOCK8 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK8_Msk = 0x100
	// Bit LOCK8.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK8 = 0x100
	// Position of LOCK9 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK9_Pos = 0x9
	// Bit mask of LOCK9 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK9_Msk = 0x200
	// Bit LOCK9.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK9 = 0x200
	// Position of LOCK10 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK10_Pos = 0xa
	// Bit mask of LOCK10 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK10_Msk = 0x400
	// Bit LOCK10.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK10 = 0x400
	// Position of LOCK11 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK11_Pos = 0xb
	// Bit mask of LOCK11 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK11_Msk = 0x800
	// Bit LOCK11.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK11 = 0x800
	// Position of LOCK12 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK12_Pos = 0xc
	// Bit mask of LOCK12 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK12_Msk = 0x1000
	// Bit LOCK12.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK12 = 0x1000
	// Position of LOCK13 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK13_Pos = 0xd
	// Bit mask of LOCK13 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK13_Msk = 0x2000
	// Bit LOCK13.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK13 = 0x2000
	// Position of LOCK14 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK14_Pos = 0xe
	// Bit mask of LOCK14 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK14_Msk = 0x4000
	// Bit LOCK14.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK14 = 0x4000
	// Position of LOCK15 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK15_Pos = 0xf
	// Bit mask of LOCK15 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK15_Msk = 0x8000
	// Bit LOCK15.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK15 = 0x8000
	// Position of LOCK16 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK16_Pos = 0x10
	// Bit mask of LOCK16 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK16_Msk = 0x10000
	// Bit LOCK16.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK16 = 0x10000
	// Position of LOCK17 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK17_Pos = 0x11
	// Bit mask of LOCK17 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK17_Msk = 0x20000
	// Bit LOCK17.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK17 = 0x20000
	// Position of LOCK18 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK18_Pos = 0x12
	// Bit mask of LOCK18 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK18_Msk = 0x40000
	// Bit LOCK18.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK18 = 0x40000
	// Position of LOCK19 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK19_Pos = 0x13
	// Bit mask of LOCK19 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK19_Msk = 0x80000
	// Bit LOCK19.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK19 = 0x80000
	// Position of LOCK20 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK20_Pos = 0x14
	// Bit mask of LOCK20 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK20_Msk = 0x100000
	// Bit LOCK20.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK20 = 0x100000
	// Position of LOCK21 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK21_Pos = 0x15
	// Bit mask of LOCK21 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK21_Msk = 0x200000
	// Bit LOCK21.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK21 = 0x200000
	// Position of LOCK22 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK22_Pos = 0x16
	// Bit mask of LOCK22 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK22_Msk = 0x400000
	// Bit LOCK22.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK22 = 0x400000
	// Position of LOCK23 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK23_Pos = 0x17
	// Bit mask of LOCK23 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK23_Msk = 0x800000
	// Bit LOCK23.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK23 = 0x800000
	// Position of LOCK24 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK24_Pos = 0x18
	// Bit mask of LOCK24 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK24_Msk = 0x1000000
	// Bit LOCK24.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK24 = 0x1000000
	// Position of LOCK25 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK25_Pos = 0x19
	// Bit mask of LOCK25 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK25_Msk = 0x2000000
	// Bit LOCK25.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK25 = 0x2000000
	// Position of LOCK26 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK26_Pos = 0x1a
	// Bit mask of LOCK26 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK26_Msk = 0x4000000
	// Bit LOCK26.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK26 = 0x4000000
	// Position of LOCK27 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK27_Pos = 0x1b
	// Bit mask of LOCK27 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK27_Msk = 0x8000000
	// Bit LOCK27.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK27 = 0x8000000
	// Position of LOCK28 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK28_Pos = 0x1c
	// Bit mask of LOCK28 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK28_Msk = 0x10000000
	// Bit LOCK28.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK28 = 0x10000000
	// Position of LOCK29 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK29_Pos = 0x1d
	// Bit mask of LOCK29 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK29_Msk = 0x20000000
	// Bit LOCK29.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK29 = 0x20000000
	// Position of LOCK30 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK30_Pos = 0x1e
	// Bit mask of LOCK30 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK30_Msk = 0x40000000
	// Bit LOCK30.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK30 = 0x40000000
	// Position of LOCK31 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK31_Pos = 0x1f
	// Bit mask of LOCK31 field.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK31_Msk = 0x80000000
	// Bit LOCK31.
	ETZPC_ETZPC_DECPROT_LOCK1_LOCK31 = 0x80000000

	// ETZPC_DECPROT_LOCK2: ETZPC decprot lock 2 register
	// Position of LOCK0 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK0_Pos = 0x0
	// Bit mask of LOCK0 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK0_Msk = 0x1
	// Bit LOCK0.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK0 = 0x1
	// Position of LOCK1 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK1_Pos = 0x1
	// Bit mask of LOCK1 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK1_Msk = 0x2
	// Bit LOCK1.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK1 = 0x2
	// Position of LOCK2 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK2_Pos = 0x2
	// Bit mask of LOCK2 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK2_Msk = 0x4
	// Bit LOCK2.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK2 = 0x4
	// Position of LOCK3 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK3_Pos = 0x3
	// Bit mask of LOCK3 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK3_Msk = 0x8
	// Bit LOCK3.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK3 = 0x8
	// Position of LOCK4 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK4_Pos = 0x4
	// Bit mask of LOCK4 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK4_Msk = 0x10
	// Bit LOCK4.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK4 = 0x10
	// Position of LOCK5 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK5_Pos = 0x5
	// Bit mask of LOCK5 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK5_Msk = 0x20
	// Bit LOCK5.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK5 = 0x20
	// Position of LOCK6 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK6_Pos = 0x6
	// Bit mask of LOCK6 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK6_Msk = 0x40
	// Bit LOCK6.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK6 = 0x40
	// Position of LOCK7 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK7_Pos = 0x7
	// Bit mask of LOCK7 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK7_Msk = 0x80
	// Bit LOCK7.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK7 = 0x80
	// Position of LOCK8 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK8_Pos = 0x8
	// Bit mask of LOCK8 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK8_Msk = 0x100
	// Bit LOCK8.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK8 = 0x100
	// Position of LOCK9 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK9_Pos = 0x9
	// Bit mask of LOCK9 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK9_Msk = 0x200
	// Bit LOCK9.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK9 = 0x200
	// Position of LOCK10 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK10_Pos = 0xa
	// Bit mask of LOCK10 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK10_Msk = 0x400
	// Bit LOCK10.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK10 = 0x400
	// Position of LOCK11 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK11_Pos = 0xb
	// Bit mask of LOCK11 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK11_Msk = 0x800
	// Bit LOCK11.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK11 = 0x800
	// Position of LOCK12 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK12_Pos = 0xc
	// Bit mask of LOCK12 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK12_Msk = 0x1000
	// Bit LOCK12.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK12 = 0x1000
	// Position of LOCK13 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK13_Pos = 0xd
	// Bit mask of LOCK13 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK13_Msk = 0x2000
	// Bit LOCK13.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK13 = 0x2000
	// Position of LOCK14 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK14_Pos = 0xe
	// Bit mask of LOCK14 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK14_Msk = 0x4000
	// Bit LOCK14.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK14 = 0x4000
	// Position of LOCK15 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK15_Pos = 0xf
	// Bit mask of LOCK15 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK15_Msk = 0x8000
	// Bit LOCK15.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK15 = 0x8000
	// Position of LOCK16 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK16_Pos = 0x10
	// Bit mask of LOCK16 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK16_Msk = 0x10000
	// Bit LOCK16.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK16 = 0x10000
	// Position of LOCK17 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK17_Pos = 0x11
	// Bit mask of LOCK17 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK17_Msk = 0x20000
	// Bit LOCK17.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK17 = 0x20000
	// Position of LOCK18 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK18_Pos = 0x12
	// Bit mask of LOCK18 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK18_Msk = 0x40000
	// Bit LOCK18.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK18 = 0x40000
	// Position of LOCK19 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK19_Pos = 0x13
	// Bit mask of LOCK19 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK19_Msk = 0x80000
	// Bit LOCK19.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK19 = 0x80000
	// Position of LOCK20 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK20_Pos = 0x14
	// Bit mask of LOCK20 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK20_Msk = 0x100000
	// Bit LOCK20.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK20 = 0x100000
	// Position of LOCK21 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK21_Pos = 0x15
	// Bit mask of LOCK21 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK21_Msk = 0x200000
	// Bit LOCK21.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK21 = 0x200000
	// Position of LOCK22 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK22_Pos = 0x16
	// Bit mask of LOCK22 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK22_Msk = 0x400000
	// Bit LOCK22.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK22 = 0x400000
	// Position of LOCK23 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK23_Pos = 0x17
	// Bit mask of LOCK23 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK23_Msk = 0x800000
	// Bit LOCK23.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK23 = 0x800000
	// Position of LOCK24 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK24_Pos = 0x18
	// Bit mask of LOCK24 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK24_Msk = 0x1000000
	// Bit LOCK24.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK24 = 0x1000000
	// Position of LOCK25 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK25_Pos = 0x19
	// Bit mask of LOCK25 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK25_Msk = 0x2000000
	// Bit LOCK25.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK25 = 0x2000000
	// Position of LOCK26 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK26_Pos = 0x1a
	// Bit mask of LOCK26 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK26_Msk = 0x4000000
	// Bit LOCK26.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK26 = 0x4000000
	// Position of LOCK27 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK27_Pos = 0x1b
	// Bit mask of LOCK27 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK27_Msk = 0x8000000
	// Bit LOCK27.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK27 = 0x8000000
	// Position of LOCK28 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK28_Pos = 0x1c
	// Bit mask of LOCK28 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK28_Msk = 0x10000000
	// Bit LOCK28.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK28 = 0x10000000
	// Position of LOCK29 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK29_Pos = 0x1d
	// Bit mask of LOCK29 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK29_Msk = 0x20000000
	// Bit LOCK29.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK29 = 0x20000000
	// Position of LOCK30 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK30_Pos = 0x1e
	// Bit mask of LOCK30 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK30_Msk = 0x40000000
	// Bit LOCK30.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK30 = 0x40000000
	// Position of LOCK31 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK31_Pos = 0x1f
	// Bit mask of LOCK31 field.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK31_Msk = 0x80000000
	// Bit LOCK31.
	ETZPC_ETZPC_DECPROT_LOCK2_LOCK31 = 0x80000000

	// ETZPC_HWCFGR: ETZPC IP HW configuration register
	// Position of NUM_TZMA field.
	ETZPC_ETZPC_HWCFGR_NUM_TZMA_Pos = 0x0
	// Bit mask of NUM_TZMA field.
	ETZPC_ETZPC_HWCFGR_NUM_TZMA_Msk = 0xff
	// Position of NUM_PER_SEC field.
	ETZPC_ETZPC_HWCFGR_NUM_PER_SEC_Pos = 0x8
	// Bit mask of NUM_PER_SEC field.
	ETZPC_ETZPC_HWCFGR_NUM_PER_SEC_Msk = 0xff00
	// Position of NUM_AHB_SEC field.
	ETZPC_ETZPC_HWCFGR_NUM_AHB_SEC_Pos = 0x10
	// Bit mask of NUM_AHB_SEC field.
	ETZPC_ETZPC_HWCFGR_NUM_AHB_SEC_Msk = 0xff0000
	// Position of CHUNKS1N4 field.
	ETZPC_ETZPC_HWCFGR_CHUNKS1N4_Pos = 0x18
	// Bit mask of CHUNKS1N4 field.
	ETZPC_ETZPC_HWCFGR_CHUNKS1N4_Msk = 0xff000000

	// ETZPC_VERR: ETZPC IP version register
	// Position of MINREV field.
	ETZPC_ETZPC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	ETZPC_ETZPC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	ETZPC_ETZPC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	ETZPC_ETZPC_VERR_MAJREV_Msk = 0xf0

	// ETZPC_IDR: ETZPC IP version register
	// Position of ID field.
	ETZPC_ETZPC_IDR_ID_Pos = 0x0
	// Bit mask of ID field.
	ETZPC_ETZPC_IDR_ID_Msk = 0xffffffff

	// ETZPC_SIDR: ETZPC IP version register
	// Position of SID field.
	ETZPC_ETZPC_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	ETZPC_ETZPC_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for EXTI: EXTI
const (
	// EXTI_RTSR1: Contains only register bits for configurable events.
	// Position of RT0 field.
	EXTI_EXTI_RTSR1_RT0_Pos = 0x0
	// Bit mask of RT0 field.
	EXTI_EXTI_RTSR1_RT0_Msk = 0x1
	// Bit RT0.
	EXTI_EXTI_RTSR1_RT0 = 0x1
	// Position of RT1 field.
	EXTI_EXTI_RTSR1_RT1_Pos = 0x1
	// Bit mask of RT1 field.
	EXTI_EXTI_RTSR1_RT1_Msk = 0x2
	// Bit RT1.
	EXTI_EXTI_RTSR1_RT1 = 0x2
	// Position of RT2 field.
	EXTI_EXTI_RTSR1_RT2_Pos = 0x2
	// Bit mask of RT2 field.
	EXTI_EXTI_RTSR1_RT2_Msk = 0x4
	// Bit RT2.
	EXTI_EXTI_RTSR1_RT2 = 0x4
	// Position of RT3 field.
	EXTI_EXTI_RTSR1_RT3_Pos = 0x3
	// Bit mask of RT3 field.
	EXTI_EXTI_RTSR1_RT3_Msk = 0x8
	// Bit RT3.
	EXTI_EXTI_RTSR1_RT3 = 0x8
	// Position of RT4 field.
	EXTI_EXTI_RTSR1_RT4_Pos = 0x4
	// Bit mask of RT4 field.
	EXTI_EXTI_RTSR1_RT4_Msk = 0x10
	// Bit RT4.
	EXTI_EXTI_RTSR1_RT4 = 0x10
	// Position of RT5 field.
	EXTI_EXTI_RTSR1_RT5_Pos = 0x5
	// Bit mask of RT5 field.
	EXTI_EXTI_RTSR1_RT5_Msk = 0x20
	// Bit RT5.
	EXTI_EXTI_RTSR1_RT5 = 0x20
	// Position of RT6 field.
	EXTI_EXTI_RTSR1_RT6_Pos = 0x6
	// Bit mask of RT6 field.
	EXTI_EXTI_RTSR1_RT6_Msk = 0x40
	// Bit RT6.
	EXTI_EXTI_RTSR1_RT6 = 0x40
	// Position of RT7 field.
	EXTI_EXTI_RTSR1_RT7_Pos = 0x7
	// Bit mask of RT7 field.
	EXTI_EXTI_RTSR1_RT7_Msk = 0x80
	// Bit RT7.
	EXTI_EXTI_RTSR1_RT7 = 0x80
	// Position of RT8 field.
	EXTI_EXTI_RTSR1_RT8_Pos = 0x8
	// Bit mask of RT8 field.
	EXTI_EXTI_RTSR1_RT8_Msk = 0x100
	// Bit RT8.
	EXTI_EXTI_RTSR1_RT8 = 0x100
	// Position of RT9 field.
	EXTI_EXTI_RTSR1_RT9_Pos = 0x9
	// Bit mask of RT9 field.
	EXTI_EXTI_RTSR1_RT9_Msk = 0x200
	// Bit RT9.
	EXTI_EXTI_RTSR1_RT9 = 0x200
	// Position of RT10 field.
	EXTI_EXTI_RTSR1_RT10_Pos = 0xa
	// Bit mask of RT10 field.
	EXTI_EXTI_RTSR1_RT10_Msk = 0x400
	// Bit RT10.
	EXTI_EXTI_RTSR1_RT10 = 0x400
	// Position of RT11 field.
	EXTI_EXTI_RTSR1_RT11_Pos = 0xb
	// Bit mask of RT11 field.
	EXTI_EXTI_RTSR1_RT11_Msk = 0x800
	// Bit RT11.
	EXTI_EXTI_RTSR1_RT11 = 0x800
	// Position of RT12 field.
	EXTI_EXTI_RTSR1_RT12_Pos = 0xc
	// Bit mask of RT12 field.
	EXTI_EXTI_RTSR1_RT12_Msk = 0x1000
	// Bit RT12.
	EXTI_EXTI_RTSR1_RT12 = 0x1000
	// Position of RT13 field.
	EXTI_EXTI_RTSR1_RT13_Pos = 0xd
	// Bit mask of RT13 field.
	EXTI_EXTI_RTSR1_RT13_Msk = 0x2000
	// Bit RT13.
	EXTI_EXTI_RTSR1_RT13 = 0x2000
	// Position of RT14 field.
	EXTI_EXTI_RTSR1_RT14_Pos = 0xe
	// Bit mask of RT14 field.
	EXTI_EXTI_RTSR1_RT14_Msk = 0x4000
	// Bit RT14.
	EXTI_EXTI_RTSR1_RT14 = 0x4000
	// Position of RT15 field.
	EXTI_EXTI_RTSR1_RT15_Pos = 0xf
	// Bit mask of RT15 field.
	EXTI_EXTI_RTSR1_RT15_Msk = 0x8000
	// Bit RT15.
	EXTI_EXTI_RTSR1_RT15 = 0x8000
	// Position of RT16 field.
	EXTI_EXTI_RTSR1_RT16_Pos = 0x10
	// Bit mask of RT16 field.
	EXTI_EXTI_RTSR1_RT16_Msk = 0x10000
	// Bit RT16.
	EXTI_EXTI_RTSR1_RT16 = 0x10000

	// EXTI_FTSR1: Contains only register bits for configurable events.
	// Position of FT0 field.
	EXTI_EXTI_FTSR1_FT0_Pos = 0x0
	// Bit mask of FT0 field.
	EXTI_EXTI_FTSR1_FT0_Msk = 0x1
	// Bit FT0.
	EXTI_EXTI_FTSR1_FT0 = 0x1
	// Position of FT1 field.
	EXTI_EXTI_FTSR1_FT1_Pos = 0x1
	// Bit mask of FT1 field.
	EXTI_EXTI_FTSR1_FT1_Msk = 0x2
	// Bit FT1.
	EXTI_EXTI_FTSR1_FT1 = 0x2
	// Position of FT2 field.
	EXTI_EXTI_FTSR1_FT2_Pos = 0x2
	// Bit mask of FT2 field.
	EXTI_EXTI_FTSR1_FT2_Msk = 0x4
	// Bit FT2.
	EXTI_EXTI_FTSR1_FT2 = 0x4
	// Position of FT3 field.
	EXTI_EXTI_FTSR1_FT3_Pos = 0x3
	// Bit mask of FT3 field.
	EXTI_EXTI_FTSR1_FT3_Msk = 0x8
	// Bit FT3.
	EXTI_EXTI_FTSR1_FT3 = 0x8
	// Position of FT4 field.
	EXTI_EXTI_FTSR1_FT4_Pos = 0x4
	// Bit mask of FT4 field.
	EXTI_EXTI_FTSR1_FT4_Msk = 0x10
	// Bit FT4.
	EXTI_EXTI_FTSR1_FT4 = 0x10
	// Position of FT5 field.
	EXTI_EXTI_FTSR1_FT5_Pos = 0x5
	// Bit mask of FT5 field.
	EXTI_EXTI_FTSR1_FT5_Msk = 0x20
	// Bit FT5.
	EXTI_EXTI_FTSR1_FT5 = 0x20
	// Position of FT6 field.
	EXTI_EXTI_FTSR1_FT6_Pos = 0x6
	// Bit mask of FT6 field.
	EXTI_EXTI_FTSR1_FT6_Msk = 0x40
	// Bit FT6.
	EXTI_EXTI_FTSR1_FT6 = 0x40
	// Position of FT7 field.
	EXTI_EXTI_FTSR1_FT7_Pos = 0x7
	// Bit mask of FT7 field.
	EXTI_EXTI_FTSR1_FT7_Msk = 0x80
	// Bit FT7.
	EXTI_EXTI_FTSR1_FT7 = 0x80
	// Position of FT8 field.
	EXTI_EXTI_FTSR1_FT8_Pos = 0x8
	// Bit mask of FT8 field.
	EXTI_EXTI_FTSR1_FT8_Msk = 0x100
	// Bit FT8.
	EXTI_EXTI_FTSR1_FT8 = 0x100
	// Position of FT9 field.
	EXTI_EXTI_FTSR1_FT9_Pos = 0x9
	// Bit mask of FT9 field.
	EXTI_EXTI_FTSR1_FT9_Msk = 0x200
	// Bit FT9.
	EXTI_EXTI_FTSR1_FT9 = 0x200
	// Position of FT10 field.
	EXTI_EXTI_FTSR1_FT10_Pos = 0xa
	// Bit mask of FT10 field.
	EXTI_EXTI_FTSR1_FT10_Msk = 0x400
	// Bit FT10.
	EXTI_EXTI_FTSR1_FT10 = 0x400
	// Position of FT11 field.
	EXTI_EXTI_FTSR1_FT11_Pos = 0xb
	// Bit mask of FT11 field.
	EXTI_EXTI_FTSR1_FT11_Msk = 0x800
	// Bit FT11.
	EXTI_EXTI_FTSR1_FT11 = 0x800
	// Position of FT12 field.
	EXTI_EXTI_FTSR1_FT12_Pos = 0xc
	// Bit mask of FT12 field.
	EXTI_EXTI_FTSR1_FT12_Msk = 0x1000
	// Bit FT12.
	EXTI_EXTI_FTSR1_FT12 = 0x1000
	// Position of FT13 field.
	EXTI_EXTI_FTSR1_FT13_Pos = 0xd
	// Bit mask of FT13 field.
	EXTI_EXTI_FTSR1_FT13_Msk = 0x2000
	// Bit FT13.
	EXTI_EXTI_FTSR1_FT13 = 0x2000
	// Position of FT14 field.
	EXTI_EXTI_FTSR1_FT14_Pos = 0xe
	// Bit mask of FT14 field.
	EXTI_EXTI_FTSR1_FT14_Msk = 0x4000
	// Bit FT14.
	EXTI_EXTI_FTSR1_FT14 = 0x4000
	// Position of FT15 field.
	EXTI_EXTI_FTSR1_FT15_Pos = 0xf
	// Bit mask of FT15 field.
	EXTI_EXTI_FTSR1_FT15_Msk = 0x8000
	// Bit FT15.
	EXTI_EXTI_FTSR1_FT15 = 0x8000
	// Position of FT16 field.
	EXTI_EXTI_FTSR1_FT16_Pos = 0x10
	// Bit mask of FT16 field.
	EXTI_EXTI_FTSR1_FT16_Msk = 0x10000
	// Bit FT16.
	EXTI_EXTI_FTSR1_FT16 = 0x10000

	// EXTI_SWIER1: Contains only register bits for configurable events.
	// Position of SWI0 field.
	EXTI_EXTI_SWIER1_SWI0_Pos = 0x0
	// Bit mask of SWI0 field.
	EXTI_EXTI_SWIER1_SWI0_Msk = 0x1
	// Bit SWI0.
	EXTI_EXTI_SWIER1_SWI0 = 0x1
	// Position of SWI1 field.
	EXTI_EXTI_SWIER1_SWI1_Pos = 0x1
	// Bit mask of SWI1 field.
	EXTI_EXTI_SWIER1_SWI1_Msk = 0x2
	// Bit SWI1.
	EXTI_EXTI_SWIER1_SWI1 = 0x2
	// Position of SWI2 field.
	EXTI_EXTI_SWIER1_SWI2_Pos = 0x2
	// Bit mask of SWI2 field.
	EXTI_EXTI_SWIER1_SWI2_Msk = 0x4
	// Bit SWI2.
	EXTI_EXTI_SWIER1_SWI2 = 0x4
	// Position of SWI3 field.
	EXTI_EXTI_SWIER1_SWI3_Pos = 0x3
	// Bit mask of SWI3 field.
	EXTI_EXTI_SWIER1_SWI3_Msk = 0x8
	// Bit SWI3.
	EXTI_EXTI_SWIER1_SWI3 = 0x8
	// Position of SWI4 field.
	EXTI_EXTI_SWIER1_SWI4_Pos = 0x4
	// Bit mask of SWI4 field.
	EXTI_EXTI_SWIER1_SWI4_Msk = 0x10
	// Bit SWI4.
	EXTI_EXTI_SWIER1_SWI4 = 0x10
	// Position of SWI5 field.
	EXTI_EXTI_SWIER1_SWI5_Pos = 0x5
	// Bit mask of SWI5 field.
	EXTI_EXTI_SWIER1_SWI5_Msk = 0x20
	// Bit SWI5.
	EXTI_EXTI_SWIER1_SWI5 = 0x20
	// Position of SWI6 field.
	EXTI_EXTI_SWIER1_SWI6_Pos = 0x6
	// Bit mask of SWI6 field.
	EXTI_EXTI_SWIER1_SWI6_Msk = 0x40
	// Bit SWI6.
	EXTI_EXTI_SWIER1_SWI6 = 0x40
	// Position of SWI7 field.
	EXTI_EXTI_SWIER1_SWI7_Pos = 0x7
	// Bit mask of SWI7 field.
	EXTI_EXTI_SWIER1_SWI7_Msk = 0x80
	// Bit SWI7.
	EXTI_EXTI_SWIER1_SWI7 = 0x80
	// Position of SWI8 field.
	EXTI_EXTI_SWIER1_SWI8_Pos = 0x8
	// Bit mask of SWI8 field.
	EXTI_EXTI_SWIER1_SWI8_Msk = 0x100
	// Bit SWI8.
	EXTI_EXTI_SWIER1_SWI8 = 0x100
	// Position of SWI9 field.
	EXTI_EXTI_SWIER1_SWI9_Pos = 0x9
	// Bit mask of SWI9 field.
	EXTI_EXTI_SWIER1_SWI9_Msk = 0x200
	// Bit SWI9.
	EXTI_EXTI_SWIER1_SWI9 = 0x200
	// Position of SWI10 field.
	EXTI_EXTI_SWIER1_SWI10_Pos = 0xa
	// Bit mask of SWI10 field.
	EXTI_EXTI_SWIER1_SWI10_Msk = 0x400
	// Bit SWI10.
	EXTI_EXTI_SWIER1_SWI10 = 0x400
	// Position of SWI11 field.
	EXTI_EXTI_SWIER1_SWI11_Pos = 0xb
	// Bit mask of SWI11 field.
	EXTI_EXTI_SWIER1_SWI11_Msk = 0x800
	// Bit SWI11.
	EXTI_EXTI_SWIER1_SWI11 = 0x800
	// Position of SWI12 field.
	EXTI_EXTI_SWIER1_SWI12_Pos = 0xc
	// Bit mask of SWI12 field.
	EXTI_EXTI_SWIER1_SWI12_Msk = 0x1000
	// Bit SWI12.
	EXTI_EXTI_SWIER1_SWI12 = 0x1000
	// Position of SWI13 field.
	EXTI_EXTI_SWIER1_SWI13_Pos = 0xd
	// Bit mask of SWI13 field.
	EXTI_EXTI_SWIER1_SWI13_Msk = 0x2000
	// Bit SWI13.
	EXTI_EXTI_SWIER1_SWI13 = 0x2000
	// Position of SWI14 field.
	EXTI_EXTI_SWIER1_SWI14_Pos = 0xe
	// Bit mask of SWI14 field.
	EXTI_EXTI_SWIER1_SWI14_Msk = 0x4000
	// Bit SWI14.
	EXTI_EXTI_SWIER1_SWI14 = 0x4000
	// Position of SWI15 field.
	EXTI_EXTI_SWIER1_SWI15_Pos = 0xf
	// Bit mask of SWI15 field.
	EXTI_EXTI_SWIER1_SWI15_Msk = 0x8000
	// Bit SWI15.
	EXTI_EXTI_SWIER1_SWI15 = 0x8000
	// Position of SWI16 field.
	EXTI_EXTI_SWIER1_SWI16_Pos = 0x10
	// Bit mask of SWI16 field.
	EXTI_EXTI_SWIER1_SWI16_Msk = 0x10000
	// Bit SWI16.
	EXTI_EXTI_SWIER1_SWI16 = 0x10000

	// EXTI_RPR1: Contains only register bits for configurable events.
	// Position of RPIF0 field.
	EXTI_EXTI_RPR1_RPIF0_Pos = 0x0
	// Bit mask of RPIF0 field.
	EXTI_EXTI_RPR1_RPIF0_Msk = 0x1
	// Bit RPIF0.
	EXTI_EXTI_RPR1_RPIF0 = 0x1
	// Position of RPIF1 field.
	EXTI_EXTI_RPR1_RPIF1_Pos = 0x1
	// Bit mask of RPIF1 field.
	EXTI_EXTI_RPR1_RPIF1_Msk = 0x2
	// Bit RPIF1.
	EXTI_EXTI_RPR1_RPIF1 = 0x2
	// Position of RPIF2 field.
	EXTI_EXTI_RPR1_RPIF2_Pos = 0x2
	// Bit mask of RPIF2 field.
	EXTI_EXTI_RPR1_RPIF2_Msk = 0x4
	// Bit RPIF2.
	EXTI_EXTI_RPR1_RPIF2 = 0x4
	// Position of RPIF3 field.
	EXTI_EXTI_RPR1_RPIF3_Pos = 0x3
	// Bit mask of RPIF3 field.
	EXTI_EXTI_RPR1_RPIF3_Msk = 0x8
	// Bit RPIF3.
	EXTI_EXTI_RPR1_RPIF3 = 0x8
	// Position of RPIF4 field.
	EXTI_EXTI_RPR1_RPIF4_Pos = 0x4
	// Bit mask of RPIF4 field.
	EXTI_EXTI_RPR1_RPIF4_Msk = 0x10
	// Bit RPIF4.
	EXTI_EXTI_RPR1_RPIF4 = 0x10
	// Position of RPIF5 field.
	EXTI_EXTI_RPR1_RPIF5_Pos = 0x5
	// Bit mask of RPIF5 field.
	EXTI_EXTI_RPR1_RPIF5_Msk = 0x20
	// Bit RPIF5.
	EXTI_EXTI_RPR1_RPIF5 = 0x20
	// Position of RPIF6 field.
	EXTI_EXTI_RPR1_RPIF6_Pos = 0x6
	// Bit mask of RPIF6 field.
	EXTI_EXTI_RPR1_RPIF6_Msk = 0x40
	// Bit RPIF6.
	EXTI_EXTI_RPR1_RPIF6 = 0x40
	// Position of RPIF7 field.
	EXTI_EXTI_RPR1_RPIF7_Pos = 0x7
	// Bit mask of RPIF7 field.
	EXTI_EXTI_RPR1_RPIF7_Msk = 0x80
	// Bit RPIF7.
	EXTI_EXTI_RPR1_RPIF7 = 0x80
	// Position of RPIF8 field.
	EXTI_EXTI_RPR1_RPIF8_Pos = 0x8
	// Bit mask of RPIF8 field.
	EXTI_EXTI_RPR1_RPIF8_Msk = 0x100
	// Bit RPIF8.
	EXTI_EXTI_RPR1_RPIF8 = 0x100
	// Position of RPIF9 field.
	EXTI_EXTI_RPR1_RPIF9_Pos = 0x9
	// Bit mask of RPIF9 field.
	EXTI_EXTI_RPR1_RPIF9_Msk = 0x200
	// Bit RPIF9.
	EXTI_EXTI_RPR1_RPIF9 = 0x200
	// Position of RPIF10 field.
	EXTI_EXTI_RPR1_RPIF10_Pos = 0xa
	// Bit mask of RPIF10 field.
	EXTI_EXTI_RPR1_RPIF10_Msk = 0x400
	// Bit RPIF10.
	EXTI_EXTI_RPR1_RPIF10 = 0x400
	// Position of RPIF11 field.
	EXTI_EXTI_RPR1_RPIF11_Pos = 0xb
	// Bit mask of RPIF11 field.
	EXTI_EXTI_RPR1_RPIF11_Msk = 0x800
	// Bit RPIF11.
	EXTI_EXTI_RPR1_RPIF11 = 0x800
	// Position of RPIF12 field.
	EXTI_EXTI_RPR1_RPIF12_Pos = 0xc
	// Bit mask of RPIF12 field.
	EXTI_EXTI_RPR1_RPIF12_Msk = 0x1000
	// Bit RPIF12.
	EXTI_EXTI_RPR1_RPIF12 = 0x1000
	// Position of RPIF13 field.
	EXTI_EXTI_RPR1_RPIF13_Pos = 0xd
	// Bit mask of RPIF13 field.
	EXTI_EXTI_RPR1_RPIF13_Msk = 0x2000
	// Bit RPIF13.
	EXTI_EXTI_RPR1_RPIF13 = 0x2000
	// Position of RPIF14 field.
	EXTI_EXTI_RPR1_RPIF14_Pos = 0xe
	// Bit mask of RPIF14 field.
	EXTI_EXTI_RPR1_RPIF14_Msk = 0x4000
	// Bit RPIF14.
	EXTI_EXTI_RPR1_RPIF14 = 0x4000
	// Position of RPIF15 field.
	EXTI_EXTI_RPR1_RPIF15_Pos = 0xf
	// Bit mask of RPIF15 field.
	EXTI_EXTI_RPR1_RPIF15_Msk = 0x8000
	// Bit RPIF15.
	EXTI_EXTI_RPR1_RPIF15 = 0x8000
	// Position of RPIF16 field.
	EXTI_EXTI_RPR1_RPIF16_Pos = 0x10
	// Bit mask of RPIF16 field.
	EXTI_EXTI_RPR1_RPIF16_Msk = 0x10000
	// Bit RPIF16.
	EXTI_EXTI_RPR1_RPIF16 = 0x10000

	// EXTI_FPR1: Contains only register bits for configurable events.
	// Position of FPIF0 field.
	EXTI_EXTI_FPR1_FPIF0_Pos = 0x0
	// Bit mask of FPIF0 field.
	EXTI_EXTI_FPR1_FPIF0_Msk = 0x1
	// Bit FPIF0.
	EXTI_EXTI_FPR1_FPIF0 = 0x1
	// Position of FPIF1 field.
	EXTI_EXTI_FPR1_FPIF1_Pos = 0x1
	// Bit mask of FPIF1 field.
	EXTI_EXTI_FPR1_FPIF1_Msk = 0x2
	// Bit FPIF1.
	EXTI_EXTI_FPR1_FPIF1 = 0x2
	// Position of FPIF2 field.
	EXTI_EXTI_FPR1_FPIF2_Pos = 0x2
	// Bit mask of FPIF2 field.
	EXTI_EXTI_FPR1_FPIF2_Msk = 0x4
	// Bit FPIF2.
	EXTI_EXTI_FPR1_FPIF2 = 0x4
	// Position of FPIF3 field.
	EXTI_EXTI_FPR1_FPIF3_Pos = 0x3
	// Bit mask of FPIF3 field.
	EXTI_EXTI_FPR1_FPIF3_Msk = 0x8
	// Bit FPIF3.
	EXTI_EXTI_FPR1_FPIF3 = 0x8
	// Position of FPIF4 field.
	EXTI_EXTI_FPR1_FPIF4_Pos = 0x4
	// Bit mask of FPIF4 field.
	EXTI_EXTI_FPR1_FPIF4_Msk = 0x10
	// Bit FPIF4.
	EXTI_EXTI_FPR1_FPIF4 = 0x10
	// Position of FPIF5 field.
	EXTI_EXTI_FPR1_FPIF5_Pos = 0x5
	// Bit mask of FPIF5 field.
	EXTI_EXTI_FPR1_FPIF5_Msk = 0x20
	// Bit FPIF5.
	EXTI_EXTI_FPR1_FPIF5 = 0x20
	// Position of FPIF6 field.
	EXTI_EXTI_FPR1_FPIF6_Pos = 0x6
	// Bit mask of FPIF6 field.
	EXTI_EXTI_FPR1_FPIF6_Msk = 0x40
	// Bit FPIF6.
	EXTI_EXTI_FPR1_FPIF6 = 0x40
	// Position of FPIF7 field.
	EXTI_EXTI_FPR1_FPIF7_Pos = 0x7
	// Bit mask of FPIF7 field.
	EXTI_EXTI_FPR1_FPIF7_Msk = 0x80
	// Bit FPIF7.
	EXTI_EXTI_FPR1_FPIF7 = 0x80
	// Position of FPIF8 field.
	EXTI_EXTI_FPR1_FPIF8_Pos = 0x8
	// Bit mask of FPIF8 field.
	EXTI_EXTI_FPR1_FPIF8_Msk = 0x100
	// Bit FPIF8.
	EXTI_EXTI_FPR1_FPIF8 = 0x100
	// Position of FPIF9 field.
	EXTI_EXTI_FPR1_FPIF9_Pos = 0x9
	// Bit mask of FPIF9 field.
	EXTI_EXTI_FPR1_FPIF9_Msk = 0x200
	// Bit FPIF9.
	EXTI_EXTI_FPR1_FPIF9 = 0x200
	// Position of FPIF10 field.
	EXTI_EXTI_FPR1_FPIF10_Pos = 0xa
	// Bit mask of FPIF10 field.
	EXTI_EXTI_FPR1_FPIF10_Msk = 0x400
	// Bit FPIF10.
	EXTI_EXTI_FPR1_FPIF10 = 0x400
	// Position of FPIF11 field.
	EXTI_EXTI_FPR1_FPIF11_Pos = 0xb
	// Bit mask of FPIF11 field.
	EXTI_EXTI_FPR1_FPIF11_Msk = 0x800
	// Bit FPIF11.
	EXTI_EXTI_FPR1_FPIF11 = 0x800
	// Position of FPIF12 field.
	EXTI_EXTI_FPR1_FPIF12_Pos = 0xc
	// Bit mask of FPIF12 field.
	EXTI_EXTI_FPR1_FPIF12_Msk = 0x1000
	// Bit FPIF12.
	EXTI_EXTI_FPR1_FPIF12 = 0x1000
	// Position of FPIF13 field.
	EXTI_EXTI_FPR1_FPIF13_Pos = 0xd
	// Bit mask of FPIF13 field.
	EXTI_EXTI_FPR1_FPIF13_Msk = 0x2000
	// Bit FPIF13.
	EXTI_EXTI_FPR1_FPIF13 = 0x2000
	// Position of FPIF14 field.
	EXTI_EXTI_FPR1_FPIF14_Pos = 0xe
	// Bit mask of FPIF14 field.
	EXTI_EXTI_FPR1_FPIF14_Msk = 0x4000
	// Bit FPIF14.
	EXTI_EXTI_FPR1_FPIF14 = 0x4000
	// Position of FPIF15 field.
	EXTI_EXTI_FPR1_FPIF15_Pos = 0xf
	// Bit mask of FPIF15 field.
	EXTI_EXTI_FPR1_FPIF15_Msk = 0x8000
	// Bit FPIF15.
	EXTI_EXTI_FPR1_FPIF15 = 0x8000
	// Position of FPIF16 field.
	EXTI_EXTI_FPR1_FPIF16_Pos = 0x10
	// Bit mask of FPIF16 field.
	EXTI_EXTI_FPR1_FPIF16_Msk = 0x10000
	// Bit FPIF16.
	EXTI_EXTI_FPR1_FPIF16 = 0x10000

	// EXTI_TZENR1: This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.
	// Position of TZEN0 field.
	EXTI_EXTI_TZENR1_TZEN0_Pos = 0x0
	// Bit mask of TZEN0 field.
	EXTI_EXTI_TZENR1_TZEN0_Msk = 0x1
	// Bit TZEN0.
	EXTI_EXTI_TZENR1_TZEN0 = 0x1
	// Position of TZEN1 field.
	EXTI_EXTI_TZENR1_TZEN1_Pos = 0x1
	// Bit mask of TZEN1 field.
	EXTI_EXTI_TZENR1_TZEN1_Msk = 0x2
	// Bit TZEN1.
	EXTI_EXTI_TZENR1_TZEN1 = 0x2
	// Position of TZEN2 field.
	EXTI_EXTI_TZENR1_TZEN2_Pos = 0x2
	// Bit mask of TZEN2 field.
	EXTI_EXTI_TZENR1_TZEN2_Msk = 0x4
	// Bit TZEN2.
	EXTI_EXTI_TZENR1_TZEN2 = 0x4
	// Position of TZEN3 field.
	EXTI_EXTI_TZENR1_TZEN3_Pos = 0x3
	// Bit mask of TZEN3 field.
	EXTI_EXTI_TZENR1_TZEN3_Msk = 0x8
	// Bit TZEN3.
	EXTI_EXTI_TZENR1_TZEN3 = 0x8
	// Position of TZEN4 field.
	EXTI_EXTI_TZENR1_TZEN4_Pos = 0x4
	// Bit mask of TZEN4 field.
	EXTI_EXTI_TZENR1_TZEN4_Msk = 0x10
	// Bit TZEN4.
	EXTI_EXTI_TZENR1_TZEN4 = 0x10
	// Position of TZEN5 field.
	EXTI_EXTI_TZENR1_TZEN5_Pos = 0x5
	// Bit mask of TZEN5 field.
	EXTI_EXTI_TZENR1_TZEN5_Msk = 0x20
	// Bit TZEN5.
	EXTI_EXTI_TZENR1_TZEN5 = 0x20
	// Position of TZEN6 field.
	EXTI_EXTI_TZENR1_TZEN6_Pos = 0x6
	// Bit mask of TZEN6 field.
	EXTI_EXTI_TZENR1_TZEN6_Msk = 0x40
	// Bit TZEN6.
	EXTI_EXTI_TZENR1_TZEN6 = 0x40
	// Position of TZEN7 field.
	EXTI_EXTI_TZENR1_TZEN7_Pos = 0x7
	// Bit mask of TZEN7 field.
	EXTI_EXTI_TZENR1_TZEN7_Msk = 0x80
	// Bit TZEN7.
	EXTI_EXTI_TZENR1_TZEN7 = 0x80
	// Position of TZEN8 field.
	EXTI_EXTI_TZENR1_TZEN8_Pos = 0x8
	// Bit mask of TZEN8 field.
	EXTI_EXTI_TZENR1_TZEN8_Msk = 0x100
	// Bit TZEN8.
	EXTI_EXTI_TZENR1_TZEN8 = 0x100
	// Position of TZEN9 field.
	EXTI_EXTI_TZENR1_TZEN9_Pos = 0x9
	// Bit mask of TZEN9 field.
	EXTI_EXTI_TZENR1_TZEN9_Msk = 0x200
	// Bit TZEN9.
	EXTI_EXTI_TZENR1_TZEN9 = 0x200
	// Position of TZEN10 field.
	EXTI_EXTI_TZENR1_TZEN10_Pos = 0xa
	// Bit mask of TZEN10 field.
	EXTI_EXTI_TZENR1_TZEN10_Msk = 0x400
	// Bit TZEN10.
	EXTI_EXTI_TZENR1_TZEN10 = 0x400
	// Position of TZEN11 field.
	EXTI_EXTI_TZENR1_TZEN11_Pos = 0xb
	// Bit mask of TZEN11 field.
	EXTI_EXTI_TZENR1_TZEN11_Msk = 0x800
	// Bit TZEN11.
	EXTI_EXTI_TZENR1_TZEN11 = 0x800
	// Position of TZEN12 field.
	EXTI_EXTI_TZENR1_TZEN12_Pos = 0xc
	// Bit mask of TZEN12 field.
	EXTI_EXTI_TZENR1_TZEN12_Msk = 0x1000
	// Bit TZEN12.
	EXTI_EXTI_TZENR1_TZEN12 = 0x1000
	// Position of TZEN13 field.
	EXTI_EXTI_TZENR1_TZEN13_Pos = 0xd
	// Bit mask of TZEN13 field.
	EXTI_EXTI_TZENR1_TZEN13_Msk = 0x2000
	// Bit TZEN13.
	EXTI_EXTI_TZENR1_TZEN13 = 0x2000
	// Position of TZEN14 field.
	EXTI_EXTI_TZENR1_TZEN14_Pos = 0xe
	// Bit mask of TZEN14 field.
	EXTI_EXTI_TZENR1_TZEN14_Msk = 0x4000
	// Bit TZEN14.
	EXTI_EXTI_TZENR1_TZEN14 = 0x4000
	// Position of TZEN15 field.
	EXTI_EXTI_TZENR1_TZEN15_Pos = 0xf
	// Bit mask of TZEN15 field.
	EXTI_EXTI_TZENR1_TZEN15_Msk = 0x8000
	// Bit TZEN15.
	EXTI_EXTI_TZENR1_TZEN15 = 0x8000
	// Position of TZEN17 field.
	EXTI_EXTI_TZENR1_TZEN17_Pos = 0x11
	// Bit mask of TZEN17 field.
	EXTI_EXTI_TZENR1_TZEN17_Msk = 0x20000
	// Bit TZEN17.
	EXTI_EXTI_TZENR1_TZEN17 = 0x20000
	// Position of TZEN18 field.
	EXTI_EXTI_TZENR1_TZEN18_Pos = 0x12
	// Bit mask of TZEN18 field.
	EXTI_EXTI_TZENR1_TZEN18_Msk = 0x40000
	// Bit TZEN18.
	EXTI_EXTI_TZENR1_TZEN18 = 0x40000
	// Position of TZEN19 field.
	EXTI_EXTI_TZENR1_TZEN19_Pos = 0x13
	// Bit mask of TZEN19 field.
	EXTI_EXTI_TZENR1_TZEN19_Msk = 0x80000
	// Bit TZEN19.
	EXTI_EXTI_TZENR1_TZEN19 = 0x80000
	// Position of TZEN24 field.
	EXTI_EXTI_TZENR1_TZEN24_Pos = 0x18
	// Bit mask of TZEN24 field.
	EXTI_EXTI_TZENR1_TZEN24_Msk = 0x1000000
	// Bit TZEN24.
	EXTI_EXTI_TZENR1_TZEN24 = 0x1000000
	// Position of TZEN26 field.
	EXTI_EXTI_TZENR1_TZEN26_Pos = 0x1a
	// Bit mask of TZEN26 field.
	EXTI_EXTI_TZENR1_TZEN26_Msk = 0x4000000
	// Bit TZEN26.
	EXTI_EXTI_TZENR1_TZEN26 = 0x4000000

	// EXTI_TZENR2: This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.
	// Position of TZEN41 field.
	EXTI_EXTI_TZENR2_TZEN41_Pos = 0x9
	// Bit mask of TZEN41 field.
	EXTI_EXTI_TZENR2_TZEN41_Msk = 0x200
	// Bit TZEN41.
	EXTI_EXTI_TZENR2_TZEN41 = 0x200
	// Position of TZEN54 field.
	EXTI_EXTI_TZENR2_TZEN54_Pos = 0x16
	// Bit mask of TZEN54 field.
	EXTI_EXTI_TZENR2_TZEN54_Msk = 0x400000
	// Bit TZEN54.
	EXTI_EXTI_TZENR2_TZEN54 = 0x400000
	// Position of TZEN55 field.
	EXTI_EXTI_TZENR2_TZEN55_Pos = 0x17
	// Bit mask of TZEN55 field.
	EXTI_EXTI_TZENR2_TZEN55_Msk = 0x800000
	// Bit TZEN55.
	EXTI_EXTI_TZENR2_TZEN55 = 0x800000
	// Position of TZEN56 field.
	EXTI_EXTI_TZENR2_TZEN56_Pos = 0x18
	// Bit mask of TZEN56 field.
	EXTI_EXTI_TZENR2_TZEN56_Msk = 0x1000000
	// Bit TZEN56.
	EXTI_EXTI_TZENR2_TZEN56 = 0x1000000
	// Position of TZEN57 field.
	EXTI_EXTI_TZENR2_TZEN57_Pos = 0x19
	// Bit mask of TZEN57 field.
	EXTI_EXTI_TZENR2_TZEN57_Msk = 0x2000000
	// Bit TZEN57.
	EXTI_EXTI_TZENR2_TZEN57 = 0x2000000
	// Position of TZEN58 field.
	EXTI_EXTI_TZENR2_TZEN58_Pos = 0x1a
	// Bit mask of TZEN58 field.
	EXTI_EXTI_TZENR2_TZEN58_Msk = 0x4000000
	// Bit TZEN58.
	EXTI_EXTI_TZENR2_TZEN58 = 0x4000000
	// Position of TZEN59 field.
	EXTI_EXTI_TZENR2_TZEN59_Pos = 0x1b
	// Bit mask of TZEN59 field.
	EXTI_EXTI_TZENR2_TZEN59_Msk = 0x8000000
	// Bit TZEN59.
	EXTI_EXTI_TZENR2_TZEN59 = 0x8000000
	// Position of TZEN60 field.
	EXTI_EXTI_TZENR2_TZEN60_Pos = 0x1c
	// Bit mask of TZEN60 field.
	EXTI_EXTI_TZENR2_TZEN60_Msk = 0x10000000
	// Bit TZEN60.
	EXTI_EXTI_TZENR2_TZEN60 = 0x10000000

	// EXTI_RTSR3: Contains only register bits for configurable events.
	// Position of RT65 field.
	EXTI_EXTI_RTSR3_RT65_Pos = 0x1
	// Bit mask of RT65 field.
	EXTI_EXTI_RTSR3_RT65_Msk = 0x2
	// Bit RT65.
	EXTI_EXTI_RTSR3_RT65 = 0x2
	// Position of RT66 field.
	EXTI_EXTI_RTSR3_RT66_Pos = 0x2
	// Bit mask of RT66 field.
	EXTI_EXTI_RTSR3_RT66_Msk = 0x4
	// Bit RT66.
	EXTI_EXTI_RTSR3_RT66 = 0x4
	// Position of RT68 field.
	EXTI_EXTI_RTSR3_RT68_Pos = 0x4
	// Bit mask of RT68 field.
	EXTI_EXTI_RTSR3_RT68_Msk = 0x10
	// Bit RT68.
	EXTI_EXTI_RTSR3_RT68 = 0x10
	// Position of RT73 field.
	EXTI_EXTI_RTSR3_RT73_Pos = 0x9
	// Bit mask of RT73 field.
	EXTI_EXTI_RTSR3_RT73_Msk = 0x200
	// Bit RT73.
	EXTI_EXTI_RTSR3_RT73 = 0x200
	// Position of RT74 field.
	EXTI_EXTI_RTSR3_RT74_Pos = 0xa
	// Bit mask of RT74 field.
	EXTI_EXTI_RTSR3_RT74_Msk = 0x400
	// Bit RT74.
	EXTI_EXTI_RTSR3_RT74 = 0x400

	// EXTI_FTSR3: Contains only register bits for configurable events.
	// Position of FT65 field.
	EXTI_EXTI_FTSR3_FT65_Pos = 0x1
	// Bit mask of FT65 field.
	EXTI_EXTI_FTSR3_FT65_Msk = 0x2
	// Bit FT65.
	EXTI_EXTI_FTSR3_FT65 = 0x2
	// Position of FT66 field.
	EXTI_EXTI_FTSR3_FT66_Pos = 0x2
	// Bit mask of FT66 field.
	EXTI_EXTI_FTSR3_FT66_Msk = 0x4
	// Bit FT66.
	EXTI_EXTI_FTSR3_FT66 = 0x4
	// Position of FT68 field.
	EXTI_EXTI_FTSR3_FT68_Pos = 0x4
	// Bit mask of FT68 field.
	EXTI_EXTI_FTSR3_FT68_Msk = 0x10
	// Bit FT68.
	EXTI_EXTI_FTSR3_FT68 = 0x10
	// Position of FT73 field.
	EXTI_EXTI_FTSR3_FT73_Pos = 0x9
	// Bit mask of FT73 field.
	EXTI_EXTI_FTSR3_FT73_Msk = 0x200
	// Bit FT73.
	EXTI_EXTI_FTSR3_FT73 = 0x200
	// Position of FT74 field.
	EXTI_EXTI_FTSR3_FT74_Pos = 0xa
	// Bit mask of FT74 field.
	EXTI_EXTI_FTSR3_FT74_Msk = 0x400
	// Bit FT74.
	EXTI_EXTI_FTSR3_FT74 = 0x400

	// EXTI_SWIER3: Contains only register bits for configurable events.
	// Position of SWI65 field.
	EXTI_EXTI_SWIER3_SWI65_Pos = 0x1
	// Bit mask of SWI65 field.
	EXTI_EXTI_SWIER3_SWI65_Msk = 0x2
	// Bit SWI65.
	EXTI_EXTI_SWIER3_SWI65 = 0x2
	// Position of SWI66 field.
	EXTI_EXTI_SWIER3_SWI66_Pos = 0x2
	// Bit mask of SWI66 field.
	EXTI_EXTI_SWIER3_SWI66_Msk = 0x4
	// Bit SWI66.
	EXTI_EXTI_SWIER3_SWI66 = 0x4
	// Position of SWI68 field.
	EXTI_EXTI_SWIER3_SWI68_Pos = 0x4
	// Bit mask of SWI68 field.
	EXTI_EXTI_SWIER3_SWI68_Msk = 0x10
	// Bit SWI68.
	EXTI_EXTI_SWIER3_SWI68 = 0x10
	// Position of SWI73 field.
	EXTI_EXTI_SWIER3_SWI73_Pos = 0x9
	// Bit mask of SWI73 field.
	EXTI_EXTI_SWIER3_SWI73_Msk = 0x200
	// Bit SWI73.
	EXTI_EXTI_SWIER3_SWI73 = 0x200
	// Position of SWI74 field.
	EXTI_EXTI_SWIER3_SWI74_Pos = 0xa
	// Bit mask of SWI74 field.
	EXTI_EXTI_SWIER3_SWI74_Msk = 0x400
	// Bit SWI74.
	EXTI_EXTI_SWIER3_SWI74 = 0x400

	// EXTI_RPR3: Contains only register bits for configurable events.
	// Position of RPIF65 field.
	EXTI_EXTI_RPR3_RPIF65_Pos = 0x1
	// Bit mask of RPIF65 field.
	EXTI_EXTI_RPR3_RPIF65_Msk = 0x2
	// Bit RPIF65.
	EXTI_EXTI_RPR3_RPIF65 = 0x2
	// Position of RPIF66 field.
	EXTI_EXTI_RPR3_RPIF66_Pos = 0x2
	// Bit mask of RPIF66 field.
	EXTI_EXTI_RPR3_RPIF66_Msk = 0x4
	// Bit RPIF66.
	EXTI_EXTI_RPR3_RPIF66 = 0x4
	// Position of RPIF68 field.
	EXTI_EXTI_RPR3_RPIF68_Pos = 0x4
	// Bit mask of RPIF68 field.
	EXTI_EXTI_RPR3_RPIF68_Msk = 0x10
	// Bit RPIF68.
	EXTI_EXTI_RPR3_RPIF68 = 0x10
	// Position of RPIF73 field.
	EXTI_EXTI_RPR3_RPIF73_Pos = 0x9
	// Bit mask of RPIF73 field.
	EXTI_EXTI_RPR3_RPIF73_Msk = 0x200
	// Bit RPIF73.
	EXTI_EXTI_RPR3_RPIF73 = 0x200
	// Position of RPIF74 field.
	EXTI_EXTI_RPR3_RPIF74_Pos = 0xa
	// Bit mask of RPIF74 field.
	EXTI_EXTI_RPR3_RPIF74_Msk = 0x400
	// Bit RPIF74.
	EXTI_EXTI_RPR3_RPIF74 = 0x400

	// EXTI_FPR3: Contains only register bits for configurable events.
	// Position of FPIF65 field.
	EXTI_EXTI_FPR3_FPIF65_Pos = 0x1
	// Bit mask of FPIF65 field.
	EXTI_EXTI_FPR3_FPIF65_Msk = 0x2
	// Bit FPIF65.
	EXTI_EXTI_FPR3_FPIF65 = 0x2
	// Position of FPIF66 field.
	EXTI_EXTI_FPR3_FPIF66_Pos = 0x2
	// Bit mask of FPIF66 field.
	EXTI_EXTI_FPR3_FPIF66_Msk = 0x4
	// Bit FPIF66.
	EXTI_EXTI_FPR3_FPIF66 = 0x4
	// Position of FPIF68 field.
	EXTI_EXTI_FPR3_FPIF68_Pos = 0x4
	// Bit mask of FPIF68 field.
	EXTI_EXTI_FPR3_FPIF68_Msk = 0x10
	// Bit FPIF68.
	EXTI_EXTI_FPR3_FPIF68 = 0x10
	// Position of FPIF73 field.
	EXTI_EXTI_FPR3_FPIF73_Pos = 0x9
	// Bit mask of FPIF73 field.
	EXTI_EXTI_FPR3_FPIF73_Msk = 0x200
	// Bit FPIF73.
	EXTI_EXTI_FPR3_FPIF73 = 0x200
	// Position of FPIF74 field.
	EXTI_EXTI_FPR3_FPIF74_Pos = 0xa
	// Bit mask of FPIF74 field.
	EXTI_EXTI_FPR3_FPIF74_Msk = 0x400
	// Bit FPIF74.
	EXTI_EXTI_FPR3_FPIF74 = 0x400

	// EXTI_EXTICR1: EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
	// Position of EXTI0 field.
	EXTI_EXTI_EXTICR1_EXTI0_Pos = 0x0
	// Bit mask of EXTI0 field.
	EXTI_EXTI_EXTICR1_EXTI0_Msk = 0xff
	// Position of EXTI1 field.
	EXTI_EXTI_EXTICR1_EXTI1_Pos = 0x8
	// Bit mask of EXTI1 field.
	EXTI_EXTI_EXTICR1_EXTI1_Msk = 0xff00
	// Position of EXTI2 field.
	EXTI_EXTI_EXTICR1_EXTI2_Pos = 0x10
	// Bit mask of EXTI2 field.
	EXTI_EXTI_EXTICR1_EXTI2_Msk = 0xff0000
	// Position of EXTI3 field.
	EXTI_EXTI_EXTICR1_EXTI3_Pos = 0x18
	// Bit mask of EXTI3 field.
	EXTI_EXTI_EXTICR1_EXTI3_Msk = 0xff000000

	// EXTI_EXTICR2: EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
	// Position of EXTI4 field.
	EXTI_EXTI_EXTICR2_EXTI4_Pos = 0x0
	// Bit mask of EXTI4 field.
	EXTI_EXTI_EXTICR2_EXTI4_Msk = 0xff
	// Position of EXTI5 field.
	EXTI_EXTI_EXTICR2_EXTI5_Pos = 0x8
	// Bit mask of EXTI5 field.
	EXTI_EXTI_EXTICR2_EXTI5_Msk = 0xff00
	// Position of EXTI6 field.
	EXTI_EXTI_EXTICR2_EXTI6_Pos = 0x10
	// Bit mask of EXTI6 field.
	EXTI_EXTI_EXTICR2_EXTI6_Msk = 0xff0000
	// Position of EXTI7 field.
	EXTI_EXTI_EXTICR2_EXTI7_Pos = 0x18
	// Bit mask of EXTI7 field.
	EXTI_EXTI_EXTICR2_EXTI7_Msk = 0xff000000

	// EXTI_EXTICR3: EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
	// Position of EXTI8 field.
	EXTI_EXTI_EXTICR3_EXTI8_Pos = 0x0
	// Bit mask of EXTI8 field.
	EXTI_EXTI_EXTICR3_EXTI8_Msk = 0xff
	// Position of EXTI9 field.
	EXTI_EXTI_EXTICR3_EXTI9_Pos = 0x8
	// Bit mask of EXTI9 field.
	EXTI_EXTI_EXTICR3_EXTI9_Msk = 0xff00
	// Position of EXTI10 field.
	EXTI_EXTI_EXTICR3_EXTI10_Pos = 0x10
	// Bit mask of EXTI10 field.
	EXTI_EXTI_EXTICR3_EXTI10_Msk = 0xff0000
	// Position of EXTI11 field.
	EXTI_EXTI_EXTICR3_EXTI11_Pos = 0x18
	// Bit mask of EXTI11 field.
	EXTI_EXTI_EXTICR3_EXTI11_Msk = 0xff000000

	// EXTI_EXTICR4: EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
	// Position of EXTI12 field.
	EXTI_EXTI_EXTICR4_EXTI12_Pos = 0x0
	// Bit mask of EXTI12 field.
	EXTI_EXTI_EXTICR4_EXTI12_Msk = 0xff
	// Position of EXTI13 field.
	EXTI_EXTI_EXTICR4_EXTI13_Pos = 0x8
	// Bit mask of EXTI13 field.
	EXTI_EXTI_EXTICR4_EXTI13_Msk = 0xff00
	// Position of EXTI14 field.
	EXTI_EXTI_EXTICR4_EXTI14_Pos = 0x10
	// Bit mask of EXTI14 field.
	EXTI_EXTI_EXTICR4_EXTI14_Msk = 0xff0000
	// Position of EXTI15 field.
	EXTI_EXTI_EXTICR4_EXTI15_Pos = 0x18
	// Bit mask of EXTI15 field.
	EXTI_EXTI_EXTICR4_EXTI15_Msk = 0xff000000

	// EXTI_IMR1: Contains register bits for configurable events and Direct events.
	// Position of IM0 field.
	EXTI_EXTI_IMR1_IM0_Pos = 0x0
	// Bit mask of IM0 field.
	EXTI_EXTI_IMR1_IM0_Msk = 0x1
	// Bit IM0.
	EXTI_EXTI_IMR1_IM0 = 0x1
	// Position of IM1 field.
	EXTI_EXTI_IMR1_IM1_Pos = 0x1
	// Bit mask of IM1 field.
	EXTI_EXTI_IMR1_IM1_Msk = 0x2
	// Bit IM1.
	EXTI_EXTI_IMR1_IM1 = 0x2
	// Position of IM2 field.
	EXTI_EXTI_IMR1_IM2_Pos = 0x2
	// Bit mask of IM2 field.
	EXTI_EXTI_IMR1_IM2_Msk = 0x4
	// Bit IM2.
	EXTI_EXTI_IMR1_IM2 = 0x4
	// Position of IM3 field.
	EXTI_EXTI_IMR1_IM3_Pos = 0x3
	// Bit mask of IM3 field.
	EXTI_EXTI_IMR1_IM3_Msk = 0x8
	// Bit IM3.
	EXTI_EXTI_IMR1_IM3 = 0x8
	// Position of IM4 field.
	EXTI_EXTI_IMR1_IM4_Pos = 0x4
	// Bit mask of IM4 field.
	EXTI_EXTI_IMR1_IM4_Msk = 0x10
	// Bit IM4.
	EXTI_EXTI_IMR1_IM4 = 0x10
	// Position of IM5 field.
	EXTI_EXTI_IMR1_IM5_Pos = 0x5
	// Bit mask of IM5 field.
	EXTI_EXTI_IMR1_IM5_Msk = 0x20
	// Bit IM5.
	EXTI_EXTI_IMR1_IM5 = 0x20
	// Position of IM6 field.
	EXTI_EXTI_IMR1_IM6_Pos = 0x6
	// Bit mask of IM6 field.
	EXTI_EXTI_IMR1_IM6_Msk = 0x40
	// Bit IM6.
	EXTI_EXTI_IMR1_IM6 = 0x40
	// Position of IM7 field.
	EXTI_EXTI_IMR1_IM7_Pos = 0x7
	// Bit mask of IM7 field.
	EXTI_EXTI_IMR1_IM7_Msk = 0x80
	// Bit IM7.
	EXTI_EXTI_IMR1_IM7 = 0x80
	// Position of IM8 field.
	EXTI_EXTI_IMR1_IM8_Pos = 0x8
	// Bit mask of IM8 field.
	EXTI_EXTI_IMR1_IM8_Msk = 0x100
	// Bit IM8.
	EXTI_EXTI_IMR1_IM8 = 0x100
	// Position of IM9 field.
	EXTI_EXTI_IMR1_IM9_Pos = 0x9
	// Bit mask of IM9 field.
	EXTI_EXTI_IMR1_IM9_Msk = 0x200
	// Bit IM9.
	EXTI_EXTI_IMR1_IM9 = 0x200
	// Position of IM10 field.
	EXTI_EXTI_IMR1_IM10_Pos = 0xa
	// Bit mask of IM10 field.
	EXTI_EXTI_IMR1_IM10_Msk = 0x400
	// Bit IM10.
	EXTI_EXTI_IMR1_IM10 = 0x400
	// Position of IM11 field.
	EXTI_EXTI_IMR1_IM11_Pos = 0xb
	// Bit mask of IM11 field.
	EXTI_EXTI_IMR1_IM11_Msk = 0x800
	// Bit IM11.
	EXTI_EXTI_IMR1_IM11 = 0x800
	// Position of IM12 field.
	EXTI_EXTI_IMR1_IM12_Pos = 0xc
	// Bit mask of IM12 field.
	EXTI_EXTI_IMR1_IM12_Msk = 0x1000
	// Bit IM12.
	EXTI_EXTI_IMR1_IM12 = 0x1000
	// Position of IM13 field.
	EXTI_EXTI_IMR1_IM13_Pos = 0xd
	// Bit mask of IM13 field.
	EXTI_EXTI_IMR1_IM13_Msk = 0x2000
	// Bit IM13.
	EXTI_EXTI_IMR1_IM13 = 0x2000
	// Position of IM14 field.
	EXTI_EXTI_IMR1_IM14_Pos = 0xe
	// Bit mask of IM14 field.
	EXTI_EXTI_IMR1_IM14_Msk = 0x4000
	// Bit IM14.
	EXTI_EXTI_IMR1_IM14 = 0x4000
	// Position of IM15 field.
	EXTI_EXTI_IMR1_IM15_Pos = 0xf
	// Bit mask of IM15 field.
	EXTI_EXTI_IMR1_IM15_Msk = 0x8000
	// Bit IM15.
	EXTI_EXTI_IMR1_IM15 = 0x8000
	// Position of IM16 field.
	EXTI_EXTI_IMR1_IM16_Pos = 0x10
	// Bit mask of IM16 field.
	EXTI_EXTI_IMR1_IM16_Msk = 0x10000
	// Bit IM16.
	EXTI_EXTI_IMR1_IM16 = 0x10000
	// Position of IM17 field.
	EXTI_EXTI_IMR1_IM17_Pos = 0x11
	// Bit mask of IM17 field.
	EXTI_EXTI_IMR1_IM17_Msk = 0x20000
	// Bit IM17.
	EXTI_EXTI_IMR1_IM17 = 0x20000
	// Position of IM18 field.
	EXTI_EXTI_IMR1_IM18_Pos = 0x12
	// Bit mask of IM18 field.
	EXTI_EXTI_IMR1_IM18_Msk = 0x40000
	// Bit IM18.
	EXTI_EXTI_IMR1_IM18 = 0x40000
	// Position of IM19 field.
	EXTI_EXTI_IMR1_IM19_Pos = 0x13
	// Bit mask of IM19 field.
	EXTI_EXTI_IMR1_IM19_Msk = 0x80000
	// Bit IM19.
	EXTI_EXTI_IMR1_IM19 = 0x80000
	// Position of IM20 field.
	EXTI_EXTI_IMR1_IM20_Pos = 0x14
	// Bit mask of IM20 field.
	EXTI_EXTI_IMR1_IM20_Msk = 0x100000
	// Bit IM20.
	EXTI_EXTI_IMR1_IM20 = 0x100000
	// Position of IM21 field.
	EXTI_EXTI_IMR1_IM21_Pos = 0x15
	// Bit mask of IM21 field.
	EXTI_EXTI_IMR1_IM21_Msk = 0x200000
	// Bit IM21.
	EXTI_EXTI_IMR1_IM21 = 0x200000
	// Position of IM22 field.
	EXTI_EXTI_IMR1_IM22_Pos = 0x16
	// Bit mask of IM22 field.
	EXTI_EXTI_IMR1_IM22_Msk = 0x400000
	// Bit IM22.
	EXTI_EXTI_IMR1_IM22 = 0x400000
	// Position of IM23 field.
	EXTI_EXTI_IMR1_IM23_Pos = 0x17
	// Bit mask of IM23 field.
	EXTI_EXTI_IMR1_IM23_Msk = 0x800000
	// Bit IM23.
	EXTI_EXTI_IMR1_IM23 = 0x800000
	// Position of IM24 field.
	EXTI_EXTI_IMR1_IM24_Pos = 0x18
	// Bit mask of IM24 field.
	EXTI_EXTI_IMR1_IM24_Msk = 0x1000000
	// Bit IM24.
	EXTI_EXTI_IMR1_IM24 = 0x1000000
	// Position of IM25 field.
	EXTI_EXTI_IMR1_IM25_Pos = 0x19
	// Bit mask of IM25 field.
	EXTI_EXTI_IMR1_IM25_Msk = 0x2000000
	// Bit IM25.
	EXTI_EXTI_IMR1_IM25 = 0x2000000
	// Position of IM26 field.
	EXTI_EXTI_IMR1_IM26_Pos = 0x1a
	// Bit mask of IM26 field.
	EXTI_EXTI_IMR1_IM26_Msk = 0x4000000
	// Bit IM26.
	EXTI_EXTI_IMR1_IM26 = 0x4000000
	// Position of IM27 field.
	EXTI_EXTI_IMR1_IM27_Pos = 0x1b
	// Bit mask of IM27 field.
	EXTI_EXTI_IMR1_IM27_Msk = 0x8000000
	// Bit IM27.
	EXTI_EXTI_IMR1_IM27 = 0x8000000
	// Position of IM28 field.
	EXTI_EXTI_IMR1_IM28_Pos = 0x1c
	// Bit mask of IM28 field.
	EXTI_EXTI_IMR1_IM28_Msk = 0x10000000
	// Bit IM28.
	EXTI_EXTI_IMR1_IM28 = 0x10000000
	// Position of IM29 field.
	EXTI_EXTI_IMR1_IM29_Pos = 0x1d
	// Bit mask of IM29 field.
	EXTI_EXTI_IMR1_IM29_Msk = 0x20000000
	// Bit IM29.
	EXTI_EXTI_IMR1_IM29 = 0x20000000
	// Position of IM30 field.
	EXTI_EXTI_IMR1_IM30_Pos = 0x1e
	// Bit mask of IM30 field.
	EXTI_EXTI_IMR1_IM30_Msk = 0x40000000
	// Bit IM30.
	EXTI_EXTI_IMR1_IM30 = 0x40000000
	// Position of IM31 field.
	EXTI_EXTI_IMR1_IM31_Pos = 0x1f
	// Bit mask of IM31 field.
	EXTI_EXTI_IMR1_IM31_Msk = 0x80000000
	// Bit IM31.
	EXTI_EXTI_IMR1_IM31 = 0x80000000

	// EXTI_EMR1: EXTI CPU wakeup with event mask register
	// Position of EM0 field.
	EXTI_EXTI_EMR1_EM0_Pos = 0x0
	// Bit mask of EM0 field.
	EXTI_EXTI_EMR1_EM0_Msk = 0x1
	// Bit EM0.
	EXTI_EXTI_EMR1_EM0 = 0x1
	// Position of EM1 field.
	EXTI_EXTI_EMR1_EM1_Pos = 0x1
	// Bit mask of EM1 field.
	EXTI_EXTI_EMR1_EM1_Msk = 0x2
	// Bit EM1.
	EXTI_EXTI_EMR1_EM1 = 0x2
	// Position of EM2 field.
	EXTI_EXTI_EMR1_EM2_Pos = 0x2
	// Bit mask of EM2 field.
	EXTI_EXTI_EMR1_EM2_Msk = 0x4
	// Bit EM2.
	EXTI_EXTI_EMR1_EM2 = 0x4
	// Position of EM3 field.
	EXTI_EXTI_EMR1_EM3_Pos = 0x3
	// Bit mask of EM3 field.
	EXTI_EXTI_EMR1_EM3_Msk = 0x8
	// Bit EM3.
	EXTI_EXTI_EMR1_EM3 = 0x8
	// Position of EM4 field.
	EXTI_EXTI_EMR1_EM4_Pos = 0x4
	// Bit mask of EM4 field.
	EXTI_EXTI_EMR1_EM4_Msk = 0x10
	// Bit EM4.
	EXTI_EXTI_EMR1_EM4 = 0x10
	// Position of EM5 field.
	EXTI_EXTI_EMR1_EM5_Pos = 0x5
	// Bit mask of EM5 field.
	EXTI_EXTI_EMR1_EM5_Msk = 0x20
	// Bit EM5.
	EXTI_EXTI_EMR1_EM5 = 0x20
	// Position of EM6 field.
	EXTI_EXTI_EMR1_EM6_Pos = 0x6
	// Bit mask of EM6 field.
	EXTI_EXTI_EMR1_EM6_Msk = 0x40
	// Bit EM6.
	EXTI_EXTI_EMR1_EM6 = 0x40
	// Position of EM7 field.
	EXTI_EXTI_EMR1_EM7_Pos = 0x7
	// Bit mask of EM7 field.
	EXTI_EXTI_EMR1_EM7_Msk = 0x80
	// Bit EM7.
	EXTI_EXTI_EMR1_EM7 = 0x80
	// Position of EM8 field.
	EXTI_EXTI_EMR1_EM8_Pos = 0x8
	// Bit mask of EM8 field.
	EXTI_EXTI_EMR1_EM8_Msk = 0x100
	// Bit EM8.
	EXTI_EXTI_EMR1_EM8 = 0x100
	// Position of EM9 field.
	EXTI_EXTI_EMR1_EM9_Pos = 0x9
	// Bit mask of EM9 field.
	EXTI_EXTI_EMR1_EM9_Msk = 0x200
	// Bit EM9.
	EXTI_EXTI_EMR1_EM9 = 0x200
	// Position of EM10 field.
	EXTI_EXTI_EMR1_EM10_Pos = 0xa
	// Bit mask of EM10 field.
	EXTI_EXTI_EMR1_EM10_Msk = 0x400
	// Bit EM10.
	EXTI_EXTI_EMR1_EM10 = 0x400
	// Position of EM11 field.
	EXTI_EXTI_EMR1_EM11_Pos = 0xb
	// Bit mask of EM11 field.
	EXTI_EXTI_EMR1_EM11_Msk = 0x800
	// Bit EM11.
	EXTI_EXTI_EMR1_EM11 = 0x800
	// Position of EM12 field.
	EXTI_EXTI_EMR1_EM12_Pos = 0xc
	// Bit mask of EM12 field.
	EXTI_EXTI_EMR1_EM12_Msk = 0x1000
	// Bit EM12.
	EXTI_EXTI_EMR1_EM12 = 0x1000
	// Position of EM13 field.
	EXTI_EXTI_EMR1_EM13_Pos = 0xd
	// Bit mask of EM13 field.
	EXTI_EXTI_EMR1_EM13_Msk = 0x2000
	// Bit EM13.
	EXTI_EXTI_EMR1_EM13 = 0x2000
	// Position of EM14 field.
	EXTI_EXTI_EMR1_EM14_Pos = 0xe
	// Bit mask of EM14 field.
	EXTI_EXTI_EMR1_EM14_Msk = 0x4000
	// Bit EM14.
	EXTI_EXTI_EMR1_EM14 = 0x4000
	// Position of EM15 field.
	EXTI_EXTI_EMR1_EM15_Pos = 0xf
	// Bit mask of EM15 field.
	EXTI_EXTI_EMR1_EM15_Msk = 0x8000
	// Bit EM15.
	EXTI_EXTI_EMR1_EM15 = 0x8000
	// Position of EM17 field.
	EXTI_EXTI_EMR1_EM17_Pos = 0x11
	// Bit mask of EM17 field.
	EXTI_EXTI_EMR1_EM17_Msk = 0x20000
	// Bit EM17.
	EXTI_EXTI_EMR1_EM17 = 0x20000
	// Position of EM18 field.
	EXTI_EXTI_EMR1_EM18_Pos = 0x12
	// Bit mask of EM18 field.
	EXTI_EXTI_EMR1_EM18_Msk = 0x40000
	// Bit EM18.
	EXTI_EXTI_EMR1_EM18 = 0x40000
	// Position of EM19 field.
	EXTI_EXTI_EMR1_EM19_Pos = 0x13
	// Bit mask of EM19 field.
	EXTI_EXTI_EMR1_EM19_Msk = 0x80000
	// Bit EM19.
	EXTI_EXTI_EMR1_EM19 = 0x80000

	// EXTI_IMR2: Contains register bits for configurable events and direct events.
	// Position of IM32 field.
	EXTI_EXTI_IMR2_IM32_Pos = 0x0
	// Bit mask of IM32 field.
	EXTI_EXTI_IMR2_IM32_Msk = 0x1
	// Bit IM32.
	EXTI_EXTI_IMR2_IM32 = 0x1
	// Position of IM33 field.
	EXTI_EXTI_IMR2_IM33_Pos = 0x1
	// Bit mask of IM33 field.
	EXTI_EXTI_IMR2_IM33_Msk = 0x2
	// Bit IM33.
	EXTI_EXTI_IMR2_IM33 = 0x2
	// Position of IM34 field.
	EXTI_EXTI_IMR2_IM34_Pos = 0x2
	// Bit mask of IM34 field.
	EXTI_EXTI_IMR2_IM34_Msk = 0x4
	// Bit IM34.
	EXTI_EXTI_IMR2_IM34 = 0x4
	// Position of IM35 field.
	EXTI_EXTI_IMR2_IM35_Pos = 0x3
	// Bit mask of IM35 field.
	EXTI_EXTI_IMR2_IM35_Msk = 0x8
	// Bit IM35.
	EXTI_EXTI_IMR2_IM35 = 0x8
	// Position of IM36 field.
	EXTI_EXTI_IMR2_IM36_Pos = 0x4
	// Bit mask of IM36 field.
	EXTI_EXTI_IMR2_IM36_Msk = 0x10
	// Bit IM36.
	EXTI_EXTI_IMR2_IM36 = 0x10
	// Position of IM37 field.
	EXTI_EXTI_IMR2_IM37_Pos = 0x5
	// Bit mask of IM37 field.
	EXTI_EXTI_IMR2_IM37_Msk = 0x20
	// Bit IM37.
	EXTI_EXTI_IMR2_IM37 = 0x20
	// Position of IM38 field.
	EXTI_EXTI_IMR2_IM38_Pos = 0x6
	// Bit mask of IM38 field.
	EXTI_EXTI_IMR2_IM38_Msk = 0x40
	// Bit IM38.
	EXTI_EXTI_IMR2_IM38 = 0x40
	// Position of IM39 field.
	EXTI_EXTI_IMR2_IM39_Pos = 0x7
	// Bit mask of IM39 field.
	EXTI_EXTI_IMR2_IM39_Msk = 0x80
	// Bit IM39.
	EXTI_EXTI_IMR2_IM39 = 0x80
	// Position of IM40 field.
	EXTI_EXTI_IMR2_IM40_Pos = 0x8
	// Bit mask of IM40 field.
	EXTI_EXTI_IMR2_IM40_Msk = 0x100
	// Bit IM40.
	EXTI_EXTI_IMR2_IM40 = 0x100
	// Position of IM41 field.
	EXTI_EXTI_IMR2_IM41_Pos = 0x9
	// Bit mask of IM41 field.
	EXTI_EXTI_IMR2_IM41_Msk = 0x200
	// Bit IM41.
	EXTI_EXTI_IMR2_IM41 = 0x200
	// Position of IM42 field.
	EXTI_EXTI_IMR2_IM42_Pos = 0xa
	// Bit mask of IM42 field.
	EXTI_EXTI_IMR2_IM42_Msk = 0x400
	// Bit IM42.
	EXTI_EXTI_IMR2_IM42 = 0x400
	// Position of IM43 field.
	EXTI_EXTI_IMR2_IM43_Pos = 0xb
	// Bit mask of IM43 field.
	EXTI_EXTI_IMR2_IM43_Msk = 0x800
	// Bit IM43.
	EXTI_EXTI_IMR2_IM43 = 0x800
	// Position of IM44 field.
	EXTI_EXTI_IMR2_IM44_Pos = 0xc
	// Bit mask of IM44 field.
	EXTI_EXTI_IMR2_IM44_Msk = 0x1000
	// Bit IM44.
	EXTI_EXTI_IMR2_IM44 = 0x1000
	// Position of IM45 field.
	EXTI_EXTI_IMR2_IM45_Pos = 0xd
	// Bit mask of IM45 field.
	EXTI_EXTI_IMR2_IM45_Msk = 0x2000
	// Bit IM45.
	EXTI_EXTI_IMR2_IM45 = 0x2000
	// Position of IM46 field.
	EXTI_EXTI_IMR2_IM46_Pos = 0xe
	// Bit mask of IM46 field.
	EXTI_EXTI_IMR2_IM46_Msk = 0x4000
	// Bit IM46.
	EXTI_EXTI_IMR2_IM46 = 0x4000
	// Position of IM47 field.
	EXTI_EXTI_IMR2_IM47_Pos = 0xf
	// Bit mask of IM47 field.
	EXTI_EXTI_IMR2_IM47_Msk = 0x8000
	// Bit IM47.
	EXTI_EXTI_IMR2_IM47 = 0x8000
	// Position of IM48 field.
	EXTI_EXTI_IMR2_IM48_Pos = 0x10
	// Bit mask of IM48 field.
	EXTI_EXTI_IMR2_IM48_Msk = 0x10000
	// Bit IM48.
	EXTI_EXTI_IMR2_IM48 = 0x10000
	// Position of IM49 field.
	EXTI_EXTI_IMR2_IM49_Pos = 0x11
	// Bit mask of IM49 field.
	EXTI_EXTI_IMR2_IM49_Msk = 0x20000
	// Bit IM49.
	EXTI_EXTI_IMR2_IM49 = 0x20000
	// Position of IM50 field.
	EXTI_EXTI_IMR2_IM50_Pos = 0x12
	// Bit mask of IM50 field.
	EXTI_EXTI_IMR2_IM50_Msk = 0x40000
	// Bit IM50.
	EXTI_EXTI_IMR2_IM50 = 0x40000
	// Position of IM51 field.
	EXTI_EXTI_IMR2_IM51_Pos = 0x13
	// Bit mask of IM51 field.
	EXTI_EXTI_IMR2_IM51_Msk = 0x80000
	// Bit IM51.
	EXTI_EXTI_IMR2_IM51 = 0x80000
	// Position of IM52 field.
	EXTI_EXTI_IMR2_IM52_Pos = 0x14
	// Bit mask of IM52 field.
	EXTI_EXTI_IMR2_IM52_Msk = 0x100000
	// Bit IM52.
	EXTI_EXTI_IMR2_IM52 = 0x100000
	// Position of IM53 field.
	EXTI_EXTI_IMR2_IM53_Pos = 0x15
	// Bit mask of IM53 field.
	EXTI_EXTI_IMR2_IM53_Msk = 0x200000
	// Bit IM53.
	EXTI_EXTI_IMR2_IM53 = 0x200000
	// Position of IM54 field.
	EXTI_EXTI_IMR2_IM54_Pos = 0x16
	// Bit mask of IM54 field.
	EXTI_EXTI_IMR2_IM54_Msk = 0x400000
	// Bit IM54.
	EXTI_EXTI_IMR2_IM54 = 0x400000
	// Position of IM55 field.
	EXTI_EXTI_IMR2_IM55_Pos = 0x17
	// Bit mask of IM55 field.
	EXTI_EXTI_IMR2_IM55_Msk = 0x800000
	// Bit IM55.
	EXTI_EXTI_IMR2_IM55 = 0x800000
	// Position of IM56 field.
	EXTI_EXTI_IMR2_IM56_Pos = 0x18
	// Bit mask of IM56 field.
	EXTI_EXTI_IMR2_IM56_Msk = 0x1000000
	// Bit IM56.
	EXTI_EXTI_IMR2_IM56 = 0x1000000
	// Position of IM57 field.
	EXTI_EXTI_IMR2_IM57_Pos = 0x19
	// Bit mask of IM57 field.
	EXTI_EXTI_IMR2_IM57_Msk = 0x2000000
	// Bit IM57.
	EXTI_EXTI_IMR2_IM57 = 0x2000000
	// Position of IM58 field.
	EXTI_EXTI_IMR2_IM58_Pos = 0x1a
	// Bit mask of IM58 field.
	EXTI_EXTI_IMR2_IM58_Msk = 0x4000000
	// Bit IM58.
	EXTI_EXTI_IMR2_IM58 = 0x4000000
	// Position of IM59 field.
	EXTI_EXTI_IMR2_IM59_Pos = 0x1b
	// Bit mask of IM59 field.
	EXTI_EXTI_IMR2_IM59_Msk = 0x8000000
	// Bit IM59.
	EXTI_EXTI_IMR2_IM59 = 0x8000000
	// Position of IM60 field.
	EXTI_EXTI_IMR2_IM60_Pos = 0x1c
	// Bit mask of IM60 field.
	EXTI_EXTI_IMR2_IM60_Msk = 0x10000000
	// Bit IM60.
	EXTI_EXTI_IMR2_IM60 = 0x10000000
	// Position of IM61 field.
	EXTI_EXTI_IMR2_IM61_Pos = 0x1d
	// Bit mask of IM61 field.
	EXTI_EXTI_IMR2_IM61_Msk = 0x20000000
	// Bit IM61.
	EXTI_EXTI_IMR2_IM61 = 0x20000000
	// Position of IM62 field.
	EXTI_EXTI_IMR2_IM62_Pos = 0x1e
	// Bit mask of IM62 field.
	EXTI_EXTI_IMR2_IM62_Msk = 0x40000000
	// Bit IM62.
	EXTI_EXTI_IMR2_IM62 = 0x40000000
	// Position of IM63 field.
	EXTI_EXTI_IMR2_IM63_Pos = 0x1f
	// Bit mask of IM63 field.
	EXTI_EXTI_IMR2_IM63_Msk = 0x80000000
	// Bit IM63.
	EXTI_EXTI_IMR2_IM63 = 0x80000000

	// EXTI_IMR3: Contains register bits for configurable events and direct events.
	// Position of IM64 field.
	EXTI_EXTI_IMR3_IM64_Pos = 0x0
	// Bit mask of IM64 field.
	EXTI_EXTI_IMR3_IM64_Msk = 0x1
	// Bit IM64.
	EXTI_EXTI_IMR3_IM64 = 0x1
	// Position of IM65 field.
	EXTI_EXTI_IMR3_IM65_Pos = 0x1
	// Bit mask of IM65 field.
	EXTI_EXTI_IMR3_IM65_Msk = 0x2
	// Bit IM65.
	EXTI_EXTI_IMR3_IM65 = 0x2
	// Position of IM66 field.
	EXTI_EXTI_IMR3_IM66_Pos = 0x2
	// Bit mask of IM66 field.
	EXTI_EXTI_IMR3_IM66_Msk = 0x4
	// Bit IM66.
	EXTI_EXTI_IMR3_IM66 = 0x4
	// Position of IM67 field.
	EXTI_EXTI_IMR3_IM67_Pos = 0x3
	// Bit mask of IM67 field.
	EXTI_EXTI_IMR3_IM67_Msk = 0x8
	// Bit IM67.
	EXTI_EXTI_IMR3_IM67 = 0x8
	// Position of IM68 field.
	EXTI_EXTI_IMR3_IM68_Pos = 0x4
	// Bit mask of IM68 field.
	EXTI_EXTI_IMR3_IM68_Msk = 0x10
	// Bit IM68.
	EXTI_EXTI_IMR3_IM68 = 0x10
	// Position of IM69 field.
	EXTI_EXTI_IMR3_IM69_Pos = 0x5
	// Bit mask of IM69 field.
	EXTI_EXTI_IMR3_IM69_Msk = 0x20
	// Bit IM69.
	EXTI_EXTI_IMR3_IM69 = 0x20
	// Position of IM70 field.
	EXTI_EXTI_IMR3_IM70_Pos = 0x6
	// Bit mask of IM70 field.
	EXTI_EXTI_IMR3_IM70_Msk = 0x40
	// Bit IM70.
	EXTI_EXTI_IMR3_IM70 = 0x40
	// Position of IM71 field.
	EXTI_EXTI_IMR3_IM71_Pos = 0x7
	// Bit mask of IM71 field.
	EXTI_EXTI_IMR3_IM71_Msk = 0x80
	// Bit IM71.
	EXTI_EXTI_IMR3_IM71 = 0x80
	// Position of IM72 field.
	EXTI_EXTI_IMR3_IM72_Pos = 0x8
	// Bit mask of IM72 field.
	EXTI_EXTI_IMR3_IM72_Msk = 0x100
	// Bit IM72.
	EXTI_EXTI_IMR3_IM72 = 0x100
	// Position of IM73 field.
	EXTI_EXTI_IMR3_IM73_Pos = 0x9
	// Bit mask of IM73 field.
	EXTI_EXTI_IMR3_IM73_Msk = 0x200
	// Bit IM73.
	EXTI_EXTI_IMR3_IM73 = 0x200
	// Position of IM74 field.
	EXTI_EXTI_IMR3_IM74_Pos = 0xa
	// Bit mask of IM74 field.
	EXTI_EXTI_IMR3_IM74_Msk = 0x400
	// Bit IM74.
	EXTI_EXTI_IMR3_IM74 = 0x400
	// Position of IM75 field.
	EXTI_EXTI_IMR3_IM75_Pos = 0xb
	// Bit mask of IM75 field.
	EXTI_EXTI_IMR3_IM75_Msk = 0x800
	// Bit IM75.
	EXTI_EXTI_IMR3_IM75 = 0x800

	// EXTI_EMR3: EXTI CPU wakeup with event mask register
	// Position of EM66 field.
	EXTI_EXTI_EMR3_EM66_Pos = 0x2
	// Bit mask of EM66 field.
	EXTI_EXTI_EMR3_EM66_Msk = 0x4
	// Bit EM66.
	EXTI_EXTI_EMR3_EM66 = 0x4

	// EXTI_C2IMR1: Contains register bits for configurable events and Direct events.
	// Position of IM0 field.
	EXTI_EXTI_C2IMR1_IM0_Pos = 0x0
	// Bit mask of IM0 field.
	EXTI_EXTI_C2IMR1_IM0_Msk = 0x1
	// Bit IM0.
	EXTI_EXTI_C2IMR1_IM0 = 0x1
	// Position of IM1 field.
	EXTI_EXTI_C2IMR1_IM1_Pos = 0x1
	// Bit mask of IM1 field.
	EXTI_EXTI_C2IMR1_IM1_Msk = 0x2
	// Bit IM1.
	EXTI_EXTI_C2IMR1_IM1 = 0x2
	// Position of IM2 field.
	EXTI_EXTI_C2IMR1_IM2_Pos = 0x2
	// Bit mask of IM2 field.
	EXTI_EXTI_C2IMR1_IM2_Msk = 0x4
	// Bit IM2.
	EXTI_EXTI_C2IMR1_IM2 = 0x4
	// Position of IM3 field.
	EXTI_EXTI_C2IMR1_IM3_Pos = 0x3
	// Bit mask of IM3 field.
	EXTI_EXTI_C2IMR1_IM3_Msk = 0x8
	// Bit IM3.
	EXTI_EXTI_C2IMR1_IM3 = 0x8
	// Position of IM4 field.
	EXTI_EXTI_C2IMR1_IM4_Pos = 0x4
	// Bit mask of IM4 field.
	EXTI_EXTI_C2IMR1_IM4_Msk = 0x10
	// Bit IM4.
	EXTI_EXTI_C2IMR1_IM4 = 0x10
	// Position of IM5 field.
	EXTI_EXTI_C2IMR1_IM5_Pos = 0x5
	// Bit mask of IM5 field.
	EXTI_EXTI_C2IMR1_IM5_Msk = 0x20
	// Bit IM5.
	EXTI_EXTI_C2IMR1_IM5 = 0x20
	// Position of IM6 field.
	EXTI_EXTI_C2IMR1_IM6_Pos = 0x6
	// Bit mask of IM6 field.
	EXTI_EXTI_C2IMR1_IM6_Msk = 0x40
	// Bit IM6.
	EXTI_EXTI_C2IMR1_IM6 = 0x40
	// Position of IM7 field.
	EXTI_EXTI_C2IMR1_IM7_Pos = 0x7
	// Bit mask of IM7 field.
	EXTI_EXTI_C2IMR1_IM7_Msk = 0x80
	// Bit IM7.
	EXTI_EXTI_C2IMR1_IM7 = 0x80
	// Position of IM8 field.
	EXTI_EXTI_C2IMR1_IM8_Pos = 0x8
	// Bit mask of IM8 field.
	EXTI_EXTI_C2IMR1_IM8_Msk = 0x100
	// Bit IM8.
	EXTI_EXTI_C2IMR1_IM8 = 0x100
	// Position of IM9 field.
	EXTI_EXTI_C2IMR1_IM9_Pos = 0x9
	// Bit mask of IM9 field.
	EXTI_EXTI_C2IMR1_IM9_Msk = 0x200
	// Bit IM9.
	EXTI_EXTI_C2IMR1_IM9 = 0x200
	// Position of IM10 field.
	EXTI_EXTI_C2IMR1_IM10_Pos = 0xa
	// Bit mask of IM10 field.
	EXTI_EXTI_C2IMR1_IM10_Msk = 0x400
	// Bit IM10.
	EXTI_EXTI_C2IMR1_IM10 = 0x400
	// Position of IM11 field.
	EXTI_EXTI_C2IMR1_IM11_Pos = 0xb
	// Bit mask of IM11 field.
	EXTI_EXTI_C2IMR1_IM11_Msk = 0x800
	// Bit IM11.
	EXTI_EXTI_C2IMR1_IM11 = 0x800
	// Position of IM12 field.
	EXTI_EXTI_C2IMR1_IM12_Pos = 0xc
	// Bit mask of IM12 field.
	EXTI_EXTI_C2IMR1_IM12_Msk = 0x1000
	// Bit IM12.
	EXTI_EXTI_C2IMR1_IM12 = 0x1000
	// Position of IM13 field.
	EXTI_EXTI_C2IMR1_IM13_Pos = 0xd
	// Bit mask of IM13 field.
	EXTI_EXTI_C2IMR1_IM13_Msk = 0x2000
	// Bit IM13.
	EXTI_EXTI_C2IMR1_IM13 = 0x2000
	// Position of IM14 field.
	EXTI_EXTI_C2IMR1_IM14_Pos = 0xe
	// Bit mask of IM14 field.
	EXTI_EXTI_C2IMR1_IM14_Msk = 0x4000
	// Bit IM14.
	EXTI_EXTI_C2IMR1_IM14 = 0x4000
	// Position of IM15 field.
	EXTI_EXTI_C2IMR1_IM15_Pos = 0xf
	// Bit mask of IM15 field.
	EXTI_EXTI_C2IMR1_IM15_Msk = 0x8000
	// Bit IM15.
	EXTI_EXTI_C2IMR1_IM15 = 0x8000
	// Position of IM16 field.
	EXTI_EXTI_C2IMR1_IM16_Pos = 0x10
	// Bit mask of IM16 field.
	EXTI_EXTI_C2IMR1_IM16_Msk = 0x10000
	// Bit IM16.
	EXTI_EXTI_C2IMR1_IM16 = 0x10000
	// Position of IM17 field.
	EXTI_EXTI_C2IMR1_IM17_Pos = 0x11
	// Bit mask of IM17 field.
	EXTI_EXTI_C2IMR1_IM17_Msk = 0x20000
	// Bit IM17.
	EXTI_EXTI_C2IMR1_IM17 = 0x20000
	// Position of IM18 field.
	EXTI_EXTI_C2IMR1_IM18_Pos = 0x12
	// Bit mask of IM18 field.
	EXTI_EXTI_C2IMR1_IM18_Msk = 0x40000
	// Bit IM18.
	EXTI_EXTI_C2IMR1_IM18 = 0x40000
	// Position of IM19 field.
	EXTI_EXTI_C2IMR1_IM19_Pos = 0x13
	// Bit mask of IM19 field.
	EXTI_EXTI_C2IMR1_IM19_Msk = 0x80000
	// Bit IM19.
	EXTI_EXTI_C2IMR1_IM19 = 0x80000
	// Position of IM20 field.
	EXTI_EXTI_C2IMR1_IM20_Pos = 0x14
	// Bit mask of IM20 field.
	EXTI_EXTI_C2IMR1_IM20_Msk = 0x100000
	// Bit IM20.
	EXTI_EXTI_C2IMR1_IM20 = 0x100000
	// Position of IM21 field.
	EXTI_EXTI_C2IMR1_IM21_Pos = 0x15
	// Bit mask of IM21 field.
	EXTI_EXTI_C2IMR1_IM21_Msk = 0x200000
	// Bit IM21.
	EXTI_EXTI_C2IMR1_IM21 = 0x200000
	// Position of IM22 field.
	EXTI_EXTI_C2IMR1_IM22_Pos = 0x16
	// Bit mask of IM22 field.
	EXTI_EXTI_C2IMR1_IM22_Msk = 0x400000
	// Bit IM22.
	EXTI_EXTI_C2IMR1_IM22 = 0x400000
	// Position of IM23 field.
	EXTI_EXTI_C2IMR1_IM23_Pos = 0x17
	// Bit mask of IM23 field.
	EXTI_EXTI_C2IMR1_IM23_Msk = 0x800000
	// Bit IM23.
	EXTI_EXTI_C2IMR1_IM23 = 0x800000
	// Position of IM24 field.
	EXTI_EXTI_C2IMR1_IM24_Pos = 0x18
	// Bit mask of IM24 field.
	EXTI_EXTI_C2IMR1_IM24_Msk = 0x1000000
	// Bit IM24.
	EXTI_EXTI_C2IMR1_IM24 = 0x1000000
	// Position of IM25 field.
	EXTI_EXTI_C2IMR1_IM25_Pos = 0x19
	// Bit mask of IM25 field.
	EXTI_EXTI_C2IMR1_IM25_Msk = 0x2000000
	// Bit IM25.
	EXTI_EXTI_C2IMR1_IM25 = 0x2000000
	// Position of IM26 field.
	EXTI_EXTI_C2IMR1_IM26_Pos = 0x1a
	// Bit mask of IM26 field.
	EXTI_EXTI_C2IMR1_IM26_Msk = 0x4000000
	// Bit IM26.
	EXTI_EXTI_C2IMR1_IM26 = 0x4000000
	// Position of IM27 field.
	EXTI_EXTI_C2IMR1_IM27_Pos = 0x1b
	// Bit mask of IM27 field.
	EXTI_EXTI_C2IMR1_IM27_Msk = 0x8000000
	// Bit IM27.
	EXTI_EXTI_C2IMR1_IM27 = 0x8000000
	// Position of IM28 field.
	EXTI_EXTI_C2IMR1_IM28_Pos = 0x1c
	// Bit mask of IM28 field.
	EXTI_EXTI_C2IMR1_IM28_Msk = 0x10000000
	// Bit IM28.
	EXTI_EXTI_C2IMR1_IM28 = 0x10000000
	// Position of IM29 field.
	EXTI_EXTI_C2IMR1_IM29_Pos = 0x1d
	// Bit mask of IM29 field.
	EXTI_EXTI_C2IMR1_IM29_Msk = 0x20000000
	// Bit IM29.
	EXTI_EXTI_C2IMR1_IM29 = 0x20000000
	// Position of IM30 field.
	EXTI_EXTI_C2IMR1_IM30_Pos = 0x1e
	// Bit mask of IM30 field.
	EXTI_EXTI_C2IMR1_IM30_Msk = 0x40000000
	// Bit IM30.
	EXTI_EXTI_C2IMR1_IM30 = 0x40000000
	// Position of IM31 field.
	EXTI_EXTI_C2IMR1_IM31_Pos = 0x1f
	// Bit mask of IM31 field.
	EXTI_EXTI_C2IMR1_IM31_Msk = 0x80000000
	// Bit IM31.
	EXTI_EXTI_C2IMR1_IM31 = 0x80000000

	// EXTI_C2EMR1: EXTI CPU2 wakeup with event mask register
	// Position of EM0 field.
	EXTI_EXTI_C2EMR1_EM0_Pos = 0x0
	// Bit mask of EM0 field.
	EXTI_EXTI_C2EMR1_EM0_Msk = 0x1
	// Bit EM0.
	EXTI_EXTI_C2EMR1_EM0 = 0x1
	// Position of EM1 field.
	EXTI_EXTI_C2EMR1_EM1_Pos = 0x1
	// Bit mask of EM1 field.
	EXTI_EXTI_C2EMR1_EM1_Msk = 0x2
	// Bit EM1.
	EXTI_EXTI_C2EMR1_EM1 = 0x2
	// Position of EM2 field.
	EXTI_EXTI_C2EMR1_EM2_Pos = 0x2
	// Bit mask of EM2 field.
	EXTI_EXTI_C2EMR1_EM2_Msk = 0x4
	// Bit EM2.
	EXTI_EXTI_C2EMR1_EM2 = 0x4
	// Position of EM3 field.
	EXTI_EXTI_C2EMR1_EM3_Pos = 0x3
	// Bit mask of EM3 field.
	EXTI_EXTI_C2EMR1_EM3_Msk = 0x8
	// Bit EM3.
	EXTI_EXTI_C2EMR1_EM3 = 0x8
	// Position of EM4 field.
	EXTI_EXTI_C2EMR1_EM4_Pos = 0x4
	// Bit mask of EM4 field.
	EXTI_EXTI_C2EMR1_EM4_Msk = 0x10
	// Bit EM4.
	EXTI_EXTI_C2EMR1_EM4 = 0x10
	// Position of EM5 field.
	EXTI_EXTI_C2EMR1_EM5_Pos = 0x5
	// Bit mask of EM5 field.
	EXTI_EXTI_C2EMR1_EM5_Msk = 0x20
	// Bit EM5.
	EXTI_EXTI_C2EMR1_EM5 = 0x20
	// Position of EM6 field.
	EXTI_EXTI_C2EMR1_EM6_Pos = 0x6
	// Bit mask of EM6 field.
	EXTI_EXTI_C2EMR1_EM6_Msk = 0x40
	// Bit EM6.
	EXTI_EXTI_C2EMR1_EM6 = 0x40
	// Position of EM7 field.
	EXTI_EXTI_C2EMR1_EM7_Pos = 0x7
	// Bit mask of EM7 field.
	EXTI_EXTI_C2EMR1_EM7_Msk = 0x80
	// Bit EM7.
	EXTI_EXTI_C2EMR1_EM7 = 0x80
	// Position of EM8 field.
	EXTI_EXTI_C2EMR1_EM8_Pos = 0x8
	// Bit mask of EM8 field.
	EXTI_EXTI_C2EMR1_EM8_Msk = 0x100
	// Bit EM8.
	EXTI_EXTI_C2EMR1_EM8 = 0x100
	// Position of EM9 field.
	EXTI_EXTI_C2EMR1_EM9_Pos = 0x9
	// Bit mask of EM9 field.
	EXTI_EXTI_C2EMR1_EM9_Msk = 0x200
	// Bit EM9.
	EXTI_EXTI_C2EMR1_EM9 = 0x200
	// Position of EM10 field.
	EXTI_EXTI_C2EMR1_EM10_Pos = 0xa
	// Bit mask of EM10 field.
	EXTI_EXTI_C2EMR1_EM10_Msk = 0x400
	// Bit EM10.
	EXTI_EXTI_C2EMR1_EM10 = 0x400
	// Position of EM11 field.
	EXTI_EXTI_C2EMR1_EM11_Pos = 0xb
	// Bit mask of EM11 field.
	EXTI_EXTI_C2EMR1_EM11_Msk = 0x800
	// Bit EM11.
	EXTI_EXTI_C2EMR1_EM11 = 0x800
	// Position of EM12 field.
	EXTI_EXTI_C2EMR1_EM12_Pos = 0xc
	// Bit mask of EM12 field.
	EXTI_EXTI_C2EMR1_EM12_Msk = 0x1000
	// Bit EM12.
	EXTI_EXTI_C2EMR1_EM12 = 0x1000
	// Position of EM13 field.
	EXTI_EXTI_C2EMR1_EM13_Pos = 0xd
	// Bit mask of EM13 field.
	EXTI_EXTI_C2EMR1_EM13_Msk = 0x2000
	// Bit EM13.
	EXTI_EXTI_C2EMR1_EM13 = 0x2000
	// Position of EM14 field.
	EXTI_EXTI_C2EMR1_EM14_Pos = 0xe
	// Bit mask of EM14 field.
	EXTI_EXTI_C2EMR1_EM14_Msk = 0x4000
	// Bit EM14.
	EXTI_EXTI_C2EMR1_EM14 = 0x4000
	// Position of EM15 field.
	EXTI_EXTI_C2EMR1_EM15_Pos = 0xf
	// Bit mask of EM15 field.
	EXTI_EXTI_C2EMR1_EM15_Msk = 0x8000
	// Bit EM15.
	EXTI_EXTI_C2EMR1_EM15 = 0x8000
	// Position of EM17 field.
	EXTI_EXTI_C2EMR1_EM17_Pos = 0x11
	// Bit mask of EM17 field.
	EXTI_EXTI_C2EMR1_EM17_Msk = 0x20000
	// Bit EM17.
	EXTI_EXTI_C2EMR1_EM17 = 0x20000
	// Position of EM18 field.
	EXTI_EXTI_C2EMR1_EM18_Pos = 0x12
	// Bit mask of EM18 field.
	EXTI_EXTI_C2EMR1_EM18_Msk = 0x40000
	// Bit EM18.
	EXTI_EXTI_C2EMR1_EM18 = 0x40000
	// Position of EM19 field.
	EXTI_EXTI_C2EMR1_EM19_Pos = 0x13
	// Bit mask of EM19 field.
	EXTI_EXTI_C2EMR1_EM19_Msk = 0x80000
	// Bit EM19.
	EXTI_EXTI_C2EMR1_EM19 = 0x80000

	// EXTI_C2IMR2: Contains register bits for configurable events and direct events.
	// Position of IM32 field.
	EXTI_EXTI_C2IMR2_IM32_Pos = 0x0
	// Bit mask of IM32 field.
	EXTI_EXTI_C2IMR2_IM32_Msk = 0x1
	// Bit IM32.
	EXTI_EXTI_C2IMR2_IM32 = 0x1
	// Position of IM33 field.
	EXTI_EXTI_C2IMR2_IM33_Pos = 0x1
	// Bit mask of IM33 field.
	EXTI_EXTI_C2IMR2_IM33_Msk = 0x2
	// Bit IM33.
	EXTI_EXTI_C2IMR2_IM33 = 0x2
	// Position of IM34 field.
	EXTI_EXTI_C2IMR2_IM34_Pos = 0x2
	// Bit mask of IM34 field.
	EXTI_EXTI_C2IMR2_IM34_Msk = 0x4
	// Bit IM34.
	EXTI_EXTI_C2IMR2_IM34 = 0x4
	// Position of IM35 field.
	EXTI_EXTI_C2IMR2_IM35_Pos = 0x3
	// Bit mask of IM35 field.
	EXTI_EXTI_C2IMR2_IM35_Msk = 0x8
	// Bit IM35.
	EXTI_EXTI_C2IMR2_IM35 = 0x8
	// Position of IM36 field.
	EXTI_EXTI_C2IMR2_IM36_Pos = 0x4
	// Bit mask of IM36 field.
	EXTI_EXTI_C2IMR2_IM36_Msk = 0x10
	// Bit IM36.
	EXTI_EXTI_C2IMR2_IM36 = 0x10
	// Position of IM37 field.
	EXTI_EXTI_C2IMR2_IM37_Pos = 0x5
	// Bit mask of IM37 field.
	EXTI_EXTI_C2IMR2_IM37_Msk = 0x20
	// Bit IM37.
	EXTI_EXTI_C2IMR2_IM37 = 0x20
	// Position of IM38 field.
	EXTI_EXTI_C2IMR2_IM38_Pos = 0x6
	// Bit mask of IM38 field.
	EXTI_EXTI_C2IMR2_IM38_Msk = 0x40
	// Bit IM38.
	EXTI_EXTI_C2IMR2_IM38 = 0x40
	// Position of IM39 field.
	EXTI_EXTI_C2IMR2_IM39_Pos = 0x7
	// Bit mask of IM39 field.
	EXTI_EXTI_C2IMR2_IM39_Msk = 0x80
	// Bit IM39.
	EXTI_EXTI_C2IMR2_IM39 = 0x80
	// Position of IM40 field.
	EXTI_EXTI_C2IMR2_IM40_Pos = 0x8
	// Bit mask of IM40 field.
	EXTI_EXTI_C2IMR2_IM40_Msk = 0x100
	// Bit IM40.
	EXTI_EXTI_C2IMR2_IM40 = 0x100
	// Position of IM41 field.
	EXTI_EXTI_C2IMR2_IM41_Pos = 0x9
	// Bit mask of IM41 field.
	EXTI_EXTI_C2IMR2_IM41_Msk = 0x200
	// Bit IM41.
	EXTI_EXTI_C2IMR2_IM41 = 0x200
	// Position of IM42 field.
	EXTI_EXTI_C2IMR2_IM42_Pos = 0xa
	// Bit mask of IM42 field.
	EXTI_EXTI_C2IMR2_IM42_Msk = 0x400
	// Bit IM42.
	EXTI_EXTI_C2IMR2_IM42 = 0x400
	// Position of IM43 field.
	EXTI_EXTI_C2IMR2_IM43_Pos = 0xb
	// Bit mask of IM43 field.
	EXTI_EXTI_C2IMR2_IM43_Msk = 0x800
	// Bit IM43.
	EXTI_EXTI_C2IMR2_IM43 = 0x800
	// Position of IM44 field.
	EXTI_EXTI_C2IMR2_IM44_Pos = 0xc
	// Bit mask of IM44 field.
	EXTI_EXTI_C2IMR2_IM44_Msk = 0x1000
	// Bit IM44.
	EXTI_EXTI_C2IMR2_IM44 = 0x1000
	// Position of IM45 field.
	EXTI_EXTI_C2IMR2_IM45_Pos = 0xd
	// Bit mask of IM45 field.
	EXTI_EXTI_C2IMR2_IM45_Msk = 0x2000
	// Bit IM45.
	EXTI_EXTI_C2IMR2_IM45 = 0x2000
	// Position of IM46 field.
	EXTI_EXTI_C2IMR2_IM46_Pos = 0xe
	// Bit mask of IM46 field.
	EXTI_EXTI_C2IMR2_IM46_Msk = 0x4000
	// Bit IM46.
	EXTI_EXTI_C2IMR2_IM46 = 0x4000
	// Position of IM47 field.
	EXTI_EXTI_C2IMR2_IM47_Pos = 0xf
	// Bit mask of IM47 field.
	EXTI_EXTI_C2IMR2_IM47_Msk = 0x8000
	// Bit IM47.
	EXTI_EXTI_C2IMR2_IM47 = 0x8000
	// Position of IM48 field.
	EXTI_EXTI_C2IMR2_IM48_Pos = 0x10
	// Bit mask of IM48 field.
	EXTI_EXTI_C2IMR2_IM48_Msk = 0x10000
	// Bit IM48.
	EXTI_EXTI_C2IMR2_IM48 = 0x10000
	// Position of IM49 field.
	EXTI_EXTI_C2IMR2_IM49_Pos = 0x11
	// Bit mask of IM49 field.
	EXTI_EXTI_C2IMR2_IM49_Msk = 0x20000
	// Bit IM49.
	EXTI_EXTI_C2IMR2_IM49 = 0x20000
	// Position of IM50 field.
	EXTI_EXTI_C2IMR2_IM50_Pos = 0x12
	// Bit mask of IM50 field.
	EXTI_EXTI_C2IMR2_IM50_Msk = 0x40000
	// Bit IM50.
	EXTI_EXTI_C2IMR2_IM50 = 0x40000
	// Position of IM51 field.
	EXTI_EXTI_C2IMR2_IM51_Pos = 0x13
	// Bit mask of IM51 field.
	EXTI_EXTI_C2IMR2_IM51_Msk = 0x80000
	// Bit IM51.
	EXTI_EXTI_C2IMR2_IM51 = 0x80000
	// Position of IM52 field.
	EXTI_EXTI_C2IMR2_IM52_Pos = 0x14
	// Bit mask of IM52 field.
	EXTI_EXTI_C2IMR2_IM52_Msk = 0x100000
	// Bit IM52.
	EXTI_EXTI_C2IMR2_IM52 = 0x100000
	// Position of IM53 field.
	EXTI_EXTI_C2IMR2_IM53_Pos = 0x15
	// Bit mask of IM53 field.
	EXTI_EXTI_C2IMR2_IM53_Msk = 0x200000
	// Bit IM53.
	EXTI_EXTI_C2IMR2_IM53 = 0x200000
	// Position of IM54 field.
	EXTI_EXTI_C2IMR2_IM54_Pos = 0x16
	// Bit mask of IM54 field.
	EXTI_EXTI_C2IMR2_IM54_Msk = 0x400000
	// Bit IM54.
	EXTI_EXTI_C2IMR2_IM54 = 0x400000
	// Position of IM55 field.
	EXTI_EXTI_C2IMR2_IM55_Pos = 0x17
	// Bit mask of IM55 field.
	EXTI_EXTI_C2IMR2_IM55_Msk = 0x800000
	// Bit IM55.
	EXTI_EXTI_C2IMR2_IM55 = 0x800000
	// Position of IM56 field.
	EXTI_EXTI_C2IMR2_IM56_Pos = 0x18
	// Bit mask of IM56 field.
	EXTI_EXTI_C2IMR2_IM56_Msk = 0x1000000
	// Bit IM56.
	EXTI_EXTI_C2IMR2_IM56 = 0x1000000
	// Position of IM57 field.
	EXTI_EXTI_C2IMR2_IM57_Pos = 0x19
	// Bit mask of IM57 field.
	EXTI_EXTI_C2IMR2_IM57_Msk = 0x2000000
	// Bit IM57.
	EXTI_EXTI_C2IMR2_IM57 = 0x2000000
	// Position of IM58 field.
	EXTI_EXTI_C2IMR2_IM58_Pos = 0x1a
	// Bit mask of IM58 field.
	EXTI_EXTI_C2IMR2_IM58_Msk = 0x4000000
	// Bit IM58.
	EXTI_EXTI_C2IMR2_IM58 = 0x4000000
	// Position of IM59 field.
	EXTI_EXTI_C2IMR2_IM59_Pos = 0x1b
	// Bit mask of IM59 field.
	EXTI_EXTI_C2IMR2_IM59_Msk = 0x8000000
	// Bit IM59.
	EXTI_EXTI_C2IMR2_IM59 = 0x8000000
	// Position of IM60 field.
	EXTI_EXTI_C2IMR2_IM60_Pos = 0x1c
	// Bit mask of IM60 field.
	EXTI_EXTI_C2IMR2_IM60_Msk = 0x10000000
	// Bit IM60.
	EXTI_EXTI_C2IMR2_IM60 = 0x10000000
	// Position of IM61 field.
	EXTI_EXTI_C2IMR2_IM61_Pos = 0x1d
	// Bit mask of IM61 field.
	EXTI_EXTI_C2IMR2_IM61_Msk = 0x20000000
	// Bit IM61.
	EXTI_EXTI_C2IMR2_IM61 = 0x20000000
	// Position of IM62 field.
	EXTI_EXTI_C2IMR2_IM62_Pos = 0x1e
	// Bit mask of IM62 field.
	EXTI_EXTI_C2IMR2_IM62_Msk = 0x40000000
	// Bit IM62.
	EXTI_EXTI_C2IMR2_IM62 = 0x40000000
	// Position of IM63 field.
	EXTI_EXTI_C2IMR2_IM63_Pos = 0x1f
	// Bit mask of IM63 field.
	EXTI_EXTI_C2IMR2_IM63_Msk = 0x80000000
	// Bit IM63.
	EXTI_EXTI_C2IMR2_IM63 = 0x80000000

	// EXTI_C2IMR3: Contains register bits for configurable events and direct events.
	// Position of IM64 field.
	EXTI_EXTI_C2IMR3_IM64_Pos = 0x0
	// Bit mask of IM64 field.
	EXTI_EXTI_C2IMR3_IM64_Msk = 0x1
	// Bit IM64.
	EXTI_EXTI_C2IMR3_IM64 = 0x1
	// Position of IM65 field.
	EXTI_EXTI_C2IMR3_IM65_Pos = 0x1
	// Bit mask of IM65 field.
	EXTI_EXTI_C2IMR3_IM65_Msk = 0x2
	// Bit IM65.
	EXTI_EXTI_C2IMR3_IM65 = 0x2
	// Position of IM66 field.
	EXTI_EXTI_C2IMR3_IM66_Pos = 0x2
	// Bit mask of IM66 field.
	EXTI_EXTI_C2IMR3_IM66_Msk = 0x4
	// Bit IM66.
	EXTI_EXTI_C2IMR3_IM66 = 0x4
	// Position of IM67 field.
	EXTI_EXTI_C2IMR3_IM67_Pos = 0x3
	// Bit mask of IM67 field.
	EXTI_EXTI_C2IMR3_IM67_Msk = 0x8
	// Bit IM67.
	EXTI_EXTI_C2IMR3_IM67 = 0x8
	// Position of IM68 field.
	EXTI_EXTI_C2IMR3_IM68_Pos = 0x4
	// Bit mask of IM68 field.
	EXTI_EXTI_C2IMR3_IM68_Msk = 0x10
	// Bit IM68.
	EXTI_EXTI_C2IMR3_IM68 = 0x10
	// Position of IM69 field.
	EXTI_EXTI_C2IMR3_IM69_Pos = 0x5
	// Bit mask of IM69 field.
	EXTI_EXTI_C2IMR3_IM69_Msk = 0x20
	// Bit IM69.
	EXTI_EXTI_C2IMR3_IM69 = 0x20
	// Position of IM70 field.
	EXTI_EXTI_C2IMR3_IM70_Pos = 0x6
	// Bit mask of IM70 field.
	EXTI_EXTI_C2IMR3_IM70_Msk = 0x40
	// Bit IM70.
	EXTI_EXTI_C2IMR3_IM70 = 0x40
	// Position of IM71 field.
	EXTI_EXTI_C2IMR3_IM71_Pos = 0x7
	// Bit mask of IM71 field.
	EXTI_EXTI_C2IMR3_IM71_Msk = 0x80
	// Bit IM71.
	EXTI_EXTI_C2IMR3_IM71 = 0x80
	// Position of IM72 field.
	EXTI_EXTI_C2IMR3_IM72_Pos = 0x8
	// Bit mask of IM72 field.
	EXTI_EXTI_C2IMR3_IM72_Msk = 0x100
	// Bit IM72.
	EXTI_EXTI_C2IMR3_IM72 = 0x100
	// Position of IM73 field.
	EXTI_EXTI_C2IMR3_IM73_Pos = 0x9
	// Bit mask of IM73 field.
	EXTI_EXTI_C2IMR3_IM73_Msk = 0x200
	// Bit IM73.
	EXTI_EXTI_C2IMR3_IM73 = 0x200
	// Position of IM74 field.
	EXTI_EXTI_C2IMR3_IM74_Pos = 0xa
	// Bit mask of IM74 field.
	EXTI_EXTI_C2IMR3_IM74_Msk = 0x400
	// Bit IM74.
	EXTI_EXTI_C2IMR3_IM74 = 0x400
	// Position of IM75 field.
	EXTI_EXTI_C2IMR3_IM75_Pos = 0xb
	// Bit mask of IM75 field.
	EXTI_EXTI_C2IMR3_IM75_Msk = 0x800
	// Bit IM75.
	EXTI_EXTI_C2IMR3_IM75 = 0x800

	// EXTI_C2EMR3: EXTI CPU2 wakeup with event mask register
	// Position of EM66 field.
	EXTI_EXTI_C2EMR3_EM66_Pos = 0x2
	// Bit mask of EM66 field.
	EXTI_EXTI_C2EMR3_EM66_Msk = 0x4
	// Bit EM66.
	EXTI_EXTI_C2EMR3_EM66 = 0x4

	// EXTI_HWCFGR13: EXTI hardware configuration register 13
	// Position of TZ field.
	EXTI_EXTI_HWCFGR13_TZ_Pos = 0x0
	// Bit mask of TZ field.
	EXTI_EXTI_HWCFGR13_TZ_Msk = 0xffffffff

	// EXTI_HWCFGR12: EXTI hardware configuration register 12
	// Position of TZ field.
	EXTI_EXTI_HWCFGR12_TZ_Pos = 0x0
	// Bit mask of TZ field.
	EXTI_EXTI_HWCFGR12_TZ_Msk = 0xffffffff

	// EXTI_HWCFGR11: EXTI hardware configuration register 11
	// Position of TZ field.
	EXTI_EXTI_HWCFGR11_TZ_Pos = 0x0
	// Bit mask of TZ field.
	EXTI_EXTI_HWCFGR11_TZ_Msk = 0xffffffff

	// EXTI_HWCFGR7: EXTI hardware configuration register 7
	// Position of CPUEVENT field.
	EXTI_EXTI_HWCFGR7_CPUEVENT_Pos = 0x0
	// Bit mask of CPUEVENT field.
	EXTI_EXTI_HWCFGR7_CPUEVENT_Msk = 0xffffffff

	// EXTI_HWCFGR6: EXTI hardware configuration register 6
	// Position of CPUEVENT field.
	EXTI_EXTI_HWCFGR6_CPUEVENT_Pos = 0x0
	// Bit mask of CPUEVENT field.
	EXTI_EXTI_HWCFGR6_CPUEVENT_Msk = 0xffffffff

	// EXTI_HWCFGR5: EXTI hardware configuration register 5
	// Position of CPUEVENT field.
	EXTI_EXTI_HWCFGR5_CPUEVENT_Pos = 0x0
	// Bit mask of CPUEVENT field.
	EXTI_EXTI_HWCFGR5_CPUEVENT_Msk = 0xffffffff

	// EXTI_HWCFGR4: EXTI hardware configuration register 4
	// Position of EVENT_TRG field.
	EXTI_EXTI_HWCFGR4_EVENT_TRG_Pos = 0x0
	// Bit mask of EVENT_TRG field.
	EXTI_EXTI_HWCFGR4_EVENT_TRG_Msk = 0xffffffff

	// EXTI_HWCFGR3: EXTI hardware configuration register 3
	// Position of EVENT_TRG field.
	EXTI_EXTI_HWCFGR3_EVENT_TRG_Pos = 0x0
	// Bit mask of EVENT_TRG field.
	EXTI_EXTI_HWCFGR3_EVENT_TRG_Msk = 0xffffffff

	// EXTI_HWCFGR2: EXTI hardware configuration register 2
	// Position of EVENT_TRG field.
	EXTI_EXTI_HWCFGR2_EVENT_TRG_Pos = 0x0
	// Bit mask of EVENT_TRG field.
	EXTI_EXTI_HWCFGR2_EVENT_TRG_Msk = 0xffffffff

	// EXTI_HWCFGR1: EXTI hardware configuration register 1
	// Position of NBEVENTS field.
	EXTI_EXTI_HWCFGR1_NBEVENTS_Pos = 0x0
	// Bit mask of NBEVENTS field.
	EXTI_EXTI_HWCFGR1_NBEVENTS_Msk = 0xff
	// Position of NBCPUS field.
	EXTI_EXTI_HWCFGR1_NBCPUS_Pos = 0x8
	// Bit mask of NBCPUS field.
	EXTI_EXTI_HWCFGR1_NBCPUS_Msk = 0xf00
	// Position of CPUEVTEN field.
	EXTI_EXTI_HWCFGR1_CPUEVTEN_Pos = 0xc
	// Bit mask of CPUEVTEN field.
	EXTI_EXTI_HWCFGR1_CPUEVTEN_Msk = 0xf000
	// Position of NBIOPORT field.
	EXTI_EXTI_HWCFGR1_NBIOPORT_Pos = 0x10
	// Bit mask of NBIOPORT field.
	EXTI_EXTI_HWCFGR1_NBIOPORT_Msk = 0xff0000

	// EXTI_VERR: EXTI IP version register
	// Position of MINREV field.
	EXTI_EXTI_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	EXTI_EXTI_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	EXTI_EXTI_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	EXTI_EXTI_VERR_MAJREV_Msk = 0xf0

	// EXTI_IPIDR: EXTI identification register
	// Position of IPID field.
	EXTI_EXTI_IPIDR_IPID_Pos = 0x0
	// Bit mask of IPID field.
	EXTI_EXTI_IPIDR_IPID_Msk = 0xffffffff

	// EXTI_SIDR: EXTI size ID register
	// Position of SID field.
	EXTI_EXTI_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	EXTI_EXTI_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for FDCAN1: FDCAN1
const (
	// FDCAN_CREL: FDCAN core release register
	// Position of DAY field.
	FDCAN1_FDCAN_CREL_DAY_Pos = 0x0
	// Bit mask of DAY field.
	FDCAN1_FDCAN_CREL_DAY_Msk = 0xff
	// Position of MON field.
	FDCAN1_FDCAN_CREL_MON_Pos = 0x8
	// Bit mask of MON field.
	FDCAN1_FDCAN_CREL_MON_Msk = 0xff00
	// Position of YEAR field.
	FDCAN1_FDCAN_CREL_YEAR_Pos = 0x10
	// Bit mask of YEAR field.
	FDCAN1_FDCAN_CREL_YEAR_Msk = 0xf0000
	// Position of SUBSTEP field.
	FDCAN1_FDCAN_CREL_SUBSTEP_Pos = 0x14
	// Bit mask of SUBSTEP field.
	FDCAN1_FDCAN_CREL_SUBSTEP_Msk = 0xf00000
	// Position of STEP field.
	FDCAN1_FDCAN_CREL_STEP_Pos = 0x18
	// Bit mask of STEP field.
	FDCAN1_FDCAN_CREL_STEP_Msk = 0xf000000
	// Position of REL field.
	FDCAN1_FDCAN_CREL_REL_Pos = 0x1c
	// Bit mask of REL field.
	FDCAN1_FDCAN_CREL_REL_Msk = 0xf0000000

	// FDCAN_ENDN: FDCAN Endian register
	// Position of ETV field.
	FDCAN1_FDCAN_ENDN_ETV_Pos = 0x0
	// Bit mask of ETV field.
	FDCAN1_FDCAN_ENDN_ETV_Msk = 0xffffffff

	// FDCAN_DBTP: This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
	// Position of DSJW field.
	FDCAN1_FDCAN_DBTP_DSJW_Pos = 0x0
	// Bit mask of DSJW field.
	FDCAN1_FDCAN_DBTP_DSJW_Msk = 0xf
	// Position of DTSEG2 field.
	FDCAN1_FDCAN_DBTP_DTSEG2_Pos = 0x4
	// Bit mask of DTSEG2 field.
	FDCAN1_FDCAN_DBTP_DTSEG2_Msk = 0xf0
	// Position of DTSEG1 field.
	FDCAN1_FDCAN_DBTP_DTSEG1_Pos = 0x8
	// Bit mask of DTSEG1 field.
	FDCAN1_FDCAN_DBTP_DTSEG1_Msk = 0x1f00
	// Position of DBRP field.
	FDCAN1_FDCAN_DBTP_DBRP_Pos = 0x10
	// Bit mask of DBRP field.
	FDCAN1_FDCAN_DBTP_DBRP_Msk = 0x1f0000
	// Position of TDC field.
	FDCAN1_FDCAN_DBTP_TDC_Pos = 0x17
	// Bit mask of TDC field.
	FDCAN1_FDCAN_DBTP_TDC_Msk = 0x800000
	// Bit TDC.
	FDCAN1_FDCAN_DBTP_TDC = 0x800000

	// FDCAN_TEST: Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
	// Position of LBCK field.
	FDCAN1_FDCAN_TEST_LBCK_Pos = 0x4
	// Bit mask of LBCK field.
	FDCAN1_FDCAN_TEST_LBCK_Msk = 0x10
	// Bit LBCK.
	FDCAN1_FDCAN_TEST_LBCK = 0x10
	// Position of TX field.
	FDCAN1_FDCAN_TEST_TX_Pos = 0x5
	// Bit mask of TX field.
	FDCAN1_FDCAN_TEST_TX_Msk = 0x60
	// Position of RX field.
	FDCAN1_FDCAN_TEST_RX_Pos = 0x7
	// Bit mask of RX field.
	FDCAN1_FDCAN_TEST_RX_Msk = 0x80
	// Bit RX.
	FDCAN1_FDCAN_TEST_RX = 0x80

	// FDCAN_RWD: The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock.
	// Position of WDC field.
	FDCAN1_FDCAN_RWD_WDC_Pos = 0x0
	// Bit mask of WDC field.
	FDCAN1_FDCAN_RWD_WDC_Msk = 0xff
	// Position of WDV field.
	FDCAN1_FDCAN_RWD_WDV_Pos = 0x8
	// Bit mask of WDV field.
	FDCAN1_FDCAN_RWD_WDV_Msk = 0xff00

	// FDCAN_CCCR: For details about setting and resetting of single bits see Software initialization.
	// Position of INIT field.
	FDCAN1_FDCAN_CCCR_INIT_Pos = 0x0
	// Bit mask of INIT field.
	FDCAN1_FDCAN_CCCR_INIT_Msk = 0x1
	// Bit INIT.
	FDCAN1_FDCAN_CCCR_INIT = 0x1
	// Position of CCE field.
	FDCAN1_FDCAN_CCCR_CCE_Pos = 0x1
	// Bit mask of CCE field.
	FDCAN1_FDCAN_CCCR_CCE_Msk = 0x2
	// Bit CCE.
	FDCAN1_FDCAN_CCCR_CCE = 0x2
	// Position of ASM field.
	FDCAN1_FDCAN_CCCR_ASM_Pos = 0x2
	// Bit mask of ASM field.
	FDCAN1_FDCAN_CCCR_ASM_Msk = 0x4
	// Bit ASM.
	FDCAN1_FDCAN_CCCR_ASM = 0x4
	// Position of CSA field.
	FDCAN1_FDCAN_CCCR_CSA_Pos = 0x3
	// Bit mask of CSA field.
	FDCAN1_FDCAN_CCCR_CSA_Msk = 0x8
	// Bit CSA.
	FDCAN1_FDCAN_CCCR_CSA = 0x8
	// Position of CSR field.
	FDCAN1_FDCAN_CCCR_CSR_Pos = 0x4
	// Bit mask of CSR field.
	FDCAN1_FDCAN_CCCR_CSR_Msk = 0x10
	// Bit CSR.
	FDCAN1_FDCAN_CCCR_CSR = 0x10
	// Position of MON field.
	FDCAN1_FDCAN_CCCR_MON_Pos = 0x5
	// Bit mask of MON field.
	FDCAN1_FDCAN_CCCR_MON_Msk = 0x20
	// Bit MON.
	FDCAN1_FDCAN_CCCR_MON = 0x20
	// Position of DAR field.
	FDCAN1_FDCAN_CCCR_DAR_Pos = 0x6
	// Bit mask of DAR field.
	FDCAN1_FDCAN_CCCR_DAR_Msk = 0x40
	// Bit DAR.
	FDCAN1_FDCAN_CCCR_DAR = 0x40
	// Position of TEST field.
	FDCAN1_FDCAN_CCCR_TEST_Pos = 0x7
	// Bit mask of TEST field.
	FDCAN1_FDCAN_CCCR_TEST_Msk = 0x80
	// Bit TEST.
	FDCAN1_FDCAN_CCCR_TEST = 0x80
	// Position of FDOE field.
	FDCAN1_FDCAN_CCCR_FDOE_Pos = 0x8
	// Bit mask of FDOE field.
	FDCAN1_FDCAN_CCCR_FDOE_Msk = 0x100
	// Bit FDOE.
	FDCAN1_FDCAN_CCCR_FDOE = 0x100
	// Position of BRSE field.
	FDCAN1_FDCAN_CCCR_BRSE_Pos = 0x9
	// Bit mask of BRSE field.
	FDCAN1_FDCAN_CCCR_BRSE_Msk = 0x200
	// Bit BRSE.
	FDCAN1_FDCAN_CCCR_BRSE = 0x200
	// Position of PXHD field.
	FDCAN1_FDCAN_CCCR_PXHD_Pos = 0xc
	// Bit mask of PXHD field.
	FDCAN1_FDCAN_CCCR_PXHD_Msk = 0x1000
	// Bit PXHD.
	FDCAN1_FDCAN_CCCR_PXHD = 0x1000
	// Position of EFBI field.
	FDCAN1_FDCAN_CCCR_EFBI_Pos = 0xd
	// Bit mask of EFBI field.
	FDCAN1_FDCAN_CCCR_EFBI_Msk = 0x2000
	// Bit EFBI.
	FDCAN1_FDCAN_CCCR_EFBI = 0x2000
	// Position of TXP field.
	FDCAN1_FDCAN_CCCR_TXP_Pos = 0xe
	// Bit mask of TXP field.
	FDCAN1_FDCAN_CCCR_TXP_Msk = 0x4000
	// Bit TXP.
	FDCAN1_FDCAN_CCCR_TXP = 0x4000
	// Position of NISO field.
	FDCAN1_FDCAN_CCCR_NISO_Pos = 0xf
	// Bit mask of NISO field.
	FDCAN1_FDCAN_CCCR_NISO_Msk = 0x8000
	// Bit NISO.
	FDCAN1_FDCAN_CCCR_NISO = 0x8000

	// FDCAN_NBTP: This register is dedicated to the nominal bit timing used during the arbitration phase.
	// Position of NTSEG2 field.
	FDCAN1_FDCAN_NBTP_NTSEG2_Pos = 0x0
	// Bit mask of NTSEG2 field.
	FDCAN1_FDCAN_NBTP_NTSEG2_Msk = 0x7f
	// Position of NTSEG1 field.
	FDCAN1_FDCAN_NBTP_NTSEG1_Pos = 0x8
	// Bit mask of NTSEG1 field.
	FDCAN1_FDCAN_NBTP_NTSEG1_Msk = 0xff00
	// Position of NBRP field.
	FDCAN1_FDCAN_NBTP_NBRP_Pos = 0x10
	// Bit mask of NBRP field.
	FDCAN1_FDCAN_NBTP_NBRP_Msk = 0x1ff0000
	// Position of NSJW field.
	FDCAN1_FDCAN_NBTP_NSJW_Pos = 0x19
	// Bit mask of NSJW field.
	FDCAN1_FDCAN_NBTP_NSJW_Msk = 0xfe000000

	// FDCAN_TSCC: FDCAN timestamp counter configuration register
	// Position of TSS field.
	FDCAN1_FDCAN_TSCC_TSS_Pos = 0x0
	// Bit mask of TSS field.
	FDCAN1_FDCAN_TSCC_TSS_Msk = 0x3
	// Position of TCP field.
	FDCAN1_FDCAN_TSCC_TCP_Pos = 0x10
	// Bit mask of TCP field.
	FDCAN1_FDCAN_TSCC_TCP_Msk = 0xf0000

	// FDCAN_TSCV: FDCAN timestamp counter value register
	// Position of TSC field.
	FDCAN1_FDCAN_TSCV_TSC_Pos = 0x0
	// Bit mask of TSC field.
	FDCAN1_FDCAN_TSCV_TSC_Msk = 0xffff

	// FDCAN_TOCC: FDCAN timeout counter configuration register
	// Position of ETOC field.
	FDCAN1_FDCAN_TOCC_ETOC_Pos = 0x0
	// Bit mask of ETOC field.
	FDCAN1_FDCAN_TOCC_ETOC_Msk = 0x1
	// Bit ETOC.
	FDCAN1_FDCAN_TOCC_ETOC = 0x1
	// Position of TOS field.
	FDCAN1_FDCAN_TOCC_TOS_Pos = 0x1
	// Bit mask of TOS field.
	FDCAN1_FDCAN_TOCC_TOS_Msk = 0x6
	// Position of TOP field.
	FDCAN1_FDCAN_TOCC_TOP_Pos = 0x10
	// Bit mask of TOP field.
	FDCAN1_FDCAN_TOCC_TOP_Msk = 0xffff0000

	// FDCAN_TOCV: FDCAN timeout counter value register
	// Position of TOC field.
	FDCAN1_FDCAN_TOCV_TOC_Pos = 0x0
	// Bit mask of TOC field.
	FDCAN1_FDCAN_TOCV_TOC_Msk = 0xffff

	// FDCAN_ECR: FDCAN error counter register
	// Position of TEC field.
	FDCAN1_FDCAN_ECR_TEC_Pos = 0x0
	// Bit mask of TEC field.
	FDCAN1_FDCAN_ECR_TEC_Msk = 0xff
	// Position of TREC field.
	FDCAN1_FDCAN_ECR_TREC_Pos = 0x8
	// Bit mask of TREC field.
	FDCAN1_FDCAN_ECR_TREC_Msk = 0x7f00
	// Position of RP field.
	FDCAN1_FDCAN_ECR_RP_Pos = 0xf
	// Bit mask of RP field.
	FDCAN1_FDCAN_ECR_RP_Msk = 0x8000
	// Bit RP.
	FDCAN1_FDCAN_ECR_RP = 0x8000
	// Position of CEL field.
	FDCAN1_FDCAN_ECR_CEL_Pos = 0x10
	// Bit mask of CEL field.
	FDCAN1_FDCAN_ECR_CEL_Msk = 0xff0000

	// FDCAN_PSR: FDCAN protocol status register
	// Position of LEC field.
	FDCAN1_FDCAN_PSR_LEC_Pos = 0x0
	// Bit mask of LEC field.
	FDCAN1_FDCAN_PSR_LEC_Msk = 0x7
	// Position of ACT field.
	FDCAN1_FDCAN_PSR_ACT_Pos = 0x3
	// Bit mask of ACT field.
	FDCAN1_FDCAN_PSR_ACT_Msk = 0x18
	// Position of EP field.
	FDCAN1_FDCAN_PSR_EP_Pos = 0x5
	// Bit mask of EP field.
	FDCAN1_FDCAN_PSR_EP_Msk = 0x20
	// Bit EP.
	FDCAN1_FDCAN_PSR_EP = 0x20
	// Position of EW field.
	FDCAN1_FDCAN_PSR_EW_Pos = 0x6
	// Bit mask of EW field.
	FDCAN1_FDCAN_PSR_EW_Msk = 0x40
	// Bit EW.
	FDCAN1_FDCAN_PSR_EW = 0x40
	// Position of BO field.
	FDCAN1_FDCAN_PSR_BO_Pos = 0x7
	// Bit mask of BO field.
	FDCAN1_FDCAN_PSR_BO_Msk = 0x80
	// Bit BO.
	FDCAN1_FDCAN_PSR_BO = 0x80
	// Position of DLEC field.
	FDCAN1_FDCAN_PSR_DLEC_Pos = 0x8
	// Bit mask of DLEC field.
	FDCAN1_FDCAN_PSR_DLEC_Msk = 0x700
	// Position of RESI field.
	FDCAN1_FDCAN_PSR_RESI_Pos = 0xb
	// Bit mask of RESI field.
	FDCAN1_FDCAN_PSR_RESI_Msk = 0x800
	// Bit RESI.
	FDCAN1_FDCAN_PSR_RESI = 0x800
	// Position of RBRS field.
	FDCAN1_FDCAN_PSR_RBRS_Pos = 0xc
	// Bit mask of RBRS field.
	FDCAN1_FDCAN_PSR_RBRS_Msk = 0x1000
	// Bit RBRS.
	FDCAN1_FDCAN_PSR_RBRS = 0x1000
	// Position of REDL field.
	FDCAN1_FDCAN_PSR_REDL_Pos = 0xd
	// Bit mask of REDL field.
	FDCAN1_FDCAN_PSR_REDL_Msk = 0x2000
	// Bit REDL.
	FDCAN1_FDCAN_PSR_REDL = 0x2000
	// Position of PXE field.
	FDCAN1_FDCAN_PSR_PXE_Pos = 0xe
	// Bit mask of PXE field.
	FDCAN1_FDCAN_PSR_PXE_Msk = 0x4000
	// Bit PXE.
	FDCAN1_FDCAN_PSR_PXE = 0x4000
	// Position of TDCV field.
	FDCAN1_FDCAN_PSR_TDCV_Pos = 0x10
	// Bit mask of TDCV field.
	FDCAN1_FDCAN_PSR_TDCV_Msk = 0x7f0000

	// FDCAN_TDCR: FDCAN transmitter delay compensation register
	// Position of TDCF field.
	FDCAN1_FDCAN_TDCR_TDCF_Pos = 0x0
	// Bit mask of TDCF field.
	FDCAN1_FDCAN_TDCR_TDCF_Msk = 0x7f
	// Position of TDCO field.
	FDCAN1_FDCAN_TDCR_TDCO_Pos = 0x8
	// Bit mask of TDCO field.
	FDCAN1_FDCAN_TDCR_TDCO_Msk = 0x7f00

	// FDCAN_IR: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
	// Position of RF0N field.
	FDCAN1_FDCAN_IR_RF0N_Pos = 0x0
	// Bit mask of RF0N field.
	FDCAN1_FDCAN_IR_RF0N_Msk = 0x1
	// Bit RF0N.
	FDCAN1_FDCAN_IR_RF0N = 0x1
	// Position of RF0W field.
	FDCAN1_FDCAN_IR_RF0W_Pos = 0x1
	// Bit mask of RF0W field.
	FDCAN1_FDCAN_IR_RF0W_Msk = 0x2
	// Bit RF0W.
	FDCAN1_FDCAN_IR_RF0W = 0x2
	// Position of RF0F field.
	FDCAN1_FDCAN_IR_RF0F_Pos = 0x2
	// Bit mask of RF0F field.
	FDCAN1_FDCAN_IR_RF0F_Msk = 0x4
	// Bit RF0F.
	FDCAN1_FDCAN_IR_RF0F = 0x4
	// Position of RF0L field.
	FDCAN1_FDCAN_IR_RF0L_Pos = 0x3
	// Bit mask of RF0L field.
	FDCAN1_FDCAN_IR_RF0L_Msk = 0x8
	// Bit RF0L.
	FDCAN1_FDCAN_IR_RF0L = 0x8
	// Position of RF1N field.
	FDCAN1_FDCAN_IR_RF1N_Pos = 0x4
	// Bit mask of RF1N field.
	FDCAN1_FDCAN_IR_RF1N_Msk = 0x10
	// Bit RF1N.
	FDCAN1_FDCAN_IR_RF1N = 0x10
	// Position of RF1W field.
	FDCAN1_FDCAN_IR_RF1W_Pos = 0x5
	// Bit mask of RF1W field.
	FDCAN1_FDCAN_IR_RF1W_Msk = 0x20
	// Bit RF1W.
	FDCAN1_FDCAN_IR_RF1W = 0x20
	// Position of RF1F field.
	FDCAN1_FDCAN_IR_RF1F_Pos = 0x6
	// Bit mask of RF1F field.
	FDCAN1_FDCAN_IR_RF1F_Msk = 0x40
	// Bit RF1F.
	FDCAN1_FDCAN_IR_RF1F = 0x40
	// Position of RF1L field.
	FDCAN1_FDCAN_IR_RF1L_Pos = 0x7
	// Bit mask of RF1L field.
	FDCAN1_FDCAN_IR_RF1L_Msk = 0x80
	// Bit RF1L.
	FDCAN1_FDCAN_IR_RF1L = 0x80
	// Position of HPM field.
	FDCAN1_FDCAN_IR_HPM_Pos = 0x8
	// Bit mask of HPM field.
	FDCAN1_FDCAN_IR_HPM_Msk = 0x100
	// Bit HPM.
	FDCAN1_FDCAN_IR_HPM = 0x100
	// Position of TC field.
	FDCAN1_FDCAN_IR_TC_Pos = 0x9
	// Bit mask of TC field.
	FDCAN1_FDCAN_IR_TC_Msk = 0x200
	// Bit TC.
	FDCAN1_FDCAN_IR_TC = 0x200
	// Position of TCF field.
	FDCAN1_FDCAN_IR_TCF_Pos = 0xa
	// Bit mask of TCF field.
	FDCAN1_FDCAN_IR_TCF_Msk = 0x400
	// Bit TCF.
	FDCAN1_FDCAN_IR_TCF = 0x400
	// Position of TFE field.
	FDCAN1_FDCAN_IR_TFE_Pos = 0xb
	// Bit mask of TFE field.
	FDCAN1_FDCAN_IR_TFE_Msk = 0x800
	// Bit TFE.
	FDCAN1_FDCAN_IR_TFE = 0x800
	// Position of TEFN field.
	FDCAN1_FDCAN_IR_TEFN_Pos = 0xc
	// Bit mask of TEFN field.
	FDCAN1_FDCAN_IR_TEFN_Msk = 0x1000
	// Bit TEFN.
	FDCAN1_FDCAN_IR_TEFN = 0x1000
	// Position of TEFW field.
	FDCAN1_FDCAN_IR_TEFW_Pos = 0xd
	// Bit mask of TEFW field.
	FDCAN1_FDCAN_IR_TEFW_Msk = 0x2000
	// Bit TEFW.
	FDCAN1_FDCAN_IR_TEFW = 0x2000
	// Position of TEFF field.
	FDCAN1_FDCAN_IR_TEFF_Pos = 0xe
	// Bit mask of TEFF field.
	FDCAN1_FDCAN_IR_TEFF_Msk = 0x4000
	// Bit TEFF.
	FDCAN1_FDCAN_IR_TEFF = 0x4000
	// Position of TEFL field.
	FDCAN1_FDCAN_IR_TEFL_Pos = 0xf
	// Bit mask of TEFL field.
	FDCAN1_FDCAN_IR_TEFL_Msk = 0x8000
	// Bit TEFL.
	FDCAN1_FDCAN_IR_TEFL = 0x8000
	// Position of TSW field.
	FDCAN1_FDCAN_IR_TSW_Pos = 0x10
	// Bit mask of TSW field.
	FDCAN1_FDCAN_IR_TSW_Msk = 0x10000
	// Bit TSW.
	FDCAN1_FDCAN_IR_TSW = 0x10000
	// Position of MRAF field.
	FDCAN1_FDCAN_IR_MRAF_Pos = 0x11
	// Bit mask of MRAF field.
	FDCAN1_FDCAN_IR_MRAF_Msk = 0x20000
	// Bit MRAF.
	FDCAN1_FDCAN_IR_MRAF = 0x20000
	// Position of TOO field.
	FDCAN1_FDCAN_IR_TOO_Pos = 0x12
	// Bit mask of TOO field.
	FDCAN1_FDCAN_IR_TOO_Msk = 0x40000
	// Bit TOO.
	FDCAN1_FDCAN_IR_TOO = 0x40000
	// Position of DRX field.
	FDCAN1_FDCAN_IR_DRX_Pos = 0x13
	// Bit mask of DRX field.
	FDCAN1_FDCAN_IR_DRX_Msk = 0x80000
	// Bit DRX.
	FDCAN1_FDCAN_IR_DRX = 0x80000
	// Position of ELO field.
	FDCAN1_FDCAN_IR_ELO_Pos = 0x16
	// Bit mask of ELO field.
	FDCAN1_FDCAN_IR_ELO_Msk = 0x400000
	// Bit ELO.
	FDCAN1_FDCAN_IR_ELO = 0x400000
	// Position of EP field.
	FDCAN1_FDCAN_IR_EP_Pos = 0x17
	// Bit mask of EP field.
	FDCAN1_FDCAN_IR_EP_Msk = 0x800000
	// Bit EP.
	FDCAN1_FDCAN_IR_EP = 0x800000
	// Position of EW field.
	FDCAN1_FDCAN_IR_EW_Pos = 0x18
	// Bit mask of EW field.
	FDCAN1_FDCAN_IR_EW_Msk = 0x1000000
	// Bit EW.
	FDCAN1_FDCAN_IR_EW = 0x1000000
	// Position of BO field.
	FDCAN1_FDCAN_IR_BO_Pos = 0x19
	// Bit mask of BO field.
	FDCAN1_FDCAN_IR_BO_Msk = 0x2000000
	// Bit BO.
	FDCAN1_FDCAN_IR_BO = 0x2000000
	// Position of WDI field.
	FDCAN1_FDCAN_IR_WDI_Pos = 0x1a
	// Bit mask of WDI field.
	FDCAN1_FDCAN_IR_WDI_Msk = 0x4000000
	// Bit WDI.
	FDCAN1_FDCAN_IR_WDI = 0x4000000
	// Position of PEA field.
	FDCAN1_FDCAN_IR_PEA_Pos = 0x1b
	// Bit mask of PEA field.
	FDCAN1_FDCAN_IR_PEA_Msk = 0x8000000
	// Bit PEA.
	FDCAN1_FDCAN_IR_PEA = 0x8000000
	// Position of PED field.
	FDCAN1_FDCAN_IR_PED_Pos = 0x1c
	// Bit mask of PED field.
	FDCAN1_FDCAN_IR_PED_Msk = 0x10000000
	// Bit PED.
	FDCAN1_FDCAN_IR_PED = 0x10000000
	// Position of ARA field.
	FDCAN1_FDCAN_IR_ARA_Pos = 0x1d
	// Bit mask of ARA field.
	FDCAN1_FDCAN_IR_ARA_Msk = 0x20000000
	// Bit ARA.
	FDCAN1_FDCAN_IR_ARA = 0x20000000

	// FDCAN_IE: The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line.
	// Position of RF0NE field.
	FDCAN1_FDCAN_IE_RF0NE_Pos = 0x0
	// Bit mask of RF0NE field.
	FDCAN1_FDCAN_IE_RF0NE_Msk = 0x1
	// Bit RF0NE.
	FDCAN1_FDCAN_IE_RF0NE = 0x1
	// Position of RF0WE field.
	FDCAN1_FDCAN_IE_RF0WE_Pos = 0x1
	// Bit mask of RF0WE field.
	FDCAN1_FDCAN_IE_RF0WE_Msk = 0x2
	// Bit RF0WE.
	FDCAN1_FDCAN_IE_RF0WE = 0x2
	// Position of RF0FE field.
	FDCAN1_FDCAN_IE_RF0FE_Pos = 0x2
	// Bit mask of RF0FE field.
	FDCAN1_FDCAN_IE_RF0FE_Msk = 0x4
	// Bit RF0FE.
	FDCAN1_FDCAN_IE_RF0FE = 0x4
	// Position of RF0LE field.
	FDCAN1_FDCAN_IE_RF0LE_Pos = 0x3
	// Bit mask of RF0LE field.
	FDCAN1_FDCAN_IE_RF0LE_Msk = 0x8
	// Bit RF0LE.
	FDCAN1_FDCAN_IE_RF0LE = 0x8
	// Position of RF1NE field.
	FDCAN1_FDCAN_IE_RF1NE_Pos = 0x4
	// Bit mask of RF1NE field.
	FDCAN1_FDCAN_IE_RF1NE_Msk = 0x10
	// Bit RF1NE.
	FDCAN1_FDCAN_IE_RF1NE = 0x10
	// Position of RF1WE field.
	FDCAN1_FDCAN_IE_RF1WE_Pos = 0x5
	// Bit mask of RF1WE field.
	FDCAN1_FDCAN_IE_RF1WE_Msk = 0x20
	// Bit RF1WE.
	FDCAN1_FDCAN_IE_RF1WE = 0x20
	// Position of RF1FE field.
	FDCAN1_FDCAN_IE_RF1FE_Pos = 0x6
	// Bit mask of RF1FE field.
	FDCAN1_FDCAN_IE_RF1FE_Msk = 0x40
	// Bit RF1FE.
	FDCAN1_FDCAN_IE_RF1FE = 0x40
	// Position of RF1LE field.
	FDCAN1_FDCAN_IE_RF1LE_Pos = 0x7
	// Bit mask of RF1LE field.
	FDCAN1_FDCAN_IE_RF1LE_Msk = 0x80
	// Bit RF1LE.
	FDCAN1_FDCAN_IE_RF1LE = 0x80
	// Position of HPME field.
	FDCAN1_FDCAN_IE_HPME_Pos = 0x8
	// Bit mask of HPME field.
	FDCAN1_FDCAN_IE_HPME_Msk = 0x100
	// Bit HPME.
	FDCAN1_FDCAN_IE_HPME = 0x100
	// Position of TCE field.
	FDCAN1_FDCAN_IE_TCE_Pos = 0x9
	// Bit mask of TCE field.
	FDCAN1_FDCAN_IE_TCE_Msk = 0x200
	// Bit TCE.
	FDCAN1_FDCAN_IE_TCE = 0x200
	// Position of TCFE field.
	FDCAN1_FDCAN_IE_TCFE_Pos = 0xa
	// Bit mask of TCFE field.
	FDCAN1_FDCAN_IE_TCFE_Msk = 0x400
	// Bit TCFE.
	FDCAN1_FDCAN_IE_TCFE = 0x400
	// Position of TFEE field.
	FDCAN1_FDCAN_IE_TFEE_Pos = 0xb
	// Bit mask of TFEE field.
	FDCAN1_FDCAN_IE_TFEE_Msk = 0x800
	// Bit TFEE.
	FDCAN1_FDCAN_IE_TFEE = 0x800
	// Position of TEFNE field.
	FDCAN1_FDCAN_IE_TEFNE_Pos = 0xc
	// Bit mask of TEFNE field.
	FDCAN1_FDCAN_IE_TEFNE_Msk = 0x1000
	// Bit TEFNE.
	FDCAN1_FDCAN_IE_TEFNE = 0x1000
	// Position of TEFWE field.
	FDCAN1_FDCAN_IE_TEFWE_Pos = 0xd
	// Bit mask of TEFWE field.
	FDCAN1_FDCAN_IE_TEFWE_Msk = 0x2000
	// Bit TEFWE.
	FDCAN1_FDCAN_IE_TEFWE = 0x2000
	// Position of TEFFE field.
	FDCAN1_FDCAN_IE_TEFFE_Pos = 0xe
	// Bit mask of TEFFE field.
	FDCAN1_FDCAN_IE_TEFFE_Msk = 0x4000
	// Bit TEFFE.
	FDCAN1_FDCAN_IE_TEFFE = 0x4000
	// Position of TEFLE field.
	FDCAN1_FDCAN_IE_TEFLE_Pos = 0xf
	// Bit mask of TEFLE field.
	FDCAN1_FDCAN_IE_TEFLE_Msk = 0x8000
	// Bit TEFLE.
	FDCAN1_FDCAN_IE_TEFLE = 0x8000
	// Position of TSWE field.
	FDCAN1_FDCAN_IE_TSWE_Pos = 0x10
	// Bit mask of TSWE field.
	FDCAN1_FDCAN_IE_TSWE_Msk = 0x10000
	// Bit TSWE.
	FDCAN1_FDCAN_IE_TSWE = 0x10000
	// Position of MRAFE field.
	FDCAN1_FDCAN_IE_MRAFE_Pos = 0x11
	// Bit mask of MRAFE field.
	FDCAN1_FDCAN_IE_MRAFE_Msk = 0x20000
	// Bit MRAFE.
	FDCAN1_FDCAN_IE_MRAFE = 0x20000
	// Position of TOOE field.
	FDCAN1_FDCAN_IE_TOOE_Pos = 0x12
	// Bit mask of TOOE field.
	FDCAN1_FDCAN_IE_TOOE_Msk = 0x40000
	// Bit TOOE.
	FDCAN1_FDCAN_IE_TOOE = 0x40000
	// Position of DRXE field.
	FDCAN1_FDCAN_IE_DRXE_Pos = 0x13
	// Bit mask of DRXE field.
	FDCAN1_FDCAN_IE_DRXE_Msk = 0x80000
	// Bit DRXE.
	FDCAN1_FDCAN_IE_DRXE = 0x80000
	// Position of BECE field.
	FDCAN1_FDCAN_IE_BECE_Pos = 0x14
	// Bit mask of BECE field.
	FDCAN1_FDCAN_IE_BECE_Msk = 0x100000
	// Bit BECE.
	FDCAN1_FDCAN_IE_BECE = 0x100000
	// Position of BEUE field.
	FDCAN1_FDCAN_IE_BEUE_Pos = 0x15
	// Bit mask of BEUE field.
	FDCAN1_FDCAN_IE_BEUE_Msk = 0x200000
	// Bit BEUE.
	FDCAN1_FDCAN_IE_BEUE = 0x200000
	// Position of ELOE field.
	FDCAN1_FDCAN_IE_ELOE_Pos = 0x16
	// Bit mask of ELOE field.
	FDCAN1_FDCAN_IE_ELOE_Msk = 0x400000
	// Bit ELOE.
	FDCAN1_FDCAN_IE_ELOE = 0x400000
	// Position of EPE field.
	FDCAN1_FDCAN_IE_EPE_Pos = 0x17
	// Bit mask of EPE field.
	FDCAN1_FDCAN_IE_EPE_Msk = 0x800000
	// Bit EPE.
	FDCAN1_FDCAN_IE_EPE = 0x800000
	// Position of EWE field.
	FDCAN1_FDCAN_IE_EWE_Pos = 0x18
	// Bit mask of EWE field.
	FDCAN1_FDCAN_IE_EWE_Msk = 0x1000000
	// Bit EWE.
	FDCAN1_FDCAN_IE_EWE = 0x1000000
	// Position of BOE field.
	FDCAN1_FDCAN_IE_BOE_Pos = 0x19
	// Bit mask of BOE field.
	FDCAN1_FDCAN_IE_BOE_Msk = 0x2000000
	// Bit BOE.
	FDCAN1_FDCAN_IE_BOE = 0x2000000
	// Position of WDIE field.
	FDCAN1_FDCAN_IE_WDIE_Pos = 0x1a
	// Bit mask of WDIE field.
	FDCAN1_FDCAN_IE_WDIE_Msk = 0x4000000
	// Bit WDIE.
	FDCAN1_FDCAN_IE_WDIE = 0x4000000
	// Position of PEAE field.
	FDCAN1_FDCAN_IE_PEAE_Pos = 0x1b
	// Bit mask of PEAE field.
	FDCAN1_FDCAN_IE_PEAE_Msk = 0x8000000
	// Bit PEAE.
	FDCAN1_FDCAN_IE_PEAE = 0x8000000
	// Position of PEDE field.
	FDCAN1_FDCAN_IE_PEDE_Pos = 0x1c
	// Bit mask of PEDE field.
	FDCAN1_FDCAN_IE_PEDE_Msk = 0x10000000
	// Bit PEDE.
	FDCAN1_FDCAN_IE_PEDE = 0x10000000
	// Position of ARAE field.
	FDCAN1_FDCAN_IE_ARAE_Pos = 0x1d
	// Bit mask of ARAE field.
	FDCAN1_FDCAN_IE_ARAE_Msk = 0x20000000
	// Bit ARAE.
	FDCAN1_FDCAN_IE_ARAE = 0x20000000

	// FDCAN_ILS: This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.
	// Position of RF0NL field.
	FDCAN1_FDCAN_ILS_RF0NL_Pos = 0x0
	// Bit mask of RF0NL field.
	FDCAN1_FDCAN_ILS_RF0NL_Msk = 0x1
	// Bit RF0NL.
	FDCAN1_FDCAN_ILS_RF0NL = 0x1
	// Position of RF0WL field.
	FDCAN1_FDCAN_ILS_RF0WL_Pos = 0x1
	// Bit mask of RF0WL field.
	FDCAN1_FDCAN_ILS_RF0WL_Msk = 0x2
	// Bit RF0WL.
	FDCAN1_FDCAN_ILS_RF0WL = 0x2
	// Position of RF0FL field.
	FDCAN1_FDCAN_ILS_RF0FL_Pos = 0x2
	// Bit mask of RF0FL field.
	FDCAN1_FDCAN_ILS_RF0FL_Msk = 0x4
	// Bit RF0FL.
	FDCAN1_FDCAN_ILS_RF0FL = 0x4
	// Position of RF0LL field.
	FDCAN1_FDCAN_ILS_RF0LL_Pos = 0x3
	// Bit mask of RF0LL field.
	FDCAN1_FDCAN_ILS_RF0LL_Msk = 0x8
	// Bit RF0LL.
	FDCAN1_FDCAN_ILS_RF0LL = 0x8
	// Position of RF1NL field.
	FDCAN1_FDCAN_ILS_RF1NL_Pos = 0x4
	// Bit mask of RF1NL field.
	FDCAN1_FDCAN_ILS_RF1NL_Msk = 0x10
	// Bit RF1NL.
	FDCAN1_FDCAN_ILS_RF1NL = 0x10
	// Position of RF1WL field.
	FDCAN1_FDCAN_ILS_RF1WL_Pos = 0x5
	// Bit mask of RF1WL field.
	FDCAN1_FDCAN_ILS_RF1WL_Msk = 0x20
	// Bit RF1WL.
	FDCAN1_FDCAN_ILS_RF1WL = 0x20
	// Position of RF1FL field.
	FDCAN1_FDCAN_ILS_RF1FL_Pos = 0x6
	// Bit mask of RF1FL field.
	FDCAN1_FDCAN_ILS_RF1FL_Msk = 0x40
	// Bit RF1FL.
	FDCAN1_FDCAN_ILS_RF1FL = 0x40
	// Position of RF1LL field.
	FDCAN1_FDCAN_ILS_RF1LL_Pos = 0x7
	// Bit mask of RF1LL field.
	FDCAN1_FDCAN_ILS_RF1LL_Msk = 0x80
	// Bit RF1LL.
	FDCAN1_FDCAN_ILS_RF1LL = 0x80
	// Position of HPML field.
	FDCAN1_FDCAN_ILS_HPML_Pos = 0x8
	// Bit mask of HPML field.
	FDCAN1_FDCAN_ILS_HPML_Msk = 0x100
	// Bit HPML.
	FDCAN1_FDCAN_ILS_HPML = 0x100
	// Position of TCL field.
	FDCAN1_FDCAN_ILS_TCL_Pos = 0x9
	// Bit mask of TCL field.
	FDCAN1_FDCAN_ILS_TCL_Msk = 0x200
	// Bit TCL.
	FDCAN1_FDCAN_ILS_TCL = 0x200
	// Position of TCFL field.
	FDCAN1_FDCAN_ILS_TCFL_Pos = 0xa
	// Bit mask of TCFL field.
	FDCAN1_FDCAN_ILS_TCFL_Msk = 0x400
	// Bit TCFL.
	FDCAN1_FDCAN_ILS_TCFL = 0x400
	// Position of TFEL field.
	FDCAN1_FDCAN_ILS_TFEL_Pos = 0xb
	// Bit mask of TFEL field.
	FDCAN1_FDCAN_ILS_TFEL_Msk = 0x800
	// Bit TFEL.
	FDCAN1_FDCAN_ILS_TFEL = 0x800
	// Position of TEFNL field.
	FDCAN1_FDCAN_ILS_TEFNL_Pos = 0xc
	// Bit mask of TEFNL field.
	FDCAN1_FDCAN_ILS_TEFNL_Msk = 0x1000
	// Bit TEFNL.
	FDCAN1_FDCAN_ILS_TEFNL = 0x1000
	// Position of TEFWL field.
	FDCAN1_FDCAN_ILS_TEFWL_Pos = 0xd
	// Bit mask of TEFWL field.
	FDCAN1_FDCAN_ILS_TEFWL_Msk = 0x2000
	// Bit TEFWL.
	FDCAN1_FDCAN_ILS_TEFWL = 0x2000
	// Position of TEFFL field.
	FDCAN1_FDCAN_ILS_TEFFL_Pos = 0xe
	// Bit mask of TEFFL field.
	FDCAN1_FDCAN_ILS_TEFFL_Msk = 0x4000
	// Bit TEFFL.
	FDCAN1_FDCAN_ILS_TEFFL = 0x4000
	// Position of TEFLL field.
	FDCAN1_FDCAN_ILS_TEFLL_Pos = 0xf
	// Bit mask of TEFLL field.
	FDCAN1_FDCAN_ILS_TEFLL_Msk = 0x8000
	// Bit TEFLL.
	FDCAN1_FDCAN_ILS_TEFLL = 0x8000
	// Position of TSWL field.
	FDCAN1_FDCAN_ILS_TSWL_Pos = 0x10
	// Bit mask of TSWL field.
	FDCAN1_FDCAN_ILS_TSWL_Msk = 0x10000
	// Bit TSWL.
	FDCAN1_FDCAN_ILS_TSWL = 0x10000
	// Position of MRAFL field.
	FDCAN1_FDCAN_ILS_MRAFL_Pos = 0x11
	// Bit mask of MRAFL field.
	FDCAN1_FDCAN_ILS_MRAFL_Msk = 0x20000
	// Bit MRAFL.
	FDCAN1_FDCAN_ILS_MRAFL = 0x20000
	// Position of TOOL field.
	FDCAN1_FDCAN_ILS_TOOL_Pos = 0x12
	// Bit mask of TOOL field.
	FDCAN1_FDCAN_ILS_TOOL_Msk = 0x40000
	// Bit TOOL.
	FDCAN1_FDCAN_ILS_TOOL = 0x40000
	// Position of DRXL field.
	FDCAN1_FDCAN_ILS_DRXL_Pos = 0x13
	// Bit mask of DRXL field.
	FDCAN1_FDCAN_ILS_DRXL_Msk = 0x80000
	// Bit DRXL.
	FDCAN1_FDCAN_ILS_DRXL = 0x80000
	// Position of BECL field.
	FDCAN1_FDCAN_ILS_BECL_Pos = 0x14
	// Bit mask of BECL field.
	FDCAN1_FDCAN_ILS_BECL_Msk = 0x100000
	// Bit BECL.
	FDCAN1_FDCAN_ILS_BECL = 0x100000
	// Position of BEUL field.
	FDCAN1_FDCAN_ILS_BEUL_Pos = 0x15
	// Bit mask of BEUL field.
	FDCAN1_FDCAN_ILS_BEUL_Msk = 0x200000
	// Bit BEUL.
	FDCAN1_FDCAN_ILS_BEUL = 0x200000
	// Position of ELOL field.
	FDCAN1_FDCAN_ILS_ELOL_Pos = 0x16
	// Bit mask of ELOL field.
	FDCAN1_FDCAN_ILS_ELOL_Msk = 0x400000
	// Bit ELOL.
	FDCAN1_FDCAN_ILS_ELOL = 0x400000
	// Position of EPL field.
	FDCAN1_FDCAN_ILS_EPL_Pos = 0x17
	// Bit mask of EPL field.
	FDCAN1_FDCAN_ILS_EPL_Msk = 0x800000
	// Bit EPL.
	FDCAN1_FDCAN_ILS_EPL = 0x800000
	// Position of EWL field.
	FDCAN1_FDCAN_ILS_EWL_Pos = 0x18
	// Bit mask of EWL field.
	FDCAN1_FDCAN_ILS_EWL_Msk = 0x1000000
	// Bit EWL.
	FDCAN1_FDCAN_ILS_EWL = 0x1000000
	// Position of BOL field.
	FDCAN1_FDCAN_ILS_BOL_Pos = 0x19
	// Bit mask of BOL field.
	FDCAN1_FDCAN_ILS_BOL_Msk = 0x2000000
	// Bit BOL.
	FDCAN1_FDCAN_ILS_BOL = 0x2000000
	// Position of WDIL field.
	FDCAN1_FDCAN_ILS_WDIL_Pos = 0x1a
	// Bit mask of WDIL field.
	FDCAN1_FDCAN_ILS_WDIL_Msk = 0x4000000
	// Bit WDIL.
	FDCAN1_FDCAN_ILS_WDIL = 0x4000000
	// Position of PEAL field.
	FDCAN1_FDCAN_ILS_PEAL_Pos = 0x1b
	// Bit mask of PEAL field.
	FDCAN1_FDCAN_ILS_PEAL_Msk = 0x8000000
	// Bit PEAL.
	FDCAN1_FDCAN_ILS_PEAL = 0x8000000
	// Position of PEDL field.
	FDCAN1_FDCAN_ILS_PEDL_Pos = 0x1c
	// Bit mask of PEDL field.
	FDCAN1_FDCAN_ILS_PEDL_Msk = 0x10000000
	// Bit PEDL.
	FDCAN1_FDCAN_ILS_PEDL = 0x10000000
	// Position of ARAL field.
	FDCAN1_FDCAN_ILS_ARAL_Pos = 0x1d
	// Bit mask of ARAL field.
	FDCAN1_FDCAN_ILS_ARAL_Msk = 0x20000000
	// Bit ARAL.
	FDCAN1_FDCAN_ILS_ARAL = 0x20000000

	// FDCAN_ILE: Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
	// Position of EINT0 field.
	FDCAN1_FDCAN_ILE_EINT0_Pos = 0x0
	// Bit mask of EINT0 field.
	FDCAN1_FDCAN_ILE_EINT0_Msk = 0x1
	// Bit EINT0.
	FDCAN1_FDCAN_ILE_EINT0 = 0x1
	// Position of EINT1 field.
	FDCAN1_FDCAN_ILE_EINT1_Pos = 0x1
	// Bit mask of EINT1 field.
	FDCAN1_FDCAN_ILE_EINT1_Msk = 0x2
	// Bit EINT1.
	FDCAN1_FDCAN_ILE_EINT1 = 0x2

	// FDCAN_GFC: Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path.
	// Position of RRFE field.
	FDCAN1_FDCAN_GFC_RRFE_Pos = 0x0
	// Bit mask of RRFE field.
	FDCAN1_FDCAN_GFC_RRFE_Msk = 0x1
	// Bit RRFE.
	FDCAN1_FDCAN_GFC_RRFE = 0x1
	// Position of RRFS field.
	FDCAN1_FDCAN_GFC_RRFS_Pos = 0x1
	// Bit mask of RRFS field.
	FDCAN1_FDCAN_GFC_RRFS_Msk = 0x2
	// Bit RRFS.
	FDCAN1_FDCAN_GFC_RRFS = 0x2
	// Position of ANFE field.
	FDCAN1_FDCAN_GFC_ANFE_Pos = 0x2
	// Bit mask of ANFE field.
	FDCAN1_FDCAN_GFC_ANFE_Msk = 0xc
	// Position of ANFS field.
	FDCAN1_FDCAN_GFC_ANFS_Pos = 0x4
	// Bit mask of ANFS field.
	FDCAN1_FDCAN_GFC_ANFS_Msk = 0x30

	// FDCAN_SIDFC: Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708.
	// Position of FLSSA field.
	FDCAN1_FDCAN_SIDFC_FLSSA_Pos = 0x2
	// Bit mask of FLSSA field.
	FDCAN1_FDCAN_SIDFC_FLSSA_Msk = 0xfffc
	// Position of LSS field.
	FDCAN1_FDCAN_SIDFC_LSS_Pos = 0x10
	// Bit mask of LSS field.
	FDCAN1_FDCAN_SIDFC_LSS_Msk = 0xff0000

	// FDCAN_XIDFC: Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path.
	// Position of FLESA field.
	FDCAN1_FDCAN_XIDFC_FLESA_Pos = 0x2
	// Bit mask of FLESA field.
	FDCAN1_FDCAN_XIDFC_FLESA_Msk = 0xfffc
	// Position of LSE field.
	FDCAN1_FDCAN_XIDFC_LSE_Pos = 0x10
	// Bit mask of LSE field.
	FDCAN1_FDCAN_XIDFC_LSE_Msk = 0xff0000

	// FDCAN_XIDAM: FDCAN extended ID and mask register
	// Position of EIDM field.
	FDCAN1_FDCAN_XIDAM_EIDM_Pos = 0x0
	// Bit mask of EIDM field.
	FDCAN1_FDCAN_XIDAM_EIDM_Msk = 0x1fffffff

	// FDCAN_HPMS: This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
	// Position of BIDX field.
	FDCAN1_FDCAN_HPMS_BIDX_Pos = 0x0
	// Bit mask of BIDX field.
	FDCAN1_FDCAN_HPMS_BIDX_Msk = 0x3f
	// Position of MSI field.
	FDCAN1_FDCAN_HPMS_MSI_Pos = 0x6
	// Bit mask of MSI field.
	FDCAN1_FDCAN_HPMS_MSI_Msk = 0xc0
	// Position of FIDX field.
	FDCAN1_FDCAN_HPMS_FIDX_Pos = 0x8
	// Bit mask of FIDX field.
	FDCAN1_FDCAN_HPMS_FIDX_Msk = 0x7f00
	// Position of FLST field.
	FDCAN1_FDCAN_HPMS_FLST_Pos = 0xf
	// Bit mask of FLST field.
	FDCAN1_FDCAN_HPMS_FLST_Msk = 0x8000
	// Bit FLST.
	FDCAN1_FDCAN_HPMS_FLST = 0x8000

	// FDCAN_NDAT1: FDCAN new data 1 register
	// Position of ND0 field.
	FDCAN1_FDCAN_NDAT1_ND0_Pos = 0x0
	// Bit mask of ND0 field.
	FDCAN1_FDCAN_NDAT1_ND0_Msk = 0x1
	// Bit ND0.
	FDCAN1_FDCAN_NDAT1_ND0 = 0x1
	// Position of ND1 field.
	FDCAN1_FDCAN_NDAT1_ND1_Pos = 0x1
	// Bit mask of ND1 field.
	FDCAN1_FDCAN_NDAT1_ND1_Msk = 0x2
	// Bit ND1.
	FDCAN1_FDCAN_NDAT1_ND1 = 0x2
	// Position of ND2 field.
	FDCAN1_FDCAN_NDAT1_ND2_Pos = 0x2
	// Bit mask of ND2 field.
	FDCAN1_FDCAN_NDAT1_ND2_Msk = 0x4
	// Bit ND2.
	FDCAN1_FDCAN_NDAT1_ND2 = 0x4
	// Position of ND3 field.
	FDCAN1_FDCAN_NDAT1_ND3_Pos = 0x3
	// Bit mask of ND3 field.
	FDCAN1_FDCAN_NDAT1_ND3_Msk = 0x8
	// Bit ND3.
	FDCAN1_FDCAN_NDAT1_ND3 = 0x8
	// Position of ND4 field.
	FDCAN1_FDCAN_NDAT1_ND4_Pos = 0x4
	// Bit mask of ND4 field.
	FDCAN1_FDCAN_NDAT1_ND4_Msk = 0x10
	// Bit ND4.
	FDCAN1_FDCAN_NDAT1_ND4 = 0x10
	// Position of ND5 field.
	FDCAN1_FDCAN_NDAT1_ND5_Pos = 0x5
	// Bit mask of ND5 field.
	FDCAN1_FDCAN_NDAT1_ND5_Msk = 0x20
	// Bit ND5.
	FDCAN1_FDCAN_NDAT1_ND5 = 0x20
	// Position of ND6 field.
	FDCAN1_FDCAN_NDAT1_ND6_Pos = 0x6
	// Bit mask of ND6 field.
	FDCAN1_FDCAN_NDAT1_ND6_Msk = 0x40
	// Bit ND6.
	FDCAN1_FDCAN_NDAT1_ND6 = 0x40
	// Position of ND7 field.
	FDCAN1_FDCAN_NDAT1_ND7_Pos = 0x7
	// Bit mask of ND7 field.
	FDCAN1_FDCAN_NDAT1_ND7_Msk = 0x80
	// Bit ND7.
	FDCAN1_FDCAN_NDAT1_ND7 = 0x80
	// Position of ND8 field.
	FDCAN1_FDCAN_NDAT1_ND8_Pos = 0x8
	// Bit mask of ND8 field.
	FDCAN1_FDCAN_NDAT1_ND8_Msk = 0x100
	// Bit ND8.
	FDCAN1_FDCAN_NDAT1_ND8 = 0x100
	// Position of ND9 field.
	FDCAN1_FDCAN_NDAT1_ND9_Pos = 0x9
	// Bit mask of ND9 field.
	FDCAN1_FDCAN_NDAT1_ND9_Msk = 0x200
	// Bit ND9.
	FDCAN1_FDCAN_NDAT1_ND9 = 0x200
	// Position of ND10 field.
	FDCAN1_FDCAN_NDAT1_ND10_Pos = 0xa
	// Bit mask of ND10 field.
	FDCAN1_FDCAN_NDAT1_ND10_Msk = 0x400
	// Bit ND10.
	FDCAN1_FDCAN_NDAT1_ND10 = 0x400
	// Position of ND11 field.
	FDCAN1_FDCAN_NDAT1_ND11_Pos = 0xb
	// Bit mask of ND11 field.
	FDCAN1_FDCAN_NDAT1_ND11_Msk = 0x800
	// Bit ND11.
	FDCAN1_FDCAN_NDAT1_ND11 = 0x800
	// Position of ND12 field.
	FDCAN1_FDCAN_NDAT1_ND12_Pos = 0xc
	// Bit mask of ND12 field.
	FDCAN1_FDCAN_NDAT1_ND12_Msk = 0x1000
	// Bit ND12.
	FDCAN1_FDCAN_NDAT1_ND12 = 0x1000
	// Position of ND13 field.
	FDCAN1_FDCAN_NDAT1_ND13_Pos = 0xd
	// Bit mask of ND13 field.
	FDCAN1_FDCAN_NDAT1_ND13_Msk = 0x2000
	// Bit ND13.
	FDCAN1_FDCAN_NDAT1_ND13 = 0x2000
	// Position of ND14 field.
	FDCAN1_FDCAN_NDAT1_ND14_Pos = 0xe
	// Bit mask of ND14 field.
	FDCAN1_FDCAN_NDAT1_ND14_Msk = 0x4000
	// Bit ND14.
	FDCAN1_FDCAN_NDAT1_ND14 = 0x4000
	// Position of ND15 field.
	FDCAN1_FDCAN_NDAT1_ND15_Pos = 0xf
	// Bit mask of ND15 field.
	FDCAN1_FDCAN_NDAT1_ND15_Msk = 0x8000
	// Bit ND15.
	FDCAN1_FDCAN_NDAT1_ND15 = 0x8000
	// Position of ND16 field.
	FDCAN1_FDCAN_NDAT1_ND16_Pos = 0x10
	// Bit mask of ND16 field.
	FDCAN1_FDCAN_NDAT1_ND16_Msk = 0x10000
	// Bit ND16.
	FDCAN1_FDCAN_NDAT1_ND16 = 0x10000
	// Position of ND17 field.
	FDCAN1_FDCAN_NDAT1_ND17_Pos = 0x11
	// Bit mask of ND17 field.
	FDCAN1_FDCAN_NDAT1_ND17_Msk = 0x20000
	// Bit ND17.
	FDCAN1_FDCAN_NDAT1_ND17 = 0x20000
	// Position of ND18 field.
	FDCAN1_FDCAN_NDAT1_ND18_Pos = 0x12
	// Bit mask of ND18 field.
	FDCAN1_FDCAN_NDAT1_ND18_Msk = 0x40000
	// Bit ND18.
	FDCAN1_FDCAN_NDAT1_ND18 = 0x40000
	// Position of ND19 field.
	FDCAN1_FDCAN_NDAT1_ND19_Pos = 0x13
	// Bit mask of ND19 field.
	FDCAN1_FDCAN_NDAT1_ND19_Msk = 0x80000
	// Bit ND19.
	FDCAN1_FDCAN_NDAT1_ND19 = 0x80000
	// Position of ND20 field.
	FDCAN1_FDCAN_NDAT1_ND20_Pos = 0x14
	// Bit mask of ND20 field.
	FDCAN1_FDCAN_NDAT1_ND20_Msk = 0x100000
	// Bit ND20.
	FDCAN1_FDCAN_NDAT1_ND20 = 0x100000
	// Position of ND21 field.
	FDCAN1_FDCAN_NDAT1_ND21_Pos = 0x15
	// Bit mask of ND21 field.
	FDCAN1_FDCAN_NDAT1_ND21_Msk = 0x200000
	// Bit ND21.
	FDCAN1_FDCAN_NDAT1_ND21 = 0x200000
	// Position of ND22 field.
	FDCAN1_FDCAN_NDAT1_ND22_Pos = 0x16
	// Bit mask of ND22 field.
	FDCAN1_FDCAN_NDAT1_ND22_Msk = 0x400000
	// Bit ND22.
	FDCAN1_FDCAN_NDAT1_ND22 = 0x400000
	// Position of ND23 field.
	FDCAN1_FDCAN_NDAT1_ND23_Pos = 0x17
	// Bit mask of ND23 field.
	FDCAN1_FDCAN_NDAT1_ND23_Msk = 0x800000
	// Bit ND23.
	FDCAN1_FDCAN_NDAT1_ND23 = 0x800000
	// Position of ND24 field.
	FDCAN1_FDCAN_NDAT1_ND24_Pos = 0x18
	// Bit mask of ND24 field.
	FDCAN1_FDCAN_NDAT1_ND24_Msk = 0x1000000
	// Bit ND24.
	FDCAN1_FDCAN_NDAT1_ND24 = 0x1000000
	// Position of ND25 field.
	FDCAN1_FDCAN_NDAT1_ND25_Pos = 0x19
	// Bit mask of ND25 field.
	FDCAN1_FDCAN_NDAT1_ND25_Msk = 0x2000000
	// Bit ND25.
	FDCAN1_FDCAN_NDAT1_ND25 = 0x2000000
	// Position of ND26 field.
	FDCAN1_FDCAN_NDAT1_ND26_Pos = 0x1a
	// Bit mask of ND26 field.
	FDCAN1_FDCAN_NDAT1_ND26_Msk = 0x4000000
	// Bit ND26.
	FDCAN1_FDCAN_NDAT1_ND26 = 0x4000000
	// Position of ND27 field.
	FDCAN1_FDCAN_NDAT1_ND27_Pos = 0x1b
	// Bit mask of ND27 field.
	FDCAN1_FDCAN_NDAT1_ND27_Msk = 0x8000000
	// Bit ND27.
	FDCAN1_FDCAN_NDAT1_ND27 = 0x8000000
	// Position of ND28 field.
	FDCAN1_FDCAN_NDAT1_ND28_Pos = 0x1c
	// Bit mask of ND28 field.
	FDCAN1_FDCAN_NDAT1_ND28_Msk = 0x10000000
	// Bit ND28.
	FDCAN1_FDCAN_NDAT1_ND28 = 0x10000000
	// Position of ND29 field.
	FDCAN1_FDCAN_NDAT1_ND29_Pos = 0x1d
	// Bit mask of ND29 field.
	FDCAN1_FDCAN_NDAT1_ND29_Msk = 0x20000000
	// Bit ND29.
	FDCAN1_FDCAN_NDAT1_ND29 = 0x20000000
	// Position of ND30 field.
	FDCAN1_FDCAN_NDAT1_ND30_Pos = 0x1e
	// Bit mask of ND30 field.
	FDCAN1_FDCAN_NDAT1_ND30_Msk = 0x40000000
	// Bit ND30.
	FDCAN1_FDCAN_NDAT1_ND30 = 0x40000000
	// Position of ND31 field.
	FDCAN1_FDCAN_NDAT1_ND31_Pos = 0x1f
	// Bit mask of ND31 field.
	FDCAN1_FDCAN_NDAT1_ND31_Msk = 0x80000000
	// Bit ND31.
	FDCAN1_FDCAN_NDAT1_ND31 = 0x80000000

	// FDCAN_NDAT2: FDCAN new data 2 register
	// Position of ND32 field.
	FDCAN1_FDCAN_NDAT2_ND32_Pos = 0x0
	// Bit mask of ND32 field.
	FDCAN1_FDCAN_NDAT2_ND32_Msk = 0x1
	// Bit ND32.
	FDCAN1_FDCAN_NDAT2_ND32 = 0x1
	// Position of ND33 field.
	FDCAN1_FDCAN_NDAT2_ND33_Pos = 0x1
	// Bit mask of ND33 field.
	FDCAN1_FDCAN_NDAT2_ND33_Msk = 0x2
	// Bit ND33.
	FDCAN1_FDCAN_NDAT2_ND33 = 0x2
	// Position of ND34 field.
	FDCAN1_FDCAN_NDAT2_ND34_Pos = 0x2
	// Bit mask of ND34 field.
	FDCAN1_FDCAN_NDAT2_ND34_Msk = 0x4
	// Bit ND34.
	FDCAN1_FDCAN_NDAT2_ND34 = 0x4
	// Position of ND35 field.
	FDCAN1_FDCAN_NDAT2_ND35_Pos = 0x3
	// Bit mask of ND35 field.
	FDCAN1_FDCAN_NDAT2_ND35_Msk = 0x8
	// Bit ND35.
	FDCAN1_FDCAN_NDAT2_ND35 = 0x8
	// Position of ND36 field.
	FDCAN1_FDCAN_NDAT2_ND36_Pos = 0x4
	// Bit mask of ND36 field.
	FDCAN1_FDCAN_NDAT2_ND36_Msk = 0x10
	// Bit ND36.
	FDCAN1_FDCAN_NDAT2_ND36 = 0x10
	// Position of ND37 field.
	FDCAN1_FDCAN_NDAT2_ND37_Pos = 0x5
	// Bit mask of ND37 field.
	FDCAN1_FDCAN_NDAT2_ND37_Msk = 0x20
	// Bit ND37.
	FDCAN1_FDCAN_NDAT2_ND37 = 0x20
	// Position of ND38 field.
	FDCAN1_FDCAN_NDAT2_ND38_Pos = 0x6
	// Bit mask of ND38 field.
	FDCAN1_FDCAN_NDAT2_ND38_Msk = 0x40
	// Bit ND38.
	FDCAN1_FDCAN_NDAT2_ND38 = 0x40
	// Position of ND39 field.
	FDCAN1_FDCAN_NDAT2_ND39_Pos = 0x7
	// Bit mask of ND39 field.
	FDCAN1_FDCAN_NDAT2_ND39_Msk = 0x80
	// Bit ND39.
	FDCAN1_FDCAN_NDAT2_ND39 = 0x80
	// Position of ND40 field.
	FDCAN1_FDCAN_NDAT2_ND40_Pos = 0x8
	// Bit mask of ND40 field.
	FDCAN1_FDCAN_NDAT2_ND40_Msk = 0x100
	// Bit ND40.
	FDCAN1_FDCAN_NDAT2_ND40 = 0x100
	// Position of ND41 field.
	FDCAN1_FDCAN_NDAT2_ND41_Pos = 0x9
	// Bit mask of ND41 field.
	FDCAN1_FDCAN_NDAT2_ND41_Msk = 0x200
	// Bit ND41.
	FDCAN1_FDCAN_NDAT2_ND41 = 0x200
	// Position of ND42 field.
	FDCAN1_FDCAN_NDAT2_ND42_Pos = 0xa
	// Bit mask of ND42 field.
	FDCAN1_FDCAN_NDAT2_ND42_Msk = 0x400
	// Bit ND42.
	FDCAN1_FDCAN_NDAT2_ND42 = 0x400
	// Position of ND43 field.
	FDCAN1_FDCAN_NDAT2_ND43_Pos = 0xb
	// Bit mask of ND43 field.
	FDCAN1_FDCAN_NDAT2_ND43_Msk = 0x800
	// Bit ND43.
	FDCAN1_FDCAN_NDAT2_ND43 = 0x800
	// Position of ND44 field.
	FDCAN1_FDCAN_NDAT2_ND44_Pos = 0xc
	// Bit mask of ND44 field.
	FDCAN1_FDCAN_NDAT2_ND44_Msk = 0x1000
	// Bit ND44.
	FDCAN1_FDCAN_NDAT2_ND44 = 0x1000
	// Position of ND45 field.
	FDCAN1_FDCAN_NDAT2_ND45_Pos = 0xd
	// Bit mask of ND45 field.
	FDCAN1_FDCAN_NDAT2_ND45_Msk = 0x2000
	// Bit ND45.
	FDCAN1_FDCAN_NDAT2_ND45 = 0x2000
	// Position of ND46 field.
	FDCAN1_FDCAN_NDAT2_ND46_Pos = 0xe
	// Bit mask of ND46 field.
	FDCAN1_FDCAN_NDAT2_ND46_Msk = 0x4000
	// Bit ND46.
	FDCAN1_FDCAN_NDAT2_ND46 = 0x4000
	// Position of ND47 field.
	FDCAN1_FDCAN_NDAT2_ND47_Pos = 0xf
	// Bit mask of ND47 field.
	FDCAN1_FDCAN_NDAT2_ND47_Msk = 0x8000
	// Bit ND47.
	FDCAN1_FDCAN_NDAT2_ND47 = 0x8000
	// Position of ND48 field.
	FDCAN1_FDCAN_NDAT2_ND48_Pos = 0x10
	// Bit mask of ND48 field.
	FDCAN1_FDCAN_NDAT2_ND48_Msk = 0x10000
	// Bit ND48.
	FDCAN1_FDCAN_NDAT2_ND48 = 0x10000
	// Position of ND49 field.
	FDCAN1_FDCAN_NDAT2_ND49_Pos = 0x11
	// Bit mask of ND49 field.
	FDCAN1_FDCAN_NDAT2_ND49_Msk = 0x20000
	// Bit ND49.
	FDCAN1_FDCAN_NDAT2_ND49 = 0x20000
	// Position of ND50 field.
	FDCAN1_FDCAN_NDAT2_ND50_Pos = 0x12
	// Bit mask of ND50 field.
	FDCAN1_FDCAN_NDAT2_ND50_Msk = 0x40000
	// Bit ND50.
	FDCAN1_FDCAN_NDAT2_ND50 = 0x40000
	// Position of ND51 field.
	FDCAN1_FDCAN_NDAT2_ND51_Pos = 0x13
	// Bit mask of ND51 field.
	FDCAN1_FDCAN_NDAT2_ND51_Msk = 0x80000
	// Bit ND51.
	FDCAN1_FDCAN_NDAT2_ND51 = 0x80000
	// Position of ND52 field.
	FDCAN1_FDCAN_NDAT2_ND52_Pos = 0x14
	// Bit mask of ND52 field.
	FDCAN1_FDCAN_NDAT2_ND52_Msk = 0x100000
	// Bit ND52.
	FDCAN1_FDCAN_NDAT2_ND52 = 0x100000
	// Position of ND53 field.
	FDCAN1_FDCAN_NDAT2_ND53_Pos = 0x15
	// Bit mask of ND53 field.
	FDCAN1_FDCAN_NDAT2_ND53_Msk = 0x200000
	// Bit ND53.
	FDCAN1_FDCAN_NDAT2_ND53 = 0x200000
	// Position of ND54 field.
	FDCAN1_FDCAN_NDAT2_ND54_Pos = 0x16
	// Bit mask of ND54 field.
	FDCAN1_FDCAN_NDAT2_ND54_Msk = 0x400000
	// Bit ND54.
	FDCAN1_FDCAN_NDAT2_ND54 = 0x400000
	// Position of ND55 field.
	FDCAN1_FDCAN_NDAT2_ND55_Pos = 0x17
	// Bit mask of ND55 field.
	FDCAN1_FDCAN_NDAT2_ND55_Msk = 0x800000
	// Bit ND55.
	FDCAN1_FDCAN_NDAT2_ND55 = 0x800000
	// Position of ND56 field.
	FDCAN1_FDCAN_NDAT2_ND56_Pos = 0x18
	// Bit mask of ND56 field.
	FDCAN1_FDCAN_NDAT2_ND56_Msk = 0x1000000
	// Bit ND56.
	FDCAN1_FDCAN_NDAT2_ND56 = 0x1000000
	// Position of ND57 field.
	FDCAN1_FDCAN_NDAT2_ND57_Pos = 0x19
	// Bit mask of ND57 field.
	FDCAN1_FDCAN_NDAT2_ND57_Msk = 0x2000000
	// Bit ND57.
	FDCAN1_FDCAN_NDAT2_ND57 = 0x2000000
	// Position of ND58 field.
	FDCAN1_FDCAN_NDAT2_ND58_Pos = 0x1a
	// Bit mask of ND58 field.
	FDCAN1_FDCAN_NDAT2_ND58_Msk = 0x4000000
	// Bit ND58.
	FDCAN1_FDCAN_NDAT2_ND58 = 0x4000000
	// Position of ND59 field.
	FDCAN1_FDCAN_NDAT2_ND59_Pos = 0x1b
	// Bit mask of ND59 field.
	FDCAN1_FDCAN_NDAT2_ND59_Msk = 0x8000000
	// Bit ND59.
	FDCAN1_FDCAN_NDAT2_ND59 = 0x8000000
	// Position of ND60 field.
	FDCAN1_FDCAN_NDAT2_ND60_Pos = 0x1c
	// Bit mask of ND60 field.
	FDCAN1_FDCAN_NDAT2_ND60_Msk = 0x10000000
	// Bit ND60.
	FDCAN1_FDCAN_NDAT2_ND60 = 0x10000000
	// Position of ND61 field.
	FDCAN1_FDCAN_NDAT2_ND61_Pos = 0x1d
	// Bit mask of ND61 field.
	FDCAN1_FDCAN_NDAT2_ND61_Msk = 0x20000000
	// Bit ND61.
	FDCAN1_FDCAN_NDAT2_ND61 = 0x20000000
	// Position of ND62 field.
	FDCAN1_FDCAN_NDAT2_ND62_Pos = 0x1e
	// Bit mask of ND62 field.
	FDCAN1_FDCAN_NDAT2_ND62_Msk = 0x40000000
	// Bit ND62.
	FDCAN1_FDCAN_NDAT2_ND62 = 0x40000000
	// Position of ND63 field.
	FDCAN1_FDCAN_NDAT2_ND63_Pos = 0x1f
	// Bit mask of ND63 field.
	FDCAN1_FDCAN_NDAT2_ND63_Msk = 0x80000000
	// Bit ND63.
	FDCAN1_FDCAN_NDAT2_ND63 = 0x80000000

	// FDCAN_RXF0C: FDCAN Rx FIFO 0 configuration register
	// Position of F0SA field.
	FDCAN1_FDCAN_RXF0C_F0SA_Pos = 0x2
	// Bit mask of F0SA field.
	FDCAN1_FDCAN_RXF0C_F0SA_Msk = 0xfffc
	// Position of F0S field.
	FDCAN1_FDCAN_RXF0C_F0S_Pos = 0x10
	// Bit mask of F0S field.
	FDCAN1_FDCAN_RXF0C_F0S_Msk = 0x7f0000
	// Position of F0WM field.
	FDCAN1_FDCAN_RXF0C_F0WM_Pos = 0x18
	// Bit mask of F0WM field.
	FDCAN1_FDCAN_RXF0C_F0WM_Msk = 0x7f000000
	// Position of F0OM field.
	FDCAN1_FDCAN_RXF0C_F0OM_Pos = 0x1f
	// Bit mask of F0OM field.
	FDCAN1_FDCAN_RXF0C_F0OM_Msk = 0x80000000
	// Bit F0OM.
	FDCAN1_FDCAN_RXF0C_F0OM = 0x80000000

	// FDCAN_RXF0S: FDCAN Rx FIFO 0 status register
	// Position of F0FL field.
	FDCAN1_FDCAN_RXF0S_F0FL_Pos = 0x0
	// Bit mask of F0FL field.
	FDCAN1_FDCAN_RXF0S_F0FL_Msk = 0x7f
	// Position of F0GI field.
	FDCAN1_FDCAN_RXF0S_F0GI_Pos = 0x8
	// Bit mask of F0GI field.
	FDCAN1_FDCAN_RXF0S_F0GI_Msk = 0x3f00
	// Position of F0PI field.
	FDCAN1_FDCAN_RXF0S_F0PI_Pos = 0x10
	// Bit mask of F0PI field.
	FDCAN1_FDCAN_RXF0S_F0PI_Msk = 0x3f0000
	// Position of F0F field.
	FDCAN1_FDCAN_RXF0S_F0F_Pos = 0x18
	// Bit mask of F0F field.
	FDCAN1_FDCAN_RXF0S_F0F_Msk = 0x1000000
	// Bit F0F.
	FDCAN1_FDCAN_RXF0S_F0F = 0x1000000
	// Position of RF0L field.
	FDCAN1_FDCAN_RXF0S_RF0L_Pos = 0x19
	// Bit mask of RF0L field.
	FDCAN1_FDCAN_RXF0S_RF0L_Msk = 0x2000000
	// Bit RF0L.
	FDCAN1_FDCAN_RXF0S_RF0L = 0x2000000

	// FDCAN_RXF0A: FDCAN Rx FIFO 0 acknowledge register
	// Position of F0AI field.
	FDCAN1_FDCAN_RXF0A_F0AI_Pos = 0x0
	// Bit mask of F0AI field.
	FDCAN1_FDCAN_RXF0A_F0AI_Msk = 0x3f

	// FDCAN_RXBC: FDCAN Rx buffer configuration register
	// Position of RBSA field.
	FDCAN1_FDCAN_RXBC_RBSA_Pos = 0x2
	// Bit mask of RBSA field.
	FDCAN1_FDCAN_RXBC_RBSA_Msk = 0xfffc

	// FDCAN_RXF1C: FDCAN Rx FIFO 1 configuration register
	// Position of F1SA field.
	FDCAN1_FDCAN_RXF1C_F1SA_Pos = 0x2
	// Bit mask of F1SA field.
	FDCAN1_FDCAN_RXF1C_F1SA_Msk = 0xfffc
	// Position of F1S field.
	FDCAN1_FDCAN_RXF1C_F1S_Pos = 0x10
	// Bit mask of F1S field.
	FDCAN1_FDCAN_RXF1C_F1S_Msk = 0x7f0000
	// Position of F1WM field.
	FDCAN1_FDCAN_RXF1C_F1WM_Pos = 0x18
	// Bit mask of F1WM field.
	FDCAN1_FDCAN_RXF1C_F1WM_Msk = 0x7f000000
	// Position of F1OM field.
	FDCAN1_FDCAN_RXF1C_F1OM_Pos = 0x1f
	// Bit mask of F1OM field.
	FDCAN1_FDCAN_RXF1C_F1OM_Msk = 0x80000000
	// Bit F1OM.
	FDCAN1_FDCAN_RXF1C_F1OM = 0x80000000

	// FDCAN_RXF1S: FDCAN Rx FIFO 1 status register
	// Position of F1FL field.
	FDCAN1_FDCAN_RXF1S_F1FL_Pos = 0x0
	// Bit mask of F1FL field.
	FDCAN1_FDCAN_RXF1S_F1FL_Msk = 0x7f
	// Position of F1GI field.
	FDCAN1_FDCAN_RXF1S_F1GI_Pos = 0x8
	// Bit mask of F1GI field.
	FDCAN1_FDCAN_RXF1S_F1GI_Msk = 0x3f00
	// Position of F1PI field.
	FDCAN1_FDCAN_RXF1S_F1PI_Pos = 0x10
	// Bit mask of F1PI field.
	FDCAN1_FDCAN_RXF1S_F1PI_Msk = 0x3f0000
	// Position of F1F field.
	FDCAN1_FDCAN_RXF1S_F1F_Pos = 0x18
	// Bit mask of F1F field.
	FDCAN1_FDCAN_RXF1S_F1F_Msk = 0x1000000
	// Bit F1F.
	FDCAN1_FDCAN_RXF1S_F1F = 0x1000000
	// Position of RF1L field.
	FDCAN1_FDCAN_RXF1S_RF1L_Pos = 0x19
	// Bit mask of RF1L field.
	FDCAN1_FDCAN_RXF1S_RF1L_Msk = 0x2000000
	// Bit RF1L.
	FDCAN1_FDCAN_RXF1S_RF1L = 0x2000000
	// Position of DMS field.
	FDCAN1_FDCAN_RXF1S_DMS_Pos = 0x1e
	// Bit mask of DMS field.
	FDCAN1_FDCAN_RXF1S_DMS_Msk = 0xc0000000

	// FDCAN_RXF1A: FDCAN Rx FIFO 1 acknowledge register
	// Position of F1AI field.
	FDCAN1_FDCAN_RXF1A_F1AI_Pos = 0x0
	// Bit mask of F1AI field.
	FDCAN1_FDCAN_RXF1A_F1AI_Msk = 0x3f

	// FDCAN_RXESC: Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only.
	// Position of F0DS field.
	FDCAN1_FDCAN_RXESC_F0DS_Pos = 0x0
	// Bit mask of F0DS field.
	FDCAN1_FDCAN_RXESC_F0DS_Msk = 0x7
	// Position of F1DS field.
	FDCAN1_FDCAN_RXESC_F1DS_Pos = 0x4
	// Bit mask of F1DS field.
	FDCAN1_FDCAN_RXESC_F1DS_Msk = 0x70
	// Position of RBDS field.
	FDCAN1_FDCAN_RXESC_RBDS_Pos = 0x8
	// Bit mask of RBDS field.
	FDCAN1_FDCAN_RXESC_RBDS_Msk = 0x700

	// FDCAN_TXBC: FDCAN Tx buffer configuration register
	// Position of TBSA field.
	FDCAN1_FDCAN_TXBC_TBSA_Pos = 0x2
	// Bit mask of TBSA field.
	FDCAN1_FDCAN_TXBC_TBSA_Msk = 0xfffc
	// Position of NDTB field.
	FDCAN1_FDCAN_TXBC_NDTB_Pos = 0x10
	// Bit mask of NDTB field.
	FDCAN1_FDCAN_TXBC_NDTB_Msk = 0x3f0000
	// Position of TFQS field.
	FDCAN1_FDCAN_TXBC_TFQS_Pos = 0x18
	// Bit mask of TFQS field.
	FDCAN1_FDCAN_TXBC_TFQS_Msk = 0x3f000000
	// Position of TFQM field.
	FDCAN1_FDCAN_TXBC_TFQM_Pos = 0x1e
	// Bit mask of TFQM field.
	FDCAN1_FDCAN_TXBC_TFQM_Msk = 0x40000000
	// Bit TFQM.
	FDCAN1_FDCAN_TXBC_TFQM = 0x40000000

	// FDCAN_TXFQS: The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated).
	// Position of TFFL field.
	FDCAN1_FDCAN_TXFQS_TFFL_Pos = 0x0
	// Bit mask of TFFL field.
	FDCAN1_FDCAN_TXFQS_TFFL_Msk = 0x3f
	// Position of TFGI field.
	FDCAN1_FDCAN_TXFQS_TFGI_Pos = 0x8
	// Bit mask of TFGI field.
	FDCAN1_FDCAN_TXFQS_TFGI_Msk = 0x1f00
	// Position of TFQPI field.
	FDCAN1_FDCAN_TXFQS_TFQPI_Pos = 0x10
	// Bit mask of TFQPI field.
	FDCAN1_FDCAN_TXFQS_TFQPI_Msk = 0x1f0000
	// Position of TFQF field.
	FDCAN1_FDCAN_TXFQS_TFQF_Pos = 0x15
	// Bit mask of TFQF field.
	FDCAN1_FDCAN_TXFQS_TFQF_Msk = 0x200000
	// Bit TFQF.
	FDCAN1_FDCAN_TXFQS_TFQF = 0x200000

	// FDCAN_TXESC: Configures the number of data bytes belonging to a Tx buffer element. Data field sizes &gt;8 bytes are intended for CAN FD operation only.
	// Position of TBDS field.
	FDCAN1_FDCAN_TXESC_TBDS_Pos = 0x0
	// Bit mask of TBDS field.
	FDCAN1_FDCAN_TXESC_TBDS_Msk = 0x7

	// FDCAN_TXBAR: FDCAN Tx buffer add request register
	// Position of AR field.
	FDCAN1_FDCAN_TXBAR_AR_Pos = 0x0
	// Bit mask of AR field.
	FDCAN1_FDCAN_TXBAR_AR_Msk = 0xffffffff

	// FDCAN_TXBCR: FDCAN Tx buffer cancellation request register
	// Position of CR field.
	FDCAN1_FDCAN_TXBCR_CR_Pos = 0x0
	// Bit mask of CR field.
	FDCAN1_FDCAN_TXBCR_CR_Msk = 0xffffffff

	// FDCAN_TXBTO: FDCAN Tx buffer transmission occurred register
	// Position of TO field.
	FDCAN1_FDCAN_TXBTO_TO_Pos = 0x0
	// Bit mask of TO field.
	FDCAN1_FDCAN_TXBTO_TO_Msk = 0xffffffff

	// FDCAN_TXBCF: FDCAN Tx buffer cancellation finished register
	// Position of CF field.
	FDCAN1_FDCAN_TXBCF_CF_Pos = 0x0
	// Bit mask of CF field.
	FDCAN1_FDCAN_TXBCF_CF_Msk = 0xffffffff

	// FDCAN_TXBTIE: FDCAN Tx buffer transmission interrupt enable register
	// Position of TIE field.
	FDCAN1_FDCAN_TXBTIE_TIE_Pos = 0x0
	// Bit mask of TIE field.
	FDCAN1_FDCAN_TXBTIE_TIE_Msk = 0xffffffff

	// FDCAN_TXBCIE: FDCAN Tx buffer cancellation finished interrupt enable register
	// Position of CFIE field.
	FDCAN1_FDCAN_TXBCIE_CFIE_Pos = 0x0
	// Bit mask of CFIE field.
	FDCAN1_FDCAN_TXBCIE_CFIE_Msk = 0xffffffff

	// FDCAN_TXEFC: FDCAN Tx event FIFO configuration register
	// Position of EFSA field.
	FDCAN1_FDCAN_TXEFC_EFSA_Pos = 0x2
	// Bit mask of EFSA field.
	FDCAN1_FDCAN_TXEFC_EFSA_Msk = 0xfffc
	// Position of EFS field.
	FDCAN1_FDCAN_TXEFC_EFS_Pos = 0x10
	// Bit mask of EFS field.
	FDCAN1_FDCAN_TXEFC_EFS_Msk = 0x3f0000
	// Position of EFWM field.
	FDCAN1_FDCAN_TXEFC_EFWM_Pos = 0x18
	// Bit mask of EFWM field.
	FDCAN1_FDCAN_TXEFC_EFWM_Msk = 0x3f000000

	// FDCAN_TXEFS: FDCAN Tx event FIFO status register
	// Position of EFFL field.
	FDCAN1_FDCAN_TXEFS_EFFL_Pos = 0x0
	// Bit mask of EFFL field.
	FDCAN1_FDCAN_TXEFS_EFFL_Msk = 0x3f
	// Position of EFGI field.
	FDCAN1_FDCAN_TXEFS_EFGI_Pos = 0x8
	// Bit mask of EFGI field.
	FDCAN1_FDCAN_TXEFS_EFGI_Msk = 0x1f00
	// Position of EFPI field.
	FDCAN1_FDCAN_TXEFS_EFPI_Pos = 0x10
	// Bit mask of EFPI field.
	FDCAN1_FDCAN_TXEFS_EFPI_Msk = 0x1f0000
	// Position of EFF field.
	FDCAN1_FDCAN_TXEFS_EFF_Pos = 0x18
	// Bit mask of EFF field.
	FDCAN1_FDCAN_TXEFS_EFF_Msk = 0x1000000
	// Bit EFF.
	FDCAN1_FDCAN_TXEFS_EFF = 0x1000000
	// Position of TEFL field.
	FDCAN1_FDCAN_TXEFS_TEFL_Pos = 0x19
	// Bit mask of TEFL field.
	FDCAN1_FDCAN_TXEFS_TEFL_Msk = 0x2000000
	// Bit TEFL.
	FDCAN1_FDCAN_TXEFS_TEFL = 0x2000000

	// FDCAN_TXEFA: FDCAN Tx event FIFO acknowledge register
	// Position of EFAI field.
	FDCAN1_FDCAN_TXEFA_EFAI_Pos = 0x0
	// Bit mask of EFAI field.
	FDCAN1_FDCAN_TXEFA_EFAI_Msk = 0x1f

	// FDCAN_TTTMC: FDCAN TT trigger memory configuration register
	// Position of TMSA field.
	FDCAN1_FDCAN_TTTMC_TMSA_Pos = 0x2
	// Bit mask of TMSA field.
	FDCAN1_FDCAN_TTTMC_TMSA_Msk = 0xfffc
	// Position of TME field.
	FDCAN1_FDCAN_TTTMC_TME_Pos = 0x10
	// Bit mask of TME field.
	FDCAN1_FDCAN_TTTMC_TME_Msk = 0x7f0000

	// FDCAN_TTRMC: FDCAN TT reference message configuration register
	// Position of RID field.
	FDCAN1_FDCAN_TTRMC_RID_Pos = 0x0
	// Bit mask of RID field.
	FDCAN1_FDCAN_TTRMC_RID_Msk = 0x1fffffff
	// Position of XTD field.
	FDCAN1_FDCAN_TTRMC_XTD_Pos = 0x1e
	// Bit mask of XTD field.
	FDCAN1_FDCAN_TTRMC_XTD_Msk = 0x40000000
	// Bit XTD.
	FDCAN1_FDCAN_TTRMC_XTD = 0x40000000
	// Position of RMPS field.
	FDCAN1_FDCAN_TTRMC_RMPS_Pos = 0x1f
	// Bit mask of RMPS field.
	FDCAN1_FDCAN_TTRMC_RMPS_Msk = 0x80000000
	// Bit RMPS.
	FDCAN1_FDCAN_TTRMC_RMPS = 0x80000000

	// FDCAN_TTOCF: FDCAN TT operation configuration register
	// Position of OM field.
	FDCAN1_FDCAN_TTOCF_OM_Pos = 0x0
	// Bit mask of OM field.
	FDCAN1_FDCAN_TTOCF_OM_Msk = 0x3
	// Position of GEN field.
	FDCAN1_FDCAN_TTOCF_GEN_Pos = 0x3
	// Bit mask of GEN field.
	FDCAN1_FDCAN_TTOCF_GEN_Msk = 0x8
	// Bit GEN.
	FDCAN1_FDCAN_TTOCF_GEN = 0x8
	// Position of TM field.
	FDCAN1_FDCAN_TTOCF_TM_Pos = 0x4
	// Bit mask of TM field.
	FDCAN1_FDCAN_TTOCF_TM_Msk = 0x10
	// Bit TM.
	FDCAN1_FDCAN_TTOCF_TM = 0x10
	// Position of LDSDL field.
	FDCAN1_FDCAN_TTOCF_LDSDL_Pos = 0x5
	// Bit mask of LDSDL field.
	FDCAN1_FDCAN_TTOCF_LDSDL_Msk = 0xe0
	// Position of IRTO field.
	FDCAN1_FDCAN_TTOCF_IRTO_Pos = 0x8
	// Bit mask of IRTO field.
	FDCAN1_FDCAN_TTOCF_IRTO_Msk = 0x7f00
	// Position of EECS field.
	FDCAN1_FDCAN_TTOCF_EECS_Pos = 0xf
	// Bit mask of EECS field.
	FDCAN1_FDCAN_TTOCF_EECS_Msk = 0x8000
	// Bit EECS.
	FDCAN1_FDCAN_TTOCF_EECS = 0x8000
	// Position of AWL field.
	FDCAN1_FDCAN_TTOCF_AWL_Pos = 0x10
	// Bit mask of AWL field.
	FDCAN1_FDCAN_TTOCF_AWL_Msk = 0xff0000
	// Position of EGTF field.
	FDCAN1_FDCAN_TTOCF_EGTF_Pos = 0x18
	// Bit mask of EGTF field.
	FDCAN1_FDCAN_TTOCF_EGTF_Msk = 0x1000000
	// Bit EGTF.
	FDCAN1_FDCAN_TTOCF_EGTF = 0x1000000
	// Position of ECC field.
	FDCAN1_FDCAN_TTOCF_ECC_Pos = 0x19
	// Bit mask of ECC field.
	FDCAN1_FDCAN_TTOCF_ECC_Msk = 0x2000000
	// Bit ECC.
	FDCAN1_FDCAN_TTOCF_ECC = 0x2000000
	// Position of EVTP field.
	FDCAN1_FDCAN_TTOCF_EVTP_Pos = 0x1a
	// Bit mask of EVTP field.
	FDCAN1_FDCAN_TTOCF_EVTP_Msk = 0x4000000
	// Bit EVTP.
	FDCAN1_FDCAN_TTOCF_EVTP = 0x4000000

	// FDCAN_TTMLM: FDCAN TT matrix limits register
	// Position of CCM field.
	FDCAN1_FDCAN_TTMLM_CCM_Pos = 0x0
	// Bit mask of CCM field.
	FDCAN1_FDCAN_TTMLM_CCM_Msk = 0x3f
	// Position of CSS field.
	FDCAN1_FDCAN_TTMLM_CSS_Pos = 0x6
	// Bit mask of CSS field.
	FDCAN1_FDCAN_TTMLM_CSS_Msk = 0xc0
	// Position of TXEW field.
	FDCAN1_FDCAN_TTMLM_TXEW_Pos = 0x8
	// Bit mask of TXEW field.
	FDCAN1_FDCAN_TTMLM_TXEW_Msk = 0xf00
	// Position of ENTT field.
	FDCAN1_FDCAN_TTMLM_ENTT_Pos = 0x10
	// Bit mask of ENTT field.
	FDCAN1_FDCAN_TTMLM_ENTT_Msk = 0xfff0000

	// FDCAN_TURCF: The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process.
	// Position of NCL field.
	FDCAN1_FDCAN_TURCF_NCL_Pos = 0x0
	// Bit mask of NCL field.
	FDCAN1_FDCAN_TURCF_NCL_Msk = 0xffff
	// Position of DC field.
	FDCAN1_FDCAN_TURCF_DC_Pos = 0x10
	// Bit mask of DC field.
	FDCAN1_FDCAN_TURCF_DC_Msk = 0x3fff0000
	// Position of ELT field.
	FDCAN1_FDCAN_TURCF_ELT_Pos = 0x1f
	// Bit mask of ELT field.
	FDCAN1_FDCAN_TURCF_ELT_Msk = 0x80000000
	// Bit ELT.
	FDCAN1_FDCAN_TURCF_ELT = 0x80000000

	// FDCAN_TTOCN: FDCAN TT operation control register
	// Position of SGT field.
	FDCAN1_FDCAN_TTOCN_SGT_Pos = 0x0
	// Bit mask of SGT field.
	FDCAN1_FDCAN_TTOCN_SGT_Msk = 0x1
	// Bit SGT.
	FDCAN1_FDCAN_TTOCN_SGT = 0x1
	// Position of ECS field.
	FDCAN1_FDCAN_TTOCN_ECS_Pos = 0x1
	// Bit mask of ECS field.
	FDCAN1_FDCAN_TTOCN_ECS_Msk = 0x2
	// Bit ECS.
	FDCAN1_FDCAN_TTOCN_ECS = 0x2
	// Position of SWP field.
	FDCAN1_FDCAN_TTOCN_SWP_Pos = 0x2
	// Bit mask of SWP field.
	FDCAN1_FDCAN_TTOCN_SWP_Msk = 0x4
	// Bit SWP.
	FDCAN1_FDCAN_TTOCN_SWP = 0x4
	// Position of SWS field.
	FDCAN1_FDCAN_TTOCN_SWS_Pos = 0x3
	// Bit mask of SWS field.
	FDCAN1_FDCAN_TTOCN_SWS_Msk = 0x18
	// Position of RTIE field.
	FDCAN1_FDCAN_TTOCN_RTIE_Pos = 0x5
	// Bit mask of RTIE field.
	FDCAN1_FDCAN_TTOCN_RTIE_Msk = 0x20
	// Bit RTIE.
	FDCAN1_FDCAN_TTOCN_RTIE = 0x20
	// Position of TMC field.
	FDCAN1_FDCAN_TTOCN_TMC_Pos = 0x6
	// Bit mask of TMC field.
	FDCAN1_FDCAN_TTOCN_TMC_Msk = 0xc0
	// Position of TTIE field.
	FDCAN1_FDCAN_TTOCN_TTIE_Pos = 0x8
	// Bit mask of TTIE field.
	FDCAN1_FDCAN_TTOCN_TTIE_Msk = 0x100
	// Bit TTIE.
	FDCAN1_FDCAN_TTOCN_TTIE = 0x100
	// Position of GCS field.
	FDCAN1_FDCAN_TTOCN_GCS_Pos = 0x9
	// Bit mask of GCS field.
	FDCAN1_FDCAN_TTOCN_GCS_Msk = 0x200
	// Bit GCS.
	FDCAN1_FDCAN_TTOCN_GCS = 0x200
	// Position of FGP field.
	FDCAN1_FDCAN_TTOCN_FGP_Pos = 0xa
	// Bit mask of FGP field.
	FDCAN1_FDCAN_TTOCN_FGP_Msk = 0x400
	// Bit FGP.
	FDCAN1_FDCAN_TTOCN_FGP = 0x400
	// Position of TMG field.
	FDCAN1_FDCAN_TTOCN_TMG_Pos = 0xb
	// Bit mask of TMG field.
	FDCAN1_FDCAN_TTOCN_TMG_Msk = 0x800
	// Bit TMG.
	FDCAN1_FDCAN_TTOCN_TMG = 0x800
	// Position of NIG field.
	FDCAN1_FDCAN_TTOCN_NIG_Pos = 0xc
	// Bit mask of NIG field.
	FDCAN1_FDCAN_TTOCN_NIG_Msk = 0x1000
	// Bit NIG.
	FDCAN1_FDCAN_TTOCN_NIG = 0x1000
	// Position of ESCN field.
	FDCAN1_FDCAN_TTOCN_ESCN_Pos = 0xd
	// Bit mask of ESCN field.
	FDCAN1_FDCAN_TTOCN_ESCN_Msk = 0x2000
	// Bit ESCN.
	FDCAN1_FDCAN_TTOCN_ESCN = 0x2000
	// Position of LCKC field.
	FDCAN1_FDCAN_TTOCN_LCKC_Pos = 0xf
	// Bit mask of LCKC field.
	FDCAN1_FDCAN_TTOCN_LCKC_Msk = 0x8000
	// Bit LCKC.
	FDCAN1_FDCAN_TTOCN_LCKC = 0x8000

	// FDCAN_TTGTP: If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master.
	// Position of TP field.
	FDCAN1_FDCAN_TTGTP_TP_Pos = 0x0
	// Bit mask of TP field.
	FDCAN1_FDCAN_TTGTP_TP_Msk = 0xffff
	// Position of CTP field.
	FDCAN1_FDCAN_TTGTP_CTP_Pos = 0x10
	// Bit mask of CTP field.
	FDCAN1_FDCAN_TTGTP_CTP_Msk = 0xffff0000

	// FDCAN_TTTMK: A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM.
	// Position of TM field.
	FDCAN1_FDCAN_TTTMK_TM_Pos = 0x0
	// Bit mask of TM field.
	FDCAN1_FDCAN_TTTMK_TM_Msk = 0xffff
	// Position of TICC field.
	FDCAN1_FDCAN_TTTMK_TICC_Pos = 0x10
	// Bit mask of TICC field.
	FDCAN1_FDCAN_TTTMK_TICC_Msk = 0x7f0000
	// Position of LCKM field.
	FDCAN1_FDCAN_TTTMK_LCKM_Pos = 0x1f
	// Bit mask of LCKM field.
	FDCAN1_FDCAN_TTTMK_LCKM_Msk = 0x80000000
	// Bit LCKM.
	FDCAN1_FDCAN_TTTMK_LCKM = 0x80000000

	// FDCAN_TTIR: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.
	// Position of SBC field.
	FDCAN1_FDCAN_TTIR_SBC_Pos = 0x0
	// Bit mask of SBC field.
	FDCAN1_FDCAN_TTIR_SBC_Msk = 0x1
	// Bit SBC.
	FDCAN1_FDCAN_TTIR_SBC = 0x1
	// Position of SMC field.
	FDCAN1_FDCAN_TTIR_SMC_Pos = 0x1
	// Bit mask of SMC field.
	FDCAN1_FDCAN_TTIR_SMC_Msk = 0x2
	// Bit SMC.
	FDCAN1_FDCAN_TTIR_SMC = 0x2
	// Position of CSM field.
	FDCAN1_FDCAN_TTIR_CSM_Pos = 0x2
	// Bit mask of CSM field.
	FDCAN1_FDCAN_TTIR_CSM_Msk = 0x4
	// Bit CSM.
	FDCAN1_FDCAN_TTIR_CSM = 0x4
	// Position of SOG field.
	FDCAN1_FDCAN_TTIR_SOG_Pos = 0x3
	// Bit mask of SOG field.
	FDCAN1_FDCAN_TTIR_SOG_Msk = 0x8
	// Bit SOG.
	FDCAN1_FDCAN_TTIR_SOG = 0x8
	// Position of RTMI field.
	FDCAN1_FDCAN_TTIR_RTMI_Pos = 0x4
	// Bit mask of RTMI field.
	FDCAN1_FDCAN_TTIR_RTMI_Msk = 0x10
	// Bit RTMI.
	FDCAN1_FDCAN_TTIR_RTMI = 0x10
	// Position of TTMI field.
	FDCAN1_FDCAN_TTIR_TTMI_Pos = 0x5
	// Bit mask of TTMI field.
	FDCAN1_FDCAN_TTIR_TTMI_Msk = 0x20
	// Bit TTMI.
	FDCAN1_FDCAN_TTIR_TTMI = 0x20
	// Position of SWE field.
	FDCAN1_FDCAN_TTIR_SWE_Pos = 0x6
	// Bit mask of SWE field.
	FDCAN1_FDCAN_TTIR_SWE_Msk = 0x40
	// Bit SWE.
	FDCAN1_FDCAN_TTIR_SWE = 0x40
	// Position of GTW field.
	FDCAN1_FDCAN_TTIR_GTW_Pos = 0x7
	// Bit mask of GTW field.
	FDCAN1_FDCAN_TTIR_GTW_Msk = 0x80
	// Bit GTW.
	FDCAN1_FDCAN_TTIR_GTW = 0x80
	// Position of GTD field.
	FDCAN1_FDCAN_TTIR_GTD_Pos = 0x8
	// Bit mask of GTD field.
	FDCAN1_FDCAN_TTIR_GTD_Msk = 0x100
	// Bit GTD.
	FDCAN1_FDCAN_TTIR_GTD = 0x100
	// Position of GTE field.
	FDCAN1_FDCAN_TTIR_GTE_Pos = 0x9
	// Bit mask of GTE field.
	FDCAN1_FDCAN_TTIR_GTE_Msk = 0x200
	// Bit GTE.
	FDCAN1_FDCAN_TTIR_GTE = 0x200
	// Position of TXU field.
	FDCAN1_FDCAN_TTIR_TXU_Pos = 0xa
	// Bit mask of TXU field.
	FDCAN1_FDCAN_TTIR_TXU_Msk = 0x400
	// Bit TXU.
	FDCAN1_FDCAN_TTIR_TXU = 0x400
	// Position of TXO field.
	FDCAN1_FDCAN_TTIR_TXO_Pos = 0xb
	// Bit mask of TXO field.
	FDCAN1_FDCAN_TTIR_TXO_Msk = 0x800
	// Bit TXO.
	FDCAN1_FDCAN_TTIR_TXO = 0x800
	// Position of SE1 field.
	FDCAN1_FDCAN_TTIR_SE1_Pos = 0xc
	// Bit mask of SE1 field.
	FDCAN1_FDCAN_TTIR_SE1_Msk = 0x1000
	// Bit SE1.
	FDCAN1_FDCAN_TTIR_SE1 = 0x1000
	// Position of SE2 field.
	FDCAN1_FDCAN_TTIR_SE2_Pos = 0xd
	// Bit mask of SE2 field.
	FDCAN1_FDCAN_TTIR_SE2_Msk = 0x2000
	// Bit SE2.
	FDCAN1_FDCAN_TTIR_SE2 = 0x2000
	// Position of ELC field.
	FDCAN1_FDCAN_TTIR_ELC_Pos = 0xe
	// Bit mask of ELC field.
	FDCAN1_FDCAN_TTIR_ELC_Msk = 0x4000
	// Bit ELC.
	FDCAN1_FDCAN_TTIR_ELC = 0x4000
	// Position of IWTG field.
	FDCAN1_FDCAN_TTIR_IWTG_Pos = 0xf
	// Bit mask of IWTG field.
	FDCAN1_FDCAN_TTIR_IWTG_Msk = 0x8000
	// Bit IWTG.
	FDCAN1_FDCAN_TTIR_IWTG = 0x8000
	// Position of WT field.
	FDCAN1_FDCAN_TTIR_WT_Pos = 0x10
	// Bit mask of WT field.
	FDCAN1_FDCAN_TTIR_WT_Msk = 0x10000
	// Bit WT.
	FDCAN1_FDCAN_TTIR_WT = 0x10000
	// Position of AW field.
	FDCAN1_FDCAN_TTIR_AW_Pos = 0x11
	// Bit mask of AW field.
	FDCAN1_FDCAN_TTIR_AW_Msk = 0x20000
	// Bit AW.
	FDCAN1_FDCAN_TTIR_AW = 0x20000
	// Position of CER field.
	FDCAN1_FDCAN_TTIR_CER_Pos = 0x12
	// Bit mask of CER field.
	FDCAN1_FDCAN_TTIR_CER_Msk = 0x40000
	// Bit CER.
	FDCAN1_FDCAN_TTIR_CER = 0x40000

	// FDCAN_TTIE: The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt.
	// Position of SBCE field.
	FDCAN1_FDCAN_TTIE_SBCE_Pos = 0x0
	// Bit mask of SBCE field.
	FDCAN1_FDCAN_TTIE_SBCE_Msk = 0x1
	// Bit SBCE.
	FDCAN1_FDCAN_TTIE_SBCE = 0x1
	// Position of SMCE field.
	FDCAN1_FDCAN_TTIE_SMCE_Pos = 0x1
	// Bit mask of SMCE field.
	FDCAN1_FDCAN_TTIE_SMCE_Msk = 0x2
	// Bit SMCE.
	FDCAN1_FDCAN_TTIE_SMCE = 0x2
	// Position of CSME field.
	FDCAN1_FDCAN_TTIE_CSME_Pos = 0x2
	// Bit mask of CSME field.
	FDCAN1_FDCAN_TTIE_CSME_Msk = 0x4
	// Bit CSME.
	FDCAN1_FDCAN_TTIE_CSME = 0x4
	// Position of SOGE field.
	FDCAN1_FDCAN_TTIE_SOGE_Pos = 0x3
	// Bit mask of SOGE field.
	FDCAN1_FDCAN_TTIE_SOGE_Msk = 0x8
	// Bit SOGE.
	FDCAN1_FDCAN_TTIE_SOGE = 0x8
	// Position of RTMIE field.
	FDCAN1_FDCAN_TTIE_RTMIE_Pos = 0x4
	// Bit mask of RTMIE field.
	FDCAN1_FDCAN_TTIE_RTMIE_Msk = 0x10
	// Bit RTMIE.
	FDCAN1_FDCAN_TTIE_RTMIE = 0x10
	// Position of TTMIE field.
	FDCAN1_FDCAN_TTIE_TTMIE_Pos = 0x5
	// Bit mask of TTMIE field.
	FDCAN1_FDCAN_TTIE_TTMIE_Msk = 0x20
	// Bit TTMIE.
	FDCAN1_FDCAN_TTIE_TTMIE = 0x20
	// Position of SWEE field.
	FDCAN1_FDCAN_TTIE_SWEE_Pos = 0x6
	// Bit mask of SWEE field.
	FDCAN1_FDCAN_TTIE_SWEE_Msk = 0x40
	// Bit SWEE.
	FDCAN1_FDCAN_TTIE_SWEE = 0x40
	// Position of GTWE field.
	FDCAN1_FDCAN_TTIE_GTWE_Pos = 0x7
	// Bit mask of GTWE field.
	FDCAN1_FDCAN_TTIE_GTWE_Msk = 0x80
	// Bit GTWE.
	FDCAN1_FDCAN_TTIE_GTWE = 0x80
	// Position of GTDE field.
	FDCAN1_FDCAN_TTIE_GTDE_Pos = 0x8
	// Bit mask of GTDE field.
	FDCAN1_FDCAN_TTIE_GTDE_Msk = 0x100
	// Bit GTDE.
	FDCAN1_FDCAN_TTIE_GTDE = 0x100
	// Position of GTEE field.
	FDCAN1_FDCAN_TTIE_GTEE_Pos = 0x9
	// Bit mask of GTEE field.
	FDCAN1_FDCAN_TTIE_GTEE_Msk = 0x200
	// Bit GTEE.
	FDCAN1_FDCAN_TTIE_GTEE = 0x200
	// Position of TXUE field.
	FDCAN1_FDCAN_TTIE_TXUE_Pos = 0xa
	// Bit mask of TXUE field.
	FDCAN1_FDCAN_TTIE_TXUE_Msk = 0x400
	// Bit TXUE.
	FDCAN1_FDCAN_TTIE_TXUE = 0x400
	// Position of TXOE field.
	FDCAN1_FDCAN_TTIE_TXOE_Pos = 0xb
	// Bit mask of TXOE field.
	FDCAN1_FDCAN_TTIE_TXOE_Msk = 0x800
	// Bit TXOE.
	FDCAN1_FDCAN_TTIE_TXOE = 0x800
	// Position of SE1E field.
	FDCAN1_FDCAN_TTIE_SE1E_Pos = 0xc
	// Bit mask of SE1E field.
	FDCAN1_FDCAN_TTIE_SE1E_Msk = 0x1000
	// Bit SE1E.
	FDCAN1_FDCAN_TTIE_SE1E = 0x1000
	// Position of SE2E field.
	FDCAN1_FDCAN_TTIE_SE2E_Pos = 0xd
	// Bit mask of SE2E field.
	FDCAN1_FDCAN_TTIE_SE2E_Msk = 0x2000
	// Bit SE2E.
	FDCAN1_FDCAN_TTIE_SE2E = 0x2000
	// Position of ELCE field.
	FDCAN1_FDCAN_TTIE_ELCE_Pos = 0xe
	// Bit mask of ELCE field.
	FDCAN1_FDCAN_TTIE_ELCE_Msk = 0x4000
	// Bit ELCE.
	FDCAN1_FDCAN_TTIE_ELCE = 0x4000
	// Position of IWTE field.
	FDCAN1_FDCAN_TTIE_IWTE_Pos = 0xf
	// Bit mask of IWTE field.
	FDCAN1_FDCAN_TTIE_IWTE_Msk = 0x8000
	// Bit IWTE.
	FDCAN1_FDCAN_TTIE_IWTE = 0x8000
	// Position of WTE field.
	FDCAN1_FDCAN_TTIE_WTE_Pos = 0x10
	// Bit mask of WTE field.
	FDCAN1_FDCAN_TTIE_WTE_Msk = 0x10000
	// Bit WTE.
	FDCAN1_FDCAN_TTIE_WTE = 0x10000
	// Position of AWE field.
	FDCAN1_FDCAN_TTIE_AWE_Pos = 0x11
	// Bit mask of AWE field.
	FDCAN1_FDCAN_TTIE_AWE_Msk = 0x20000
	// Bit AWE.
	FDCAN1_FDCAN_TTIE_AWE = 0x20000
	// Position of CERE field.
	FDCAN1_FDCAN_TTIE_CERE_Pos = 0x12
	// Bit mask of CERE field.
	FDCAN1_FDCAN_TTIE_CERE_Msk = 0x40000
	// Bit CERE.
	FDCAN1_FDCAN_TTIE_CERE = 0x40000

	// FDCAN_TTILS: The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.
	// Position of SBCL field.
	FDCAN1_FDCAN_TTILS_SBCL_Pos = 0x0
	// Bit mask of SBCL field.
	FDCAN1_FDCAN_TTILS_SBCL_Msk = 0x1
	// Bit SBCL.
	FDCAN1_FDCAN_TTILS_SBCL = 0x1
	// Position of SMCL field.
	FDCAN1_FDCAN_TTILS_SMCL_Pos = 0x1
	// Bit mask of SMCL field.
	FDCAN1_FDCAN_TTILS_SMCL_Msk = 0x2
	// Bit SMCL.
	FDCAN1_FDCAN_TTILS_SMCL = 0x2
	// Position of CSML field.
	FDCAN1_FDCAN_TTILS_CSML_Pos = 0x2
	// Bit mask of CSML field.
	FDCAN1_FDCAN_TTILS_CSML_Msk = 0x4
	// Bit CSML.
	FDCAN1_FDCAN_TTILS_CSML = 0x4
	// Position of SOGL field.
	FDCAN1_FDCAN_TTILS_SOGL_Pos = 0x3
	// Bit mask of SOGL field.
	FDCAN1_FDCAN_TTILS_SOGL_Msk = 0x8
	// Bit SOGL.
	FDCAN1_FDCAN_TTILS_SOGL = 0x8
	// Position of RTMIL field.
	FDCAN1_FDCAN_TTILS_RTMIL_Pos = 0x4
	// Bit mask of RTMIL field.
	FDCAN1_FDCAN_TTILS_RTMIL_Msk = 0x10
	// Bit RTMIL.
	FDCAN1_FDCAN_TTILS_RTMIL = 0x10
	// Position of TTMIL field.
	FDCAN1_FDCAN_TTILS_TTMIL_Pos = 0x5
	// Bit mask of TTMIL field.
	FDCAN1_FDCAN_TTILS_TTMIL_Msk = 0x20
	// Bit TTMIL.
	FDCAN1_FDCAN_TTILS_TTMIL = 0x20
	// Position of SWEL field.
	FDCAN1_FDCAN_TTILS_SWEL_Pos = 0x6
	// Bit mask of SWEL field.
	FDCAN1_FDCAN_TTILS_SWEL_Msk = 0x40
	// Bit SWEL.
	FDCAN1_FDCAN_TTILS_SWEL = 0x40
	// Position of GTWL field.
	FDCAN1_FDCAN_TTILS_GTWL_Pos = 0x7
	// Bit mask of GTWL field.
	FDCAN1_FDCAN_TTILS_GTWL_Msk = 0x80
	// Bit GTWL.
	FDCAN1_FDCAN_TTILS_GTWL = 0x80
	// Position of GTDL field.
	FDCAN1_FDCAN_TTILS_GTDL_Pos = 0x8
	// Bit mask of GTDL field.
	FDCAN1_FDCAN_TTILS_GTDL_Msk = 0x100
	// Bit GTDL.
	FDCAN1_FDCAN_TTILS_GTDL = 0x100
	// Position of GTEL field.
	FDCAN1_FDCAN_TTILS_GTEL_Pos = 0x9
	// Bit mask of GTEL field.
	FDCAN1_FDCAN_TTILS_GTEL_Msk = 0x200
	// Bit GTEL.
	FDCAN1_FDCAN_TTILS_GTEL = 0x200
	// Position of TXUL field.
	FDCAN1_FDCAN_TTILS_TXUL_Pos = 0xa
	// Bit mask of TXUL field.
	FDCAN1_FDCAN_TTILS_TXUL_Msk = 0x400
	// Bit TXUL.
	FDCAN1_FDCAN_TTILS_TXUL = 0x400
	// Position of TXOL field.
	FDCAN1_FDCAN_TTILS_TXOL_Pos = 0xb
	// Bit mask of TXOL field.
	FDCAN1_FDCAN_TTILS_TXOL_Msk = 0x800
	// Bit TXOL.
	FDCAN1_FDCAN_TTILS_TXOL = 0x800
	// Position of SE1L field.
	FDCAN1_FDCAN_TTILS_SE1L_Pos = 0xc
	// Bit mask of SE1L field.
	FDCAN1_FDCAN_TTILS_SE1L_Msk = 0x1000
	// Bit SE1L.
	FDCAN1_FDCAN_TTILS_SE1L = 0x1000
	// Position of SE2L field.
	FDCAN1_FDCAN_TTILS_SE2L_Pos = 0xd
	// Bit mask of SE2L field.
	FDCAN1_FDCAN_TTILS_SE2L_Msk = 0x2000
	// Bit SE2L.
	FDCAN1_FDCAN_TTILS_SE2L = 0x2000
	// Position of ELCL field.
	FDCAN1_FDCAN_TTILS_ELCL_Pos = 0xe
	// Bit mask of ELCL field.
	FDCAN1_FDCAN_TTILS_ELCL_Msk = 0x4000
	// Bit ELCL.
	FDCAN1_FDCAN_TTILS_ELCL = 0x4000
	// Position of IWTL field.
	FDCAN1_FDCAN_TTILS_IWTL_Pos = 0xf
	// Bit mask of IWTL field.
	FDCAN1_FDCAN_TTILS_IWTL_Msk = 0x8000
	// Bit IWTL.
	FDCAN1_FDCAN_TTILS_IWTL = 0x8000
	// Position of WTL field.
	FDCAN1_FDCAN_TTILS_WTL_Pos = 0x10
	// Bit mask of WTL field.
	FDCAN1_FDCAN_TTILS_WTL_Msk = 0x10000
	// Bit WTL.
	FDCAN1_FDCAN_TTILS_WTL = 0x10000
	// Position of AWL field.
	FDCAN1_FDCAN_TTILS_AWL_Pos = 0x11
	// Bit mask of AWL field.
	FDCAN1_FDCAN_TTILS_AWL_Msk = 0x20000
	// Bit AWL.
	FDCAN1_FDCAN_TTILS_AWL = 0x20000
	// Position of CERL field.
	FDCAN1_FDCAN_TTILS_CERL_Pos = 0x12
	// Bit mask of CERL field.
	FDCAN1_FDCAN_TTILS_CERL_Msk = 0x40000
	// Bit CERL.
	FDCAN1_FDCAN_TTILS_CERL = 0x40000

	// FDCAN_TTOST: FDCAN TT operation status register
	// Position of EL field.
	FDCAN1_FDCAN_TTOST_EL_Pos = 0x0
	// Bit mask of EL field.
	FDCAN1_FDCAN_TTOST_EL_Msk = 0x3
	// Position of MS field.
	FDCAN1_FDCAN_TTOST_MS_Pos = 0x2
	// Bit mask of MS field.
	FDCAN1_FDCAN_TTOST_MS_Msk = 0xc
	// Position of SYS field.
	FDCAN1_FDCAN_TTOST_SYS_Pos = 0x4
	// Bit mask of SYS field.
	FDCAN1_FDCAN_TTOST_SYS_Msk = 0x30
	// Position of QGTP field.
	FDCAN1_FDCAN_TTOST_QGTP_Pos = 0x6
	// Bit mask of QGTP field.
	FDCAN1_FDCAN_TTOST_QGTP_Msk = 0x40
	// Bit QGTP.
	FDCAN1_FDCAN_TTOST_QGTP = 0x40
	// Position of QCS field.
	FDCAN1_FDCAN_TTOST_QCS_Pos = 0x7
	// Bit mask of QCS field.
	FDCAN1_FDCAN_TTOST_QCS_Msk = 0x80
	// Bit QCS.
	FDCAN1_FDCAN_TTOST_QCS = 0x80
	// Position of RTO field.
	FDCAN1_FDCAN_TTOST_RTO_Pos = 0x8
	// Bit mask of RTO field.
	FDCAN1_FDCAN_TTOST_RTO_Msk = 0xff00
	// Position of WGTD field.
	FDCAN1_FDCAN_TTOST_WGTD_Pos = 0x16
	// Bit mask of WGTD field.
	FDCAN1_FDCAN_TTOST_WGTD_Msk = 0x400000
	// Bit WGTD.
	FDCAN1_FDCAN_TTOST_WGTD = 0x400000
	// Position of GFI field.
	FDCAN1_FDCAN_TTOST_GFI_Pos = 0x17
	// Bit mask of GFI field.
	FDCAN1_FDCAN_TTOST_GFI_Msk = 0x800000
	// Bit GFI.
	FDCAN1_FDCAN_TTOST_GFI = 0x800000
	// Position of TMP field.
	FDCAN1_FDCAN_TTOST_TMP_Pos = 0x18
	// Bit mask of TMP field.
	FDCAN1_FDCAN_TTOST_TMP_Msk = 0x7000000
	// Position of GSI field.
	FDCAN1_FDCAN_TTOST_GSI_Pos = 0x1b
	// Bit mask of GSI field.
	FDCAN1_FDCAN_TTOST_GSI_Msk = 0x8000000
	// Bit GSI.
	FDCAN1_FDCAN_TTOST_GSI = 0x8000000
	// Position of WFE field.
	FDCAN1_FDCAN_TTOST_WFE_Pos = 0x1c
	// Bit mask of WFE field.
	FDCAN1_FDCAN_TTOST_WFE_Msk = 0x10000000
	// Bit WFE.
	FDCAN1_FDCAN_TTOST_WFE = 0x10000000
	// Position of AWE field.
	FDCAN1_FDCAN_TTOST_AWE_Pos = 0x1d
	// Bit mask of AWE field.
	FDCAN1_FDCAN_TTOST_AWE_Msk = 0x20000000
	// Bit AWE.
	FDCAN1_FDCAN_TTOST_AWE = 0x20000000
	// Position of WECS field.
	FDCAN1_FDCAN_TTOST_WECS_Pos = 0x1e
	// Bit mask of WECS field.
	FDCAN1_FDCAN_TTOST_WECS_Msk = 0x40000000
	// Bit WECS.
	FDCAN1_FDCAN_TTOST_WECS = 0x40000000
	// Position of SPL field.
	FDCAN1_FDCAN_TTOST_SPL_Pos = 0x1f
	// Bit mask of SPL field.
	FDCAN1_FDCAN_TTOST_SPL_Msk = 0x80000000
	// Bit SPL.
	FDCAN1_FDCAN_TTOST_SPL = 0x80000000

	// FDCAN_TURNA: There is no drift compensation in TTCAN level 1.
	// Position of NAV field.
	FDCAN1_FDCAN_TURNA_NAV_Pos = 0x0
	// Bit mask of NAV field.
	FDCAN1_FDCAN_TURNA_NAV_Msk = 0x3ffff

	// FDCAN_TTLGT: FDCAN TT local and global time register
	// Position of LT field.
	FDCAN1_FDCAN_TTLGT_LT_Pos = 0x0
	// Bit mask of LT field.
	FDCAN1_FDCAN_TTLGT_LT_Msk = 0xffff
	// Position of GT field.
	FDCAN1_FDCAN_TTLGT_GT_Pos = 0x10
	// Bit mask of GT field.
	FDCAN1_FDCAN_TTLGT_GT_Msk = 0xffff0000

	// FDCAN_TTCTC: FDCAN TT cycle time and count register
	// Position of CT field.
	FDCAN1_FDCAN_TTCTC_CT_Pos = 0x0
	// Bit mask of CT field.
	FDCAN1_FDCAN_TTCTC_CT_Msk = 0xffff
	// Position of CC field.
	FDCAN1_FDCAN_TTCTC_CC_Pos = 0x10
	// Bit mask of CC field.
	FDCAN1_FDCAN_TTCTC_CC_Msk = 0x3f0000

	// FDCAN_TTCPT: FDCAN TT capture time register
	// Position of CCV field.
	FDCAN1_FDCAN_TTCPT_CCV_Pos = 0x0
	// Bit mask of CCV field.
	FDCAN1_FDCAN_TTCPT_CCV_Msk = 0x3f
	// Position of SWV field.
	FDCAN1_FDCAN_TTCPT_SWV_Pos = 0x10
	// Bit mask of SWV field.
	FDCAN1_FDCAN_TTCPT_SWV_Msk = 0xffff0000

	// FDCAN_TTCSM: FDCAN TT cycle sync mark register
	// Position of CSM field.
	FDCAN1_FDCAN_TTCSM_CSM_Pos = 0x0
	// Bit mask of CSM field.
	FDCAN1_FDCAN_TTCSM_CSM_Msk = 0xffff

	// FDCAN_TTTS: The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger.
	// Position of SWTDEL field.
	FDCAN1_FDCAN_TTTS_SWTDEL_Pos = 0x0
	// Bit mask of SWTDEL field.
	FDCAN1_FDCAN_TTTS_SWTDEL_Msk = 0x3
	// Position of EVTSEL field.
	FDCAN1_FDCAN_TTTS_EVTSEL_Pos = 0x4
	// Bit mask of EVTSEL field.
	FDCAN1_FDCAN_TTTS_EVTSEL_Msk = 0x30
)

// Bitfields for FMC: FMC register block
const (
	// FMC_BCR1: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_FMC_BCR1_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_FMC_BCR1_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_FMC_BCR1_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_FMC_BCR1_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_FMC_BCR1_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_FMC_BCR1_MUXEN = 0x2
	// Position of MTYP field.
	FMC_FMC_BCR1_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_FMC_BCR1_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_FMC_BCR1_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_FMC_BCR1_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_FMC_BCR1_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_FMC_BCR1_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_FMC_BCR1_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_FMC_BCR1_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_FMC_BCR1_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_FMC_BCR1_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_FMC_BCR1_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_FMC_BCR1_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_FMC_BCR1_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_FMC_BCR1_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_FMC_BCR1_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_FMC_BCR1_WAITCFG = 0x800
	// Position of WREN field.
	FMC_FMC_BCR1_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_FMC_BCR1_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_FMC_BCR1_WREN = 0x1000
	// Position of WAITEN field.
	FMC_FMC_BCR1_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_FMC_BCR1_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_FMC_BCR1_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_FMC_BCR1_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_FMC_BCR1_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_FMC_BCR1_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_FMC_BCR1_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_FMC_BCR1_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_FMC_BCR1_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_FMC_BCR1_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_FMC_BCR1_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_FMC_BCR1_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_FMC_BCR1_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_FMC_BCR1_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_FMC_BCR1_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_FMC_BCR1_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_FMC_BCR1_CCLKEN = 0x100000
	// Position of NBLSET field.
	FMC_FMC_BCR1_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_FMC_BCR1_NBLSET_Msk = 0xc00000
	// Position of FMCEN field.
	FMC_FMC_BCR1_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_FMC_BCR1_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_FMC_BCR1_FMCEN = 0x80000000

	// FMC_BTR1: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_FMC_BTR1_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BTR1_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BTR1_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BTR1_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BTR1_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BTR1_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BTR1_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BTR1_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_FMC_BTR1_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_FMC_BTR1_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_FMC_BTR1_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_FMC_BTR1_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_FMC_BTR1_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BTR1_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BTR1_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BTR1_DATAHLD_Msk = 0xc0000000

	// FMC_BCR2: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_FMC_BCR2_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_FMC_BCR2_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_FMC_BCR2_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_FMC_BCR2_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_FMC_BCR2_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_FMC_BCR2_MUXEN = 0x2
	// Position of MTYP field.
	FMC_FMC_BCR2_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_FMC_BCR2_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_FMC_BCR2_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_FMC_BCR2_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_FMC_BCR2_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_FMC_BCR2_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_FMC_BCR2_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_FMC_BCR2_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_FMC_BCR2_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_FMC_BCR2_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_FMC_BCR2_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_FMC_BCR2_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_FMC_BCR2_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_FMC_BCR2_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_FMC_BCR2_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_FMC_BCR2_WAITCFG = 0x800
	// Position of WREN field.
	FMC_FMC_BCR2_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_FMC_BCR2_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_FMC_BCR2_WREN = 0x1000
	// Position of WAITEN field.
	FMC_FMC_BCR2_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_FMC_BCR2_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_FMC_BCR2_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_FMC_BCR2_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_FMC_BCR2_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_FMC_BCR2_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_FMC_BCR2_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_FMC_BCR2_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_FMC_BCR2_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_FMC_BCR2_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_FMC_BCR2_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_FMC_BCR2_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_FMC_BCR2_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_FMC_BCR2_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_FMC_BCR2_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_FMC_BCR2_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_FMC_BCR2_CCLKEN = 0x100000
	// Position of NBLSET field.
	FMC_FMC_BCR2_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_FMC_BCR2_NBLSET_Msk = 0xc00000
	// Position of FMCEN field.
	FMC_FMC_BCR2_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_FMC_BCR2_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_FMC_BCR2_FMCEN = 0x80000000

	// FMC_BTR2: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_FMC_BTR2_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BTR2_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BTR2_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BTR2_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BTR2_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BTR2_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BTR2_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BTR2_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_FMC_BTR2_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_FMC_BTR2_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_FMC_BTR2_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_FMC_BTR2_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_FMC_BTR2_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BTR2_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BTR2_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BTR2_DATAHLD_Msk = 0xc0000000

	// FMC_BCR3: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_FMC_BCR3_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_FMC_BCR3_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_FMC_BCR3_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_FMC_BCR3_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_FMC_BCR3_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_FMC_BCR3_MUXEN = 0x2
	// Position of MTYP field.
	FMC_FMC_BCR3_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_FMC_BCR3_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_FMC_BCR3_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_FMC_BCR3_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_FMC_BCR3_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_FMC_BCR3_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_FMC_BCR3_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_FMC_BCR3_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_FMC_BCR3_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_FMC_BCR3_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_FMC_BCR3_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_FMC_BCR3_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_FMC_BCR3_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_FMC_BCR3_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_FMC_BCR3_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_FMC_BCR3_WAITCFG = 0x800
	// Position of WREN field.
	FMC_FMC_BCR3_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_FMC_BCR3_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_FMC_BCR3_WREN = 0x1000
	// Position of WAITEN field.
	FMC_FMC_BCR3_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_FMC_BCR3_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_FMC_BCR3_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_FMC_BCR3_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_FMC_BCR3_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_FMC_BCR3_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_FMC_BCR3_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_FMC_BCR3_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_FMC_BCR3_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_FMC_BCR3_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_FMC_BCR3_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_FMC_BCR3_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_FMC_BCR3_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_FMC_BCR3_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_FMC_BCR3_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_FMC_BCR3_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_FMC_BCR3_CCLKEN = 0x100000
	// Position of NBLSET field.
	FMC_FMC_BCR3_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_FMC_BCR3_NBLSET_Msk = 0xc00000
	// Position of FMCEN field.
	FMC_FMC_BCR3_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_FMC_BCR3_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_FMC_BCR3_FMCEN = 0x80000000

	// FMC_BTR3: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_FMC_BTR3_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BTR3_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BTR3_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BTR3_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BTR3_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BTR3_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BTR3_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BTR3_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_FMC_BTR3_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_FMC_BTR3_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_FMC_BTR3_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_FMC_BTR3_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_FMC_BTR3_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BTR3_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BTR3_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BTR3_DATAHLD_Msk = 0xc0000000

	// FMC_BCR4: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_FMC_BCR4_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_FMC_BCR4_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_FMC_BCR4_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_FMC_BCR4_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_FMC_BCR4_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_FMC_BCR4_MUXEN = 0x2
	// Position of MTYP field.
	FMC_FMC_BCR4_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_FMC_BCR4_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_FMC_BCR4_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_FMC_BCR4_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_FMC_BCR4_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_FMC_BCR4_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_FMC_BCR4_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_FMC_BCR4_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_FMC_BCR4_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_FMC_BCR4_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_FMC_BCR4_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_FMC_BCR4_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_FMC_BCR4_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_FMC_BCR4_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_FMC_BCR4_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_FMC_BCR4_WAITCFG = 0x800
	// Position of WREN field.
	FMC_FMC_BCR4_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_FMC_BCR4_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_FMC_BCR4_WREN = 0x1000
	// Position of WAITEN field.
	FMC_FMC_BCR4_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_FMC_BCR4_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_FMC_BCR4_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_FMC_BCR4_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_FMC_BCR4_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_FMC_BCR4_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_FMC_BCR4_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_FMC_BCR4_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_FMC_BCR4_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_FMC_BCR4_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_FMC_BCR4_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_FMC_BCR4_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_FMC_BCR4_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_FMC_BCR4_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_FMC_BCR4_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_FMC_BCR4_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_FMC_BCR4_CCLKEN = 0x100000
	// Position of NBLSET field.
	FMC_FMC_BCR4_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_FMC_BCR4_NBLSET_Msk = 0xc00000
	// Position of FMCEN field.
	FMC_FMC_BCR4_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_FMC_BCR4_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_FMC_BCR4_FMCEN = 0x80000000

	// FMC_BTR4: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_FMC_BTR4_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BTR4_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BTR4_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BTR4_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BTR4_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BTR4_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BTR4_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BTR4_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_FMC_BTR4_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_FMC_BTR4_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_FMC_BTR4_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_FMC_BTR4_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_FMC_BTR4_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BTR4_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BTR4_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BTR4_DATAHLD_Msk = 0xc0000000

	// FMC_PCSCNTR: This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h
	// Position of CSCOUNT field.
	FMC_FMC_PCSCNTR_CSCOUNT_Pos = 0x0
	// Bit mask of CSCOUNT field.
	FMC_FMC_PCSCNTR_CSCOUNT_Msk = 0xffff
	// Position of CNTB1EN field.
	FMC_FMC_PCSCNTR_CNTB1EN_Pos = 0x10
	// Bit mask of CNTB1EN field.
	FMC_FMC_PCSCNTR_CNTB1EN_Msk = 0x10000
	// Bit CNTB1EN.
	FMC_FMC_PCSCNTR_CNTB1EN = 0x10000
	// Position of CNTB2EN field.
	FMC_FMC_PCSCNTR_CNTB2EN_Pos = 0x11
	// Bit mask of CNTB2EN field.
	FMC_FMC_PCSCNTR_CNTB2EN_Msk = 0x20000
	// Bit CNTB2EN.
	FMC_FMC_PCSCNTR_CNTB2EN = 0x20000
	// Position of CNTB3EN field.
	FMC_FMC_PCSCNTR_CNTB3EN_Pos = 0x12
	// Bit mask of CNTB3EN field.
	FMC_FMC_PCSCNTR_CNTB3EN_Msk = 0x40000
	// Bit CNTB3EN.
	FMC_FMC_PCSCNTR_CNTB3EN = 0x40000
	// Position of CNTB4EN field.
	FMC_FMC_PCSCNTR_CNTB4EN_Pos = 0x13
	// Bit mask of CNTB4EN field.
	FMC_FMC_PCSCNTR_CNTB4EN_Msk = 0x80000
	// Bit CNTB4EN.
	FMC_FMC_PCSCNTR_CNTB4EN = 0x80000

	// FMC_PCR: NAND Flash Programmable control register
	// Position of PWAITEN field.
	FMC_FMC_PCR_PWAITEN_Pos = 0x1
	// Bit mask of PWAITEN field.
	FMC_FMC_PCR_PWAITEN_Msk = 0x2
	// Bit PWAITEN.
	FMC_FMC_PCR_PWAITEN = 0x2
	// Position of PBKEN field.
	FMC_FMC_PCR_PBKEN_Pos = 0x2
	// Bit mask of PBKEN field.
	FMC_FMC_PCR_PBKEN_Msk = 0x4
	// Bit PBKEN.
	FMC_FMC_PCR_PBKEN = 0x4
	// Position of PWID field.
	FMC_FMC_PCR_PWID_Pos = 0x4
	// Bit mask of PWID field.
	FMC_FMC_PCR_PWID_Msk = 0x30
	// Position of ECCEN field.
	FMC_FMC_PCR_ECCEN_Pos = 0x6
	// Bit mask of ECCEN field.
	FMC_FMC_PCR_ECCEN_Msk = 0x40
	// Bit ECCEN.
	FMC_FMC_PCR_ECCEN = 0x40
	// Position of ECCALG field.
	FMC_FMC_PCR_ECCALG_Pos = 0x8
	// Bit mask of ECCALG field.
	FMC_FMC_PCR_ECCALG_Msk = 0x100
	// Bit ECCALG.
	FMC_FMC_PCR_ECCALG = 0x100
	// Position of TCLR field.
	FMC_FMC_PCR_TCLR_Pos = 0x9
	// Bit mask of TCLR field.
	FMC_FMC_PCR_TCLR_Msk = 0x1e00
	// Position of TAR field.
	FMC_FMC_PCR_TAR_Pos = 0xd
	// Bit mask of TAR field.
	FMC_FMC_PCR_TAR_Msk = 0x1e000
	// Position of ECCSS field.
	FMC_FMC_PCR_ECCSS_Pos = 0x11
	// Bit mask of ECCSS field.
	FMC_FMC_PCR_ECCSS_Msk = 0xe0000
	// Position of TCEH field.
	FMC_FMC_PCR_TCEH_Pos = 0x14
	// Bit mask of TCEH field.
	FMC_FMC_PCR_TCEH_Msk = 0xf00000
	// Position of BCHECC field.
	FMC_FMC_PCR_BCHECC_Pos = 0x18
	// Bit mask of BCHECC field.
	FMC_FMC_PCR_BCHECC_Msk = 0x1000000
	// Bit BCHECC.
	FMC_FMC_PCR_BCHECC = 0x1000000
	// Position of WEN field.
	FMC_FMC_PCR_WEN_Pos = 0x19
	// Bit mask of WEN field.
	FMC_FMC_PCR_WEN_Msk = 0x2000000
	// Bit WEN.
	FMC_FMC_PCR_WEN = 0x2000000

	// FMC_SR: This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits.
	// Position of ISOST field.
	FMC_FMC_SR_ISOST_Pos = 0x0
	// Bit mask of ISOST field.
	FMC_FMC_SR_ISOST_Msk = 0x3
	// Position of PEF field.
	FMC_FMC_SR_PEF_Pos = 0x4
	// Bit mask of PEF field.
	FMC_FMC_SR_PEF_Msk = 0x10
	// Bit PEF.
	FMC_FMC_SR_PEF = 0x10
	// Position of NWRF field.
	FMC_FMC_SR_NWRF_Pos = 0x6
	// Bit mask of NWRF field.
	FMC_FMC_SR_NWRF_Msk = 0x40
	// Bit NWRF.
	FMC_FMC_SR_NWRF = 0x40

	// FMC_PMEM: The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses.
	// Position of MEMSET field.
	FMC_FMC_PMEM_MEMSET_Pos = 0x0
	// Bit mask of MEMSET field.
	FMC_FMC_PMEM_MEMSET_Msk = 0xff
	// Position of MEMWAIT field.
	FMC_FMC_PMEM_MEMWAIT_Pos = 0x8
	// Bit mask of MEMWAIT field.
	FMC_FMC_PMEM_MEMWAIT_Msk = 0xff00
	// Position of MEMHOLD field.
	FMC_FMC_PMEM_MEMHOLD_Pos = 0x10
	// Bit mask of MEMHOLD field.
	FMC_FMC_PMEM_MEMHOLD_Msk = 0xff0000
	// Position of MEMHIZ field.
	FMC_FMC_PMEM_MEMHIZ_Pos = 0x18
	// Bit mask of MEMHIZ field.
	FMC_FMC_PMEM_MEMHIZ_Msk = 0xff000000

	// FMC_PATT: The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function).
	// Position of ATTSET field.
	FMC_FMC_PATT_ATTSET_Pos = 0x0
	// Bit mask of ATTSET field.
	FMC_FMC_PATT_ATTSET_Msk = 0xff
	// Position of ATTWAIT field.
	FMC_FMC_PATT_ATTWAIT_Pos = 0x8
	// Bit mask of ATTWAIT field.
	FMC_FMC_PATT_ATTWAIT_Msk = 0xff00
	// Position of ATTHOLD field.
	FMC_FMC_PATT_ATTHOLD_Pos = 0x10
	// Bit mask of ATTHOLD field.
	FMC_FMC_PATT_ATTHOLD_Msk = 0xff0000
	// Position of ATTHIZ field.
	FMC_FMC_PATT_ATTHIZ_Pos = 0x18
	// Bit mask of ATTHIZ field.
	FMC_FMC_PATT_ATTHIZ_Msk = 0xff000000

	// FMC_HPR: This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
	// Position of HPR field.
	FMC_FMC_HPR_HPR_Pos = 0x0
	// Bit mask of HPR field.
	FMC_FMC_HPR_HPR_Msk = 0xffffffff

	// FMC_HECCR: This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
	// Position of HECC field.
	FMC_FMC_HECCR_HECC_Pos = 0x0
	// Bit mask of HECC field.
	FMC_FMC_HECCR_HECC_Msk = 0xffffffff

	// FMC_BWTR1: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_FMC_BWTR1_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BWTR1_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BWTR1_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BWTR1_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BWTR1_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BWTR1_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BWTR1_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BWTR1_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_FMC_BWTR1_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BWTR1_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BWTR1_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BWTR1_DATAHLD_Msk = 0xc0000000

	// FMC_BWTR2: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_FMC_BWTR2_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BWTR2_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BWTR2_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BWTR2_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BWTR2_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BWTR2_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BWTR2_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BWTR2_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_FMC_BWTR2_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BWTR2_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BWTR2_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BWTR2_DATAHLD_Msk = 0xc0000000

	// FMC_BWTR3: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_FMC_BWTR3_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BWTR3_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BWTR3_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BWTR3_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BWTR3_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BWTR3_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BWTR3_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BWTR3_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_FMC_BWTR3_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BWTR3_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BWTR3_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BWTR3_DATAHLD_Msk = 0xc0000000

	// FMC_BWTR4: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_FMC_BWTR4_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_FMC_BWTR4_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_FMC_BWTR4_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_FMC_BWTR4_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_FMC_BWTR4_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_FMC_BWTR4_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_FMC_BWTR4_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_FMC_BWTR4_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_FMC_BWTR4_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_FMC_BWTR4_ACCMOD_Msk = 0x30000000
	// Position of DATAHLD field.
	FMC_FMC_BWTR4_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_FMC_BWTR4_DATAHLD_Msk = 0xc0000000

	// FMC_CSQCR: FMC NAND Command Sequencer Control Register
	// Position of CSQSTART field.
	FMC_FMC_CSQCR_CSQSTART_Pos = 0x0
	// Bit mask of CSQSTART field.
	FMC_FMC_CSQCR_CSQSTART_Msk = 0x1
	// Bit CSQSTART.
	FMC_FMC_CSQCR_CSQSTART = 0x1

	// FMC_CSQCFGR1: FMC NAND Command Sequencer Configuration Register 1
	// Position of CMD2EN field.
	FMC_FMC_CSQCFGR1_CMD2EN_Pos = 0x1
	// Bit mask of CMD2EN field.
	FMC_FMC_CSQCFGR1_CMD2EN_Msk = 0x2
	// Bit CMD2EN.
	FMC_FMC_CSQCFGR1_CMD2EN = 0x2
	// Position of DMADEN field.
	FMC_FMC_CSQCFGR1_DMADEN_Pos = 0x2
	// Bit mask of DMADEN field.
	FMC_FMC_CSQCFGR1_DMADEN_Msk = 0x4
	// Bit DMADEN.
	FMC_FMC_CSQCFGR1_DMADEN = 0x4
	// Position of ACYNBR field.
	FMC_FMC_CSQCFGR1_ACYNBR_Pos = 0x4
	// Bit mask of ACYNBR field.
	FMC_FMC_CSQCFGR1_ACYNBR_Msk = 0x70
	// Position of CMD1 field.
	FMC_FMC_CSQCFGR1_CMD1_Pos = 0x8
	// Bit mask of CMD1 field.
	FMC_FMC_CSQCFGR1_CMD1_Msk = 0xff00
	// Position of CMD2 field.
	FMC_FMC_CSQCFGR1_CMD2_Pos = 0x10
	// Bit mask of CMD2 field.
	FMC_FMC_CSQCFGR1_CMD2_Msk = 0xff0000
	// Position of CMD1T field.
	FMC_FMC_CSQCFGR1_CMD1T_Pos = 0x18
	// Bit mask of CMD1T field.
	FMC_FMC_CSQCFGR1_CMD1T_Msk = 0x1000000
	// Bit CMD1T.
	FMC_FMC_CSQCFGR1_CMD1T = 0x1000000
	// Position of CMD2T field.
	FMC_FMC_CSQCFGR1_CMD2T_Pos = 0x19
	// Bit mask of CMD2T field.
	FMC_FMC_CSQCFGR1_CMD2T_Msk = 0x2000000
	// Bit CMD2T.
	FMC_FMC_CSQCFGR1_CMD2T = 0x2000000

	// FMC_CSQCFGR2: This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. .
	// Position of SQSDTEN field.
	FMC_FMC_CSQCFGR2_SQSDTEN_Pos = 0x0
	// Bit mask of SQSDTEN field.
	FMC_FMC_CSQCFGR2_SQSDTEN_Msk = 0x1
	// Bit SQSDTEN.
	FMC_FMC_CSQCFGR2_SQSDTEN = 0x1
	// Position of RCMD2EN field.
	FMC_FMC_CSQCFGR2_RCMD2EN_Pos = 0x1
	// Bit mask of RCMD2EN field.
	FMC_FMC_CSQCFGR2_RCMD2EN_Msk = 0x2
	// Bit RCMD2EN.
	FMC_FMC_CSQCFGR2_RCMD2EN = 0x2
	// Position of DMASEN field.
	FMC_FMC_CSQCFGR2_DMASEN_Pos = 0x2
	// Bit mask of DMASEN field.
	FMC_FMC_CSQCFGR2_DMASEN_Msk = 0x4
	// Bit DMASEN.
	FMC_FMC_CSQCFGR2_DMASEN = 0x4
	// Position of RCMD1 field.
	FMC_FMC_CSQCFGR2_RCMD1_Pos = 0x8
	// Bit mask of RCMD1 field.
	FMC_FMC_CSQCFGR2_RCMD1_Msk = 0xff00
	// Position of RCMD2 field.
	FMC_FMC_CSQCFGR2_RCMD2_Pos = 0x10
	// Bit mask of RCMD2 field.
	FMC_FMC_CSQCFGR2_RCMD2_Msk = 0xff0000
	// Position of RCMD1T field.
	FMC_FMC_CSQCFGR2_RCMD1T_Pos = 0x18
	// Bit mask of RCMD1T field.
	FMC_FMC_CSQCFGR2_RCMD1T_Msk = 0x1000000
	// Bit RCMD1T.
	FMC_FMC_CSQCFGR2_RCMD1T = 0x1000000
	// Position of RCMD2T field.
	FMC_FMC_CSQCFGR2_RCMD2T_Pos = 0x19
	// Bit mask of RCMD2T field.
	FMC_FMC_CSQCFGR2_RCMD2T_Msk = 0x2000000
	// Bit RCMD2T.
	FMC_FMC_CSQCFGR2_RCMD2T = 0x2000000

	// FMC_CSQCFGR3: FMC NAND sequencer configuration register 3
	// Position of SNBR field.
	FMC_FMC_CSQCFGR3_SNBR_Pos = 0x8
	// Bit mask of SNBR field.
	FMC_FMC_CSQCFGR3_SNBR_Msk = 0x3f00
	// Position of AC1T field.
	FMC_FMC_CSQCFGR3_AC1T_Pos = 0x10
	// Bit mask of AC1T field.
	FMC_FMC_CSQCFGR3_AC1T_Msk = 0x10000
	// Bit AC1T.
	FMC_FMC_CSQCFGR3_AC1T = 0x10000
	// Position of AC2T field.
	FMC_FMC_CSQCFGR3_AC2T_Pos = 0x11
	// Bit mask of AC2T field.
	FMC_FMC_CSQCFGR3_AC2T_Msk = 0x20000
	// Bit AC2T.
	FMC_FMC_CSQCFGR3_AC2T = 0x20000
	// Position of AC3T field.
	FMC_FMC_CSQCFGR3_AC3T_Pos = 0x12
	// Bit mask of AC3T field.
	FMC_FMC_CSQCFGR3_AC3T_Msk = 0x40000
	// Bit AC3T.
	FMC_FMC_CSQCFGR3_AC3T = 0x40000
	// Position of AC4T field.
	FMC_FMC_CSQCFGR3_AC4T_Pos = 0x13
	// Bit mask of AC4T field.
	FMC_FMC_CSQCFGR3_AC4T_Msk = 0x80000
	// Bit AC4T.
	FMC_FMC_CSQCFGR3_AC4T = 0x80000
	// Position of AC5T field.
	FMC_FMC_CSQCFGR3_AC5T_Pos = 0x14
	// Bit mask of AC5T field.
	FMC_FMC_CSQCFGR3_AC5T_Msk = 0x100000
	// Bit AC5T.
	FMC_FMC_CSQCFGR3_AC5T = 0x100000
	// Position of SDT field.
	FMC_FMC_CSQCFGR3_SDT_Pos = 0x15
	// Bit mask of SDT field.
	FMC_FMC_CSQCFGR3_SDT_Msk = 0x200000
	// Bit SDT.
	FMC_FMC_CSQCFGR3_SDT = 0x200000
	// Position of RAC1T field.
	FMC_FMC_CSQCFGR3_RAC1T_Pos = 0x16
	// Bit mask of RAC1T field.
	FMC_FMC_CSQCFGR3_RAC1T_Msk = 0x400000
	// Bit RAC1T.
	FMC_FMC_CSQCFGR3_RAC1T = 0x400000
	// Position of RAC2T field.
	FMC_FMC_CSQCFGR3_RAC2T_Pos = 0x17
	// Bit mask of RAC2T field.
	FMC_FMC_CSQCFGR3_RAC2T_Msk = 0x800000
	// Bit RAC2T.
	FMC_FMC_CSQCFGR3_RAC2T = 0x800000

	// FMC_CSQAR1: This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.
	// Position of ADDC1 field.
	FMC_FMC_CSQAR1_ADDC1_Pos = 0x0
	// Bit mask of ADDC1 field.
	FMC_FMC_CSQAR1_ADDC1_Msk = 0xff
	// Position of ADDC2 field.
	FMC_FMC_CSQAR1_ADDC2_Pos = 0x8
	// Bit mask of ADDC2 field.
	FMC_FMC_CSQAR1_ADDC2_Msk = 0xff00
	// Position of ADDC3 field.
	FMC_FMC_CSQAR1_ADDC3_Pos = 0x10
	// Bit mask of ADDC3 field.
	FMC_FMC_CSQAR1_ADDC3_Msk = 0xff0000
	// Position of ADDC4 field.
	FMC_FMC_CSQAR1_ADDC4_Pos = 0x18
	// Bit mask of ADDC4 field.
	FMC_FMC_CSQAR1_ADDC4_Msk = 0xff000000

	// FMC_CSQAR2: This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable.
	// Position of ADDC5 field.
	FMC_FMC_CSQAR2_ADDC5_Pos = 0x0
	// Bit mask of ADDC5 field.
	FMC_FMC_CSQAR2_ADDC5_Msk = 0xff
	// Position of NANDCEN0 field.
	FMC_FMC_CSQAR2_NANDCEN0_Pos = 0xa
	// Bit mask of NANDCEN0 field.
	FMC_FMC_CSQAR2_NANDCEN0_Msk = 0x400
	// Bit NANDCEN0.
	FMC_FMC_CSQAR2_NANDCEN0 = 0x400
	// Position of NANDCEN1 field.
	FMC_FMC_CSQAR2_NANDCEN1_Pos = 0xb
	// Bit mask of NANDCEN1 field.
	FMC_FMC_CSQAR2_NANDCEN1_Msk = 0x800
	// Bit NANDCEN1.
	FMC_FMC_CSQAR2_NANDCEN1 = 0x800
	// Position of SAO field.
	FMC_FMC_CSQAR2_SAO_Pos = 0x10
	// Bit mask of SAO field.
	FMC_FMC_CSQAR2_SAO_Msk = 0xffff0000

	// FMC_CSQIER: FMC NAND Command Sequencer Interrupt Enable Register
	// Position of TCIE field.
	FMC_FMC_CSQIER_TCIE_Pos = 0x0
	// Bit mask of TCIE field.
	FMC_FMC_CSQIER_TCIE_Msk = 0x1
	// Bit TCIE.
	FMC_FMC_CSQIER_TCIE = 0x1
	// Position of SCIE field.
	FMC_FMC_CSQIER_SCIE_Pos = 0x1
	// Bit mask of SCIE field.
	FMC_FMC_CSQIER_SCIE_Msk = 0x2
	// Bit SCIE.
	FMC_FMC_CSQIER_SCIE = 0x2
	// Position of SEIE field.
	FMC_FMC_CSQIER_SEIE_Pos = 0x2
	// Bit mask of SEIE field.
	FMC_FMC_CSQIER_SEIE_Msk = 0x4
	// Bit SEIE.
	FMC_FMC_CSQIER_SEIE = 0x4
	// Position of SUEIE field.
	FMC_FMC_CSQIER_SUEIE_Pos = 0x3
	// Bit mask of SUEIE field.
	FMC_FMC_CSQIER_SUEIE_Msk = 0x8
	// Bit SUEIE.
	FMC_FMC_CSQIER_SUEIE = 0x8
	// Position of CMDTCIE field.
	FMC_FMC_CSQIER_CMDTCIE_Pos = 0x4
	// Bit mask of CMDTCIE field.
	FMC_FMC_CSQIER_CMDTCIE_Msk = 0x10
	// Bit CMDTCIE.
	FMC_FMC_CSQIER_CMDTCIE = 0x10

	// FMC_CSQISR: FMC NAND Command Sequencer Interrupt Status Register
	// Position of TCF field.
	FMC_FMC_CSQISR_TCF_Pos = 0x0
	// Bit mask of TCF field.
	FMC_FMC_CSQISR_TCF_Msk = 0x1
	// Bit TCF.
	FMC_FMC_CSQISR_TCF = 0x1
	// Position of SCF field.
	FMC_FMC_CSQISR_SCF_Pos = 0x1
	// Bit mask of SCF field.
	FMC_FMC_CSQISR_SCF_Msk = 0x2
	// Bit SCF.
	FMC_FMC_CSQISR_SCF = 0x2
	// Position of SEF field.
	FMC_FMC_CSQISR_SEF_Pos = 0x2
	// Bit mask of SEF field.
	FMC_FMC_CSQISR_SEF_Msk = 0x4
	// Bit SEF.
	FMC_FMC_CSQISR_SEF = 0x4
	// Position of SUEF field.
	FMC_FMC_CSQISR_SUEF_Pos = 0x3
	// Bit mask of SUEF field.
	FMC_FMC_CSQISR_SUEF_Msk = 0x8
	// Bit SUEF.
	FMC_FMC_CSQISR_SUEF = 0x8
	// Position of CMDTCF field.
	FMC_FMC_CSQISR_CMDTCF_Pos = 0x4
	// Bit mask of CMDTCF field.
	FMC_FMC_CSQISR_CMDTCF_Msk = 0x10
	// Bit CMDTCF.
	FMC_FMC_CSQISR_CMDTCF = 0x10

	// FMC_CSQICR: FMC NAND Command Sequencer Interrupt Clear Register
	// Position of CTCF field.
	FMC_FMC_CSQICR_CTCF_Pos = 0x0
	// Bit mask of CTCF field.
	FMC_FMC_CSQICR_CTCF_Msk = 0x1
	// Bit CTCF.
	FMC_FMC_CSQICR_CTCF = 0x1
	// Position of CSCF field.
	FMC_FMC_CSQICR_CSCF_Pos = 0x1
	// Bit mask of CSCF field.
	FMC_FMC_CSQICR_CSCF_Msk = 0x2
	// Bit CSCF.
	FMC_FMC_CSQICR_CSCF = 0x2
	// Position of CSEF field.
	FMC_FMC_CSQICR_CSEF_Pos = 0x2
	// Bit mask of CSEF field.
	FMC_FMC_CSQICR_CSEF_Msk = 0x4
	// Bit CSEF.
	FMC_FMC_CSQICR_CSEF = 0x4
	// Position of CSUEF field.
	FMC_FMC_CSQICR_CSUEF_Pos = 0x3
	// Bit mask of CSUEF field.
	FMC_FMC_CSQICR_CSUEF_Msk = 0x8
	// Bit CSUEF.
	FMC_FMC_CSQICR_CSUEF = 0x8
	// Position of CCMDTCF field.
	FMC_FMC_CSQICR_CCMDTCF_Pos = 0x4
	// Bit mask of CCMDTCF field.
	FMC_FMC_CSQICR_CCMDTCF_Msk = 0x10
	// Bit CCMDTCF.
	FMC_FMC_CSQICR_CCMDTCF = 0x10

	// FMC_CSQEMSR: This register holds a sector error mapping status when the whole transfer is complete.
	// Position of SEM field.
	FMC_FMC_CSQEMSR_SEM_Pos = 0x0
	// Bit mask of SEM field.
	FMC_FMC_CSQEMSR_SEM_Msk = 0xffff

	// FMC_BCHIER: FMC BCH Interrupt enable register
	// Position of DUEIE field.
	FMC_FMC_BCHIER_DUEIE_Pos = 0x0
	// Bit mask of DUEIE field.
	FMC_FMC_BCHIER_DUEIE_Msk = 0x1
	// Bit DUEIE.
	FMC_FMC_BCHIER_DUEIE = 0x1
	// Position of DERIE field.
	FMC_FMC_BCHIER_DERIE_Pos = 0x1
	// Bit mask of DERIE field.
	FMC_FMC_BCHIER_DERIE_Msk = 0x2
	// Bit DERIE.
	FMC_FMC_BCHIER_DERIE = 0x2
	// Position of DEFIE field.
	FMC_FMC_BCHIER_DEFIE_Pos = 0x2
	// Bit mask of DEFIE field.
	FMC_FMC_BCHIER_DEFIE_Msk = 0x4
	// Bit DEFIE.
	FMC_FMC_BCHIER_DEFIE = 0x4
	// Position of DSRIE field.
	FMC_FMC_BCHIER_DSRIE_Pos = 0x3
	// Bit mask of DSRIE field.
	FMC_FMC_BCHIER_DSRIE_Msk = 0x8
	// Bit DSRIE.
	FMC_FMC_BCHIER_DSRIE = 0x8
	// Position of EPBRIE field.
	FMC_FMC_BCHIER_EPBRIE_Pos = 0x4
	// Bit mask of EPBRIE field.
	FMC_FMC_BCHIER_EPBRIE_Msk = 0x10
	// Bit EPBRIE.
	FMC_FMC_BCHIER_EPBRIE = 0x10

	// FMC_BCHISR: This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared.
	// Position of DUEF field.
	FMC_FMC_BCHISR_DUEF_Pos = 0x0
	// Bit mask of DUEF field.
	FMC_FMC_BCHISR_DUEF_Msk = 0x1
	// Bit DUEF.
	FMC_FMC_BCHISR_DUEF = 0x1
	// Position of DERF field.
	FMC_FMC_BCHISR_DERF_Pos = 0x1
	// Bit mask of DERF field.
	FMC_FMC_BCHISR_DERF_Msk = 0x2
	// Bit DERF.
	FMC_FMC_BCHISR_DERF = 0x2
	// Position of DEFF field.
	FMC_FMC_BCHISR_DEFF_Pos = 0x2
	// Bit mask of DEFF field.
	FMC_FMC_BCHISR_DEFF_Msk = 0x4
	// Bit DEFF.
	FMC_FMC_BCHISR_DEFF = 0x4
	// Position of DSRF field.
	FMC_FMC_BCHISR_DSRF_Pos = 0x3
	// Bit mask of DSRF field.
	FMC_FMC_BCHISR_DSRF_Msk = 0x8
	// Bit DSRF.
	FMC_FMC_BCHISR_DSRF = 0x8
	// Position of EPBRF field.
	FMC_FMC_BCHISR_EPBRF_Pos = 0x4
	// Bit mask of EPBRF field.
	FMC_FMC_BCHISR_EPBRF_Msk = 0x10
	// Bit EPBRF.
	FMC_FMC_BCHISR_EPBRF = 0x10

	// FMC_BCHICR: FMC BCH Interrupt Clear Register
	// Position of CDUEF field.
	FMC_FMC_BCHICR_CDUEF_Pos = 0x0
	// Bit mask of CDUEF field.
	FMC_FMC_BCHICR_CDUEF_Msk = 0x1
	// Bit CDUEF.
	FMC_FMC_BCHICR_CDUEF = 0x1
	// Position of CDERF field.
	FMC_FMC_BCHICR_CDERF_Pos = 0x1
	// Bit mask of CDERF field.
	FMC_FMC_BCHICR_CDERF_Msk = 0x2
	// Bit CDERF.
	FMC_FMC_BCHICR_CDERF = 0x2
	// Position of CDEFF field.
	FMC_FMC_BCHICR_CDEFF_Pos = 0x2
	// Bit mask of CDEFF field.
	FMC_FMC_BCHICR_CDEFF_Msk = 0x4
	// Bit CDEFF.
	FMC_FMC_BCHICR_CDEFF = 0x4
	// Position of CDSRF field.
	FMC_FMC_BCHICR_CDSRF_Pos = 0x3
	// Bit mask of CDSRF field.
	FMC_FMC_BCHICR_CDSRF_Msk = 0x8
	// Bit CDSRF.
	FMC_FMC_BCHICR_CDSRF = 0x8
	// Position of CEPBRF field.
	FMC_FMC_BCHICR_CEPBRF_Pos = 0x4
	// Bit mask of CEPBRF field.
	FMC_FMC_BCHICR_CEPBRF_Msk = 0x10
	// Bit CEPBRF.
	FMC_FMC_BCHICR_CEPBRF = 0x10

	// FMC_BCHPBR1: These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant.
	// Position of BCHPB field.
	FMC_FMC_BCHPBR1_BCHPB_Pos = 0x0
	// Bit mask of BCHPB field.
	FMC_FMC_BCHPBR1_BCHPB_Msk = 0xffffffff

	// FMC_BCHPBR2: FMC BCH Parity Bits Register 2
	// Position of BCHPB field.
	FMC_FMC_BCHPBR2_BCHPB_Pos = 0x0
	// Bit mask of BCHPB field.
	FMC_FMC_BCHPBR2_BCHPB_Msk = 0xffffffff

	// FMC_BCHPBR3: FMC BCH Parity Bits Register 3
	// Position of BCHPB field.
	FMC_FMC_BCHPBR3_BCHPB_Pos = 0x0
	// Bit mask of BCHPB field.
	FMC_FMC_BCHPBR3_BCHPB_Msk = 0xffffffff

	// FMC_BCHPBR4: FMC BCH Parity Bits Register 4
	// Position of BCHPB field.
	FMC_FMC_BCHPBR4_BCHPB_Pos = 0x0
	// Bit mask of BCHPB field.
	FMC_FMC_BCHPBR4_BCHPB_Msk = 0xff

	// FMC_BCHDSR0: This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. .
	// Position of DUE field.
	FMC_FMC_BCHDSR0_DUE_Pos = 0x0
	// Bit mask of DUE field.
	FMC_FMC_BCHDSR0_DUE_Msk = 0x1
	// Bit DUE.
	FMC_FMC_BCHDSR0_DUE = 0x1
	// Position of DEF field.
	FMC_FMC_BCHDSR0_DEF_Pos = 0x1
	// Bit mask of DEF field.
	FMC_FMC_BCHDSR0_DEF_Msk = 0x2
	// Bit DEF.
	FMC_FMC_BCHDSR0_DEF = 0x2
	// Position of DEN field.
	FMC_FMC_BCHDSR0_DEN_Pos = 0x4
	// Bit mask of DEN field.
	FMC_FMC_BCHDSR0_DEN_Msk = 0xf0

	// FMC_BCHDSR1: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors
	// Position of EBP1 field.
	FMC_FMC_BCHDSR1_EBP1_Pos = 0x0
	// Bit mask of EBP1 field.
	FMC_FMC_BCHDSR1_EBP1_Msk = 0x1fff
	// Position of EBP2 field.
	FMC_FMC_BCHDSR1_EBP2_Pos = 0x10
	// Bit mask of EBP2 field.
	FMC_FMC_BCHDSR1_EBP2_Msk = 0x1fff0000

	// FMC_BCHDSR2: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively.
	// Position of EBP3 field.
	FMC_FMC_BCHDSR2_EBP3_Pos = 0x0
	// Bit mask of EBP3 field.
	FMC_FMC_BCHDSR2_EBP3_Msk = 0x1fff
	// Position of EBP4 field.
	FMC_FMC_BCHDSR2_EBP4_Pos = 0x10
	// Bit mask of EBP4 field.
	FMC_FMC_BCHDSR2_EBP4_Msk = 0x1fff0000

	// FMC_BCHDSR3: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
	// Position of EBP5 field.
	FMC_FMC_BCHDSR3_EBP5_Pos = 0x0
	// Bit mask of EBP5 field.
	FMC_FMC_BCHDSR3_EBP5_Msk = 0x1fff
	// Position of EBP6 field.
	FMC_FMC_BCHDSR3_EBP6_Pos = 0x10
	// Bit mask of EBP6 field.
	FMC_FMC_BCHDSR3_EBP6_Msk = 0x1fff0000

	// FMC_BCHDSR4: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. .
	// Position of EBP7 field.
	FMC_FMC_BCHDSR4_EBP7_Pos = 0x0
	// Bit mask of EBP7 field.
	FMC_FMC_BCHDSR4_EBP7_Msk = 0x1fff
	// Position of EBP8 field.
	FMC_FMC_BCHDSR4_EBP8_Pos = 0x10
	// Bit mask of EBP8 field.
	FMC_FMC_BCHDSR4_EBP8_Msk = 0x1fff0000

	// FMC_HWCFGR2: FMC Hardware configuration register 2
	// Position of RD_LN2DPTH field.
	FMC_FMC_HWCFGR2_RD_LN2DPTH_Pos = 0x0
	// Bit mask of RD_LN2DPTH field.
	FMC_FMC_HWCFGR2_RD_LN2DPTH_Msk = 0xf
	// Position of NOR_BASE field.
	FMC_FMC_HWCFGR2_NOR_BASE_Pos = 0x4
	// Bit mask of NOR_BASE field.
	FMC_FMC_HWCFGR2_NOR_BASE_Msk = 0xf0
	// Position of SDRAM_RBASE field.
	FMC_FMC_HWCFGR2_SDRAM_RBASE_Pos = 0x8
	// Bit mask of SDRAM_RBASE field.
	FMC_FMC_HWCFGR2_SDRAM_RBASE_Msk = 0xf00
	// Position of NAND_BASE field.
	FMC_FMC_HWCFGR2_NAND_BASE_Pos = 0xc
	// Bit mask of NAND_BASE field.
	FMC_FMC_HWCFGR2_NAND_BASE_Msk = 0xf000
	// Position of SDRAM1_BASE field.
	FMC_FMC_HWCFGR2_SDRAM1_BASE_Pos = 0x10
	// Bit mask of SDRAM1_BASE field.
	FMC_FMC_HWCFGR2_SDRAM1_BASE_Msk = 0xf0000
	// Position of SDRAM2_BASE field.
	FMC_FMC_HWCFGR2_SDRAM2_BASE_Pos = 0x14
	// Bit mask of SDRAM2_BASE field.
	FMC_FMC_HWCFGR2_SDRAM2_BASE_Msk = 0xf00000

	// FMC_HWCFGR1: FMC Hardware configuration register 1
	// Position of NAND_SEL field.
	FMC_FMC_HWCFGR1_NAND_SEL_Pos = 0x0
	// Bit mask of NAND_SEL field.
	FMC_FMC_HWCFGR1_NAND_SEL_Msk = 0x1
	// Bit NAND_SEL.
	FMC_FMC_HWCFGR1_NAND_SEL = 0x1
	// Position of NAND_ECC field.
	FMC_FMC_HWCFGR1_NAND_ECC_Pos = 0x4
	// Bit mask of NAND_ECC field.
	FMC_FMC_HWCFGR1_NAND_ECC_Msk = 0x10
	// Bit NAND_ECC.
	FMC_FMC_HWCFGR1_NAND_ECC = 0x10
	// Position of SDRAM_SEL field.
	FMC_FMC_HWCFGR1_SDRAM_SEL_Pos = 0x8
	// Bit mask of SDRAM_SEL field.
	FMC_FMC_HWCFGR1_SDRAM_SEL_Msk = 0x100
	// Bit SDRAM_SEL.
	FMC_FMC_HWCFGR1_SDRAM_SEL = 0x100
	// Position of ID_SIZE field.
	FMC_FMC_HWCFGR1_ID_SIZE_Pos = 0xc
	// Bit mask of ID_SIZE field.
	FMC_FMC_HWCFGR1_ID_SIZE_Msk = 0xf000
	// Position of WA_LN2DPTH field.
	FMC_FMC_HWCFGR1_WA_LN2DPTH_Pos = 0x10
	// Bit mask of WA_LN2DPTH field.
	FMC_FMC_HWCFGR1_WA_LN2DPTH_Msk = 0xf0000
	// Position of WD_LN2DPTH field.
	FMC_FMC_HWCFGR1_WD_LN2DPTH_Pos = 0x14
	// Bit mask of WD_LN2DPTH field.
	FMC_FMC_HWCFGR1_WD_LN2DPTH_Msk = 0xf00000
	// Position of WR_LN2DPTH field.
	FMC_FMC_HWCFGR1_WR_LN2DPTH_Pos = 0x18
	// Bit mask of WR_LN2DPTH field.
	FMC_FMC_HWCFGR1_WR_LN2DPTH_Msk = 0xf000000
	// Position of RA_LN2DPTH field.
	FMC_FMC_HWCFGR1_RA_LN2DPTH_Pos = 0x1c
	// Bit mask of RA_LN2DPTH field.
	FMC_FMC_HWCFGR1_RA_LN2DPTH_Msk = 0xf0000000

	// FMC_VERR: FMC Version register
	// Position of MINREV field.
	FMC_FMC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	FMC_FMC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	FMC_FMC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	FMC_FMC_VERR_MAJREV_Msk = 0xf0

	// FMC_IPIDR: FMC Identification register
	// Position of ID field.
	FMC_FMC_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	FMC_FMC_IPIDR_ID_Msk = 0xffffffff

	// FMC_SIDR: FMC Size Identification register
	// Position of SID field.
	FMC_FMC_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	FMC_FMC_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for GICC: GICC
const (
	// GICC_CTLR: GICC control register
	// Position of ENABLEGRP0 field.
	GICC_GICC_CTLR_ENABLEGRP0_Pos = 0x0
	// Bit mask of ENABLEGRP0 field.
	GICC_GICC_CTLR_ENABLEGRP0_Msk = 0x1
	// Bit ENABLEGRP0.
	GICC_GICC_CTLR_ENABLEGRP0 = 0x1
	// Position of ENABLEGRP1 field.
	GICC_GICC_CTLR_ENABLEGRP1_Pos = 0x1
	// Bit mask of ENABLEGRP1 field.
	GICC_GICC_CTLR_ENABLEGRP1_Msk = 0x2
	// Bit ENABLEGRP1.
	GICC_GICC_CTLR_ENABLEGRP1 = 0x2
	// Position of ACKCTL field.
	GICC_GICC_CTLR_ACKCTL_Pos = 0x2
	// Bit mask of ACKCTL field.
	GICC_GICC_CTLR_ACKCTL_Msk = 0x4
	// Bit ACKCTL.
	GICC_GICC_CTLR_ACKCTL = 0x4
	// Position of FIQEN field.
	GICC_GICC_CTLR_FIQEN_Pos = 0x3
	// Bit mask of FIQEN field.
	GICC_GICC_CTLR_FIQEN_Msk = 0x8
	// Bit FIQEN.
	GICC_GICC_CTLR_FIQEN = 0x8
	// Position of CBPR field.
	GICC_GICC_CTLR_CBPR_Pos = 0x4
	// Bit mask of CBPR field.
	GICC_GICC_CTLR_CBPR_Msk = 0x10
	// Bit CBPR.
	GICC_GICC_CTLR_CBPR = 0x10
	// Position of FIQBYPDISGRP0 field.
	GICC_GICC_CTLR_FIQBYPDISGRP0_Pos = 0x5
	// Bit mask of FIQBYPDISGRP0 field.
	GICC_GICC_CTLR_FIQBYPDISGRP0_Msk = 0x20
	// Bit FIQBYPDISGRP0.
	GICC_GICC_CTLR_FIQBYPDISGRP0 = 0x20
	// Position of IRQBYPDISGRP0 field.
	GICC_GICC_CTLR_IRQBYPDISGRP0_Pos = 0x6
	// Bit mask of IRQBYPDISGRP0 field.
	GICC_GICC_CTLR_IRQBYPDISGRP0_Msk = 0x40
	// Bit IRQBYPDISGRP0.
	GICC_GICC_CTLR_IRQBYPDISGRP0 = 0x40
	// Position of FIQBYPDISGRP1 field.
	GICC_GICC_CTLR_FIQBYPDISGRP1_Pos = 0x7
	// Bit mask of FIQBYPDISGRP1 field.
	GICC_GICC_CTLR_FIQBYPDISGRP1_Msk = 0x80
	// Bit FIQBYPDISGRP1.
	GICC_GICC_CTLR_FIQBYPDISGRP1 = 0x80
	// Position of IRQBYPDISGRP1 field.
	GICC_GICC_CTLR_IRQBYPDISGRP1_Pos = 0x8
	// Bit mask of IRQBYPDISGRP1 field.
	GICC_GICC_CTLR_IRQBYPDISGRP1_Msk = 0x100
	// Bit IRQBYPDISGRP1.
	GICC_GICC_CTLR_IRQBYPDISGRP1 = 0x100
	// Position of EOIMODES field.
	GICC_GICC_CTLR_EOIMODES_Pos = 0x9
	// Bit mask of EOIMODES field.
	GICC_GICC_CTLR_EOIMODES_Msk = 0x200
	// Bit EOIMODES.
	GICC_GICC_CTLR_EOIMODES = 0x200
	// Position of EOIMODENS field.
	GICC_GICC_CTLR_EOIMODENS_Pos = 0xa
	// Bit mask of EOIMODENS field.
	GICC_GICC_CTLR_EOIMODENS_Msk = 0x400
	// Bit EOIMODENS.
	GICC_GICC_CTLR_EOIMODENS = 0x400

	// GICC_PMR: GICC input priority mask register
	// Position of PRIORITY field.
	GICC_GICC_PMR_PRIORITY_Pos = 0x3
	// Bit mask of PRIORITY field.
	GICC_GICC_PMR_PRIORITY_Msk = 0xf8

	// GICC_BPR: GICC binary point register
	// Position of BINARY_POINT field.
	GICC_GICC_BPR_BINARY_POINT_Pos = 0x0
	// Bit mask of BINARY_POINT field.
	GICC_GICC_BPR_BINARY_POINT_Msk = 0x7

	// GICC_IAR: GICC interrupt acknowledge register
	// Position of INTERRUPT_ID field.
	GICC_GICC_IAR_INTERRUPT_ID_Pos = 0x0
	// Bit mask of INTERRUPT_ID field.
	GICC_GICC_IAR_INTERRUPT_ID_Msk = 0x3ff
	// Position of CPUID field.
	GICC_GICC_IAR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICC_GICC_IAR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICC_GICC_IAR_CPUID = 0x400

	// GICC_EOIR: GICC end of interrupt register
	// Position of EOIINTID field.
	GICC_GICC_EOIR_EOIINTID_Pos = 0x0
	// Bit mask of EOIINTID field.
	GICC_GICC_EOIR_EOIINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICC_GICC_EOIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICC_GICC_EOIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICC_GICC_EOIR_CPUID = 0x400

	// GICC_RPR: GICC running priority register
	// Position of PRIORITY field.
	GICC_GICC_RPR_PRIORITY_Pos = 0x3
	// Bit mask of PRIORITY field.
	GICC_GICC_RPR_PRIORITY_Msk = 0xf8

	// GICC_HPPIR: GICC highest priority pending interrupt register
	// Position of PENDINTID field.
	GICC_GICC_HPPIR_PENDINTID_Pos = 0x0
	// Bit mask of PENDINTID field.
	GICC_GICC_HPPIR_PENDINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICC_GICC_HPPIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICC_GICC_HPPIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICC_GICC_HPPIR_CPUID = 0x400

	// GICC_ABPR: GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR.
	// Position of BINARY_POINT field.
	GICC_GICC_ABPR_BINARY_POINT_Pos = 0x0
	// Bit mask of BINARY_POINT field.
	GICC_GICC_ABPR_BINARY_POINT_Msk = 0x7

	// GICC_AIAR: GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR.
	// Position of INTERRUPT_ID field.
	GICC_GICC_AIAR_INTERRUPT_ID_Pos = 0x0
	// Bit mask of INTERRUPT_ID field.
	GICC_GICC_AIAR_INTERRUPT_ID_Msk = 0x3ff
	// Position of CPUID field.
	GICC_GICC_AIAR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICC_GICC_AIAR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICC_GICC_AIAR_CPUID = 0x400

	// GICC_AEOIR: GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used.
	// Position of EOIINTID field.
	GICC_GICC_AEOIR_EOIINTID_Pos = 0x0
	// Bit mask of EOIINTID field.
	GICC_GICC_AEOIR_EOIINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICC_GICC_AEOIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICC_GICC_AEOIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICC_GICC_AEOIR_CPUID = 0x400

	// GICC_AHPPIR: ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR.
	// Position of PENDINTID field.
	GICC_GICC_AHPPIR_PENDINTID_Pos = 0x0
	// Bit mask of PENDINTID field.
	GICC_GICC_AHPPIR_PENDINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICC_GICC_AHPPIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICC_GICC_AHPPIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICC_GICC_AHPPIR_CPUID = 0x400

	// GICC_APR0: GICC active priority register
	// Position of APR0 field.
	GICC_GICC_APR0_APR0_Pos = 0x0
	// Bit mask of APR0 field.
	GICC_GICC_APR0_APR0_Msk = 0xffffffff

	// GICC_NSAPR0: GICC non-secure active priority register
	// Position of NSAPR0 field.
	GICC_GICC_NSAPR0_NSAPR0_Pos = 0x0
	// Bit mask of NSAPR0 field.
	GICC_GICC_NSAPR0_NSAPR0_Msk = 0xffffffff

	// GICC_IIDR: GICC interface identification register
	// Position of IMPLEMENTER field.
	GICC_GICC_IIDR_IMPLEMENTER_Pos = 0x0
	// Bit mask of IMPLEMENTER field.
	GICC_GICC_IIDR_IMPLEMENTER_Msk = 0xfff
	// Position of REVISION field.
	GICC_GICC_IIDR_REVISION_Pos = 0xc
	// Bit mask of REVISION field.
	GICC_GICC_IIDR_REVISION_Msk = 0xf000
	// Position of ARCH field.
	GICC_GICC_IIDR_ARCH_Pos = 0x10
	// Bit mask of ARCH field.
	GICC_GICC_IIDR_ARCH_Msk = 0xf0000
	// Position of PRODUCTID field.
	GICC_GICC_IIDR_PRODUCTID_Pos = 0x14
	// Bit mask of PRODUCTID field.
	GICC_GICC_IIDR_PRODUCTID_Msk = 0xfff00000

	// GICC_DIR: GICC deactivate interrupt register
	// Position of INTERRUPT_ID field.
	GICC_GICC_DIR_INTERRUPT_ID_Pos = 0x0
	// Bit mask of INTERRUPT_ID field.
	GICC_GICC_DIR_INTERRUPT_ID_Msk = 0x3ff
	// Position of CPUID field.
	GICC_GICC_DIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICC_GICC_DIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICC_GICC_DIR_CPUID = 0x400
)

// Bitfields for GICD: GICD
const (
	// GICD_CTLR: GICD control register
	// Position of ENABLEGRP0 field.
	GICD_GICD_CTLR_ENABLEGRP0_Pos = 0x0
	// Bit mask of ENABLEGRP0 field.
	GICD_GICD_CTLR_ENABLEGRP0_Msk = 0x1
	// Bit ENABLEGRP0.
	GICD_GICD_CTLR_ENABLEGRP0 = 0x1
	// Position of ENABLEGRP1 field.
	GICD_GICD_CTLR_ENABLEGRP1_Pos = 0x1
	// Bit mask of ENABLEGRP1 field.
	GICD_GICD_CTLR_ENABLEGRP1_Msk = 0x2
	// Bit ENABLEGRP1.
	GICD_GICD_CTLR_ENABLEGRP1 = 0x2

	// GICD_TYPER: GICD interrupt controller type register
	// Position of ITLINESNUMBER field.
	GICD_GICD_TYPER_ITLINESNUMBER_Pos = 0x0
	// Bit mask of ITLINESNUMBER field.
	GICD_GICD_TYPER_ITLINESNUMBER_Msk = 0x1f
	// Position of CPUNUMBER field.
	GICD_GICD_TYPER_CPUNUMBER_Pos = 0x5
	// Bit mask of CPUNUMBER field.
	GICD_GICD_TYPER_CPUNUMBER_Msk = 0xe0
	// Position of SECURITYEXTN field.
	GICD_GICD_TYPER_SECURITYEXTN_Pos = 0xa
	// Bit mask of SECURITYEXTN field.
	GICD_GICD_TYPER_SECURITYEXTN_Msk = 0x400
	// Bit SECURITYEXTN.
	GICD_GICD_TYPER_SECURITYEXTN = 0x400
	// Position of LSPI field.
	GICD_GICD_TYPER_LSPI_Pos = 0xb
	// Bit mask of LSPI field.
	GICD_GICD_TYPER_LSPI_Msk = 0xf800

	// GICD_IIDR: GICD implementer identification register
	// Position of IMPLEMENTER field.
	GICD_GICD_IIDR_IMPLEMENTER_Pos = 0x0
	// Bit mask of IMPLEMENTER field.
	GICD_GICD_IIDR_IMPLEMENTER_Msk = 0xfff
	// Position of VARIANT field.
	GICD_GICD_IIDR_VARIANT_Pos = 0xc
	// Bit mask of VARIANT field.
	GICD_GICD_IIDR_VARIANT_Msk = 0xf000
	// Position of REVISION field.
	GICD_GICD_IIDR_REVISION_Pos = 0x10
	// Bit mask of REVISION field.
	GICD_GICD_IIDR_REVISION_Msk = 0xf0000
	// Position of PRODUCTID field.
	GICD_GICD_IIDR_PRODUCTID_Pos = 0x18
	// Bit mask of PRODUCTID field.
	GICD_GICD_IIDR_PRODUCTID_Msk = 0xff000000

	// GICD_IGROUPR0: For interrupts ID
	// Position of IGROUPR0 field.
	GICD_GICD_IGROUPR0_IGROUPR0_Pos = 0x0
	// Bit mask of IGROUPR0 field.
	GICD_GICD_IGROUPR0_IGROUPR0_Msk = 0xffffffff

	// GICD_IGROUPR1: For interrupts ID
	// Position of IGROUPR1 field.
	GICD_GICD_IGROUPR1_IGROUPR1_Pos = 0x0
	// Bit mask of IGROUPR1 field.
	GICD_GICD_IGROUPR1_IGROUPR1_Msk = 0xffffffff

	// GICD_IGROUPR2: For interrupts ID
	// Position of IGROUPR2 field.
	GICD_GICD_IGROUPR2_IGROUPR2_Pos = 0x0
	// Bit mask of IGROUPR2 field.
	GICD_GICD_IGROUPR2_IGROUPR2_Msk = 0xffffffff

	// GICD_IGROUPR3: For interrupts ID = x*32 to ID = x*32+31
	// Position of IGROUPR3 field.
	GICD_GICD_IGROUPR3_IGROUPR3_Pos = 0x0
	// Bit mask of IGROUPR3 field.
	GICD_GICD_IGROUPR3_IGROUPR3_Msk = 0xffffffff

	// GICD_IGROUPR4: For interrupts ID = x*32 to ID = x*32+31
	// Position of IGROUPR4 field.
	GICD_GICD_IGROUPR4_IGROUPR4_Pos = 0x0
	// Bit mask of IGROUPR4 field.
	GICD_GICD_IGROUPR4_IGROUPR4_Msk = 0xffffffff

	// GICD_IGROUPR5: For interrupts ID
	// Position of IGROUPR5 field.
	GICD_GICD_IGROUPR5_IGROUPR5_Pos = 0x0
	// Bit mask of IGROUPR5 field.
	GICD_GICD_IGROUPR5_IGROUPR5_Msk = 0xffffffff

	// GICD_IGROUPR6: For interrupts ID
	// Position of IGROUPR6 field.
	GICD_GICD_IGROUPR6_IGROUPR6_Pos = 0x0
	// Bit mask of IGROUPR6 field.
	GICD_GICD_IGROUPR6_IGROUPR6_Msk = 0xffffffff

	// GICD_IGROUPR7: For interrupts ID
	// Position of IGROUPR7 field.
	GICD_GICD_IGROUPR7_IGROUPR7_Pos = 0x0
	// Bit mask of IGROUPR7 field.
	GICD_GICD_IGROUPR7_IGROUPR7_Msk = 0xffffffff

	// GICD_IGROUPR8: For interrupts ID
	// Position of IGROUPR8 field.
	GICD_GICD_IGROUPR8_IGROUPR8_Pos = 0x0
	// Bit mask of IGROUPR8 field.
	GICD_GICD_IGROUPR8_IGROUPR8_Msk = 0xffffffff

	// GICD_ISENABLER0: For interrupts ID = 0 to ID = 31
	// Position of ISENABLER0 field.
	GICD_GICD_ISENABLER0_ISENABLER0_Pos = 0x0
	// Bit mask of ISENABLER0 field.
	GICD_GICD_ISENABLER0_ISENABLER0_Msk = 0xffffffff

	// GICD_ISENABLER1: For interrupts ID
	// Position of ISENABLER1 field.
	GICD_GICD_ISENABLER1_ISENABLER1_Pos = 0x0
	// Bit mask of ISENABLER1 field.
	GICD_GICD_ISENABLER1_ISENABLER1_Msk = 0xffffffff

	// GICD_ISENABLER2: For interrupts ID
	// Position of ISENABLER2 field.
	GICD_GICD_ISENABLER2_ISENABLER2_Pos = 0x0
	// Bit mask of ISENABLER2 field.
	GICD_GICD_ISENABLER2_ISENABLER2_Msk = 0xffffffff

	// GICD_ISENABLER3: For interrupts ID
	// Position of ISENABLER3 field.
	GICD_GICD_ISENABLER3_ISENABLER3_Pos = 0x0
	// Bit mask of ISENABLER3 field.
	GICD_GICD_ISENABLER3_ISENABLER3_Msk = 0xffffffff

	// GICD_ISENABLER4: For interrupts ID
	// Position of ISENABLER4 field.
	GICD_GICD_ISENABLER4_ISENABLER4_Pos = 0x0
	// Bit mask of ISENABLER4 field.
	GICD_GICD_ISENABLER4_ISENABLER4_Msk = 0xffffffff

	// GICD_ISENABLER5: For interrupts ID
	// Position of ISENABLER5 field.
	GICD_GICD_ISENABLER5_ISENABLER5_Pos = 0x0
	// Bit mask of ISENABLER5 field.
	GICD_GICD_ISENABLER5_ISENABLER5_Msk = 0xffffffff

	// GICD_ISENABLER6: For interrupts ID
	// Position of ISENABLER6 field.
	GICD_GICD_ISENABLER6_ISENABLER6_Pos = 0x0
	// Bit mask of ISENABLER6 field.
	GICD_GICD_ISENABLER6_ISENABLER6_Msk = 0xffffffff

	// GICD_ISENABLER7: For interrupts ID
	// Position of ISENABLER7 field.
	GICD_GICD_ISENABLER7_ISENABLER7_Pos = 0x0
	// Bit mask of ISENABLER7 field.
	GICD_GICD_ISENABLER7_ISENABLER7_Msk = 0xffffffff

	// GICD_ISENABLER8: For interrupts ID
	// Position of ISENABLER8 field.
	GICD_GICD_ISENABLER8_ISENABLER8_Pos = 0x0
	// Bit mask of ISENABLER8 field.
	GICD_GICD_ISENABLER8_ISENABLER8_Msk = 0xffffffff

	// GICD_ICENABLER0: For interrupts ID = 0 to ID = 31
	// Position of ICENABLER0 field.
	GICD_GICD_ICENABLER0_ICENABLER0_Pos = 0x0
	// Bit mask of ICENABLER0 field.
	GICD_GICD_ICENABLER0_ICENABLER0_Msk = 0xffffffff

	// GICD_ICENABLER1: For interrupts ID
	// Position of ICENABLER1 field.
	GICD_GICD_ICENABLER1_ICENABLER1_Pos = 0x0
	// Bit mask of ICENABLER1 field.
	GICD_GICD_ICENABLER1_ICENABLER1_Msk = 0xffffffff

	// GICD_ICENABLER2: For interrupts ID
	// Position of ICENABLER2 field.
	GICD_GICD_ICENABLER2_ICENABLER2_Pos = 0x0
	// Bit mask of ICENABLER2 field.
	GICD_GICD_ICENABLER2_ICENABLER2_Msk = 0xffffffff

	// GICD_ICENABLER3: For interrupts ID
	// Position of ICENABLER3 field.
	GICD_GICD_ICENABLER3_ICENABLER3_Pos = 0x0
	// Bit mask of ICENABLER3 field.
	GICD_GICD_ICENABLER3_ICENABLER3_Msk = 0xffffffff

	// GICD_ICENABLER4: For interrupts ID
	// Position of ICENABLER4 field.
	GICD_GICD_ICENABLER4_ICENABLER4_Pos = 0x0
	// Bit mask of ICENABLER4 field.
	GICD_GICD_ICENABLER4_ICENABLER4_Msk = 0xffffffff

	// GICD_ICENABLER5: For interrupts ID
	// Position of ICENABLER5 field.
	GICD_GICD_ICENABLER5_ICENABLER5_Pos = 0x0
	// Bit mask of ICENABLER5 field.
	GICD_GICD_ICENABLER5_ICENABLER5_Msk = 0xffffffff

	// GICD_ICENABLER6: For interrupts ID
	// Position of ICENABLER6 field.
	GICD_GICD_ICENABLER6_ICENABLER6_Pos = 0x0
	// Bit mask of ICENABLER6 field.
	GICD_GICD_ICENABLER6_ICENABLER6_Msk = 0xffffffff

	// GICD_ICENABLER7: For interrupts ID
	// Position of ICENABLER7 field.
	GICD_GICD_ICENABLER7_ICENABLER7_Pos = 0x0
	// Bit mask of ICENABLER7 field.
	GICD_GICD_ICENABLER7_ICENABLER7_Msk = 0xffffffff

	// GICD_ICENABLER8: For interrupts ID
	// Position of ICENABLER8 field.
	GICD_GICD_ICENABLER8_ICENABLER8_Pos = 0x0
	// Bit mask of ICENABLER8 field.
	GICD_GICD_ICENABLER8_ICENABLER8_Msk = 0xffffffff

	// GICD_ISPENDR0: For interrupts ID
	// Position of ISPENDR0 field.
	GICD_GICD_ISPENDR0_ISPENDR0_Pos = 0x0
	// Bit mask of ISPENDR0 field.
	GICD_GICD_ISPENDR0_ISPENDR0_Msk = 0xffffffff

	// GICD_ISPENDR1: For interrupts ID
	// Position of ISPENDR1 field.
	GICD_GICD_ISPENDR1_ISPENDR1_Pos = 0x0
	// Bit mask of ISPENDR1 field.
	GICD_GICD_ISPENDR1_ISPENDR1_Msk = 0xffffffff

	// GICD_ISPENDR2: For interrupts ID
	// Position of ISPENDR2 field.
	GICD_GICD_ISPENDR2_ISPENDR2_Pos = 0x0
	// Bit mask of ISPENDR2 field.
	GICD_GICD_ISPENDR2_ISPENDR2_Msk = 0xffffffff

	// GICD_ISPENDR3: For interrupts ID
	// Position of ISPENDR3 field.
	GICD_GICD_ISPENDR3_ISPENDR3_Pos = 0x0
	// Bit mask of ISPENDR3 field.
	GICD_GICD_ISPENDR3_ISPENDR3_Msk = 0xffffffff

	// GICD_ISPENDR4: For interrupts ID
	// Position of ISPENDR4 field.
	GICD_GICD_ISPENDR4_ISPENDR4_Pos = 0x0
	// Bit mask of ISPENDR4 field.
	GICD_GICD_ISPENDR4_ISPENDR4_Msk = 0xffffffff

	// GICD_ISPENDR5: For interrupts ID
	// Position of ISPENDR5 field.
	GICD_GICD_ISPENDR5_ISPENDR5_Pos = 0x0
	// Bit mask of ISPENDR5 field.
	GICD_GICD_ISPENDR5_ISPENDR5_Msk = 0xffffffff

	// GICD_ISPENDR6: For interrupts ID
	// Position of ISPENDR6 field.
	GICD_GICD_ISPENDR6_ISPENDR6_Pos = 0x0
	// Bit mask of ISPENDR6 field.
	GICD_GICD_ISPENDR6_ISPENDR6_Msk = 0xffffffff

	// GICD_ISPENDR7: For interrupts ID
	// Position of ISPENDR7 field.
	GICD_GICD_ISPENDR7_ISPENDR7_Pos = 0x0
	// Bit mask of ISPENDR7 field.
	GICD_GICD_ISPENDR7_ISPENDR7_Msk = 0xffffffff

	// GICD_ISPENDR8: For interrupts ID
	// Position of ISPENDR8 field.
	GICD_GICD_ISPENDR8_ISPENDR8_Pos = 0x0
	// Bit mask of ISPENDR8 field.
	GICD_GICD_ISPENDR8_ISPENDR8_Msk = 0xffffffff

	// GICD_ICPENDR0: For interrupts ID
	// Position of ICPENDR0 field.
	GICD_GICD_ICPENDR0_ICPENDR0_Pos = 0x0
	// Bit mask of ICPENDR0 field.
	GICD_GICD_ICPENDR0_ICPENDR0_Msk = 0xffffffff

	// GICD_ICPENDR1: For interrupts ID
	// Position of ICPENDR1 field.
	GICD_GICD_ICPENDR1_ICPENDR1_Pos = 0x0
	// Bit mask of ICPENDR1 field.
	GICD_GICD_ICPENDR1_ICPENDR1_Msk = 0xffffffff

	// GICD_ICPENDR2: For interrupts ID
	// Position of ICPENDR2 field.
	GICD_GICD_ICPENDR2_ICPENDR2_Pos = 0x0
	// Bit mask of ICPENDR2 field.
	GICD_GICD_ICPENDR2_ICPENDR2_Msk = 0xffffffff

	// GICD_ICPENDR3: For interrupts ID
	// Position of ICPENDR3 field.
	GICD_GICD_ICPENDR3_ICPENDR3_Pos = 0x0
	// Bit mask of ICPENDR3 field.
	GICD_GICD_ICPENDR3_ICPENDR3_Msk = 0xffffffff

	// GICD_ICPENDR4: For interrupts ID
	// Position of ICPENDR4 field.
	GICD_GICD_ICPENDR4_ICPENDR4_Pos = 0x0
	// Bit mask of ICPENDR4 field.
	GICD_GICD_ICPENDR4_ICPENDR4_Msk = 0xffffffff

	// GICD_ICPENDR5: For interrupts ID
	// Position of ICPENDR5 field.
	GICD_GICD_ICPENDR5_ICPENDR5_Pos = 0x0
	// Bit mask of ICPENDR5 field.
	GICD_GICD_ICPENDR5_ICPENDR5_Msk = 0xffffffff

	// GICD_ICPENDR6: For interrupts ID
	// Position of ICPENDR6 field.
	GICD_GICD_ICPENDR6_ICPENDR6_Pos = 0x0
	// Bit mask of ICPENDR6 field.
	GICD_GICD_ICPENDR6_ICPENDR6_Msk = 0xffffffff

	// GICD_ICPENDR7: For interrupts ID
	// Position of ICPENDR7 field.
	GICD_GICD_ICPENDR7_ICPENDR7_Pos = 0x0
	// Bit mask of ICPENDR7 field.
	GICD_GICD_ICPENDR7_ICPENDR7_Msk = 0xffffffff

	// GICD_ICPENDR8: For interrupts ID
	// Position of ICPENDR8 field.
	GICD_GICD_ICPENDR8_ICPENDR8_Pos = 0x0
	// Bit mask of ICPENDR8 field.
	GICD_GICD_ICPENDR8_ICPENDR8_Msk = 0xffffffff

	// GICD_ISACTIVER0: For interrupts ID
	// Position of ISACTIVER0 field.
	GICD_GICD_ISACTIVER0_ISACTIVER0_Pos = 0x0
	// Bit mask of ISACTIVER0 field.
	GICD_GICD_ISACTIVER0_ISACTIVER0_Msk = 0xffffffff

	// GICD_ISACTIVER1: For interrupts ID
	// Position of ISACTIVER1 field.
	GICD_GICD_ISACTIVER1_ISACTIVER1_Pos = 0x0
	// Bit mask of ISACTIVER1 field.
	GICD_GICD_ISACTIVER1_ISACTIVER1_Msk = 0xffffffff

	// GICD_ISACTIVER2: For interrupts ID
	// Position of ISACTIVER2 field.
	GICD_GICD_ISACTIVER2_ISACTIVER2_Pos = 0x0
	// Bit mask of ISACTIVER2 field.
	GICD_GICD_ISACTIVER2_ISACTIVER2_Msk = 0xffffffff

	// GICD_ISACTIVER3: For interrupts ID
	// Position of ISACTIVER3 field.
	GICD_GICD_ISACTIVER3_ISACTIVER3_Pos = 0x0
	// Bit mask of ISACTIVER3 field.
	GICD_GICD_ISACTIVER3_ISACTIVER3_Msk = 0xffffffff

	// GICD_ISACTIVER4: For interrupts ID
	// Position of ISACTIVER4 field.
	GICD_GICD_ISACTIVER4_ISACTIVER4_Pos = 0x0
	// Bit mask of ISACTIVER4 field.
	GICD_GICD_ISACTIVER4_ISACTIVER4_Msk = 0xffffffff

	// GICD_ISACTIVER5: For interrupts ID
	// Position of ISACTIVER5 field.
	GICD_GICD_ISACTIVER5_ISACTIVER5_Pos = 0x0
	// Bit mask of ISACTIVER5 field.
	GICD_GICD_ISACTIVER5_ISACTIVER5_Msk = 0xffffffff

	// GICD_ISACTIVER6: For interrupts ID
	// Position of ISACTIVER6 field.
	GICD_GICD_ISACTIVER6_ISACTIVER6_Pos = 0x0
	// Bit mask of ISACTIVER6 field.
	GICD_GICD_ISACTIVER6_ISACTIVER6_Msk = 0xffffffff

	// GICD_ISACTIVER7: For interrupts ID
	// Position of ISACTIVER7 field.
	GICD_GICD_ISACTIVER7_ISACTIVER7_Pos = 0x0
	// Bit mask of ISACTIVER7 field.
	GICD_GICD_ISACTIVER7_ISACTIVER7_Msk = 0xffffffff

	// GICD_ISACTIVER8: For interrupts ID
	// Position of ISACTIVER8 field.
	GICD_GICD_ISACTIVER8_ISACTIVER8_Pos = 0x0
	// Bit mask of ISACTIVER8 field.
	GICD_GICD_ISACTIVER8_ISACTIVER8_Msk = 0xffffffff

	// GICD_ICACTIVER0: For interrupts ID
	// Position of ICACTIVER0 field.
	GICD_GICD_ICACTIVER0_ICACTIVER0_Pos = 0x0
	// Bit mask of ICACTIVER0 field.
	GICD_GICD_ICACTIVER0_ICACTIVER0_Msk = 0xffffffff

	// GICD_ICACTIVER1: For interrupts ID
	// Position of ICACTIVER1 field.
	GICD_GICD_ICACTIVER1_ICACTIVER1_Pos = 0x0
	// Bit mask of ICACTIVER1 field.
	GICD_GICD_ICACTIVER1_ICACTIVER1_Msk = 0xffffffff

	// GICD_ICACTIVER2: For interrupts ID
	// Position of ICACTIVER2 field.
	GICD_GICD_ICACTIVER2_ICACTIVER2_Pos = 0x0
	// Bit mask of ICACTIVER2 field.
	GICD_GICD_ICACTIVER2_ICACTIVER2_Msk = 0xffffffff

	// GICD_ICACTIVER3: For interrupts ID
	// Position of ICACTIVER3 field.
	GICD_GICD_ICACTIVER3_ICACTIVER3_Pos = 0x0
	// Bit mask of ICACTIVER3 field.
	GICD_GICD_ICACTIVER3_ICACTIVER3_Msk = 0xffffffff

	// GICD_ICACTIVER4: For interrupts ID
	// Position of ICACTIVER4 field.
	GICD_GICD_ICACTIVER4_ICACTIVER4_Pos = 0x0
	// Bit mask of ICACTIVER4 field.
	GICD_GICD_ICACTIVER4_ICACTIVER4_Msk = 0xffffffff

	// GICD_ICACTIVER5: For interrupts ID
	// Position of ICACTIVER5 field.
	GICD_GICD_ICACTIVER5_ICACTIVER5_Pos = 0x0
	// Bit mask of ICACTIVER5 field.
	GICD_GICD_ICACTIVER5_ICACTIVER5_Msk = 0xffffffff

	// GICD_ICACTIVER6: For interrupts ID
	// Position of ICACTIVER6 field.
	GICD_GICD_ICACTIVER6_ICACTIVER6_Pos = 0x0
	// Bit mask of ICACTIVER6 field.
	GICD_GICD_ICACTIVER6_ICACTIVER6_Msk = 0xffffffff

	// GICD_ICACTIVER7: For interrupts ID
	// Position of ICACTIVER7 field.
	GICD_GICD_ICACTIVER7_ICACTIVER7_Pos = 0x0
	// Bit mask of ICACTIVER7 field.
	GICD_GICD_ICACTIVER7_ICACTIVER7_Msk = 0xffffffff

	// GICD_ICACTIVER8: For interrupts ID
	// Position of ICACTIVER8 field.
	GICD_GICD_ICACTIVER8_ICACTIVER8_Pos = 0x0
	// Bit mask of ICACTIVER8 field.
	GICD_GICD_ICACTIVER8_ICACTIVER8_Msk = 0xffffffff

	// GICD_IPRIORITYR0: GICD interrupt priority register 0
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR0_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR0_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR0_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR0_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR0_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR0_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR0_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR0_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR1: GICD interrupt priority register 1
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR1_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR1_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR1_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR1_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR1_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR1_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR1_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR1_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR2: GICD interrupt priority register 2
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR2_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR2_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR2_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR2_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR2_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR2_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR2_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR2_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR3: GICD interrupt priority register 3
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR3_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR3_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR3_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR3_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR3_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR3_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR3_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR3_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR4: GICD interrupt priority register 4
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR4_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR4_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR4_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR4_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR4_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR4_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR4_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR4_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR5: GICD interrupt priority register 5
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR5_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR5_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR5_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR5_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR5_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR5_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR5_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR5_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR6: GICD interrupt priority register 6
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR6_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR6_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR6_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR6_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR6_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR6_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR6_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR6_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR7: GICD interrupt priority register 7
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR7_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR7_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR7_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR7_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR7_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR7_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR7_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR7_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR8: GICD interrupt priority register 8
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR8_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR8_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR8_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR8_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR8_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR8_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR8_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR8_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR9: GICD interrupt priority register 9
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR9_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR9_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR9_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR9_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR9_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR9_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR9_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR9_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR10: GICD interrupt priority register 10
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR10_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR10_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR10_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR10_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR10_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR10_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR10_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR10_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR11: GICD interrupt priority register 11
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR11_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR11_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR11_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR11_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR11_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR11_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR11_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR11_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR12: GICD interrupt priority register 12
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR12_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR12_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR12_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR12_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR12_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR12_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR12_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR12_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR13: GICD interrupt priority register 13
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR13_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR13_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR13_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR13_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR13_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR13_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR13_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR13_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR14: GICD interrupt priority register 14
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR14_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR14_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR14_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR14_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR14_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR14_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR14_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR14_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR15: GICD interrupt priority register 15
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR15_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR15_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR15_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR15_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR15_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR15_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR15_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR15_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR16: GICD interrupt priority register 16
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR16_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR16_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR16_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR16_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR16_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR16_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR16_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR16_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR17: GICD interrupt priority register 17
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR17_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR17_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR17_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR17_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR17_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR17_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR17_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR17_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR18: GICD interrupt priority register 18
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR18_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR18_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR18_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR18_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR18_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR18_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR18_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR18_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR19: GICD interrupt priority register 19
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR19_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR19_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR19_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR19_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR19_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR19_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR19_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR19_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR20: GICD interrupt priority register 20
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR20_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR20_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR20_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR20_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR20_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR20_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR20_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR20_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR21: GICD interrupt priority register 21
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR21_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR21_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR21_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR21_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR21_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR21_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR21_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR21_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR22: GICD interrupt priority register 22
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR22_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR22_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR22_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR22_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR22_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR22_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR22_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR22_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR23: GICD interrupt priority register 23
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR23_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR23_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR23_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR23_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR23_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR23_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR23_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR23_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR24: GICD interrupt priority register 24
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR24_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR24_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR24_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR24_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR24_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR24_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR24_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR24_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR25: GICD interrupt priority register 25
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR25_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR25_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR25_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR25_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR25_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR25_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR25_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR25_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR26: GICD interrupt priority register 26
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR26_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR26_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR26_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR26_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR26_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR26_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR26_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR26_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR27: GICD interrupt priority register 27
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR27_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR27_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR27_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR27_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR27_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR27_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR27_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR27_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR28: GICD interrupt priority register 28
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR28_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR28_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR28_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR28_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR28_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR28_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR28_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR28_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR29: GICD interrupt priority register 29
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR29_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR29_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR29_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR29_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR29_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR29_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR29_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR29_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR30: GICD interrupt priority register 30
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR30_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR30_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR30_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR30_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR30_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR30_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR30_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR30_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR31: GICD interrupt priority register 31
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR31_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR31_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR31_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR31_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR31_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR31_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR31_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR31_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR32: GICD interrupt priority register 32
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR32_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR32_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR32_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR32_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR32_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR32_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR32_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR32_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR33: GICD interrupt priority register 33
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR33_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR33_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR33_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR33_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR33_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR33_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR33_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR33_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR34: GICD interrupt priority register 34
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR34_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR34_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR34_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR34_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR34_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR34_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR34_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR34_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR35: GICD interrupt priority register 35
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR35_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR35_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR35_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR35_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR35_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR35_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR35_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR35_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR36: GICD interrupt priority register 36
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR36_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR36_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR36_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR36_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR36_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR36_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR36_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR36_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR37: GICD interrupt priority register 37
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR37_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR37_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR37_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR37_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR37_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR37_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR37_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR37_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR38: GICD interrupt priority register 38
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR38_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR38_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR38_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR38_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR38_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR38_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR38_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR38_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR39: GICD interrupt priority register 39
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR39_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR39_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR39_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR39_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR39_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR39_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR39_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR39_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR40: GICD interrupt priority register 40
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR40_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR40_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR40_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR40_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR40_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR40_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR40_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR40_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR41: GICD interrupt priority register 41
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR41_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR41_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR41_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR41_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR41_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR41_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR41_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR41_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR42: GICD interrupt priority register 42
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR42_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR42_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR42_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR42_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR42_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR42_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR42_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR42_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR43: GICD interrupt priority register 43
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR43_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR43_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR43_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR43_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR43_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR43_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR43_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR43_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR44: GICD interrupt priority register 44
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR44_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR44_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR44_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR44_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR44_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR44_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR44_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR44_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR45: GICD interrupt priority register 45
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR45_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR45_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR45_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR45_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR45_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR45_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR45_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR45_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR46: GICD interrupt priority register 46
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR46_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR46_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR46_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR46_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR46_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR46_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR46_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR46_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR47: GICD interrupt priority register 47
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR47_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR47_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR47_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR47_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR47_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR47_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR47_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR47_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR48: GICD interrupt priority register 48
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR48_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR48_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR48_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR48_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR48_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR48_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR48_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR48_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR49: GICD interrupt priority register 49
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR49_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR49_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR49_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR49_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR49_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR49_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR49_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR49_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR50: GICD interrupt priority register 50
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR50_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR50_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR50_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR50_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR50_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR50_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR50_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR50_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR51: GICD interrupt priority register 51
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR51_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR51_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR51_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR51_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR51_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR51_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR51_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR51_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR52: GICD interrupt priority register 52
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR52_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR52_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR52_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR52_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR52_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR52_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR52_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR52_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR53: GICD interrupt priority register 53
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR53_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR53_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR53_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR53_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR53_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR53_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR53_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR53_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR54: GICD interrupt priority register 54
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR54_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR54_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR54_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR54_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR54_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR54_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR54_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR54_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR55: GICD interrupt priority register 55
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR55_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR55_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR55_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR55_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR55_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR55_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR55_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR55_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR56: GICD interrupt priority register 56
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR56_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR56_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR56_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR56_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR56_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR56_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR56_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR56_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR57: GICD interrupt priority register 57
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR57_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR57_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR57_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR57_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR57_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR57_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR57_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR57_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR58: GICD interrupt priority register 58
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR58_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR58_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR58_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR58_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR58_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR58_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR58_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR58_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR59: GICD interrupt priority register 59
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR59_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR59_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR59_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR59_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR59_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR59_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR59_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR59_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR60: GICD interrupt priority register 60
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR60_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR60_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR60_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR60_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR60_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR60_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR60_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR60_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR61: GICD interrupt priority register 61
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR61_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR61_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR61_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR61_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR61_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR61_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR61_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR61_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR62: GICD interrupt priority register 62
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR62_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR62_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR62_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR62_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR62_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR62_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR62_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR62_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR63: GICD interrupt priority register 63
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR63_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR63_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR63_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR63_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR63_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR63_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR63_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR63_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR64: GICD interrupt priority register 64
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR64_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR64_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR64_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR64_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR64_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR64_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR64_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR64_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR65: GICD interrupt priority register 65
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR65_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR65_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR65_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR65_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR65_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR65_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR65_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR65_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR66: GICD interrupt priority register 66
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR66_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR66_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR66_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR66_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR66_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR66_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR66_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR66_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR67: GICD interrupt priority register 67
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR67_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR67_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR67_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR67_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR67_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR67_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR67_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR67_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR68: GICD interrupt priority register 68
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR68_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR68_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR68_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR68_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR68_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR68_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR68_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR68_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR69: GICD interrupt priority register 69
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR69_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR69_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR69_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR69_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR69_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR69_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR69_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR69_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR70: GICD interrupt priority register 70
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR70_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR70_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR70_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR70_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR70_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR70_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR70_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR70_PRIORITY3_Msk = 0xf8000000

	// GICD_IPRIORITYR71: GICD interrupt priority register 71
	// Position of PRIORITY0 field.
	GICD_GICD_IPRIORITYR71_PRIORITY0_Pos = 0x3
	// Bit mask of PRIORITY0 field.
	GICD_GICD_IPRIORITYR71_PRIORITY0_Msk = 0xf8
	// Position of PRIORITY1 field.
	GICD_GICD_IPRIORITYR71_PRIORITY1_Pos = 0xb
	// Bit mask of PRIORITY1 field.
	GICD_GICD_IPRIORITYR71_PRIORITY1_Msk = 0xf800
	// Position of PRIORITY2 field.
	GICD_GICD_IPRIORITYR71_PRIORITY2_Pos = 0x13
	// Bit mask of PRIORITY2 field.
	GICD_GICD_IPRIORITYR71_PRIORITY2_Msk = 0xf80000
	// Position of PRIORITY3 field.
	GICD_GICD_IPRIORITYR71_PRIORITY3_Pos = 0x1b
	// Bit mask of PRIORITY3 field.
	GICD_GICD_IPRIORITYR71_PRIORITY3_Msk = 0xf8000000

	// GICD_ITARGETSR0: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR0_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR1: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR1_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR2: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR2_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR3: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR3_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR4: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR4_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR5: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR5_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR6: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR6_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR7: For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR7_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR8: GICD interrupt processor target register 8
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR8_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR9: GICD interrupt processor target register 9
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR9_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR10: GICD interrupt processor target register 10
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR10_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR11: GICD interrupt processor target register 11
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR11_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR12: GICD interrupt processor target register 12
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR12_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR13: GICD interrupt processor target register 13
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR13_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR14: GICD interrupt processor target register 14
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR14_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR15: GICD interrupt processor target register 15
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR15_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR16: GICD interrupt processor target register 16
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR16_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR17: GICD interrupt processor target register 17
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR17_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR18: GICD interrupt processor target register 18
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR18_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR19: GICD interrupt processor target register 19
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR19_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR20: GICD interrupt processor target register 20
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR20_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR21: GICD interrupt processor target register 21
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR21_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR22: GICD interrupt processor target register 22
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR22_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR23: GICD interrupt processor target register 23
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR23_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR24: GICD interrupt processor target register 24
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR24_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR25: GICD interrupt processor target register 25
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR25_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR26: GICD interrupt processor target register 26
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR26_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR27: GICD interrupt processor target register 27
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR27_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR28: GICD interrupt processor target register 28
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR28_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR29: GICD interrupt processor target register 29
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR29_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR30: GICD interrupt processor target register 30
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR30_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR31: GICD interrupt processor target register 31
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR31_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR32: GICD interrupt processor target register 32
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR32_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR33: GICD interrupt processor target register 33
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR33_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR34: GICD interrupt processor target register 34
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR34_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR35: GICD interrupt processor target register 35
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR35_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR36: GICD interrupt processor target register 36
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR36_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR37: GICD interrupt processor target register 37
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR37_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR38: GICD interrupt processor target register 38
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR38_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR39: GICD interrupt processor target register 39
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR39_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR40: GICD interrupt processor target register 40
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR40_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR41: GICD interrupt processor target register 41
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR41_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR42: GICD interrupt processor target register 42
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR42_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR43: GICD interrupt processor target register 43
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR43_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR44: GICD interrupt processor target register 44
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR44_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR45: GICD interrupt processor target register 45
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR45_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR46: GICD interrupt processor target register 46
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR46_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR47: GICD interrupt processor target register 47
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR47_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR48: GICD interrupt processor target register 48
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR48_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR49: GICD interrupt processor target register 49
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR49_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR50: GICD interrupt processor target register 50
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR50_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR51: GICD interrupt processor target register 51
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR51_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR52: GICD interrupt processor target register 52
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR52_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR53: GICD interrupt processor target register 53
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR53_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR54: GICD interrupt processor target register 54
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR54_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR55: GICD interrupt processor target register 55
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR55_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR56: GICD interrupt processor target register 56
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR56_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR57: GICD interrupt processor target register 57
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR57_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR58: GICD interrupt processor target register 58
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR58_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR59: GICD interrupt processor target register 59
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR59_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR60: GICD interrupt processor target register 60
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR60_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR61: GICD interrupt processor target register 61
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR61_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR62: GICD interrupt processor target register 62
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR62_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR63: GICD interrupt processor target register 63
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR63_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR64: GICD interrupt processor target register 64
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR64_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR65: GICD interrupt processor target register 65
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR65_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR66: GICD interrupt processor target register 66
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR66_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR67: GICD interrupt processor target register 67
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR67_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR68: GICD interrupt processor target register 68
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR68_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR69: GICD interrupt processor target register 69
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR69_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR70: GICD interrupt processor target register 70
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR70_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ITARGETSR71: GICD interrupt processor target register 71
	// Position of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS0_Pos = 0x0
	// Bit mask of CPU_TARGETS0 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS0_Msk = 0x3
	// Position of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS1_Pos = 0x8
	// Bit mask of CPU_TARGETS1 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS1_Msk = 0x300
	// Position of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS2_Pos = 0x10
	// Bit mask of CPU_TARGETS2 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS2_Msk = 0x30000
	// Position of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS3_Pos = 0x18
	// Bit mask of CPU_TARGETS3 field.
	GICD_GICD_ITARGETSR71_CPU_TARGETS3_Msk = 0x3000000

	// GICD_ICFGR0: GICD interrupt configuration register
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR0_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR0_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR0_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR0_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR0_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR0_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR0_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR0_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR0_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR0_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR0_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR0_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR0_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR0_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR0_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR0_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR0_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR0_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR0_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR0_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR0_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR0_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR0_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR0_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR0_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR0_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR0_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR0_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR0_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR0_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR0_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR0_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR1: GICD interrupt configuration register
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR1_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR1_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR1_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR1_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR1_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR1_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR1_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR1_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR1_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR1_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR1_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR1_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR1_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR1_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR1_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR1_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR1_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR1_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR1_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR1_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR1_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR1_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR1_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR1_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR1_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR1_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR1_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR1_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR1_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR1_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR1_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR1_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR2: GICD interrupt configuration register 2
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR2_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR2_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR2_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR2_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR2_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR2_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR2_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR2_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR2_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR2_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR2_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR2_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR2_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR2_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR2_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR2_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR2_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR2_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR2_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR2_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR2_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR2_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR2_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR2_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR2_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR2_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR2_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR2_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR2_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR2_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR2_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR2_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR3: GICD interrupt configuration register 3
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR3_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR3_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR3_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR3_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR3_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR3_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR3_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR3_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR3_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR3_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR3_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR3_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR3_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR3_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR3_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR3_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR3_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR3_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR3_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR3_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR3_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR3_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR3_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR3_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR3_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR3_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR3_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR3_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR3_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR3_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR3_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR3_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR4: GICD interrupt configuration register 4
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR4_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR4_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR4_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR4_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR4_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR4_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR4_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR4_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR4_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR4_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR4_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR4_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR4_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR4_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR4_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR4_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR4_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR4_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR4_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR4_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR4_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR4_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR4_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR4_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR4_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR4_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR4_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR4_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR4_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR4_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR4_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR4_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR5: GICD interrupt configuration register 5
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR5_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR5_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR5_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR5_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR5_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR5_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR5_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR5_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR5_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR5_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR5_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR5_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR5_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR5_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR5_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR5_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR5_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR5_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR5_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR5_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR5_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR5_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR5_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR5_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR5_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR5_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR5_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR5_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR5_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR5_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR5_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR5_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR6: GICD interrupt configuration register 6
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR6_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR6_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR6_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR6_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR6_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR6_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR6_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR6_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR6_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR6_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR6_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR6_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR6_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR6_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR6_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR6_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR6_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR6_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR6_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR6_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR6_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR6_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR6_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR6_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR6_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR6_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR6_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR6_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR6_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR6_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR6_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR6_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR7: GICD interrupt configuration register 7
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR7_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR7_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR7_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR7_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR7_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR7_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR7_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR7_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR7_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR7_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR7_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR7_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR7_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR7_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR7_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR7_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR7_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR7_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR7_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR7_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR7_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR7_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR7_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR7_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR7_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR7_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR7_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR7_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR7_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR7_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR7_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR7_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR8: GICD interrupt configuration register 8
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR8_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR8_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR8_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR8_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR8_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR8_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR8_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR8_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR8_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR8_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR8_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR8_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR8_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR8_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR8_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR8_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR8_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR8_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR8_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR8_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR8_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR8_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR8_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR8_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR8_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR8_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR8_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR8_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR8_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR8_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR8_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR8_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR9: GICD interrupt configuration register 9
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR9_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR9_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR9_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR9_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR9_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR9_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR9_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR9_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR9_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR9_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR9_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR9_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR9_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR9_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR9_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR9_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR9_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR9_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR9_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR9_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR9_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR9_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR9_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR9_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR9_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR9_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR9_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR9_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR9_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR9_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR9_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR9_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR10: GICD interrupt configuration register 10
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR10_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR10_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR10_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR10_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR10_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR10_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR10_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR10_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR10_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR10_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR10_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR10_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR10_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR10_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR10_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR10_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR10_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR10_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR10_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR10_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR10_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR10_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR10_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR10_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR10_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR10_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR10_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR10_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR10_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR10_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR10_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR10_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR11: GICD interrupt configuration register 11
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR11_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR11_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR11_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR11_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR11_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR11_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR11_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR11_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR11_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR11_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR11_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR11_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR11_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR11_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR11_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR11_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR11_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR11_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR11_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR11_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR11_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR11_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR11_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR11_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR11_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR11_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR11_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR11_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR11_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR11_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR11_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR11_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR12: GICD interrupt configuration register 12
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR12_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR12_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR12_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR12_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR12_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR12_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR12_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR12_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR12_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR12_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR12_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR12_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR12_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR12_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR12_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR12_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR12_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR12_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR12_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR12_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR12_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR12_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR12_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR12_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR12_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR12_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR12_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR12_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR12_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR12_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR12_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR12_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR13: GICD interrupt configuration register 13
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR13_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR13_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR13_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR13_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR13_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR13_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR13_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR13_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR13_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR13_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR13_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR13_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR13_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR13_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR13_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR13_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR13_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR13_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR13_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR13_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR13_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR13_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR13_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR13_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR13_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR13_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR13_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR13_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR13_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR13_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR13_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR13_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR14: GICD interrupt configuration register 14
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR14_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR14_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR14_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR14_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR14_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR14_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR14_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR14_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR14_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR14_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR14_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR14_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR14_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR14_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR14_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR14_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR14_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR14_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR14_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR14_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR14_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR14_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR14_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR14_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR14_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR14_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR14_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR14_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR14_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR14_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR14_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR14_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR15: GICD interrupt configuration register 15
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR15_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR15_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR15_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR15_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR15_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR15_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR15_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR15_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR15_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR15_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR15_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR15_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR15_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR15_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR15_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR15_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR15_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR15_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR15_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR15_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR15_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR15_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR15_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR15_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR15_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR15_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR15_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR15_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR15_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR15_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR15_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR15_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR16: GICD interrupt configuration register 16
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR16_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR16_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR16_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR16_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR16_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR16_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR16_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR16_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR16_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR16_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR16_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR16_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR16_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR16_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR16_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR16_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR16_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR16_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR16_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR16_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR16_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR16_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR16_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR16_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR16_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR16_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR16_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR16_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR16_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR16_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR16_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR16_INT_CONFIG15_Msk = 0xc0000000

	// GICD_ICFGR17: GICD interrupt configuration register 17
	// Position of INT_CONFIG0 field.
	GICD_GICD_ICFGR17_INT_CONFIG0_Pos = 0x0
	// Bit mask of INT_CONFIG0 field.
	GICD_GICD_ICFGR17_INT_CONFIG0_Msk = 0x3
	// Position of INT_CONFIG1 field.
	GICD_GICD_ICFGR17_INT_CONFIG1_Pos = 0x2
	// Bit mask of INT_CONFIG1 field.
	GICD_GICD_ICFGR17_INT_CONFIG1_Msk = 0xc
	// Position of INT_CONFIG2 field.
	GICD_GICD_ICFGR17_INT_CONFIG2_Pos = 0x4
	// Bit mask of INT_CONFIG2 field.
	GICD_GICD_ICFGR17_INT_CONFIG2_Msk = 0x30
	// Position of INT_CONFIG3 field.
	GICD_GICD_ICFGR17_INT_CONFIG3_Pos = 0x6
	// Bit mask of INT_CONFIG3 field.
	GICD_GICD_ICFGR17_INT_CONFIG3_Msk = 0xc0
	// Position of INT_CONFIG4 field.
	GICD_GICD_ICFGR17_INT_CONFIG4_Pos = 0x8
	// Bit mask of INT_CONFIG4 field.
	GICD_GICD_ICFGR17_INT_CONFIG4_Msk = 0x300
	// Position of INT_CONFIG5 field.
	GICD_GICD_ICFGR17_INT_CONFIG5_Pos = 0xa
	// Bit mask of INT_CONFIG5 field.
	GICD_GICD_ICFGR17_INT_CONFIG5_Msk = 0xc00
	// Position of INT_CONFIG6 field.
	GICD_GICD_ICFGR17_INT_CONFIG6_Pos = 0xc
	// Bit mask of INT_CONFIG6 field.
	GICD_GICD_ICFGR17_INT_CONFIG6_Msk = 0x3000
	// Position of INT_CONFIG7 field.
	GICD_GICD_ICFGR17_INT_CONFIG7_Pos = 0xe
	// Bit mask of INT_CONFIG7 field.
	GICD_GICD_ICFGR17_INT_CONFIG7_Msk = 0xc000
	// Position of INT_CONFIG8 field.
	GICD_GICD_ICFGR17_INT_CONFIG8_Pos = 0x10
	// Bit mask of INT_CONFIG8 field.
	GICD_GICD_ICFGR17_INT_CONFIG8_Msk = 0x30000
	// Position of INT_CONFIG9 field.
	GICD_GICD_ICFGR17_INT_CONFIG9_Pos = 0x12
	// Bit mask of INT_CONFIG9 field.
	GICD_GICD_ICFGR17_INT_CONFIG9_Msk = 0xc0000
	// Position of INT_CONFIG10 field.
	GICD_GICD_ICFGR17_INT_CONFIG10_Pos = 0x14
	// Bit mask of INT_CONFIG10 field.
	GICD_GICD_ICFGR17_INT_CONFIG10_Msk = 0x300000
	// Position of INT_CONFIG11 field.
	GICD_GICD_ICFGR17_INT_CONFIG11_Pos = 0x16
	// Bit mask of INT_CONFIG11 field.
	GICD_GICD_ICFGR17_INT_CONFIG11_Msk = 0xc00000
	// Position of INT_CONFIG12 field.
	GICD_GICD_ICFGR17_INT_CONFIG12_Pos = 0x18
	// Bit mask of INT_CONFIG12 field.
	GICD_GICD_ICFGR17_INT_CONFIG12_Msk = 0x3000000
	// Position of INT_CONFIG13 field.
	GICD_GICD_ICFGR17_INT_CONFIG13_Pos = 0x1a
	// Bit mask of INT_CONFIG13 field.
	GICD_GICD_ICFGR17_INT_CONFIG13_Msk = 0xc000000
	// Position of INT_CONFIG14 field.
	GICD_GICD_ICFGR17_INT_CONFIG14_Pos = 0x1c
	// Bit mask of INT_CONFIG14 field.
	GICD_GICD_ICFGR17_INT_CONFIG14_Msk = 0x30000000
	// Position of INT_CONFIG15 field.
	GICD_GICD_ICFGR17_INT_CONFIG15_Pos = 0x1e
	// Bit mask of INT_CONFIG15 field.
	GICD_GICD_ICFGR17_INT_CONFIG15_Msk = 0xc0000000

	// GICD_PPISR: GICD private peripheral interrupt status register
	// Position of PPI6 field.
	GICD_GICD_PPISR_PPI6_Pos = 0x9
	// Bit mask of PPI6 field.
	GICD_GICD_PPISR_PPI6_Msk = 0x200
	// Bit PPI6.
	GICD_GICD_PPISR_PPI6 = 0x200
	// Position of PPI5 field.
	GICD_GICD_PPISR_PPI5_Pos = 0xa
	// Bit mask of PPI5 field.
	GICD_GICD_PPISR_PPI5_Msk = 0x400
	// Bit PPI5.
	GICD_GICD_PPISR_PPI5 = 0x400
	// Position of PPI4 field.
	GICD_GICD_PPISR_PPI4_Pos = 0xb
	// Bit mask of PPI4 field.
	GICD_GICD_PPISR_PPI4_Msk = 0x800
	// Bit PPI4.
	GICD_GICD_PPISR_PPI4 = 0x800
	// Position of PPI0 field.
	GICD_GICD_PPISR_PPI0_Pos = 0xc
	// Bit mask of PPI0 field.
	GICD_GICD_PPISR_PPI0_Msk = 0x1000
	// Bit PPI0.
	GICD_GICD_PPISR_PPI0 = 0x1000
	// Position of PPI1 field.
	GICD_GICD_PPISR_PPI1_Pos = 0xd
	// Bit mask of PPI1 field.
	GICD_GICD_PPISR_PPI1_Msk = 0x2000
	// Bit PPI1.
	GICD_GICD_PPISR_PPI1 = 0x2000
	// Position of PPI2 field.
	GICD_GICD_PPISR_PPI2_Pos = 0xe
	// Bit mask of PPI2 field.
	GICD_GICD_PPISR_PPI2_Msk = 0x4000
	// Bit PPI2.
	GICD_GICD_PPISR_PPI2 = 0x4000
	// Position of PPI3 field.
	GICD_GICD_PPISR_PPI3_Pos = 0xf
	// Bit mask of PPI3 field.
	GICD_GICD_PPISR_PPI3_Msk = 0x8000
	// Bit PPI3.
	GICD_GICD_PPISR_PPI3 = 0x8000

	// GICD_SPISR1: For interrupts ID = SPI number+32, from SPI [x*32+31] to SPI [x*32]
	// Position of SPISR1 field.
	GICD_GICD_SPISR1_SPISR1_Pos = 0x0
	// Bit mask of SPISR1 field.
	GICD_GICD_SPISR1_SPISR1_Msk = 0xffffffff

	// GICD_SPISR2: For interrupts ID
	// Position of SPISR2 field.
	GICD_GICD_SPISR2_SPISR2_Pos = 0x0
	// Bit mask of SPISR2 field.
	GICD_GICD_SPISR2_SPISR2_Msk = 0xffffffff

	// GICD_SPISR3: For interrupts ID
	// Position of SPISR3 field.
	GICD_GICD_SPISR3_SPISR3_Pos = 0x0
	// Bit mask of SPISR3 field.
	GICD_GICD_SPISR3_SPISR3_Msk = 0xffffffff

	// GICD_SPISR4: For interrupts ID
	// Position of SPISR4 field.
	GICD_GICD_SPISR4_SPISR4_Pos = 0x0
	// Bit mask of SPISR4 field.
	GICD_GICD_SPISR4_SPISR4_Msk = 0xffffffff

	// GICD_SPISR5: For interrupts ID
	// Position of SPISR5 field.
	GICD_GICD_SPISR5_SPISR5_Pos = 0x0
	// Bit mask of SPISR5 field.
	GICD_GICD_SPISR5_SPISR5_Msk = 0xffffffff

	// GICD_SPISR6: For interrupts ID
	// Position of SPISR6 field.
	GICD_GICD_SPISR6_SPISR6_Pos = 0x0
	// Bit mask of SPISR6 field.
	GICD_GICD_SPISR6_SPISR6_Msk = 0xffffffff

	// GICD_SPISR7: For interrupts ID
	// Position of SPISR7 field.
	GICD_GICD_SPISR7_SPISR7_Pos = 0x0
	// Bit mask of SPISR7 field.
	GICD_GICD_SPISR7_SPISR7_Msk = 0xffffffff

	// GICD_SGIR: GICD software generated interrupt register
	// Position of SGIINTID field.
	GICD_GICD_SGIR_SGIINTID_Pos = 0x0
	// Bit mask of SGIINTID field.
	GICD_GICD_SGIR_SGIINTID_Msk = 0xf
	// Position of NSATT field.
	GICD_GICD_SGIR_NSATT_Pos = 0xf
	// Bit mask of NSATT field.
	GICD_GICD_SGIR_NSATT_Msk = 0x8000
	// Bit NSATT.
	GICD_GICD_SGIR_NSATT = 0x8000
	// Position of CPUTARGETLIST field.
	GICD_GICD_SGIR_CPUTARGETLIST_Pos = 0x10
	// Bit mask of CPUTARGETLIST field.
	GICD_GICD_SGIR_CPUTARGETLIST_Msk = 0x30000
	// Position of TARGETLISTFILTER field.
	GICD_GICD_SGIR_TARGETLISTFILTER_Pos = 0x18
	// Bit mask of TARGETLISTFILTER field.
	GICD_GICD_SGIR_TARGETLISTFILTER_Msk = 0x3000000

	// GICD_CPENDSGIR0: For SGI x*4 to SGI x*4+3
	// Position of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING0_Pos = 0x0
	// Bit mask of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING0_Msk = 0x3
	// Position of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING1_Pos = 0x8
	// Bit mask of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING1_Msk = 0x300
	// Position of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING2_Pos = 0x10
	// Bit mask of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING2_Msk = 0x30000
	// Position of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING3_Pos = 0x18
	// Bit mask of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR0_SGI_CLEAR_PENDING3_Msk = 0x3000000

	// GICD_CPENDSGIR1: For SGI x*4 to SGI x*4+3
	// Position of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING0_Pos = 0x0
	// Bit mask of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING0_Msk = 0x3
	// Position of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING1_Pos = 0x8
	// Bit mask of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING1_Msk = 0x300
	// Position of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING2_Pos = 0x10
	// Bit mask of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING2_Msk = 0x30000
	// Position of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING3_Pos = 0x18
	// Bit mask of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR1_SGI_CLEAR_PENDING3_Msk = 0x3000000

	// GICD_CPENDSGIR2: For SGI x*4 to SGI x*4+3
	// Position of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING0_Pos = 0x0
	// Bit mask of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING0_Msk = 0x3
	// Position of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING1_Pos = 0x8
	// Bit mask of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING1_Msk = 0x300
	// Position of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING2_Pos = 0x10
	// Bit mask of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING2_Msk = 0x30000
	// Position of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING3_Pos = 0x18
	// Bit mask of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR2_SGI_CLEAR_PENDING3_Msk = 0x3000000

	// GICD_CPENDSGIR3: For SGI x*4 to SGI x*4+3
	// Position of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING0_Pos = 0x0
	// Bit mask of SGI_CLEAR_PENDING0 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING0_Msk = 0x3
	// Position of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING1_Pos = 0x8
	// Bit mask of SGI_CLEAR_PENDING1 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING1_Msk = 0x300
	// Position of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING2_Pos = 0x10
	// Bit mask of SGI_CLEAR_PENDING2 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING2_Msk = 0x30000
	// Position of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING3_Pos = 0x18
	// Bit mask of SGI_CLEAR_PENDING3 field.
	GICD_GICD_CPENDSGIR3_SGI_CLEAR_PENDING3_Msk = 0x3000000

	// GICD_SPENDSGIR0: For SGI x*4 to SGI x*4+3
	// Position of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING0_Pos = 0x0
	// Bit mask of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING0_Msk = 0x3
	// Position of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING1_Pos = 0x8
	// Bit mask of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING1_Msk = 0x300
	// Position of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING2_Pos = 0x10
	// Bit mask of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING2_Msk = 0x30000
	// Position of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING3_Pos = 0x18
	// Bit mask of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR0_SGI_SET_PENDING3_Msk = 0x3000000

	// GICD_SPENDSGIR1: For SGI x*4 to SGI x*4+3
	// Position of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING0_Pos = 0x0
	// Bit mask of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING0_Msk = 0x3
	// Position of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING1_Pos = 0x8
	// Bit mask of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING1_Msk = 0x300
	// Position of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING2_Pos = 0x10
	// Bit mask of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING2_Msk = 0x30000
	// Position of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING3_Pos = 0x18
	// Bit mask of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR1_SGI_SET_PENDING3_Msk = 0x3000000

	// GICD_SPENDSGIR2: For SGI x*4 to SGI x*4+3
	// Position of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING0_Pos = 0x0
	// Bit mask of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING0_Msk = 0x3
	// Position of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING1_Pos = 0x8
	// Bit mask of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING1_Msk = 0x300
	// Position of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING2_Pos = 0x10
	// Bit mask of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING2_Msk = 0x30000
	// Position of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING3_Pos = 0x18
	// Bit mask of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR2_SGI_SET_PENDING3_Msk = 0x3000000

	// GICD_SPENDSGIR3: For SGI x*4 to SGI x*4+3
	// Position of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING0_Pos = 0x0
	// Bit mask of SGI_SET_PENDING0 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING0_Msk = 0x3
	// Position of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING1_Pos = 0x8
	// Bit mask of SGI_SET_PENDING1 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING1_Msk = 0x300
	// Position of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING2_Pos = 0x10
	// Bit mask of SGI_SET_PENDING2 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING2_Msk = 0x30000
	// Position of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING3_Pos = 0x18
	// Bit mask of SGI_SET_PENDING3 field.
	GICD_GICD_SPENDSGIR3_SGI_SET_PENDING3_Msk = 0x3000000

	// GICD_PIDR4: GICD peripheral ID4 register
	// Position of PIDR4 field.
	GICD_GICD_PIDR4_PIDR4_Pos = 0x0
	// Bit mask of PIDR4 field.
	GICD_GICD_PIDR4_PIDR4_Msk = 0xffffffff

	// GICD_PIDR5: GICD peripheral ID5 to ID7 register 5
	// Position of PIDR5 field.
	GICD_GICD_PIDR5_PIDR5_Pos = 0x0
	// Bit mask of PIDR5 field.
	GICD_GICD_PIDR5_PIDR5_Msk = 0xffffffff

	// GICD_PIDR6: GICD peripheral ID5 to ID7 register 6
	// Position of PIDR6 field.
	GICD_GICD_PIDR6_PIDR6_Pos = 0x0
	// Bit mask of PIDR6 field.
	GICD_GICD_PIDR6_PIDR6_Msk = 0xffffffff

	// GICD_PIDR7: GICD peripheral ID5 to ID7 register 7
	// Position of PIDR7 field.
	GICD_GICD_PIDR7_PIDR7_Pos = 0x0
	// Bit mask of PIDR7 field.
	GICD_GICD_PIDR7_PIDR7_Msk = 0xffffffff

	// GICD_PIDR0: GICD peripheral ID0 register
	// Position of PIDR0 field.
	GICD_GICD_PIDR0_PIDR0_Pos = 0x0
	// Bit mask of PIDR0 field.
	GICD_GICD_PIDR0_PIDR0_Msk = 0xffffffff

	// GICD_PIDR1: GICD peripheral ID1 register
	// Position of PIDR1 field.
	GICD_GICD_PIDR1_PIDR1_Pos = 0x0
	// Bit mask of PIDR1 field.
	GICD_GICD_PIDR1_PIDR1_Msk = 0xffffffff

	// GICD_PIDR2: GICD peripheral ID2 register
	// Position of PIDR2 field.
	GICD_GICD_PIDR2_PIDR2_Pos = 0x0
	// Bit mask of PIDR2 field.
	GICD_GICD_PIDR2_PIDR2_Msk = 0xffffffff

	// GICD_PIDR3: GICD peripheral ID3 register
	// Position of PIDR3 field.
	GICD_GICD_PIDR3_PIDR3_Pos = 0x0
	// Bit mask of PIDR3 field.
	GICD_GICD_PIDR3_PIDR3_Msk = 0xffffffff

	// GICD_CIDR0: GICD component ID0 register
	// Position of CIDR0 field.
	GICD_GICD_CIDR0_CIDR0_Pos = 0x0
	// Bit mask of CIDR0 field.
	GICD_GICD_CIDR0_CIDR0_Msk = 0xffffffff

	// GICD_CIDR1: GICD component ID1 register
	// Position of CIDR1 field.
	GICD_GICD_CIDR1_CIDR1_Pos = 0x0
	// Bit mask of CIDR1 field.
	GICD_GICD_CIDR1_CIDR1_Msk = 0xffffffff

	// GICD_CIDR2: GICD component ID2 register
	// Position of CIDR2 field.
	GICD_GICD_CIDR2_CIDR2_Pos = 0x0
	// Bit mask of CIDR2 field.
	GICD_GICD_CIDR2_CIDR2_Msk = 0xffffffff

	// GICD_CIDR3: GICD component ID3 register
	// Position of CIDR3 field.
	GICD_GICD_CIDR3_CIDR3_Pos = 0x0
	// Bit mask of CIDR3 field.
	GICD_GICD_CIDR3_CIDR3_Msk = 0xffffffff
)

// Bitfields for GICH: GICH
const (
	// GICH_HCR: GICH hypervisor control register
	// Position of EN field.
	GICH_GICH_HCR_EN_Pos = 0x0
	// Bit mask of EN field.
	GICH_GICH_HCR_EN_Msk = 0x1
	// Bit EN.
	GICH_GICH_HCR_EN = 0x1
	// Position of UIE field.
	GICH_GICH_HCR_UIE_Pos = 0x1
	// Bit mask of UIE field.
	GICH_GICH_HCR_UIE_Msk = 0x2
	// Bit UIE.
	GICH_GICH_HCR_UIE = 0x2
	// Position of LRENPIE field.
	GICH_GICH_HCR_LRENPIE_Pos = 0x2
	// Bit mask of LRENPIE field.
	GICH_GICH_HCR_LRENPIE_Msk = 0x4
	// Bit LRENPIE.
	GICH_GICH_HCR_LRENPIE = 0x4
	// Position of NPIE field.
	GICH_GICH_HCR_NPIE_Pos = 0x3
	// Bit mask of NPIE field.
	GICH_GICH_HCR_NPIE_Msk = 0x8
	// Bit NPIE.
	GICH_GICH_HCR_NPIE = 0x8
	// Position of VGRP0EIE field.
	GICH_GICH_HCR_VGRP0EIE_Pos = 0x4
	// Bit mask of VGRP0EIE field.
	GICH_GICH_HCR_VGRP0EIE_Msk = 0x10
	// Bit VGRP0EIE.
	GICH_GICH_HCR_VGRP0EIE = 0x10
	// Position of VGRP0DIE field.
	GICH_GICH_HCR_VGRP0DIE_Pos = 0x5
	// Bit mask of VGRP0DIE field.
	GICH_GICH_HCR_VGRP0DIE_Msk = 0x20
	// Bit VGRP0DIE.
	GICH_GICH_HCR_VGRP0DIE = 0x20
	// Position of VGRP1EIE field.
	GICH_GICH_HCR_VGRP1EIE_Pos = 0x6
	// Bit mask of VGRP1EIE field.
	GICH_GICH_HCR_VGRP1EIE_Msk = 0x40
	// Bit VGRP1EIE.
	GICH_GICH_HCR_VGRP1EIE = 0x40
	// Position of VGRP1DIE field.
	GICH_GICH_HCR_VGRP1DIE_Pos = 0x7
	// Bit mask of VGRP1DIE field.
	GICH_GICH_HCR_VGRP1DIE_Msk = 0x80
	// Bit VGRP1DIE.
	GICH_GICH_HCR_VGRP1DIE = 0x80
	// Position of EOICOUNT field.
	GICH_GICH_HCR_EOICOUNT_Pos = 0x1b
	// Bit mask of EOICOUNT field.
	GICH_GICH_HCR_EOICOUNT_Msk = 0xf8000000

	// GICH_VTR: GICH VGIC type register
	// Position of LISTREGS field.
	GICH_GICH_VTR_LISTREGS_Pos = 0x0
	// Bit mask of LISTREGS field.
	GICH_GICH_VTR_LISTREGS_Msk = 0x1f
	// Position of PREBITS field.
	GICH_GICH_VTR_PREBITS_Pos = 0x1a
	// Bit mask of PREBITS field.
	GICH_GICH_VTR_PREBITS_Msk = 0x1c000000
	// Position of PRIBITS field.
	GICH_GICH_VTR_PRIBITS_Pos = 0x1d
	// Bit mask of PRIBITS field.
	GICH_GICH_VTR_PRIBITS_Msk = 0xe0000000

	// GICH_VMCR: GICH virtual machine control register
	// Position of VMGRP0EN field.
	GICH_GICH_VMCR_VMGRP0EN_Pos = 0x0
	// Bit mask of VMGRP0EN field.
	GICH_GICH_VMCR_VMGRP0EN_Msk = 0x1
	// Bit VMGRP0EN.
	GICH_GICH_VMCR_VMGRP0EN = 0x1
	// Position of VMGRP1EN field.
	GICH_GICH_VMCR_VMGRP1EN_Pos = 0x1
	// Bit mask of VMGRP1EN field.
	GICH_GICH_VMCR_VMGRP1EN_Msk = 0x2
	// Bit VMGRP1EN.
	GICH_GICH_VMCR_VMGRP1EN = 0x2
	// Position of VMACKCTL field.
	GICH_GICH_VMCR_VMACKCTL_Pos = 0x2
	// Bit mask of VMACKCTL field.
	GICH_GICH_VMCR_VMACKCTL_Msk = 0x4
	// Bit VMACKCTL.
	GICH_GICH_VMCR_VMACKCTL = 0x4
	// Position of VMFIQEN field.
	GICH_GICH_VMCR_VMFIQEN_Pos = 0x3
	// Bit mask of VMFIQEN field.
	GICH_GICH_VMCR_VMFIQEN_Msk = 0x8
	// Bit VMFIQEN.
	GICH_GICH_VMCR_VMFIQEN = 0x8
	// Position of VMCBPR field.
	GICH_GICH_VMCR_VMCBPR_Pos = 0x4
	// Bit mask of VMCBPR field.
	GICH_GICH_VMCR_VMCBPR_Msk = 0x10
	// Bit VMCBPR.
	GICH_GICH_VMCR_VMCBPR = 0x10
	// Position of VEM field.
	GICH_GICH_VMCR_VEM_Pos = 0x9
	// Bit mask of VEM field.
	GICH_GICH_VMCR_VEM_Msk = 0x200
	// Bit VEM.
	GICH_GICH_VMCR_VEM = 0x200
	// Position of VMABP field.
	GICH_GICH_VMCR_VMABP_Pos = 0x12
	// Bit mask of VMABP field.
	GICH_GICH_VMCR_VMABP_Msk = 0x1c0000
	// Position of VMBP field.
	GICH_GICH_VMCR_VMBP_Pos = 0x15
	// Bit mask of VMBP field.
	GICH_GICH_VMCR_VMBP_Msk = 0xe00000
	// Position of VMPRIMASK field.
	GICH_GICH_VMCR_VMPRIMASK_Pos = 0x1b
	// Bit mask of VMPRIMASK field.
	GICH_GICH_VMCR_VMPRIMASK_Msk = 0xf8000000

	// GICH_MISR: GICH maintenance interrupt status register
	// Position of EOI field.
	GICH_GICH_MISR_EOI_Pos = 0x0
	// Bit mask of EOI field.
	GICH_GICH_MISR_EOI_Msk = 0x1
	// Bit EOI.
	GICH_GICH_MISR_EOI = 0x1
	// Position of U field.
	GICH_GICH_MISR_U_Pos = 0x1
	// Bit mask of U field.
	GICH_GICH_MISR_U_Msk = 0x2
	// Bit U.
	GICH_GICH_MISR_U = 0x2
	// Position of LRENP field.
	GICH_GICH_MISR_LRENP_Pos = 0x2
	// Bit mask of LRENP field.
	GICH_GICH_MISR_LRENP_Msk = 0x4
	// Bit LRENP.
	GICH_GICH_MISR_LRENP = 0x4
	// Position of NP field.
	GICH_GICH_MISR_NP_Pos = 0x3
	// Bit mask of NP field.
	GICH_GICH_MISR_NP_Msk = 0x8
	// Bit NP.
	GICH_GICH_MISR_NP = 0x8
	// Position of VGRP0E field.
	GICH_GICH_MISR_VGRP0E_Pos = 0x4
	// Bit mask of VGRP0E field.
	GICH_GICH_MISR_VGRP0E_Msk = 0x10
	// Bit VGRP0E.
	GICH_GICH_MISR_VGRP0E = 0x10
	// Position of VGRP0D field.
	GICH_GICH_MISR_VGRP0D_Pos = 0x5
	// Bit mask of VGRP0D field.
	GICH_GICH_MISR_VGRP0D_Msk = 0x20
	// Bit VGRP0D.
	GICH_GICH_MISR_VGRP0D = 0x20
	// Position of VGRP1E field.
	GICH_GICH_MISR_VGRP1E_Pos = 0x6
	// Bit mask of VGRP1E field.
	GICH_GICH_MISR_VGRP1E_Msk = 0x40
	// Bit VGRP1E.
	GICH_GICH_MISR_VGRP1E = 0x40
	// Position of VGRP1D field.
	GICH_GICH_MISR_VGRP1D_Pos = 0x7
	// Bit mask of VGRP1D field.
	GICH_GICH_MISR_VGRP1D_Msk = 0x80
	// Bit VGRP1D.
	GICH_GICH_MISR_VGRP1D = 0x80

	// GICH_EISR0: GICH end of interrupt status register
	// Position of EISR0 field.
	GICH_GICH_EISR0_EISR0_Pos = 0x0
	// Bit mask of EISR0 field.
	GICH_GICH_EISR0_EISR0_Msk = 0xffffffff

	// GICH_ELSR0: GICH empty list status register
	// Position of ELSR0 field.
	GICH_GICH_ELSR0_ELSR0_Pos = 0x0
	// Bit mask of ELSR0 field.
	GICH_GICH_ELSR0_ELSR0_Msk = 0xffffffff

	// GICH_APR0: GICH active priority register
	// Position of APR0 field.
	GICH_GICH_APR0_APR0_Pos = 0x0
	// Bit mask of APR0 field.
	GICH_GICH_APR0_APR0_Msk = 0xffffffff

	// GICH_LR0: GICH list register 0
	// Position of VIRTUALID field.
	GICH_GICH_LR0_VIRTUALID_Pos = 0x0
	// Bit mask of VIRTUALID field.
	GICH_GICH_LR0_VIRTUALID_Msk = 0x3ff
	// Position of PHYSICALID field.
	GICH_GICH_LR0_PHYSICALID_Pos = 0xa
	// Bit mask of PHYSICALID field.
	GICH_GICH_LR0_PHYSICALID_Msk = 0xffc00
	// Position of PRIORITY field.
	GICH_GICH_LR0_PRIORITY_Pos = 0x17
	// Bit mask of PRIORITY field.
	GICH_GICH_LR0_PRIORITY_Msk = 0xf800000
	// Position of STATE field.
	GICH_GICH_LR0_STATE_Pos = 0x1c
	// Bit mask of STATE field.
	GICH_GICH_LR0_STATE_Msk = 0x30000000
	// Position of GRP1 field.
	GICH_GICH_LR0_GRP1_Pos = 0x1e
	// Bit mask of GRP1 field.
	GICH_GICH_LR0_GRP1_Msk = 0x40000000
	// Bit GRP1.
	GICH_GICH_LR0_GRP1 = 0x40000000
	// Position of HW field.
	GICH_GICH_LR0_HW_Pos = 0x1f
	// Bit mask of HW field.
	GICH_GICH_LR0_HW_Msk = 0x80000000
	// Bit HW.
	GICH_GICH_LR0_HW = 0x80000000

	// GICH_LR1: GICH list register 1
	// Position of VIRTUALID field.
	GICH_GICH_LR1_VIRTUALID_Pos = 0x0
	// Bit mask of VIRTUALID field.
	GICH_GICH_LR1_VIRTUALID_Msk = 0x3ff
	// Position of PHYSICALID field.
	GICH_GICH_LR1_PHYSICALID_Pos = 0xa
	// Bit mask of PHYSICALID field.
	GICH_GICH_LR1_PHYSICALID_Msk = 0xffc00
	// Position of PRIORITY field.
	GICH_GICH_LR1_PRIORITY_Pos = 0x17
	// Bit mask of PRIORITY field.
	GICH_GICH_LR1_PRIORITY_Msk = 0xf800000
	// Position of STATE field.
	GICH_GICH_LR1_STATE_Pos = 0x1c
	// Bit mask of STATE field.
	GICH_GICH_LR1_STATE_Msk = 0x30000000
	// Position of GRP1 field.
	GICH_GICH_LR1_GRP1_Pos = 0x1e
	// Bit mask of GRP1 field.
	GICH_GICH_LR1_GRP1_Msk = 0x40000000
	// Bit GRP1.
	GICH_GICH_LR1_GRP1 = 0x40000000
	// Position of HW field.
	GICH_GICH_LR1_HW_Pos = 0x1f
	// Bit mask of HW field.
	GICH_GICH_LR1_HW_Msk = 0x80000000
	// Bit HW.
	GICH_GICH_LR1_HW = 0x80000000

	// GICH_LR2: GICH list register 2
	// Position of VIRTUALID field.
	GICH_GICH_LR2_VIRTUALID_Pos = 0x0
	// Bit mask of VIRTUALID field.
	GICH_GICH_LR2_VIRTUALID_Msk = 0x3ff
	// Position of PHYSICALID field.
	GICH_GICH_LR2_PHYSICALID_Pos = 0xa
	// Bit mask of PHYSICALID field.
	GICH_GICH_LR2_PHYSICALID_Msk = 0xffc00
	// Position of PRIORITY field.
	GICH_GICH_LR2_PRIORITY_Pos = 0x17
	// Bit mask of PRIORITY field.
	GICH_GICH_LR2_PRIORITY_Msk = 0xf800000
	// Position of STATE field.
	GICH_GICH_LR2_STATE_Pos = 0x1c
	// Bit mask of STATE field.
	GICH_GICH_LR2_STATE_Msk = 0x30000000
	// Position of GRP1 field.
	GICH_GICH_LR2_GRP1_Pos = 0x1e
	// Bit mask of GRP1 field.
	GICH_GICH_LR2_GRP1_Msk = 0x40000000
	// Bit GRP1.
	GICH_GICH_LR2_GRP1 = 0x40000000
	// Position of HW field.
	GICH_GICH_LR2_HW_Pos = 0x1f
	// Bit mask of HW field.
	GICH_GICH_LR2_HW_Msk = 0x80000000
	// Bit HW.
	GICH_GICH_LR2_HW = 0x80000000

	// GICH_LR3: GICH list register 3
	// Position of VIRTUALID field.
	GICH_GICH_LR3_VIRTUALID_Pos = 0x0
	// Bit mask of VIRTUALID field.
	GICH_GICH_LR3_VIRTUALID_Msk = 0x3ff
	// Position of PHYSICALID field.
	GICH_GICH_LR3_PHYSICALID_Pos = 0xa
	// Bit mask of PHYSICALID field.
	GICH_GICH_LR3_PHYSICALID_Msk = 0xffc00
	// Position of PRIORITY field.
	GICH_GICH_LR3_PRIORITY_Pos = 0x17
	// Bit mask of PRIORITY field.
	GICH_GICH_LR3_PRIORITY_Msk = 0xf800000
	// Position of STATE field.
	GICH_GICH_LR3_STATE_Pos = 0x1c
	// Bit mask of STATE field.
	GICH_GICH_LR3_STATE_Msk = 0x30000000
	// Position of GRP1 field.
	GICH_GICH_LR3_GRP1_Pos = 0x1e
	// Bit mask of GRP1 field.
	GICH_GICH_LR3_GRP1_Msk = 0x40000000
	// Bit GRP1.
	GICH_GICH_LR3_GRP1 = 0x40000000
	// Position of HW field.
	GICH_GICH_LR3_HW_Pos = 0x1f
	// Bit mask of HW field.
	GICH_GICH_LR3_HW_Msk = 0x80000000
	// Bit HW.
	GICH_GICH_LR3_HW = 0x80000000
)

// Bitfields for GICV: GICV
const (
	// GICV_CTLR: GICV virtual machine control register
	// Position of ENABLEGRP0 field.
	GICV_GICV_CTLR_ENABLEGRP0_Pos = 0x0
	// Bit mask of ENABLEGRP0 field.
	GICV_GICV_CTLR_ENABLEGRP0_Msk = 0x1
	// Bit ENABLEGRP0.
	GICV_GICV_CTLR_ENABLEGRP0 = 0x1
	// Position of ENABLEGRP1 field.
	GICV_GICV_CTLR_ENABLEGRP1_Pos = 0x1
	// Bit mask of ENABLEGRP1 field.
	GICV_GICV_CTLR_ENABLEGRP1_Msk = 0x2
	// Bit ENABLEGRP1.
	GICV_GICV_CTLR_ENABLEGRP1 = 0x2
	// Position of ACKCTL field.
	GICV_GICV_CTLR_ACKCTL_Pos = 0x2
	// Bit mask of ACKCTL field.
	GICV_GICV_CTLR_ACKCTL_Msk = 0x4
	// Bit ACKCTL.
	GICV_GICV_CTLR_ACKCTL = 0x4
	// Position of FIQEN field.
	GICV_GICV_CTLR_FIQEN_Pos = 0x3
	// Bit mask of FIQEN field.
	GICV_GICV_CTLR_FIQEN_Msk = 0x8
	// Bit FIQEN.
	GICV_GICV_CTLR_FIQEN = 0x8
	// Position of CBPR field.
	GICV_GICV_CTLR_CBPR_Pos = 0x4
	// Bit mask of CBPR field.
	GICV_GICV_CTLR_CBPR_Msk = 0x10
	// Bit CBPR.
	GICV_GICV_CTLR_CBPR = 0x10
	// Position of EOIMODE field.
	GICV_GICV_CTLR_EOIMODE_Pos = 0x9
	// Bit mask of EOIMODE field.
	GICV_GICV_CTLR_EOIMODE_Msk = 0x200
	// Bit EOIMODE.
	GICV_GICV_CTLR_EOIMODE = 0x200

	// GICV_PMR: GICV VM priority mask register
	// Position of PRIORITY field.
	GICV_GICV_PMR_PRIORITY_Pos = 0x3
	// Bit mask of PRIORITY field.
	GICV_GICV_PMR_PRIORITY_Msk = 0xf8

	// GICV_BPR: GICV VM binary point register
	// Position of BINARY_POINT field.
	GICV_GICV_BPR_BINARY_POINT_Pos = 0x0
	// Bit mask of BINARY_POINT field.
	GICV_GICV_BPR_BINARY_POINT_Msk = 0x7

	// GICV_IAR: GICV VM interrupt acknowledge register
	// Position of INTERRUPT_ID field.
	GICV_GICV_IAR_INTERRUPT_ID_Pos = 0x0
	// Bit mask of INTERRUPT_ID field.
	GICV_GICV_IAR_INTERRUPT_ID_Msk = 0x3ff
	// Position of CPUID field.
	GICV_GICV_IAR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICV_GICV_IAR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICV_GICV_IAR_CPUID = 0x400

	// GICV_EOIR: GICV VM end of interrupt register
	// Position of EOIINTID field.
	GICV_GICV_EOIR_EOIINTID_Pos = 0x0
	// Bit mask of EOIINTID field.
	GICV_GICV_EOIR_EOIINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICV_GICV_EOIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICV_GICV_EOIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICV_GICV_EOIR_CPUID = 0x400

	// GICV_RPR: GICV VM running priority register
	// Position of PRIORITY field.
	GICV_GICV_RPR_PRIORITY_Pos = 0x3
	// Bit mask of PRIORITY field.
	GICV_GICV_RPR_PRIORITY_Msk = 0xf8

	// GICV_HPPIR: GICV VM highest priority pending interrupt register
	// Position of PENDINTID field.
	GICV_GICV_HPPIR_PENDINTID_Pos = 0x0
	// Bit mask of PENDINTID field.
	GICV_GICV_HPPIR_PENDINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICV_GICV_HPPIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICV_GICV_HPPIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICV_GICV_HPPIR_CPUID = 0x400

	// GICV_ABPR: GICV VM aliased binary point register
	// Position of BINARY_POINT field.
	GICV_GICV_ABPR_BINARY_POINT_Pos = 0x0
	// Bit mask of BINARY_POINT field.
	GICV_GICV_ABPR_BINARY_POINT_Msk = 0x7

	// GICV_AIAR: GICV VM aliased interrupt register
	// Position of INTERRUPT_ID field.
	GICV_GICV_AIAR_INTERRUPT_ID_Pos = 0x0
	// Bit mask of INTERRUPT_ID field.
	GICV_GICV_AIAR_INTERRUPT_ID_Msk = 0x3ff
	// Position of CPUID field.
	GICV_GICV_AIAR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICV_GICV_AIAR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICV_GICV_AIAR_CPUID = 0x400

	// GICV_AEOIR: GICV VM aliased end of interrupt register
	// Position of EOIINTID field.
	GICV_GICV_AEOIR_EOIINTID_Pos = 0x0
	// Bit mask of EOIINTID field.
	GICV_GICV_AEOIR_EOIINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICV_GICV_AEOIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICV_GICV_AEOIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICV_GICV_AEOIR_CPUID = 0x400

	// GICV_AHPPIR: GICV VM aliased highest priority pending interrupt register
	// Position of PENDINTID field.
	GICV_GICV_AHPPIR_PENDINTID_Pos = 0x0
	// Bit mask of PENDINTID field.
	GICV_GICV_AHPPIR_PENDINTID_Msk = 0x3ff
	// Position of CPUID field.
	GICV_GICV_AHPPIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICV_GICV_AHPPIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICV_GICV_AHPPIR_CPUID = 0x400

	// GICV_APR0: The GICV_APR0 is an alias of GICH_APR.
	// Position of APR0 field.
	GICV_GICV_APR0_APR0_Pos = 0x0
	// Bit mask of APR0 field.
	GICV_GICV_APR0_APR0_Msk = 0xffffffff

	// GICV_IIDR: The GICV_IIDR is an alias of GICC_IIDR.
	// Position of IIDR field.
	GICV_GICV_IIDR_IIDR_Pos = 0x0
	// Bit mask of IIDR field.
	GICV_GICV_IIDR_IIDR_Msk = 0xffffffff

	// GICV_DIR: GICV VM deactivate interrupt register
	// Position of INTERRUPT_ID field.
	GICV_GICV_DIR_INTERRUPT_ID_Pos = 0x0
	// Bit mask of INTERRUPT_ID field.
	GICV_GICV_DIR_INTERRUPT_ID_Msk = 0x3ff
	// Position of CPUID field.
	GICV_GICV_DIR_CPUID_Pos = 0xa
	// Bit mask of CPUID field.
	GICV_GICV_DIR_CPUID_Msk = 0x400
	// Bit CPUID.
	GICV_GICV_DIR_CPUID = 0x400
)

// Bitfields for GPIOA: GPIOA
const (
	// GPIOA_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOA_GPIOA_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOA_GPIOA_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOA_GPIOA_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOA_GPIOA_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOA_GPIOA_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOA_GPIOA_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOA_GPIOA_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOA_GPIOA_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOA_GPIOA_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOA_GPIOA_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOA_GPIOA_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOA_GPIOA_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOA_GPIOA_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOA_GPIOA_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOA_GPIOA_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOA_GPIOA_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOA_GPIOA_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOA_GPIOA_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOA_GPIOA_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOA_GPIOA_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOA_GPIOA_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOA_GPIOA_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOA_GPIOA_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOA_GPIOA_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOA_GPIOA_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOA_GPIOA_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOA_GPIOA_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOA_GPIOA_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOA_GPIOA_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOA_GPIOA_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOA_GPIOA_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOA_GPIOA_MODER_MODER15_Msk = 0xc0000000

	// GPIOA_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOA_GPIOA_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOA_GPIOA_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOA_GPIOA_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOA_GPIOA_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOA_GPIOA_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOA_GPIOA_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOA_GPIOA_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOA_GPIOA_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOA_GPIOA_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOA_GPIOA_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOA_GPIOA_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOA_GPIOA_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOA_GPIOA_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOA_GPIOA_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOA_GPIOA_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOA_GPIOA_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOA_GPIOA_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOA_GPIOA_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOA_GPIOA_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOA_GPIOA_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOA_GPIOA_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOA_GPIOA_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOA_GPIOA_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOA_GPIOA_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOA_GPIOA_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOA_GPIOA_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOA_GPIOA_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOA_GPIOA_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOA_GPIOA_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOA_GPIOA_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOA_GPIOA_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOA_GPIOA_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOA_GPIOA_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOA_GPIOA_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOA_GPIOA_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOA_GPIOA_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOA_GPIOA_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOA_GPIOA_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOA_GPIOA_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOA_GPIOA_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOA_GPIOA_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOA_GPIOA_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOA_GPIOA_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOA_GPIOA_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOA_GPIOA_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOA_GPIOA_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOA_GPIOA_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOA_GPIOA_OTYPER_OT15 = 0x8000

	// GPIOA_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOA_GPIOA_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOA_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOA_GPIOA_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOA_GPIOA_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOA_GPIOA_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOA_GPIOA_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOA_GPIOA_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOA_GPIOA_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOA_GPIOA_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOA_GPIOA_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOA_GPIOA_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOA_GPIOA_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOA_GPIOA_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOA_GPIOA_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOA_GPIOA_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOA_GPIOA_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOA_GPIOA_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOA_GPIOA_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOA_GPIOA_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOA_GPIOA_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOA_GPIOA_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOA_GPIOA_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOA_GPIOA_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOA_GPIOA_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOA_GPIOA_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOA_GPIOA_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOA_GPIOA_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOA_GPIOA_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOA_GPIOA_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOA_GPIOA_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOA_GPIOA_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOA_GPIOA_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOA_GPIOA_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOA_GPIOA_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOA_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOA_GPIOA_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOA_GPIOA_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOA_GPIOA_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOA_GPIOA_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOA_GPIOA_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOA_GPIOA_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOA_GPIOA_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOA_GPIOA_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOA_GPIOA_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOA_GPIOA_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOA_GPIOA_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOA_GPIOA_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOA_GPIOA_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOA_GPIOA_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOA_GPIOA_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOA_GPIOA_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOA_GPIOA_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOA_GPIOA_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOA_GPIOA_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOA_GPIOA_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOA_GPIOA_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOA_GPIOA_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOA_GPIOA_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOA_GPIOA_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOA_GPIOA_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOA_GPIOA_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOA_GPIOA_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOA_GPIOA_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOA_GPIOA_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOA_GPIOA_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOA_GPIOA_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOA_GPIOA_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOA_GPIOA_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOA_GPIOA_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOA_GPIOA_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOA_GPIOA_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOA_GPIOA_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOA_GPIOA_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOA_GPIOA_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOA_GPIOA_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOA_GPIOA_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOA_GPIOA_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOA_GPIOA_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOA_GPIOA_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOA_GPIOA_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOA_GPIOA_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOA_GPIOA_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOA_GPIOA_IDR_IDR15 = 0x8000

	// GPIOA_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOA_GPIOA_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOA_GPIOA_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOA_GPIOA_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOA_GPIOA_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOA_GPIOA_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOA_GPIOA_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOA_GPIOA_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOA_GPIOA_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOA_GPIOA_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOA_GPIOA_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOA_GPIOA_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOA_GPIOA_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOA_GPIOA_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOA_GPIOA_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOA_GPIOA_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOA_GPIOA_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOA_GPIOA_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOA_GPIOA_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOA_GPIOA_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOA_GPIOA_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOA_GPIOA_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOA_GPIOA_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOA_GPIOA_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOA_GPIOA_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOA_GPIOA_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOA_GPIOA_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOA_GPIOA_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOA_GPIOA_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOA_GPIOA_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOA_GPIOA_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOA_GPIOA_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOA_GPIOA_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOA_GPIOA_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOA_GPIOA_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOA_GPIOA_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOA_GPIOA_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOA_GPIOA_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOA_GPIOA_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOA_GPIOA_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOA_GPIOA_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOA_GPIOA_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOA_GPIOA_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOA_GPIOA_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOA_GPIOA_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOA_GPIOA_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOA_GPIOA_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOA_GPIOA_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOA_GPIOA_ODR_ODR15 = 0x8000

	// GPIOA_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOA_GPIOA_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOA_GPIOA_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOA_GPIOA_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOA_GPIOA_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOA_GPIOA_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOA_GPIOA_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOA_GPIOA_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOA_GPIOA_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOA_GPIOA_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOA_GPIOA_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOA_GPIOA_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOA_GPIOA_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOA_GPIOA_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOA_GPIOA_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOA_GPIOA_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOA_GPIOA_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOA_GPIOA_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOA_GPIOA_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOA_GPIOA_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOA_GPIOA_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOA_GPIOA_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOA_GPIOA_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOA_GPIOA_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOA_GPIOA_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOA_GPIOA_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOA_GPIOA_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOA_GPIOA_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOA_GPIOA_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOA_GPIOA_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOA_GPIOA_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOA_GPIOA_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOA_GPIOA_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOA_GPIOA_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOA_GPIOA_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOA_GPIOA_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOA_GPIOA_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOA_GPIOA_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOA_GPIOA_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOA_GPIOA_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOA_GPIOA_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOA_GPIOA_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOA_GPIOA_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOA_GPIOA_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOA_GPIOA_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOA_GPIOA_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOA_GPIOA_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOA_GPIOA_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOA_GPIOA_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOA_GPIOA_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOA_GPIOA_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOA_GPIOA_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOA_GPIOA_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOA_GPIOA_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOA_GPIOA_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOA_GPIOA_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOA_GPIOA_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOA_GPIOA_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOA_GPIOA_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOA_GPIOA_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOA_GPIOA_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOA_GPIOA_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOA_GPIOA_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOA_GPIOA_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOA_GPIOA_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOA_GPIOA_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOA_GPIOA_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOA_GPIOA_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOA_GPIOA_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOA_GPIOA_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOA_GPIOA_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOA_GPIOA_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOA_GPIOA_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOA_GPIOA_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOA_GPIOA_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOA_GPIOA_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOA_GPIOA_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOA_GPIOA_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOA_GPIOA_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOA_GPIOA_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOA_GPIOA_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOA_GPIOA_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOA_GPIOA_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOA_GPIOA_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOA_GPIOA_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOA_GPIOA_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOA_GPIOA_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOA_GPIOA_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOA_GPIOA_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOA_GPIOA_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOA_GPIOA_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOA_GPIOA_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOA_GPIOA_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOA_GPIOA_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOA_GPIOA_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOA_GPIOA_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOA_GPIOA_BSRR_BR15 = 0x80000000

	// GPIOA_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOA_GPIOA_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOA_GPIOA_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOA_GPIOA_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOA_GPIOA_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOA_GPIOA_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOA_GPIOA_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOA_GPIOA_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOA_GPIOA_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOA_GPIOA_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOA_GPIOA_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOA_GPIOA_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOA_GPIOA_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOA_GPIOA_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOA_GPIOA_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOA_GPIOA_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOA_GPIOA_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOA_GPIOA_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOA_GPIOA_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOA_GPIOA_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOA_GPIOA_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOA_GPIOA_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOA_GPIOA_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOA_GPIOA_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOA_GPIOA_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOA_GPIOA_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOA_GPIOA_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOA_GPIOA_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOA_GPIOA_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOA_GPIOA_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOA_GPIOA_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOA_GPIOA_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOA_GPIOA_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOA_GPIOA_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOA_GPIOA_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOA_GPIOA_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOA_GPIOA_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOA_GPIOA_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOA_GPIOA_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOA_GPIOA_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOA_GPIOA_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOA_GPIOA_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOA_GPIOA_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOA_GPIOA_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOA_GPIOA_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOA_GPIOA_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOA_GPIOA_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOA_GPIOA_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOA_GPIOA_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOA_GPIOA_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOA_GPIOA_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOA_GPIOA_LCKR_LCKK = 0x10000

	// GPIOA_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOA_GPIOA_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOA_GPIOA_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOA_GPIOA_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOA_GPIOA_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOA_GPIOA_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOA_GPIOA_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOA_GPIOA_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOA_GPIOA_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOA_GPIOA_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOA_GPIOA_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOA_GPIOA_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOA_GPIOA_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOA_GPIOA_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOA_GPIOA_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOA_GPIOA_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOA_GPIOA_AFRL_AFR7_Msk = 0xf0000000

	// GPIOA_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOA_GPIOA_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOA_GPIOA_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOA_GPIOA_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOA_GPIOA_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOA_GPIOA_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOA_GPIOA_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOA_GPIOA_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOA_GPIOA_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOA_GPIOA_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOA_GPIOA_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOA_GPIOA_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOA_GPIOA_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOA_GPIOA_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOA_GPIOA_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOA_GPIOA_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOA_GPIOA_AFRH_AFR15_Msk = 0xf0000000

	// GPIOA_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOA_GPIOA_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOA_GPIOA_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOA_GPIOA_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOA_GPIOA_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOA_GPIOA_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOA_GPIOA_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOA_GPIOA_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOA_GPIOA_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOA_GPIOA_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOA_GPIOA_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOA_GPIOA_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOA_GPIOA_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOA_GPIOA_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOA_GPIOA_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOA_GPIOA_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOA_GPIOA_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOA_GPIOA_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOA_GPIOA_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOA_GPIOA_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOA_GPIOA_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOA_GPIOA_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOA_GPIOA_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOA_GPIOA_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOA_GPIOA_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOA_GPIOA_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOA_GPIOA_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOA_GPIOA_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOA_GPIOA_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOA_GPIOA_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOA_GPIOA_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOA_GPIOA_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOA_GPIOA_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOA_GPIOA_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOA_GPIOA_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOA_GPIOA_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOA_GPIOA_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOA_GPIOA_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOA_GPIOA_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOA_GPIOA_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOA_GPIOA_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOA_GPIOA_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOA_GPIOA_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOA_GPIOA_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOA_GPIOA_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOA_GPIOA_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOA_GPIOA_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOA_GPIOA_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOA_GPIOA_BRR_BR15 = 0x8000

	// GPIOA_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOA_GPIOA_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOA_GPIOA_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOA_GPIOA_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOA_GPIOA_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOA_GPIOA_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOA_GPIOA_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOA_GPIOA_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOA_GPIOA_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOA_GPIOA_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOA_GPIOA_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOA_GPIOA_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOA_GPIOA_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOA_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOA_GPIOA_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOA_GPIOA_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOA_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOA_GPIOA_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOA_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOA_GPIOA_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOA_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOA_GPIOA_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOA_GPIOA_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOA_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOA_GPIOA_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOA_GPIOA_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOA_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOA_GPIOA_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOA_GPIOA_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOA_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOA_GPIOA_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOA_GPIOA_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOA_GPIOA_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOA_GPIOA_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOA_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOA_GPIOA_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOA_GPIOA_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOA_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOA_GPIOA_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOA_GPIOA_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOA_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOA_GPIOA_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOA_GPIOA_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOA_VERR: GPIO version register
	// Position of MINREV field.
	GPIOA_GPIOA_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOA_GPIOA_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOA_GPIOA_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOA_GPIOA_VERR_MAJREV_Msk = 0xf0

	// GPIOA_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOA_GPIOA_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOA_GPIOA_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOA_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOA_GPIOA_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOA_GPIOA_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOB: GPIOB
const (
	// GPIOB_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOB_GPIOB_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOB_GPIOB_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOB_GPIOB_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOB_GPIOB_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOB_GPIOB_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOB_GPIOB_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOB_GPIOB_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOB_GPIOB_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOB_GPIOB_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOB_GPIOB_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOB_GPIOB_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOB_GPIOB_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOB_GPIOB_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOB_GPIOB_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOB_GPIOB_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOB_GPIOB_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOB_GPIOB_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOB_GPIOB_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOB_GPIOB_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOB_GPIOB_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOB_GPIOB_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOB_GPIOB_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOB_GPIOB_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOB_GPIOB_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOB_GPIOB_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOB_GPIOB_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOB_GPIOB_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOB_GPIOB_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOB_GPIOB_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOB_GPIOB_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOB_GPIOB_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOB_GPIOB_MODER_MODER15_Msk = 0xc0000000

	// GPIOB_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOB_GPIOB_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOB_GPIOB_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOB_GPIOB_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOB_GPIOB_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOB_GPIOB_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOB_GPIOB_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOB_GPIOB_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOB_GPIOB_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOB_GPIOB_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOB_GPIOB_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOB_GPIOB_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOB_GPIOB_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOB_GPIOB_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOB_GPIOB_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOB_GPIOB_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOB_GPIOB_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOB_GPIOB_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOB_GPIOB_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOB_GPIOB_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOB_GPIOB_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOB_GPIOB_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOB_GPIOB_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOB_GPIOB_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOB_GPIOB_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOB_GPIOB_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOB_GPIOB_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOB_GPIOB_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOB_GPIOB_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOB_GPIOB_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOB_GPIOB_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOB_GPIOB_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOB_GPIOB_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOB_GPIOB_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOB_GPIOB_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOB_GPIOB_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOB_GPIOB_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOB_GPIOB_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOB_GPIOB_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOB_GPIOB_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOB_GPIOB_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOB_GPIOB_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOB_GPIOB_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOB_GPIOB_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOB_GPIOB_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOB_GPIOB_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOB_GPIOB_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOB_GPIOB_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOB_GPIOB_OTYPER_OT15 = 0x8000

	// GPIOB_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOB_GPIOB_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOB_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOB_GPIOB_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOB_GPIOB_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOB_GPIOB_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOB_GPIOB_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOB_GPIOB_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOB_GPIOB_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOB_GPIOB_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOB_GPIOB_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOB_GPIOB_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOB_GPIOB_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOB_GPIOB_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOB_GPIOB_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOB_GPIOB_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOB_GPIOB_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOB_GPIOB_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOB_GPIOB_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOB_GPIOB_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOB_GPIOB_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOB_GPIOB_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOB_GPIOB_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOB_GPIOB_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOB_GPIOB_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOB_GPIOB_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOB_GPIOB_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOB_GPIOB_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOB_GPIOB_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOB_GPIOB_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOB_GPIOB_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOB_GPIOB_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOB_GPIOB_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOB_GPIOB_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOB_GPIOB_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOB_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOB_GPIOB_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOB_GPIOB_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOB_GPIOB_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOB_GPIOB_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOB_GPIOB_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOB_GPIOB_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOB_GPIOB_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOB_GPIOB_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOB_GPIOB_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOB_GPIOB_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOB_GPIOB_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOB_GPIOB_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOB_GPIOB_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOB_GPIOB_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOB_GPIOB_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOB_GPIOB_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOB_GPIOB_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOB_GPIOB_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOB_GPIOB_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOB_GPIOB_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOB_GPIOB_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOB_GPIOB_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOB_GPIOB_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOB_GPIOB_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOB_GPIOB_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOB_GPIOB_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOB_GPIOB_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOB_GPIOB_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOB_GPIOB_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOB_GPIOB_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOB_GPIOB_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOB_GPIOB_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOB_GPIOB_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOB_GPIOB_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOB_GPIOB_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOB_GPIOB_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOB_GPIOB_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOB_GPIOB_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOB_GPIOB_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOB_GPIOB_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOB_GPIOB_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOB_GPIOB_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOB_GPIOB_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOB_GPIOB_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOB_GPIOB_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOB_GPIOB_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOB_GPIOB_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOB_GPIOB_IDR_IDR15 = 0x8000

	// GPIOB_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOB_GPIOB_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOB_GPIOB_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOB_GPIOB_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOB_GPIOB_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOB_GPIOB_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOB_GPIOB_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOB_GPIOB_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOB_GPIOB_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOB_GPIOB_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOB_GPIOB_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOB_GPIOB_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOB_GPIOB_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOB_GPIOB_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOB_GPIOB_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOB_GPIOB_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOB_GPIOB_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOB_GPIOB_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOB_GPIOB_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOB_GPIOB_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOB_GPIOB_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOB_GPIOB_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOB_GPIOB_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOB_GPIOB_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOB_GPIOB_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOB_GPIOB_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOB_GPIOB_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOB_GPIOB_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOB_GPIOB_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOB_GPIOB_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOB_GPIOB_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOB_GPIOB_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOB_GPIOB_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOB_GPIOB_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOB_GPIOB_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOB_GPIOB_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOB_GPIOB_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOB_GPIOB_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOB_GPIOB_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOB_GPIOB_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOB_GPIOB_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOB_GPIOB_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOB_GPIOB_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOB_GPIOB_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOB_GPIOB_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOB_GPIOB_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOB_GPIOB_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOB_GPIOB_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOB_GPIOB_ODR_ODR15 = 0x8000

	// GPIOB_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOB_GPIOB_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOB_GPIOB_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOB_GPIOB_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOB_GPIOB_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOB_GPIOB_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOB_GPIOB_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOB_GPIOB_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOB_GPIOB_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOB_GPIOB_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOB_GPIOB_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOB_GPIOB_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOB_GPIOB_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOB_GPIOB_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOB_GPIOB_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOB_GPIOB_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOB_GPIOB_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOB_GPIOB_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOB_GPIOB_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOB_GPIOB_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOB_GPIOB_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOB_GPIOB_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOB_GPIOB_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOB_GPIOB_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOB_GPIOB_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOB_GPIOB_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOB_GPIOB_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOB_GPIOB_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOB_GPIOB_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOB_GPIOB_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOB_GPIOB_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOB_GPIOB_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOB_GPIOB_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOB_GPIOB_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOB_GPIOB_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOB_GPIOB_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOB_GPIOB_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOB_GPIOB_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOB_GPIOB_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOB_GPIOB_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOB_GPIOB_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOB_GPIOB_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOB_GPIOB_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOB_GPIOB_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOB_GPIOB_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOB_GPIOB_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOB_GPIOB_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOB_GPIOB_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOB_GPIOB_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOB_GPIOB_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOB_GPIOB_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOB_GPIOB_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOB_GPIOB_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOB_GPIOB_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOB_GPIOB_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOB_GPIOB_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOB_GPIOB_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOB_GPIOB_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOB_GPIOB_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOB_GPIOB_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOB_GPIOB_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOB_GPIOB_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOB_GPIOB_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOB_GPIOB_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOB_GPIOB_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOB_GPIOB_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOB_GPIOB_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOB_GPIOB_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOB_GPIOB_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOB_GPIOB_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOB_GPIOB_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOB_GPIOB_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOB_GPIOB_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOB_GPIOB_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOB_GPIOB_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOB_GPIOB_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOB_GPIOB_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOB_GPIOB_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOB_GPIOB_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOB_GPIOB_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOB_GPIOB_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOB_GPIOB_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOB_GPIOB_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOB_GPIOB_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOB_GPIOB_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOB_GPIOB_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOB_GPIOB_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOB_GPIOB_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOB_GPIOB_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOB_GPIOB_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOB_GPIOB_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOB_GPIOB_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOB_GPIOB_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOB_GPIOB_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOB_GPIOB_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOB_GPIOB_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOB_GPIOB_BSRR_BR15 = 0x80000000

	// GPIOB_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOB_GPIOB_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOB_GPIOB_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOB_GPIOB_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOB_GPIOB_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOB_GPIOB_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOB_GPIOB_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOB_GPIOB_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOB_GPIOB_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOB_GPIOB_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOB_GPIOB_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOB_GPIOB_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOB_GPIOB_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOB_GPIOB_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOB_GPIOB_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOB_GPIOB_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOB_GPIOB_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOB_GPIOB_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOB_GPIOB_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOB_GPIOB_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOB_GPIOB_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOB_GPIOB_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOB_GPIOB_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOB_GPIOB_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOB_GPIOB_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOB_GPIOB_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOB_GPIOB_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOB_GPIOB_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOB_GPIOB_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOB_GPIOB_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOB_GPIOB_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOB_GPIOB_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOB_GPIOB_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOB_GPIOB_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOB_GPIOB_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOB_GPIOB_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOB_GPIOB_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOB_GPIOB_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOB_GPIOB_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOB_GPIOB_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOB_GPIOB_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOB_GPIOB_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOB_GPIOB_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOB_GPIOB_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOB_GPIOB_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOB_GPIOB_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOB_GPIOB_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOB_GPIOB_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOB_GPIOB_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOB_GPIOB_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOB_GPIOB_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOB_GPIOB_LCKR_LCKK = 0x10000

	// GPIOB_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOB_GPIOB_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOB_GPIOB_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOB_GPIOB_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOB_GPIOB_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOB_GPIOB_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOB_GPIOB_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOB_GPIOB_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOB_GPIOB_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOB_GPIOB_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOB_GPIOB_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOB_GPIOB_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOB_GPIOB_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOB_GPIOB_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOB_GPIOB_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOB_GPIOB_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOB_GPIOB_AFRL_AFR7_Msk = 0xf0000000

	// GPIOB_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOB_GPIOB_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOB_GPIOB_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOB_GPIOB_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOB_GPIOB_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOB_GPIOB_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOB_GPIOB_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOB_GPIOB_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOB_GPIOB_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOB_GPIOB_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOB_GPIOB_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOB_GPIOB_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOB_GPIOB_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOB_GPIOB_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOB_GPIOB_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOB_GPIOB_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOB_GPIOB_AFRH_AFR15_Msk = 0xf0000000

	// GPIOB_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOB_GPIOB_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOB_GPIOB_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOB_GPIOB_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOB_GPIOB_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOB_GPIOB_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOB_GPIOB_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOB_GPIOB_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOB_GPIOB_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOB_GPIOB_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOB_GPIOB_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOB_GPIOB_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOB_GPIOB_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOB_GPIOB_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOB_GPIOB_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOB_GPIOB_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOB_GPIOB_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOB_GPIOB_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOB_GPIOB_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOB_GPIOB_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOB_GPIOB_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOB_GPIOB_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOB_GPIOB_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOB_GPIOB_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOB_GPIOB_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOB_GPIOB_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOB_GPIOB_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOB_GPIOB_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOB_GPIOB_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOB_GPIOB_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOB_GPIOB_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOB_GPIOB_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOB_GPIOB_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOB_GPIOB_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOB_GPIOB_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOB_GPIOB_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOB_GPIOB_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOB_GPIOB_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOB_GPIOB_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOB_GPIOB_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOB_GPIOB_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOB_GPIOB_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOB_GPIOB_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOB_GPIOB_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOB_GPIOB_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOB_GPIOB_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOB_GPIOB_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOB_GPIOB_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOB_GPIOB_BRR_BR15 = 0x8000

	// GPIOB_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOB_GPIOB_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOB_GPIOB_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOB_GPIOB_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOB_GPIOB_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOB_GPIOB_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOB_GPIOB_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOB_GPIOB_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOB_GPIOB_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOB_GPIOB_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOB_GPIOB_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOB_GPIOB_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOB_GPIOB_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOB_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOB_GPIOB_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOB_GPIOB_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOB_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOB_GPIOB_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOB_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOB_GPIOB_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOB_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOB_GPIOB_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOB_GPIOB_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOB_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOB_GPIOB_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOB_GPIOB_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOB_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOB_GPIOB_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOB_GPIOB_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOB_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOB_GPIOB_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOB_GPIOB_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOB_GPIOB_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOB_GPIOB_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOB_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOB_GPIOB_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOB_GPIOB_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOB_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOB_GPIOB_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOB_GPIOB_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOB_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOB_GPIOB_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOB_GPIOB_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOB_VERR: GPIO version register
	// Position of MINREV field.
	GPIOB_GPIOB_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOB_GPIOB_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOB_GPIOB_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOB_GPIOB_VERR_MAJREV_Msk = 0xf0

	// GPIOB_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOB_GPIOB_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOB_GPIOB_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOB_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOB_GPIOB_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOB_GPIOB_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOC: GPIOC
const (
	// GPIOC_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOC_GPIOC_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOC_GPIOC_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOC_GPIOC_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOC_GPIOC_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOC_GPIOC_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOC_GPIOC_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOC_GPIOC_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOC_GPIOC_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOC_GPIOC_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOC_GPIOC_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOC_GPIOC_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOC_GPIOC_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOC_GPIOC_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOC_GPIOC_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOC_GPIOC_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOC_GPIOC_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOC_GPIOC_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOC_GPIOC_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOC_GPIOC_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOC_GPIOC_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOC_GPIOC_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOC_GPIOC_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOC_GPIOC_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOC_GPIOC_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOC_GPIOC_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOC_GPIOC_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOC_GPIOC_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOC_GPIOC_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOC_GPIOC_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOC_GPIOC_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOC_GPIOC_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOC_GPIOC_MODER_MODER15_Msk = 0xc0000000

	// GPIOC_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOC_GPIOC_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOC_GPIOC_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOC_GPIOC_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOC_GPIOC_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOC_GPIOC_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOC_GPIOC_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOC_GPIOC_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOC_GPIOC_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOC_GPIOC_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOC_GPIOC_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOC_GPIOC_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOC_GPIOC_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOC_GPIOC_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOC_GPIOC_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOC_GPIOC_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOC_GPIOC_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOC_GPIOC_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOC_GPIOC_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOC_GPIOC_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOC_GPIOC_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOC_GPIOC_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOC_GPIOC_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOC_GPIOC_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOC_GPIOC_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOC_GPIOC_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOC_GPIOC_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOC_GPIOC_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOC_GPIOC_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOC_GPIOC_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOC_GPIOC_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOC_GPIOC_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOC_GPIOC_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOC_GPIOC_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOC_GPIOC_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOC_GPIOC_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOC_GPIOC_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOC_GPIOC_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOC_GPIOC_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOC_GPIOC_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOC_GPIOC_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOC_GPIOC_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOC_GPIOC_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOC_GPIOC_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOC_GPIOC_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOC_GPIOC_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOC_GPIOC_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOC_GPIOC_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOC_GPIOC_OTYPER_OT15 = 0x8000

	// GPIOC_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOC_GPIOC_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOC_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOC_GPIOC_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOC_GPIOC_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOC_GPIOC_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOC_GPIOC_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOC_GPIOC_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOC_GPIOC_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOC_GPIOC_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOC_GPIOC_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOC_GPIOC_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOC_GPIOC_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOC_GPIOC_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOC_GPIOC_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOC_GPIOC_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOC_GPIOC_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOC_GPIOC_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOC_GPIOC_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOC_GPIOC_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOC_GPIOC_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOC_GPIOC_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOC_GPIOC_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOC_GPIOC_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOC_GPIOC_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOC_GPIOC_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOC_GPIOC_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOC_GPIOC_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOC_GPIOC_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOC_GPIOC_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOC_GPIOC_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOC_GPIOC_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOC_GPIOC_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOC_GPIOC_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOC_GPIOC_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOC_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOC_GPIOC_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOC_GPIOC_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOC_GPIOC_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOC_GPIOC_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOC_GPIOC_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOC_GPIOC_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOC_GPIOC_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOC_GPIOC_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOC_GPIOC_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOC_GPIOC_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOC_GPIOC_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOC_GPIOC_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOC_GPIOC_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOC_GPIOC_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOC_GPIOC_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOC_GPIOC_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOC_GPIOC_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOC_GPIOC_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOC_GPIOC_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOC_GPIOC_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOC_GPIOC_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOC_GPIOC_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOC_GPIOC_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOC_GPIOC_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOC_GPIOC_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOC_GPIOC_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOC_GPIOC_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOC_GPIOC_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOC_GPIOC_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOC_GPIOC_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOC_GPIOC_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOC_GPIOC_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOC_GPIOC_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOC_GPIOC_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOC_GPIOC_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOC_GPIOC_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOC_GPIOC_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOC_GPIOC_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOC_GPIOC_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOC_GPIOC_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOC_GPIOC_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOC_GPIOC_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOC_GPIOC_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOC_GPIOC_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOC_GPIOC_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOC_GPIOC_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOC_GPIOC_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOC_GPIOC_IDR_IDR15 = 0x8000

	// GPIOC_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOC_GPIOC_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOC_GPIOC_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOC_GPIOC_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOC_GPIOC_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOC_GPIOC_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOC_GPIOC_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOC_GPIOC_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOC_GPIOC_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOC_GPIOC_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOC_GPIOC_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOC_GPIOC_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOC_GPIOC_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOC_GPIOC_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOC_GPIOC_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOC_GPIOC_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOC_GPIOC_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOC_GPIOC_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOC_GPIOC_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOC_GPIOC_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOC_GPIOC_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOC_GPIOC_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOC_GPIOC_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOC_GPIOC_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOC_GPIOC_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOC_GPIOC_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOC_GPIOC_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOC_GPIOC_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOC_GPIOC_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOC_GPIOC_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOC_GPIOC_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOC_GPIOC_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOC_GPIOC_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOC_GPIOC_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOC_GPIOC_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOC_GPIOC_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOC_GPIOC_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOC_GPIOC_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOC_GPIOC_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOC_GPIOC_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOC_GPIOC_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOC_GPIOC_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOC_GPIOC_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOC_GPIOC_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOC_GPIOC_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOC_GPIOC_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOC_GPIOC_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOC_GPIOC_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOC_GPIOC_ODR_ODR15 = 0x8000

	// GPIOC_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOC_GPIOC_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOC_GPIOC_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOC_GPIOC_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOC_GPIOC_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOC_GPIOC_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOC_GPIOC_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOC_GPIOC_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOC_GPIOC_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOC_GPIOC_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOC_GPIOC_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOC_GPIOC_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOC_GPIOC_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOC_GPIOC_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOC_GPIOC_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOC_GPIOC_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOC_GPIOC_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOC_GPIOC_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOC_GPIOC_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOC_GPIOC_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOC_GPIOC_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOC_GPIOC_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOC_GPIOC_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOC_GPIOC_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOC_GPIOC_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOC_GPIOC_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOC_GPIOC_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOC_GPIOC_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOC_GPIOC_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOC_GPIOC_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOC_GPIOC_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOC_GPIOC_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOC_GPIOC_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOC_GPIOC_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOC_GPIOC_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOC_GPIOC_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOC_GPIOC_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOC_GPIOC_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOC_GPIOC_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOC_GPIOC_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOC_GPIOC_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOC_GPIOC_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOC_GPIOC_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOC_GPIOC_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOC_GPIOC_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOC_GPIOC_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOC_GPIOC_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOC_GPIOC_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOC_GPIOC_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOC_GPIOC_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOC_GPIOC_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOC_GPIOC_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOC_GPIOC_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOC_GPIOC_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOC_GPIOC_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOC_GPIOC_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOC_GPIOC_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOC_GPIOC_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOC_GPIOC_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOC_GPIOC_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOC_GPIOC_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOC_GPIOC_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOC_GPIOC_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOC_GPIOC_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOC_GPIOC_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOC_GPIOC_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOC_GPIOC_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOC_GPIOC_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOC_GPIOC_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOC_GPIOC_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOC_GPIOC_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOC_GPIOC_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOC_GPIOC_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOC_GPIOC_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOC_GPIOC_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOC_GPIOC_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOC_GPIOC_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOC_GPIOC_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOC_GPIOC_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOC_GPIOC_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOC_GPIOC_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOC_GPIOC_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOC_GPIOC_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOC_GPIOC_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOC_GPIOC_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOC_GPIOC_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOC_GPIOC_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOC_GPIOC_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOC_GPIOC_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOC_GPIOC_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOC_GPIOC_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOC_GPIOC_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOC_GPIOC_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOC_GPIOC_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOC_GPIOC_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOC_GPIOC_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOC_GPIOC_BSRR_BR15 = 0x80000000

	// GPIOC_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOC_GPIOC_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOC_GPIOC_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOC_GPIOC_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOC_GPIOC_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOC_GPIOC_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOC_GPIOC_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOC_GPIOC_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOC_GPIOC_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOC_GPIOC_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOC_GPIOC_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOC_GPIOC_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOC_GPIOC_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOC_GPIOC_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOC_GPIOC_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOC_GPIOC_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOC_GPIOC_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOC_GPIOC_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOC_GPIOC_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOC_GPIOC_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOC_GPIOC_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOC_GPIOC_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOC_GPIOC_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOC_GPIOC_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOC_GPIOC_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOC_GPIOC_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOC_GPIOC_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOC_GPIOC_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOC_GPIOC_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOC_GPIOC_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOC_GPIOC_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOC_GPIOC_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOC_GPIOC_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOC_GPIOC_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOC_GPIOC_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOC_GPIOC_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOC_GPIOC_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOC_GPIOC_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOC_GPIOC_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOC_GPIOC_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOC_GPIOC_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOC_GPIOC_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOC_GPIOC_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOC_GPIOC_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOC_GPIOC_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOC_GPIOC_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOC_GPIOC_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOC_GPIOC_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOC_GPIOC_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOC_GPIOC_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOC_GPIOC_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOC_GPIOC_LCKR_LCKK = 0x10000

	// GPIOC_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOC_GPIOC_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOC_GPIOC_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOC_GPIOC_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOC_GPIOC_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOC_GPIOC_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOC_GPIOC_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOC_GPIOC_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOC_GPIOC_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOC_GPIOC_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOC_GPIOC_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOC_GPIOC_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOC_GPIOC_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOC_GPIOC_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOC_GPIOC_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOC_GPIOC_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOC_GPIOC_AFRL_AFR7_Msk = 0xf0000000

	// GPIOC_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOC_GPIOC_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOC_GPIOC_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOC_GPIOC_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOC_GPIOC_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOC_GPIOC_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOC_GPIOC_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOC_GPIOC_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOC_GPIOC_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOC_GPIOC_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOC_GPIOC_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOC_GPIOC_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOC_GPIOC_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOC_GPIOC_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOC_GPIOC_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOC_GPIOC_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOC_GPIOC_AFRH_AFR15_Msk = 0xf0000000

	// GPIOC_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOC_GPIOC_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOC_GPIOC_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOC_GPIOC_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOC_GPIOC_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOC_GPIOC_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOC_GPIOC_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOC_GPIOC_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOC_GPIOC_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOC_GPIOC_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOC_GPIOC_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOC_GPIOC_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOC_GPIOC_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOC_GPIOC_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOC_GPIOC_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOC_GPIOC_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOC_GPIOC_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOC_GPIOC_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOC_GPIOC_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOC_GPIOC_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOC_GPIOC_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOC_GPIOC_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOC_GPIOC_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOC_GPIOC_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOC_GPIOC_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOC_GPIOC_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOC_GPIOC_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOC_GPIOC_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOC_GPIOC_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOC_GPIOC_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOC_GPIOC_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOC_GPIOC_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOC_GPIOC_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOC_GPIOC_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOC_GPIOC_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOC_GPIOC_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOC_GPIOC_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOC_GPIOC_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOC_GPIOC_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOC_GPIOC_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOC_GPIOC_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOC_GPIOC_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOC_GPIOC_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOC_GPIOC_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOC_GPIOC_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOC_GPIOC_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOC_GPIOC_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOC_GPIOC_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOC_GPIOC_BRR_BR15 = 0x8000

	// GPIOC_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOC_GPIOC_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOC_GPIOC_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOC_GPIOC_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOC_GPIOC_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOC_GPIOC_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOC_GPIOC_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOC_GPIOC_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOC_GPIOC_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOC_GPIOC_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOC_GPIOC_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOC_GPIOC_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOC_GPIOC_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOC_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOC_GPIOC_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOC_GPIOC_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOC_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOC_GPIOC_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOC_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOC_GPIOC_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOC_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOC_GPIOC_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOC_GPIOC_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOC_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOC_GPIOC_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOC_GPIOC_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOC_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOC_GPIOC_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOC_GPIOC_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOC_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOC_GPIOC_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOC_GPIOC_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOC_GPIOC_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOC_GPIOC_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOC_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOC_GPIOC_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOC_GPIOC_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOC_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOC_GPIOC_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOC_GPIOC_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOC_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOC_GPIOC_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOC_GPIOC_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOC_VERR: GPIO version register
	// Position of MINREV field.
	GPIOC_GPIOC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOC_GPIOC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOC_GPIOC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOC_GPIOC_VERR_MAJREV_Msk = 0xf0

	// GPIOC_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOC_GPIOC_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOC_GPIOC_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOC_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOC_GPIOC_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOC_GPIOC_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOD: GPIOD
const (
	// GPIOD_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOD_GPIOD_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOD_GPIOD_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOD_GPIOD_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOD_GPIOD_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOD_GPIOD_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOD_GPIOD_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOD_GPIOD_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOD_GPIOD_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOD_GPIOD_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOD_GPIOD_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOD_GPIOD_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOD_GPIOD_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOD_GPIOD_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOD_GPIOD_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOD_GPIOD_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOD_GPIOD_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOD_GPIOD_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOD_GPIOD_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOD_GPIOD_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOD_GPIOD_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOD_GPIOD_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOD_GPIOD_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOD_GPIOD_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOD_GPIOD_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOD_GPIOD_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOD_GPIOD_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOD_GPIOD_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOD_GPIOD_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOD_GPIOD_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOD_GPIOD_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOD_GPIOD_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOD_GPIOD_MODER_MODER15_Msk = 0xc0000000

	// GPIOD_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOD_GPIOD_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOD_GPIOD_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOD_GPIOD_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOD_GPIOD_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOD_GPIOD_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOD_GPIOD_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOD_GPIOD_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOD_GPIOD_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOD_GPIOD_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOD_GPIOD_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOD_GPIOD_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOD_GPIOD_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOD_GPIOD_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOD_GPIOD_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOD_GPIOD_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOD_GPIOD_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOD_GPIOD_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOD_GPIOD_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOD_GPIOD_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOD_GPIOD_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOD_GPIOD_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOD_GPIOD_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOD_GPIOD_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOD_GPIOD_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOD_GPIOD_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOD_GPIOD_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOD_GPIOD_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOD_GPIOD_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOD_GPIOD_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOD_GPIOD_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOD_GPIOD_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOD_GPIOD_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOD_GPIOD_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOD_GPIOD_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOD_GPIOD_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOD_GPIOD_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOD_GPIOD_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOD_GPIOD_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOD_GPIOD_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOD_GPIOD_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOD_GPIOD_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOD_GPIOD_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOD_GPIOD_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOD_GPIOD_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOD_GPIOD_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOD_GPIOD_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOD_GPIOD_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOD_GPIOD_OTYPER_OT15 = 0x8000

	// GPIOD_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOD_GPIOD_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOD_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOD_GPIOD_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOD_GPIOD_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOD_GPIOD_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOD_GPIOD_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOD_GPIOD_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOD_GPIOD_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOD_GPIOD_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOD_GPIOD_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOD_GPIOD_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOD_GPIOD_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOD_GPIOD_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOD_GPIOD_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOD_GPIOD_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOD_GPIOD_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOD_GPIOD_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOD_GPIOD_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOD_GPIOD_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOD_GPIOD_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOD_GPIOD_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOD_GPIOD_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOD_GPIOD_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOD_GPIOD_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOD_GPIOD_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOD_GPIOD_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOD_GPIOD_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOD_GPIOD_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOD_GPIOD_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOD_GPIOD_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOD_GPIOD_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOD_GPIOD_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOD_GPIOD_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOD_GPIOD_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOD_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOD_GPIOD_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOD_GPIOD_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOD_GPIOD_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOD_GPIOD_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOD_GPIOD_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOD_GPIOD_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOD_GPIOD_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOD_GPIOD_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOD_GPIOD_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOD_GPIOD_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOD_GPIOD_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOD_GPIOD_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOD_GPIOD_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOD_GPIOD_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOD_GPIOD_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOD_GPIOD_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOD_GPIOD_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOD_GPIOD_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOD_GPIOD_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOD_GPIOD_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOD_GPIOD_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOD_GPIOD_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOD_GPIOD_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOD_GPIOD_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOD_GPIOD_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOD_GPIOD_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOD_GPIOD_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOD_GPIOD_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOD_GPIOD_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOD_GPIOD_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOD_GPIOD_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOD_GPIOD_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOD_GPIOD_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOD_GPIOD_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOD_GPIOD_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOD_GPIOD_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOD_GPIOD_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOD_GPIOD_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOD_GPIOD_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOD_GPIOD_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOD_GPIOD_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOD_GPIOD_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOD_GPIOD_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOD_GPIOD_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOD_GPIOD_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOD_GPIOD_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOD_GPIOD_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOD_GPIOD_IDR_IDR15 = 0x8000

	// GPIOD_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOD_GPIOD_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOD_GPIOD_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOD_GPIOD_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOD_GPIOD_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOD_GPIOD_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOD_GPIOD_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOD_GPIOD_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOD_GPIOD_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOD_GPIOD_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOD_GPIOD_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOD_GPIOD_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOD_GPIOD_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOD_GPIOD_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOD_GPIOD_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOD_GPIOD_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOD_GPIOD_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOD_GPIOD_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOD_GPIOD_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOD_GPIOD_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOD_GPIOD_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOD_GPIOD_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOD_GPIOD_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOD_GPIOD_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOD_GPIOD_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOD_GPIOD_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOD_GPIOD_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOD_GPIOD_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOD_GPIOD_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOD_GPIOD_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOD_GPIOD_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOD_GPIOD_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOD_GPIOD_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOD_GPIOD_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOD_GPIOD_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOD_GPIOD_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOD_GPIOD_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOD_GPIOD_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOD_GPIOD_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOD_GPIOD_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOD_GPIOD_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOD_GPIOD_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOD_GPIOD_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOD_GPIOD_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOD_GPIOD_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOD_GPIOD_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOD_GPIOD_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOD_GPIOD_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOD_GPIOD_ODR_ODR15 = 0x8000

	// GPIOD_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOD_GPIOD_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOD_GPIOD_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOD_GPIOD_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOD_GPIOD_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOD_GPIOD_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOD_GPIOD_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOD_GPIOD_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOD_GPIOD_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOD_GPIOD_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOD_GPIOD_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOD_GPIOD_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOD_GPIOD_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOD_GPIOD_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOD_GPIOD_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOD_GPIOD_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOD_GPIOD_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOD_GPIOD_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOD_GPIOD_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOD_GPIOD_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOD_GPIOD_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOD_GPIOD_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOD_GPIOD_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOD_GPIOD_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOD_GPIOD_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOD_GPIOD_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOD_GPIOD_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOD_GPIOD_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOD_GPIOD_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOD_GPIOD_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOD_GPIOD_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOD_GPIOD_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOD_GPIOD_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOD_GPIOD_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOD_GPIOD_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOD_GPIOD_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOD_GPIOD_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOD_GPIOD_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOD_GPIOD_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOD_GPIOD_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOD_GPIOD_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOD_GPIOD_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOD_GPIOD_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOD_GPIOD_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOD_GPIOD_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOD_GPIOD_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOD_GPIOD_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOD_GPIOD_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOD_GPIOD_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOD_GPIOD_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOD_GPIOD_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOD_GPIOD_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOD_GPIOD_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOD_GPIOD_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOD_GPIOD_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOD_GPIOD_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOD_GPIOD_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOD_GPIOD_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOD_GPIOD_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOD_GPIOD_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOD_GPIOD_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOD_GPIOD_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOD_GPIOD_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOD_GPIOD_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOD_GPIOD_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOD_GPIOD_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOD_GPIOD_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOD_GPIOD_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOD_GPIOD_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOD_GPIOD_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOD_GPIOD_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOD_GPIOD_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOD_GPIOD_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOD_GPIOD_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOD_GPIOD_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOD_GPIOD_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOD_GPIOD_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOD_GPIOD_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOD_GPIOD_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOD_GPIOD_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOD_GPIOD_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOD_GPIOD_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOD_GPIOD_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOD_GPIOD_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOD_GPIOD_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOD_GPIOD_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOD_GPIOD_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOD_GPIOD_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOD_GPIOD_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOD_GPIOD_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOD_GPIOD_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOD_GPIOD_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOD_GPIOD_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOD_GPIOD_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOD_GPIOD_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOD_GPIOD_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOD_GPIOD_BSRR_BR15 = 0x80000000

	// GPIOD_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOD_GPIOD_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOD_GPIOD_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOD_GPIOD_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOD_GPIOD_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOD_GPIOD_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOD_GPIOD_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOD_GPIOD_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOD_GPIOD_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOD_GPIOD_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOD_GPIOD_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOD_GPIOD_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOD_GPIOD_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOD_GPIOD_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOD_GPIOD_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOD_GPIOD_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOD_GPIOD_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOD_GPIOD_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOD_GPIOD_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOD_GPIOD_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOD_GPIOD_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOD_GPIOD_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOD_GPIOD_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOD_GPIOD_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOD_GPIOD_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOD_GPIOD_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOD_GPIOD_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOD_GPIOD_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOD_GPIOD_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOD_GPIOD_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOD_GPIOD_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOD_GPIOD_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOD_GPIOD_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOD_GPIOD_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOD_GPIOD_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOD_GPIOD_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOD_GPIOD_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOD_GPIOD_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOD_GPIOD_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOD_GPIOD_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOD_GPIOD_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOD_GPIOD_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOD_GPIOD_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOD_GPIOD_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOD_GPIOD_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOD_GPIOD_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOD_GPIOD_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOD_GPIOD_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOD_GPIOD_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOD_GPIOD_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOD_GPIOD_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOD_GPIOD_LCKR_LCKK = 0x10000

	// GPIOD_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOD_GPIOD_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOD_GPIOD_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOD_GPIOD_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOD_GPIOD_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOD_GPIOD_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOD_GPIOD_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOD_GPIOD_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOD_GPIOD_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOD_GPIOD_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOD_GPIOD_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOD_GPIOD_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOD_GPIOD_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOD_GPIOD_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOD_GPIOD_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOD_GPIOD_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOD_GPIOD_AFRL_AFR7_Msk = 0xf0000000

	// GPIOD_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOD_GPIOD_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOD_GPIOD_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOD_GPIOD_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOD_GPIOD_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOD_GPIOD_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOD_GPIOD_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOD_GPIOD_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOD_GPIOD_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOD_GPIOD_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOD_GPIOD_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOD_GPIOD_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOD_GPIOD_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOD_GPIOD_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOD_GPIOD_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOD_GPIOD_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOD_GPIOD_AFRH_AFR15_Msk = 0xf0000000

	// GPIOD_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOD_GPIOD_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOD_GPIOD_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOD_GPIOD_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOD_GPIOD_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOD_GPIOD_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOD_GPIOD_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOD_GPIOD_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOD_GPIOD_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOD_GPIOD_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOD_GPIOD_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOD_GPIOD_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOD_GPIOD_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOD_GPIOD_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOD_GPIOD_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOD_GPIOD_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOD_GPIOD_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOD_GPIOD_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOD_GPIOD_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOD_GPIOD_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOD_GPIOD_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOD_GPIOD_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOD_GPIOD_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOD_GPIOD_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOD_GPIOD_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOD_GPIOD_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOD_GPIOD_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOD_GPIOD_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOD_GPIOD_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOD_GPIOD_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOD_GPIOD_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOD_GPIOD_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOD_GPIOD_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOD_GPIOD_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOD_GPIOD_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOD_GPIOD_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOD_GPIOD_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOD_GPIOD_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOD_GPIOD_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOD_GPIOD_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOD_GPIOD_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOD_GPIOD_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOD_GPIOD_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOD_GPIOD_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOD_GPIOD_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOD_GPIOD_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOD_GPIOD_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOD_GPIOD_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOD_GPIOD_BRR_BR15 = 0x8000

	// GPIOD_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOD_GPIOD_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOD_GPIOD_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOD_GPIOD_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOD_GPIOD_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOD_GPIOD_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOD_GPIOD_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOD_GPIOD_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOD_GPIOD_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOD_GPIOD_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOD_GPIOD_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOD_GPIOD_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOD_GPIOD_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOD_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOD_GPIOD_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOD_GPIOD_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOD_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOD_GPIOD_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOD_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOD_GPIOD_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOD_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOD_GPIOD_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOD_GPIOD_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOD_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOD_GPIOD_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOD_GPIOD_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOD_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOD_GPIOD_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOD_GPIOD_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOD_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOD_GPIOD_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOD_GPIOD_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOD_GPIOD_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOD_GPIOD_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOD_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOD_GPIOD_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOD_GPIOD_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOD_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOD_GPIOD_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOD_GPIOD_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOD_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOD_GPIOD_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOD_GPIOD_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOD_VERR: GPIO version register
	// Position of MINREV field.
	GPIOD_GPIOD_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOD_GPIOD_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOD_GPIOD_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOD_GPIOD_VERR_MAJREV_Msk = 0xf0

	// GPIOD_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOD_GPIOD_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOD_GPIOD_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOD_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOD_GPIOD_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOD_GPIOD_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOE: GPIOE
const (
	// GPIOE_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOE_GPIOE_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOE_GPIOE_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOE_GPIOE_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOE_GPIOE_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOE_GPIOE_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOE_GPIOE_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOE_GPIOE_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOE_GPIOE_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOE_GPIOE_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOE_GPIOE_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOE_GPIOE_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOE_GPIOE_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOE_GPIOE_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOE_GPIOE_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOE_GPIOE_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOE_GPIOE_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOE_GPIOE_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOE_GPIOE_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOE_GPIOE_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOE_GPIOE_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOE_GPIOE_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOE_GPIOE_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOE_GPIOE_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOE_GPIOE_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOE_GPIOE_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOE_GPIOE_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOE_GPIOE_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOE_GPIOE_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOE_GPIOE_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOE_GPIOE_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOE_GPIOE_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOE_GPIOE_MODER_MODER15_Msk = 0xc0000000

	// GPIOE_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOE_GPIOE_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOE_GPIOE_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOE_GPIOE_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOE_GPIOE_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOE_GPIOE_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOE_GPIOE_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOE_GPIOE_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOE_GPIOE_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOE_GPIOE_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOE_GPIOE_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOE_GPIOE_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOE_GPIOE_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOE_GPIOE_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOE_GPIOE_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOE_GPIOE_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOE_GPIOE_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOE_GPIOE_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOE_GPIOE_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOE_GPIOE_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOE_GPIOE_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOE_GPIOE_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOE_GPIOE_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOE_GPIOE_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOE_GPIOE_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOE_GPIOE_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOE_GPIOE_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOE_GPIOE_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOE_GPIOE_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOE_GPIOE_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOE_GPIOE_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOE_GPIOE_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOE_GPIOE_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOE_GPIOE_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOE_GPIOE_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOE_GPIOE_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOE_GPIOE_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOE_GPIOE_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOE_GPIOE_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOE_GPIOE_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOE_GPIOE_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOE_GPIOE_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOE_GPIOE_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOE_GPIOE_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOE_GPIOE_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOE_GPIOE_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOE_GPIOE_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOE_GPIOE_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOE_GPIOE_OTYPER_OT15 = 0x8000

	// GPIOE_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOE_GPIOE_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOE_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOE_GPIOE_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOE_GPIOE_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOE_GPIOE_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOE_GPIOE_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOE_GPIOE_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOE_GPIOE_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOE_GPIOE_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOE_GPIOE_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOE_GPIOE_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOE_GPIOE_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOE_GPIOE_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOE_GPIOE_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOE_GPIOE_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOE_GPIOE_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOE_GPIOE_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOE_GPIOE_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOE_GPIOE_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOE_GPIOE_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOE_GPIOE_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOE_GPIOE_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOE_GPIOE_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOE_GPIOE_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOE_GPIOE_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOE_GPIOE_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOE_GPIOE_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOE_GPIOE_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOE_GPIOE_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOE_GPIOE_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOE_GPIOE_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOE_GPIOE_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOE_GPIOE_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOE_GPIOE_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOE_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOE_GPIOE_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOE_GPIOE_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOE_GPIOE_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOE_GPIOE_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOE_GPIOE_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOE_GPIOE_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOE_GPIOE_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOE_GPIOE_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOE_GPIOE_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOE_GPIOE_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOE_GPIOE_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOE_GPIOE_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOE_GPIOE_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOE_GPIOE_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOE_GPIOE_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOE_GPIOE_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOE_GPIOE_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOE_GPIOE_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOE_GPIOE_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOE_GPIOE_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOE_GPIOE_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOE_GPIOE_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOE_GPIOE_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOE_GPIOE_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOE_GPIOE_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOE_GPIOE_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOE_GPIOE_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOE_GPIOE_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOE_GPIOE_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOE_GPIOE_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOE_GPIOE_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOE_GPIOE_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOE_GPIOE_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOE_GPIOE_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOE_GPIOE_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOE_GPIOE_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOE_GPIOE_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOE_GPIOE_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOE_GPIOE_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOE_GPIOE_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOE_GPIOE_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOE_GPIOE_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOE_GPIOE_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOE_GPIOE_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOE_GPIOE_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOE_GPIOE_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOE_GPIOE_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOE_GPIOE_IDR_IDR15 = 0x8000

	// GPIOE_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOE_GPIOE_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOE_GPIOE_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOE_GPIOE_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOE_GPIOE_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOE_GPIOE_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOE_GPIOE_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOE_GPIOE_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOE_GPIOE_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOE_GPIOE_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOE_GPIOE_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOE_GPIOE_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOE_GPIOE_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOE_GPIOE_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOE_GPIOE_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOE_GPIOE_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOE_GPIOE_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOE_GPIOE_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOE_GPIOE_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOE_GPIOE_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOE_GPIOE_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOE_GPIOE_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOE_GPIOE_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOE_GPIOE_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOE_GPIOE_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOE_GPIOE_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOE_GPIOE_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOE_GPIOE_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOE_GPIOE_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOE_GPIOE_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOE_GPIOE_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOE_GPIOE_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOE_GPIOE_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOE_GPIOE_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOE_GPIOE_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOE_GPIOE_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOE_GPIOE_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOE_GPIOE_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOE_GPIOE_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOE_GPIOE_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOE_GPIOE_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOE_GPIOE_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOE_GPIOE_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOE_GPIOE_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOE_GPIOE_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOE_GPIOE_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOE_GPIOE_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOE_GPIOE_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOE_GPIOE_ODR_ODR15 = 0x8000

	// GPIOE_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOE_GPIOE_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOE_GPIOE_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOE_GPIOE_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOE_GPIOE_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOE_GPIOE_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOE_GPIOE_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOE_GPIOE_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOE_GPIOE_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOE_GPIOE_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOE_GPIOE_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOE_GPIOE_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOE_GPIOE_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOE_GPIOE_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOE_GPIOE_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOE_GPIOE_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOE_GPIOE_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOE_GPIOE_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOE_GPIOE_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOE_GPIOE_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOE_GPIOE_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOE_GPIOE_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOE_GPIOE_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOE_GPIOE_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOE_GPIOE_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOE_GPIOE_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOE_GPIOE_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOE_GPIOE_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOE_GPIOE_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOE_GPIOE_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOE_GPIOE_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOE_GPIOE_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOE_GPIOE_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOE_GPIOE_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOE_GPIOE_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOE_GPIOE_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOE_GPIOE_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOE_GPIOE_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOE_GPIOE_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOE_GPIOE_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOE_GPIOE_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOE_GPIOE_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOE_GPIOE_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOE_GPIOE_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOE_GPIOE_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOE_GPIOE_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOE_GPIOE_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOE_GPIOE_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOE_GPIOE_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOE_GPIOE_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOE_GPIOE_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOE_GPIOE_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOE_GPIOE_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOE_GPIOE_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOE_GPIOE_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOE_GPIOE_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOE_GPIOE_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOE_GPIOE_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOE_GPIOE_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOE_GPIOE_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOE_GPIOE_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOE_GPIOE_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOE_GPIOE_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOE_GPIOE_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOE_GPIOE_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOE_GPIOE_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOE_GPIOE_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOE_GPIOE_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOE_GPIOE_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOE_GPIOE_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOE_GPIOE_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOE_GPIOE_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOE_GPIOE_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOE_GPIOE_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOE_GPIOE_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOE_GPIOE_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOE_GPIOE_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOE_GPIOE_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOE_GPIOE_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOE_GPIOE_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOE_GPIOE_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOE_GPIOE_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOE_GPIOE_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOE_GPIOE_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOE_GPIOE_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOE_GPIOE_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOE_GPIOE_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOE_GPIOE_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOE_GPIOE_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOE_GPIOE_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOE_GPIOE_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOE_GPIOE_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOE_GPIOE_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOE_GPIOE_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOE_GPIOE_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOE_GPIOE_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOE_GPIOE_BSRR_BR15 = 0x80000000

	// GPIOE_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOE_GPIOE_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOE_GPIOE_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOE_GPIOE_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOE_GPIOE_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOE_GPIOE_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOE_GPIOE_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOE_GPIOE_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOE_GPIOE_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOE_GPIOE_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOE_GPIOE_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOE_GPIOE_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOE_GPIOE_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOE_GPIOE_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOE_GPIOE_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOE_GPIOE_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOE_GPIOE_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOE_GPIOE_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOE_GPIOE_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOE_GPIOE_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOE_GPIOE_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOE_GPIOE_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOE_GPIOE_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOE_GPIOE_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOE_GPIOE_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOE_GPIOE_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOE_GPIOE_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOE_GPIOE_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOE_GPIOE_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOE_GPIOE_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOE_GPIOE_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOE_GPIOE_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOE_GPIOE_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOE_GPIOE_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOE_GPIOE_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOE_GPIOE_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOE_GPIOE_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOE_GPIOE_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOE_GPIOE_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOE_GPIOE_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOE_GPIOE_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOE_GPIOE_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOE_GPIOE_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOE_GPIOE_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOE_GPIOE_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOE_GPIOE_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOE_GPIOE_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOE_GPIOE_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOE_GPIOE_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOE_GPIOE_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOE_GPIOE_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOE_GPIOE_LCKR_LCKK = 0x10000

	// GPIOE_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOE_GPIOE_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOE_GPIOE_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOE_GPIOE_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOE_GPIOE_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOE_GPIOE_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOE_GPIOE_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOE_GPIOE_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOE_GPIOE_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOE_GPIOE_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOE_GPIOE_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOE_GPIOE_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOE_GPIOE_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOE_GPIOE_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOE_GPIOE_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOE_GPIOE_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOE_GPIOE_AFRL_AFR7_Msk = 0xf0000000

	// GPIOE_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOE_GPIOE_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOE_GPIOE_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOE_GPIOE_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOE_GPIOE_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOE_GPIOE_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOE_GPIOE_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOE_GPIOE_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOE_GPIOE_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOE_GPIOE_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOE_GPIOE_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOE_GPIOE_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOE_GPIOE_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOE_GPIOE_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOE_GPIOE_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOE_GPIOE_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOE_GPIOE_AFRH_AFR15_Msk = 0xf0000000

	// GPIOE_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOE_GPIOE_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOE_GPIOE_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOE_GPIOE_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOE_GPIOE_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOE_GPIOE_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOE_GPIOE_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOE_GPIOE_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOE_GPIOE_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOE_GPIOE_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOE_GPIOE_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOE_GPIOE_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOE_GPIOE_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOE_GPIOE_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOE_GPIOE_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOE_GPIOE_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOE_GPIOE_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOE_GPIOE_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOE_GPIOE_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOE_GPIOE_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOE_GPIOE_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOE_GPIOE_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOE_GPIOE_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOE_GPIOE_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOE_GPIOE_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOE_GPIOE_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOE_GPIOE_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOE_GPIOE_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOE_GPIOE_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOE_GPIOE_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOE_GPIOE_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOE_GPIOE_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOE_GPIOE_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOE_GPIOE_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOE_GPIOE_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOE_GPIOE_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOE_GPIOE_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOE_GPIOE_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOE_GPIOE_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOE_GPIOE_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOE_GPIOE_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOE_GPIOE_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOE_GPIOE_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOE_GPIOE_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOE_GPIOE_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOE_GPIOE_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOE_GPIOE_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOE_GPIOE_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOE_GPIOE_BRR_BR15 = 0x8000

	// GPIOE_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOE_GPIOE_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOE_GPIOE_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOE_GPIOE_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOE_GPIOE_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOE_GPIOE_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOE_GPIOE_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOE_GPIOE_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOE_GPIOE_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOE_GPIOE_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOE_GPIOE_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOE_GPIOE_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOE_GPIOE_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOE_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOE_GPIOE_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOE_GPIOE_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOE_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOE_GPIOE_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOE_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOE_GPIOE_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOE_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOE_GPIOE_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOE_GPIOE_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOE_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOE_GPIOE_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOE_GPIOE_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOE_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOE_GPIOE_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOE_GPIOE_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOE_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOE_GPIOE_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOE_GPIOE_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOE_GPIOE_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOE_GPIOE_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOE_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOE_GPIOE_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOE_GPIOE_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOE_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOE_GPIOE_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOE_GPIOE_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOE_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOE_GPIOE_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOE_GPIOE_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOE_VERR: GPIO version register
	// Position of MINREV field.
	GPIOE_GPIOE_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOE_GPIOE_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOE_GPIOE_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOE_GPIOE_VERR_MAJREV_Msk = 0xf0

	// GPIOE_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOE_GPIOE_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOE_GPIOE_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOE_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOE_GPIOE_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOE_GPIOE_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOF: GPIOF
const (
	// GPIOF_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOF_GPIOF_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOF_GPIOF_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOF_GPIOF_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOF_GPIOF_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOF_GPIOF_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOF_GPIOF_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOF_GPIOF_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOF_GPIOF_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOF_GPIOF_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOF_GPIOF_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOF_GPIOF_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOF_GPIOF_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOF_GPIOF_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOF_GPIOF_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOF_GPIOF_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOF_GPIOF_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOF_GPIOF_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOF_GPIOF_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOF_GPIOF_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOF_GPIOF_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOF_GPIOF_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOF_GPIOF_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOF_GPIOF_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOF_GPIOF_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOF_GPIOF_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOF_GPIOF_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOF_GPIOF_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOF_GPIOF_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOF_GPIOF_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOF_GPIOF_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOF_GPIOF_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOF_GPIOF_MODER_MODER15_Msk = 0xc0000000

	// GPIOF_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOF_GPIOF_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOF_GPIOF_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOF_GPIOF_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOF_GPIOF_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOF_GPIOF_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOF_GPIOF_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOF_GPIOF_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOF_GPIOF_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOF_GPIOF_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOF_GPIOF_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOF_GPIOF_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOF_GPIOF_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOF_GPIOF_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOF_GPIOF_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOF_GPIOF_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOF_GPIOF_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOF_GPIOF_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOF_GPIOF_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOF_GPIOF_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOF_GPIOF_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOF_GPIOF_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOF_GPIOF_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOF_GPIOF_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOF_GPIOF_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOF_GPIOF_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOF_GPIOF_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOF_GPIOF_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOF_GPIOF_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOF_GPIOF_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOF_GPIOF_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOF_GPIOF_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOF_GPIOF_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOF_GPIOF_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOF_GPIOF_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOF_GPIOF_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOF_GPIOF_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOF_GPIOF_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOF_GPIOF_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOF_GPIOF_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOF_GPIOF_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOF_GPIOF_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOF_GPIOF_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOF_GPIOF_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOF_GPIOF_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOF_GPIOF_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOF_GPIOF_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOF_GPIOF_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOF_GPIOF_OTYPER_OT15 = 0x8000

	// GPIOF_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOF_GPIOF_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOF_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOF_GPIOF_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOF_GPIOF_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOF_GPIOF_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOF_GPIOF_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOF_GPIOF_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOF_GPIOF_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOF_GPIOF_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOF_GPIOF_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOF_GPIOF_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOF_GPIOF_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOF_GPIOF_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOF_GPIOF_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOF_GPIOF_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOF_GPIOF_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOF_GPIOF_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOF_GPIOF_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOF_GPIOF_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOF_GPIOF_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOF_GPIOF_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOF_GPIOF_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOF_GPIOF_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOF_GPIOF_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOF_GPIOF_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOF_GPIOF_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOF_GPIOF_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOF_GPIOF_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOF_GPIOF_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOF_GPIOF_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOF_GPIOF_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOF_GPIOF_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOF_GPIOF_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOF_GPIOF_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOF_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOF_GPIOF_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOF_GPIOF_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOF_GPIOF_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOF_GPIOF_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOF_GPIOF_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOF_GPIOF_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOF_GPIOF_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOF_GPIOF_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOF_GPIOF_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOF_GPIOF_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOF_GPIOF_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOF_GPIOF_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOF_GPIOF_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOF_GPIOF_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOF_GPIOF_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOF_GPIOF_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOF_GPIOF_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOF_GPIOF_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOF_GPIOF_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOF_GPIOF_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOF_GPIOF_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOF_GPIOF_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOF_GPIOF_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOF_GPIOF_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOF_GPIOF_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOF_GPIOF_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOF_GPIOF_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOF_GPIOF_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOF_GPIOF_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOF_GPIOF_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOF_GPIOF_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOF_GPIOF_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOF_GPIOF_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOF_GPIOF_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOF_GPIOF_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOF_GPIOF_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOF_GPIOF_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOF_GPIOF_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOF_GPIOF_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOF_GPIOF_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOF_GPIOF_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOF_GPIOF_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOF_GPIOF_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOF_GPIOF_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOF_GPIOF_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOF_GPIOF_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOF_GPIOF_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOF_GPIOF_IDR_IDR15 = 0x8000

	// GPIOF_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOF_GPIOF_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOF_GPIOF_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOF_GPIOF_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOF_GPIOF_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOF_GPIOF_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOF_GPIOF_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOF_GPIOF_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOF_GPIOF_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOF_GPIOF_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOF_GPIOF_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOF_GPIOF_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOF_GPIOF_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOF_GPIOF_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOF_GPIOF_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOF_GPIOF_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOF_GPIOF_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOF_GPIOF_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOF_GPIOF_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOF_GPIOF_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOF_GPIOF_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOF_GPIOF_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOF_GPIOF_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOF_GPIOF_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOF_GPIOF_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOF_GPIOF_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOF_GPIOF_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOF_GPIOF_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOF_GPIOF_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOF_GPIOF_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOF_GPIOF_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOF_GPIOF_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOF_GPIOF_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOF_GPIOF_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOF_GPIOF_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOF_GPIOF_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOF_GPIOF_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOF_GPIOF_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOF_GPIOF_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOF_GPIOF_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOF_GPIOF_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOF_GPIOF_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOF_GPIOF_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOF_GPIOF_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOF_GPIOF_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOF_GPIOF_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOF_GPIOF_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOF_GPIOF_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOF_GPIOF_ODR_ODR15 = 0x8000

	// GPIOF_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOF_GPIOF_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOF_GPIOF_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOF_GPIOF_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOF_GPIOF_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOF_GPIOF_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOF_GPIOF_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOF_GPIOF_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOF_GPIOF_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOF_GPIOF_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOF_GPIOF_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOF_GPIOF_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOF_GPIOF_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOF_GPIOF_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOF_GPIOF_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOF_GPIOF_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOF_GPIOF_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOF_GPIOF_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOF_GPIOF_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOF_GPIOF_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOF_GPIOF_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOF_GPIOF_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOF_GPIOF_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOF_GPIOF_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOF_GPIOF_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOF_GPIOF_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOF_GPIOF_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOF_GPIOF_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOF_GPIOF_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOF_GPIOF_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOF_GPIOF_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOF_GPIOF_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOF_GPIOF_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOF_GPIOF_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOF_GPIOF_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOF_GPIOF_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOF_GPIOF_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOF_GPIOF_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOF_GPIOF_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOF_GPIOF_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOF_GPIOF_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOF_GPIOF_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOF_GPIOF_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOF_GPIOF_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOF_GPIOF_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOF_GPIOF_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOF_GPIOF_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOF_GPIOF_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOF_GPIOF_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOF_GPIOF_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOF_GPIOF_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOF_GPIOF_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOF_GPIOF_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOF_GPIOF_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOF_GPIOF_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOF_GPIOF_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOF_GPIOF_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOF_GPIOF_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOF_GPIOF_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOF_GPIOF_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOF_GPIOF_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOF_GPIOF_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOF_GPIOF_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOF_GPIOF_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOF_GPIOF_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOF_GPIOF_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOF_GPIOF_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOF_GPIOF_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOF_GPIOF_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOF_GPIOF_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOF_GPIOF_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOF_GPIOF_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOF_GPIOF_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOF_GPIOF_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOF_GPIOF_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOF_GPIOF_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOF_GPIOF_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOF_GPIOF_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOF_GPIOF_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOF_GPIOF_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOF_GPIOF_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOF_GPIOF_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOF_GPIOF_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOF_GPIOF_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOF_GPIOF_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOF_GPIOF_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOF_GPIOF_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOF_GPIOF_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOF_GPIOF_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOF_GPIOF_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOF_GPIOF_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOF_GPIOF_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOF_GPIOF_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOF_GPIOF_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOF_GPIOF_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOF_GPIOF_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOF_GPIOF_BSRR_BR15 = 0x80000000

	// GPIOF_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOF_GPIOF_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOF_GPIOF_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOF_GPIOF_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOF_GPIOF_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOF_GPIOF_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOF_GPIOF_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOF_GPIOF_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOF_GPIOF_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOF_GPIOF_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOF_GPIOF_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOF_GPIOF_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOF_GPIOF_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOF_GPIOF_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOF_GPIOF_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOF_GPIOF_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOF_GPIOF_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOF_GPIOF_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOF_GPIOF_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOF_GPIOF_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOF_GPIOF_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOF_GPIOF_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOF_GPIOF_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOF_GPIOF_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOF_GPIOF_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOF_GPIOF_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOF_GPIOF_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOF_GPIOF_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOF_GPIOF_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOF_GPIOF_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOF_GPIOF_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOF_GPIOF_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOF_GPIOF_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOF_GPIOF_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOF_GPIOF_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOF_GPIOF_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOF_GPIOF_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOF_GPIOF_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOF_GPIOF_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOF_GPIOF_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOF_GPIOF_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOF_GPIOF_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOF_GPIOF_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOF_GPIOF_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOF_GPIOF_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOF_GPIOF_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOF_GPIOF_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOF_GPIOF_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOF_GPIOF_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOF_GPIOF_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOF_GPIOF_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOF_GPIOF_LCKR_LCKK = 0x10000

	// GPIOF_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOF_GPIOF_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOF_GPIOF_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOF_GPIOF_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOF_GPIOF_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOF_GPIOF_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOF_GPIOF_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOF_GPIOF_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOF_GPIOF_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOF_GPIOF_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOF_GPIOF_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOF_GPIOF_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOF_GPIOF_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOF_GPIOF_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOF_GPIOF_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOF_GPIOF_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOF_GPIOF_AFRL_AFR7_Msk = 0xf0000000

	// GPIOF_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOF_GPIOF_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOF_GPIOF_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOF_GPIOF_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOF_GPIOF_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOF_GPIOF_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOF_GPIOF_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOF_GPIOF_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOF_GPIOF_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOF_GPIOF_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOF_GPIOF_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOF_GPIOF_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOF_GPIOF_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOF_GPIOF_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOF_GPIOF_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOF_GPIOF_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOF_GPIOF_AFRH_AFR15_Msk = 0xf0000000

	// GPIOF_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOF_GPIOF_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOF_GPIOF_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOF_GPIOF_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOF_GPIOF_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOF_GPIOF_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOF_GPIOF_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOF_GPIOF_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOF_GPIOF_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOF_GPIOF_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOF_GPIOF_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOF_GPIOF_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOF_GPIOF_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOF_GPIOF_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOF_GPIOF_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOF_GPIOF_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOF_GPIOF_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOF_GPIOF_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOF_GPIOF_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOF_GPIOF_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOF_GPIOF_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOF_GPIOF_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOF_GPIOF_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOF_GPIOF_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOF_GPIOF_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOF_GPIOF_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOF_GPIOF_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOF_GPIOF_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOF_GPIOF_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOF_GPIOF_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOF_GPIOF_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOF_GPIOF_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOF_GPIOF_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOF_GPIOF_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOF_GPIOF_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOF_GPIOF_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOF_GPIOF_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOF_GPIOF_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOF_GPIOF_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOF_GPIOF_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOF_GPIOF_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOF_GPIOF_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOF_GPIOF_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOF_GPIOF_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOF_GPIOF_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOF_GPIOF_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOF_GPIOF_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOF_GPIOF_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOF_GPIOF_BRR_BR15 = 0x8000

	// GPIOF_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOF_GPIOF_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOF_GPIOF_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOF_GPIOF_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOF_GPIOF_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOF_GPIOF_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOF_GPIOF_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOF_GPIOF_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOF_GPIOF_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOF_GPIOF_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOF_GPIOF_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOF_GPIOF_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOF_GPIOF_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOF_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOF_GPIOF_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOF_GPIOF_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOF_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOF_GPIOF_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOF_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOF_GPIOF_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOF_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOF_GPIOF_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOF_GPIOF_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOF_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOF_GPIOF_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOF_GPIOF_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOF_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOF_GPIOF_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOF_GPIOF_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOF_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOF_GPIOF_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOF_GPIOF_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOF_GPIOF_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOF_GPIOF_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOF_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOF_GPIOF_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOF_GPIOF_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOF_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOF_GPIOF_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOF_GPIOF_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOF_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOF_GPIOF_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOF_GPIOF_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOF_VERR: GPIO version register
	// Position of MINREV field.
	GPIOF_GPIOF_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOF_GPIOF_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOF_GPIOF_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOF_GPIOF_VERR_MAJREV_Msk = 0xf0

	// GPIOF_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOF_GPIOF_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOF_GPIOF_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOF_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOF_GPIOF_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOF_GPIOF_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOG: GPIOG
const (
	// GPIOG_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOG_GPIOG_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOG_GPIOG_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOG_GPIOG_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOG_GPIOG_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOG_GPIOG_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOG_GPIOG_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOG_GPIOG_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOG_GPIOG_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOG_GPIOG_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOG_GPIOG_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOG_GPIOG_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOG_GPIOG_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOG_GPIOG_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOG_GPIOG_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOG_GPIOG_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOG_GPIOG_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOG_GPIOG_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOG_GPIOG_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOG_GPIOG_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOG_GPIOG_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOG_GPIOG_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOG_GPIOG_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOG_GPIOG_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOG_GPIOG_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOG_GPIOG_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOG_GPIOG_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOG_GPIOG_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOG_GPIOG_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOG_GPIOG_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOG_GPIOG_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOG_GPIOG_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOG_GPIOG_MODER_MODER15_Msk = 0xc0000000

	// GPIOG_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOG_GPIOG_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOG_GPIOG_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOG_GPIOG_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOG_GPIOG_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOG_GPIOG_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOG_GPIOG_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOG_GPIOG_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOG_GPIOG_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOG_GPIOG_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOG_GPIOG_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOG_GPIOG_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOG_GPIOG_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOG_GPIOG_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOG_GPIOG_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOG_GPIOG_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOG_GPIOG_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOG_GPIOG_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOG_GPIOG_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOG_GPIOG_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOG_GPIOG_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOG_GPIOG_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOG_GPIOG_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOG_GPIOG_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOG_GPIOG_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOG_GPIOG_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOG_GPIOG_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOG_GPIOG_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOG_GPIOG_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOG_GPIOG_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOG_GPIOG_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOG_GPIOG_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOG_GPIOG_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOG_GPIOG_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOG_GPIOG_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOG_GPIOG_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOG_GPIOG_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOG_GPIOG_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOG_GPIOG_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOG_GPIOG_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOG_GPIOG_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOG_GPIOG_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOG_GPIOG_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOG_GPIOG_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOG_GPIOG_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOG_GPIOG_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOG_GPIOG_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOG_GPIOG_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOG_GPIOG_OTYPER_OT15 = 0x8000

	// GPIOG_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOG_GPIOG_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOG_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOG_GPIOG_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOG_GPIOG_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOG_GPIOG_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOG_GPIOG_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOG_GPIOG_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOG_GPIOG_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOG_GPIOG_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOG_GPIOG_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOG_GPIOG_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOG_GPIOG_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOG_GPIOG_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOG_GPIOG_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOG_GPIOG_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOG_GPIOG_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOG_GPIOG_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOG_GPIOG_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOG_GPIOG_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOG_GPIOG_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOG_GPIOG_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOG_GPIOG_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOG_GPIOG_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOG_GPIOG_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOG_GPIOG_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOG_GPIOG_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOG_GPIOG_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOG_GPIOG_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOG_GPIOG_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOG_GPIOG_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOG_GPIOG_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOG_GPIOG_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOG_GPIOG_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOG_GPIOG_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOG_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOG_GPIOG_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOG_GPIOG_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOG_GPIOG_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOG_GPIOG_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOG_GPIOG_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOG_GPIOG_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOG_GPIOG_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOG_GPIOG_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOG_GPIOG_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOG_GPIOG_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOG_GPIOG_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOG_GPIOG_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOG_GPIOG_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOG_GPIOG_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOG_GPIOG_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOG_GPIOG_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOG_GPIOG_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOG_GPIOG_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOG_GPIOG_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOG_GPIOG_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOG_GPIOG_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOG_GPIOG_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOG_GPIOG_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOG_GPIOG_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOG_GPIOG_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOG_GPIOG_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOG_GPIOG_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOG_GPIOG_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOG_GPIOG_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOG_GPIOG_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOG_GPIOG_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOG_GPIOG_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOG_GPIOG_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOG_GPIOG_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOG_GPIOG_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOG_GPIOG_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOG_GPIOG_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOG_GPIOG_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOG_GPIOG_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOG_GPIOG_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOG_GPIOG_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOG_GPIOG_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOG_GPIOG_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOG_GPIOG_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOG_GPIOG_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOG_GPIOG_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOG_GPIOG_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOG_GPIOG_IDR_IDR15 = 0x8000

	// GPIOG_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOG_GPIOG_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOG_GPIOG_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOG_GPIOG_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOG_GPIOG_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOG_GPIOG_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOG_GPIOG_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOG_GPIOG_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOG_GPIOG_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOG_GPIOG_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOG_GPIOG_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOG_GPIOG_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOG_GPIOG_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOG_GPIOG_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOG_GPIOG_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOG_GPIOG_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOG_GPIOG_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOG_GPIOG_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOG_GPIOG_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOG_GPIOG_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOG_GPIOG_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOG_GPIOG_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOG_GPIOG_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOG_GPIOG_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOG_GPIOG_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOG_GPIOG_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOG_GPIOG_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOG_GPIOG_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOG_GPIOG_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOG_GPIOG_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOG_GPIOG_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOG_GPIOG_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOG_GPIOG_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOG_GPIOG_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOG_GPIOG_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOG_GPIOG_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOG_GPIOG_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOG_GPIOG_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOG_GPIOG_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOG_GPIOG_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOG_GPIOG_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOG_GPIOG_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOG_GPIOG_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOG_GPIOG_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOG_GPIOG_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOG_GPIOG_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOG_GPIOG_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOG_GPIOG_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOG_GPIOG_ODR_ODR15 = 0x8000

	// GPIOG_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOG_GPIOG_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOG_GPIOG_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOG_GPIOG_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOG_GPIOG_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOG_GPIOG_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOG_GPIOG_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOG_GPIOG_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOG_GPIOG_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOG_GPIOG_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOG_GPIOG_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOG_GPIOG_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOG_GPIOG_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOG_GPIOG_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOG_GPIOG_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOG_GPIOG_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOG_GPIOG_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOG_GPIOG_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOG_GPIOG_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOG_GPIOG_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOG_GPIOG_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOG_GPIOG_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOG_GPIOG_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOG_GPIOG_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOG_GPIOG_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOG_GPIOG_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOG_GPIOG_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOG_GPIOG_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOG_GPIOG_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOG_GPIOG_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOG_GPIOG_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOG_GPIOG_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOG_GPIOG_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOG_GPIOG_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOG_GPIOG_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOG_GPIOG_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOG_GPIOG_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOG_GPIOG_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOG_GPIOG_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOG_GPIOG_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOG_GPIOG_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOG_GPIOG_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOG_GPIOG_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOG_GPIOG_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOG_GPIOG_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOG_GPIOG_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOG_GPIOG_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOG_GPIOG_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOG_GPIOG_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOG_GPIOG_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOG_GPIOG_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOG_GPIOG_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOG_GPIOG_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOG_GPIOG_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOG_GPIOG_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOG_GPIOG_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOG_GPIOG_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOG_GPIOG_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOG_GPIOG_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOG_GPIOG_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOG_GPIOG_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOG_GPIOG_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOG_GPIOG_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOG_GPIOG_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOG_GPIOG_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOG_GPIOG_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOG_GPIOG_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOG_GPIOG_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOG_GPIOG_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOG_GPIOG_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOG_GPIOG_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOG_GPIOG_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOG_GPIOG_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOG_GPIOG_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOG_GPIOG_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOG_GPIOG_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOG_GPIOG_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOG_GPIOG_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOG_GPIOG_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOG_GPIOG_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOG_GPIOG_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOG_GPIOG_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOG_GPIOG_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOG_GPIOG_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOG_GPIOG_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOG_GPIOG_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOG_GPIOG_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOG_GPIOG_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOG_GPIOG_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOG_GPIOG_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOG_GPIOG_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOG_GPIOG_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOG_GPIOG_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOG_GPIOG_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOG_GPIOG_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOG_GPIOG_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOG_GPIOG_BSRR_BR15 = 0x80000000

	// GPIOG_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOG_GPIOG_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOG_GPIOG_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOG_GPIOG_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOG_GPIOG_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOG_GPIOG_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOG_GPIOG_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOG_GPIOG_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOG_GPIOG_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOG_GPIOG_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOG_GPIOG_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOG_GPIOG_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOG_GPIOG_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOG_GPIOG_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOG_GPIOG_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOG_GPIOG_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOG_GPIOG_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOG_GPIOG_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOG_GPIOG_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOG_GPIOG_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOG_GPIOG_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOG_GPIOG_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOG_GPIOG_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOG_GPIOG_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOG_GPIOG_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOG_GPIOG_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOG_GPIOG_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOG_GPIOG_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOG_GPIOG_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOG_GPIOG_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOG_GPIOG_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOG_GPIOG_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOG_GPIOG_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOG_GPIOG_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOG_GPIOG_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOG_GPIOG_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOG_GPIOG_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOG_GPIOG_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOG_GPIOG_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOG_GPIOG_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOG_GPIOG_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOG_GPIOG_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOG_GPIOG_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOG_GPIOG_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOG_GPIOG_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOG_GPIOG_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOG_GPIOG_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOG_GPIOG_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOG_GPIOG_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOG_GPIOG_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOG_GPIOG_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOG_GPIOG_LCKR_LCKK = 0x10000

	// GPIOG_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOG_GPIOG_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOG_GPIOG_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOG_GPIOG_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOG_GPIOG_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOG_GPIOG_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOG_GPIOG_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOG_GPIOG_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOG_GPIOG_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOG_GPIOG_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOG_GPIOG_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOG_GPIOG_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOG_GPIOG_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOG_GPIOG_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOG_GPIOG_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOG_GPIOG_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOG_GPIOG_AFRL_AFR7_Msk = 0xf0000000

	// GPIOG_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOG_GPIOG_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOG_GPIOG_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOG_GPIOG_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOG_GPIOG_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOG_GPIOG_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOG_GPIOG_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOG_GPIOG_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOG_GPIOG_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOG_GPIOG_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOG_GPIOG_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOG_GPIOG_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOG_GPIOG_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOG_GPIOG_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOG_GPIOG_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOG_GPIOG_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOG_GPIOG_AFRH_AFR15_Msk = 0xf0000000

	// GPIOG_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOG_GPIOG_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOG_GPIOG_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOG_GPIOG_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOG_GPIOG_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOG_GPIOG_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOG_GPIOG_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOG_GPIOG_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOG_GPIOG_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOG_GPIOG_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOG_GPIOG_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOG_GPIOG_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOG_GPIOG_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOG_GPIOG_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOG_GPIOG_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOG_GPIOG_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOG_GPIOG_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOG_GPIOG_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOG_GPIOG_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOG_GPIOG_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOG_GPIOG_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOG_GPIOG_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOG_GPIOG_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOG_GPIOG_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOG_GPIOG_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOG_GPIOG_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOG_GPIOG_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOG_GPIOG_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOG_GPIOG_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOG_GPIOG_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOG_GPIOG_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOG_GPIOG_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOG_GPIOG_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOG_GPIOG_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOG_GPIOG_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOG_GPIOG_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOG_GPIOG_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOG_GPIOG_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOG_GPIOG_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOG_GPIOG_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOG_GPIOG_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOG_GPIOG_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOG_GPIOG_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOG_GPIOG_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOG_GPIOG_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOG_GPIOG_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOG_GPIOG_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOG_GPIOG_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOG_GPIOG_BRR_BR15 = 0x8000

	// GPIOG_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOG_GPIOG_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOG_GPIOG_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOG_GPIOG_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOG_GPIOG_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOG_GPIOG_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOG_GPIOG_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOG_GPIOG_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOG_GPIOG_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOG_GPIOG_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOG_GPIOG_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOG_GPIOG_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOG_GPIOG_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOG_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOG_GPIOG_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOG_GPIOG_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOG_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOG_GPIOG_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOG_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOG_GPIOG_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOG_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOG_GPIOG_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOG_GPIOG_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOG_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOG_GPIOG_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOG_GPIOG_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOG_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOG_GPIOG_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOG_GPIOG_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOG_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOG_GPIOG_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOG_GPIOG_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOG_GPIOG_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOG_GPIOG_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOG_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOG_GPIOG_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOG_GPIOG_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOG_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOG_GPIOG_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOG_GPIOG_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOG_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOG_GPIOG_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOG_GPIOG_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOG_VERR: GPIO version register
	// Position of MINREV field.
	GPIOG_GPIOG_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOG_GPIOG_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOG_GPIOG_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOG_GPIOG_VERR_MAJREV_Msk = 0xf0

	// GPIOG_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOG_GPIOG_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOG_GPIOG_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOG_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOG_GPIOG_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOG_GPIOG_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOH: GPIOH
const (
	// GPIOH_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOH_GPIOH_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOH_GPIOH_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOH_GPIOH_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOH_GPIOH_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOH_GPIOH_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOH_GPIOH_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOH_GPIOH_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOH_GPIOH_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOH_GPIOH_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOH_GPIOH_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOH_GPIOH_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOH_GPIOH_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOH_GPIOH_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOH_GPIOH_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOH_GPIOH_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOH_GPIOH_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOH_GPIOH_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOH_GPIOH_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOH_GPIOH_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOH_GPIOH_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOH_GPIOH_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOH_GPIOH_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOH_GPIOH_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOH_GPIOH_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOH_GPIOH_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOH_GPIOH_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOH_GPIOH_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOH_GPIOH_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOH_GPIOH_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOH_GPIOH_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOH_GPIOH_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOH_GPIOH_MODER_MODER15_Msk = 0xc0000000

	// GPIOH_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOH_GPIOH_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOH_GPIOH_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOH_GPIOH_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOH_GPIOH_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOH_GPIOH_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOH_GPIOH_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOH_GPIOH_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOH_GPIOH_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOH_GPIOH_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOH_GPIOH_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOH_GPIOH_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOH_GPIOH_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOH_GPIOH_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOH_GPIOH_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOH_GPIOH_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOH_GPIOH_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOH_GPIOH_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOH_GPIOH_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOH_GPIOH_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOH_GPIOH_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOH_GPIOH_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOH_GPIOH_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOH_GPIOH_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOH_GPIOH_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOH_GPIOH_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOH_GPIOH_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOH_GPIOH_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOH_GPIOH_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOH_GPIOH_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOH_GPIOH_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOH_GPIOH_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOH_GPIOH_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOH_GPIOH_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOH_GPIOH_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOH_GPIOH_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOH_GPIOH_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOH_GPIOH_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOH_GPIOH_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOH_GPIOH_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOH_GPIOH_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOH_GPIOH_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOH_GPIOH_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOH_GPIOH_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOH_GPIOH_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOH_GPIOH_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOH_GPIOH_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOH_GPIOH_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOH_GPIOH_OTYPER_OT15 = 0x8000

	// GPIOH_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOH_GPIOH_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOH_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOH_GPIOH_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOH_GPIOH_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOH_GPIOH_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOH_GPIOH_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOH_GPIOH_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOH_GPIOH_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOH_GPIOH_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOH_GPIOH_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOH_GPIOH_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOH_GPIOH_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOH_GPIOH_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOH_GPIOH_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOH_GPIOH_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOH_GPIOH_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOH_GPIOH_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOH_GPIOH_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOH_GPIOH_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOH_GPIOH_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOH_GPIOH_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOH_GPIOH_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOH_GPIOH_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOH_GPIOH_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOH_GPIOH_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOH_GPIOH_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOH_GPIOH_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOH_GPIOH_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOH_GPIOH_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOH_GPIOH_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOH_GPIOH_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOH_GPIOH_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOH_GPIOH_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOH_GPIOH_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOH_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOH_GPIOH_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOH_GPIOH_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOH_GPIOH_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOH_GPIOH_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOH_GPIOH_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOH_GPIOH_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOH_GPIOH_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOH_GPIOH_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOH_GPIOH_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOH_GPIOH_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOH_GPIOH_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOH_GPIOH_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOH_GPIOH_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOH_GPIOH_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOH_GPIOH_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOH_GPIOH_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOH_GPIOH_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOH_GPIOH_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOH_GPIOH_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOH_GPIOH_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOH_GPIOH_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOH_GPIOH_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOH_GPIOH_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOH_GPIOH_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOH_GPIOH_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOH_GPIOH_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOH_GPIOH_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOH_GPIOH_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOH_GPIOH_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOH_GPIOH_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOH_GPIOH_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOH_GPIOH_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOH_GPIOH_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOH_GPIOH_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOH_GPIOH_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOH_GPIOH_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOH_GPIOH_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOH_GPIOH_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOH_GPIOH_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOH_GPIOH_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOH_GPIOH_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOH_GPIOH_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOH_GPIOH_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOH_GPIOH_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOH_GPIOH_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOH_GPIOH_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOH_GPIOH_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOH_GPIOH_IDR_IDR15 = 0x8000

	// GPIOH_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOH_GPIOH_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOH_GPIOH_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOH_GPIOH_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOH_GPIOH_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOH_GPIOH_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOH_GPIOH_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOH_GPIOH_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOH_GPIOH_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOH_GPIOH_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOH_GPIOH_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOH_GPIOH_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOH_GPIOH_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOH_GPIOH_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOH_GPIOH_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOH_GPIOH_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOH_GPIOH_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOH_GPIOH_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOH_GPIOH_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOH_GPIOH_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOH_GPIOH_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOH_GPIOH_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOH_GPIOH_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOH_GPIOH_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOH_GPIOH_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOH_GPIOH_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOH_GPIOH_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOH_GPIOH_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOH_GPIOH_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOH_GPIOH_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOH_GPIOH_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOH_GPIOH_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOH_GPIOH_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOH_GPIOH_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOH_GPIOH_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOH_GPIOH_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOH_GPIOH_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOH_GPIOH_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOH_GPIOH_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOH_GPIOH_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOH_GPIOH_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOH_GPIOH_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOH_GPIOH_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOH_GPIOH_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOH_GPIOH_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOH_GPIOH_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOH_GPIOH_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOH_GPIOH_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOH_GPIOH_ODR_ODR15 = 0x8000

	// GPIOH_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOH_GPIOH_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOH_GPIOH_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOH_GPIOH_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOH_GPIOH_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOH_GPIOH_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOH_GPIOH_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOH_GPIOH_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOH_GPIOH_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOH_GPIOH_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOH_GPIOH_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOH_GPIOH_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOH_GPIOH_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOH_GPIOH_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOH_GPIOH_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOH_GPIOH_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOH_GPIOH_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOH_GPIOH_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOH_GPIOH_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOH_GPIOH_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOH_GPIOH_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOH_GPIOH_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOH_GPIOH_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOH_GPIOH_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOH_GPIOH_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOH_GPIOH_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOH_GPIOH_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOH_GPIOH_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOH_GPIOH_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOH_GPIOH_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOH_GPIOH_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOH_GPIOH_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOH_GPIOH_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOH_GPIOH_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOH_GPIOH_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOH_GPIOH_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOH_GPIOH_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOH_GPIOH_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOH_GPIOH_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOH_GPIOH_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOH_GPIOH_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOH_GPIOH_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOH_GPIOH_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOH_GPIOH_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOH_GPIOH_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOH_GPIOH_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOH_GPIOH_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOH_GPIOH_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOH_GPIOH_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOH_GPIOH_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOH_GPIOH_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOH_GPIOH_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOH_GPIOH_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOH_GPIOH_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOH_GPIOH_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOH_GPIOH_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOH_GPIOH_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOH_GPIOH_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOH_GPIOH_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOH_GPIOH_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOH_GPIOH_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOH_GPIOH_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOH_GPIOH_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOH_GPIOH_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOH_GPIOH_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOH_GPIOH_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOH_GPIOH_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOH_GPIOH_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOH_GPIOH_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOH_GPIOH_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOH_GPIOH_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOH_GPIOH_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOH_GPIOH_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOH_GPIOH_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOH_GPIOH_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOH_GPIOH_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOH_GPIOH_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOH_GPIOH_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOH_GPIOH_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOH_GPIOH_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOH_GPIOH_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOH_GPIOH_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOH_GPIOH_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOH_GPIOH_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOH_GPIOH_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOH_GPIOH_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOH_GPIOH_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOH_GPIOH_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOH_GPIOH_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOH_GPIOH_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOH_GPIOH_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOH_GPIOH_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOH_GPIOH_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOH_GPIOH_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOH_GPIOH_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOH_GPIOH_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOH_GPIOH_BSRR_BR15 = 0x80000000

	// GPIOH_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOH_GPIOH_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOH_GPIOH_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOH_GPIOH_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOH_GPIOH_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOH_GPIOH_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOH_GPIOH_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOH_GPIOH_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOH_GPIOH_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOH_GPIOH_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOH_GPIOH_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOH_GPIOH_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOH_GPIOH_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOH_GPIOH_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOH_GPIOH_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOH_GPIOH_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOH_GPIOH_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOH_GPIOH_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOH_GPIOH_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOH_GPIOH_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOH_GPIOH_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOH_GPIOH_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOH_GPIOH_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOH_GPIOH_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOH_GPIOH_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOH_GPIOH_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOH_GPIOH_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOH_GPIOH_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOH_GPIOH_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOH_GPIOH_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOH_GPIOH_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOH_GPIOH_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOH_GPIOH_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOH_GPIOH_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOH_GPIOH_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOH_GPIOH_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOH_GPIOH_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOH_GPIOH_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOH_GPIOH_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOH_GPIOH_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOH_GPIOH_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOH_GPIOH_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOH_GPIOH_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOH_GPIOH_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOH_GPIOH_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOH_GPIOH_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOH_GPIOH_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOH_GPIOH_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOH_GPIOH_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOH_GPIOH_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOH_GPIOH_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOH_GPIOH_LCKR_LCKK = 0x10000

	// GPIOH_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOH_GPIOH_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOH_GPIOH_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOH_GPIOH_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOH_GPIOH_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOH_GPIOH_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOH_GPIOH_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOH_GPIOH_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOH_GPIOH_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOH_GPIOH_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOH_GPIOH_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOH_GPIOH_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOH_GPIOH_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOH_GPIOH_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOH_GPIOH_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOH_GPIOH_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOH_GPIOH_AFRL_AFR7_Msk = 0xf0000000

	// GPIOH_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOH_GPIOH_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOH_GPIOH_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOH_GPIOH_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOH_GPIOH_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOH_GPIOH_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOH_GPIOH_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOH_GPIOH_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOH_GPIOH_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOH_GPIOH_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOH_GPIOH_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOH_GPIOH_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOH_GPIOH_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOH_GPIOH_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOH_GPIOH_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOH_GPIOH_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOH_GPIOH_AFRH_AFR15_Msk = 0xf0000000

	// GPIOH_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOH_GPIOH_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOH_GPIOH_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOH_GPIOH_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOH_GPIOH_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOH_GPIOH_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOH_GPIOH_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOH_GPIOH_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOH_GPIOH_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOH_GPIOH_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOH_GPIOH_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOH_GPIOH_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOH_GPIOH_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOH_GPIOH_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOH_GPIOH_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOH_GPIOH_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOH_GPIOH_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOH_GPIOH_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOH_GPIOH_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOH_GPIOH_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOH_GPIOH_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOH_GPIOH_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOH_GPIOH_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOH_GPIOH_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOH_GPIOH_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOH_GPIOH_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOH_GPIOH_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOH_GPIOH_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOH_GPIOH_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOH_GPIOH_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOH_GPIOH_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOH_GPIOH_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOH_GPIOH_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOH_GPIOH_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOH_GPIOH_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOH_GPIOH_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOH_GPIOH_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOH_GPIOH_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOH_GPIOH_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOH_GPIOH_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOH_GPIOH_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOH_GPIOH_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOH_GPIOH_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOH_GPIOH_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOH_GPIOH_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOH_GPIOH_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOH_GPIOH_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOH_GPIOH_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOH_GPIOH_BRR_BR15 = 0x8000

	// GPIOH_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOH_GPIOH_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOH_GPIOH_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOH_GPIOH_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOH_GPIOH_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOH_GPIOH_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOH_GPIOH_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOH_GPIOH_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOH_GPIOH_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOH_GPIOH_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOH_GPIOH_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOH_GPIOH_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOH_GPIOH_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOH_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOH_GPIOH_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOH_GPIOH_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOH_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOH_GPIOH_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOH_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOH_GPIOH_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOH_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOH_GPIOH_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOH_GPIOH_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOH_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOH_GPIOH_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOH_GPIOH_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOH_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOH_GPIOH_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOH_GPIOH_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOH_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOH_GPIOH_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOH_GPIOH_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOH_GPIOH_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOH_GPIOH_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOH_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOH_GPIOH_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOH_GPIOH_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOH_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOH_GPIOH_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOH_GPIOH_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOH_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOH_GPIOH_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOH_GPIOH_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOH_VERR: GPIO version register
	// Position of MINREV field.
	GPIOH_GPIOH_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOH_GPIOH_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOH_GPIOH_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOH_GPIOH_VERR_MAJREV_Msk = 0xf0

	// GPIOH_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOH_GPIOH_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOH_GPIOH_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOH_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOH_GPIOH_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOH_GPIOH_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOI: GPIOI
const (
	// GPIOI_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOI_GPIOI_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOI_GPIOI_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOI_GPIOI_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOI_GPIOI_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOI_GPIOI_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOI_GPIOI_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOI_GPIOI_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOI_GPIOI_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOI_GPIOI_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOI_GPIOI_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOI_GPIOI_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOI_GPIOI_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOI_GPIOI_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOI_GPIOI_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOI_GPIOI_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOI_GPIOI_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOI_GPIOI_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOI_GPIOI_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOI_GPIOI_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOI_GPIOI_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOI_GPIOI_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOI_GPIOI_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOI_GPIOI_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOI_GPIOI_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOI_GPIOI_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOI_GPIOI_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOI_GPIOI_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOI_GPIOI_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOI_GPIOI_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOI_GPIOI_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOI_GPIOI_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOI_GPIOI_MODER_MODER15_Msk = 0xc0000000

	// GPIOI_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOI_GPIOI_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOI_GPIOI_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOI_GPIOI_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOI_GPIOI_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOI_GPIOI_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOI_GPIOI_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOI_GPIOI_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOI_GPIOI_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOI_GPIOI_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOI_GPIOI_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOI_GPIOI_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOI_GPIOI_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOI_GPIOI_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOI_GPIOI_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOI_GPIOI_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOI_GPIOI_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOI_GPIOI_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOI_GPIOI_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOI_GPIOI_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOI_GPIOI_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOI_GPIOI_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOI_GPIOI_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOI_GPIOI_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOI_GPIOI_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOI_GPIOI_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOI_GPIOI_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOI_GPIOI_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOI_GPIOI_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOI_GPIOI_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOI_GPIOI_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOI_GPIOI_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOI_GPIOI_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOI_GPIOI_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOI_GPIOI_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOI_GPIOI_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOI_GPIOI_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOI_GPIOI_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOI_GPIOI_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOI_GPIOI_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOI_GPIOI_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOI_GPIOI_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOI_GPIOI_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOI_GPIOI_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOI_GPIOI_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOI_GPIOI_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOI_GPIOI_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOI_GPIOI_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOI_GPIOI_OTYPER_OT15 = 0x8000

	// GPIOI_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOI_GPIOI_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOI_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOI_GPIOI_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOI_GPIOI_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOI_GPIOI_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOI_GPIOI_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOI_GPIOI_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOI_GPIOI_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOI_GPIOI_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOI_GPIOI_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOI_GPIOI_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOI_GPIOI_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOI_GPIOI_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOI_GPIOI_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOI_GPIOI_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOI_GPIOI_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOI_GPIOI_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOI_GPIOI_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOI_GPIOI_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOI_GPIOI_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOI_GPIOI_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOI_GPIOI_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOI_GPIOI_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOI_GPIOI_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOI_GPIOI_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOI_GPIOI_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOI_GPIOI_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOI_GPIOI_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOI_GPIOI_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOI_GPIOI_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOI_GPIOI_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOI_GPIOI_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOI_GPIOI_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOI_GPIOI_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOI_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOI_GPIOI_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOI_GPIOI_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOI_GPIOI_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOI_GPIOI_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOI_GPIOI_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOI_GPIOI_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOI_GPIOI_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOI_GPIOI_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOI_GPIOI_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOI_GPIOI_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOI_GPIOI_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOI_GPIOI_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOI_GPIOI_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOI_GPIOI_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOI_GPIOI_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOI_GPIOI_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOI_GPIOI_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOI_GPIOI_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOI_GPIOI_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOI_GPIOI_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOI_GPIOI_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOI_GPIOI_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOI_GPIOI_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOI_GPIOI_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOI_GPIOI_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOI_GPIOI_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOI_GPIOI_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOI_GPIOI_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOI_GPIOI_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOI_GPIOI_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOI_GPIOI_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOI_GPIOI_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOI_GPIOI_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOI_GPIOI_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOI_GPIOI_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOI_GPIOI_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOI_GPIOI_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOI_GPIOI_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOI_GPIOI_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOI_GPIOI_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOI_GPIOI_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOI_GPIOI_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOI_GPIOI_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOI_GPIOI_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOI_GPIOI_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOI_GPIOI_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOI_GPIOI_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOI_GPIOI_IDR_IDR15 = 0x8000

	// GPIOI_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOI_GPIOI_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOI_GPIOI_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOI_GPIOI_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOI_GPIOI_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOI_GPIOI_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOI_GPIOI_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOI_GPIOI_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOI_GPIOI_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOI_GPIOI_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOI_GPIOI_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOI_GPIOI_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOI_GPIOI_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOI_GPIOI_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOI_GPIOI_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOI_GPIOI_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOI_GPIOI_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOI_GPIOI_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOI_GPIOI_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOI_GPIOI_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOI_GPIOI_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOI_GPIOI_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOI_GPIOI_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOI_GPIOI_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOI_GPIOI_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOI_GPIOI_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOI_GPIOI_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOI_GPIOI_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOI_GPIOI_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOI_GPIOI_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOI_GPIOI_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOI_GPIOI_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOI_GPIOI_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOI_GPIOI_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOI_GPIOI_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOI_GPIOI_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOI_GPIOI_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOI_GPIOI_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOI_GPIOI_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOI_GPIOI_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOI_GPIOI_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOI_GPIOI_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOI_GPIOI_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOI_GPIOI_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOI_GPIOI_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOI_GPIOI_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOI_GPIOI_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOI_GPIOI_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOI_GPIOI_ODR_ODR15 = 0x8000

	// GPIOI_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOI_GPIOI_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOI_GPIOI_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOI_GPIOI_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOI_GPIOI_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOI_GPIOI_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOI_GPIOI_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOI_GPIOI_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOI_GPIOI_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOI_GPIOI_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOI_GPIOI_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOI_GPIOI_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOI_GPIOI_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOI_GPIOI_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOI_GPIOI_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOI_GPIOI_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOI_GPIOI_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOI_GPIOI_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOI_GPIOI_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOI_GPIOI_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOI_GPIOI_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOI_GPIOI_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOI_GPIOI_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOI_GPIOI_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOI_GPIOI_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOI_GPIOI_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOI_GPIOI_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOI_GPIOI_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOI_GPIOI_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOI_GPIOI_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOI_GPIOI_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOI_GPIOI_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOI_GPIOI_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOI_GPIOI_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOI_GPIOI_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOI_GPIOI_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOI_GPIOI_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOI_GPIOI_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOI_GPIOI_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOI_GPIOI_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOI_GPIOI_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOI_GPIOI_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOI_GPIOI_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOI_GPIOI_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOI_GPIOI_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOI_GPIOI_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOI_GPIOI_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOI_GPIOI_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOI_GPIOI_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOI_GPIOI_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOI_GPIOI_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOI_GPIOI_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOI_GPIOI_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOI_GPIOI_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOI_GPIOI_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOI_GPIOI_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOI_GPIOI_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOI_GPIOI_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOI_GPIOI_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOI_GPIOI_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOI_GPIOI_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOI_GPIOI_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOI_GPIOI_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOI_GPIOI_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOI_GPIOI_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOI_GPIOI_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOI_GPIOI_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOI_GPIOI_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOI_GPIOI_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOI_GPIOI_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOI_GPIOI_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOI_GPIOI_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOI_GPIOI_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOI_GPIOI_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOI_GPIOI_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOI_GPIOI_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOI_GPIOI_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOI_GPIOI_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOI_GPIOI_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOI_GPIOI_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOI_GPIOI_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOI_GPIOI_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOI_GPIOI_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOI_GPIOI_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOI_GPIOI_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOI_GPIOI_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOI_GPIOI_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOI_GPIOI_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOI_GPIOI_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOI_GPIOI_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOI_GPIOI_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOI_GPIOI_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOI_GPIOI_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOI_GPIOI_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOI_GPIOI_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOI_GPIOI_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOI_GPIOI_BSRR_BR15 = 0x80000000

	// GPIOI_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOI_GPIOI_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOI_GPIOI_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOI_GPIOI_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOI_GPIOI_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOI_GPIOI_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOI_GPIOI_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOI_GPIOI_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOI_GPIOI_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOI_GPIOI_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOI_GPIOI_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOI_GPIOI_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOI_GPIOI_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOI_GPIOI_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOI_GPIOI_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOI_GPIOI_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOI_GPIOI_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOI_GPIOI_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOI_GPIOI_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOI_GPIOI_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOI_GPIOI_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOI_GPIOI_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOI_GPIOI_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOI_GPIOI_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOI_GPIOI_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOI_GPIOI_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOI_GPIOI_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOI_GPIOI_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOI_GPIOI_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOI_GPIOI_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOI_GPIOI_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOI_GPIOI_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOI_GPIOI_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOI_GPIOI_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOI_GPIOI_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOI_GPIOI_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOI_GPIOI_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOI_GPIOI_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOI_GPIOI_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOI_GPIOI_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOI_GPIOI_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOI_GPIOI_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOI_GPIOI_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOI_GPIOI_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOI_GPIOI_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOI_GPIOI_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOI_GPIOI_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOI_GPIOI_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOI_GPIOI_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOI_GPIOI_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOI_GPIOI_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOI_GPIOI_LCKR_LCKK = 0x10000

	// GPIOI_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOI_GPIOI_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOI_GPIOI_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOI_GPIOI_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOI_GPIOI_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOI_GPIOI_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOI_GPIOI_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOI_GPIOI_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOI_GPIOI_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOI_GPIOI_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOI_GPIOI_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOI_GPIOI_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOI_GPIOI_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOI_GPIOI_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOI_GPIOI_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOI_GPIOI_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOI_GPIOI_AFRL_AFR7_Msk = 0xf0000000

	// GPIOI_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOI_GPIOI_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOI_GPIOI_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOI_GPIOI_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOI_GPIOI_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOI_GPIOI_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOI_GPIOI_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOI_GPIOI_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOI_GPIOI_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOI_GPIOI_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOI_GPIOI_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOI_GPIOI_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOI_GPIOI_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOI_GPIOI_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOI_GPIOI_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOI_GPIOI_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOI_GPIOI_AFRH_AFR15_Msk = 0xf0000000

	// GPIOI_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOI_GPIOI_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOI_GPIOI_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOI_GPIOI_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOI_GPIOI_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOI_GPIOI_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOI_GPIOI_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOI_GPIOI_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOI_GPIOI_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOI_GPIOI_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOI_GPIOI_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOI_GPIOI_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOI_GPIOI_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOI_GPIOI_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOI_GPIOI_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOI_GPIOI_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOI_GPIOI_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOI_GPIOI_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOI_GPIOI_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOI_GPIOI_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOI_GPIOI_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOI_GPIOI_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOI_GPIOI_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOI_GPIOI_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOI_GPIOI_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOI_GPIOI_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOI_GPIOI_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOI_GPIOI_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOI_GPIOI_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOI_GPIOI_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOI_GPIOI_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOI_GPIOI_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOI_GPIOI_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOI_GPIOI_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOI_GPIOI_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOI_GPIOI_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOI_GPIOI_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOI_GPIOI_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOI_GPIOI_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOI_GPIOI_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOI_GPIOI_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOI_GPIOI_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOI_GPIOI_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOI_GPIOI_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOI_GPIOI_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOI_GPIOI_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOI_GPIOI_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOI_GPIOI_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOI_GPIOI_BRR_BR15 = 0x8000

	// GPIOI_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOI_GPIOI_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOI_GPIOI_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOI_GPIOI_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOI_GPIOI_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOI_GPIOI_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOI_GPIOI_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOI_GPIOI_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOI_GPIOI_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOI_GPIOI_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOI_GPIOI_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOI_GPIOI_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOI_GPIOI_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOI_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOI_GPIOI_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOI_GPIOI_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOI_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOI_GPIOI_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOI_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOI_GPIOI_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOI_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOI_GPIOI_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOI_GPIOI_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOI_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOI_GPIOI_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOI_GPIOI_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOI_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOI_GPIOI_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOI_GPIOI_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOI_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOI_GPIOI_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOI_GPIOI_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOI_GPIOI_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOI_GPIOI_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOI_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOI_GPIOI_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOI_GPIOI_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOI_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOI_GPIOI_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOI_GPIOI_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOI_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOI_GPIOI_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOI_GPIOI_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOI_VERR: GPIO version register
	// Position of MINREV field.
	GPIOI_GPIOI_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOI_GPIOI_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOI_GPIOI_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOI_GPIOI_VERR_MAJREV_Msk = 0xf0

	// GPIOI_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOI_GPIOI_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOI_GPIOI_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOI_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOI_GPIOI_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOI_GPIOI_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOJ: GPIOJ
const (
	// GPIOJ_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOJ_GPIOJ_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOJ_GPIOJ_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOJ_GPIOJ_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOJ_GPIOJ_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOJ_GPIOJ_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOJ_GPIOJ_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOJ_GPIOJ_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOJ_GPIOJ_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOJ_GPIOJ_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOJ_GPIOJ_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOJ_GPIOJ_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOJ_GPIOJ_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOJ_GPIOJ_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOJ_GPIOJ_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOJ_GPIOJ_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOJ_GPIOJ_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOJ_GPIOJ_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOJ_GPIOJ_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOJ_GPIOJ_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOJ_GPIOJ_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOJ_GPIOJ_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOJ_GPIOJ_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOJ_GPIOJ_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOJ_GPIOJ_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOJ_GPIOJ_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOJ_GPIOJ_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOJ_GPIOJ_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOJ_GPIOJ_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOJ_GPIOJ_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOJ_GPIOJ_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOJ_GPIOJ_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOJ_GPIOJ_MODER_MODER15_Msk = 0xc0000000

	// GPIOJ_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOJ_GPIOJ_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOJ_GPIOJ_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOJ_GPIOJ_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOJ_GPIOJ_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOJ_GPIOJ_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOJ_GPIOJ_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOJ_GPIOJ_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOJ_GPIOJ_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOJ_GPIOJ_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOJ_GPIOJ_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOJ_GPIOJ_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOJ_GPIOJ_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOJ_GPIOJ_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOJ_GPIOJ_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOJ_GPIOJ_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOJ_GPIOJ_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOJ_GPIOJ_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOJ_GPIOJ_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOJ_GPIOJ_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOJ_GPIOJ_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOJ_GPIOJ_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOJ_GPIOJ_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOJ_GPIOJ_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOJ_GPIOJ_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOJ_GPIOJ_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOJ_GPIOJ_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOJ_GPIOJ_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOJ_GPIOJ_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOJ_GPIOJ_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOJ_GPIOJ_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOJ_GPIOJ_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOJ_GPIOJ_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOJ_GPIOJ_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOJ_GPIOJ_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOJ_GPIOJ_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOJ_GPIOJ_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOJ_GPIOJ_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOJ_GPIOJ_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOJ_GPIOJ_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOJ_GPIOJ_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOJ_GPIOJ_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOJ_GPIOJ_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOJ_GPIOJ_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOJ_GPIOJ_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOJ_GPIOJ_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOJ_GPIOJ_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOJ_GPIOJ_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOJ_GPIOJ_OTYPER_OT15 = 0x8000

	// GPIOJ_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOJ_GPIOJ_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOJ_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOJ_GPIOJ_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOJ_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOJ_GPIOJ_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOJ_GPIOJ_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOJ_GPIOJ_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOJ_GPIOJ_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOJ_GPIOJ_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOJ_GPIOJ_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOJ_GPIOJ_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOJ_GPIOJ_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOJ_GPIOJ_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOJ_GPIOJ_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOJ_GPIOJ_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOJ_GPIOJ_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOJ_GPIOJ_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOJ_GPIOJ_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOJ_GPIOJ_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOJ_GPIOJ_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOJ_GPIOJ_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOJ_GPIOJ_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOJ_GPIOJ_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOJ_GPIOJ_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOJ_GPIOJ_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOJ_GPIOJ_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOJ_GPIOJ_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOJ_GPIOJ_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOJ_GPIOJ_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOJ_GPIOJ_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOJ_GPIOJ_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOJ_GPIOJ_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOJ_GPIOJ_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOJ_GPIOJ_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOJ_GPIOJ_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOJ_GPIOJ_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOJ_GPIOJ_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOJ_GPIOJ_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOJ_GPIOJ_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOJ_GPIOJ_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOJ_GPIOJ_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOJ_GPIOJ_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOJ_GPIOJ_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOJ_GPIOJ_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOJ_GPIOJ_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOJ_GPIOJ_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOJ_GPIOJ_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOJ_GPIOJ_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOJ_GPIOJ_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOJ_GPIOJ_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOJ_GPIOJ_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOJ_GPIOJ_IDR_IDR15 = 0x8000

	// GPIOJ_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOJ_GPIOJ_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOJ_GPIOJ_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOJ_GPIOJ_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOJ_GPIOJ_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOJ_GPIOJ_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOJ_GPIOJ_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOJ_GPIOJ_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOJ_GPIOJ_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOJ_GPIOJ_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOJ_GPIOJ_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOJ_GPIOJ_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOJ_GPIOJ_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOJ_GPIOJ_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOJ_GPIOJ_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOJ_GPIOJ_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOJ_GPIOJ_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOJ_GPIOJ_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOJ_GPIOJ_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOJ_GPIOJ_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOJ_GPIOJ_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOJ_GPIOJ_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOJ_GPIOJ_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOJ_GPIOJ_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOJ_GPIOJ_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOJ_GPIOJ_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOJ_GPIOJ_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOJ_GPIOJ_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOJ_GPIOJ_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOJ_GPIOJ_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOJ_GPIOJ_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOJ_GPIOJ_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOJ_GPIOJ_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOJ_GPIOJ_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOJ_GPIOJ_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOJ_GPIOJ_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOJ_GPIOJ_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOJ_GPIOJ_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOJ_GPIOJ_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOJ_GPIOJ_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOJ_GPIOJ_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOJ_GPIOJ_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOJ_GPIOJ_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOJ_GPIOJ_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOJ_GPIOJ_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOJ_GPIOJ_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOJ_GPIOJ_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOJ_GPIOJ_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOJ_GPIOJ_ODR_ODR15 = 0x8000

	// GPIOJ_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOJ_GPIOJ_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOJ_GPIOJ_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOJ_GPIOJ_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOJ_GPIOJ_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOJ_GPIOJ_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOJ_GPIOJ_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOJ_GPIOJ_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOJ_GPIOJ_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOJ_GPIOJ_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOJ_GPIOJ_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOJ_GPIOJ_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOJ_GPIOJ_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOJ_GPIOJ_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOJ_GPIOJ_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOJ_GPIOJ_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOJ_GPIOJ_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOJ_GPIOJ_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOJ_GPIOJ_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOJ_GPIOJ_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOJ_GPIOJ_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOJ_GPIOJ_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOJ_GPIOJ_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOJ_GPIOJ_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOJ_GPIOJ_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOJ_GPIOJ_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOJ_GPIOJ_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOJ_GPIOJ_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOJ_GPIOJ_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOJ_GPIOJ_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOJ_GPIOJ_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOJ_GPIOJ_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOJ_GPIOJ_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOJ_GPIOJ_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOJ_GPIOJ_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOJ_GPIOJ_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOJ_GPIOJ_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOJ_GPIOJ_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOJ_GPIOJ_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOJ_GPIOJ_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOJ_GPIOJ_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOJ_GPIOJ_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOJ_GPIOJ_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOJ_GPIOJ_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOJ_GPIOJ_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOJ_GPIOJ_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOJ_GPIOJ_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOJ_GPIOJ_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOJ_GPIOJ_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOJ_GPIOJ_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOJ_GPIOJ_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOJ_GPIOJ_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOJ_GPIOJ_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOJ_GPIOJ_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOJ_GPIOJ_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOJ_GPIOJ_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOJ_GPIOJ_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOJ_GPIOJ_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOJ_GPIOJ_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOJ_GPIOJ_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOJ_GPIOJ_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOJ_GPIOJ_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOJ_GPIOJ_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOJ_GPIOJ_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOJ_GPIOJ_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOJ_GPIOJ_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOJ_GPIOJ_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOJ_GPIOJ_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOJ_GPIOJ_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOJ_GPIOJ_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOJ_GPIOJ_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOJ_GPIOJ_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOJ_GPIOJ_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOJ_GPIOJ_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOJ_GPIOJ_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOJ_GPIOJ_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOJ_GPIOJ_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOJ_GPIOJ_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOJ_GPIOJ_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOJ_GPIOJ_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOJ_GPIOJ_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOJ_GPIOJ_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOJ_GPIOJ_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOJ_GPIOJ_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOJ_GPIOJ_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOJ_GPIOJ_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOJ_GPIOJ_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOJ_GPIOJ_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOJ_GPIOJ_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOJ_GPIOJ_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOJ_GPIOJ_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOJ_GPIOJ_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOJ_GPIOJ_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOJ_GPIOJ_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOJ_GPIOJ_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOJ_GPIOJ_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOJ_GPIOJ_BSRR_BR15 = 0x80000000

	// GPIOJ_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOJ_GPIOJ_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOJ_GPIOJ_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOJ_GPIOJ_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOJ_GPIOJ_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOJ_GPIOJ_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOJ_GPIOJ_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOJ_GPIOJ_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOJ_GPIOJ_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOJ_GPIOJ_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOJ_GPIOJ_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOJ_GPIOJ_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOJ_GPIOJ_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOJ_GPIOJ_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOJ_GPIOJ_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOJ_GPIOJ_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOJ_GPIOJ_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOJ_GPIOJ_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOJ_GPIOJ_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOJ_GPIOJ_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOJ_GPIOJ_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOJ_GPIOJ_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOJ_GPIOJ_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOJ_GPIOJ_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOJ_GPIOJ_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOJ_GPIOJ_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOJ_GPIOJ_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOJ_GPIOJ_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOJ_GPIOJ_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOJ_GPIOJ_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOJ_GPIOJ_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOJ_GPIOJ_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOJ_GPIOJ_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOJ_GPIOJ_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOJ_GPIOJ_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOJ_GPIOJ_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOJ_GPIOJ_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOJ_GPIOJ_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOJ_GPIOJ_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOJ_GPIOJ_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOJ_GPIOJ_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOJ_GPIOJ_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOJ_GPIOJ_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOJ_GPIOJ_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOJ_GPIOJ_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOJ_GPIOJ_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOJ_GPIOJ_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOJ_GPIOJ_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOJ_GPIOJ_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOJ_GPIOJ_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOJ_GPIOJ_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOJ_GPIOJ_LCKR_LCKK = 0x10000

	// GPIOJ_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOJ_GPIOJ_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOJ_GPIOJ_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOJ_GPIOJ_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOJ_GPIOJ_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOJ_GPIOJ_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOJ_GPIOJ_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOJ_GPIOJ_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOJ_GPIOJ_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOJ_GPIOJ_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOJ_GPIOJ_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOJ_GPIOJ_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOJ_GPIOJ_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOJ_GPIOJ_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOJ_GPIOJ_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOJ_GPIOJ_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOJ_GPIOJ_AFRL_AFR7_Msk = 0xf0000000

	// GPIOJ_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOJ_GPIOJ_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOJ_GPIOJ_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOJ_GPIOJ_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOJ_GPIOJ_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOJ_GPIOJ_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOJ_GPIOJ_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOJ_GPIOJ_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOJ_GPIOJ_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOJ_GPIOJ_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOJ_GPIOJ_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOJ_GPIOJ_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOJ_GPIOJ_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOJ_GPIOJ_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOJ_GPIOJ_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOJ_GPIOJ_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOJ_GPIOJ_AFRH_AFR15_Msk = 0xf0000000

	// GPIOJ_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOJ_GPIOJ_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOJ_GPIOJ_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOJ_GPIOJ_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOJ_GPIOJ_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOJ_GPIOJ_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOJ_GPIOJ_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOJ_GPIOJ_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOJ_GPIOJ_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOJ_GPIOJ_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOJ_GPIOJ_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOJ_GPIOJ_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOJ_GPIOJ_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOJ_GPIOJ_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOJ_GPIOJ_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOJ_GPIOJ_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOJ_GPIOJ_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOJ_GPIOJ_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOJ_GPIOJ_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOJ_GPIOJ_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOJ_GPIOJ_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOJ_GPIOJ_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOJ_GPIOJ_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOJ_GPIOJ_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOJ_GPIOJ_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOJ_GPIOJ_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOJ_GPIOJ_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOJ_GPIOJ_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOJ_GPIOJ_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOJ_GPIOJ_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOJ_GPIOJ_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOJ_GPIOJ_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOJ_GPIOJ_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOJ_GPIOJ_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOJ_GPIOJ_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOJ_GPIOJ_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOJ_GPIOJ_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOJ_GPIOJ_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOJ_GPIOJ_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOJ_GPIOJ_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOJ_GPIOJ_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOJ_GPIOJ_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOJ_GPIOJ_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOJ_GPIOJ_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOJ_GPIOJ_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOJ_GPIOJ_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOJ_GPIOJ_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOJ_GPIOJ_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOJ_GPIOJ_BRR_BR15 = 0x8000

	// GPIOJ_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOJ_GPIOJ_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOJ_GPIOJ_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOJ_GPIOJ_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOJ_GPIOJ_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOJ_GPIOJ_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOJ_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOJ_GPIOJ_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOJ_GPIOJ_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOJ_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOJ_GPIOJ_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOJ_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOJ_GPIOJ_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOJ_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOJ_GPIOJ_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOJ_GPIOJ_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOJ_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOJ_GPIOJ_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOJ_GPIOJ_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOJ_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOJ_GPIOJ_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOJ_GPIOJ_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOJ_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOJ_GPIOJ_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOJ_GPIOJ_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOJ_GPIOJ_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOJ_GPIOJ_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOJ_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOJ_GPIOJ_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOJ_GPIOJ_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOJ_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOJ_GPIOJ_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOJ_GPIOJ_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOJ_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOJ_GPIOJ_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOJ_GPIOJ_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOJ_VERR: GPIO version register
	// Position of MINREV field.
	GPIOJ_GPIOJ_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOJ_GPIOJ_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOJ_GPIOJ_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOJ_GPIOJ_VERR_MAJREV_Msk = 0xf0

	// GPIOJ_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOJ_GPIOJ_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOJ_GPIOJ_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOJ_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOJ_GPIOJ_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOJ_GPIOJ_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOK: GPIOK
const (
	// GPIOK_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOK_GPIOK_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOK_GPIOK_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOK_GPIOK_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOK_GPIOK_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOK_GPIOK_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOK_GPIOK_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOK_GPIOK_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOK_GPIOK_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOK_GPIOK_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOK_GPIOK_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOK_GPIOK_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOK_GPIOK_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOK_GPIOK_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOK_GPIOK_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOK_GPIOK_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOK_GPIOK_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOK_GPIOK_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOK_GPIOK_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOK_GPIOK_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOK_GPIOK_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOK_GPIOK_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOK_GPIOK_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOK_GPIOK_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOK_GPIOK_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOK_GPIOK_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOK_GPIOK_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOK_GPIOK_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOK_GPIOK_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOK_GPIOK_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOK_GPIOK_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOK_GPIOK_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOK_GPIOK_MODER_MODER15_Msk = 0xc0000000

	// GPIOK_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOK_GPIOK_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOK_GPIOK_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOK_GPIOK_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOK_GPIOK_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOK_GPIOK_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOK_GPIOK_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOK_GPIOK_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOK_GPIOK_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOK_GPIOK_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOK_GPIOK_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOK_GPIOK_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOK_GPIOK_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOK_GPIOK_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOK_GPIOK_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOK_GPIOK_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOK_GPIOK_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOK_GPIOK_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOK_GPIOK_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOK_GPIOK_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOK_GPIOK_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOK_GPIOK_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOK_GPIOK_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOK_GPIOK_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOK_GPIOK_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOK_GPIOK_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOK_GPIOK_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOK_GPIOK_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOK_GPIOK_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOK_GPIOK_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOK_GPIOK_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOK_GPIOK_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOK_GPIOK_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOK_GPIOK_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOK_GPIOK_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOK_GPIOK_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOK_GPIOK_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOK_GPIOK_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOK_GPIOK_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOK_GPIOK_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOK_GPIOK_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOK_GPIOK_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOK_GPIOK_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOK_GPIOK_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOK_GPIOK_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOK_GPIOK_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOK_GPIOK_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOK_GPIOK_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOK_GPIOK_OTYPER_OT15 = 0x8000

	// GPIOK_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOK_GPIOK_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOK_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOK_GPIOK_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOK_GPIOK_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOK_GPIOK_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOK_GPIOK_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOK_GPIOK_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOK_GPIOK_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOK_GPIOK_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOK_GPIOK_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOK_GPIOK_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOK_GPIOK_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOK_GPIOK_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOK_GPIOK_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOK_GPIOK_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOK_GPIOK_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOK_GPIOK_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOK_GPIOK_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOK_GPIOK_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOK_GPIOK_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOK_GPIOK_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOK_GPIOK_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOK_GPIOK_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOK_GPIOK_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOK_GPIOK_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOK_GPIOK_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOK_GPIOK_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOK_GPIOK_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOK_GPIOK_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOK_GPIOK_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOK_GPIOK_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOK_GPIOK_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOK_GPIOK_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOK_GPIOK_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOK_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOK_GPIOK_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOK_GPIOK_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOK_GPIOK_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOK_GPIOK_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOK_GPIOK_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOK_GPIOK_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOK_GPIOK_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOK_GPIOK_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOK_GPIOK_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOK_GPIOK_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOK_GPIOK_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOK_GPIOK_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOK_GPIOK_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOK_GPIOK_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOK_GPIOK_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOK_GPIOK_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOK_GPIOK_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOK_GPIOK_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOK_GPIOK_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOK_GPIOK_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOK_GPIOK_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOK_GPIOK_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOK_GPIOK_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOK_GPIOK_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOK_GPIOK_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOK_GPIOK_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOK_GPIOK_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOK_GPIOK_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOK_GPIOK_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOK_GPIOK_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOK_GPIOK_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOK_GPIOK_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOK_GPIOK_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOK_GPIOK_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOK_GPIOK_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOK_GPIOK_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOK_GPIOK_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOK_GPIOK_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOK_GPIOK_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOK_GPIOK_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOK_GPIOK_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOK_GPIOK_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOK_GPIOK_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOK_GPIOK_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOK_GPIOK_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOK_GPIOK_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOK_GPIOK_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOK_GPIOK_IDR_IDR15 = 0x8000

	// GPIOK_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOK_GPIOK_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOK_GPIOK_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOK_GPIOK_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOK_GPIOK_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOK_GPIOK_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOK_GPIOK_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOK_GPIOK_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOK_GPIOK_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOK_GPIOK_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOK_GPIOK_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOK_GPIOK_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOK_GPIOK_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOK_GPIOK_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOK_GPIOK_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOK_GPIOK_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOK_GPIOK_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOK_GPIOK_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOK_GPIOK_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOK_GPIOK_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOK_GPIOK_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOK_GPIOK_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOK_GPIOK_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOK_GPIOK_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOK_GPIOK_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOK_GPIOK_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOK_GPIOK_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOK_GPIOK_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOK_GPIOK_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOK_GPIOK_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOK_GPIOK_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOK_GPIOK_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOK_GPIOK_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOK_GPIOK_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOK_GPIOK_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOK_GPIOK_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOK_GPIOK_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOK_GPIOK_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOK_GPIOK_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOK_GPIOK_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOK_GPIOK_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOK_GPIOK_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOK_GPIOK_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOK_GPIOK_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOK_GPIOK_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOK_GPIOK_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOK_GPIOK_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOK_GPIOK_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOK_GPIOK_ODR_ODR15 = 0x8000

	// GPIOK_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOK_GPIOK_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOK_GPIOK_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOK_GPIOK_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOK_GPIOK_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOK_GPIOK_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOK_GPIOK_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOK_GPIOK_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOK_GPIOK_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOK_GPIOK_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOK_GPIOK_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOK_GPIOK_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOK_GPIOK_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOK_GPIOK_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOK_GPIOK_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOK_GPIOK_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOK_GPIOK_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOK_GPIOK_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOK_GPIOK_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOK_GPIOK_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOK_GPIOK_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOK_GPIOK_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOK_GPIOK_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOK_GPIOK_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOK_GPIOK_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOK_GPIOK_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOK_GPIOK_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOK_GPIOK_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOK_GPIOK_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOK_GPIOK_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOK_GPIOK_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOK_GPIOK_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOK_GPIOK_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOK_GPIOK_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOK_GPIOK_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOK_GPIOK_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOK_GPIOK_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOK_GPIOK_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOK_GPIOK_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOK_GPIOK_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOK_GPIOK_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOK_GPIOK_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOK_GPIOK_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOK_GPIOK_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOK_GPIOK_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOK_GPIOK_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOK_GPIOK_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOK_GPIOK_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOK_GPIOK_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOK_GPIOK_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOK_GPIOK_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOK_GPIOK_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOK_GPIOK_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOK_GPIOK_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOK_GPIOK_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOK_GPIOK_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOK_GPIOK_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOK_GPIOK_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOK_GPIOK_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOK_GPIOK_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOK_GPIOK_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOK_GPIOK_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOK_GPIOK_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOK_GPIOK_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOK_GPIOK_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOK_GPIOK_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOK_GPIOK_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOK_GPIOK_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOK_GPIOK_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOK_GPIOK_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOK_GPIOK_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOK_GPIOK_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOK_GPIOK_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOK_GPIOK_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOK_GPIOK_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOK_GPIOK_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOK_GPIOK_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOK_GPIOK_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOK_GPIOK_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOK_GPIOK_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOK_GPIOK_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOK_GPIOK_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOK_GPIOK_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOK_GPIOK_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOK_GPIOK_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOK_GPIOK_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOK_GPIOK_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOK_GPIOK_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOK_GPIOK_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOK_GPIOK_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOK_GPIOK_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOK_GPIOK_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOK_GPIOK_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOK_GPIOK_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOK_GPIOK_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOK_GPIOK_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOK_GPIOK_BSRR_BR15 = 0x80000000

	// GPIOK_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOK_GPIOK_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOK_GPIOK_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOK_GPIOK_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOK_GPIOK_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOK_GPIOK_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOK_GPIOK_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOK_GPIOK_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOK_GPIOK_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOK_GPIOK_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOK_GPIOK_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOK_GPIOK_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOK_GPIOK_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOK_GPIOK_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOK_GPIOK_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOK_GPIOK_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOK_GPIOK_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOK_GPIOK_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOK_GPIOK_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOK_GPIOK_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOK_GPIOK_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOK_GPIOK_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOK_GPIOK_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOK_GPIOK_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOK_GPIOK_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOK_GPIOK_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOK_GPIOK_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOK_GPIOK_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOK_GPIOK_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOK_GPIOK_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOK_GPIOK_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOK_GPIOK_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOK_GPIOK_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOK_GPIOK_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOK_GPIOK_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOK_GPIOK_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOK_GPIOK_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOK_GPIOK_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOK_GPIOK_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOK_GPIOK_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOK_GPIOK_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOK_GPIOK_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOK_GPIOK_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOK_GPIOK_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOK_GPIOK_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOK_GPIOK_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOK_GPIOK_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOK_GPIOK_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOK_GPIOK_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOK_GPIOK_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOK_GPIOK_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOK_GPIOK_LCKR_LCKK = 0x10000

	// GPIOK_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOK_GPIOK_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOK_GPIOK_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOK_GPIOK_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOK_GPIOK_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOK_GPIOK_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOK_GPIOK_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOK_GPIOK_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOK_GPIOK_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOK_GPIOK_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOK_GPIOK_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOK_GPIOK_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOK_GPIOK_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOK_GPIOK_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOK_GPIOK_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOK_GPIOK_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOK_GPIOK_AFRL_AFR7_Msk = 0xf0000000

	// GPIOK_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOK_GPIOK_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOK_GPIOK_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOK_GPIOK_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOK_GPIOK_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOK_GPIOK_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOK_GPIOK_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOK_GPIOK_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOK_GPIOK_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOK_GPIOK_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOK_GPIOK_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOK_GPIOK_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOK_GPIOK_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOK_GPIOK_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOK_GPIOK_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOK_GPIOK_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOK_GPIOK_AFRH_AFR15_Msk = 0xf0000000

	// GPIOK_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOK_GPIOK_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOK_GPIOK_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOK_GPIOK_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOK_GPIOK_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOK_GPIOK_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOK_GPIOK_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOK_GPIOK_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOK_GPIOK_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOK_GPIOK_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOK_GPIOK_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOK_GPIOK_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOK_GPIOK_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOK_GPIOK_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOK_GPIOK_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOK_GPIOK_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOK_GPIOK_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOK_GPIOK_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOK_GPIOK_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOK_GPIOK_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOK_GPIOK_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOK_GPIOK_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOK_GPIOK_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOK_GPIOK_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOK_GPIOK_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOK_GPIOK_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOK_GPIOK_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOK_GPIOK_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOK_GPIOK_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOK_GPIOK_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOK_GPIOK_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOK_GPIOK_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOK_GPIOK_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOK_GPIOK_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOK_GPIOK_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOK_GPIOK_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOK_GPIOK_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOK_GPIOK_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOK_GPIOK_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOK_GPIOK_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOK_GPIOK_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOK_GPIOK_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOK_GPIOK_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOK_GPIOK_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOK_GPIOK_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOK_GPIOK_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOK_GPIOK_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOK_GPIOK_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOK_GPIOK_BRR_BR15 = 0x8000

	// GPIOK_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOK_GPIOK_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOK_GPIOK_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOK_GPIOK_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOK_GPIOK_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOK_GPIOK_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOK_GPIOK_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOK_GPIOK_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOK_GPIOK_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOK_GPIOK_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOK_GPIOK_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOK_GPIOK_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOK_GPIOK_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOK_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOK_GPIOK_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOK_GPIOK_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOK_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOK_GPIOK_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOK_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOK_GPIOK_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOK_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOK_GPIOK_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOK_GPIOK_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOK_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOK_GPIOK_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOK_GPIOK_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOK_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOK_GPIOK_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOK_GPIOK_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOK_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOK_GPIOK_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOK_GPIOK_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOK_GPIOK_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOK_GPIOK_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOK_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOK_GPIOK_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOK_GPIOK_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOK_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOK_GPIOK_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOK_GPIOK_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOK_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOK_GPIOK_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOK_GPIOK_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOK_VERR: GPIO version register
	// Position of MINREV field.
	GPIOK_GPIOK_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOK_GPIOK_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOK_GPIOK_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOK_GPIOK_VERR_MAJREV_Msk = 0xf0

	// GPIOK_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOK_GPIOK_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOK_GPIOK_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOK_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOK_GPIOK_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOK_GPIOK_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for GPIOZ: GPIOZ
const (
	// GPIOZ_MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIOZ_GPIOZ_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIOZ_GPIOZ_MODER_MODER0_Msk = 0x3
	// Position of MODER1 field.
	GPIOZ_GPIOZ_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIOZ_GPIOZ_MODER_MODER1_Msk = 0xc
	// Position of MODER2 field.
	GPIOZ_GPIOZ_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIOZ_GPIOZ_MODER_MODER2_Msk = 0x30
	// Position of MODER3 field.
	GPIOZ_GPIOZ_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIOZ_GPIOZ_MODER_MODER3_Msk = 0xc0
	// Position of MODER4 field.
	GPIOZ_GPIOZ_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIOZ_GPIOZ_MODER_MODER4_Msk = 0x300
	// Position of MODER5 field.
	GPIOZ_GPIOZ_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIOZ_GPIOZ_MODER_MODER5_Msk = 0xc00
	// Position of MODER6 field.
	GPIOZ_GPIOZ_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIOZ_GPIOZ_MODER_MODER6_Msk = 0x3000
	// Position of MODER7 field.
	GPIOZ_GPIOZ_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIOZ_GPIOZ_MODER_MODER7_Msk = 0xc000
	// Position of MODER8 field.
	GPIOZ_GPIOZ_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIOZ_GPIOZ_MODER_MODER8_Msk = 0x30000
	// Position of MODER9 field.
	GPIOZ_GPIOZ_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIOZ_GPIOZ_MODER_MODER9_Msk = 0xc0000
	// Position of MODER10 field.
	GPIOZ_GPIOZ_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIOZ_GPIOZ_MODER_MODER10_Msk = 0x300000
	// Position of MODER11 field.
	GPIOZ_GPIOZ_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIOZ_GPIOZ_MODER_MODER11_Msk = 0xc00000
	// Position of MODER12 field.
	GPIOZ_GPIOZ_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIOZ_GPIOZ_MODER_MODER12_Msk = 0x3000000
	// Position of MODER13 field.
	GPIOZ_GPIOZ_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIOZ_GPIOZ_MODER_MODER13_Msk = 0xc000000
	// Position of MODER14 field.
	GPIOZ_GPIOZ_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIOZ_GPIOZ_MODER_MODER14_Msk = 0x30000000
	// Position of MODER15 field.
	GPIOZ_GPIOZ_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIOZ_GPIOZ_MODER_MODER15_Msk = 0xc0000000

	// GPIOZ_OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIOZ_GPIOZ_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIOZ_GPIOZ_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIOZ_GPIOZ_OTYPER_OT0 = 0x1
	// Position of OT1 field.
	GPIOZ_GPIOZ_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIOZ_GPIOZ_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIOZ_GPIOZ_OTYPER_OT1 = 0x2
	// Position of OT2 field.
	GPIOZ_GPIOZ_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIOZ_GPIOZ_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIOZ_GPIOZ_OTYPER_OT2 = 0x4
	// Position of OT3 field.
	GPIOZ_GPIOZ_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIOZ_GPIOZ_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIOZ_GPIOZ_OTYPER_OT3 = 0x8
	// Position of OT4 field.
	GPIOZ_GPIOZ_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIOZ_GPIOZ_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIOZ_GPIOZ_OTYPER_OT4 = 0x10
	// Position of OT5 field.
	GPIOZ_GPIOZ_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIOZ_GPIOZ_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIOZ_GPIOZ_OTYPER_OT5 = 0x20
	// Position of OT6 field.
	GPIOZ_GPIOZ_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIOZ_GPIOZ_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIOZ_GPIOZ_OTYPER_OT6 = 0x40
	// Position of OT7 field.
	GPIOZ_GPIOZ_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIOZ_GPIOZ_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIOZ_GPIOZ_OTYPER_OT7 = 0x80
	// Position of OT8 field.
	GPIOZ_GPIOZ_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIOZ_GPIOZ_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIOZ_GPIOZ_OTYPER_OT8 = 0x100
	// Position of OT9 field.
	GPIOZ_GPIOZ_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIOZ_GPIOZ_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIOZ_GPIOZ_OTYPER_OT9 = 0x200
	// Position of OT10 field.
	GPIOZ_GPIOZ_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIOZ_GPIOZ_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIOZ_GPIOZ_OTYPER_OT10 = 0x400
	// Position of OT11 field.
	GPIOZ_GPIOZ_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIOZ_GPIOZ_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIOZ_GPIOZ_OTYPER_OT11 = 0x800
	// Position of OT12 field.
	GPIOZ_GPIOZ_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIOZ_GPIOZ_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIOZ_GPIOZ_OTYPER_OT12 = 0x1000
	// Position of OT13 field.
	GPIOZ_GPIOZ_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIOZ_GPIOZ_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIOZ_GPIOZ_OTYPER_OT13 = 0x2000
	// Position of OT14 field.
	GPIOZ_GPIOZ_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIOZ_GPIOZ_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIOZ_GPIOZ_OTYPER_OT14 = 0x4000
	// Position of OT15 field.
	GPIOZ_GPIOZ_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIOZ_GPIOZ_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIOZ_GPIOZ_OTYPER_OT15 = 0x8000

	// GPIOZ_OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Position of OSPEEDR1 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Position of OSPEEDR2 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Position of OSPEEDR3 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Position of OSPEEDR4 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Position of OSPEEDR5 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Position of OSPEEDR6 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Position of OSPEEDR7 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Position of OSPEEDR8 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Position of OSPEEDR9 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Position of OSPEEDR10 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Position of OSPEEDR11 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Position of OSPEEDR12 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Position of OSPEEDR13 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Position of OSPEEDR14 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Position of OSPEEDR15 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIOZ_GPIOZ_OSPEEDR_OSPEEDR15_Msk = 0xc0000000

	// GPIOZ_PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR0_Msk = 0x3
	// Position of PUPDR1 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR1_Msk = 0xc
	// Position of PUPDR2 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR2_Msk = 0x30
	// Position of PUPDR3 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR3_Msk = 0xc0
	// Position of PUPDR4 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR4_Msk = 0x300
	// Position of PUPDR5 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR5_Msk = 0xc00
	// Position of PUPDR6 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR6_Msk = 0x3000
	// Position of PUPDR7 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR7_Msk = 0xc000
	// Position of PUPDR8 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR8_Msk = 0x30000
	// Position of PUPDR9 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR9_Msk = 0xc0000
	// Position of PUPDR10 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR10_Msk = 0x300000
	// Position of PUPDR11 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR11_Msk = 0xc00000
	// Position of PUPDR12 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR12_Msk = 0x3000000
	// Position of PUPDR13 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR13_Msk = 0xc000000
	// Position of PUPDR14 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR14_Msk = 0x30000000
	// Position of PUPDR15 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIOZ_GPIOZ_PUPDR_PUPDR15_Msk = 0xc0000000

	// GPIOZ_IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIOZ_GPIOZ_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIOZ_GPIOZ_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIOZ_GPIOZ_IDR_IDR0 = 0x1
	// Position of IDR1 field.
	GPIOZ_GPIOZ_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIOZ_GPIOZ_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIOZ_GPIOZ_IDR_IDR1 = 0x2
	// Position of IDR2 field.
	GPIOZ_GPIOZ_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIOZ_GPIOZ_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIOZ_GPIOZ_IDR_IDR2 = 0x4
	// Position of IDR3 field.
	GPIOZ_GPIOZ_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIOZ_GPIOZ_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIOZ_GPIOZ_IDR_IDR3 = 0x8
	// Position of IDR4 field.
	GPIOZ_GPIOZ_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIOZ_GPIOZ_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIOZ_GPIOZ_IDR_IDR4 = 0x10
	// Position of IDR5 field.
	GPIOZ_GPIOZ_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIOZ_GPIOZ_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIOZ_GPIOZ_IDR_IDR5 = 0x20
	// Position of IDR6 field.
	GPIOZ_GPIOZ_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIOZ_GPIOZ_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIOZ_GPIOZ_IDR_IDR6 = 0x40
	// Position of IDR7 field.
	GPIOZ_GPIOZ_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIOZ_GPIOZ_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIOZ_GPIOZ_IDR_IDR7 = 0x80
	// Position of IDR8 field.
	GPIOZ_GPIOZ_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIOZ_GPIOZ_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIOZ_GPIOZ_IDR_IDR8 = 0x100
	// Position of IDR9 field.
	GPIOZ_GPIOZ_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIOZ_GPIOZ_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIOZ_GPIOZ_IDR_IDR9 = 0x200
	// Position of IDR10 field.
	GPIOZ_GPIOZ_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIOZ_GPIOZ_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIOZ_GPIOZ_IDR_IDR10 = 0x400
	// Position of IDR11 field.
	GPIOZ_GPIOZ_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIOZ_GPIOZ_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIOZ_GPIOZ_IDR_IDR11 = 0x800
	// Position of IDR12 field.
	GPIOZ_GPIOZ_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIOZ_GPIOZ_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIOZ_GPIOZ_IDR_IDR12 = 0x1000
	// Position of IDR13 field.
	GPIOZ_GPIOZ_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIOZ_GPIOZ_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIOZ_GPIOZ_IDR_IDR13 = 0x2000
	// Position of IDR14 field.
	GPIOZ_GPIOZ_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIOZ_GPIOZ_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIOZ_GPIOZ_IDR_IDR14 = 0x4000
	// Position of IDR15 field.
	GPIOZ_GPIOZ_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIOZ_GPIOZ_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIOZ_GPIOZ_IDR_IDR15 = 0x8000

	// GPIOZ_ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIOZ_GPIOZ_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIOZ_GPIOZ_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIOZ_GPIOZ_ODR_ODR0 = 0x1
	// Position of ODR1 field.
	GPIOZ_GPIOZ_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIOZ_GPIOZ_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIOZ_GPIOZ_ODR_ODR1 = 0x2
	// Position of ODR2 field.
	GPIOZ_GPIOZ_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIOZ_GPIOZ_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIOZ_GPIOZ_ODR_ODR2 = 0x4
	// Position of ODR3 field.
	GPIOZ_GPIOZ_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIOZ_GPIOZ_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIOZ_GPIOZ_ODR_ODR3 = 0x8
	// Position of ODR4 field.
	GPIOZ_GPIOZ_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIOZ_GPIOZ_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIOZ_GPIOZ_ODR_ODR4 = 0x10
	// Position of ODR5 field.
	GPIOZ_GPIOZ_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIOZ_GPIOZ_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIOZ_GPIOZ_ODR_ODR5 = 0x20
	// Position of ODR6 field.
	GPIOZ_GPIOZ_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIOZ_GPIOZ_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIOZ_GPIOZ_ODR_ODR6 = 0x40
	// Position of ODR7 field.
	GPIOZ_GPIOZ_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIOZ_GPIOZ_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIOZ_GPIOZ_ODR_ODR7 = 0x80
	// Position of ODR8 field.
	GPIOZ_GPIOZ_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIOZ_GPIOZ_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIOZ_GPIOZ_ODR_ODR8 = 0x100
	// Position of ODR9 field.
	GPIOZ_GPIOZ_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIOZ_GPIOZ_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIOZ_GPIOZ_ODR_ODR9 = 0x200
	// Position of ODR10 field.
	GPIOZ_GPIOZ_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIOZ_GPIOZ_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIOZ_GPIOZ_ODR_ODR10 = 0x400
	// Position of ODR11 field.
	GPIOZ_GPIOZ_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIOZ_GPIOZ_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIOZ_GPIOZ_ODR_ODR11 = 0x800
	// Position of ODR12 field.
	GPIOZ_GPIOZ_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIOZ_GPIOZ_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIOZ_GPIOZ_ODR_ODR12 = 0x1000
	// Position of ODR13 field.
	GPIOZ_GPIOZ_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIOZ_GPIOZ_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIOZ_GPIOZ_ODR_ODR13 = 0x2000
	// Position of ODR14 field.
	GPIOZ_GPIOZ_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIOZ_GPIOZ_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIOZ_GPIOZ_ODR_ODR14 = 0x4000
	// Position of ODR15 field.
	GPIOZ_GPIOZ_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIOZ_GPIOZ_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIOZ_GPIOZ_ODR_ODR15 = 0x8000

	// GPIOZ_BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIOZ_GPIOZ_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIOZ_GPIOZ_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIOZ_GPIOZ_BSRR_BS0 = 0x1
	// Position of BS1 field.
	GPIOZ_GPIOZ_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIOZ_GPIOZ_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIOZ_GPIOZ_BSRR_BS1 = 0x2
	// Position of BS2 field.
	GPIOZ_GPIOZ_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIOZ_GPIOZ_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIOZ_GPIOZ_BSRR_BS2 = 0x4
	// Position of BS3 field.
	GPIOZ_GPIOZ_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIOZ_GPIOZ_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIOZ_GPIOZ_BSRR_BS3 = 0x8
	// Position of BS4 field.
	GPIOZ_GPIOZ_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIOZ_GPIOZ_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIOZ_GPIOZ_BSRR_BS4 = 0x10
	// Position of BS5 field.
	GPIOZ_GPIOZ_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIOZ_GPIOZ_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIOZ_GPIOZ_BSRR_BS5 = 0x20
	// Position of BS6 field.
	GPIOZ_GPIOZ_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIOZ_GPIOZ_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIOZ_GPIOZ_BSRR_BS6 = 0x40
	// Position of BS7 field.
	GPIOZ_GPIOZ_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIOZ_GPIOZ_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIOZ_GPIOZ_BSRR_BS7 = 0x80
	// Position of BS8 field.
	GPIOZ_GPIOZ_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIOZ_GPIOZ_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIOZ_GPIOZ_BSRR_BS8 = 0x100
	// Position of BS9 field.
	GPIOZ_GPIOZ_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIOZ_GPIOZ_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIOZ_GPIOZ_BSRR_BS9 = 0x200
	// Position of BS10 field.
	GPIOZ_GPIOZ_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIOZ_GPIOZ_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIOZ_GPIOZ_BSRR_BS10 = 0x400
	// Position of BS11 field.
	GPIOZ_GPIOZ_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIOZ_GPIOZ_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIOZ_GPIOZ_BSRR_BS11 = 0x800
	// Position of BS12 field.
	GPIOZ_GPIOZ_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIOZ_GPIOZ_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIOZ_GPIOZ_BSRR_BS12 = 0x1000
	// Position of BS13 field.
	GPIOZ_GPIOZ_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIOZ_GPIOZ_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIOZ_GPIOZ_BSRR_BS13 = 0x2000
	// Position of BS14 field.
	GPIOZ_GPIOZ_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIOZ_GPIOZ_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIOZ_GPIOZ_BSRR_BS14 = 0x4000
	// Position of BS15 field.
	GPIOZ_GPIOZ_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIOZ_GPIOZ_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIOZ_GPIOZ_BSRR_BS15 = 0x8000
	// Position of BR0 field.
	GPIOZ_GPIOZ_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIOZ_GPIOZ_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIOZ_GPIOZ_BSRR_BR0 = 0x10000
	// Position of BR1 field.
	GPIOZ_GPIOZ_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIOZ_GPIOZ_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIOZ_GPIOZ_BSRR_BR1 = 0x20000
	// Position of BR2 field.
	GPIOZ_GPIOZ_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIOZ_GPIOZ_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIOZ_GPIOZ_BSRR_BR2 = 0x40000
	// Position of BR3 field.
	GPIOZ_GPIOZ_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIOZ_GPIOZ_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIOZ_GPIOZ_BSRR_BR3 = 0x80000
	// Position of BR4 field.
	GPIOZ_GPIOZ_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIOZ_GPIOZ_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIOZ_GPIOZ_BSRR_BR4 = 0x100000
	// Position of BR5 field.
	GPIOZ_GPIOZ_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIOZ_GPIOZ_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIOZ_GPIOZ_BSRR_BR5 = 0x200000
	// Position of BR6 field.
	GPIOZ_GPIOZ_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIOZ_GPIOZ_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIOZ_GPIOZ_BSRR_BR6 = 0x400000
	// Position of BR7 field.
	GPIOZ_GPIOZ_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIOZ_GPIOZ_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIOZ_GPIOZ_BSRR_BR7 = 0x800000
	// Position of BR8 field.
	GPIOZ_GPIOZ_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIOZ_GPIOZ_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIOZ_GPIOZ_BSRR_BR8 = 0x1000000
	// Position of BR9 field.
	GPIOZ_GPIOZ_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIOZ_GPIOZ_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIOZ_GPIOZ_BSRR_BR9 = 0x2000000
	// Position of BR10 field.
	GPIOZ_GPIOZ_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIOZ_GPIOZ_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIOZ_GPIOZ_BSRR_BR10 = 0x4000000
	// Position of BR11 field.
	GPIOZ_GPIOZ_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIOZ_GPIOZ_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIOZ_GPIOZ_BSRR_BR11 = 0x8000000
	// Position of BR12 field.
	GPIOZ_GPIOZ_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIOZ_GPIOZ_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIOZ_GPIOZ_BSRR_BR12 = 0x10000000
	// Position of BR13 field.
	GPIOZ_GPIOZ_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIOZ_GPIOZ_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIOZ_GPIOZ_BSRR_BR13 = 0x20000000
	// Position of BR14 field.
	GPIOZ_GPIOZ_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIOZ_GPIOZ_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIOZ_GPIOZ_BSRR_BR14 = 0x40000000
	// Position of BR15 field.
	GPIOZ_GPIOZ_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIOZ_GPIOZ_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIOZ_GPIOZ_BSRR_BR15 = 0x80000000

	// GPIOZ_LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIOZ_GPIOZ_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIOZ_GPIOZ_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIOZ_GPIOZ_LCKR_LCK0 = 0x1
	// Position of LCK1 field.
	GPIOZ_GPIOZ_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIOZ_GPIOZ_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIOZ_GPIOZ_LCKR_LCK1 = 0x2
	// Position of LCK2 field.
	GPIOZ_GPIOZ_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIOZ_GPIOZ_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIOZ_GPIOZ_LCKR_LCK2 = 0x4
	// Position of LCK3 field.
	GPIOZ_GPIOZ_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIOZ_GPIOZ_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIOZ_GPIOZ_LCKR_LCK3 = 0x8
	// Position of LCK4 field.
	GPIOZ_GPIOZ_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIOZ_GPIOZ_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIOZ_GPIOZ_LCKR_LCK4 = 0x10
	// Position of LCK5 field.
	GPIOZ_GPIOZ_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIOZ_GPIOZ_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIOZ_GPIOZ_LCKR_LCK5 = 0x20
	// Position of LCK6 field.
	GPIOZ_GPIOZ_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIOZ_GPIOZ_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIOZ_GPIOZ_LCKR_LCK6 = 0x40
	// Position of LCK7 field.
	GPIOZ_GPIOZ_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIOZ_GPIOZ_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIOZ_GPIOZ_LCKR_LCK7 = 0x80
	// Position of LCK8 field.
	GPIOZ_GPIOZ_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIOZ_GPIOZ_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIOZ_GPIOZ_LCKR_LCK8 = 0x100
	// Position of LCK9 field.
	GPIOZ_GPIOZ_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIOZ_GPIOZ_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIOZ_GPIOZ_LCKR_LCK9 = 0x200
	// Position of LCK10 field.
	GPIOZ_GPIOZ_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIOZ_GPIOZ_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIOZ_GPIOZ_LCKR_LCK10 = 0x400
	// Position of LCK11 field.
	GPIOZ_GPIOZ_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIOZ_GPIOZ_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIOZ_GPIOZ_LCKR_LCK11 = 0x800
	// Position of LCK12 field.
	GPIOZ_GPIOZ_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIOZ_GPIOZ_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIOZ_GPIOZ_LCKR_LCK12 = 0x1000
	// Position of LCK13 field.
	GPIOZ_GPIOZ_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIOZ_GPIOZ_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIOZ_GPIOZ_LCKR_LCK13 = 0x2000
	// Position of LCK14 field.
	GPIOZ_GPIOZ_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIOZ_GPIOZ_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIOZ_GPIOZ_LCKR_LCK14 = 0x4000
	// Position of LCK15 field.
	GPIOZ_GPIOZ_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIOZ_GPIOZ_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIOZ_GPIOZ_LCKR_LCK15 = 0x8000
	// Position of LCKK field.
	GPIOZ_GPIOZ_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIOZ_GPIOZ_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIOZ_GPIOZ_LCKR_LCKK = 0x10000

	// GPIOZ_AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIOZ_GPIOZ_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIOZ_GPIOZ_AFRL_AFR0_Msk = 0xf
	// Position of AFR1 field.
	GPIOZ_GPIOZ_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIOZ_GPIOZ_AFRL_AFR1_Msk = 0xf0
	// Position of AFR2 field.
	GPIOZ_GPIOZ_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIOZ_GPIOZ_AFRL_AFR2_Msk = 0xf00
	// Position of AFR3 field.
	GPIOZ_GPIOZ_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIOZ_GPIOZ_AFRL_AFR3_Msk = 0xf000
	// Position of AFR4 field.
	GPIOZ_GPIOZ_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIOZ_GPIOZ_AFRL_AFR4_Msk = 0xf0000
	// Position of AFR5 field.
	GPIOZ_GPIOZ_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIOZ_GPIOZ_AFRL_AFR5_Msk = 0xf00000
	// Position of AFR6 field.
	GPIOZ_GPIOZ_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIOZ_GPIOZ_AFRL_AFR6_Msk = 0xf000000
	// Position of AFR7 field.
	GPIOZ_GPIOZ_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIOZ_GPIOZ_AFRL_AFR7_Msk = 0xf0000000

	// GPIOZ_AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIOZ_GPIOZ_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIOZ_GPIOZ_AFRH_AFR8_Msk = 0xf
	// Position of AFR9 field.
	GPIOZ_GPIOZ_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIOZ_GPIOZ_AFRH_AFR9_Msk = 0xf0
	// Position of AFR10 field.
	GPIOZ_GPIOZ_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIOZ_GPIOZ_AFRH_AFR10_Msk = 0xf00
	// Position of AFR11 field.
	GPIOZ_GPIOZ_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIOZ_GPIOZ_AFRH_AFR11_Msk = 0xf000
	// Position of AFR12 field.
	GPIOZ_GPIOZ_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIOZ_GPIOZ_AFRH_AFR12_Msk = 0xf0000
	// Position of AFR13 field.
	GPIOZ_GPIOZ_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIOZ_GPIOZ_AFRH_AFR13_Msk = 0xf00000
	// Position of AFR14 field.
	GPIOZ_GPIOZ_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIOZ_GPIOZ_AFRH_AFR14_Msk = 0xf000000
	// Position of AFR15 field.
	GPIOZ_GPIOZ_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIOZ_GPIOZ_AFRH_AFR15_Msk = 0xf0000000

	// GPIOZ_BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIOZ_GPIOZ_BRR_BR0_Pos = 0x0
	// Bit mask of BR0 field.
	GPIOZ_GPIOZ_BRR_BR0_Msk = 0x1
	// Bit BR0.
	GPIOZ_GPIOZ_BRR_BR0 = 0x1
	// Position of BR1 field.
	GPIOZ_GPIOZ_BRR_BR1_Pos = 0x1
	// Bit mask of BR1 field.
	GPIOZ_GPIOZ_BRR_BR1_Msk = 0x2
	// Bit BR1.
	GPIOZ_GPIOZ_BRR_BR1 = 0x2
	// Position of BR2 field.
	GPIOZ_GPIOZ_BRR_BR2_Pos = 0x2
	// Bit mask of BR2 field.
	GPIOZ_GPIOZ_BRR_BR2_Msk = 0x4
	// Bit BR2.
	GPIOZ_GPIOZ_BRR_BR2 = 0x4
	// Position of BR3 field.
	GPIOZ_GPIOZ_BRR_BR3_Pos = 0x3
	// Bit mask of BR3 field.
	GPIOZ_GPIOZ_BRR_BR3_Msk = 0x8
	// Bit BR3.
	GPIOZ_GPIOZ_BRR_BR3 = 0x8
	// Position of BR4 field.
	GPIOZ_GPIOZ_BRR_BR4_Pos = 0x4
	// Bit mask of BR4 field.
	GPIOZ_GPIOZ_BRR_BR4_Msk = 0x10
	// Bit BR4.
	GPIOZ_GPIOZ_BRR_BR4 = 0x10
	// Position of BR5 field.
	GPIOZ_GPIOZ_BRR_BR5_Pos = 0x5
	// Bit mask of BR5 field.
	GPIOZ_GPIOZ_BRR_BR5_Msk = 0x20
	// Bit BR5.
	GPIOZ_GPIOZ_BRR_BR5 = 0x20
	// Position of BR6 field.
	GPIOZ_GPIOZ_BRR_BR6_Pos = 0x6
	// Bit mask of BR6 field.
	GPIOZ_GPIOZ_BRR_BR6_Msk = 0x40
	// Bit BR6.
	GPIOZ_GPIOZ_BRR_BR6 = 0x40
	// Position of BR7 field.
	GPIOZ_GPIOZ_BRR_BR7_Pos = 0x7
	// Bit mask of BR7 field.
	GPIOZ_GPIOZ_BRR_BR7_Msk = 0x80
	// Bit BR7.
	GPIOZ_GPIOZ_BRR_BR7 = 0x80
	// Position of BR8 field.
	GPIOZ_GPIOZ_BRR_BR8_Pos = 0x8
	// Bit mask of BR8 field.
	GPIOZ_GPIOZ_BRR_BR8_Msk = 0x100
	// Bit BR8.
	GPIOZ_GPIOZ_BRR_BR8 = 0x100
	// Position of BR9 field.
	GPIOZ_GPIOZ_BRR_BR9_Pos = 0x9
	// Bit mask of BR9 field.
	GPIOZ_GPIOZ_BRR_BR9_Msk = 0x200
	// Bit BR9.
	GPIOZ_GPIOZ_BRR_BR9 = 0x200
	// Position of BR10 field.
	GPIOZ_GPIOZ_BRR_BR10_Pos = 0xa
	// Bit mask of BR10 field.
	GPIOZ_GPIOZ_BRR_BR10_Msk = 0x400
	// Bit BR10.
	GPIOZ_GPIOZ_BRR_BR10 = 0x400
	// Position of BR11 field.
	GPIOZ_GPIOZ_BRR_BR11_Pos = 0xb
	// Bit mask of BR11 field.
	GPIOZ_GPIOZ_BRR_BR11_Msk = 0x800
	// Bit BR11.
	GPIOZ_GPIOZ_BRR_BR11 = 0x800
	// Position of BR12 field.
	GPIOZ_GPIOZ_BRR_BR12_Pos = 0xc
	// Bit mask of BR12 field.
	GPIOZ_GPIOZ_BRR_BR12_Msk = 0x1000
	// Bit BR12.
	GPIOZ_GPIOZ_BRR_BR12 = 0x1000
	// Position of BR13 field.
	GPIOZ_GPIOZ_BRR_BR13_Pos = 0xd
	// Bit mask of BR13 field.
	GPIOZ_GPIOZ_BRR_BR13_Msk = 0x2000
	// Bit BR13.
	GPIOZ_GPIOZ_BRR_BR13 = 0x2000
	// Position of BR14 field.
	GPIOZ_GPIOZ_BRR_BR14_Pos = 0xe
	// Bit mask of BR14 field.
	GPIOZ_GPIOZ_BRR_BR14_Msk = 0x4000
	// Bit BR14.
	GPIOZ_GPIOZ_BRR_BR14 = 0x4000
	// Position of BR15 field.
	GPIOZ_GPIOZ_BRR_BR15_Pos = 0xf
	// Bit mask of BR15 field.
	GPIOZ_GPIOZ_BRR_BR15_Msk = 0x8000
	// Bit BR15.
	GPIOZ_GPIOZ_BRR_BR15 = 0x8000

	// GPIOZ_SECCFGR: This register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A non-secure write access to this register is discarded.
	// Position of SEC0 field.
	GPIOZ_GPIOZ_SECCFGR_SEC0_Pos = 0x0
	// Bit mask of SEC0 field.
	GPIOZ_GPIOZ_SECCFGR_SEC0_Msk = 0x1
	// Bit SEC0.
	GPIOZ_GPIOZ_SECCFGR_SEC0 = 0x1
	// Position of SEC1 field.
	GPIOZ_GPIOZ_SECCFGR_SEC1_Pos = 0x1
	// Bit mask of SEC1 field.
	GPIOZ_GPIOZ_SECCFGR_SEC1_Msk = 0x2
	// Bit SEC1.
	GPIOZ_GPIOZ_SECCFGR_SEC1 = 0x2
	// Position of SEC2 field.
	GPIOZ_GPIOZ_SECCFGR_SEC2_Pos = 0x2
	// Bit mask of SEC2 field.
	GPIOZ_GPIOZ_SECCFGR_SEC2_Msk = 0x4
	// Bit SEC2.
	GPIOZ_GPIOZ_SECCFGR_SEC2 = 0x4
	// Position of SEC3 field.
	GPIOZ_GPIOZ_SECCFGR_SEC3_Pos = 0x3
	// Bit mask of SEC3 field.
	GPIOZ_GPIOZ_SECCFGR_SEC3_Msk = 0x8
	// Bit SEC3.
	GPIOZ_GPIOZ_SECCFGR_SEC3 = 0x8
	// Position of SEC4 field.
	GPIOZ_GPIOZ_SECCFGR_SEC4_Pos = 0x4
	// Bit mask of SEC4 field.
	GPIOZ_GPIOZ_SECCFGR_SEC4_Msk = 0x10
	// Bit SEC4.
	GPIOZ_GPIOZ_SECCFGR_SEC4 = 0x10
	// Position of SEC5 field.
	GPIOZ_GPIOZ_SECCFGR_SEC5_Pos = 0x5
	// Bit mask of SEC5 field.
	GPIOZ_GPIOZ_SECCFGR_SEC5_Msk = 0x20
	// Bit SEC5.
	GPIOZ_GPIOZ_SECCFGR_SEC5 = 0x20
	// Position of SEC6 field.
	GPIOZ_GPIOZ_SECCFGR_SEC6_Pos = 0x6
	// Bit mask of SEC6 field.
	GPIOZ_GPIOZ_SECCFGR_SEC6_Msk = 0x40
	// Bit SEC6.
	GPIOZ_GPIOZ_SECCFGR_SEC6 = 0x40
	// Position of SEC7 field.
	GPIOZ_GPIOZ_SECCFGR_SEC7_Pos = 0x7
	// Bit mask of SEC7 field.
	GPIOZ_GPIOZ_SECCFGR_SEC7_Msk = 0x80
	// Bit SEC7.
	GPIOZ_GPIOZ_SECCFGR_SEC7 = 0x80

	// GPIOZ_HWCFGR10: For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
	// Position of AHB_IOP field.
	GPIOZ_GPIOZ_HWCFGR10_AHB_IOP_Pos = 0x0
	// Bit mask of AHB_IOP field.
	GPIOZ_GPIOZ_HWCFGR10_AHB_IOP_Msk = 0xf
	// Position of AF_SIZE field.
	GPIOZ_GPIOZ_HWCFGR10_AF_SIZE_Pos = 0x4
	// Bit mask of AF_SIZE field.
	GPIOZ_GPIOZ_HWCFGR10_AF_SIZE_Msk = 0xf0
	// Position of SPEED_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_SPEED_CFG_Pos = 0x8
	// Bit mask of SPEED_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_SPEED_CFG_Msk = 0xf00
	// Position of LOCK_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_LOCK_CFG_Pos = 0xc
	// Bit mask of LOCK_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_LOCK_CFG_Msk = 0xf000
	// Position of SEC_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_SEC_CFG_Pos = 0x10
	// Bit mask of SEC_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_SEC_CFG_Msk = 0xf0000
	// Position of OR_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_OR_CFG_Pos = 0x14
	// Bit mask of OR_CFG field.
	GPIOZ_GPIOZ_HWCFGR10_OR_CFG_Msk = 0xf00000

	// GPIOZ_HWCFGR9: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of EN_IO field.
	GPIOZ_GPIOZ_HWCFGR9_EN_IO_Pos = 0x0
	// Bit mask of EN_IO field.
	GPIOZ_GPIOZ_HWCFGR9_EN_IO_Msk = 0xffff

	// GPIOZ_HWCFGR8: For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
	// Position of AF_PRIO8 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO8_Pos = 0x0
	// Bit mask of AF_PRIO8 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO8_Msk = 0xf
	// Position of AF_PRIO9 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO9_Pos = 0x4
	// Bit mask of AF_PRIO9 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO9_Msk = 0xf0
	// Position of AF_PRIO10 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO10_Pos = 0x8
	// Bit mask of AF_PRIO10 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO10_Msk = 0xf00
	// Position of AF_PRIO11 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO11_Pos = 0xc
	// Bit mask of AF_PRIO11 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO11_Msk = 0xf000
	// Position of AF_PRIO12 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO12_Pos = 0x10
	// Bit mask of AF_PRIO12 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO12_Msk = 0xf0000
	// Position of AF_PRIO13 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO13_Pos = 0x14
	// Bit mask of AF_PRIO13 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO13_Msk = 0xf00000
	// Position of AF_PRIO14 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO14_Pos = 0x18
	// Bit mask of AF_PRIO14 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO14_Msk = 0xf000000
	// Position of AF_PRIO15 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO15_Pos = 0x1c
	// Bit mask of AF_PRIO15 field.
	GPIOZ_GPIOZ_HWCFGR8_AF_PRIO15_Msk = 0xf0000000

	// GPIOZ_HWCFGR7: GPIO hardware configuration register 7
	// Position of AF_PRIO0 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO0_Pos = 0x0
	// Bit mask of AF_PRIO0 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO0_Msk = 0xf
	// Position of AF_PRIO1 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO1_Pos = 0x4
	// Bit mask of AF_PRIO1 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO1_Msk = 0xf0
	// Position of AF_PRIO2 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO2_Pos = 0x8
	// Bit mask of AF_PRIO2 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO2_Msk = 0xf00
	// Position of AF_PRIO3 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO3_Pos = 0xc
	// Bit mask of AF_PRIO3 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO3_Msk = 0xf000
	// Position of AF_PRIO4 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO4_Pos = 0x10
	// Bit mask of AF_PRIO4 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO4_Msk = 0xf0000
	// Position of AF_PRIO5 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO5_Pos = 0x14
	// Bit mask of AF_PRIO5 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO5_Msk = 0xf00000
	// Position of AF_PRIO6 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO6_Pos = 0x18
	// Bit mask of AF_PRIO6 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO6_Msk = 0xf000000
	// Position of AF_PRIO7 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO7_Pos = 0x1c
	// Bit mask of AF_PRIO7 field.
	GPIOZ_GPIOZ_HWCFGR7_AF_PRIO7_Msk = 0xf0000000

	// GPIOZ_HWCFGR6: GPIO hardware configuration register 6
	// Position of MODER_RES field.
	GPIOZ_GPIOZ_HWCFGR6_MODER_RES_Pos = 0x0
	// Bit mask of MODER_RES field.
	GPIOZ_GPIOZ_HWCFGR6_MODER_RES_Msk = 0xffffffff

	// GPIOZ_HWCFGR5: GPIO hardware configuration register 5
	// Position of PUPDR_RES field.
	GPIOZ_GPIOZ_HWCFGR5_PUPDR_RES_Pos = 0x0
	// Bit mask of PUPDR_RES field.
	GPIOZ_GPIOZ_HWCFGR5_PUPDR_RES_Msk = 0xffffffff

	// GPIOZ_HWCFGR4: GPIO hardware configuration register 4
	// Position of OSPEED_RES field.
	GPIOZ_GPIOZ_HWCFGR4_OSPEED_RES_Pos = 0x0
	// Bit mask of OSPEED_RES field.
	GPIOZ_GPIOZ_HWCFGR4_OSPEED_RES_Msk = 0xffffffff

	// GPIOZ_HWCFGR3: GPIO hardware configuration register 3
	// Position of ODR_RES field.
	GPIOZ_GPIOZ_HWCFGR3_ODR_RES_Pos = 0x0
	// Bit mask of ODR_RES field.
	GPIOZ_GPIOZ_HWCFGR3_ODR_RES_Msk = 0xffff
	// Position of OTYPER_RES field.
	GPIOZ_GPIOZ_HWCFGR3_OTYPER_RES_Pos = 0x10
	// Bit mask of OTYPER_RES field.
	GPIOZ_GPIOZ_HWCFGR3_OTYPER_RES_Msk = 0xffff0000

	// GPIOZ_HWCFGR2: GPIO hardware configuration register 2
	// Position of AFRL_RES field.
	GPIOZ_GPIOZ_HWCFGR2_AFRL_RES_Pos = 0x0
	// Bit mask of AFRL_RES field.
	GPIOZ_GPIOZ_HWCFGR2_AFRL_RES_Msk = 0xffffffff

	// GPIOZ_HWCFGR1: GPIO hardware configuration register 1
	// Position of AFRH_RES field.
	GPIOZ_GPIOZ_HWCFGR1_AFRH_RES_Pos = 0x0
	// Bit mask of AFRH_RES field.
	GPIOZ_GPIOZ_HWCFGR1_AFRH_RES_Msk = 0xffffffff

	// GPIOZ_HWCFGR0: GPIO hardware configuration register 0
	// Position of OR_RES field.
	GPIOZ_GPIOZ_HWCFGR0_OR_RES_Pos = 0x0
	// Bit mask of OR_RES field.
	GPIOZ_GPIOZ_HWCFGR0_OR_RES_Msk = 0xffff

	// GPIOZ_VERR: GPIO version register
	// Position of MINREV field.
	GPIOZ_GPIOZ_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	GPIOZ_GPIOZ_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	GPIOZ_GPIOZ_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	GPIOZ_GPIOZ_VERR_MAJREV_Msk = 0xf0

	// GPIOZ_IPIDR: GPIO identification register
	// Position of IPIDR field.
	GPIOZ_GPIOZ_IPIDR_IPIDR_Pos = 0x0
	// Bit mask of IPIDR field.
	GPIOZ_GPIOZ_IPIDR_IPIDR_Msk = 0xffffffff

	// GPIOZ_SIDR: GPIO size identification register
	// Position of SIDR field.
	GPIOZ_GPIOZ_SIDR_SIDR_Pos = 0x0
	// Bit mask of SIDR field.
	GPIOZ_GPIOZ_SIDR_SIDR_Msk = 0xffffffff
)

// Bitfields for HASH1: HASH register block
const (
	// HASH_CR: HASH control register
	// Position of INIT field.
	HASH_HASH_CR_INIT_Pos = 0x2
	// Bit mask of INIT field.
	HASH_HASH_CR_INIT_Msk = 0x4
	// Bit INIT.
	HASH_HASH_CR_INIT = 0x4
	// Position of DMAE field.
	HASH_HASH_CR_DMAE_Pos = 0x3
	// Bit mask of DMAE field.
	HASH_HASH_CR_DMAE_Msk = 0x8
	// Bit DMAE.
	HASH_HASH_CR_DMAE = 0x8
	// Position of DATATYPE field.
	HASH_HASH_CR_DATATYPE_Pos = 0x4
	// Bit mask of DATATYPE field.
	HASH_HASH_CR_DATATYPE_Msk = 0x30
	// Position of MODE field.
	HASH_HASH_CR_MODE_Pos = 0x6
	// Bit mask of MODE field.
	HASH_HASH_CR_MODE_Msk = 0x40
	// Bit MODE.
	HASH_HASH_CR_MODE = 0x40
	// Position of ALGO0 field.
	HASH_HASH_CR_ALGO0_Pos = 0x7
	// Bit mask of ALGO0 field.
	HASH_HASH_CR_ALGO0_Msk = 0x80
	// Bit ALGO0.
	HASH_HASH_CR_ALGO0 = 0x80
	// Position of NBW field.
	HASH_HASH_CR_NBW_Pos = 0x8
	// Bit mask of NBW field.
	HASH_HASH_CR_NBW_Msk = 0xf00
	// Position of DINNE field.
	HASH_HASH_CR_DINNE_Pos = 0xc
	// Bit mask of DINNE field.
	HASH_HASH_CR_DINNE_Msk = 0x1000
	// Bit DINNE.
	HASH_HASH_CR_DINNE = 0x1000
	// Position of MDMAT field.
	HASH_HASH_CR_MDMAT_Pos = 0xd
	// Bit mask of MDMAT field.
	HASH_HASH_CR_MDMAT_Msk = 0x2000
	// Bit MDMAT.
	HASH_HASH_CR_MDMAT = 0x2000
	// Position of DMAA field.
	HASH_HASH_CR_DMAA_Pos = 0xe
	// Bit mask of DMAA field.
	HASH_HASH_CR_DMAA_Msk = 0x4000
	// Bit DMAA.
	HASH_HASH_CR_DMAA = 0x4000
	// Position of LKEY field.
	HASH_HASH_CR_LKEY_Pos = 0x10
	// Bit mask of LKEY field.
	HASH_HASH_CR_LKEY_Msk = 0x10000
	// Bit LKEY.
	HASH_HASH_CR_LKEY = 0x10000
	// Position of ALGO1 field.
	HASH_HASH_CR_ALGO1_Pos = 0x12
	// Bit mask of ALGO1 field.
	HASH_HASH_CR_ALGO1_Msk = 0x40000
	// Bit ALGO1.
	HASH_HASH_CR_ALGO1 = 0x40000

	// HASH_DIN: HASH_DIN is the data input register.
	// Position of DATAIN field.
	HASH_HASH_DIN_DATAIN_Pos = 0x0
	// Bit mask of DATAIN field.
	HASH_HASH_DIN_DATAIN_Msk = 0xffffffff

	// HASH_STR: The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1
	// Position of NBLW field.
	HASH_HASH_STR_NBLW_Pos = 0x0
	// Bit mask of NBLW field.
	HASH_HASH_STR_NBLW_Msk = 0x1f
	// Position of DCAL field.
	HASH_HASH_STR_DCAL_Pos = 0x8
	// Bit mask of DCAL field.
	HASH_HASH_STR_DCAL_Msk = 0x100
	// Bit DCAL.
	HASH_HASH_STR_DCAL = 0x100

	// HASH_HR0: HASH digest register 0
	// Position of H0 field.
	HASH_HASH_HR0_H0_Pos = 0x0
	// Bit mask of H0 field.
	HASH_HASH_HR0_H0_Msk = 0xffffffff

	// HASH_HR1: HASH digest register 1
	// Position of H1 field.
	HASH_HASH_HR1_H1_Pos = 0x0
	// Bit mask of H1 field.
	HASH_HASH_HR1_H1_Msk = 0xffffffff

	// HASH_HR2: HASH digest register 2
	// Position of H2 field.
	HASH_HASH_HR2_H2_Pos = 0x0
	// Bit mask of H2 field.
	HASH_HASH_HR2_H2_Msk = 0xffffffff

	// HASH_HR3: HASH digest register 3
	// Position of H3 field.
	HASH_HASH_HR3_H3_Pos = 0x0
	// Bit mask of H3 field.
	HASH_HASH_HR3_H3_Msk = 0xffffffff

	// HASH_HR4: HASH digest register 4
	// Position of H4 field.
	HASH_HASH_HR4_H4_Pos = 0x0
	// Bit mask of H4 field.
	HASH_HASH_HR4_H4_Msk = 0xffffffff

	// HASH_IMR: HASH interrupt enable register
	// Position of DINIE field.
	HASH_HASH_IMR_DINIE_Pos = 0x0
	// Bit mask of DINIE field.
	HASH_HASH_IMR_DINIE_Msk = 0x1
	// Bit DINIE.
	HASH_HASH_IMR_DINIE = 0x1
	// Position of DCIE field.
	HASH_HASH_IMR_DCIE_Pos = 0x1
	// Bit mask of DCIE field.
	HASH_HASH_IMR_DCIE_Msk = 0x2
	// Bit DCIE.
	HASH_HASH_IMR_DCIE = 0x2

	// HASH_SR: HASH status register
	// Position of DINIS field.
	HASH_HASH_SR_DINIS_Pos = 0x0
	// Bit mask of DINIS field.
	HASH_HASH_SR_DINIS_Msk = 0x1
	// Bit DINIS.
	HASH_HASH_SR_DINIS = 0x1
	// Position of DCIS field.
	HASH_HASH_SR_DCIS_Pos = 0x1
	// Bit mask of DCIS field.
	HASH_HASH_SR_DCIS_Msk = 0x2
	// Bit DCIS.
	HASH_HASH_SR_DCIS = 0x2
	// Position of DMAS field.
	HASH_HASH_SR_DMAS_Pos = 0x2
	// Bit mask of DMAS field.
	HASH_HASH_SR_DMAS_Msk = 0x4
	// Bit DMAS.
	HASH_HASH_SR_DMAS = 0x4
	// Position of BUSY field.
	HASH_HASH_SR_BUSY_Pos = 0x3
	// Bit mask of BUSY field.
	HASH_HASH_SR_BUSY_Msk = 0x8
	// Bit BUSY.
	HASH_HASH_SR_BUSY = 0x8

	// HASH_CSR0: These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers.
	// Position of CS0 field.
	HASH_HASH_CSR0_CS0_Pos = 0x0
	// Bit mask of CS0 field.
	HASH_HASH_CSR0_CS0_Msk = 0xffffffff

	// HASH_CSR1: HASH context swap registers
	// Position of CS1 field.
	HASH_HASH_CSR1_CS1_Pos = 0x0
	// Bit mask of CS1 field.
	HASH_HASH_CSR1_CS1_Msk = 0xffffffff

	// HASH_CSR2: HASH context swap registers
	// Position of CS2 field.
	HASH_HASH_CSR2_CS2_Pos = 0x0
	// Bit mask of CS2 field.
	HASH_HASH_CSR2_CS2_Msk = 0xffffffff

	// HASH_CSR3: HASH context swap registers
	// Position of CS3 field.
	HASH_HASH_CSR3_CS3_Pos = 0x0
	// Bit mask of CS3 field.
	HASH_HASH_CSR3_CS3_Msk = 0xffffffff

	// HASH_CSR4: HASH context swap registers
	// Position of CS4 field.
	HASH_HASH_CSR4_CS4_Pos = 0x0
	// Bit mask of CS4 field.
	HASH_HASH_CSR4_CS4_Msk = 0xffffffff

	// HASH_CSR5: HASH context swap registers
	// Position of CS5 field.
	HASH_HASH_CSR5_CS5_Pos = 0x0
	// Bit mask of CS5 field.
	HASH_HASH_CSR5_CS5_Msk = 0xffffffff

	// HASH_CSR6: HASH context swap registers
	// Position of CS6 field.
	HASH_HASH_CSR6_CS6_Pos = 0x0
	// Bit mask of CS6 field.
	HASH_HASH_CSR6_CS6_Msk = 0xffffffff

	// HASH_CSR7: HASH context swap registers
	// Position of CS7 field.
	HASH_HASH_CSR7_CS7_Pos = 0x0
	// Bit mask of CS7 field.
	HASH_HASH_CSR7_CS7_Msk = 0xffffffff

	// HASH_CSR8: HASH context swap registers
	// Position of CS8 field.
	HASH_HASH_CSR8_CS8_Pos = 0x0
	// Bit mask of CS8 field.
	HASH_HASH_CSR8_CS8_Msk = 0xffffffff

	// HASH_CSR9: HASH context swap registers
	// Position of CS9 field.
	HASH_HASH_CSR9_CS9_Pos = 0x0
	// Bit mask of CS9 field.
	HASH_HASH_CSR9_CS9_Msk = 0xffffffff

	// HASH_CSR10: HASH context swap registers
	// Position of CS10 field.
	HASH_HASH_CSR10_CS10_Pos = 0x0
	// Bit mask of CS10 field.
	HASH_HASH_CSR10_CS10_Msk = 0xffffffff

	// HASH_CSR11: HASH context swap registers
	// Position of CS11 field.
	HASH_HASH_CSR11_CS11_Pos = 0x0
	// Bit mask of CS11 field.
	HASH_HASH_CSR11_CS11_Msk = 0xffffffff

	// HASH_CSR12: HASH context swap registers
	// Position of CS12 field.
	HASH_HASH_CSR12_CS12_Pos = 0x0
	// Bit mask of CS12 field.
	HASH_HASH_CSR12_CS12_Msk = 0xffffffff

	// HASH_CSR13: HASH context swap registers
	// Position of CS13 field.
	HASH_HASH_CSR13_CS13_Pos = 0x0
	// Bit mask of CS13 field.
	HASH_HASH_CSR13_CS13_Msk = 0xffffffff

	// HASH_CSR14: HASH context swap registers
	// Position of CS14 field.
	HASH_HASH_CSR14_CS14_Pos = 0x0
	// Bit mask of CS14 field.
	HASH_HASH_CSR14_CS14_Msk = 0xffffffff

	// HASH_CSR15: HASH context swap registers
	// Position of CS15 field.
	HASH_HASH_CSR15_CS15_Pos = 0x0
	// Bit mask of CS15 field.
	HASH_HASH_CSR15_CS15_Msk = 0xffffffff

	// HASH_CSR16: HASH context swap registers
	// Position of CS16 field.
	HASH_HASH_CSR16_CS16_Pos = 0x0
	// Bit mask of CS16 field.
	HASH_HASH_CSR16_CS16_Msk = 0xffffffff

	// HASH_CSR17: HASH context swap registers
	// Position of CS17 field.
	HASH_HASH_CSR17_CS17_Pos = 0x0
	// Bit mask of CS17 field.
	HASH_HASH_CSR17_CS17_Msk = 0xffffffff

	// HASH_CSR18: HASH context swap registers
	// Position of CS18 field.
	HASH_HASH_CSR18_CS18_Pos = 0x0
	// Bit mask of CS18 field.
	HASH_HASH_CSR18_CS18_Msk = 0xffffffff

	// HASH_CSR19: HASH context swap registers
	// Position of CS19 field.
	HASH_HASH_CSR19_CS19_Pos = 0x0
	// Bit mask of CS19 field.
	HASH_HASH_CSR19_CS19_Msk = 0xffffffff

	// HASH_CSR20: HASH context swap registers
	// Position of CS20 field.
	HASH_HASH_CSR20_CS20_Pos = 0x0
	// Bit mask of CS20 field.
	HASH_HASH_CSR20_CS20_Msk = 0xffffffff

	// HASH_CSR21: HASH context swap registers
	// Position of CS21 field.
	HASH_HASH_CSR21_CS21_Pos = 0x0
	// Bit mask of CS21 field.
	HASH_HASH_CSR21_CS21_Msk = 0xffffffff

	// HASH_CSR22: HASH context swap registers
	// Position of CS22 field.
	HASH_HASH_CSR22_CS22_Pos = 0x0
	// Bit mask of CS22 field.
	HASH_HASH_CSR22_CS22_Msk = 0xffffffff

	// HASH_CSR23: HASH context swap registers
	// Position of CS23 field.
	HASH_HASH_CSR23_CS23_Pos = 0x0
	// Bit mask of CS23 field.
	HASH_HASH_CSR23_CS23_Msk = 0xffffffff

	// HASH_CSR24: HASH context swap registers
	// Position of CS24 field.
	HASH_HASH_CSR24_CS24_Pos = 0x0
	// Bit mask of CS24 field.
	HASH_HASH_CSR24_CS24_Msk = 0xffffffff

	// HASH_CSR25: HASH context swap registers
	// Position of CS25 field.
	HASH_HASH_CSR25_CS25_Pos = 0x0
	// Bit mask of CS25 field.
	HASH_HASH_CSR25_CS25_Msk = 0xffffffff

	// HASH_CSR26: HASH context swap registers
	// Position of CS26 field.
	HASH_HASH_CSR26_CS26_Pos = 0x0
	// Bit mask of CS26 field.
	HASH_HASH_CSR26_CS26_Msk = 0xffffffff

	// HASH_CSR27: HASH context swap registers
	// Position of CS27 field.
	HASH_HASH_CSR27_CS27_Pos = 0x0
	// Bit mask of CS27 field.
	HASH_HASH_CSR27_CS27_Msk = 0xffffffff

	// HASH_CSR28: HASH context swap registers
	// Position of CS28 field.
	HASH_HASH_CSR28_CS28_Pos = 0x0
	// Bit mask of CS28 field.
	HASH_HASH_CSR28_CS28_Msk = 0xffffffff

	// HASH_CSR29: HASH context swap registers
	// Position of CS29 field.
	HASH_HASH_CSR29_CS29_Pos = 0x0
	// Bit mask of CS29 field.
	HASH_HASH_CSR29_CS29_Msk = 0xffffffff

	// HASH_CSR30: HASH context swap registers
	// Position of CS30 field.
	HASH_HASH_CSR30_CS30_Pos = 0x0
	// Bit mask of CS30 field.
	HASH_HASH_CSR30_CS30_Msk = 0xffffffff

	// HASH_CSR31: HASH context swap registers
	// Position of CS31 field.
	HASH_HASH_CSR31_CS31_Pos = 0x0
	// Bit mask of CS31 field.
	HASH_HASH_CSR31_CS31_Msk = 0xffffffff

	// HASH_CSR32: HASH context swap registers
	// Position of CS32 field.
	HASH_HASH_CSR32_CS32_Pos = 0x0
	// Bit mask of CS32 field.
	HASH_HASH_CSR32_CS32_Msk = 0xffffffff

	// HASH_CSR33: HASH context swap registers
	// Position of CS33 field.
	HASH_HASH_CSR33_CS33_Pos = 0x0
	// Bit mask of CS33 field.
	HASH_HASH_CSR33_CS33_Msk = 0xffffffff

	// HASH_CSR34: HASH context swap registers
	// Position of CS34 field.
	HASH_HASH_CSR34_CS34_Pos = 0x0
	// Bit mask of CS34 field.
	HASH_HASH_CSR34_CS34_Msk = 0xffffffff

	// HASH_CSR35: HASH context swap registers
	// Position of CS35 field.
	HASH_HASH_CSR35_CS35_Pos = 0x0
	// Bit mask of CS35 field.
	HASH_HASH_CSR35_CS35_Msk = 0xffffffff

	// HASH_CSR36: HASH context swap registers
	// Position of CS36 field.
	HASH_HASH_CSR36_CS36_Pos = 0x0
	// Bit mask of CS36 field.
	HASH_HASH_CSR36_CS36_Msk = 0xffffffff

	// HASH_CSR37: HASH context swap registers
	// Position of CS37 field.
	HASH_HASH_CSR37_CS37_Pos = 0x0
	// Bit mask of CS37 field.
	HASH_HASH_CSR37_CS37_Msk = 0xffffffff

	// HASH_CSR38: HASH context swap registers
	// Position of CS38 field.
	HASH_HASH_CSR38_CS38_Pos = 0x0
	// Bit mask of CS38 field.
	HASH_HASH_CSR38_CS38_Msk = 0xffffffff

	// HASH_CSR39: HASH context swap registers
	// Position of CS39 field.
	HASH_HASH_CSR39_CS39_Pos = 0x0
	// Bit mask of CS39 field.
	HASH_HASH_CSR39_CS39_Msk = 0xffffffff

	// HASH_CSR40: HASH context swap registers
	// Position of CS40 field.
	HASH_HASH_CSR40_CS40_Pos = 0x0
	// Bit mask of CS40 field.
	HASH_HASH_CSR40_CS40_Msk = 0xffffffff

	// HASH_CSR41: HASH context swap registers
	// Position of CS41 field.
	HASH_HASH_CSR41_CS41_Pos = 0x0
	// Bit mask of CS41 field.
	HASH_HASH_CSR41_CS41_Msk = 0xffffffff

	// HASH_CSR42: HASH context swap registers
	// Position of CS42 field.
	HASH_HASH_CSR42_CS42_Pos = 0x0
	// Bit mask of CS42 field.
	HASH_HASH_CSR42_CS42_Msk = 0xffffffff

	// HASH_CSR43: HASH context swap registers
	// Position of CS43 field.
	HASH_HASH_CSR43_CS43_Pos = 0x0
	// Bit mask of CS43 field.
	HASH_HASH_CSR43_CS43_Msk = 0xffffffff

	// HASH_CSR44: HASH context swap registers
	// Position of CS44 field.
	HASH_HASH_CSR44_CS44_Pos = 0x0
	// Bit mask of CS44 field.
	HASH_HASH_CSR44_CS44_Msk = 0xffffffff

	// HASH_CSR45: HASH context swap registers
	// Position of CS45 field.
	HASH_HASH_CSR45_CS45_Pos = 0x0
	// Bit mask of CS45 field.
	HASH_HASH_CSR45_CS45_Msk = 0xffffffff

	// HASH_CSR46: HASH context swap registers
	// Position of CS46 field.
	HASH_HASH_CSR46_CS46_Pos = 0x0
	// Bit mask of CS46 field.
	HASH_HASH_CSR46_CS46_Msk = 0xffffffff

	// HASH_CSR47: HASH context swap registers
	// Position of CS47 field.
	HASH_HASH_CSR47_CS47_Pos = 0x0
	// Bit mask of CS47 field.
	HASH_HASH_CSR47_CS47_Msk = 0xffffffff

	// HASH_CSR48: HASH context swap registers
	// Position of CS48 field.
	HASH_HASH_CSR48_CS48_Pos = 0x0
	// Bit mask of CS48 field.
	HASH_HASH_CSR48_CS48_Msk = 0xffffffff

	// HASH_CSR49: HASH context swap registers
	// Position of CS49 field.
	HASH_HASH_CSR49_CS49_Pos = 0x0
	// Bit mask of CS49 field.
	HASH_HASH_CSR49_CS49_Msk = 0xffffffff

	// HASH_CSR50: HASH context swap registers
	// Position of CS50 field.
	HASH_HASH_CSR50_CS50_Pos = 0x0
	// Bit mask of CS50 field.
	HASH_HASH_CSR50_CS50_Msk = 0xffffffff

	// HASH_CSR51: HASH context swap registers
	// Position of CS51 field.
	HASH_HASH_CSR51_CS51_Pos = 0x0
	// Bit mask of CS51 field.
	HASH_HASH_CSR51_CS51_Msk = 0xffffffff

	// HASH_CSR52: HASH context swap registers
	// Position of CS52 field.
	HASH_HASH_CSR52_CS52_Pos = 0x0
	// Bit mask of CS52 field.
	HASH_HASH_CSR52_CS52_Msk = 0xffffffff

	// HASH_CSR53: HASH context swap registers
	// Position of CS53 field.
	HASH_HASH_CSR53_CS53_Pos = 0x0
	// Bit mask of CS53 field.
	HASH_HASH_CSR53_CS53_Msk = 0xffffffff

	// HASH_HR5: HASH digest register 5
	// Position of H5 field.
	HASH_HASH_HR5_H5_Pos = 0x0
	// Bit mask of H5 field.
	HASH_HASH_HR5_H5_Msk = 0xffffffff

	// HASH_HR6: HASH digest register 6
	// Position of H6 field.
	HASH_HASH_HR6_H6_Pos = 0x0
	// Bit mask of H6 field.
	HASH_HASH_HR6_H6_Msk = 0xffffffff

	// HASH_HR7: HASH digest register 7
	// Position of H7 field.
	HASH_HASH_HR7_H7_Pos = 0x0
	// Bit mask of H7 field.
	HASH_HASH_HR7_H7_Msk = 0xffffffff

	// HASH_HWCFGR: HASH Hardware Configuration Register
	// Position of CFG1 field.
	HASH_HASH_HWCFGR_CFG1_Pos = 0x0
	// Bit mask of CFG1 field.
	HASH_HASH_HWCFGR_CFG1_Msk = 0xf

	// HASH_VERR: HASH Version Register
	// Position of VER field.
	HASH_HASH_VERR_VER_Pos = 0x0
	// Bit mask of VER field.
	HASH_HASH_VERR_VER_Msk = 0xff

	// HASH_IPIDR: HASH Identification
	// Position of ID field.
	HASH_HASH_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	HASH_HASH_IPIDR_ID_Msk = 0xffffffff

	// HASH_MID: HASH Hardware Magic ID
	// Position of MID field.
	HASH_HASH_MID_MID_Pos = 0x0
	// Bit mask of MID field.
	HASH_HASH_MID_MID_Msk = 0xffffffff
)

// Bitfields for HDMI_CEC: HDMI_CEC
const (
	// CEC_CR: CEC control register
	// Position of CECEN field.
	HDMI_CEC_CEC_CR_CECEN_Pos = 0x0
	// Bit mask of CECEN field.
	HDMI_CEC_CEC_CR_CECEN_Msk = 0x1
	// Bit CECEN.
	HDMI_CEC_CEC_CR_CECEN = 0x1
	// Position of TXSOM field.
	HDMI_CEC_CEC_CR_TXSOM_Pos = 0x1
	// Bit mask of TXSOM field.
	HDMI_CEC_CEC_CR_TXSOM_Msk = 0x2
	// Bit TXSOM.
	HDMI_CEC_CEC_CR_TXSOM = 0x2
	// Position of TXEOM field.
	HDMI_CEC_CEC_CR_TXEOM_Pos = 0x2
	// Bit mask of TXEOM field.
	HDMI_CEC_CEC_CR_TXEOM_Msk = 0x4
	// Bit TXEOM.
	HDMI_CEC_CEC_CR_TXEOM = 0x4

	// CEC_CFGR: This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.
	// Position of SFT field.
	HDMI_CEC_CEC_CFGR_SFT_Pos = 0x0
	// Bit mask of SFT field.
	HDMI_CEC_CEC_CFGR_SFT_Msk = 0x7
	// Position of RXTOL field.
	HDMI_CEC_CEC_CFGR_RXTOL_Pos = 0x3
	// Bit mask of RXTOL field.
	HDMI_CEC_CEC_CFGR_RXTOL_Msk = 0x8
	// Bit RXTOL.
	HDMI_CEC_CEC_CFGR_RXTOL = 0x8
	// Position of BRESTP field.
	HDMI_CEC_CEC_CFGR_BRESTP_Pos = 0x4
	// Bit mask of BRESTP field.
	HDMI_CEC_CEC_CFGR_BRESTP_Msk = 0x10
	// Bit BRESTP.
	HDMI_CEC_CEC_CFGR_BRESTP = 0x10
	// Position of BREGEN field.
	HDMI_CEC_CEC_CFGR_BREGEN_Pos = 0x5
	// Bit mask of BREGEN field.
	HDMI_CEC_CEC_CFGR_BREGEN_Msk = 0x20
	// Bit BREGEN.
	HDMI_CEC_CEC_CFGR_BREGEN = 0x20
	// Position of LBPEGEN field.
	HDMI_CEC_CEC_CFGR_LBPEGEN_Pos = 0x6
	// Bit mask of LBPEGEN field.
	HDMI_CEC_CEC_CFGR_LBPEGEN_Msk = 0x40
	// Bit LBPEGEN.
	HDMI_CEC_CEC_CFGR_LBPEGEN = 0x40
	// Position of BRDNOGEN field.
	HDMI_CEC_CEC_CFGR_BRDNOGEN_Pos = 0x7
	// Bit mask of BRDNOGEN field.
	HDMI_CEC_CEC_CFGR_BRDNOGEN_Msk = 0x80
	// Bit BRDNOGEN.
	HDMI_CEC_CEC_CFGR_BRDNOGEN = 0x80
	// Position of SFTOP field.
	HDMI_CEC_CEC_CFGR_SFTOP_Pos = 0x8
	// Bit mask of SFTOP field.
	HDMI_CEC_CEC_CFGR_SFTOP_Msk = 0x100
	// Bit SFTOP.
	HDMI_CEC_CEC_CFGR_SFTOP = 0x100
	// Position of OAR field.
	HDMI_CEC_CEC_CFGR_OAR_Pos = 0x10
	// Bit mask of OAR field.
	HDMI_CEC_CEC_CFGR_OAR_Msk = 0x7fff0000
	// Position of LSTN field.
	HDMI_CEC_CEC_CFGR_LSTN_Pos = 0x1f
	// Bit mask of LSTN field.
	HDMI_CEC_CEC_CFGR_LSTN_Msk = 0x80000000
	// Bit LSTN.
	HDMI_CEC_CEC_CFGR_LSTN = 0x80000000

	// CEC_TXDR: CEC Tx data register
	// Position of TXD field.
	HDMI_CEC_CEC_TXDR_TXD_Pos = 0x0
	// Bit mask of TXD field.
	HDMI_CEC_CEC_TXDR_TXD_Msk = 0xff

	// CEC_RXDR: CEC Rx data register
	// Position of RXD field.
	HDMI_CEC_CEC_RXDR_RXD_Pos = 0x0
	// Bit mask of RXD field.
	HDMI_CEC_CEC_RXDR_RXD_Msk = 0xff

	// CEC_ISR: CEC Interrupt and Status Register
	// Position of RXBR field.
	HDMI_CEC_CEC_ISR_RXBR_Pos = 0x0
	// Bit mask of RXBR field.
	HDMI_CEC_CEC_ISR_RXBR_Msk = 0x1
	// Bit RXBR.
	HDMI_CEC_CEC_ISR_RXBR = 0x1
	// Position of RXEND field.
	HDMI_CEC_CEC_ISR_RXEND_Pos = 0x1
	// Bit mask of RXEND field.
	HDMI_CEC_CEC_ISR_RXEND_Msk = 0x2
	// Bit RXEND.
	HDMI_CEC_CEC_ISR_RXEND = 0x2
	// Position of RXOVR field.
	HDMI_CEC_CEC_ISR_RXOVR_Pos = 0x2
	// Bit mask of RXOVR field.
	HDMI_CEC_CEC_ISR_RXOVR_Msk = 0x4
	// Bit RXOVR.
	HDMI_CEC_CEC_ISR_RXOVR = 0x4
	// Position of BRE field.
	HDMI_CEC_CEC_ISR_BRE_Pos = 0x3
	// Bit mask of BRE field.
	HDMI_CEC_CEC_ISR_BRE_Msk = 0x8
	// Bit BRE.
	HDMI_CEC_CEC_ISR_BRE = 0x8
	// Position of SBPE field.
	HDMI_CEC_CEC_ISR_SBPE_Pos = 0x4
	// Bit mask of SBPE field.
	HDMI_CEC_CEC_ISR_SBPE_Msk = 0x10
	// Bit SBPE.
	HDMI_CEC_CEC_ISR_SBPE = 0x10
	// Position of LBPE field.
	HDMI_CEC_CEC_ISR_LBPE_Pos = 0x5
	// Bit mask of LBPE field.
	HDMI_CEC_CEC_ISR_LBPE_Msk = 0x20
	// Bit LBPE.
	HDMI_CEC_CEC_ISR_LBPE = 0x20
	// Position of RXACKE field.
	HDMI_CEC_CEC_ISR_RXACKE_Pos = 0x6
	// Bit mask of RXACKE field.
	HDMI_CEC_CEC_ISR_RXACKE_Msk = 0x40
	// Bit RXACKE.
	HDMI_CEC_CEC_ISR_RXACKE = 0x40
	// Position of ARBLST field.
	HDMI_CEC_CEC_ISR_ARBLST_Pos = 0x7
	// Bit mask of ARBLST field.
	HDMI_CEC_CEC_ISR_ARBLST_Msk = 0x80
	// Bit ARBLST.
	HDMI_CEC_CEC_ISR_ARBLST = 0x80
	// Position of TXBR field.
	HDMI_CEC_CEC_ISR_TXBR_Pos = 0x8
	// Bit mask of TXBR field.
	HDMI_CEC_CEC_ISR_TXBR_Msk = 0x100
	// Bit TXBR.
	HDMI_CEC_CEC_ISR_TXBR = 0x100
	// Position of TXEND field.
	HDMI_CEC_CEC_ISR_TXEND_Pos = 0x9
	// Bit mask of TXEND field.
	HDMI_CEC_CEC_ISR_TXEND_Msk = 0x200
	// Bit TXEND.
	HDMI_CEC_CEC_ISR_TXEND = 0x200
	// Position of TXUDR field.
	HDMI_CEC_CEC_ISR_TXUDR_Pos = 0xa
	// Bit mask of TXUDR field.
	HDMI_CEC_CEC_ISR_TXUDR_Msk = 0x400
	// Bit TXUDR.
	HDMI_CEC_CEC_ISR_TXUDR = 0x400
	// Position of TXERR field.
	HDMI_CEC_CEC_ISR_TXERR_Pos = 0xb
	// Bit mask of TXERR field.
	HDMI_CEC_CEC_ISR_TXERR_Msk = 0x800
	// Bit TXERR.
	HDMI_CEC_CEC_ISR_TXERR = 0x800
	// Position of TXACKE field.
	HDMI_CEC_CEC_ISR_TXACKE_Pos = 0xc
	// Bit mask of TXACKE field.
	HDMI_CEC_CEC_ISR_TXACKE_Msk = 0x1000
	// Bit TXACKE.
	HDMI_CEC_CEC_ISR_TXACKE = 0x1000

	// CEC_IER: CEC interrupt enable register
	// Position of RXBRIE field.
	HDMI_CEC_CEC_IER_RXBRIE_Pos = 0x0
	// Bit mask of RXBRIE field.
	HDMI_CEC_CEC_IER_RXBRIE_Msk = 0x1
	// Bit RXBRIE.
	HDMI_CEC_CEC_IER_RXBRIE = 0x1
	// Position of RXENDIE field.
	HDMI_CEC_CEC_IER_RXENDIE_Pos = 0x1
	// Bit mask of RXENDIE field.
	HDMI_CEC_CEC_IER_RXENDIE_Msk = 0x2
	// Bit RXENDIE.
	HDMI_CEC_CEC_IER_RXENDIE = 0x2
	// Position of RXOVRIE field.
	HDMI_CEC_CEC_IER_RXOVRIE_Pos = 0x2
	// Bit mask of RXOVRIE field.
	HDMI_CEC_CEC_IER_RXOVRIE_Msk = 0x4
	// Bit RXOVRIE.
	HDMI_CEC_CEC_IER_RXOVRIE = 0x4
	// Position of BREIE field.
	HDMI_CEC_CEC_IER_BREIE_Pos = 0x3
	// Bit mask of BREIE field.
	HDMI_CEC_CEC_IER_BREIE_Msk = 0x8
	// Bit BREIE.
	HDMI_CEC_CEC_IER_BREIE = 0x8
	// Position of SBPEIE field.
	HDMI_CEC_CEC_IER_SBPEIE_Pos = 0x4
	// Bit mask of SBPEIE field.
	HDMI_CEC_CEC_IER_SBPEIE_Msk = 0x10
	// Bit SBPEIE.
	HDMI_CEC_CEC_IER_SBPEIE = 0x10
	// Position of LBPEIE field.
	HDMI_CEC_CEC_IER_LBPEIE_Pos = 0x5
	// Bit mask of LBPEIE field.
	HDMI_CEC_CEC_IER_LBPEIE_Msk = 0x20
	// Bit LBPEIE.
	HDMI_CEC_CEC_IER_LBPEIE = 0x20
	// Position of RXACKIE field.
	HDMI_CEC_CEC_IER_RXACKIE_Pos = 0x6
	// Bit mask of RXACKIE field.
	HDMI_CEC_CEC_IER_RXACKIE_Msk = 0x40
	// Bit RXACKIE.
	HDMI_CEC_CEC_IER_RXACKIE = 0x40
	// Position of ARBLSTIE field.
	HDMI_CEC_CEC_IER_ARBLSTIE_Pos = 0x7
	// Bit mask of ARBLSTIE field.
	HDMI_CEC_CEC_IER_ARBLSTIE_Msk = 0x80
	// Bit ARBLSTIE.
	HDMI_CEC_CEC_IER_ARBLSTIE = 0x80
	// Position of TXBRIE field.
	HDMI_CEC_CEC_IER_TXBRIE_Pos = 0x8
	// Bit mask of TXBRIE field.
	HDMI_CEC_CEC_IER_TXBRIE_Msk = 0x100
	// Bit TXBRIE.
	HDMI_CEC_CEC_IER_TXBRIE = 0x100
	// Position of TXENDIE field.
	HDMI_CEC_CEC_IER_TXENDIE_Pos = 0x9
	// Bit mask of TXENDIE field.
	HDMI_CEC_CEC_IER_TXENDIE_Msk = 0x200
	// Bit TXENDIE.
	HDMI_CEC_CEC_IER_TXENDIE = 0x200
	// Position of TXUDRIE field.
	HDMI_CEC_CEC_IER_TXUDRIE_Pos = 0xa
	// Bit mask of TXUDRIE field.
	HDMI_CEC_CEC_IER_TXUDRIE_Msk = 0x400
	// Bit TXUDRIE.
	HDMI_CEC_CEC_IER_TXUDRIE = 0x400
	// Position of TXERRIE field.
	HDMI_CEC_CEC_IER_TXERRIE_Pos = 0xb
	// Bit mask of TXERRIE field.
	HDMI_CEC_CEC_IER_TXERRIE_Msk = 0x800
	// Bit TXERRIE.
	HDMI_CEC_CEC_IER_TXERRIE = 0x800
	// Position of TXACKIE field.
	HDMI_CEC_CEC_IER_TXACKIE_Pos = 0xc
	// Bit mask of TXACKIE field.
	HDMI_CEC_CEC_IER_TXACKIE_Msk = 0x1000
	// Bit TXACKIE.
	HDMI_CEC_CEC_IER_TXACKIE = 0x1000
)

// Bitfields for HDP: HDP
const (
	// HDP_CTRL: HDP Control
	// Position of EN field.
	HDP_HDP_CTRL_EN_Pos = 0x0
	// Bit mask of EN field.
	HDP_HDP_CTRL_EN_Msk = 0x1
	// Bit EN.
	HDP_HDP_CTRL_EN = 0x1

	// HDP_MUX: HDP multiplexing
	// Position of MUX0 field.
	HDP_HDP_MUX_MUX0_Pos = 0x0
	// Bit mask of MUX0 field.
	HDP_HDP_MUX_MUX0_Msk = 0xf
	// Position of MUX1 field.
	HDP_HDP_MUX_MUX1_Pos = 0x4
	// Bit mask of MUX1 field.
	HDP_HDP_MUX_MUX1_Msk = 0xf0
	// Position of MUX2 field.
	HDP_HDP_MUX_MUX2_Pos = 0x8
	// Bit mask of MUX2 field.
	HDP_HDP_MUX_MUX2_Msk = 0xf00
	// Position of MUX3 field.
	HDP_HDP_MUX_MUX3_Pos = 0xc
	// Bit mask of MUX3 field.
	HDP_HDP_MUX_MUX3_Msk = 0xf000
	// Position of MUX4 field.
	HDP_HDP_MUX_MUX4_Pos = 0x10
	// Bit mask of MUX4 field.
	HDP_HDP_MUX_MUX4_Msk = 0xf0000
	// Position of MUX5 field.
	HDP_HDP_MUX_MUX5_Pos = 0x14
	// Bit mask of MUX5 field.
	HDP_HDP_MUX_MUX5_Msk = 0xf00000
	// Position of MUX6 field.
	HDP_HDP_MUX_MUX6_Pos = 0x18
	// Bit mask of MUX6 field.
	HDP_HDP_MUX_MUX6_Msk = 0xf000000
	// Position of MUX7 field.
	HDP_HDP_MUX_MUX7_Pos = 0x1c
	// Bit mask of MUX7 field.
	HDP_HDP_MUX_MUX7_Msk = 0xf0000000

	// HDP_VAL: HDP value
	// Position of HDPVAL field.
	HDP_HDP_VAL_HDPVAL_Pos = 0x0
	// Bit mask of HDPVAL field.
	HDP_HDP_VAL_HDPVAL_Msk = 0xff

	// HDP_GPOSET: HDP GPO set
	// Position of HDPGPOSET field.
	HDP_HDP_GPOSET_HDPGPOSET_Pos = 0x0
	// Bit mask of HDPGPOSET field.
	HDP_HDP_GPOSET_HDPGPOSET_Msk = 0xff

	// HDP_GPOCLR: HDP GPO clear
	// Position of HDPGPOCLR field.
	HDP_HDP_GPOCLR_HDPGPOCLR_Pos = 0x0
	// Bit mask of HDPGPOCLR field.
	HDP_HDP_GPOCLR_HDPGPOCLR_Msk = 0xff

	// HDP_GPOVAL: HDP GPO value
	// Position of HDPGPOVAL field.
	HDP_HDP_GPOVAL_HDPGPOVAL_Pos = 0x0
	// Bit mask of HDPGPOVAL field.
	HDP_HDP_GPOVAL_HDPGPOVAL_Msk = 0xff

	// HDP_VERR: HDP version register
	// Position of MINREV field.
	HDP_HDP_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	HDP_HDP_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	HDP_HDP_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	HDP_HDP_VERR_MAJREV_Msk = 0xf0

	// HDP_IPIDR: HDP IP identification register
	// Position of ID field.
	HDP_HDP_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	HDP_HDP_IPIDR_ID_Msk = 0xffffffff

	// HDP_SIDR: HDP size identification register
	// Position of SID field.
	HDP_HDP_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	HDP_HDP_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for HSEM: HSEM
const (
	// HSEM_R0: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R0_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R0_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R0_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R0_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R0_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R0_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R0_LOCK = 0x80000000

	// HSEM_R1: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R1_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R1_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R1_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R1_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R1_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R1_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R1_LOCK = 0x80000000

	// HSEM_R2: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R2_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R2_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R2_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R2_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R2_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R2_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R2_LOCK = 0x80000000

	// HSEM_R3: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R3_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R3_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R3_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R3_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R3_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R3_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R3_LOCK = 0x80000000

	// HSEM_R4: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R4_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R4_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R4_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R4_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R4_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R4_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R4_LOCK = 0x80000000

	// HSEM_R5: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R5_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R5_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R5_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R5_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R5_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R5_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R5_LOCK = 0x80000000

	// HSEM_R6: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R6_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R6_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R6_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R6_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R6_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R6_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R6_LOCK = 0x80000000

	// HSEM_R7: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R7_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R7_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R7_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R7_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R7_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R7_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R7_LOCK = 0x80000000

	// HSEM_R8: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R8_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R8_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R8_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R8_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R8_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R8_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R8_LOCK = 0x80000000

	// HSEM_R9: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R9_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R9_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R9_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R9_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R9_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R9_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R9_LOCK = 0x80000000

	// HSEM_R10: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R10_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R10_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R10_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R10_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R10_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R10_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R10_LOCK = 0x80000000

	// HSEM_R11: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R11_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R11_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R11_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R11_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R11_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R11_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R11_LOCK = 0x80000000

	// HSEM_R12: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R12_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R12_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R12_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R12_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R12_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R12_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R12_LOCK = 0x80000000

	// HSEM_R13: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R13_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R13_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R13_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R13_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R13_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R13_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R13_LOCK = 0x80000000

	// HSEM_R14: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R14_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R14_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R14_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R14_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R14_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R14_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R14_LOCK = 0x80000000

	// HSEM_R15: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R15_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R15_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R15_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R15_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R15_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R15_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R15_LOCK = 0x80000000

	// HSEM_R16: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R16_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R16_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R16_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R16_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R16_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R16_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R16_LOCK = 0x80000000

	// HSEM_R17: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R17_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R17_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R17_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R17_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R17_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R17_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R17_LOCK = 0x80000000

	// HSEM_R18: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R18_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R18_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R18_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R18_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R18_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R18_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R18_LOCK = 0x80000000

	// HSEM_R19: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R19_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R19_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R19_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R19_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R19_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R19_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R19_LOCK = 0x80000000

	// HSEM_R20: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R20_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R20_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R20_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R20_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R20_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R20_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R20_LOCK = 0x80000000

	// HSEM_R21: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R21_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R21_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R21_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R21_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R21_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R21_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R21_LOCK = 0x80000000

	// HSEM_R22: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R22_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R22_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R22_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R22_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R22_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R22_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R22_LOCK = 0x80000000

	// HSEM_R23: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R23_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R23_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R23_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R23_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R23_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R23_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R23_LOCK = 0x80000000

	// HSEM_R24: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R24_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R24_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R24_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R24_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R24_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R24_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R24_LOCK = 0x80000000

	// HSEM_R25: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R25_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R25_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R25_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R25_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R25_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R25_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R25_LOCK = 0x80000000

	// HSEM_R26: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R26_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R26_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R26_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R26_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R26_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R26_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R26_LOCK = 0x80000000

	// HSEM_R27: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R27_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R27_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R27_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R27_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R27_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R27_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R27_LOCK = 0x80000000

	// HSEM_R28: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R28_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R28_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R28_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R28_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R28_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R28_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R28_LOCK = 0x80000000

	// HSEM_R29: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R29_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R29_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R29_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R29_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R29_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R29_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R29_LOCK = 0x80000000

	// HSEM_R30: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R30_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R30_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R30_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R30_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R30_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R30_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R30_LOCK = 0x80000000

	// HSEM_R31: The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_R31_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_R31_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_R31_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_R31_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_R31_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_R31_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_R31_LOCK = 0x80000000

	// HSEM_RLR0: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR0_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR0_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR0_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR0_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR0_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR0_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR0_LOCK = 0x80000000

	// HSEM_RLR1: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR1_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR1_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR1_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR1_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR1_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR1_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR1_LOCK = 0x80000000

	// HSEM_RLR2: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR2_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR2_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR2_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR2_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR2_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR2_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR2_LOCK = 0x80000000

	// HSEM_RLR3: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR3_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR3_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR3_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR3_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR3_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR3_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR3_LOCK = 0x80000000

	// HSEM_RLR4: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR4_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR4_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR4_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR4_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR4_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR4_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR4_LOCK = 0x80000000

	// HSEM_RLR5: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR5_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR5_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR5_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR5_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR5_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR5_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR5_LOCK = 0x80000000

	// HSEM_RLR6: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR6_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR6_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR6_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR6_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR6_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR6_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR6_LOCK = 0x80000000

	// HSEM_RLR7: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR7_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR7_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR7_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR7_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR7_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR7_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR7_LOCK = 0x80000000

	// HSEM_RLR8: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR8_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR8_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR8_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR8_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR8_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR8_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR8_LOCK = 0x80000000

	// HSEM_RLR9: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR9_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR9_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR9_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR9_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR9_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR9_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR9_LOCK = 0x80000000

	// HSEM_RLR10: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR10_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR10_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR10_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR10_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR10_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR10_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR10_LOCK = 0x80000000

	// HSEM_RLR11: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR11_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR11_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR11_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR11_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR11_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR11_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR11_LOCK = 0x80000000

	// HSEM_RLR12: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR12_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR12_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR12_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR12_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR12_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR12_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR12_LOCK = 0x80000000

	// HSEM_RLR13: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR13_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR13_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR13_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR13_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR13_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR13_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR13_LOCK = 0x80000000

	// HSEM_RLR14: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR14_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR14_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR14_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR14_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR14_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR14_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR14_LOCK = 0x80000000

	// HSEM_RLR15: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR15_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR15_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR15_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR15_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR15_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR15_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR15_LOCK = 0x80000000

	// HSEM_RLR16: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR16_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR16_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR16_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR16_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR16_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR16_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR16_LOCK = 0x80000000

	// HSEM_RLR17: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR17_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR17_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR17_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR17_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR17_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR17_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR17_LOCK = 0x80000000

	// HSEM_RLR18: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR18_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR18_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR18_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR18_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR18_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR18_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR18_LOCK = 0x80000000

	// HSEM_RLR19: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR19_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR19_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR19_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR19_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR19_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR19_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR19_LOCK = 0x80000000

	// HSEM_RLR20: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR20_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR20_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR20_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR20_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR20_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR20_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR20_LOCK = 0x80000000

	// HSEM_RLR21: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR21_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR21_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR21_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR21_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR21_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR21_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR21_LOCK = 0x80000000

	// HSEM_RLR22: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR22_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR22_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR22_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR22_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR22_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR22_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR22_LOCK = 0x80000000

	// HSEM_RLR23: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR23_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR23_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR23_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR23_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR23_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR23_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR23_LOCK = 0x80000000

	// HSEM_RLR24: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR24_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR24_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR24_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR24_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR24_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR24_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR24_LOCK = 0x80000000

	// HSEM_RLR25: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR25_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR25_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR25_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR25_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR25_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR25_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR25_LOCK = 0x80000000

	// HSEM_RLR26: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR26_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR26_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR26_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR26_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR26_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR26_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR26_LOCK = 0x80000000

	// HSEM_RLR27: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR27_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR27_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR27_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR27_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR27_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR27_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR27_LOCK = 0x80000000

	// HSEM_RLR28: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR28_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR28_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR28_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR28_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR28_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR28_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR28_LOCK = 0x80000000

	// HSEM_RLR29: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR29_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR29_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR29_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR29_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR29_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR29_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR29_LOCK = 0x80000000

	// HSEM_RLR30: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR30_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR30_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR30_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR30_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR30_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR30_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR30_LOCK = 0x80000000

	// HSEM_RLR31: Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
	// Position of PROCID field.
	HSEM_IPXACT_HSEM_RLR31_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_IPXACT_HSEM_RLR31_PROCID_Msk = 0xff
	// Position of COREID field.
	HSEM_IPXACT_HSEM_RLR31_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_RLR31_COREID_Msk = 0xf00
	// Position of LOCK field.
	HSEM_IPXACT_HSEM_RLR31_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_IPXACT_HSEM_RLR31_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_IPXACT_HSEM_RLR31_LOCK = 0x80000000

	// HSEM_C1IER: HSEM i1terrupt enable register
	// Position of ISE field.
	HSEM_IPXACT_HSEM_C1IER_ISE_Pos = 0x0
	// Bit mask of ISE field.
	HSEM_IPXACT_HSEM_C1IER_ISE_Msk = 0xffffffff

	// HSEM_C1ICR: HSEM i1terrupt clear register
	// Position of ISC field.
	HSEM_IPXACT_HSEM_C1ICR_ISC_Pos = 0x0
	// Bit mask of ISC field.
	HSEM_IPXACT_HSEM_C1ICR_ISC_Msk = 0xffffffff

	// HSEM_C1ISR: HSEM i1terrupt status register
	// Position of ISF field.
	HSEM_IPXACT_HSEM_C1ISR_ISF_Pos = 0x0
	// Bit mask of ISF field.
	HSEM_IPXACT_HSEM_C1ISR_ISF_Msk = 0xffffffff

	// HSEM_C1MISR: HSEM i1terrupt status register
	// Position of MISF field.
	HSEM_IPXACT_HSEM_C1MISR_MISF_Pos = 0x0
	// Bit mask of MISF field.
	HSEM_IPXACT_HSEM_C1MISR_MISF_Msk = 0xffffffff

	// HSEM_C2IER: HSEM i2terrupt enable register
	// Position of ISE field.
	HSEM_IPXACT_HSEM_C2IER_ISE_Pos = 0x0
	// Bit mask of ISE field.
	HSEM_IPXACT_HSEM_C2IER_ISE_Msk = 0xffffffff

	// HSEM_C2ICR: HSEM i2terrupt clear register
	// Position of ISC field.
	HSEM_IPXACT_HSEM_C2ICR_ISC_Pos = 0x0
	// Bit mask of ISC field.
	HSEM_IPXACT_HSEM_C2ICR_ISC_Msk = 0xffffffff

	// HSEM_C2ISR: HSEM i2terrupt status register
	// Position of ISF field.
	HSEM_IPXACT_HSEM_C2ISR_ISF_Pos = 0x0
	// Bit mask of ISF field.
	HSEM_IPXACT_HSEM_C2ISR_ISF_Msk = 0xffffffff

	// HSEM_C2MISR: HSEM i2terrupt status register
	// Position of MISF field.
	HSEM_IPXACT_HSEM_C2MISR_MISF_Pos = 0x0
	// Bit mask of MISF field.
	HSEM_IPXACT_HSEM_C2MISR_MISF_Msk = 0xffffffff

	// HSEM_CR: Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
	// Position of COREID field.
	HSEM_IPXACT_HSEM_CR_COREID_Pos = 0x8
	// Bit mask of COREID field.
	HSEM_IPXACT_HSEM_CR_COREID_Msk = 0xf00
	// Position of KEY field.
	HSEM_IPXACT_HSEM_CR_KEY_Pos = 0x10
	// Bit mask of KEY field.
	HSEM_IPXACT_HSEM_CR_KEY_Msk = 0xffff0000

	// HSEM_KEYR: HSEM interrupt clear register
	// Position of KEY field.
	HSEM_IPXACT_HSEM_KEYR_KEY_Pos = 0x10
	// Bit mask of KEY field.
	HSEM_IPXACT_HSEM_KEYR_KEY_Msk = 0xffff0000

	// HSEM_HWCFGR2: HSEM hardware configuration register 2
	// Position of MASTERID1 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID1_Pos = 0x0
	// Bit mask of MASTERID1 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID1_Msk = 0xf
	// Position of MASTERID2 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID2_Pos = 0x4
	// Bit mask of MASTERID2 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID2_Msk = 0xf0
	// Position of MASTERID3 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID3_Pos = 0x8
	// Bit mask of MASTERID3 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID3_Msk = 0xf00
	// Position of MASTERID4 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID4_Pos = 0xc
	// Bit mask of MASTERID4 field.
	HSEM_IPXACT_HSEM_HWCFGR2_MASTERID4_Msk = 0xf000

	// HSEM_HWCFGR1: HSEM hardware configuration register 1
	// Position of NBSEM field.
	HSEM_IPXACT_HSEM_HWCFGR1_NBSEM_Pos = 0x0
	// Bit mask of NBSEM field.
	HSEM_IPXACT_HSEM_HWCFGR1_NBSEM_Msk = 0xff
	// Position of NBINT field.
	HSEM_IPXACT_HSEM_HWCFGR1_NBINT_Pos = 0x8
	// Bit mask of NBINT field.
	HSEM_IPXACT_HSEM_HWCFGR1_NBINT_Msk = 0xf00

	// HSEM_VERR: HSEM IP version register
	// Position of MINREV field.
	HSEM_IPXACT_HSEM_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	HSEM_IPXACT_HSEM_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	HSEM_IPXACT_HSEM_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	HSEM_IPXACT_HSEM_VERR_MAJREV_Msk = 0xf0

	// HSEM_IPIDR: HSEM IP identification register
	// Position of IPID field.
	HSEM_IPXACT_HSEM_IPIDR_IPID_Pos = 0x0
	// Bit mask of IPID field.
	HSEM_IPXACT_HSEM_IPIDR_IPID_Msk = 0xffffffff

	// HSEM_SIDR: HSEM size identification register
	// Position of SID field.
	HSEM_IPXACT_HSEM_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	HSEM_IPXACT_HSEM_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for I2C1: I2C1
const (
	// I2C_CR1: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.
	// Position of PE field.
	I2C2_IPXACT_I2C_CR1_PE_Pos = 0x0
	// Bit mask of PE field.
	I2C2_IPXACT_I2C_CR1_PE_Msk = 0x1
	// Bit PE.
	I2C2_IPXACT_I2C_CR1_PE = 0x1
	// Position of TXIE field.
	I2C2_IPXACT_I2C_CR1_TXIE_Pos = 0x1
	// Bit mask of TXIE field.
	I2C2_IPXACT_I2C_CR1_TXIE_Msk = 0x2
	// Bit TXIE.
	I2C2_IPXACT_I2C_CR1_TXIE = 0x2
	// Position of RXIE field.
	I2C2_IPXACT_I2C_CR1_RXIE_Pos = 0x2
	// Bit mask of RXIE field.
	I2C2_IPXACT_I2C_CR1_RXIE_Msk = 0x4
	// Bit RXIE.
	I2C2_IPXACT_I2C_CR1_RXIE = 0x4
	// Position of ADDRIE field.
	I2C2_IPXACT_I2C_CR1_ADDRIE_Pos = 0x3
	// Bit mask of ADDRIE field.
	I2C2_IPXACT_I2C_CR1_ADDRIE_Msk = 0x8
	// Bit ADDRIE.
	I2C2_IPXACT_I2C_CR1_ADDRIE = 0x8
	// Position of NACKIE field.
	I2C2_IPXACT_I2C_CR1_NACKIE_Pos = 0x4
	// Bit mask of NACKIE field.
	I2C2_IPXACT_I2C_CR1_NACKIE_Msk = 0x10
	// Bit NACKIE.
	I2C2_IPXACT_I2C_CR1_NACKIE = 0x10
	// Position of STOPIE field.
	I2C2_IPXACT_I2C_CR1_STOPIE_Pos = 0x5
	// Bit mask of STOPIE field.
	I2C2_IPXACT_I2C_CR1_STOPIE_Msk = 0x20
	// Bit STOPIE.
	I2C2_IPXACT_I2C_CR1_STOPIE = 0x20
	// Position of TCIE field.
	I2C2_IPXACT_I2C_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	I2C2_IPXACT_I2C_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	I2C2_IPXACT_I2C_CR1_TCIE = 0x40
	// Position of ERRIE field.
	I2C2_IPXACT_I2C_CR1_ERRIE_Pos = 0x7
	// Bit mask of ERRIE field.
	I2C2_IPXACT_I2C_CR1_ERRIE_Msk = 0x80
	// Bit ERRIE.
	I2C2_IPXACT_I2C_CR1_ERRIE = 0x80
	// Position of DNF field.
	I2C2_IPXACT_I2C_CR1_DNF_Pos = 0x8
	// Bit mask of DNF field.
	I2C2_IPXACT_I2C_CR1_DNF_Msk = 0xf00
	// Position of ANFOFF field.
	I2C2_IPXACT_I2C_CR1_ANFOFF_Pos = 0xc
	// Bit mask of ANFOFF field.
	I2C2_IPXACT_I2C_CR1_ANFOFF_Msk = 0x1000
	// Bit ANFOFF.
	I2C2_IPXACT_I2C_CR1_ANFOFF = 0x1000
	// Position of TXDMAEN field.
	I2C2_IPXACT_I2C_CR1_TXDMAEN_Pos = 0xe
	// Bit mask of TXDMAEN field.
	I2C2_IPXACT_I2C_CR1_TXDMAEN_Msk = 0x4000
	// Bit TXDMAEN.
	I2C2_IPXACT_I2C_CR1_TXDMAEN = 0x4000
	// Position of RXDMAEN field.
	I2C2_IPXACT_I2C_CR1_RXDMAEN_Pos = 0xf
	// Bit mask of RXDMAEN field.
	I2C2_IPXACT_I2C_CR1_RXDMAEN_Msk = 0x8000
	// Bit RXDMAEN.
	I2C2_IPXACT_I2C_CR1_RXDMAEN = 0x8000
	// Position of SBC field.
	I2C2_IPXACT_I2C_CR1_SBC_Pos = 0x10
	// Bit mask of SBC field.
	I2C2_IPXACT_I2C_CR1_SBC_Msk = 0x10000
	// Bit SBC.
	I2C2_IPXACT_I2C_CR1_SBC = 0x10000
	// Position of NOSTRETCH field.
	I2C2_IPXACT_I2C_CR1_NOSTRETCH_Pos = 0x11
	// Bit mask of NOSTRETCH field.
	I2C2_IPXACT_I2C_CR1_NOSTRETCH_Msk = 0x20000
	// Bit NOSTRETCH.
	I2C2_IPXACT_I2C_CR1_NOSTRETCH = 0x20000
	// Position of WUPEN field.
	I2C2_IPXACT_I2C_CR1_WUPEN_Pos = 0x12
	// Bit mask of WUPEN field.
	I2C2_IPXACT_I2C_CR1_WUPEN_Msk = 0x40000
	// Bit WUPEN.
	I2C2_IPXACT_I2C_CR1_WUPEN = 0x40000
	// Position of GCEN field.
	I2C2_IPXACT_I2C_CR1_GCEN_Pos = 0x13
	// Bit mask of GCEN field.
	I2C2_IPXACT_I2C_CR1_GCEN_Msk = 0x80000
	// Bit GCEN.
	I2C2_IPXACT_I2C_CR1_GCEN = 0x80000
	// Position of SMBHEN field.
	I2C2_IPXACT_I2C_CR1_SMBHEN_Pos = 0x14
	// Bit mask of SMBHEN field.
	I2C2_IPXACT_I2C_CR1_SMBHEN_Msk = 0x100000
	// Bit SMBHEN.
	I2C2_IPXACT_I2C_CR1_SMBHEN = 0x100000
	// Position of SMBDEN field.
	I2C2_IPXACT_I2C_CR1_SMBDEN_Pos = 0x15
	// Bit mask of SMBDEN field.
	I2C2_IPXACT_I2C_CR1_SMBDEN_Msk = 0x200000
	// Bit SMBDEN.
	I2C2_IPXACT_I2C_CR1_SMBDEN = 0x200000
	// Position of ALERTEN field.
	I2C2_IPXACT_I2C_CR1_ALERTEN_Pos = 0x16
	// Bit mask of ALERTEN field.
	I2C2_IPXACT_I2C_CR1_ALERTEN_Msk = 0x400000
	// Bit ALERTEN.
	I2C2_IPXACT_I2C_CR1_ALERTEN = 0x400000
	// Position of PECEN field.
	I2C2_IPXACT_I2C_CR1_PECEN_Pos = 0x17
	// Bit mask of PECEN field.
	I2C2_IPXACT_I2C_CR1_PECEN_Msk = 0x800000
	// Bit PECEN.
	I2C2_IPXACT_I2C_CR1_PECEN = 0x800000

	// I2C_CR2: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
	// Position of SADD field.
	I2C2_IPXACT_I2C_CR2_SADD_Pos = 0x0
	// Bit mask of SADD field.
	I2C2_IPXACT_I2C_CR2_SADD_Msk = 0x3ff
	// Position of RD_WRN field.
	I2C2_IPXACT_I2C_CR2_RD_WRN_Pos = 0xa
	// Bit mask of RD_WRN field.
	I2C2_IPXACT_I2C_CR2_RD_WRN_Msk = 0x400
	// Bit RD_WRN.
	I2C2_IPXACT_I2C_CR2_RD_WRN = 0x400
	// Position of ADD10 field.
	I2C2_IPXACT_I2C_CR2_ADD10_Pos = 0xb
	// Bit mask of ADD10 field.
	I2C2_IPXACT_I2C_CR2_ADD10_Msk = 0x800
	// Bit ADD10.
	I2C2_IPXACT_I2C_CR2_ADD10 = 0x800
	// Position of HEAD10R field.
	I2C2_IPXACT_I2C_CR2_HEAD10R_Pos = 0xc
	// Bit mask of HEAD10R field.
	I2C2_IPXACT_I2C_CR2_HEAD10R_Msk = 0x1000
	// Bit HEAD10R.
	I2C2_IPXACT_I2C_CR2_HEAD10R = 0x1000
	// Position of START field.
	I2C2_IPXACT_I2C_CR2_START_Pos = 0xd
	// Bit mask of START field.
	I2C2_IPXACT_I2C_CR2_START_Msk = 0x2000
	// Bit START.
	I2C2_IPXACT_I2C_CR2_START = 0x2000
	// Position of STOP field.
	I2C2_IPXACT_I2C_CR2_STOP_Pos = 0xe
	// Bit mask of STOP field.
	I2C2_IPXACT_I2C_CR2_STOP_Msk = 0x4000
	// Bit STOP.
	I2C2_IPXACT_I2C_CR2_STOP = 0x4000
	// Position of NACK field.
	I2C2_IPXACT_I2C_CR2_NACK_Pos = 0xf
	// Bit mask of NACK field.
	I2C2_IPXACT_I2C_CR2_NACK_Msk = 0x8000
	// Bit NACK.
	I2C2_IPXACT_I2C_CR2_NACK = 0x8000
	// Position of NBYTES field.
	I2C2_IPXACT_I2C_CR2_NBYTES_Pos = 0x10
	// Bit mask of NBYTES field.
	I2C2_IPXACT_I2C_CR2_NBYTES_Msk = 0xff0000
	// Position of RELOAD field.
	I2C2_IPXACT_I2C_CR2_RELOAD_Pos = 0x18
	// Bit mask of RELOAD field.
	I2C2_IPXACT_I2C_CR2_RELOAD_Msk = 0x1000000
	// Bit RELOAD.
	I2C2_IPXACT_I2C_CR2_RELOAD = 0x1000000
	// Position of AUTOEND field.
	I2C2_IPXACT_I2C_CR2_AUTOEND_Pos = 0x19
	// Bit mask of AUTOEND field.
	I2C2_IPXACT_I2C_CR2_AUTOEND_Msk = 0x2000000
	// Bit AUTOEND.
	I2C2_IPXACT_I2C_CR2_AUTOEND = 0x2000000
	// Position of PECBYTE field.
	I2C2_IPXACT_I2C_CR2_PECBYTE_Pos = 0x1a
	// Bit mask of PECBYTE field.
	I2C2_IPXACT_I2C_CR2_PECBYTE_Msk = 0x4000000
	// Bit PECBYTE.
	I2C2_IPXACT_I2C_CR2_PECBYTE = 0x4000000

	// I2C_OAR1: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
	// Position of OA1 field.
	I2C2_IPXACT_I2C_OAR1_OA1_Pos = 0x0
	// Bit mask of OA1 field.
	I2C2_IPXACT_I2C_OAR1_OA1_Msk = 0x3ff
	// Position of OA1MODE field.
	I2C2_IPXACT_I2C_OAR1_OA1MODE_Pos = 0xa
	// Bit mask of OA1MODE field.
	I2C2_IPXACT_I2C_OAR1_OA1MODE_Msk = 0x400
	// Bit OA1MODE.
	I2C2_IPXACT_I2C_OAR1_OA1MODE = 0x400
	// Position of OA1EN field.
	I2C2_IPXACT_I2C_OAR1_OA1EN_Pos = 0xf
	// Bit mask of OA1EN field.
	I2C2_IPXACT_I2C_OAR1_OA1EN_Msk = 0x8000
	// Bit OA1EN.
	I2C2_IPXACT_I2C_OAR1_OA1EN = 0x8000

	// I2C_OAR2: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
	// Position of OA2 field.
	I2C2_IPXACT_I2C_OAR2_OA2_Pos = 0x1
	// Bit mask of OA2 field.
	I2C2_IPXACT_I2C_OAR2_OA2_Msk = 0xfe
	// Position of OA2MSK field.
	I2C2_IPXACT_I2C_OAR2_OA2MSK_Pos = 0x8
	// Bit mask of OA2MSK field.
	I2C2_IPXACT_I2C_OAR2_OA2MSK_Msk = 0x700
	// Position of OA2EN field.
	I2C2_IPXACT_I2C_OAR2_OA2EN_Pos = 0xf
	// Bit mask of OA2EN field.
	I2C2_IPXACT_I2C_OAR2_OA2EN_Msk = 0x8000
	// Bit OA2EN.
	I2C2_IPXACT_I2C_OAR2_OA2EN = 0x8000

	// I2C_TIMINGR: Access: No wait states
	// Position of SCLL field.
	I2C2_IPXACT_I2C_TIMINGR_SCLL_Pos = 0x0
	// Bit mask of SCLL field.
	I2C2_IPXACT_I2C_TIMINGR_SCLL_Msk = 0xff
	// Position of SCLH field.
	I2C2_IPXACT_I2C_TIMINGR_SCLH_Pos = 0x8
	// Bit mask of SCLH field.
	I2C2_IPXACT_I2C_TIMINGR_SCLH_Msk = 0xff00
	// Position of SDADEL field.
	I2C2_IPXACT_I2C_TIMINGR_SDADEL_Pos = 0x10
	// Bit mask of SDADEL field.
	I2C2_IPXACT_I2C_TIMINGR_SDADEL_Msk = 0xf0000
	// Position of SCLDEL field.
	I2C2_IPXACT_I2C_TIMINGR_SCLDEL_Pos = 0x14
	// Bit mask of SCLDEL field.
	I2C2_IPXACT_I2C_TIMINGR_SCLDEL_Msk = 0xf00000
	// Position of PRESC field.
	I2C2_IPXACT_I2C_TIMINGR_PRESC_Pos = 0x1c
	// Bit mask of PRESC field.
	I2C2_IPXACT_I2C_TIMINGR_PRESC_Msk = 0xf0000000

	// I2C_TIMEOUTR: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
	// Position of TIMEOUTA field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0
	// Bit mask of TIMEOUTA field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff
	// Position of TIDLE field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIDLE_Pos = 0xc
	// Bit mask of TIDLE field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIDLE_Msk = 0x1000
	// Bit TIDLE.
	I2C2_IPXACT_I2C_TIMEOUTR_TIDLE = 0x1000
	// Position of TIMOUTEN field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf
	// Bit mask of TIMOUTEN field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000
	// Bit TIMOUTEN.
	I2C2_IPXACT_I2C_TIMEOUTR_TIMOUTEN = 0x8000
	// Position of TIMEOUTB field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10
	// Bit mask of TIMEOUTB field.
	I2C2_IPXACT_I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000
	// Position of TEXTEN field.
	I2C2_IPXACT_I2C_TIMEOUTR_TEXTEN_Pos = 0x1f
	// Bit mask of TEXTEN field.
	I2C2_IPXACT_I2C_TIMEOUTR_TEXTEN_Msk = 0x80000000
	// Bit TEXTEN.
	I2C2_IPXACT_I2C_TIMEOUTR_TEXTEN = 0x80000000

	// I2C_ISR: Access: No wait states
	// Position of TXE field.
	I2C2_IPXACT_I2C_ISR_TXE_Pos = 0x0
	// Bit mask of TXE field.
	I2C2_IPXACT_I2C_ISR_TXE_Msk = 0x1
	// Bit TXE.
	I2C2_IPXACT_I2C_ISR_TXE = 0x1
	// Position of TXIS field.
	I2C2_IPXACT_I2C_ISR_TXIS_Pos = 0x1
	// Bit mask of TXIS field.
	I2C2_IPXACT_I2C_ISR_TXIS_Msk = 0x2
	// Bit TXIS.
	I2C2_IPXACT_I2C_ISR_TXIS = 0x2
	// Position of RXNE field.
	I2C2_IPXACT_I2C_ISR_RXNE_Pos = 0x2
	// Bit mask of RXNE field.
	I2C2_IPXACT_I2C_ISR_RXNE_Msk = 0x4
	// Bit RXNE.
	I2C2_IPXACT_I2C_ISR_RXNE = 0x4
	// Position of ADDR field.
	I2C2_IPXACT_I2C_ISR_ADDR_Pos = 0x3
	// Bit mask of ADDR field.
	I2C2_IPXACT_I2C_ISR_ADDR_Msk = 0x8
	// Bit ADDR.
	I2C2_IPXACT_I2C_ISR_ADDR = 0x8
	// Position of NACKF field.
	I2C2_IPXACT_I2C_ISR_NACKF_Pos = 0x4
	// Bit mask of NACKF field.
	I2C2_IPXACT_I2C_ISR_NACKF_Msk = 0x10
	// Bit NACKF.
	I2C2_IPXACT_I2C_ISR_NACKF = 0x10
	// Position of STOPF field.
	I2C2_IPXACT_I2C_ISR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	I2C2_IPXACT_I2C_ISR_STOPF_Msk = 0x20
	// Bit STOPF.
	I2C2_IPXACT_I2C_ISR_STOPF = 0x20
	// Position of TC field.
	I2C2_IPXACT_I2C_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	I2C2_IPXACT_I2C_ISR_TC_Msk = 0x40
	// Bit TC.
	I2C2_IPXACT_I2C_ISR_TC = 0x40
	// Position of TCR field.
	I2C2_IPXACT_I2C_ISR_TCR_Pos = 0x7
	// Bit mask of TCR field.
	I2C2_IPXACT_I2C_ISR_TCR_Msk = 0x80
	// Bit TCR.
	I2C2_IPXACT_I2C_ISR_TCR = 0x80
	// Position of BERR field.
	I2C2_IPXACT_I2C_ISR_BERR_Pos = 0x8
	// Bit mask of BERR field.
	I2C2_IPXACT_I2C_ISR_BERR_Msk = 0x100
	// Bit BERR.
	I2C2_IPXACT_I2C_ISR_BERR = 0x100
	// Position of ARLO field.
	I2C2_IPXACT_I2C_ISR_ARLO_Pos = 0x9
	// Bit mask of ARLO field.
	I2C2_IPXACT_I2C_ISR_ARLO_Msk = 0x200
	// Bit ARLO.
	I2C2_IPXACT_I2C_ISR_ARLO = 0x200
	// Position of OVR field.
	I2C2_IPXACT_I2C_ISR_OVR_Pos = 0xa
	// Bit mask of OVR field.
	I2C2_IPXACT_I2C_ISR_OVR_Msk = 0x400
	// Bit OVR.
	I2C2_IPXACT_I2C_ISR_OVR = 0x400
	// Position of PECERR field.
	I2C2_IPXACT_I2C_ISR_PECERR_Pos = 0xb
	// Bit mask of PECERR field.
	I2C2_IPXACT_I2C_ISR_PECERR_Msk = 0x800
	// Bit PECERR.
	I2C2_IPXACT_I2C_ISR_PECERR = 0x800
	// Position of TIMEOUT field.
	I2C2_IPXACT_I2C_ISR_TIMEOUT_Pos = 0xc
	// Bit mask of TIMEOUT field.
	I2C2_IPXACT_I2C_ISR_TIMEOUT_Msk = 0x1000
	// Bit TIMEOUT.
	I2C2_IPXACT_I2C_ISR_TIMEOUT = 0x1000
	// Position of ALERT field.
	I2C2_IPXACT_I2C_ISR_ALERT_Pos = 0xd
	// Bit mask of ALERT field.
	I2C2_IPXACT_I2C_ISR_ALERT_Msk = 0x2000
	// Bit ALERT.
	I2C2_IPXACT_I2C_ISR_ALERT = 0x2000
	// Position of BUSY field.
	I2C2_IPXACT_I2C_ISR_BUSY_Pos = 0xf
	// Bit mask of BUSY field.
	I2C2_IPXACT_I2C_ISR_BUSY_Msk = 0x8000
	// Bit BUSY.
	I2C2_IPXACT_I2C_ISR_BUSY = 0x8000
	// Position of DIR field.
	I2C2_IPXACT_I2C_ISR_DIR_Pos = 0x10
	// Bit mask of DIR field.
	I2C2_IPXACT_I2C_ISR_DIR_Msk = 0x10000
	// Bit DIR.
	I2C2_IPXACT_I2C_ISR_DIR = 0x10000
	// Position of ADDCODE field.
	I2C2_IPXACT_I2C_ISR_ADDCODE_Pos = 0x11
	// Bit mask of ADDCODE field.
	I2C2_IPXACT_I2C_ISR_ADDCODE_Msk = 0xfe0000

	// I2C_ICR: Access: No wait states
	// Position of ADDRCF field.
	I2C2_IPXACT_I2C_ICR_ADDRCF_Pos = 0x3
	// Bit mask of ADDRCF field.
	I2C2_IPXACT_I2C_ICR_ADDRCF_Msk = 0x8
	// Bit ADDRCF.
	I2C2_IPXACT_I2C_ICR_ADDRCF = 0x8
	// Position of NACKCF field.
	I2C2_IPXACT_I2C_ICR_NACKCF_Pos = 0x4
	// Bit mask of NACKCF field.
	I2C2_IPXACT_I2C_ICR_NACKCF_Msk = 0x10
	// Bit NACKCF.
	I2C2_IPXACT_I2C_ICR_NACKCF = 0x10
	// Position of STOPCF field.
	I2C2_IPXACT_I2C_ICR_STOPCF_Pos = 0x5
	// Bit mask of STOPCF field.
	I2C2_IPXACT_I2C_ICR_STOPCF_Msk = 0x20
	// Bit STOPCF.
	I2C2_IPXACT_I2C_ICR_STOPCF = 0x20
	// Position of BERRCF field.
	I2C2_IPXACT_I2C_ICR_BERRCF_Pos = 0x8
	// Bit mask of BERRCF field.
	I2C2_IPXACT_I2C_ICR_BERRCF_Msk = 0x100
	// Bit BERRCF.
	I2C2_IPXACT_I2C_ICR_BERRCF = 0x100
	// Position of ARLOCF field.
	I2C2_IPXACT_I2C_ICR_ARLOCF_Pos = 0x9
	// Bit mask of ARLOCF field.
	I2C2_IPXACT_I2C_ICR_ARLOCF_Msk = 0x200
	// Bit ARLOCF.
	I2C2_IPXACT_I2C_ICR_ARLOCF = 0x200
	// Position of OVRCF field.
	I2C2_IPXACT_I2C_ICR_OVRCF_Pos = 0xa
	// Bit mask of OVRCF field.
	I2C2_IPXACT_I2C_ICR_OVRCF_Msk = 0x400
	// Bit OVRCF.
	I2C2_IPXACT_I2C_ICR_OVRCF = 0x400
	// Position of PECCF field.
	I2C2_IPXACT_I2C_ICR_PECCF_Pos = 0xb
	// Bit mask of PECCF field.
	I2C2_IPXACT_I2C_ICR_PECCF_Msk = 0x800
	// Bit PECCF.
	I2C2_IPXACT_I2C_ICR_PECCF = 0x800
	// Position of TIMOUTCF field.
	I2C2_IPXACT_I2C_ICR_TIMOUTCF_Pos = 0xc
	// Bit mask of TIMOUTCF field.
	I2C2_IPXACT_I2C_ICR_TIMOUTCF_Msk = 0x1000
	// Bit TIMOUTCF.
	I2C2_IPXACT_I2C_ICR_TIMOUTCF = 0x1000
	// Position of ALERTCF field.
	I2C2_IPXACT_I2C_ICR_ALERTCF_Pos = 0xd
	// Bit mask of ALERTCF field.
	I2C2_IPXACT_I2C_ICR_ALERTCF_Msk = 0x2000
	// Bit ALERTCF.
	I2C2_IPXACT_I2C_ICR_ALERTCF = 0x2000

	// I2C_PECR: Access: No wait states
	// Position of PEC field.
	I2C2_IPXACT_I2C_PECR_PEC_Pos = 0x0
	// Bit mask of PEC field.
	I2C2_IPXACT_I2C_PECR_PEC_Msk = 0xff

	// I2C_RXDR: Access: No wait states
	// Position of RXDATA field.
	I2C2_IPXACT_I2C_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	I2C2_IPXACT_I2C_RXDR_RXDATA_Msk = 0xff

	// I2C_TXDR: Access: No wait states
	// Position of TXDATA field.
	I2C2_IPXACT_I2C_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	I2C2_IPXACT_I2C_TXDR_TXDATA_Msk = 0xff

	// I2C_HWCFGR: I2C hardware configuration register
	// Position of SMBUS field.
	I2C2_IPXACT_I2C_HWCFGR_SMBUS_Pos = 0x0
	// Bit mask of SMBUS field.
	I2C2_IPXACT_I2C_HWCFGR_SMBUS_Msk = 0xf
	// Position of ASYN field.
	I2C2_IPXACT_I2C_HWCFGR_ASYN_Pos = 0x4
	// Bit mask of ASYN field.
	I2C2_IPXACT_I2C_HWCFGR_ASYN_Msk = 0xf0
	// Position of WKP field.
	I2C2_IPXACT_I2C_HWCFGR_WKP_Pos = 0x8
	// Bit mask of WKP field.
	I2C2_IPXACT_I2C_HWCFGR_WKP_Msk = 0xf00

	// I2C_VERR: I2C version register
	// Position of MINREV field.
	I2C2_IPXACT_I2C_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	I2C2_IPXACT_I2C_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	I2C2_IPXACT_I2C_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	I2C2_IPXACT_I2C_VERR_MAJREV_Msk = 0xf0

	// I2C_IPIDR: I2C identification register
	// Position of ID field.
	I2C2_IPXACT_I2C_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	I2C2_IPXACT_I2C_IPIDR_ID_Msk = 0xffffffff

	// I2C_SIDR: I2C size identification register
	// Position of SID field.
	I2C2_IPXACT_I2C_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	I2C2_IPXACT_I2C_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for IPCC: IPCC
const (
	// IPCC_C1CR: IPCC Processor 1 control register
	// Position of RXOIE field.
	IPCC_IPCC_C1CR_RXOIE_Pos = 0x0
	// Bit mask of RXOIE field.
	IPCC_IPCC_C1CR_RXOIE_Msk = 0x1
	// Bit RXOIE.
	IPCC_IPCC_C1CR_RXOIE = 0x1
	// Position of TXFIE field.
	IPCC_IPCC_C1CR_TXFIE_Pos = 0x10
	// Bit mask of TXFIE field.
	IPCC_IPCC_C1CR_TXFIE_Msk = 0x10000
	// Bit TXFIE.
	IPCC_IPCC_C1CR_TXFIE = 0x10000

	// IPCC_C1MR: IPCC Processor 1 mask register
	// Position of CHxOM field.
	IPCC_IPCC_C1MR_CHxOM_Pos = 0x0
	// Bit mask of CHxOM field.
	IPCC_IPCC_C1MR_CHxOM_Msk = 0x3f
	// Position of CHxFM field.
	IPCC_IPCC_C1MR_CHxFM_Pos = 0x10
	// Bit mask of CHxFM field.
	IPCC_IPCC_C1MR_CHxFM_Msk = 0x3f0000

	// IPCC_C1SCR: Reading this register will always return 0x0000 0000.
	// Position of CHxC field.
	IPCC_IPCC_C1SCR_CHxC_Pos = 0x0
	// Bit mask of CHxC field.
	IPCC_IPCC_C1SCR_CHxC_Msk = 0x3f
	// Position of CHxS field.
	IPCC_IPCC_C1SCR_CHxS_Pos = 0x10
	// Bit mask of CHxS field.
	IPCC_IPCC_C1SCR_CHxS_Msk = 0x3f0000

	// IPCC_C1TOC2SR: IPCC processor 1 to processor 2 status register
	// Position of CHxF field.
	IPCC_IPCC_C1TOC2SR_CHxF_Pos = 0x0
	// Bit mask of CHxF field.
	IPCC_IPCC_C1TOC2SR_CHxF_Msk = 0x3f

	// IPCC_C2CR: IPCC Processor 2 control register
	// Position of RXOIE field.
	IPCC_IPCC_C2CR_RXOIE_Pos = 0x0
	// Bit mask of RXOIE field.
	IPCC_IPCC_C2CR_RXOIE_Msk = 0x1
	// Bit RXOIE.
	IPCC_IPCC_C2CR_RXOIE = 0x1
	// Position of TXFIE field.
	IPCC_IPCC_C2CR_TXFIE_Pos = 0x10
	// Bit mask of TXFIE field.
	IPCC_IPCC_C2CR_TXFIE_Msk = 0x10000
	// Bit TXFIE.
	IPCC_IPCC_C2CR_TXFIE = 0x10000

	// IPCC_C2MR: IPCC Processor 2 mask register
	// Position of CHxOM field.
	IPCC_IPCC_C2MR_CHxOM_Pos = 0x0
	// Bit mask of CHxOM field.
	IPCC_IPCC_C2MR_CHxOM_Msk = 0x3f
	// Position of CHxFM field.
	IPCC_IPCC_C2MR_CHxFM_Pos = 0x10
	// Bit mask of CHxFM field.
	IPCC_IPCC_C2MR_CHxFM_Msk = 0x3f0000

	// IPCC_C2SCR: Reading this register will always return 0x0000 0000.
	// Position of CHxC field.
	IPCC_IPCC_C2SCR_CHxC_Pos = 0x0
	// Bit mask of CHxC field.
	IPCC_IPCC_C2SCR_CHxC_Msk = 0x3f
	// Position of CHxS field.
	IPCC_IPCC_C2SCR_CHxS_Pos = 0x10
	// Bit mask of CHxS field.
	IPCC_IPCC_C2SCR_CHxS_Msk = 0x3f0000

	// IPCC_C2TOC1SR: IPCC processor 2 to processor 1 status register
	// Position of CHxF field.
	IPCC_IPCC_C2TOC1SR_CHxF_Pos = 0x0
	// Bit mask of CHxF field.
	IPCC_IPCC_C2TOC1SR_CHxF_Msk = 0x3f

	// IPCC_HWCFGR: IPCC Hardware configuration register
	// Position of CHANNELS field.
	IPCC_IPCC_HWCFGR_CHANNELS_Pos = 0x0
	// Bit mask of CHANNELS field.
	IPCC_IPCC_HWCFGR_CHANNELS_Msk = 0xff

	// IPCC_VER: IPCC IP Version register
	// Position of MINREV field.
	IPCC_IPCC_VER_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	IPCC_IPCC_VER_MINREV_Msk = 0xf
	// Position of MAJREV field.
	IPCC_IPCC_VER_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	IPCC_IPCC_VER_MAJREV_Msk = 0xf0

	// IPCC_ID: IPCC IP Identification register
	// Position of IPID field.
	IPCC_IPCC_ID_IPID_Pos = 0x0
	// Bit mask of IPID field.
	IPCC_IPCC_ID_IPID_Msk = 0xffffffff

	// IPCC_SID: IPCC Size ID register
	// Position of SID field.
	IPCC_IPCC_SID_SID_Pos = 0x0
	// Bit mask of SID field.
	IPCC_IPCC_SID_SID_Msk = 0xffffffff
)

// Bitfields for IWDG1: IWDG1
const (
	// IWDG_KR: Key register
	// Position of KEY field.
	IWDG1_IWDG_KR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	IWDG1_IWDG_KR_KEY_Msk = 0xffff

	// IWDG_PR: Prescaler register
	// Position of PR field.
	IWDG1_IWDG_PR_PR_Pos = 0x0
	// Bit mask of PR field.
	IWDG1_IWDG_PR_PR_Msk = 0x7

	// IWDG_RLR: Reload register
	// Position of RL field.
	IWDG1_IWDG_RLR_RL_Pos = 0x0
	// Bit mask of RL field.
	IWDG1_IWDG_RLR_RL_Msk = 0xfff

	// IWDG_SR: Status register
	// Position of PVU field.
	IWDG1_IWDG_SR_PVU_Pos = 0x0
	// Bit mask of PVU field.
	IWDG1_IWDG_SR_PVU_Msk = 0x1
	// Bit PVU.
	IWDG1_IWDG_SR_PVU = 0x1
	// Position of RVU field.
	IWDG1_IWDG_SR_RVU_Pos = 0x1
	// Bit mask of RVU field.
	IWDG1_IWDG_SR_RVU_Msk = 0x2
	// Bit RVU.
	IWDG1_IWDG_SR_RVU = 0x2
	// Position of WVU field.
	IWDG1_IWDG_SR_WVU_Pos = 0x2
	// Bit mask of WVU field.
	IWDG1_IWDG_SR_WVU_Msk = 0x4
	// Bit WVU.
	IWDG1_IWDG_SR_WVU = 0x4

	// IWDG_WINR: Window register
	// Position of WIN field.
	IWDG1_IWDG_WINR_WIN_Pos = 0x0
	// Bit mask of WIN field.
	IWDG1_IWDG_WINR_WIN_Msk = 0xfff

	// IWDG_HWCFGR: IWDG hardware configuration register
	// Position of WINDOW field.
	IWDG1_IWDG_HWCFGR_WINDOW_Pos = 0x0
	// Bit mask of WINDOW field.
	IWDG1_IWDG_HWCFGR_WINDOW_Msk = 0xf
	// Position of PR_DEFAULT field.
	IWDG1_IWDG_HWCFGR_PR_DEFAULT_Pos = 0x4
	// Bit mask of PR_DEFAULT field.
	IWDG1_IWDG_HWCFGR_PR_DEFAULT_Msk = 0xf0

	// IWDG_VERR: IWDG version register
	// Position of MINREV field.
	IWDG1_IWDG_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	IWDG1_IWDG_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	IWDG1_IWDG_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	IWDG1_IWDG_VERR_MAJREV_Msk = 0xf0

	// IWDG_IDR: IWDG identification register
	// Position of ID field.
	IWDG1_IWDG_IDR_ID_Pos = 0x0
	// Bit mask of ID field.
	IWDG1_IWDG_IDR_ID_Msk = 0xffffffff

	// IWDG_SIDR: IWDG size identification register
	// Position of SID field.
	IWDG1_IWDG_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	IWDG1_IWDG_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for LPTIM1: LPTIM1
const (
	// LPTIM_ISR: LPTIM interrupt and status register
	// Position of CMPM field.
	LPTIM1_LPTIM_ISR_CMPM_Pos = 0x0
	// Bit mask of CMPM field.
	LPTIM1_LPTIM_ISR_CMPM_Msk = 0x1
	// Bit CMPM.
	LPTIM1_LPTIM_ISR_CMPM = 0x1
	// Position of ARRM field.
	LPTIM1_LPTIM_ISR_ARRM_Pos = 0x1
	// Bit mask of ARRM field.
	LPTIM1_LPTIM_ISR_ARRM_Msk = 0x2
	// Bit ARRM.
	LPTIM1_LPTIM_ISR_ARRM = 0x2
	// Position of EXTTRIG field.
	LPTIM1_LPTIM_ISR_EXTTRIG_Pos = 0x2
	// Bit mask of EXTTRIG field.
	LPTIM1_LPTIM_ISR_EXTTRIG_Msk = 0x4
	// Bit EXTTRIG.
	LPTIM1_LPTIM_ISR_EXTTRIG = 0x4
	// Position of CMPOK field.
	LPTIM1_LPTIM_ISR_CMPOK_Pos = 0x3
	// Bit mask of CMPOK field.
	LPTIM1_LPTIM_ISR_CMPOK_Msk = 0x8
	// Bit CMPOK.
	LPTIM1_LPTIM_ISR_CMPOK = 0x8
	// Position of ARROK field.
	LPTIM1_LPTIM_ISR_ARROK_Pos = 0x4
	// Bit mask of ARROK field.
	LPTIM1_LPTIM_ISR_ARROK_Msk = 0x10
	// Bit ARROK.
	LPTIM1_LPTIM_ISR_ARROK = 0x10
	// Position of UP field.
	LPTIM1_LPTIM_ISR_UP_Pos = 0x5
	// Bit mask of UP field.
	LPTIM1_LPTIM_ISR_UP_Msk = 0x20
	// Bit UP.
	LPTIM1_LPTIM_ISR_UP = 0x20
	// Position of DOWN field.
	LPTIM1_LPTIM_ISR_DOWN_Pos = 0x6
	// Bit mask of DOWN field.
	LPTIM1_LPTIM_ISR_DOWN_Msk = 0x40
	// Bit DOWN.
	LPTIM1_LPTIM_ISR_DOWN = 0x40

	// LPTIM_ICR: LPTIM interrupt clear register
	// Position of CMPMCF field.
	LPTIM1_LPTIM_ICR_CMPMCF_Pos = 0x0
	// Bit mask of CMPMCF field.
	LPTIM1_LPTIM_ICR_CMPMCF_Msk = 0x1
	// Bit CMPMCF.
	LPTIM1_LPTIM_ICR_CMPMCF = 0x1
	// Position of ARRMCF field.
	LPTIM1_LPTIM_ICR_ARRMCF_Pos = 0x1
	// Bit mask of ARRMCF field.
	LPTIM1_LPTIM_ICR_ARRMCF_Msk = 0x2
	// Bit ARRMCF.
	LPTIM1_LPTIM_ICR_ARRMCF = 0x2
	// Position of EXTTRIGCF field.
	LPTIM1_LPTIM_ICR_EXTTRIGCF_Pos = 0x2
	// Bit mask of EXTTRIGCF field.
	LPTIM1_LPTIM_ICR_EXTTRIGCF_Msk = 0x4
	// Bit EXTTRIGCF.
	LPTIM1_LPTIM_ICR_EXTTRIGCF = 0x4
	// Position of CMPOKCF field.
	LPTIM1_LPTIM_ICR_CMPOKCF_Pos = 0x3
	// Bit mask of CMPOKCF field.
	LPTIM1_LPTIM_ICR_CMPOKCF_Msk = 0x8
	// Bit CMPOKCF.
	LPTIM1_LPTIM_ICR_CMPOKCF = 0x8
	// Position of ARROKCF field.
	LPTIM1_LPTIM_ICR_ARROKCF_Pos = 0x4
	// Bit mask of ARROKCF field.
	LPTIM1_LPTIM_ICR_ARROKCF_Msk = 0x10
	// Bit ARROKCF.
	LPTIM1_LPTIM_ICR_ARROKCF = 0x10
	// Position of UPCF field.
	LPTIM1_LPTIM_ICR_UPCF_Pos = 0x5
	// Bit mask of UPCF field.
	LPTIM1_LPTIM_ICR_UPCF_Msk = 0x20
	// Bit UPCF.
	LPTIM1_LPTIM_ICR_UPCF = 0x20
	// Position of DOWNCF field.
	LPTIM1_LPTIM_ICR_DOWNCF_Pos = 0x6
	// Bit mask of DOWNCF field.
	LPTIM1_LPTIM_ICR_DOWNCF_Msk = 0x40
	// Bit DOWNCF.
	LPTIM1_LPTIM_ICR_DOWNCF = 0x40

	// LPTIM_IER: LPTIM interrupt enable register
	// Position of CMPMIE field.
	LPTIM1_LPTIM_IER_CMPMIE_Pos = 0x0
	// Bit mask of CMPMIE field.
	LPTIM1_LPTIM_IER_CMPMIE_Msk = 0x1
	// Bit CMPMIE.
	LPTIM1_LPTIM_IER_CMPMIE = 0x1
	// Position of ARRMIE field.
	LPTIM1_LPTIM_IER_ARRMIE_Pos = 0x1
	// Bit mask of ARRMIE field.
	LPTIM1_LPTIM_IER_ARRMIE_Msk = 0x2
	// Bit ARRMIE.
	LPTIM1_LPTIM_IER_ARRMIE = 0x2
	// Position of EXTTRIGIE field.
	LPTIM1_LPTIM_IER_EXTTRIGIE_Pos = 0x2
	// Bit mask of EXTTRIGIE field.
	LPTIM1_LPTIM_IER_EXTTRIGIE_Msk = 0x4
	// Bit EXTTRIGIE.
	LPTIM1_LPTIM_IER_EXTTRIGIE = 0x4
	// Position of CMPOKIE field.
	LPTIM1_LPTIM_IER_CMPOKIE_Pos = 0x3
	// Bit mask of CMPOKIE field.
	LPTIM1_LPTIM_IER_CMPOKIE_Msk = 0x8
	// Bit CMPOKIE.
	LPTIM1_LPTIM_IER_CMPOKIE = 0x8
	// Position of ARROKIE field.
	LPTIM1_LPTIM_IER_ARROKIE_Pos = 0x4
	// Bit mask of ARROKIE field.
	LPTIM1_LPTIM_IER_ARROKIE_Msk = 0x10
	// Bit ARROKIE.
	LPTIM1_LPTIM_IER_ARROKIE = 0x10
	// Position of UPIE field.
	LPTIM1_LPTIM_IER_UPIE_Pos = 0x5
	// Bit mask of UPIE field.
	LPTIM1_LPTIM_IER_UPIE_Msk = 0x20
	// Bit UPIE.
	LPTIM1_LPTIM_IER_UPIE = 0x20
	// Position of DOWNIE field.
	LPTIM1_LPTIM_IER_DOWNIE_Pos = 0x6
	// Bit mask of DOWNIE field.
	LPTIM1_LPTIM_IER_DOWNIE_Msk = 0x40
	// Bit DOWNIE.
	LPTIM1_LPTIM_IER_DOWNIE = 0x40

	// LPTIM_CFGR: LPTIM configuration register
	// Position of CKSEL field.
	LPTIM1_LPTIM_CFGR_CKSEL_Pos = 0x0
	// Bit mask of CKSEL field.
	LPTIM1_LPTIM_CFGR_CKSEL_Msk = 0x1
	// Bit CKSEL.
	LPTIM1_LPTIM_CFGR_CKSEL = 0x1
	// Position of CKPOL field.
	LPTIM1_LPTIM_CFGR_CKPOL_Pos = 0x1
	// Bit mask of CKPOL field.
	LPTIM1_LPTIM_CFGR_CKPOL_Msk = 0x6
	// Position of CKFLT field.
	LPTIM1_LPTIM_CFGR_CKFLT_Pos = 0x3
	// Bit mask of CKFLT field.
	LPTIM1_LPTIM_CFGR_CKFLT_Msk = 0x18
	// Position of TRGFLT field.
	LPTIM1_LPTIM_CFGR_TRGFLT_Pos = 0x6
	// Bit mask of TRGFLT field.
	LPTIM1_LPTIM_CFGR_TRGFLT_Msk = 0xc0
	// Position of PRESC field.
	LPTIM1_LPTIM_CFGR_PRESC_Pos = 0x9
	// Bit mask of PRESC field.
	LPTIM1_LPTIM_CFGR_PRESC_Msk = 0xe00
	// Position of TRIGSEL field.
	LPTIM1_LPTIM_CFGR_TRIGSEL_Pos = 0xd
	// Bit mask of TRIGSEL field.
	LPTIM1_LPTIM_CFGR_TRIGSEL_Msk = 0xe000
	// Position of TRIGEN field.
	LPTIM1_LPTIM_CFGR_TRIGEN_Pos = 0x11
	// Bit mask of TRIGEN field.
	LPTIM1_LPTIM_CFGR_TRIGEN_Msk = 0x60000
	// Position of TIMOUT field.
	LPTIM1_LPTIM_CFGR_TIMOUT_Pos = 0x13
	// Bit mask of TIMOUT field.
	LPTIM1_LPTIM_CFGR_TIMOUT_Msk = 0x80000
	// Bit TIMOUT.
	LPTIM1_LPTIM_CFGR_TIMOUT = 0x80000
	// Position of WAVE field.
	LPTIM1_LPTIM_CFGR_WAVE_Pos = 0x14
	// Bit mask of WAVE field.
	LPTIM1_LPTIM_CFGR_WAVE_Msk = 0x100000
	// Bit WAVE.
	LPTIM1_LPTIM_CFGR_WAVE = 0x100000
	// Position of WAVPOL field.
	LPTIM1_LPTIM_CFGR_WAVPOL_Pos = 0x15
	// Bit mask of WAVPOL field.
	LPTIM1_LPTIM_CFGR_WAVPOL_Msk = 0x200000
	// Bit WAVPOL.
	LPTIM1_LPTIM_CFGR_WAVPOL = 0x200000
	// Position of PRELOAD field.
	LPTIM1_LPTIM_CFGR_PRELOAD_Pos = 0x16
	// Bit mask of PRELOAD field.
	LPTIM1_LPTIM_CFGR_PRELOAD_Msk = 0x400000
	// Bit PRELOAD.
	LPTIM1_LPTIM_CFGR_PRELOAD = 0x400000
	// Position of COUNTMODE field.
	LPTIM1_LPTIM_CFGR_COUNTMODE_Pos = 0x17
	// Bit mask of COUNTMODE field.
	LPTIM1_LPTIM_CFGR_COUNTMODE_Msk = 0x800000
	// Bit COUNTMODE.
	LPTIM1_LPTIM_CFGR_COUNTMODE = 0x800000
	// Position of ENC field.
	LPTIM1_LPTIM_CFGR_ENC_Pos = 0x18
	// Bit mask of ENC field.
	LPTIM1_LPTIM_CFGR_ENC_Msk = 0x1000000
	// Bit ENC.
	LPTIM1_LPTIM_CFGR_ENC = 0x1000000

	// LPTIM_CR: LPTIM control register
	// Position of ENABLE field.
	LPTIM1_LPTIM_CR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	LPTIM1_LPTIM_CR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	LPTIM1_LPTIM_CR_ENABLE = 0x1
	// Position of SNGSTRT field.
	LPTIM1_LPTIM_CR_SNGSTRT_Pos = 0x1
	// Bit mask of SNGSTRT field.
	LPTIM1_LPTIM_CR_SNGSTRT_Msk = 0x2
	// Bit SNGSTRT.
	LPTIM1_LPTIM_CR_SNGSTRT = 0x2
	// Position of CNTSTRT field.
	LPTIM1_LPTIM_CR_CNTSTRT_Pos = 0x2
	// Bit mask of CNTSTRT field.
	LPTIM1_LPTIM_CR_CNTSTRT_Msk = 0x4
	// Bit CNTSTRT.
	LPTIM1_LPTIM_CR_CNTSTRT = 0x4
	// Position of COUNTRST field.
	LPTIM1_LPTIM_CR_COUNTRST_Pos = 0x3
	// Bit mask of COUNTRST field.
	LPTIM1_LPTIM_CR_COUNTRST_Msk = 0x8
	// Bit COUNTRST.
	LPTIM1_LPTIM_CR_COUNTRST = 0x8
	// Position of RSTARE field.
	LPTIM1_LPTIM_CR_RSTARE_Pos = 0x4
	// Bit mask of RSTARE field.
	LPTIM1_LPTIM_CR_RSTARE_Msk = 0x10
	// Bit RSTARE.
	LPTIM1_LPTIM_CR_RSTARE = 0x10

	// LPTIM_CMP: LPTIM compare register
	// Position of CMP field.
	LPTIM1_LPTIM_CMP_CMP_Pos = 0x0
	// Bit mask of CMP field.
	LPTIM1_LPTIM_CMP_CMP_Msk = 0xffff

	// LPTIM_ARR: LPTIM autoreload register
	// Position of ARR field.
	LPTIM1_LPTIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	LPTIM1_LPTIM_ARR_ARR_Msk = 0xffff

	// LPTIM_CNT: LPTIM counter register
	// Position of CNT field.
	LPTIM1_LPTIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	LPTIM1_LPTIM_CNT_CNT_Msk = 0xffff

	// LPTIM_CFGR2: LPTIM configuration register 2
	// Position of IN1SEL field.
	LPTIM1_LPTIM_CFGR2_IN1SEL_Pos = 0x0
	// Bit mask of IN1SEL field.
	LPTIM1_LPTIM_CFGR2_IN1SEL_Msk = 0x3
	// Position of IN2SEL field.
	LPTIM1_LPTIM_CFGR2_IN2SEL_Pos = 0x4
	// Bit mask of IN2SEL field.
	LPTIM1_LPTIM_CFGR2_IN2SEL_Msk = 0x30

	// LPTIM1_HWCFGR: LPTIM 1 peripheral hardware configuration register
	// Position of CFG1 field.
	LPTIM1_LPTIM1_HWCFGR_CFG1_Pos = 0x0
	// Bit mask of CFG1 field.
	LPTIM1_LPTIM1_HWCFGR_CFG1_Msk = 0xff
	// Position of CFG2 field.
	LPTIM1_LPTIM1_HWCFGR_CFG2_Pos = 0x8
	// Bit mask of CFG2 field.
	LPTIM1_LPTIM1_HWCFGR_CFG2_Msk = 0xff00
	// Position of CFG3 field.
	LPTIM1_LPTIM1_HWCFGR_CFG3_Pos = 0x10
	// Bit mask of CFG3 field.
	LPTIM1_LPTIM1_HWCFGR_CFG3_Msk = 0xf0000
	// Position of CFG4 field.
	LPTIM1_LPTIM1_HWCFGR_CFG4_Pos = 0x18
	// Bit mask of CFG4 field.
	LPTIM1_LPTIM1_HWCFGR_CFG4_Msk = 0xff000000

	// LPTIM_VERR: LPTIM peripheral version identification register
	// Position of MINREV field.
	LPTIM1_LPTIM_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	LPTIM1_LPTIM_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	LPTIM1_LPTIM_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	LPTIM1_LPTIM_VERR_MAJREV_Msk = 0xf0

	// LPTIM_PIDR: LPTIM peripheral type identification register
	// Position of P_ID field.
	LPTIM1_LPTIM_PIDR_P_ID_Pos = 0x0
	// Bit mask of P_ID field.
	LPTIM1_LPTIM_PIDR_P_ID_Msk = 0xffffffff

	// LPTIM_SIDR: LPTIM registers map size identification register
	// Position of S_ID field.
	LPTIM1_LPTIM_SIDR_S_ID_Pos = 0x0
	// Bit mask of S_ID field.
	LPTIM1_LPTIM_SIDR_S_ID_Msk = 0xffffffff
)

// Bitfields for LTDC: LTDC
const (
	// LTDC_IDR: LTDC identification register
	// Position of REV field.
	LTDC_LTDC_IDR_REV_Pos = 0x0
	// Bit mask of REV field.
	LTDC_LTDC_IDR_REV_Msk = 0xff
	// Position of MINVER field.
	LTDC_LTDC_IDR_MINVER_Pos = 0x8
	// Bit mask of MINVER field.
	LTDC_LTDC_IDR_MINVER_Msk = 0xff00
	// Position of MAJVER field.
	LTDC_LTDC_IDR_MAJVER_Pos = 0x10
	// Bit mask of MAJVER field.
	LTDC_LTDC_IDR_MAJVER_Msk = 0xff0000

	// LTDC_LCR: LDTC layer count register
	// Position of LNBR field.
	LTDC_LTDC_LCR_LNBR_Pos = 0x0
	// Bit mask of LNBR field.
	LTDC_LTDC_LCR_LNBR_Msk = 0xff

	// LTDC_SSCR: This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
	// Position of VSH field.
	LTDC_LTDC_SSCR_VSH_Pos = 0x0
	// Bit mask of VSH field.
	LTDC_LTDC_SSCR_VSH_Msk = 0xfff
	// Position of HSW field.
	LTDC_LTDC_SSCR_HSW_Pos = 0x10
	// Bit mask of HSW field.
	LTDC_LTDC_SSCR_HSW_Msk = 0xfff0000

	// LTDC_BPCR: This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
	// Position of AVBP field.
	LTDC_LTDC_BPCR_AVBP_Pos = 0x0
	// Bit mask of AVBP field.
	LTDC_LTDC_BPCR_AVBP_Msk = 0xfff
	// Position of AHBP field.
	LTDC_LTDC_BPCR_AHBP_Pos = 0x10
	// Bit mask of AHBP field.
	LTDC_LTDC_BPCR_AHBP_Msk = 0xfff0000

	// LTDC_AWCR: This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
	// Position of AAH field.
	LTDC_LTDC_AWCR_AAH_Pos = 0x0
	// Bit mask of AAH field.
	LTDC_LTDC_AWCR_AAH_Msk = 0xfff
	// Position of AAW field.
	LTDC_LTDC_AWCR_AAW_Pos = 0x10
	// Bit mask of AAW field.
	LTDC_LTDC_AWCR_AAW_Msk = 0xfff0000

	// LTDC_TWCR: This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
	// Position of TOTALH field.
	LTDC_LTDC_TWCR_TOTALH_Pos = 0x0
	// Bit mask of TOTALH field.
	LTDC_LTDC_TWCR_TOTALH_Msk = 0xfff
	// Position of TOTALW field.
	LTDC_LTDC_TWCR_TOTALW_Pos = 0x10
	// Bit mask of TOTALW field.
	LTDC_LTDC_TWCR_TOTALW_Msk = 0xfff0000

	// LTDC_GCR: This register defines the global configuration of the LCD-TFT controller.
	// Position of LTDCEN field.
	LTDC_LTDC_GCR_LTDCEN_Pos = 0x0
	// Bit mask of LTDCEN field.
	LTDC_LTDC_GCR_LTDCEN_Msk = 0x1
	// Bit LTDCEN.
	LTDC_LTDC_GCR_LTDCEN = 0x1
	// Position of DBW field.
	LTDC_LTDC_GCR_DBW_Pos = 0x4
	// Bit mask of DBW field.
	LTDC_LTDC_GCR_DBW_Msk = 0x70
	// Position of DGW field.
	LTDC_LTDC_GCR_DGW_Pos = 0x8
	// Bit mask of DGW field.
	LTDC_LTDC_GCR_DGW_Msk = 0x700
	// Position of DRW field.
	LTDC_LTDC_GCR_DRW_Pos = 0xc
	// Bit mask of DRW field.
	LTDC_LTDC_GCR_DRW_Msk = 0x7000
	// Position of DEN field.
	LTDC_LTDC_GCR_DEN_Pos = 0x10
	// Bit mask of DEN field.
	LTDC_LTDC_GCR_DEN_Msk = 0x10000
	// Bit DEN.
	LTDC_LTDC_GCR_DEN = 0x10000
	// Position of PCPOL field.
	LTDC_LTDC_GCR_PCPOL_Pos = 0x1c
	// Bit mask of PCPOL field.
	LTDC_LTDC_GCR_PCPOL_Msk = 0x10000000
	// Bit PCPOL.
	LTDC_LTDC_GCR_PCPOL = 0x10000000
	// Position of DEPOL field.
	LTDC_LTDC_GCR_DEPOL_Pos = 0x1d
	// Bit mask of DEPOL field.
	LTDC_LTDC_GCR_DEPOL_Msk = 0x20000000
	// Bit DEPOL.
	LTDC_LTDC_GCR_DEPOL = 0x20000000
	// Position of VSPOL field.
	LTDC_LTDC_GCR_VSPOL_Pos = 0x1e
	// Bit mask of VSPOL field.
	LTDC_LTDC_GCR_VSPOL_Msk = 0x40000000
	// Bit VSPOL.
	LTDC_LTDC_GCR_VSPOL = 0x40000000
	// Position of HSPOL field.
	LTDC_LTDC_GCR_HSPOL_Pos = 0x1f
	// Bit mask of HSPOL field.
	LTDC_LTDC_GCR_HSPOL_Msk = 0x80000000
	// Bit HSPOL.
	LTDC_LTDC_GCR_HSPOL = 0x80000000

	// LTDC_GC1R: LTDC global configuration 1 register
	// Position of WBCH field.
	LTDC_LTDC_GC1R_WBCH_Pos = 0x0
	// Bit mask of WBCH field.
	LTDC_LTDC_GC1R_WBCH_Msk = 0xf
	// Position of WGCH field.
	LTDC_LTDC_GC1R_WGCH_Pos = 0x4
	// Bit mask of WGCH field.
	LTDC_LTDC_GC1R_WGCH_Msk = 0xf0
	// Position of WRCH field.
	LTDC_LTDC_GC1R_WRCH_Pos = 0x8
	// Bit mask of WRCH field.
	LTDC_LTDC_GC1R_WRCH_Msk = 0xf00
	// Position of PRBEN field.
	LTDC_LTDC_GC1R_PRBEN_Pos = 0xc
	// Bit mask of PRBEN field.
	LTDC_LTDC_GC1R_PRBEN_Msk = 0x1000
	// Bit PRBEN.
	LTDC_LTDC_GC1R_PRBEN = 0x1000
	// Position of DT field.
	LTDC_LTDC_GC1R_DT_Pos = 0xe
	// Bit mask of DT field.
	LTDC_LTDC_GC1R_DT_Msk = 0xc000
	// Position of GCT field.
	LTDC_LTDC_GC1R_GCT_Pos = 0x11
	// Bit mask of GCT field.
	LTDC_LTDC_GC1R_GCT_Msk = 0xe0000
	// Position of SHREN field.
	LTDC_LTDC_GC1R_SHREN_Pos = 0x15
	// Bit mask of SHREN field.
	LTDC_LTDC_GC1R_SHREN_Msk = 0x200000
	// Bit SHREN.
	LTDC_LTDC_GC1R_SHREN = 0x200000
	// Position of BCP field.
	LTDC_LTDC_GC1R_BCP_Pos = 0x16
	// Bit mask of BCP field.
	LTDC_LTDC_GC1R_BCP_Msk = 0x400000
	// Bit BCP.
	LTDC_LTDC_GC1R_BCP = 0x400000
	// Position of BBEN field.
	LTDC_LTDC_GC1R_BBEN_Pos = 0x17
	// Bit mask of BBEN field.
	LTDC_LTDC_GC1R_BBEN_Msk = 0x800000
	// Bit BBEN.
	LTDC_LTDC_GC1R_BBEN = 0x800000
	// Position of LNIP field.
	LTDC_LTDC_GC1R_LNIP_Pos = 0x18
	// Bit mask of LNIP field.
	LTDC_LTDC_GC1R_LNIP_Msk = 0x1000000
	// Bit LNIP.
	LTDC_LTDC_GC1R_LNIP = 0x1000000
	// Position of TP field.
	LTDC_LTDC_GC1R_TP_Pos = 0x19
	// Bit mask of TP field.
	LTDC_LTDC_GC1R_TP_Msk = 0x2000000
	// Bit TP.
	LTDC_LTDC_GC1R_TP = 0x2000000
	// Position of IPP field.
	LTDC_LTDC_GC1R_IPP_Pos = 0x1a
	// Bit mask of IPP field.
	LTDC_LTDC_GC1R_IPP_Msk = 0x4000000
	// Bit IPP.
	LTDC_LTDC_GC1R_IPP = 0x4000000
	// Position of SPP field.
	LTDC_LTDC_GC1R_SPP_Pos = 0x1b
	// Bit mask of SPP field.
	LTDC_LTDC_GC1R_SPP_Msk = 0x8000000
	// Bit SPP.
	LTDC_LTDC_GC1R_SPP = 0x8000000
	// Position of DWP field.
	LTDC_LTDC_GC1R_DWP_Pos = 0x1c
	// Bit mask of DWP field.
	LTDC_LTDC_GC1R_DWP_Msk = 0x10000000
	// Bit DWP.
	LTDC_LTDC_GC1R_DWP = 0x10000000
	// Position of STREN field.
	LTDC_LTDC_GC1R_STREN_Pos = 0x1d
	// Bit mask of STREN field.
	LTDC_LTDC_GC1R_STREN_Msk = 0x20000000
	// Bit STREN.
	LTDC_LTDC_GC1R_STREN = 0x20000000
	// Position of BMEN field.
	LTDC_LTDC_GC1R_BMEN_Pos = 0x1f
	// Bit mask of BMEN field.
	LTDC_LTDC_GC1R_BMEN_Msk = 0x80000000
	// Bit BMEN.
	LTDC_LTDC_GC1R_BMEN = 0x80000000

	// LTDC_GC2R: LTDC global configuration 2 register
	// Position of EDCEN field.
	LTDC_LTDC_GC2R_EDCEN_Pos = 0x0
	// Bit mask of EDCEN field.
	LTDC_LTDC_GC2R_EDCEN_Msk = 0x1
	// Bit EDCEN.
	LTDC_LTDC_GC2R_EDCEN = 0x1
	// Position of STSAEN field.
	LTDC_LTDC_GC2R_STSAEN_Pos = 0x1
	// Bit mask of STSAEN field.
	LTDC_LTDC_GC2R_STSAEN_Msk = 0x2
	// Bit STSAEN.
	LTDC_LTDC_GC2R_STSAEN = 0x2
	// Position of DVAEN field.
	LTDC_LTDC_GC2R_DVAEN_Pos = 0x2
	// Bit mask of DVAEN field.
	LTDC_LTDC_GC2R_DVAEN_Msk = 0x4
	// Bit DVAEN.
	LTDC_LTDC_GC2R_DVAEN = 0x4
	// Position of DPAEN field.
	LTDC_LTDC_GC2R_DPAEN_Pos = 0x3
	// Bit mask of DPAEN field.
	LTDC_LTDC_GC2R_DPAEN_Msk = 0x8
	// Bit DPAEN.
	LTDC_LTDC_GC2R_DPAEN = 0x8
	// Position of BW field.
	LTDC_LTDC_GC2R_BW_Pos = 0x4
	// Bit mask of BW field.
	LTDC_LTDC_GC2R_BW_Msk = 0x70
	// Position of EDCA field.
	LTDC_LTDC_GC2R_EDCA_Pos = 0x7
	// Bit mask of EDCA field.
	LTDC_LTDC_GC2R_EDCA_Msk = 0x80
	// Bit EDCA.
	LTDC_LTDC_GC2R_EDCA = 0x80

	// LTDC_SRCR: This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
	// Position of IMR field.
	LTDC_LTDC_SRCR_IMR_Pos = 0x0
	// Bit mask of IMR field.
	LTDC_LTDC_SRCR_IMR_Msk = 0x1
	// Bit IMR.
	LTDC_LTDC_SRCR_IMR = 0x1
	// Position of VBR field.
	LTDC_LTDC_SRCR_VBR_Pos = 0x1
	// Bit mask of VBR field.
	LTDC_LTDC_SRCR_VBR_Msk = 0x2
	// Bit VBR.
	LTDC_LTDC_SRCR_VBR = 0x2

	// LTDC_BCCR: This register defines the background color (RGB888).
	// Position of BCBLUE field.
	LTDC_LTDC_BCCR_BCBLUE_Pos = 0x0
	// Bit mask of BCBLUE field.
	LTDC_LTDC_BCCR_BCBLUE_Msk = 0xff
	// Position of BCGREEN field.
	LTDC_LTDC_BCCR_BCGREEN_Pos = 0x8
	// Bit mask of BCGREEN field.
	LTDC_LTDC_BCCR_BCGREEN_Msk = 0xff00
	// Position of BCRED field.
	LTDC_LTDC_BCCR_BCRED_Pos = 0x10
	// Bit mask of BCRED field.
	LTDC_LTDC_BCCR_BCRED_Msk = 0xff0000

	// LTDC_IER: This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
	// Position of LIE field.
	LTDC_LTDC_IER_LIE_Pos = 0x0
	// Bit mask of LIE field.
	LTDC_LTDC_IER_LIE_Msk = 0x1
	// Bit LIE.
	LTDC_LTDC_IER_LIE = 0x1
	// Position of FUIE field.
	LTDC_LTDC_IER_FUIE_Pos = 0x1
	// Bit mask of FUIE field.
	LTDC_LTDC_IER_FUIE_Msk = 0x2
	// Bit FUIE.
	LTDC_LTDC_IER_FUIE = 0x2
	// Position of TERRIE field.
	LTDC_LTDC_IER_TERRIE_Pos = 0x2
	// Bit mask of TERRIE field.
	LTDC_LTDC_IER_TERRIE_Msk = 0x4
	// Bit TERRIE.
	LTDC_LTDC_IER_TERRIE = 0x4
	// Position of RRIE field.
	LTDC_LTDC_IER_RRIE_Pos = 0x3
	// Bit mask of RRIE field.
	LTDC_LTDC_IER_RRIE_Msk = 0x8
	// Bit RRIE.
	LTDC_LTDC_IER_RRIE = 0x8

	// LTDC_ISR: This register returns the interrupt status flag.
	// Position of LIF field.
	LTDC_LTDC_ISR_LIF_Pos = 0x0
	// Bit mask of LIF field.
	LTDC_LTDC_ISR_LIF_Msk = 0x1
	// Bit LIF.
	LTDC_LTDC_ISR_LIF = 0x1
	// Position of FUIF field.
	LTDC_LTDC_ISR_FUIF_Pos = 0x1
	// Bit mask of FUIF field.
	LTDC_LTDC_ISR_FUIF_Msk = 0x2
	// Bit FUIF.
	LTDC_LTDC_ISR_FUIF = 0x2
	// Position of TERRIF field.
	LTDC_LTDC_ISR_TERRIF_Pos = 0x2
	// Bit mask of TERRIF field.
	LTDC_LTDC_ISR_TERRIF_Msk = 0x4
	// Bit TERRIF.
	LTDC_LTDC_ISR_TERRIF = 0x4
	// Position of RRIF field.
	LTDC_LTDC_ISR_RRIF_Pos = 0x3
	// Bit mask of RRIF field.
	LTDC_LTDC_ISR_RRIF_Msk = 0x8
	// Bit RRIF.
	LTDC_LTDC_ISR_RRIF = 0x8

	// LTDC_ICR: LTDC Interrupt Clear Register
	// Position of CLIF field.
	LTDC_LTDC_ICR_CLIF_Pos = 0x0
	// Bit mask of CLIF field.
	LTDC_LTDC_ICR_CLIF_Msk = 0x1
	// Bit CLIF.
	LTDC_LTDC_ICR_CLIF = 0x1
	// Position of CFUIF field.
	LTDC_LTDC_ICR_CFUIF_Pos = 0x1
	// Bit mask of CFUIF field.
	LTDC_LTDC_ICR_CFUIF_Msk = 0x2
	// Bit CFUIF.
	LTDC_LTDC_ICR_CFUIF = 0x2
	// Position of CTERRIF field.
	LTDC_LTDC_ICR_CTERRIF_Pos = 0x2
	// Bit mask of CTERRIF field.
	LTDC_LTDC_ICR_CTERRIF_Msk = 0x4
	// Bit CTERRIF.
	LTDC_LTDC_ICR_CTERRIF = 0x4
	// Position of CRRIF field.
	LTDC_LTDC_ICR_CRRIF_Pos = 0x3
	// Bit mask of CRRIF field.
	LTDC_LTDC_ICR_CRRIF_Msk = 0x8
	// Bit CRRIF.
	LTDC_LTDC_ICR_CRRIF = 0x8

	// LTDC_LIPCR: This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274.
	// Position of LIPOS field.
	LTDC_LTDC_LIPCR_LIPOS_Pos = 0x0
	// Bit mask of LIPOS field.
	LTDC_LTDC_LIPCR_LIPOS_Msk = 0xfff

	// LTDC_CPSR: LTDC current position status register
	// Position of CYPOS field.
	LTDC_LTDC_CPSR_CYPOS_Pos = 0x0
	// Bit mask of CYPOS field.
	LTDC_LTDC_CPSR_CYPOS_Msk = 0xffff
	// Position of CXPOS field.
	LTDC_LTDC_CPSR_CXPOS_Pos = 0x10
	// Bit mask of CXPOS field.
	LTDC_LTDC_CPSR_CXPOS_Msk = 0xffff0000

	// LTDC_CDSR: This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.
	// Position of VDES field.
	LTDC_LTDC_CDSR_VDES_Pos = 0x0
	// Bit mask of VDES field.
	LTDC_LTDC_CDSR_VDES_Msk = 0x1
	// Bit VDES.
	LTDC_LTDC_CDSR_VDES = 0x1
	// Position of HDES field.
	LTDC_LTDC_CDSR_HDES_Pos = 0x1
	// Bit mask of HDES field.
	LTDC_LTDC_CDSR_HDES_Msk = 0x2
	// Bit HDES.
	LTDC_LTDC_CDSR_HDES = 0x2
	// Position of VSYNCS field.
	LTDC_LTDC_CDSR_VSYNCS_Pos = 0x2
	// Bit mask of VSYNCS field.
	LTDC_LTDC_CDSR_VSYNCS_Msk = 0x4
	// Bit VSYNCS.
	LTDC_LTDC_CDSR_VSYNCS = 0x4
	// Position of HSYNCS field.
	LTDC_LTDC_CDSR_HSYNCS_Pos = 0x3
	// Bit mask of HSYNCS field.
	LTDC_LTDC_CDSR_HSYNCS_Msk = 0x8
	// Bit HSYNCS.
	LTDC_LTDC_CDSR_HSYNCS = 0x8

	// LTDC_L1CR: LTDC layer 1 control register
	// Position of LEN field.
	LTDC_LTDC_L1CR_LEN_Pos = 0x0
	// Bit mask of LEN field.
	LTDC_LTDC_L1CR_LEN_Msk = 0x1
	// Bit LEN.
	LTDC_LTDC_L1CR_LEN = 0x1
	// Position of COLKEN field.
	LTDC_LTDC_L1CR_COLKEN_Pos = 0x1
	// Bit mask of COLKEN field.
	LTDC_LTDC_L1CR_COLKEN_Msk = 0x2
	// Bit COLKEN.
	LTDC_LTDC_L1CR_COLKEN = 0x2
	// Position of CLUTEN field.
	LTDC_LTDC_L1CR_CLUTEN_Pos = 0x4
	// Bit mask of CLUTEN field.
	LTDC_LTDC_L1CR_CLUTEN_Msk = 0x10
	// Bit CLUTEN.
	LTDC_LTDC_L1CR_CLUTEN = 0x10

	// LTDC_L1WHPCR: This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
	// Position of WHSTPOS field.
	LTDC_LTDC_L1WHPCR_WHSTPOS_Pos = 0x0
	// Bit mask of WHSTPOS field.
	LTDC_LTDC_L1WHPCR_WHSTPOS_Msk = 0xfff
	// Position of WHSPPOS field.
	LTDC_LTDC_L1WHPCR_WHSPPOS_Pos = 0x10
	// Bit mask of WHSPPOS field.
	LTDC_LTDC_L1WHPCR_WHSPPOS_Msk = 0xfff0000

	// LTDC_L1WVPCR: This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
	// Position of WVSTPOS field.
	LTDC_LTDC_L1WVPCR_WVSTPOS_Pos = 0x0
	// Bit mask of WVSTPOS field.
	LTDC_LTDC_L1WVPCR_WVSTPOS_Msk = 0xfff
	// Position of WVSPPOS field.
	LTDC_LTDC_L1WVPCR_WVSPPOS_Pos = 0x10
	// Bit mask of WVSPPOS field.
	LTDC_LTDC_L1WVPCR_WVSPPOS_Msk = 0xfff0000

	// LTDC_L1CKCR: This register defines the color key value (RGB), that is used by the color keying.
	// Position of CKBLUE field.
	LTDC_LTDC_L1CKCR_CKBLUE_Pos = 0x0
	// Bit mask of CKBLUE field.
	LTDC_LTDC_L1CKCR_CKBLUE_Msk = 0xff
	// Position of CKGREEN field.
	LTDC_LTDC_L1CKCR_CKGREEN_Pos = 0x8
	// Bit mask of CKGREEN field.
	LTDC_LTDC_L1CKCR_CKGREEN_Msk = 0xff00
	// Position of CKRED field.
	LTDC_LTDC_L1CKCR_CKRED_Pos = 0x10
	// Bit mask of CKRED field.
	LTDC_LTDC_L1CKCR_CKRED_Msk = 0xff0000

	// LTDC_L1PFCR: This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
	// Position of PF field.
	LTDC_LTDC_L1PFCR_PF_Pos = 0x0
	// Bit mask of PF field.
	LTDC_LTDC_L1PFCR_PF_Msk = 0x7

	// LTDC_L1CACR: This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
	// Position of CONSTA field.
	LTDC_LTDC_L1CACR_CONSTA_Pos = 0x0
	// Bit mask of CONSTA field.
	LTDC_LTDC_L1CACR_CONSTA_Msk = 0xff

	// LTDC_L1DCCR: This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
	// Position of DCBLUE field.
	LTDC_LTDC_L1DCCR_DCBLUE_Pos = 0x0
	// Bit mask of DCBLUE field.
	LTDC_LTDC_L1DCCR_DCBLUE_Msk = 0xff
	// Position of DCGREEN field.
	LTDC_LTDC_L1DCCR_DCGREEN_Pos = 0x8
	// Bit mask of DCGREEN field.
	LTDC_LTDC_L1DCCR_DCGREEN_Msk = 0xff00
	// Position of DCRED field.
	LTDC_LTDC_L1DCCR_DCRED_Pos = 0x10
	// Bit mask of DCRED field.
	LTDC_LTDC_L1DCCR_DCRED_Msk = 0xff0000
	// Position of DCALPHA field.
	LTDC_LTDC_L1DCCR_DCALPHA_Pos = 0x18
	// Bit mask of DCALPHA field.
	LTDC_LTDC_L1DCCR_DCALPHA_Msk = 0xff000000

	// LTDC_L1BFCR: This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
	// Position of BF2 field.
	LTDC_LTDC_L1BFCR_BF2_Pos = 0x0
	// Bit mask of BF2 field.
	LTDC_LTDC_L1BFCR_BF2_Msk = 0x7
	// Position of BF1 field.
	LTDC_LTDC_L1BFCR_BF1_Pos = 0x8
	// Bit mask of BF1 field.
	LTDC_LTDC_L1BFCR_BF1_Msk = 0x700

	// LTDC_L1CFBAR: This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
	// Position of CFBADD field.
	LTDC_LTDC_L1CFBAR_CFBADD_Pos = 0x0
	// Bit mask of CFBADD field.
	LTDC_LTDC_L1CFBAR_CFBADD_Msk = 0xffffffff

	// LTDC_L1CFBLR: This register defines the color frame buffer line length and pitch.
	// Position of CFBLL field.
	LTDC_LTDC_L1CFBLR_CFBLL_Pos = 0x0
	// Bit mask of CFBLL field.
	LTDC_LTDC_L1CFBLR_CFBLL_Msk = 0x3fff
	// Position of CFBP field.
	LTDC_LTDC_L1CFBLR_CFBP_Pos = 0x10
	// Bit mask of CFBP field.
	LTDC_LTDC_L1CFBLR_CFBP_Msk = 0x3fff0000

	// LTDC_L1CFBLNR: This register defines the number of lines in the color frame buffer.
	// Position of CFBLNBR field.
	LTDC_LTDC_L1CFBLNR_CFBLNBR_Pos = 0x0
	// Bit mask of CFBLNBR field.
	LTDC_LTDC_L1CFBLNR_CFBLNBR_Msk = 0xfff

	// LTDC_L1CLUTWR: This register defines the CLUT address and the RGB value.
	// Position of BLUE field.
	LTDC_LTDC_L1CLUTWR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	LTDC_LTDC_L1CLUTWR_BLUE_Msk = 0xff
	// Position of GREEN field.
	LTDC_LTDC_L1CLUTWR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	LTDC_LTDC_L1CLUTWR_GREEN_Msk = 0xff00
	// Position of RED field.
	LTDC_LTDC_L1CLUTWR_RED_Pos = 0x10
	// Bit mask of RED field.
	LTDC_LTDC_L1CLUTWR_RED_Msk = 0xff0000
	// Position of CLUTADD field.
	LTDC_LTDC_L1CLUTWR_CLUTADD_Pos = 0x18
	// Bit mask of CLUTADD field.
	LTDC_LTDC_L1CLUTWR_CLUTADD_Msk = 0xff000000

	// LTDC_L2CR: LTDC layer 2 control register
	// Position of LEN field.
	LTDC_LTDC_L2CR_LEN_Pos = 0x0
	// Bit mask of LEN field.
	LTDC_LTDC_L2CR_LEN_Msk = 0x1
	// Bit LEN.
	LTDC_LTDC_L2CR_LEN = 0x1
	// Position of COLKEN field.
	LTDC_LTDC_L2CR_COLKEN_Pos = 0x1
	// Bit mask of COLKEN field.
	LTDC_LTDC_L2CR_COLKEN_Msk = 0x2
	// Bit COLKEN.
	LTDC_LTDC_L2CR_COLKEN = 0x2
	// Position of CLUTEN field.
	LTDC_LTDC_L2CR_CLUTEN_Pos = 0x4
	// Bit mask of CLUTEN field.
	LTDC_LTDC_L2CR_CLUTEN_Msk = 0x10
	// Bit CLUTEN.
	LTDC_LTDC_L2CR_CLUTEN = 0x10

	// LTDC_L2WHPCR: This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
	// Position of WHSTPOS field.
	LTDC_LTDC_L2WHPCR_WHSTPOS_Pos = 0x0
	// Bit mask of WHSTPOS field.
	LTDC_LTDC_L2WHPCR_WHSTPOS_Msk = 0xfff
	// Position of WHSPPOS field.
	LTDC_LTDC_L2WHPCR_WHSPPOS_Pos = 0x10
	// Bit mask of WHSPPOS field.
	LTDC_LTDC_L2WHPCR_WHSPPOS_Msk = 0xfff0000

	// LTDC_L2WVPCR: This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
	// Position of WVSTPOS field.
	LTDC_LTDC_L2WVPCR_WVSTPOS_Pos = 0x0
	// Bit mask of WVSTPOS field.
	LTDC_LTDC_L2WVPCR_WVSTPOS_Msk = 0xfff
	// Position of WVSPPOS field.
	LTDC_LTDC_L2WVPCR_WVSPPOS_Pos = 0x10
	// Bit mask of WVSPPOS field.
	LTDC_LTDC_L2WVPCR_WVSPPOS_Msk = 0xfff0000

	// LTDC_L2CKCR: This register defines the color key value (RGB), that is used by the color keying.
	// Position of CKBLUE field.
	LTDC_LTDC_L2CKCR_CKBLUE_Pos = 0x0
	// Bit mask of CKBLUE field.
	LTDC_LTDC_L2CKCR_CKBLUE_Msk = 0xff
	// Position of CKGREEN field.
	LTDC_LTDC_L2CKCR_CKGREEN_Pos = 0x8
	// Bit mask of CKGREEN field.
	LTDC_LTDC_L2CKCR_CKGREEN_Msk = 0xff00
	// Position of CKRED field.
	LTDC_LTDC_L2CKCR_CKRED_Pos = 0x10
	// Bit mask of CKRED field.
	LTDC_LTDC_L2CKCR_CKRED_Msk = 0xff0000

	// LTDC_L2PFCR: This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
	// Position of PF field.
	LTDC_LTDC_L2PFCR_PF_Pos = 0x0
	// Bit mask of PF field.
	LTDC_LTDC_L2PFCR_PF_Msk = 0x7

	// LTDC_L2CACR: This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
	// Position of CONSTA field.
	LTDC_LTDC_L2CACR_CONSTA_Pos = 0x0
	// Bit mask of CONSTA field.
	LTDC_LTDC_L2CACR_CONSTA_Msk = 0xff

	// LTDC_L2DCCR: This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
	// Position of DCBLUE field.
	LTDC_LTDC_L2DCCR_DCBLUE_Pos = 0x0
	// Bit mask of DCBLUE field.
	LTDC_LTDC_L2DCCR_DCBLUE_Msk = 0xff
	// Position of DCGREEN field.
	LTDC_LTDC_L2DCCR_DCGREEN_Pos = 0x8
	// Bit mask of DCGREEN field.
	LTDC_LTDC_L2DCCR_DCGREEN_Msk = 0xff00
	// Position of DCRED field.
	LTDC_LTDC_L2DCCR_DCRED_Pos = 0x10
	// Bit mask of DCRED field.
	LTDC_LTDC_L2DCCR_DCRED_Msk = 0xff0000
	// Position of DCALPHA field.
	LTDC_LTDC_L2DCCR_DCALPHA_Pos = 0x18
	// Bit mask of DCALPHA field.
	LTDC_LTDC_L2DCCR_DCALPHA_Msk = 0xff000000

	// LTDC_L2BFCR: This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
	// Position of BF2 field.
	LTDC_LTDC_L2BFCR_BF2_Pos = 0x0
	// Bit mask of BF2 field.
	LTDC_LTDC_L2BFCR_BF2_Msk = 0x7
	// Position of BF1 field.
	LTDC_LTDC_L2BFCR_BF1_Pos = 0x8
	// Bit mask of BF1 field.
	LTDC_LTDC_L2BFCR_BF1_Msk = 0x700

	// LTDC_L2CFBAR: This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
	// Position of CFBADD field.
	LTDC_LTDC_L2CFBAR_CFBADD_Pos = 0x0
	// Bit mask of CFBADD field.
	LTDC_LTDC_L2CFBAR_CFBADD_Msk = 0xffffffff

	// LTDC_L2CFBLR: This register defines the color frame buffer line length and pitch.
	// Position of CFBLL field.
	LTDC_LTDC_L2CFBLR_CFBLL_Pos = 0x0
	// Bit mask of CFBLL field.
	LTDC_LTDC_L2CFBLR_CFBLL_Msk = 0x3fff
	// Position of CFBP field.
	LTDC_LTDC_L2CFBLR_CFBP_Pos = 0x10
	// Bit mask of CFBP field.
	LTDC_LTDC_L2CFBLR_CFBP_Msk = 0x3fff0000

	// LTDC_L2CFBLNR: This register defines the number of lines in the color frame buffer.
	// Position of CFBLNBR field.
	LTDC_LTDC_L2CFBLNR_CFBLNBR_Pos = 0x0
	// Bit mask of CFBLNBR field.
	LTDC_LTDC_L2CFBLNR_CFBLNBR_Msk = 0xfff

	// LTDC_L2CLUTWR: This register defines the CLUT address and the RGB value.
	// Position of BLUE field.
	LTDC_LTDC_L2CLUTWR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	LTDC_LTDC_L2CLUTWR_BLUE_Msk = 0xff
	// Position of GREEN field.
	LTDC_LTDC_L2CLUTWR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	LTDC_LTDC_L2CLUTWR_GREEN_Msk = 0xff00
	// Position of RED field.
	LTDC_LTDC_L2CLUTWR_RED_Pos = 0x10
	// Bit mask of RED field.
	LTDC_LTDC_L2CLUTWR_RED_Msk = 0xff0000
	// Position of CLUTADD field.
	LTDC_LTDC_L2CLUTWR_CLUTADD_Pos = 0x18
	// Bit mask of CLUTADD field.
	LTDC_LTDC_L2CLUTWR_CLUTADD_Msk = 0xff000000
)

// Bitfields for MDIOS: MDIOS
const (
	// MDIOS_CR: MDIOS configuration register
	// Position of EN field.
	MDIOS_MDIOS_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDIOS_MDIOS_CR_EN_Msk = 0x1
	// Bit EN.
	MDIOS_MDIOS_CR_EN = 0x1
	// Position of WRIE field.
	MDIOS_MDIOS_CR_WRIE_Pos = 0x1
	// Bit mask of WRIE field.
	MDIOS_MDIOS_CR_WRIE_Msk = 0x2
	// Bit WRIE.
	MDIOS_MDIOS_CR_WRIE = 0x2
	// Position of RDIE field.
	MDIOS_MDIOS_CR_RDIE_Pos = 0x2
	// Bit mask of RDIE field.
	MDIOS_MDIOS_CR_RDIE_Msk = 0x4
	// Bit RDIE.
	MDIOS_MDIOS_CR_RDIE = 0x4
	// Position of EIE field.
	MDIOS_MDIOS_CR_EIE_Pos = 0x3
	// Bit mask of EIE field.
	MDIOS_MDIOS_CR_EIE_Msk = 0x8
	// Bit EIE.
	MDIOS_MDIOS_CR_EIE = 0x8
	// Position of DPC field.
	MDIOS_MDIOS_CR_DPC_Pos = 0x7
	// Bit mask of DPC field.
	MDIOS_MDIOS_CR_DPC_Msk = 0x80
	// Bit DPC.
	MDIOS_MDIOS_CR_DPC = 0x80
	// Position of PORT_ADDRESS field.
	MDIOS_MDIOS_CR_PORT_ADDRESS_Pos = 0x8
	// Bit mask of PORT_ADDRESS field.
	MDIOS_MDIOS_CR_PORT_ADDRESS_Msk = 0x1f00

	// MDIOS_WRFR: MDIOS write flag register
	// Position of WRF field.
	MDIOS_MDIOS_WRFR_WRF_Pos = 0x0
	// Bit mask of WRF field.
	MDIOS_MDIOS_WRFR_WRF_Msk = 0xffffffff

	// MDIOS_CWRFR: MDIOS clear write flag register
	// Position of CWRF field.
	MDIOS_MDIOS_CWRFR_CWRF_Pos = 0x0
	// Bit mask of CWRF field.
	MDIOS_MDIOS_CWRFR_CWRF_Msk = 0xffffffff

	// MDIOS_RDFR: MDIOS read flag register
	// Position of RDF field.
	MDIOS_MDIOS_RDFR_RDF_Pos = 0x0
	// Bit mask of RDF field.
	MDIOS_MDIOS_RDFR_RDF_Msk = 0xffffffff

	// MDIOS_CRDFR: MDIOS clear read flag register
	// Position of CRDF field.
	MDIOS_MDIOS_CRDFR_CRDF_Pos = 0x0
	// Bit mask of CRDF field.
	MDIOS_MDIOS_CRDFR_CRDF_Msk = 0xffffffff

	// MDIOS_SR: MDIOS status register
	// Position of PERF field.
	MDIOS_MDIOS_SR_PERF_Pos = 0x0
	// Bit mask of PERF field.
	MDIOS_MDIOS_SR_PERF_Msk = 0x1
	// Bit PERF.
	MDIOS_MDIOS_SR_PERF = 0x1
	// Position of SERF field.
	MDIOS_MDIOS_SR_SERF_Pos = 0x1
	// Bit mask of SERF field.
	MDIOS_MDIOS_SR_SERF_Msk = 0x2
	// Bit SERF.
	MDIOS_MDIOS_SR_SERF = 0x2
	// Position of TERF field.
	MDIOS_MDIOS_SR_TERF_Pos = 0x2
	// Bit mask of TERF field.
	MDIOS_MDIOS_SR_TERF_Msk = 0x4
	// Bit TERF.
	MDIOS_MDIOS_SR_TERF = 0x4

	// MDIOS_CLRFR: MDIOS clear flag register
	// Position of CPERF field.
	MDIOS_MDIOS_CLRFR_CPERF_Pos = 0x0
	// Bit mask of CPERF field.
	MDIOS_MDIOS_CLRFR_CPERF_Msk = 0x1
	// Bit CPERF.
	MDIOS_MDIOS_CLRFR_CPERF = 0x1
	// Position of CSERF field.
	MDIOS_MDIOS_CLRFR_CSERF_Pos = 0x1
	// Bit mask of CSERF field.
	MDIOS_MDIOS_CLRFR_CSERF_Msk = 0x2
	// Bit CSERF.
	MDIOS_MDIOS_CLRFR_CSERF = 0x2
	// Position of CTERF field.
	MDIOS_MDIOS_CLRFR_CTERF_Pos = 0x2
	// Bit mask of CTERF field.
	MDIOS_MDIOS_CLRFR_CTERF_Msk = 0x4
	// Bit CTERF.
	MDIOS_MDIOS_CLRFR_CTERF = 0x4

	// MDIOS_DINR0: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR0_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR0_DIN_Msk = 0xffff

	// MDIOS_DINR1: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR1_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR1_DIN_Msk = 0xffff

	// MDIOS_DINR2: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR2_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR2_DIN_Msk = 0xffff

	// MDIOS_DINR3: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR3_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR3_DIN_Msk = 0xffff

	// MDIOS_DINR4: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR4_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR4_DIN_Msk = 0xffff

	// MDIOS_DINR5: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR5_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR5_DIN_Msk = 0xffff

	// MDIOS_DINR6: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR6_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR6_DIN_Msk = 0xffff

	// MDIOS_DINR7: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR7_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR7_DIN_Msk = 0xffff

	// MDIOS_DINR8: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR8_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR8_DIN_Msk = 0xffff

	// MDIOS_DINR9: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR9_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR9_DIN_Msk = 0xffff

	// MDIOS_DINR10: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR10_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR10_DIN_Msk = 0xffff

	// MDIOS_DINR11: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR11_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR11_DIN_Msk = 0xffff

	// MDIOS_DINR12: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR12_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR12_DIN_Msk = 0xffff

	// MDIOS_DINR13: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR13_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR13_DIN_Msk = 0xffff

	// MDIOS_DINR14: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR14_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR14_DIN_Msk = 0xffff

	// MDIOS_DINR15: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR15_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR15_DIN_Msk = 0xffff

	// MDIOS_DINR16: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR16_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR16_DIN_Msk = 0xffff

	// MDIOS_DINR17: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR17_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR17_DIN_Msk = 0xffff

	// MDIOS_DINR18: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR18_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR18_DIN_Msk = 0xffff

	// MDIOS_DINR19: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR19_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR19_DIN_Msk = 0xffff

	// MDIOS_DINR20: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR20_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR20_DIN_Msk = 0xffff

	// MDIOS_DINR21: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR21_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR21_DIN_Msk = 0xffff

	// MDIOS_DINR22: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR22_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR22_DIN_Msk = 0xffff

	// MDIOS_DINR23: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR23_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR23_DIN_Msk = 0xffff

	// MDIOS_DINR24: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR24_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR24_DIN_Msk = 0xffff

	// MDIOS_DINR25: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR25_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR25_DIN_Msk = 0xffff

	// MDIOS_DINR26: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR26_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR26_DIN_Msk = 0xffff

	// MDIOS_DINR27: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR27_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR27_DIN_Msk = 0xffff

	// MDIOS_DINR28: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR28_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR28_DIN_Msk = 0xffff

	// MDIOS_DINR29: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR29_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR29_DIN_Msk = 0xffff

	// MDIOS_DINR30: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR30_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR30_DIN_Msk = 0xffff

	// MDIOS_DINR31: MDIOS input data register
	// Position of DIN field.
	MDIOS_MDIOS_DINR31_DIN_Pos = 0x0
	// Bit mask of DIN field.
	MDIOS_MDIOS_DINR31_DIN_Msk = 0xffff

	// MDIOS_DOUTR0: MDIOS input data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR0_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR0_DOUT_Msk = 0xffff

	// MDIOS_DOUTR1: MDIOS input data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR1_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR1_DOUT_Msk = 0xffff

	// MDIOS_DOUTR2: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR2_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR2_DOUT_Msk = 0xffff

	// MDIOS_DOUTR3: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR3_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR3_DOUT_Msk = 0xffff

	// MDIOS_DOUTR4: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR4_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR4_DOUT_Msk = 0xffff

	// MDIOS_DOUTR5: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR5_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR5_DOUT_Msk = 0xffff

	// MDIOS_DOUTR6: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR6_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR6_DOUT_Msk = 0xffff

	// MDIOS_DOUTR7: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR7_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR7_DOUT_Msk = 0xffff

	// MDIOS_DOUTR8: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR8_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR8_DOUT_Msk = 0xffff

	// MDIOS_DOUTR9: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR9_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR9_DOUT_Msk = 0xffff

	// MDIOS_DOUTR10: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR10_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR10_DOUT_Msk = 0xffff

	// MDIOS_DOUTR11: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR11_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR11_DOUT_Msk = 0xffff

	// MDIOS_DOUTR12: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR12_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR12_DOUT_Msk = 0xffff

	// MDIOS_DOUTR13: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR13_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR13_DOUT_Msk = 0xffff

	// MDIOS_DOUTR14: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR14_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR14_DOUT_Msk = 0xffff

	// MDIOS_DOUTR15: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR15_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR15_DOUT_Msk = 0xffff

	// MDIOS_DOUTR16: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR16_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR16_DOUT_Msk = 0xffff

	// MDIOS_DOUTR17: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR17_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR17_DOUT_Msk = 0xffff

	// MDIOS_DOUTR18: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR18_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR18_DOUT_Msk = 0xffff

	// MDIOS_DOUTR19: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR19_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR19_DOUT_Msk = 0xffff

	// MDIOS_DOUTR20: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR20_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR20_DOUT_Msk = 0xffff

	// MDIOS_DOUTR21: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR21_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR21_DOUT_Msk = 0xffff

	// MDIOS_DOUTR22: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR22_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR22_DOUT_Msk = 0xffff

	// MDIOS_DOUTR23: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR23_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR23_DOUT_Msk = 0xffff

	// MDIOS_DOUTR24: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR24_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR24_DOUT_Msk = 0xffff

	// MDIOS_DOUTR25: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR25_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR25_DOUT_Msk = 0xffff

	// MDIOS_DOUTR26: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR26_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR26_DOUT_Msk = 0xffff

	// MDIOS_DOUTR27: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR27_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR27_DOUT_Msk = 0xffff

	// MDIOS_DOUTR28: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR28_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR28_DOUT_Msk = 0xffff

	// MDIOS_DOUTR29: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR29_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR29_DOUT_Msk = 0xffff

	// MDIOS_DOUTR30: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR30_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR30_DOUT_Msk = 0xffff

	// MDIOS_DOUTR31: MDIOS output data register
	// Position of DOUT field.
	MDIOS_MDIOS_DOUTR31_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	MDIOS_MDIOS_DOUTR31_DOUT_Msk = 0xffff

	// MDIOS_HWCFGR: MDIOS HW configuration register
	// Position of NBREG field.
	MDIOS_MDIOS_HWCFGR_NBREG_Pos = 0x0
	// Bit mask of NBREG field.
	MDIOS_MDIOS_HWCFGR_NBREG_Msk = 0xff

	// MDIOS_VERR: MDIOS version register
	// Position of MINREV field.
	MDIOS_MDIOS_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	MDIOS_MDIOS_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	MDIOS_MDIOS_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	MDIOS_MDIOS_VERR_MAJREV_Msk = 0xf0

	// MDIOS_IPIDR: MDIOS identification register
	// Position of ID field.
	MDIOS_MDIOS_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	MDIOS_MDIOS_IPIDR_ID_Msk = 0xffffffff

	// MDIOS_SIDR: MDIOS size identification register
	// Position of SID field.
	MDIOS_MDIOS_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	MDIOS_MDIOS_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for MDMA: MDMA1
const (
	// MDMA_GISR0: MDMA global interrupt/status register
	// Position of GIF0 field.
	MDMA1_MDMA_GISR0_GIF0_Pos = 0x0
	// Bit mask of GIF0 field.
	MDMA1_MDMA_GISR0_GIF0_Msk = 0x1
	// Bit GIF0.
	MDMA1_MDMA_GISR0_GIF0 = 0x1
	// Position of GIF1 field.
	MDMA1_MDMA_GISR0_GIF1_Pos = 0x1
	// Bit mask of GIF1 field.
	MDMA1_MDMA_GISR0_GIF1_Msk = 0x2
	// Bit GIF1.
	MDMA1_MDMA_GISR0_GIF1 = 0x2
	// Position of GIF2 field.
	MDMA1_MDMA_GISR0_GIF2_Pos = 0x2
	// Bit mask of GIF2 field.
	MDMA1_MDMA_GISR0_GIF2_Msk = 0x4
	// Bit GIF2.
	MDMA1_MDMA_GISR0_GIF2 = 0x4
	// Position of GIF3 field.
	MDMA1_MDMA_GISR0_GIF3_Pos = 0x3
	// Bit mask of GIF3 field.
	MDMA1_MDMA_GISR0_GIF3_Msk = 0x8
	// Bit GIF3.
	MDMA1_MDMA_GISR0_GIF3 = 0x8
	// Position of GIF4 field.
	MDMA1_MDMA_GISR0_GIF4_Pos = 0x4
	// Bit mask of GIF4 field.
	MDMA1_MDMA_GISR0_GIF4_Msk = 0x10
	// Bit GIF4.
	MDMA1_MDMA_GISR0_GIF4 = 0x10
	// Position of GIF5 field.
	MDMA1_MDMA_GISR0_GIF5_Pos = 0x5
	// Bit mask of GIF5 field.
	MDMA1_MDMA_GISR0_GIF5_Msk = 0x20
	// Bit GIF5.
	MDMA1_MDMA_GISR0_GIF5 = 0x20
	// Position of GIF6 field.
	MDMA1_MDMA_GISR0_GIF6_Pos = 0x6
	// Bit mask of GIF6 field.
	MDMA1_MDMA_GISR0_GIF6_Msk = 0x40
	// Bit GIF6.
	MDMA1_MDMA_GISR0_GIF6 = 0x40
	// Position of GIF7 field.
	MDMA1_MDMA_GISR0_GIF7_Pos = 0x7
	// Bit mask of GIF7 field.
	MDMA1_MDMA_GISR0_GIF7_Msk = 0x80
	// Bit GIF7.
	MDMA1_MDMA_GISR0_GIF7 = 0x80
	// Position of GIF8 field.
	MDMA1_MDMA_GISR0_GIF8_Pos = 0x8
	// Bit mask of GIF8 field.
	MDMA1_MDMA_GISR0_GIF8_Msk = 0x100
	// Bit GIF8.
	MDMA1_MDMA_GISR0_GIF8 = 0x100
	// Position of GIF9 field.
	MDMA1_MDMA_GISR0_GIF9_Pos = 0x9
	// Bit mask of GIF9 field.
	MDMA1_MDMA_GISR0_GIF9_Msk = 0x200
	// Bit GIF9.
	MDMA1_MDMA_GISR0_GIF9 = 0x200
	// Position of GIF10 field.
	MDMA1_MDMA_GISR0_GIF10_Pos = 0xa
	// Bit mask of GIF10 field.
	MDMA1_MDMA_GISR0_GIF10_Msk = 0x400
	// Bit GIF10.
	MDMA1_MDMA_GISR0_GIF10 = 0x400
	// Position of GIF11 field.
	MDMA1_MDMA_GISR0_GIF11_Pos = 0xb
	// Bit mask of GIF11 field.
	MDMA1_MDMA_GISR0_GIF11_Msk = 0x800
	// Bit GIF11.
	MDMA1_MDMA_GISR0_GIF11 = 0x800
	// Position of GIF12 field.
	MDMA1_MDMA_GISR0_GIF12_Pos = 0xc
	// Bit mask of GIF12 field.
	MDMA1_MDMA_GISR0_GIF12_Msk = 0x1000
	// Bit GIF12.
	MDMA1_MDMA_GISR0_GIF12 = 0x1000
	// Position of GIF13 field.
	MDMA1_MDMA_GISR0_GIF13_Pos = 0xd
	// Bit mask of GIF13 field.
	MDMA1_MDMA_GISR0_GIF13_Msk = 0x2000
	// Bit GIF13.
	MDMA1_MDMA_GISR0_GIF13 = 0x2000
	// Position of GIF14 field.
	MDMA1_MDMA_GISR0_GIF14_Pos = 0xe
	// Bit mask of GIF14 field.
	MDMA1_MDMA_GISR0_GIF14_Msk = 0x4000
	// Bit GIF14.
	MDMA1_MDMA_GISR0_GIF14 = 0x4000
	// Position of GIF15 field.
	MDMA1_MDMA_GISR0_GIF15_Pos = 0xf
	// Bit mask of GIF15 field.
	MDMA1_MDMA_GISR0_GIF15_Msk = 0x8000
	// Bit GIF15.
	MDMA1_MDMA_GISR0_GIF15 = 0x8000
	// Position of GIF16 field.
	MDMA1_MDMA_GISR0_GIF16_Pos = 0x10
	// Bit mask of GIF16 field.
	MDMA1_MDMA_GISR0_GIF16_Msk = 0x10000
	// Bit GIF16.
	MDMA1_MDMA_GISR0_GIF16 = 0x10000
	// Position of GIF17 field.
	MDMA1_MDMA_GISR0_GIF17_Pos = 0x11
	// Bit mask of GIF17 field.
	MDMA1_MDMA_GISR0_GIF17_Msk = 0x20000
	// Bit GIF17.
	MDMA1_MDMA_GISR0_GIF17 = 0x20000
	// Position of GIF18 field.
	MDMA1_MDMA_GISR0_GIF18_Pos = 0x12
	// Bit mask of GIF18 field.
	MDMA1_MDMA_GISR0_GIF18_Msk = 0x40000
	// Bit GIF18.
	MDMA1_MDMA_GISR0_GIF18 = 0x40000
	// Position of GIF19 field.
	MDMA1_MDMA_GISR0_GIF19_Pos = 0x13
	// Bit mask of GIF19 field.
	MDMA1_MDMA_GISR0_GIF19_Msk = 0x80000
	// Bit GIF19.
	MDMA1_MDMA_GISR0_GIF19 = 0x80000
	// Position of GIF20 field.
	MDMA1_MDMA_GISR0_GIF20_Pos = 0x14
	// Bit mask of GIF20 field.
	MDMA1_MDMA_GISR0_GIF20_Msk = 0x100000
	// Bit GIF20.
	MDMA1_MDMA_GISR0_GIF20 = 0x100000
	// Position of GIF21 field.
	MDMA1_MDMA_GISR0_GIF21_Pos = 0x15
	// Bit mask of GIF21 field.
	MDMA1_MDMA_GISR0_GIF21_Msk = 0x200000
	// Bit GIF21.
	MDMA1_MDMA_GISR0_GIF21 = 0x200000
	// Position of GIF22 field.
	MDMA1_MDMA_GISR0_GIF22_Pos = 0x16
	// Bit mask of GIF22 field.
	MDMA1_MDMA_GISR0_GIF22_Msk = 0x400000
	// Bit GIF22.
	MDMA1_MDMA_GISR0_GIF22 = 0x400000
	// Position of GIF23 field.
	MDMA1_MDMA_GISR0_GIF23_Pos = 0x17
	// Bit mask of GIF23 field.
	MDMA1_MDMA_GISR0_GIF23_Msk = 0x800000
	// Bit GIF23.
	MDMA1_MDMA_GISR0_GIF23 = 0x800000
	// Position of GIF24 field.
	MDMA1_MDMA_GISR0_GIF24_Pos = 0x18
	// Bit mask of GIF24 field.
	MDMA1_MDMA_GISR0_GIF24_Msk = 0x1000000
	// Bit GIF24.
	MDMA1_MDMA_GISR0_GIF24 = 0x1000000
	// Position of GIF25 field.
	MDMA1_MDMA_GISR0_GIF25_Pos = 0x19
	// Bit mask of GIF25 field.
	MDMA1_MDMA_GISR0_GIF25_Msk = 0x2000000
	// Bit GIF25.
	MDMA1_MDMA_GISR0_GIF25 = 0x2000000
	// Position of GIF26 field.
	MDMA1_MDMA_GISR0_GIF26_Pos = 0x1a
	// Bit mask of GIF26 field.
	MDMA1_MDMA_GISR0_GIF26_Msk = 0x4000000
	// Bit GIF26.
	MDMA1_MDMA_GISR0_GIF26 = 0x4000000
	// Position of GIF27 field.
	MDMA1_MDMA_GISR0_GIF27_Pos = 0x1b
	// Bit mask of GIF27 field.
	MDMA1_MDMA_GISR0_GIF27_Msk = 0x8000000
	// Bit GIF27.
	MDMA1_MDMA_GISR0_GIF27 = 0x8000000
	// Position of GIF28 field.
	MDMA1_MDMA_GISR0_GIF28_Pos = 0x1c
	// Bit mask of GIF28 field.
	MDMA1_MDMA_GISR0_GIF28_Msk = 0x10000000
	// Bit GIF28.
	MDMA1_MDMA_GISR0_GIF28 = 0x10000000
	// Position of GIF29 field.
	MDMA1_MDMA_GISR0_GIF29_Pos = 0x1d
	// Bit mask of GIF29 field.
	MDMA1_MDMA_GISR0_GIF29_Msk = 0x20000000
	// Bit GIF29.
	MDMA1_MDMA_GISR0_GIF29 = 0x20000000
	// Position of GIF30 field.
	MDMA1_MDMA_GISR0_GIF30_Pos = 0x1e
	// Bit mask of GIF30 field.
	MDMA1_MDMA_GISR0_GIF30_Msk = 0x40000000
	// Bit GIF30.
	MDMA1_MDMA_GISR0_GIF30 = 0x40000000
	// Position of GIF31 field.
	MDMA1_MDMA_GISR0_GIF31_Pos = 0x1f
	// Bit mask of GIF31 field.
	MDMA1_MDMA_GISR0_GIF31_Msk = 0x80000000
	// Bit GIF31.
	MDMA1_MDMA_GISR0_GIF31 = 0x80000000

	// MDMA_SGISR0: MDMA secure global interrupt/status register
	// Position of GIF0 field.
	MDMA1_MDMA_SGISR0_GIF0_Pos = 0x0
	// Bit mask of GIF0 field.
	MDMA1_MDMA_SGISR0_GIF0_Msk = 0x1
	// Bit GIF0.
	MDMA1_MDMA_SGISR0_GIF0 = 0x1
	// Position of GIF1 field.
	MDMA1_MDMA_SGISR0_GIF1_Pos = 0x1
	// Bit mask of GIF1 field.
	MDMA1_MDMA_SGISR0_GIF1_Msk = 0x2
	// Bit GIF1.
	MDMA1_MDMA_SGISR0_GIF1 = 0x2
	// Position of GIF2 field.
	MDMA1_MDMA_SGISR0_GIF2_Pos = 0x2
	// Bit mask of GIF2 field.
	MDMA1_MDMA_SGISR0_GIF2_Msk = 0x4
	// Bit GIF2.
	MDMA1_MDMA_SGISR0_GIF2 = 0x4
	// Position of GIF3 field.
	MDMA1_MDMA_SGISR0_GIF3_Pos = 0x3
	// Bit mask of GIF3 field.
	MDMA1_MDMA_SGISR0_GIF3_Msk = 0x8
	// Bit GIF3.
	MDMA1_MDMA_SGISR0_GIF3 = 0x8
	// Position of GIF4 field.
	MDMA1_MDMA_SGISR0_GIF4_Pos = 0x4
	// Bit mask of GIF4 field.
	MDMA1_MDMA_SGISR0_GIF4_Msk = 0x10
	// Bit GIF4.
	MDMA1_MDMA_SGISR0_GIF4 = 0x10
	// Position of GIF5 field.
	MDMA1_MDMA_SGISR0_GIF5_Pos = 0x5
	// Bit mask of GIF5 field.
	MDMA1_MDMA_SGISR0_GIF5_Msk = 0x20
	// Bit GIF5.
	MDMA1_MDMA_SGISR0_GIF5 = 0x20
	// Position of GIF6 field.
	MDMA1_MDMA_SGISR0_GIF6_Pos = 0x6
	// Bit mask of GIF6 field.
	MDMA1_MDMA_SGISR0_GIF6_Msk = 0x40
	// Bit GIF6.
	MDMA1_MDMA_SGISR0_GIF6 = 0x40
	// Position of GIF7 field.
	MDMA1_MDMA_SGISR0_GIF7_Pos = 0x7
	// Bit mask of GIF7 field.
	MDMA1_MDMA_SGISR0_GIF7_Msk = 0x80
	// Bit GIF7.
	MDMA1_MDMA_SGISR0_GIF7 = 0x80
	// Position of GIF8 field.
	MDMA1_MDMA_SGISR0_GIF8_Pos = 0x8
	// Bit mask of GIF8 field.
	MDMA1_MDMA_SGISR0_GIF8_Msk = 0x100
	// Bit GIF8.
	MDMA1_MDMA_SGISR0_GIF8 = 0x100
	// Position of GIF9 field.
	MDMA1_MDMA_SGISR0_GIF9_Pos = 0x9
	// Bit mask of GIF9 field.
	MDMA1_MDMA_SGISR0_GIF9_Msk = 0x200
	// Bit GIF9.
	MDMA1_MDMA_SGISR0_GIF9 = 0x200
	// Position of GIF10 field.
	MDMA1_MDMA_SGISR0_GIF10_Pos = 0xa
	// Bit mask of GIF10 field.
	MDMA1_MDMA_SGISR0_GIF10_Msk = 0x400
	// Bit GIF10.
	MDMA1_MDMA_SGISR0_GIF10 = 0x400
	// Position of GIF11 field.
	MDMA1_MDMA_SGISR0_GIF11_Pos = 0xb
	// Bit mask of GIF11 field.
	MDMA1_MDMA_SGISR0_GIF11_Msk = 0x800
	// Bit GIF11.
	MDMA1_MDMA_SGISR0_GIF11 = 0x800
	// Position of GIF12 field.
	MDMA1_MDMA_SGISR0_GIF12_Pos = 0xc
	// Bit mask of GIF12 field.
	MDMA1_MDMA_SGISR0_GIF12_Msk = 0x1000
	// Bit GIF12.
	MDMA1_MDMA_SGISR0_GIF12 = 0x1000
	// Position of GIF13 field.
	MDMA1_MDMA_SGISR0_GIF13_Pos = 0xd
	// Bit mask of GIF13 field.
	MDMA1_MDMA_SGISR0_GIF13_Msk = 0x2000
	// Bit GIF13.
	MDMA1_MDMA_SGISR0_GIF13 = 0x2000
	// Position of GIF14 field.
	MDMA1_MDMA_SGISR0_GIF14_Pos = 0xe
	// Bit mask of GIF14 field.
	MDMA1_MDMA_SGISR0_GIF14_Msk = 0x4000
	// Bit GIF14.
	MDMA1_MDMA_SGISR0_GIF14 = 0x4000
	// Position of GIF15 field.
	MDMA1_MDMA_SGISR0_GIF15_Pos = 0xf
	// Bit mask of GIF15 field.
	MDMA1_MDMA_SGISR0_GIF15_Msk = 0x8000
	// Bit GIF15.
	MDMA1_MDMA_SGISR0_GIF15 = 0x8000
	// Position of GIF16 field.
	MDMA1_MDMA_SGISR0_GIF16_Pos = 0x10
	// Bit mask of GIF16 field.
	MDMA1_MDMA_SGISR0_GIF16_Msk = 0x10000
	// Bit GIF16.
	MDMA1_MDMA_SGISR0_GIF16 = 0x10000
	// Position of GIF17 field.
	MDMA1_MDMA_SGISR0_GIF17_Pos = 0x11
	// Bit mask of GIF17 field.
	MDMA1_MDMA_SGISR0_GIF17_Msk = 0x20000
	// Bit GIF17.
	MDMA1_MDMA_SGISR0_GIF17 = 0x20000
	// Position of GIF18 field.
	MDMA1_MDMA_SGISR0_GIF18_Pos = 0x12
	// Bit mask of GIF18 field.
	MDMA1_MDMA_SGISR0_GIF18_Msk = 0x40000
	// Bit GIF18.
	MDMA1_MDMA_SGISR0_GIF18 = 0x40000
	// Position of GIF19 field.
	MDMA1_MDMA_SGISR0_GIF19_Pos = 0x13
	// Bit mask of GIF19 field.
	MDMA1_MDMA_SGISR0_GIF19_Msk = 0x80000
	// Bit GIF19.
	MDMA1_MDMA_SGISR0_GIF19 = 0x80000
	// Position of GIF20 field.
	MDMA1_MDMA_SGISR0_GIF20_Pos = 0x14
	// Bit mask of GIF20 field.
	MDMA1_MDMA_SGISR0_GIF20_Msk = 0x100000
	// Bit GIF20.
	MDMA1_MDMA_SGISR0_GIF20 = 0x100000
	// Position of GIF21 field.
	MDMA1_MDMA_SGISR0_GIF21_Pos = 0x15
	// Bit mask of GIF21 field.
	MDMA1_MDMA_SGISR0_GIF21_Msk = 0x200000
	// Bit GIF21.
	MDMA1_MDMA_SGISR0_GIF21 = 0x200000
	// Position of GIF22 field.
	MDMA1_MDMA_SGISR0_GIF22_Pos = 0x16
	// Bit mask of GIF22 field.
	MDMA1_MDMA_SGISR0_GIF22_Msk = 0x400000
	// Bit GIF22.
	MDMA1_MDMA_SGISR0_GIF22 = 0x400000
	// Position of GIF23 field.
	MDMA1_MDMA_SGISR0_GIF23_Pos = 0x17
	// Bit mask of GIF23 field.
	MDMA1_MDMA_SGISR0_GIF23_Msk = 0x800000
	// Bit GIF23.
	MDMA1_MDMA_SGISR0_GIF23 = 0x800000
	// Position of GIF24 field.
	MDMA1_MDMA_SGISR0_GIF24_Pos = 0x18
	// Bit mask of GIF24 field.
	MDMA1_MDMA_SGISR0_GIF24_Msk = 0x1000000
	// Bit GIF24.
	MDMA1_MDMA_SGISR0_GIF24 = 0x1000000
	// Position of GIF25 field.
	MDMA1_MDMA_SGISR0_GIF25_Pos = 0x19
	// Bit mask of GIF25 field.
	MDMA1_MDMA_SGISR0_GIF25_Msk = 0x2000000
	// Bit GIF25.
	MDMA1_MDMA_SGISR0_GIF25 = 0x2000000
	// Position of GIF26 field.
	MDMA1_MDMA_SGISR0_GIF26_Pos = 0x1a
	// Bit mask of GIF26 field.
	MDMA1_MDMA_SGISR0_GIF26_Msk = 0x4000000
	// Bit GIF26.
	MDMA1_MDMA_SGISR0_GIF26 = 0x4000000
	// Position of GIF27 field.
	MDMA1_MDMA_SGISR0_GIF27_Pos = 0x1b
	// Bit mask of GIF27 field.
	MDMA1_MDMA_SGISR0_GIF27_Msk = 0x8000000
	// Bit GIF27.
	MDMA1_MDMA_SGISR0_GIF27 = 0x8000000
	// Position of GIF28 field.
	MDMA1_MDMA_SGISR0_GIF28_Pos = 0x1c
	// Bit mask of GIF28 field.
	MDMA1_MDMA_SGISR0_GIF28_Msk = 0x10000000
	// Bit GIF28.
	MDMA1_MDMA_SGISR0_GIF28 = 0x10000000
	// Position of GIF29 field.
	MDMA1_MDMA_SGISR0_GIF29_Pos = 0x1d
	// Bit mask of GIF29 field.
	MDMA1_MDMA_SGISR0_GIF29_Msk = 0x20000000
	// Bit GIF29.
	MDMA1_MDMA_SGISR0_GIF29 = 0x20000000
	// Position of GIF30 field.
	MDMA1_MDMA_SGISR0_GIF30_Pos = 0x1e
	// Bit mask of GIF30 field.
	MDMA1_MDMA_SGISR0_GIF30_Msk = 0x40000000
	// Bit GIF30.
	MDMA1_MDMA_SGISR0_GIF30 = 0x40000000
	// Position of GIF31 field.
	MDMA1_MDMA_SGISR0_GIF31_Pos = 0x1f
	// Bit mask of GIF31 field.
	MDMA1_MDMA_SGISR0_GIF31_Msk = 0x80000000
	// Bit GIF31.
	MDMA1_MDMA_SGISR0_GIF31 = 0x80000000

	// MDMA_C0ISR: MDMA channel 0 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C0ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C0ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C0ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C0ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C0ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C0ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C0ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C0ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C0ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C0ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C0ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C0ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C0ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C0ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C0ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C0ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C0ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C0ISR_CRQA = 0x10000

	// MDMA_C0IFCR: MDMA channel 0 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C0IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C0IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C0IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C0IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C0IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C0IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C0IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C0IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C0IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C0IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C0IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C0IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C0IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C0IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C0IFCR_CLTCIF = 0x10

	// MDMA_C0ESR: MDMA channel 0 error status register
	// Position of TEA field.
	MDMA1_MDMA_C0ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C0ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C0ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C0ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C0ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C0ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C0ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C0ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C0ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C0ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C0ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C0ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C0ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C0ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C0ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C0ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C0ESR_BSE = 0x800

	// MDMA_C0CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C0CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C0CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C0CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C0CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C0CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C0CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C0CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C0CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C0CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C0CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C0CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C0CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C0CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C0CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C0CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C0CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C0CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C0CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C0CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C0CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C0CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C0CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C0CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C0CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C0CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C0CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C0CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C0CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C0CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C0CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C0CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C0CR_SWRQ = 0x10000

	// MDMA_C0TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C0TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C0TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C0TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C0TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C0TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C0TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C0TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C0TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C0TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C0TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C0TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C0TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C0TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C0TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C0TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C0TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C0TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C0TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C0TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C0TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C0TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C0TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C0TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C0TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C0TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C0TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C0TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C0TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C0TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C0TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C0TCR_BWM = 0x80000000

	// MDMA_C0BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C0BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C0BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C0BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C0BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C0BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C0BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C0BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C0BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C0BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C0BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C0SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C0SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C0SAR_SAR_Msk = 0xffffffff

	// MDMA_C0DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C0DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C0DAR_DAR_Msk = 0xffffffff

	// MDMA_C0BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C0BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C0BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C0BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C0BRUR_DUV_Msk = 0xffff0000

	// MDMA_C0LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C0LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C0LAR_LAR_Msk = 0xffffffff

	// MDMA_C0TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C0TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C0TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C0TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C0TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C0TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C0TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C0TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C0TBR_DBUS = 0x20000

	// MDMA_C0MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C0MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C0MAR_MAR_Msk = 0xffffffff

	// MDMA_C0MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C0MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C0MDR_MDR_Msk = 0xffffffff

	// MDMA_C1ISR: MDMA channel 1 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C1ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C1ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C1ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C1ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C1ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C1ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C1ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C1ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C1ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C1ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C1ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C1ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C1ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C1ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C1ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C1ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C1ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C1ISR_CRQA = 0x10000

	// MDMA_C1IFCR: MDMA channel 1 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C1IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C1IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C1IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C1IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C1IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C1IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C1IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C1IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C1IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C1IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C1IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C1IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C1IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C1IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C1IFCR_CLTCIF = 0x10

	// MDMA_C1ESR: MDMA channel 1 error status register
	// Position of TEA field.
	MDMA1_MDMA_C1ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C1ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C1ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C1ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C1ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C1ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C1ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C1ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C1ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C1ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C1ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C1ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C1ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C1ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C1ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C1ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C1ESR_BSE = 0x800

	// MDMA_C1CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C1CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C1CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C1CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C1CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C1CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C1CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C1CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C1CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C1CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C1CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C1CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C1CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C1CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C1CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C1CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C1CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C1CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C1CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C1CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C1CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C1CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C1CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C1CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C1CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C1CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C1CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C1CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C1CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C1CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C1CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C1CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C1CR_SWRQ = 0x10000

	// MDMA_C1TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C1TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C1TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C1TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C1TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C1TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C1TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C1TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C1TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C1TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C1TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C1TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C1TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C1TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C1TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C1TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C1TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C1TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C1TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C1TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C1TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C1TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C1TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C1TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C1TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C1TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C1TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C1TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C1TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C1TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C1TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C1TCR_BWM = 0x80000000

	// MDMA_C1BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C1BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C1BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C1BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C1BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C1BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C1BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C1BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C1BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C1BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C1BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C1SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C1SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C1SAR_SAR_Msk = 0xffffffff

	// MDMA_C1DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C1DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C1DAR_DAR_Msk = 0xffffffff

	// MDMA_C1BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C1BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C1BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C1BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C1BRUR_DUV_Msk = 0xffff0000

	// MDMA_C1LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C1LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C1LAR_LAR_Msk = 0xffffffff

	// MDMA_C1TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C1TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C1TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C1TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C1TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C1TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C1TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C1TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C1TBR_DBUS = 0x20000

	// MDMA_C1MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C1MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C1MAR_MAR_Msk = 0xffffffff

	// MDMA_C1MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C1MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C1MDR_MDR_Msk = 0xffffffff

	// MDMA_C2ISR: MDMA channel 2 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C2ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C2ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C2ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C2ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C2ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C2ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C2ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C2ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C2ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C2ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C2ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C2ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C2ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C2ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C2ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C2ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C2ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C2ISR_CRQA = 0x10000

	// MDMA_C2IFCR: MDMA channel 2 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C2IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C2IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C2IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C2IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C2IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C2IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C2IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C2IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C2IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C2IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C2IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C2IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C2IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C2IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C2IFCR_CLTCIF = 0x10

	// MDMA_C2ESR: MDMA channel 2 error status register
	// Position of TEA field.
	MDMA1_MDMA_C2ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C2ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C2ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C2ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C2ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C2ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C2ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C2ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C2ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C2ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C2ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C2ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C2ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C2ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C2ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C2ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C2ESR_BSE = 0x800

	// MDMA_C2CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C2CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C2CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C2CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C2CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C2CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C2CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C2CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C2CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C2CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C2CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C2CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C2CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C2CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C2CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C2CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C2CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C2CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C2CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C2CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C2CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C2CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C2CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C2CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C2CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C2CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C2CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C2CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C2CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C2CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C2CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C2CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C2CR_SWRQ = 0x10000

	// MDMA_C2TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C2TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C2TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C2TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C2TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C2TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C2TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C2TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C2TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C2TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C2TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C2TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C2TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C2TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C2TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C2TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C2TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C2TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C2TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C2TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C2TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C2TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C2TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C2TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C2TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C2TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C2TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C2TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C2TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C2TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C2TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C2TCR_BWM = 0x80000000

	// MDMA_C2BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C2BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C2BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C2BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C2BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C2BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C2BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C2BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C2BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C2BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C2BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C2SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C2SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C2SAR_SAR_Msk = 0xffffffff

	// MDMA_C2DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C2DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C2DAR_DAR_Msk = 0xffffffff

	// MDMA_C2BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C2BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C2BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C2BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C2BRUR_DUV_Msk = 0xffff0000

	// MDMA_C2LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C2LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C2LAR_LAR_Msk = 0xffffffff

	// MDMA_C2TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C2TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C2TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C2TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C2TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C2TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C2TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C2TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C2TBR_DBUS = 0x20000

	// MDMA_C2MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C2MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C2MAR_MAR_Msk = 0xffffffff

	// MDMA_C2MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C2MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C2MDR_MDR_Msk = 0xffffffff

	// MDMA_C3ISR: MDMA channel 3 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C3ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C3ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C3ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C3ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C3ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C3ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C3ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C3ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C3ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C3ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C3ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C3ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C3ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C3ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C3ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C3ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C3ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C3ISR_CRQA = 0x10000

	// MDMA_C3IFCR: MDMA channel 3 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C3IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C3IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C3IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C3IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C3IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C3IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C3IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C3IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C3IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C3IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C3IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C3IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C3IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C3IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C3IFCR_CLTCIF = 0x10

	// MDMA_C3ESR: MDMA channel 3 error status register
	// Position of TEA field.
	MDMA1_MDMA_C3ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C3ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C3ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C3ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C3ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C3ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C3ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C3ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C3ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C3ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C3ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C3ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C3ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C3ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C3ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C3ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C3ESR_BSE = 0x800

	// MDMA_C3CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C3CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C3CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C3CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C3CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C3CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C3CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C3CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C3CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C3CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C3CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C3CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C3CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C3CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C3CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C3CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C3CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C3CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C3CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C3CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C3CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C3CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C3CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C3CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C3CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C3CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C3CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C3CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C3CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C3CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C3CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C3CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C3CR_SWRQ = 0x10000

	// MDMA_C3TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C3TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C3TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C3TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C3TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C3TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C3TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C3TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C3TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C3TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C3TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C3TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C3TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C3TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C3TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C3TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C3TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C3TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C3TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C3TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C3TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C3TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C3TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C3TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C3TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C3TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C3TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C3TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C3TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C3TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C3TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C3TCR_BWM = 0x80000000

	// MDMA_C3BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C3BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C3BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C3BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C3BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C3BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C3BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C3BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C3BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C3BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C3BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C3SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C3SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C3SAR_SAR_Msk = 0xffffffff

	// MDMA_C3DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C3DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C3DAR_DAR_Msk = 0xffffffff

	// MDMA_C3BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C3BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C3BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C3BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C3BRUR_DUV_Msk = 0xffff0000

	// MDMA_C3LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C3LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C3LAR_LAR_Msk = 0xffffffff

	// MDMA_C3TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C3TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C3TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C3TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C3TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C3TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C3TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C3TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C3TBR_DBUS = 0x20000

	// MDMA_C3MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C3MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C3MAR_MAR_Msk = 0xffffffff

	// MDMA_C3MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C3MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C3MDR_MDR_Msk = 0xffffffff

	// MDMA_C4ISR: MDMA channel 4 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C4ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C4ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C4ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C4ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C4ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C4ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C4ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C4ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C4ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C4ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C4ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C4ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C4ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C4ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C4ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C4ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C4ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C4ISR_CRQA = 0x10000

	// MDMA_C4IFCR: MDMA channel 4 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C4IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C4IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C4IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C4IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C4IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C4IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C4IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C4IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C4IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C4IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C4IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C4IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C4IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C4IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C4IFCR_CLTCIF = 0x10

	// MDMA_C4ESR: MDMA channel 4 error status register
	// Position of TEA field.
	MDMA1_MDMA_C4ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C4ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C4ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C4ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C4ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C4ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C4ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C4ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C4ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C4ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C4ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C4ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C4ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C4ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C4ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C4ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C4ESR_BSE = 0x800

	// MDMA_C4CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C4CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C4CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C4CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C4CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C4CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C4CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C4CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C4CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C4CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C4CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C4CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C4CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C4CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C4CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C4CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C4CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C4CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C4CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C4CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C4CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C4CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C4CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C4CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C4CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C4CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C4CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C4CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C4CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C4CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C4CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C4CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C4CR_SWRQ = 0x10000

	// MDMA_C4TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C4TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C4TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C4TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C4TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C4TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C4TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C4TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C4TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C4TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C4TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C4TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C4TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C4TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C4TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C4TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C4TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C4TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C4TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C4TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C4TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C4TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C4TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C4TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C4TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C4TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C4TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C4TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C4TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C4TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C4TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C4TCR_BWM = 0x80000000

	// MDMA_C4BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C4BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C4BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C4BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C4BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C4BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C4BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C4BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C4BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C4BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C4BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C4SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C4SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C4SAR_SAR_Msk = 0xffffffff

	// MDMA_C4DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C4DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C4DAR_DAR_Msk = 0xffffffff

	// MDMA_C4BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C4BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C4BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C4BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C4BRUR_DUV_Msk = 0xffff0000

	// MDMA_C4LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C4LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C4LAR_LAR_Msk = 0xffffffff

	// MDMA_C4TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C4TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C4TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C4TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C4TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C4TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C4TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C4TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C4TBR_DBUS = 0x20000

	// MDMA_C4MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C4MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C4MAR_MAR_Msk = 0xffffffff

	// MDMA_C4MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C4MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C4MDR_MDR_Msk = 0xffffffff

	// MDMA_C5ISR: MDMA channel 5 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C5ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C5ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C5ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C5ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C5ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C5ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C5ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C5ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C5ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C5ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C5ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C5ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C5ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C5ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C5ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C5ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C5ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C5ISR_CRQA = 0x10000

	// MDMA_C5IFCR: MDMA channel 5 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C5IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C5IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C5IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C5IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C5IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C5IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C5IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C5IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C5IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C5IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C5IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C5IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C5IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C5IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C5IFCR_CLTCIF = 0x10

	// MDMA_C5ESR: MDMA channel 5 error status register
	// Position of TEA field.
	MDMA1_MDMA_C5ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C5ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C5ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C5ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C5ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C5ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C5ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C5ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C5ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C5ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C5ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C5ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C5ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C5ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C5ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C5ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C5ESR_BSE = 0x800

	// MDMA_C5CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C5CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C5CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C5CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C5CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C5CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C5CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C5CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C5CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C5CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C5CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C5CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C5CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C5CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C5CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C5CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C5CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C5CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C5CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C5CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C5CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C5CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C5CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C5CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C5CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C5CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C5CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C5CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C5CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C5CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C5CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C5CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C5CR_SWRQ = 0x10000

	// MDMA_C5TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C5TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C5TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C5TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C5TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C5TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C5TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C5TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C5TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C5TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C5TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C5TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C5TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C5TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C5TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C5TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C5TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C5TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C5TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C5TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C5TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C5TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C5TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C5TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C5TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C5TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C5TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C5TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C5TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C5TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C5TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C5TCR_BWM = 0x80000000

	// MDMA_C5BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C5BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C5BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C5BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C5BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C5BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C5BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C5BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C5BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C5BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C5BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C5SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C5SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C5SAR_SAR_Msk = 0xffffffff

	// MDMA_C5DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C5DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C5DAR_DAR_Msk = 0xffffffff

	// MDMA_C5BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C5BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C5BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C5BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C5BRUR_DUV_Msk = 0xffff0000

	// MDMA_C5LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C5LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C5LAR_LAR_Msk = 0xffffffff

	// MDMA_C5TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C5TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C5TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C5TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C5TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C5TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C5TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C5TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C5TBR_DBUS = 0x20000

	// MDMA_C5MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C5MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C5MAR_MAR_Msk = 0xffffffff

	// MDMA_C5MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C5MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C5MDR_MDR_Msk = 0xffffffff

	// MDMA_C6ISR: MDMA channel 6 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C6ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C6ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C6ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C6ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C6ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C6ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C6ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C6ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C6ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C6ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C6ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C6ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C6ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C6ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C6ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C6ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C6ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C6ISR_CRQA = 0x10000

	// MDMA_C6IFCR: MDMA channel 6 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C6IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C6IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C6IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C6IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C6IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C6IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C6IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C6IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C6IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C6IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C6IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C6IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C6IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C6IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C6IFCR_CLTCIF = 0x10

	// MDMA_C6ESR: MDMA channel 6 error status register
	// Position of TEA field.
	MDMA1_MDMA_C6ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C6ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C6ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C6ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C6ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C6ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C6ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C6ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C6ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C6ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C6ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C6ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C6ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C6ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C6ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C6ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C6ESR_BSE = 0x800

	// MDMA_C6CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C6CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C6CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C6CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C6CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C6CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C6CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C6CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C6CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C6CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C6CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C6CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C6CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C6CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C6CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C6CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C6CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C6CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C6CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C6CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C6CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C6CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C6CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C6CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C6CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C6CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C6CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C6CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C6CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C6CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C6CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C6CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C6CR_SWRQ = 0x10000

	// MDMA_C6TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C6TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C6TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C6TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C6TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C6TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C6TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C6TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C6TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C6TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C6TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C6TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C6TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C6TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C6TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C6TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C6TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C6TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C6TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C6TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C6TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C6TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C6TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C6TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C6TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C6TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C6TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C6TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C6TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C6TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C6TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C6TCR_BWM = 0x80000000

	// MDMA_C6BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C6BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C6BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C6BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C6BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C6BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C6BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C6BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C6BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C6BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C6BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C6SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C6SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C6SAR_SAR_Msk = 0xffffffff

	// MDMA_C6DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C6DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C6DAR_DAR_Msk = 0xffffffff

	// MDMA_C6BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C6BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C6BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C6BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C6BRUR_DUV_Msk = 0xffff0000

	// MDMA_C6LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C6LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C6LAR_LAR_Msk = 0xffffffff

	// MDMA_C6TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C6TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C6TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C6TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C6TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C6TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C6TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C6TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C6TBR_DBUS = 0x20000

	// MDMA_C6MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C6MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C6MAR_MAR_Msk = 0xffffffff

	// MDMA_C6MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C6MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C6MDR_MDR_Msk = 0xffffffff

	// MDMA_C7ISR: MDMA channel 7 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C7ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C7ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C7ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C7ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C7ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C7ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C7ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C7ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C7ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C7ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C7ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C7ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C7ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C7ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C7ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C7ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C7ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C7ISR_CRQA = 0x10000

	// MDMA_C7IFCR: MDMA channel 7 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C7IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C7IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C7IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C7IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C7IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C7IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C7IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C7IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C7IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C7IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C7IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C7IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C7IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C7IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C7IFCR_CLTCIF = 0x10

	// MDMA_C7ESR: MDMA channel 7 error status register
	// Position of TEA field.
	MDMA1_MDMA_C7ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C7ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C7ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C7ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C7ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C7ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C7ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C7ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C7ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C7ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C7ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C7ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C7ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C7ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C7ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C7ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C7ESR_BSE = 0x800

	// MDMA_C7CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C7CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C7CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C7CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C7CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C7CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C7CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C7CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C7CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C7CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C7CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C7CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C7CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C7CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C7CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C7CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C7CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C7CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C7CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C7CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C7CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C7CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C7CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C7CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C7CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C7CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C7CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C7CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C7CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C7CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C7CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C7CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C7CR_SWRQ = 0x10000

	// MDMA_C7TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C7TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C7TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C7TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C7TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C7TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C7TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C7TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C7TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C7TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C7TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C7TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C7TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C7TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C7TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C7TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C7TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C7TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C7TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C7TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C7TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C7TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C7TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C7TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C7TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C7TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C7TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C7TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C7TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C7TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C7TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C7TCR_BWM = 0x80000000

	// MDMA_C7BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C7BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C7BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C7BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C7BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C7BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C7BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C7BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C7BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C7BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C7BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C7SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C7SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C7SAR_SAR_Msk = 0xffffffff

	// MDMA_C7DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C7DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C7DAR_DAR_Msk = 0xffffffff

	// MDMA_C7BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C7BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C7BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C7BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C7BRUR_DUV_Msk = 0xffff0000

	// MDMA_C7LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C7LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C7LAR_LAR_Msk = 0xffffffff

	// MDMA_C7TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C7TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C7TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C7TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C7TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C7TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C7TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C7TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C7TBR_DBUS = 0x20000

	// MDMA_C7MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C7MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C7MAR_MAR_Msk = 0xffffffff

	// MDMA_C7MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C7MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C7MDR_MDR_Msk = 0xffffffff

	// MDMA_C8ISR: MDMA channel 8 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C8ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C8ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C8ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C8ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C8ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C8ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C8ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C8ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C8ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C8ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C8ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C8ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C8ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C8ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C8ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C8ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C8ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C8ISR_CRQA = 0x10000

	// MDMA_C8IFCR: MDMA channel 8 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C8IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C8IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C8IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C8IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C8IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C8IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C8IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C8IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C8IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C8IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C8IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C8IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C8IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C8IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C8IFCR_CLTCIF = 0x10

	// MDMA_C8ESR: MDMA channel 8 error status register
	// Position of TEA field.
	MDMA1_MDMA_C8ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C8ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C8ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C8ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C8ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C8ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C8ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C8ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C8ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C8ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C8ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C8ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C8ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C8ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C8ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C8ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C8ESR_BSE = 0x800

	// MDMA_C8CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C8CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C8CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C8CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C8CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C8CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C8CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C8CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C8CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C8CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C8CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C8CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C8CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C8CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C8CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C8CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C8CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C8CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C8CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C8CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C8CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C8CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C8CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C8CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C8CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C8CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C8CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C8CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C8CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C8CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C8CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C8CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C8CR_SWRQ = 0x10000

	// MDMA_C8TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C8TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C8TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C8TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C8TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C8TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C8TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C8TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C8TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C8TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C8TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C8TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C8TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C8TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C8TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C8TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C8TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C8TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C8TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C8TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C8TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C8TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C8TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C8TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C8TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C8TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C8TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C8TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C8TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C8TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C8TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C8TCR_BWM = 0x80000000

	// MDMA_C8BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C8BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C8BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C8BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C8BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C8BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C8BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C8BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C8BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C8BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C8BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C8SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C8SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C8SAR_SAR_Msk = 0xffffffff

	// MDMA_C8DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C8DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C8DAR_DAR_Msk = 0xffffffff

	// MDMA_C8BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C8BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C8BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C8BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C8BRUR_DUV_Msk = 0xffff0000

	// MDMA_C8LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C8LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C8LAR_LAR_Msk = 0xffffffff

	// MDMA_C8TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C8TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C8TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C8TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C8TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C8TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C8TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C8TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C8TBR_DBUS = 0x20000

	// MDMA_C8MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C8MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C8MAR_MAR_Msk = 0xffffffff

	// MDMA_C8MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C8MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C8MDR_MDR_Msk = 0xffffffff

	// MDMA_C9ISR: MDMA channel 9 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C9ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C9ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C9ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C9ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C9ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C9ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C9ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C9ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C9ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C9ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C9ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C9ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C9ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C9ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C9ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C9ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C9ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C9ISR_CRQA = 0x10000

	// MDMA_C9IFCR: MDMA channel 9 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C9IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C9IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C9IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C9IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C9IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C9IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C9IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C9IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C9IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C9IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C9IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C9IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C9IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C9IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C9IFCR_CLTCIF = 0x10

	// MDMA_C9ESR: MDMA channel 9 error status register
	// Position of TEA field.
	MDMA1_MDMA_C9ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C9ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C9ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C9ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C9ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C9ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C9ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C9ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C9ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C9ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C9ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C9ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C9ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C9ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C9ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C9ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C9ESR_BSE = 0x800

	// MDMA_C9CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C9CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C9CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C9CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C9CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C9CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C9CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C9CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C9CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C9CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C9CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C9CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C9CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C9CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C9CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C9CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C9CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C9CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C9CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C9CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C9CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C9CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C9CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C9CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C9CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C9CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C9CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C9CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C9CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C9CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C9CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C9CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C9CR_SWRQ = 0x10000

	// MDMA_C9TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C9TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C9TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C9TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C9TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C9TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C9TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C9TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C9TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C9TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C9TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C9TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C9TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C9TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C9TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C9TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C9TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C9TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C9TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C9TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C9TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C9TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C9TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C9TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C9TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C9TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C9TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C9TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C9TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C9TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C9TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C9TCR_BWM = 0x80000000

	// MDMA_C9BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C9BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C9BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C9BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C9BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C9BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C9BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C9BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C9BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C9BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C9BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C9SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C9SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C9SAR_SAR_Msk = 0xffffffff

	// MDMA_C9DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C9DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C9DAR_DAR_Msk = 0xffffffff

	// MDMA_C9BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C9BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C9BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C9BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C9BRUR_DUV_Msk = 0xffff0000

	// MDMA_C9LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C9LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C9LAR_LAR_Msk = 0xffffffff

	// MDMA_C9TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C9TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C9TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C9TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C9TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C9TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C9TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C9TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C9TBR_DBUS = 0x20000

	// MDMA_C9MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C9MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C9MAR_MAR_Msk = 0xffffffff

	// MDMA_C9MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C9MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C9MDR_MDR_Msk = 0xffffffff

	// MDMA_C10ISR: MDMA channel 10 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C10ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C10ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C10ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C10ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C10ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C10ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C10ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C10ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C10ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C10ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C10ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C10ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C10ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C10ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C10ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C10ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C10ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C10ISR_CRQA = 0x10000

	// MDMA_C10IFCR: MDMA channel 10 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C10IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C10IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C10IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C10IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C10IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C10IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C10IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C10IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C10IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C10IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C10IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C10IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C10IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C10IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C10IFCR_CLTCIF = 0x10

	// MDMA_C10ESR: MDMA channel 10 error status register
	// Position of TEA field.
	MDMA1_MDMA_C10ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C10ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C10ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C10ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C10ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C10ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C10ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C10ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C10ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C10ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C10ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C10ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C10ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C10ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C10ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C10ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C10ESR_BSE = 0x800

	// MDMA_C10CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C10CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C10CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C10CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C10CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C10CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C10CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C10CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C10CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C10CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C10CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C10CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C10CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C10CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C10CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C10CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C10CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C10CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C10CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C10CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C10CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C10CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C10CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C10CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C10CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C10CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C10CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C10CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C10CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C10CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C10CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C10CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C10CR_SWRQ = 0x10000

	// MDMA_C10TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C10TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C10TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C10TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C10TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C10TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C10TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C10TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C10TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C10TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C10TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C10TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C10TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C10TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C10TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C10TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C10TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C10TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C10TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C10TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C10TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C10TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C10TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C10TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C10TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C10TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C10TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C10TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C10TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C10TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C10TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C10TCR_BWM = 0x80000000

	// MDMA_C10BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C10BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C10BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C10BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C10BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C10BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C10BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C10BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C10BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C10BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C10BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C10SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C10SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C10SAR_SAR_Msk = 0xffffffff

	// MDMA_C10DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C10DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C10DAR_DAR_Msk = 0xffffffff

	// MDMA_C10BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C10BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C10BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C10BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C10BRUR_DUV_Msk = 0xffff0000

	// MDMA_C10LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C10LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C10LAR_LAR_Msk = 0xffffffff

	// MDMA_C10TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C10TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C10TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C10TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C10TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C10TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C10TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C10TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C10TBR_DBUS = 0x20000

	// MDMA_C10MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C10MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C10MAR_MAR_Msk = 0xffffffff

	// MDMA_C10MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C10MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C10MDR_MDR_Msk = 0xffffffff

	// MDMA_C11ISR: MDMA channel 11 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C11ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C11ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C11ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C11ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C11ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C11ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C11ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C11ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C11ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C11ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C11ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C11ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C11ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C11ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C11ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C11ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C11ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C11ISR_CRQA = 0x10000

	// MDMA_C11IFCR: MDMA channel 11 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C11IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C11IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C11IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C11IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C11IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C11IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C11IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C11IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C11IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C11IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C11IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C11IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C11IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C11IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C11IFCR_CLTCIF = 0x10

	// MDMA_C11ESR: MDMA channel 11 error status register
	// Position of TEA field.
	MDMA1_MDMA_C11ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C11ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C11ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C11ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C11ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C11ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C11ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C11ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C11ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C11ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C11ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C11ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C11ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C11ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C11ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C11ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C11ESR_BSE = 0x800

	// MDMA_C11CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C11CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C11CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C11CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C11CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C11CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C11CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C11CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C11CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C11CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C11CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C11CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C11CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C11CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C11CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C11CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C11CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C11CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C11CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C11CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C11CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C11CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C11CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C11CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C11CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C11CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C11CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C11CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C11CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C11CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C11CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C11CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C11CR_SWRQ = 0x10000

	// MDMA_C11TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C11TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C11TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C11TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C11TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C11TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C11TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C11TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C11TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C11TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C11TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C11TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C11TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C11TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C11TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C11TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C11TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C11TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C11TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C11TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C11TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C11TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C11TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C11TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C11TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C11TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C11TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C11TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C11TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C11TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C11TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C11TCR_BWM = 0x80000000

	// MDMA_C11BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C11BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C11BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C11BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C11BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C11BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C11BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C11BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C11BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C11BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C11BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C11SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C11SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C11SAR_SAR_Msk = 0xffffffff

	// MDMA_C11DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C11DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C11DAR_DAR_Msk = 0xffffffff

	// MDMA_C11BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C11BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C11BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C11BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C11BRUR_DUV_Msk = 0xffff0000

	// MDMA_C11LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C11LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C11LAR_LAR_Msk = 0xffffffff

	// MDMA_C11TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C11TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C11TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C11TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C11TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C11TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C11TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C11TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C11TBR_DBUS = 0x20000

	// MDMA_C11MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C11MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C11MAR_MAR_Msk = 0xffffffff

	// MDMA_C11MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C11MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C11MDR_MDR_Msk = 0xffffffff

	// MDMA_C12ISR: MDMA channel 12 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C12ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C12ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C12ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C12ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C12ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C12ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C12ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C12ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C12ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C12ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C12ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C12ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C12ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C12ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C12ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C12ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C12ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C12ISR_CRQA = 0x10000

	// MDMA_C12IFCR: MDMA channel 12 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C12IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C12IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C12IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C12IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C12IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C12IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C12IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C12IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C12IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C12IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C12IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C12IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C12IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C12IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C12IFCR_CLTCIF = 0x10

	// MDMA_C12ESR: MDMA channel 12 error status register
	// Position of TEA field.
	MDMA1_MDMA_C12ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C12ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C12ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C12ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C12ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C12ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C12ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C12ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C12ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C12ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C12ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C12ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C12ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C12ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C12ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C12ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C12ESR_BSE = 0x800

	// MDMA_C12CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C12CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C12CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C12CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C12CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C12CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C12CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C12CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C12CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C12CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C12CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C12CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C12CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C12CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C12CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C12CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C12CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C12CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C12CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C12CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C12CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C12CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C12CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C12CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C12CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C12CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C12CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C12CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C12CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C12CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C12CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C12CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C12CR_SWRQ = 0x10000

	// MDMA_C12TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C12TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C12TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C12TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C12TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C12TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C12TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C12TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C12TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C12TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C12TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C12TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C12TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C12TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C12TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C12TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C12TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C12TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C12TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C12TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C12TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C12TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C12TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C12TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C12TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C12TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C12TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C12TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C12TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C12TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C12TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C12TCR_BWM = 0x80000000

	// MDMA_C12BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C12BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C12BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C12BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C12BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C12BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C12BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C12BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C12BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C12BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C12BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C12SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C12SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C12SAR_SAR_Msk = 0xffffffff

	// MDMA_C12DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C12DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C12DAR_DAR_Msk = 0xffffffff

	// MDMA_C12BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C12BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C12BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C12BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C12BRUR_DUV_Msk = 0xffff0000

	// MDMA_C12LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C12LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C12LAR_LAR_Msk = 0xffffffff

	// MDMA_C12TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C12TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C12TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C12TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C12TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C12TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C12TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C12TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C12TBR_DBUS = 0x20000

	// MDMA_C12MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C12MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C12MAR_MAR_Msk = 0xffffffff

	// MDMA_C12MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C12MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C12MDR_MDR_Msk = 0xffffffff

	// MDMA_C13ISR: MDMA channel 13 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C13ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C13ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C13ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C13ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C13ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C13ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C13ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C13ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C13ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C13ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C13ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C13ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C13ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C13ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C13ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C13ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C13ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C13ISR_CRQA = 0x10000

	// MDMA_C13IFCR: MDMA channel 13 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C13IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C13IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C13IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C13IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C13IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C13IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C13IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C13IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C13IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C13IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C13IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C13IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C13IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C13IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C13IFCR_CLTCIF = 0x10

	// MDMA_C13ESR: MDMA channel 13 error status register
	// Position of TEA field.
	MDMA1_MDMA_C13ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C13ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C13ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C13ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C13ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C13ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C13ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C13ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C13ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C13ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C13ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C13ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C13ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C13ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C13ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C13ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C13ESR_BSE = 0x800

	// MDMA_C13CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C13CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C13CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C13CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C13CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C13CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C13CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C13CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C13CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C13CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C13CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C13CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C13CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C13CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C13CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C13CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C13CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C13CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C13CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C13CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C13CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C13CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C13CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C13CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C13CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C13CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C13CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C13CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C13CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C13CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C13CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C13CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C13CR_SWRQ = 0x10000

	// MDMA_C13TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C13TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C13TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C13TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C13TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C13TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C13TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C13TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C13TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C13TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C13TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C13TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C13TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C13TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C13TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C13TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C13TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C13TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C13TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C13TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C13TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C13TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C13TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C13TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C13TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C13TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C13TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C13TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C13TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C13TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C13TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C13TCR_BWM = 0x80000000

	// MDMA_C13BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C13BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C13BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C13BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C13BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C13BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C13BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C13BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C13BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C13BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C13BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C13SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C13SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C13SAR_SAR_Msk = 0xffffffff

	// MDMA_C13DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C13DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C13DAR_DAR_Msk = 0xffffffff

	// MDMA_C13BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C13BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C13BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C13BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C13BRUR_DUV_Msk = 0xffff0000

	// MDMA_C13LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C13LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C13LAR_LAR_Msk = 0xffffffff

	// MDMA_C13TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C13TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C13TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C13TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C13TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C13TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C13TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C13TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C13TBR_DBUS = 0x20000

	// MDMA_C13MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C13MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C13MAR_MAR_Msk = 0xffffffff

	// MDMA_C13MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C13MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C13MDR_MDR_Msk = 0xffffffff

	// MDMA_C14ISR: MDMA channel 14 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C14ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C14ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C14ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C14ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C14ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C14ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C14ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C14ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C14ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C14ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C14ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C14ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C14ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C14ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C14ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C14ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C14ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C14ISR_CRQA = 0x10000

	// MDMA_C14IFCR: MDMA channel 14 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C14IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C14IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C14IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C14IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C14IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C14IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C14IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C14IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C14IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C14IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C14IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C14IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C14IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C14IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C14IFCR_CLTCIF = 0x10

	// MDMA_C14ESR: MDMA channel 14 error status register
	// Position of TEA field.
	MDMA1_MDMA_C14ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C14ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C14ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C14ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C14ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C14ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C14ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C14ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C14ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C14ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C14ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C14ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C14ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C14ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C14ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C14ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C14ESR_BSE = 0x800

	// MDMA_C14CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C14CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C14CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C14CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C14CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C14CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C14CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C14CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C14CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C14CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C14CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C14CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C14CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C14CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C14CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C14CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C14CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C14CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C14CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C14CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C14CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C14CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C14CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C14CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C14CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C14CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C14CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C14CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C14CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C14CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C14CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C14CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C14CR_SWRQ = 0x10000

	// MDMA_C14TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C14TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C14TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C14TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C14TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C14TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C14TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C14TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C14TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C14TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C14TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C14TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C14TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C14TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C14TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C14TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C14TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C14TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C14TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C14TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C14TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C14TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C14TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C14TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C14TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C14TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C14TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C14TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C14TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C14TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C14TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C14TCR_BWM = 0x80000000

	// MDMA_C14BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C14BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C14BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C14BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C14BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C14BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C14BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C14BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C14BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C14BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C14BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C14SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C14SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C14SAR_SAR_Msk = 0xffffffff

	// MDMA_C14DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C14DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C14DAR_DAR_Msk = 0xffffffff

	// MDMA_C14BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C14BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C14BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C14BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C14BRUR_DUV_Msk = 0xffff0000

	// MDMA_C14LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C14LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C14LAR_LAR_Msk = 0xffffffff

	// MDMA_C14TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C14TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C14TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C14TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C14TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C14TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C14TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C14TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C14TBR_DBUS = 0x20000

	// MDMA_C14MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C14MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C14MAR_MAR_Msk = 0xffffffff

	// MDMA_C14MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C14MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C14MDR_MDR_Msk = 0xffffffff

	// MDMA_C15ISR: MDMA channel 15 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C15ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C15ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C15ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C15ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C15ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C15ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C15ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C15ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C15ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C15ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C15ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C15ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C15ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C15ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C15ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C15ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C15ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C15ISR_CRQA = 0x10000

	// MDMA_C15IFCR: MDMA channel 15 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C15IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C15IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C15IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C15IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C15IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C15IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C15IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C15IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C15IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C15IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C15IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C15IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C15IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C15IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C15IFCR_CLTCIF = 0x10

	// MDMA_C15ESR: MDMA channel 15 error status register
	// Position of TEA field.
	MDMA1_MDMA_C15ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C15ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C15ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C15ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C15ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C15ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C15ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C15ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C15ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C15ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C15ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C15ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C15ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C15ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C15ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C15ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C15ESR_BSE = 0x800

	// MDMA_C15CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C15CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C15CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C15CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C15CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C15CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C15CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C15CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C15CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C15CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C15CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C15CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C15CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C15CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C15CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C15CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C15CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C15CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C15CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C15CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C15CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C15CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C15CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C15CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C15CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C15CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C15CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C15CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C15CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C15CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C15CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C15CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C15CR_SWRQ = 0x10000

	// MDMA_C15TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C15TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C15TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C15TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C15TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C15TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C15TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C15TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C15TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C15TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C15TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C15TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C15TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C15TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C15TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C15TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C15TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C15TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C15TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C15TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C15TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C15TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C15TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C15TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C15TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C15TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C15TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C15TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C15TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C15TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C15TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C15TCR_BWM = 0x80000000

	// MDMA_C15BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C15BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C15BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C15BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C15BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C15BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C15BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C15BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C15BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C15BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C15BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C15SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C15SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C15SAR_SAR_Msk = 0xffffffff

	// MDMA_C15DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C15DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C15DAR_DAR_Msk = 0xffffffff

	// MDMA_C15BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C15BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C15BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C15BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C15BRUR_DUV_Msk = 0xffff0000

	// MDMA_C15LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C15LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C15LAR_LAR_Msk = 0xffffffff

	// MDMA_C15TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C15TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C15TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C15TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C15TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C15TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C15TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C15TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C15TBR_DBUS = 0x20000

	// MDMA_C15MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C15MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C15MAR_MAR_Msk = 0xffffffff

	// MDMA_C15MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C15MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C15MDR_MDR_Msk = 0xffffffff

	// MDMA_C16ISR: MDMA channel 16 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C16ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C16ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C16ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C16ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C16ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C16ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C16ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C16ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C16ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C16ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C16ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C16ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C16ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C16ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C16ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C16ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C16ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C16ISR_CRQA = 0x10000

	// MDMA_C16IFCR: MDMA channel 16 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C16IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C16IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C16IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C16IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C16IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C16IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C16IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C16IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C16IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C16IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C16IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C16IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C16IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C16IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C16IFCR_CLTCIF = 0x10

	// MDMA_C16ESR: MDMA channel 16 error status register
	// Position of TEA field.
	MDMA1_MDMA_C16ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C16ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C16ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C16ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C16ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C16ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C16ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C16ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C16ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C16ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C16ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C16ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C16ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C16ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C16ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C16ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C16ESR_BSE = 0x800

	// MDMA_C16CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C16CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C16CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C16CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C16CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C16CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C16CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C16CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C16CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C16CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C16CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C16CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C16CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C16CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C16CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C16CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C16CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C16CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C16CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C16CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C16CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C16CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C16CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C16CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C16CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C16CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C16CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C16CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C16CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C16CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C16CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C16CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C16CR_SWRQ = 0x10000

	// MDMA_C16TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C16TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C16TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C16TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C16TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C16TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C16TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C16TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C16TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C16TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C16TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C16TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C16TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C16TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C16TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C16TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C16TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C16TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C16TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C16TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C16TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C16TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C16TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C16TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C16TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C16TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C16TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C16TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C16TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C16TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C16TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C16TCR_BWM = 0x80000000

	// MDMA_C16BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C16BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C16BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C16BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C16BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C16BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C16BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C16BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C16BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C16BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C16BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C16SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C16SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C16SAR_SAR_Msk = 0xffffffff

	// MDMA_C16DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C16DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C16DAR_DAR_Msk = 0xffffffff

	// MDMA_C16BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C16BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C16BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C16BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C16BRUR_DUV_Msk = 0xffff0000

	// MDMA_C16LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C16LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C16LAR_LAR_Msk = 0xffffffff

	// MDMA_C16TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C16TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C16TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C16TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C16TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C16TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C16TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C16TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C16TBR_DBUS = 0x20000

	// MDMA_C16MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C16MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C16MAR_MAR_Msk = 0xffffffff

	// MDMA_C16MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C16MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C16MDR_MDR_Msk = 0xffffffff

	// MDMA_C17ISR: MDMA channel 17 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C17ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C17ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C17ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C17ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C17ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C17ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C17ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C17ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C17ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C17ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C17ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C17ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C17ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C17ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C17ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C17ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C17ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C17ISR_CRQA = 0x10000

	// MDMA_C17IFCR: MDMA channel 17 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C17IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C17IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C17IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C17IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C17IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C17IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C17IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C17IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C17IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C17IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C17IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C17IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C17IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C17IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C17IFCR_CLTCIF = 0x10

	// MDMA_C17ESR: MDMA channel 17 error status register
	// Position of TEA field.
	MDMA1_MDMA_C17ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C17ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C17ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C17ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C17ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C17ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C17ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C17ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C17ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C17ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C17ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C17ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C17ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C17ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C17ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C17ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C17ESR_BSE = 0x800

	// MDMA_C17CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C17CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C17CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C17CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C17CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C17CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C17CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C17CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C17CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C17CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C17CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C17CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C17CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C17CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C17CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C17CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C17CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C17CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C17CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C17CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C17CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C17CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C17CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C17CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C17CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C17CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C17CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C17CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C17CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C17CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C17CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C17CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C17CR_SWRQ = 0x10000

	// MDMA_C17TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C17TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C17TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C17TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C17TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C17TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C17TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C17TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C17TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C17TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C17TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C17TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C17TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C17TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C17TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C17TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C17TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C17TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C17TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C17TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C17TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C17TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C17TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C17TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C17TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C17TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C17TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C17TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C17TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C17TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C17TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C17TCR_BWM = 0x80000000

	// MDMA_C17BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C17BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C17BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C17BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C17BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C17BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C17BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C17BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C17BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C17BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C17BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C17SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C17SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C17SAR_SAR_Msk = 0xffffffff

	// MDMA_C17DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C17DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C17DAR_DAR_Msk = 0xffffffff

	// MDMA_C17BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C17BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C17BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C17BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C17BRUR_DUV_Msk = 0xffff0000

	// MDMA_C17LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C17LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C17LAR_LAR_Msk = 0xffffffff

	// MDMA_C17TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C17TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C17TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C17TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C17TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C17TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C17TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C17TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C17TBR_DBUS = 0x20000

	// MDMA_C17MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C17MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C17MAR_MAR_Msk = 0xffffffff

	// MDMA_C17MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C17MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C17MDR_MDR_Msk = 0xffffffff

	// MDMA_C18ISR: MDMA channel 18 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C18ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C18ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C18ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C18ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C18ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C18ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C18ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C18ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C18ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C18ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C18ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C18ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C18ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C18ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C18ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C18ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C18ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C18ISR_CRQA = 0x10000

	// MDMA_C18IFCR: MDMA channel 18 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C18IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C18IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C18IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C18IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C18IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C18IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C18IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C18IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C18IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C18IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C18IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C18IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C18IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C18IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C18IFCR_CLTCIF = 0x10

	// MDMA_C18ESR: MDMA channel 18 error status register
	// Position of TEA field.
	MDMA1_MDMA_C18ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C18ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C18ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C18ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C18ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C18ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C18ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C18ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C18ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C18ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C18ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C18ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C18ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C18ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C18ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C18ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C18ESR_BSE = 0x800

	// MDMA_C18CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C18CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C18CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C18CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C18CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C18CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C18CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C18CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C18CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C18CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C18CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C18CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C18CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C18CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C18CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C18CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C18CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C18CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C18CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C18CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C18CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C18CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C18CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C18CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C18CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C18CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C18CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C18CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C18CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C18CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C18CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C18CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C18CR_SWRQ = 0x10000

	// MDMA_C18TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C18TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C18TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C18TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C18TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C18TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C18TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C18TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C18TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C18TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C18TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C18TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C18TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C18TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C18TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C18TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C18TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C18TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C18TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C18TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C18TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C18TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C18TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C18TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C18TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C18TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C18TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C18TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C18TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C18TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C18TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C18TCR_BWM = 0x80000000

	// MDMA_C18BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C18BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C18BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C18BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C18BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C18BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C18BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C18BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C18BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C18BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C18BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C18SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C18SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C18SAR_SAR_Msk = 0xffffffff

	// MDMA_C18DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C18DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C18DAR_DAR_Msk = 0xffffffff

	// MDMA_C18BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C18BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C18BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C18BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C18BRUR_DUV_Msk = 0xffff0000

	// MDMA_C18LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C18LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C18LAR_LAR_Msk = 0xffffffff

	// MDMA_C18TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C18TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C18TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C18TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C18TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C18TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C18TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C18TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C18TBR_DBUS = 0x20000

	// MDMA_C18MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C18MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C18MAR_MAR_Msk = 0xffffffff

	// MDMA_C18MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C18MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C18MDR_MDR_Msk = 0xffffffff

	// MDMA_C19ISR: MDMA channel 19 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C19ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C19ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C19ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C19ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C19ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C19ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C19ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C19ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C19ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C19ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C19ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C19ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C19ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C19ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C19ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C19ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C19ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C19ISR_CRQA = 0x10000

	// MDMA_C19IFCR: MDMA channel 19 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C19IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C19IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C19IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C19IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C19IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C19IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C19IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C19IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C19IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C19IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C19IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C19IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C19IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C19IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C19IFCR_CLTCIF = 0x10

	// MDMA_C19ESR: MDMA channel 19 error status register
	// Position of TEA field.
	MDMA1_MDMA_C19ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C19ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C19ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C19ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C19ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C19ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C19ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C19ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C19ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C19ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C19ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C19ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C19ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C19ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C19ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C19ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C19ESR_BSE = 0x800

	// MDMA_C19CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C19CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C19CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C19CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C19CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C19CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C19CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C19CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C19CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C19CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C19CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C19CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C19CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C19CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C19CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C19CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C19CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C19CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C19CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C19CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C19CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C19CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C19CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C19CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C19CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C19CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C19CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C19CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C19CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C19CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C19CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C19CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C19CR_SWRQ = 0x10000

	// MDMA_C19TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C19TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C19TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C19TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C19TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C19TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C19TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C19TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C19TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C19TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C19TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C19TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C19TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C19TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C19TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C19TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C19TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C19TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C19TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C19TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C19TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C19TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C19TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C19TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C19TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C19TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C19TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C19TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C19TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C19TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C19TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C19TCR_BWM = 0x80000000

	// MDMA_C19BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C19BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C19BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C19BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C19BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C19BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C19BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C19BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C19BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C19BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C19BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C19SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C19SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C19SAR_SAR_Msk = 0xffffffff

	// MDMA_C19DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C19DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C19DAR_DAR_Msk = 0xffffffff

	// MDMA_C19BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C19BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C19BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C19BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C19BRUR_DUV_Msk = 0xffff0000

	// MDMA_C19LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C19LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C19LAR_LAR_Msk = 0xffffffff

	// MDMA_C19TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C19TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C19TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C19TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C19TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C19TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C19TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C19TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C19TBR_DBUS = 0x20000

	// MDMA_C19MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C19MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C19MAR_MAR_Msk = 0xffffffff

	// MDMA_C19MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C19MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C19MDR_MDR_Msk = 0xffffffff

	// MDMA_C20ISR: MDMA channel 20 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C20ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C20ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C20ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C20ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C20ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C20ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C20ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C20ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C20ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C20ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C20ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C20ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C20ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C20ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C20ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C20ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C20ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C20ISR_CRQA = 0x10000

	// MDMA_C20IFCR: MDMA channel 20 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C20IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C20IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C20IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C20IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C20IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C20IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C20IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C20IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C20IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C20IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C20IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C20IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C20IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C20IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C20IFCR_CLTCIF = 0x10

	// MDMA_C20ESR: MDMA channel 20 error status register
	// Position of TEA field.
	MDMA1_MDMA_C20ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C20ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C20ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C20ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C20ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C20ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C20ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C20ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C20ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C20ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C20ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C20ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C20ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C20ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C20ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C20ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C20ESR_BSE = 0x800

	// MDMA_C20CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C20CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C20CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C20CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C20CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C20CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C20CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C20CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C20CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C20CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C20CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C20CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C20CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C20CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C20CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C20CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C20CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C20CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C20CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C20CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C20CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C20CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C20CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C20CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C20CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C20CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C20CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C20CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C20CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C20CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C20CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C20CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C20CR_SWRQ = 0x10000

	// MDMA_C20TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C20TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C20TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C20TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C20TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C20TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C20TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C20TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C20TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C20TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C20TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C20TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C20TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C20TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C20TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C20TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C20TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C20TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C20TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C20TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C20TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C20TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C20TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C20TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C20TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C20TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C20TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C20TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C20TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C20TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C20TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C20TCR_BWM = 0x80000000

	// MDMA_C20BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C20BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C20BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C20BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C20BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C20BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C20BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C20BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C20BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C20BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C20BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C20SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C20SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C20SAR_SAR_Msk = 0xffffffff

	// MDMA_C20DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C20DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C20DAR_DAR_Msk = 0xffffffff

	// MDMA_C20BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C20BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C20BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C20BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C20BRUR_DUV_Msk = 0xffff0000

	// MDMA_C20LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C20LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C20LAR_LAR_Msk = 0xffffffff

	// MDMA_C20TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C20TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C20TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C20TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C20TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C20TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C20TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C20TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C20TBR_DBUS = 0x20000

	// MDMA_C20MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C20MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C20MAR_MAR_Msk = 0xffffffff

	// MDMA_C20MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C20MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C20MDR_MDR_Msk = 0xffffffff

	// MDMA_C21ISR: MDMA channel 21 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C21ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C21ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C21ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C21ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C21ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C21ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C21ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C21ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C21ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C21ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C21ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C21ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C21ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C21ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C21ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C21ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C21ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C21ISR_CRQA = 0x10000

	// MDMA_C21IFCR: MDMA channel 21 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C21IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C21IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C21IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C21IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C21IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C21IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C21IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C21IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C21IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C21IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C21IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C21IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C21IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C21IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C21IFCR_CLTCIF = 0x10

	// MDMA_C21ESR: MDMA channel 21 error status register
	// Position of TEA field.
	MDMA1_MDMA_C21ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C21ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C21ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C21ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C21ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C21ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C21ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C21ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C21ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C21ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C21ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C21ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C21ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C21ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C21ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C21ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C21ESR_BSE = 0x800

	// MDMA_C21CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C21CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C21CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C21CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C21CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C21CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C21CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C21CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C21CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C21CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C21CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C21CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C21CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C21CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C21CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C21CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C21CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C21CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C21CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C21CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C21CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C21CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C21CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C21CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C21CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C21CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C21CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C21CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C21CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C21CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C21CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C21CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C21CR_SWRQ = 0x10000

	// MDMA_C21TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C21TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C21TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C21TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C21TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C21TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C21TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C21TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C21TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C21TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C21TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C21TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C21TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C21TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C21TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C21TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C21TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C21TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C21TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C21TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C21TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C21TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C21TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C21TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C21TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C21TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C21TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C21TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C21TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C21TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C21TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C21TCR_BWM = 0x80000000

	// MDMA_C21BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C21BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C21BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C21BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C21BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C21BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C21BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C21BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C21BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C21BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C21BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C21SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C21SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C21SAR_SAR_Msk = 0xffffffff

	// MDMA_C21DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C21DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C21DAR_DAR_Msk = 0xffffffff

	// MDMA_C21BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C21BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C21BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C21BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C21BRUR_DUV_Msk = 0xffff0000

	// MDMA_C21LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C21LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C21LAR_LAR_Msk = 0xffffffff

	// MDMA_C21TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C21TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C21TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C21TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C21TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C21TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C21TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C21TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C21TBR_DBUS = 0x20000

	// MDMA_C21MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C21MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C21MAR_MAR_Msk = 0xffffffff

	// MDMA_C21MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C21MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C21MDR_MDR_Msk = 0xffffffff

	// MDMA_C22ISR: MDMA channel 22 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C22ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C22ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C22ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C22ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C22ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C22ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C22ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C22ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C22ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C22ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C22ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C22ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C22ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C22ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C22ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C22ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C22ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C22ISR_CRQA = 0x10000

	// MDMA_C22IFCR: MDMA channel 22 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C22IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C22IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C22IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C22IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C22IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C22IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C22IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C22IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C22IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C22IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C22IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C22IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C22IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C22IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C22IFCR_CLTCIF = 0x10

	// MDMA_C22ESR: MDMA channel 22 error status register
	// Position of TEA field.
	MDMA1_MDMA_C22ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C22ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C22ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C22ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C22ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C22ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C22ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C22ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C22ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C22ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C22ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C22ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C22ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C22ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C22ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C22ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C22ESR_BSE = 0x800

	// MDMA_C22CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C22CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C22CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C22CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C22CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C22CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C22CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C22CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C22CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C22CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C22CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C22CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C22CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C22CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C22CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C22CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C22CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C22CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C22CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C22CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C22CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C22CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C22CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C22CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C22CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C22CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C22CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C22CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C22CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C22CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C22CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C22CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C22CR_SWRQ = 0x10000

	// MDMA_C22TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C22TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C22TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C22TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C22TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C22TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C22TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C22TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C22TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C22TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C22TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C22TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C22TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C22TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C22TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C22TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C22TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C22TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C22TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C22TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C22TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C22TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C22TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C22TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C22TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C22TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C22TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C22TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C22TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C22TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C22TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C22TCR_BWM = 0x80000000

	// MDMA_C22BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C22BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C22BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C22BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C22BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C22BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C22BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C22BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C22BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C22BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C22BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C22SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C22SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C22SAR_SAR_Msk = 0xffffffff

	// MDMA_C22DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C22DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C22DAR_DAR_Msk = 0xffffffff

	// MDMA_C22BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C22BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C22BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C22BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C22BRUR_DUV_Msk = 0xffff0000

	// MDMA_C22LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C22LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C22LAR_LAR_Msk = 0xffffffff

	// MDMA_C22TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C22TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C22TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C22TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C22TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C22TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C22TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C22TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C22TBR_DBUS = 0x20000

	// MDMA_C22MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C22MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C22MAR_MAR_Msk = 0xffffffff

	// MDMA_C22MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C22MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C22MDR_MDR_Msk = 0xffffffff

	// MDMA_C23ISR: MDMA channel 23 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C23ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C23ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C23ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C23ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C23ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C23ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C23ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C23ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C23ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C23ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C23ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C23ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C23ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C23ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C23ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C23ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C23ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C23ISR_CRQA = 0x10000

	// MDMA_C23IFCR: MDMA channel 23 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C23IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C23IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C23IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C23IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C23IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C23IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C23IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C23IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C23IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C23IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C23IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C23IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C23IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C23IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C23IFCR_CLTCIF = 0x10

	// MDMA_C23ESR: MDMA channel 23 error status register
	// Position of TEA field.
	MDMA1_MDMA_C23ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C23ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C23ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C23ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C23ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C23ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C23ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C23ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C23ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C23ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C23ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C23ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C23ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C23ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C23ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C23ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C23ESR_BSE = 0x800

	// MDMA_C23CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C23CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C23CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C23CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C23CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C23CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C23CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C23CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C23CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C23CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C23CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C23CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C23CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C23CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C23CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C23CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C23CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C23CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C23CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C23CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C23CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C23CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C23CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C23CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C23CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C23CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C23CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C23CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C23CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C23CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C23CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C23CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C23CR_SWRQ = 0x10000

	// MDMA_C23TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C23TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C23TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C23TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C23TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C23TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C23TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C23TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C23TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C23TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C23TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C23TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C23TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C23TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C23TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C23TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C23TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C23TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C23TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C23TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C23TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C23TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C23TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C23TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C23TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C23TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C23TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C23TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C23TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C23TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C23TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C23TCR_BWM = 0x80000000

	// MDMA_C23BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C23BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C23BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C23BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C23BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C23BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C23BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C23BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C23BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C23BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C23BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C23SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C23SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C23SAR_SAR_Msk = 0xffffffff

	// MDMA_C23DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C23DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C23DAR_DAR_Msk = 0xffffffff

	// MDMA_C23BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C23BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C23BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C23BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C23BRUR_DUV_Msk = 0xffff0000

	// MDMA_C23LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C23LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C23LAR_LAR_Msk = 0xffffffff

	// MDMA_C23TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C23TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C23TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C23TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C23TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C23TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C23TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C23TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C23TBR_DBUS = 0x20000

	// MDMA_C23MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C23MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C23MAR_MAR_Msk = 0xffffffff

	// MDMA_C23MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C23MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C23MDR_MDR_Msk = 0xffffffff

	// MDMA_C24ISR: MDMA channel 24 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C24ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C24ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C24ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C24ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C24ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C24ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C24ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C24ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C24ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C24ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C24ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C24ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C24ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C24ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C24ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C24ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C24ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C24ISR_CRQA = 0x10000

	// MDMA_C24IFCR: MDMA channel 24 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C24IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C24IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C24IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C24IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C24IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C24IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C24IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C24IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C24IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C24IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C24IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C24IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C24IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C24IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C24IFCR_CLTCIF = 0x10

	// MDMA_C24ESR: MDMA channel 24 error status register
	// Position of TEA field.
	MDMA1_MDMA_C24ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C24ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C24ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C24ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C24ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C24ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C24ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C24ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C24ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C24ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C24ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C24ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C24ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C24ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C24ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C24ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C24ESR_BSE = 0x800

	// MDMA_C24CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C24CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C24CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C24CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C24CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C24CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C24CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C24CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C24CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C24CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C24CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C24CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C24CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C24CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C24CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C24CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C24CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C24CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C24CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C24CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C24CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C24CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C24CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C24CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C24CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C24CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C24CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C24CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C24CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C24CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C24CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C24CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C24CR_SWRQ = 0x10000

	// MDMA_C24TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C24TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C24TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C24TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C24TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C24TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C24TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C24TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C24TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C24TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C24TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C24TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C24TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C24TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C24TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C24TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C24TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C24TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C24TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C24TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C24TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C24TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C24TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C24TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C24TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C24TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C24TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C24TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C24TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C24TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C24TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C24TCR_BWM = 0x80000000

	// MDMA_C24BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C24BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C24BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C24BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C24BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C24BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C24BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C24BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C24BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C24BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C24BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C24SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C24SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C24SAR_SAR_Msk = 0xffffffff

	// MDMA_C24DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C24DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C24DAR_DAR_Msk = 0xffffffff

	// MDMA_C24BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C24BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C24BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C24BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C24BRUR_DUV_Msk = 0xffff0000

	// MDMA_C24LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C24LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C24LAR_LAR_Msk = 0xffffffff

	// MDMA_C24TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C24TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C24TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C24TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C24TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C24TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C24TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C24TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C24TBR_DBUS = 0x20000

	// MDMA_C24MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C24MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C24MAR_MAR_Msk = 0xffffffff

	// MDMA_C24MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C24MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C24MDR_MDR_Msk = 0xffffffff

	// MDMA_C25ISR: MDMA channel 25 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C25ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C25ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C25ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C25ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C25ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C25ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C25ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C25ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C25ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C25ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C25ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C25ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C25ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C25ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C25ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C25ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C25ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C25ISR_CRQA = 0x10000

	// MDMA_C25IFCR: MDMA channel 25 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C25IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C25IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C25IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C25IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C25IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C25IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C25IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C25IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C25IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C25IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C25IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C25IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C25IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C25IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C25IFCR_CLTCIF = 0x10

	// MDMA_C25ESR: MDMA channel 25 error status register
	// Position of TEA field.
	MDMA1_MDMA_C25ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C25ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C25ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C25ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C25ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C25ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C25ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C25ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C25ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C25ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C25ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C25ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C25ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C25ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C25ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C25ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C25ESR_BSE = 0x800

	// MDMA_C25CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C25CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C25CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C25CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C25CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C25CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C25CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C25CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C25CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C25CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C25CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C25CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C25CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C25CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C25CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C25CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C25CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C25CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C25CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C25CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C25CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C25CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C25CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C25CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C25CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C25CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C25CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C25CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C25CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C25CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C25CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C25CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C25CR_SWRQ = 0x10000

	// MDMA_C25TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C25TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C25TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C25TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C25TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C25TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C25TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C25TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C25TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C25TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C25TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C25TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C25TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C25TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C25TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C25TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C25TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C25TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C25TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C25TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C25TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C25TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C25TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C25TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C25TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C25TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C25TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C25TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C25TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C25TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C25TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C25TCR_BWM = 0x80000000

	// MDMA_C25BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C25BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C25BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C25BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C25BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C25BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C25BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C25BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C25BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C25BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C25BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C25SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C25SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C25SAR_SAR_Msk = 0xffffffff

	// MDMA_C25DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C25DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C25DAR_DAR_Msk = 0xffffffff

	// MDMA_C25BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C25BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C25BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C25BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C25BRUR_DUV_Msk = 0xffff0000

	// MDMA_C25LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C25LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C25LAR_LAR_Msk = 0xffffffff

	// MDMA_C25TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C25TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C25TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C25TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C25TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C25TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C25TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C25TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C25TBR_DBUS = 0x20000

	// MDMA_C25MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C25MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C25MAR_MAR_Msk = 0xffffffff

	// MDMA_C25MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C25MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C25MDR_MDR_Msk = 0xffffffff

	// MDMA_C26ISR: MDMA channel 26 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C26ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C26ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C26ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C26ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C26ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C26ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C26ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C26ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C26ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C26ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C26ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C26ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C26ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C26ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C26ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C26ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C26ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C26ISR_CRQA = 0x10000

	// MDMA_C26IFCR: MDMA channel 26 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C26IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C26IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C26IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C26IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C26IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C26IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C26IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C26IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C26IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C26IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C26IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C26IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C26IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C26IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C26IFCR_CLTCIF = 0x10

	// MDMA_C26ESR: MDMA channel 26 error status register
	// Position of TEA field.
	MDMA1_MDMA_C26ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C26ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C26ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C26ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C26ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C26ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C26ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C26ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C26ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C26ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C26ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C26ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C26ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C26ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C26ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C26ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C26ESR_BSE = 0x800

	// MDMA_C26CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C26CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C26CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C26CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C26CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C26CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C26CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C26CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C26CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C26CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C26CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C26CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C26CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C26CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C26CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C26CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C26CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C26CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C26CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C26CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C26CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C26CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C26CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C26CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C26CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C26CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C26CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C26CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C26CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C26CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C26CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C26CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C26CR_SWRQ = 0x10000

	// MDMA_C26TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C26TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C26TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C26TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C26TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C26TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C26TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C26TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C26TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C26TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C26TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C26TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C26TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C26TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C26TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C26TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C26TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C26TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C26TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C26TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C26TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C26TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C26TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C26TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C26TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C26TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C26TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C26TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C26TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C26TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C26TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C26TCR_BWM = 0x80000000

	// MDMA_C26BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C26BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C26BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C26BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C26BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C26BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C26BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C26BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C26BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C26BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C26BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C26SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C26SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C26SAR_SAR_Msk = 0xffffffff

	// MDMA_C26DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C26DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C26DAR_DAR_Msk = 0xffffffff

	// MDMA_C26BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C26BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C26BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C26BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C26BRUR_DUV_Msk = 0xffff0000

	// MDMA_C26LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C26LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C26LAR_LAR_Msk = 0xffffffff

	// MDMA_C26TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C26TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C26TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C26TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C26TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C26TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C26TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C26TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C26TBR_DBUS = 0x20000

	// MDMA_C26MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C26MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C26MAR_MAR_Msk = 0xffffffff

	// MDMA_C26MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C26MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C26MDR_MDR_Msk = 0xffffffff

	// MDMA_C27ISR: MDMA channel 27 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C27ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C27ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C27ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C27ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C27ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C27ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C27ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C27ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C27ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C27ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C27ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C27ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C27ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C27ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C27ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C27ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C27ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C27ISR_CRQA = 0x10000

	// MDMA_C27IFCR: MDMA channel 27 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C27IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C27IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C27IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C27IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C27IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C27IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C27IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C27IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C27IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C27IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C27IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C27IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C27IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C27IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C27IFCR_CLTCIF = 0x10

	// MDMA_C27ESR: MDMA channel 27 error status register
	// Position of TEA field.
	MDMA1_MDMA_C27ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C27ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C27ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C27ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C27ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C27ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C27ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C27ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C27ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C27ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C27ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C27ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C27ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C27ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C27ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C27ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C27ESR_BSE = 0x800

	// MDMA_C27CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C27CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C27CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C27CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C27CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C27CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C27CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C27CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C27CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C27CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C27CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C27CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C27CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C27CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C27CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C27CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C27CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C27CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C27CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C27CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C27CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C27CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C27CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C27CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C27CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C27CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C27CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C27CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C27CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C27CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C27CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C27CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C27CR_SWRQ = 0x10000

	// MDMA_C27TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C27TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C27TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C27TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C27TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C27TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C27TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C27TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C27TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C27TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C27TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C27TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C27TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C27TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C27TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C27TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C27TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C27TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C27TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C27TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C27TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C27TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C27TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C27TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C27TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C27TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C27TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C27TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C27TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C27TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C27TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C27TCR_BWM = 0x80000000

	// MDMA_C27BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C27BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C27BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C27BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C27BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C27BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C27BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C27BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C27BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C27BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C27BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C27SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C27SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C27SAR_SAR_Msk = 0xffffffff

	// MDMA_C27DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C27DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C27DAR_DAR_Msk = 0xffffffff

	// MDMA_C27BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C27BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C27BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C27BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C27BRUR_DUV_Msk = 0xffff0000

	// MDMA_C27LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C27LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C27LAR_LAR_Msk = 0xffffffff

	// MDMA_C27TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C27TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C27TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C27TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C27TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C27TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C27TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C27TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C27TBR_DBUS = 0x20000

	// MDMA_C27MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C27MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C27MAR_MAR_Msk = 0xffffffff

	// MDMA_C27MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C27MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C27MDR_MDR_Msk = 0xffffffff

	// MDMA_C28ISR: MDMA channel 28 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C28ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C28ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C28ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C28ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C28ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C28ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C28ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C28ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C28ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C28ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C28ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C28ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C28ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C28ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C28ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C28ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C28ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C28ISR_CRQA = 0x10000

	// MDMA_C28IFCR: MDMA channel 28 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C28IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C28IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C28IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C28IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C28IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C28IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C28IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C28IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C28IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C28IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C28IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C28IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C28IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C28IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C28IFCR_CLTCIF = 0x10

	// MDMA_C28ESR: MDMA channel 28 error status register
	// Position of TEA field.
	MDMA1_MDMA_C28ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C28ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C28ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C28ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C28ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C28ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C28ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C28ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C28ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C28ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C28ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C28ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C28ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C28ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C28ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C28ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C28ESR_BSE = 0x800

	// MDMA_C28CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C28CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C28CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C28CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C28CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C28CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C28CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C28CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C28CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C28CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C28CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C28CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C28CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C28CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C28CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C28CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C28CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C28CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C28CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C28CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C28CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C28CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C28CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C28CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C28CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C28CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C28CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C28CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C28CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C28CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C28CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C28CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C28CR_SWRQ = 0x10000

	// MDMA_C28TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C28TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C28TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C28TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C28TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C28TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C28TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C28TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C28TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C28TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C28TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C28TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C28TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C28TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C28TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C28TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C28TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C28TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C28TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C28TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C28TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C28TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C28TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C28TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C28TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C28TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C28TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C28TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C28TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C28TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C28TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C28TCR_BWM = 0x80000000

	// MDMA_C28BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C28BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C28BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C28BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C28BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C28BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C28BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C28BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C28BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C28BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C28BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C28SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C28SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C28SAR_SAR_Msk = 0xffffffff

	// MDMA_C28DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C28DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C28DAR_DAR_Msk = 0xffffffff

	// MDMA_C28BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C28BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C28BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C28BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C28BRUR_DUV_Msk = 0xffff0000

	// MDMA_C28LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C28LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C28LAR_LAR_Msk = 0xffffffff

	// MDMA_C28TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C28TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C28TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C28TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C28TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C28TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C28TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C28TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C28TBR_DBUS = 0x20000

	// MDMA_C28MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C28MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C28MAR_MAR_Msk = 0xffffffff

	// MDMA_C28MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C28MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C28MDR_MDR_Msk = 0xffffffff

	// MDMA_C29ISR: MDMA channel 29 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C29ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C29ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C29ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C29ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C29ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C29ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C29ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C29ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C29ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C29ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C29ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C29ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C29ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C29ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C29ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C29ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C29ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C29ISR_CRQA = 0x10000

	// MDMA_C29IFCR: MDMA channel 29 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C29IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C29IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C29IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C29IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C29IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C29IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C29IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C29IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C29IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C29IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C29IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C29IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C29IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C29IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C29IFCR_CLTCIF = 0x10

	// MDMA_C29ESR: MDMA channel 29 error status register
	// Position of TEA field.
	MDMA1_MDMA_C29ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C29ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C29ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C29ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C29ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C29ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C29ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C29ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C29ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C29ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C29ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C29ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C29ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C29ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C29ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C29ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C29ESR_BSE = 0x800

	// MDMA_C29CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C29CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C29CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C29CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C29CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C29CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C29CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C29CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C29CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C29CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C29CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C29CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C29CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C29CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C29CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C29CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C29CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C29CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C29CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C29CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C29CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C29CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C29CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C29CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C29CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C29CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C29CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C29CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C29CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C29CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C29CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C29CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C29CR_SWRQ = 0x10000

	// MDMA_C29TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C29TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C29TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C29TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C29TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C29TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C29TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C29TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C29TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C29TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C29TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C29TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C29TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C29TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C29TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C29TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C29TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C29TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C29TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C29TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C29TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C29TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C29TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C29TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C29TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C29TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C29TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C29TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C29TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C29TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C29TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C29TCR_BWM = 0x80000000

	// MDMA_C29BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C29BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C29BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C29BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C29BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C29BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C29BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C29BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C29BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C29BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C29BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C29SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C29SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C29SAR_SAR_Msk = 0xffffffff

	// MDMA_C29DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C29DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C29DAR_DAR_Msk = 0xffffffff

	// MDMA_C29BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C29BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C29BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C29BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C29BRUR_DUV_Msk = 0xffff0000

	// MDMA_C29LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C29LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C29LAR_LAR_Msk = 0xffffffff

	// MDMA_C29TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C29TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C29TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C29TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C29TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C29TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C29TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C29TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C29TBR_DBUS = 0x20000

	// MDMA_C29MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C29MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C29MAR_MAR_Msk = 0xffffffff

	// MDMA_C29MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C29MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C29MDR_MDR_Msk = 0xffffffff

	// MDMA_C30ISR: MDMA channel 30 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C30ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C30ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C30ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C30ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C30ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C30ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C30ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C30ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C30ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C30ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C30ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C30ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C30ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C30ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C30ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C30ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C30ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C30ISR_CRQA = 0x10000

	// MDMA_C30IFCR: MDMA channel 30 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C30IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C30IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C30IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C30IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C30IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C30IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C30IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C30IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C30IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C30IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C30IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C30IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C30IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C30IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C30IFCR_CLTCIF = 0x10

	// MDMA_C30ESR: MDMA channel 30 error status register
	// Position of TEA field.
	MDMA1_MDMA_C30ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C30ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C30ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C30ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C30ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C30ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C30ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C30ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C30ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C30ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C30ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C30ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C30ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C30ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C30ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C30ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C30ESR_BSE = 0x800

	// MDMA_C30CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C30CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C30CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C30CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C30CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C30CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C30CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C30CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C30CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C30CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C30CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C30CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C30CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C30CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C30CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C30CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C30CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C30CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C30CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C30CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C30CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C30CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C30CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C30CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C30CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C30CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C30CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C30CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C30CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C30CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C30CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C30CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C30CR_SWRQ = 0x10000

	// MDMA_C30TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C30TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C30TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C30TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C30TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C30TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C30TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C30TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C30TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C30TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C30TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C30TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C30TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C30TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C30TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C30TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C30TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C30TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C30TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C30TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C30TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C30TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C30TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C30TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C30TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C30TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C30TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C30TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C30TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C30TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C30TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C30TCR_BWM = 0x80000000

	// MDMA_C30BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C30BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C30BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C30BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C30BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C30BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C30BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C30BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C30BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C30BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C30BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C30SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C30SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C30SAR_SAR_Msk = 0xffffffff

	// MDMA_C30DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C30DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C30DAR_DAR_Msk = 0xffffffff

	// MDMA_C30BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C30BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C30BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C30BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C30BRUR_DUV_Msk = 0xffff0000

	// MDMA_C30LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C30LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C30LAR_LAR_Msk = 0xffffffff

	// MDMA_C30TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C30TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C30TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C30TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C30TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C30TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C30TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C30TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C30TBR_DBUS = 0x20000

	// MDMA_C30MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C30MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C30MAR_MAR_Msk = 0xffffffff

	// MDMA_C30MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C30MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C30MDR_MDR_Msk = 0xffffffff

	// MDMA_C31ISR: MDMA channel 31 interrupt/status register
	// Position of TEIF field.
	MDMA1_MDMA_C31ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA1_MDMA_C31ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA1_MDMA_C31ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA1_MDMA_C31ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA1_MDMA_C31ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA1_MDMA_C31ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA1_MDMA_C31ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA1_MDMA_C31ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA1_MDMA_C31ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA1_MDMA_C31ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA1_MDMA_C31ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA1_MDMA_C31ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA1_MDMA_C31ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA1_MDMA_C31ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA1_MDMA_C31ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA1_MDMA_C31ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA1_MDMA_C31ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA1_MDMA_C31ISR_CRQA = 0x10000

	// MDMA_C31IFCR: MDMA channel 31 interrupt flag clear register
	// Position of CTEIF field.
	MDMA1_MDMA_C31IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA1_MDMA_C31IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA1_MDMA_C31IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA1_MDMA_C31IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA1_MDMA_C31IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA1_MDMA_C31IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA1_MDMA_C31IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA1_MDMA_C31IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA1_MDMA_C31IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA1_MDMA_C31IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA1_MDMA_C31IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA1_MDMA_C31IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA1_MDMA_C31IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA1_MDMA_C31IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA1_MDMA_C31IFCR_CLTCIF = 0x10

	// MDMA_C31ESR: MDMA channel 31 error status register
	// Position of TEA field.
	MDMA1_MDMA_C31ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA1_MDMA_C31ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA1_MDMA_C31ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA1_MDMA_C31ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA1_MDMA_C31ESR_TED = 0x80
	// Position of TELD field.
	MDMA1_MDMA_C31ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA1_MDMA_C31ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA1_MDMA_C31ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA1_MDMA_C31ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA1_MDMA_C31ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA1_MDMA_C31ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA1_MDMA_C31ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA1_MDMA_C31ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA1_MDMA_C31ESR_ASE = 0x400
	// Position of BSE field.
	MDMA1_MDMA_C31ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA1_MDMA_C31ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA1_MDMA_C31ESR_BSE = 0x800

	// MDMA_C31CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA1_MDMA_C31CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA1_MDMA_C31CR_EN_Msk = 0x1
	// Bit EN.
	MDMA1_MDMA_C31CR_EN = 0x1
	// Position of TEIE field.
	MDMA1_MDMA_C31CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA1_MDMA_C31CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA1_MDMA_C31CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA1_MDMA_C31CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA1_MDMA_C31CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA1_MDMA_C31CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA1_MDMA_C31CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA1_MDMA_C31CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA1_MDMA_C31CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA1_MDMA_C31CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA1_MDMA_C31CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA1_MDMA_C31CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA1_MDMA_C31CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA1_MDMA_C31CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA1_MDMA_C31CR_TCIE = 0x20
	// Position of PL field.
	MDMA1_MDMA_C31CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA1_MDMA_C31CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA1_MDMA_C31CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA1_MDMA_C31CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA1_MDMA_C31CR_BEX = 0x1000
	// Position of HEX field.
	MDMA1_MDMA_C31CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA1_MDMA_C31CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA1_MDMA_C31CR_HEX = 0x2000
	// Position of WEX field.
	MDMA1_MDMA_C31CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA1_MDMA_C31CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA1_MDMA_C31CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA1_MDMA_C31CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA1_MDMA_C31CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA1_MDMA_C31CR_SWRQ = 0x10000

	// MDMA_C31TCR: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
	// Position of SINC field.
	MDMA1_MDMA_C31TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA1_MDMA_C31TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA1_MDMA_C31TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA1_MDMA_C31TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA1_MDMA_C31TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA1_MDMA_C31TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA1_MDMA_C31TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA1_MDMA_C31TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA1_MDMA_C31TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA1_MDMA_C31TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA1_MDMA_C31TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA1_MDMA_C31TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA1_MDMA_C31TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA1_MDMA_C31TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA1_MDMA_C31TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA1_MDMA_C31TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA1_MDMA_C31TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA1_MDMA_C31TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA1_MDMA_C31TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA1_MDMA_C31TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA1_MDMA_C31TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA1_MDMA_C31TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA1_MDMA_C31TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA1_MDMA_C31TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA1_MDMA_C31TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA1_MDMA_C31TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA1_MDMA_C31TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA1_MDMA_C31TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA1_MDMA_C31TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA1_MDMA_C31TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA1_MDMA_C31TCR_BWM = 0x80000000

	// MDMA_C31BNDTR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
	// Position of BNDT field.
	MDMA1_MDMA_C31BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA1_MDMA_C31BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA1_MDMA_C31BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA1_MDMA_C31BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA1_MDMA_C31BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA1_MDMA_C31BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA1_MDMA_C31BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA1_MDMA_C31BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA1_MDMA_C31BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA1_MDMA_C31BNDTR_BRC_Msk = 0xfff00000

	// MDMA_C31SAR: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
	// Position of SAR field.
	MDMA1_MDMA_C31SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA1_MDMA_C31SAR_SAR_Msk = 0xffffffff

	// MDMA_C31DAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
	// Position of DAR field.
	MDMA1_MDMA_C31DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA1_MDMA_C31DAR_DAR_Msk = 0xffffffff

	// MDMA_C31BRUR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
	// Position of SUV field.
	MDMA1_MDMA_C31BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA1_MDMA_C31BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA1_MDMA_C31BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA1_MDMA_C31BRUR_DUV_Msk = 0xffff0000

	// MDMA_C31LAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
	// Position of LAR field.
	MDMA1_MDMA_C31LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA1_MDMA_C31LAR_LAR_Msk = 0xffffffff

	// MDMA_C31TBR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
	// Position of TSEL field.
	MDMA1_MDMA_C31TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA1_MDMA_C31TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA1_MDMA_C31TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA1_MDMA_C31TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA1_MDMA_C31TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA1_MDMA_C31TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA1_MDMA_C31TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA1_MDMA_C31TBR_DBUS = 0x20000

	// MDMA_C31MAR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
	// Position of MAR field.
	MDMA1_MDMA_C31MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA1_MDMA_C31MAR_MAR_Msk = 0xffffffff

	// MDMA_C31MDR: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
	// Position of MDR field.
	MDMA1_MDMA_C31MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA1_MDMA_C31MDR_MDR_Msk = 0xffffffff
)

// Bitfields for NVIC: Nested Vectored Interrupt Controller
const (
	// ISER0: Interrupt Set-Enable Register
	// Position of SETENA field.
	NVIC_ISER0_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER0_SETENA_Msk = 0xffffffff

	// ISER1: Interrupt Set-Enable Register
	// Position of SETENA field.
	NVIC_ISER1_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER1_SETENA_Msk = 0xffffffff

	// ISER2: Interrupt Set-Enable Register
	// Position of SETENA field.
	NVIC_ISER2_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER2_SETENA_Msk = 0xffffffff

	// ISER3: Interrupt Set-Enable Register
	// Position of SETENA field.
	NVIC_ISER3_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER3_SETENA_Msk = 0xffffffff

	// ICER0: Interrupt Clear-Enable Register
	// Position of CLRENA field.
	NVIC_ICER0_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER0_CLRENA_Msk = 0xffffffff

	// ICER1: Interrupt Clear-Enable Register
	// Position of CLRENA field.
	NVIC_ICER1_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER1_CLRENA_Msk = 0xffffffff

	// ICER2: Interrupt Clear-Enable Register
	// Position of CLRENA field.
	NVIC_ICER2_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER2_CLRENA_Msk = 0xffffffff

	// ICER3: Interrupt Clear-Enable Register
	// Position of CLRENA field.
	NVIC_ICER3_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER3_CLRENA_Msk = 0xffffffff

	// ISPR0: Interrupt Set-Pending Register
	// Position of SETPEND field.
	NVIC_ISPR0_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR0_SETPEND_Msk = 0xffffffff

	// ISPR1: Interrupt Set-Pending Register
	// Position of SETPEND field.
	NVIC_ISPR1_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR1_SETPEND_Msk = 0xffffffff

	// ISPR2: Interrupt Set-Pending Register
	// Position of SETPEND field.
	NVIC_ISPR2_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR2_SETPEND_Msk = 0xffffffff

	// ISPR3: Interrupt Set-Pending Register
	// Position of SETPEND field.
	NVIC_ISPR3_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR3_SETPEND_Msk = 0xffffffff

	// ICPR0: Interrupt Clear-Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR0_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR0_CLRPEND_Msk = 0xffffffff

	// ICPR1: Interrupt Clear-Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR1_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR1_CLRPEND_Msk = 0xffffffff

	// ICPR2: Interrupt Clear-Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR2_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR2_CLRPEND_Msk = 0xffffffff

	// ICPR3: Interrupt Clear-Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR3_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR3_CLRPEND_Msk = 0xffffffff

	// IABR0: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR0_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR0_ACTIVE_Msk = 0xffffffff

	// IABR1: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR1_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR1_ACTIVE_Msk = 0xffffffff

	// IABR2: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR2_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR2_ACTIVE_Msk = 0xffffffff

	// IABR3: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR3_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR3_ACTIVE_Msk = 0xffffffff

	// IPR0: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR0_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR0_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR0_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR0_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR0_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR0_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR0_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR0_IPR_N3_Msk = 0xff000000

	// IPR1: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR1_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR1_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR1_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR1_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR1_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR1_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR1_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR1_IPR_N3_Msk = 0xff000000

	// IPR2: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR2_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR2_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR2_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR2_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR2_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR2_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR2_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR2_IPR_N3_Msk = 0xff000000

	// IPR3: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR3_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR3_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR3_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR3_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR3_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR3_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR3_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR3_IPR_N3_Msk = 0xff000000

	// IPR4: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR4_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR4_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR4_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR4_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR4_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR4_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR4_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR4_IPR_N3_Msk = 0xff000000

	// IPR5: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR5_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR5_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR5_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR5_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR5_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR5_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR5_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR5_IPR_N3_Msk = 0xff000000

	// IPR6: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR6_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR6_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR6_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR6_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR6_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR6_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR6_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR6_IPR_N3_Msk = 0xff000000

	// IPR7: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR7_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR7_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR7_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR7_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR7_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR7_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR7_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR7_IPR_N3_Msk = 0xff000000

	// IPR8: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR8_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR8_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR8_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR8_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR8_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR8_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR8_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR8_IPR_N3_Msk = 0xff000000

	// IPR9: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR9_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR9_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR9_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR9_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR9_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR9_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR9_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR9_IPR_N3_Msk = 0xff000000

	// IPR10: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR10_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR10_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR10_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR10_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR10_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR10_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR10_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR10_IPR_N3_Msk = 0xff000000

	// IPR11: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR11_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR11_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR11_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR11_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR11_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR11_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR11_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR11_IPR_N3_Msk = 0xff000000

	// IPR12: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR12_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR12_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR12_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR12_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR12_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR12_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR12_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR12_IPR_N3_Msk = 0xff000000

	// IPR13: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR13_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR13_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR13_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR13_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR13_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR13_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR13_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR13_IPR_N3_Msk = 0xff000000

	// IPR14: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR14_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR14_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR14_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR14_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR14_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR14_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR14_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR14_IPR_N3_Msk = 0xff000000

	// IPR15: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR15_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR15_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR15_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR15_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR15_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR15_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR15_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR15_IPR_N3_Msk = 0xff000000

	// IPR16: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR16_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR16_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR16_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR16_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR16_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR16_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR16_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR16_IPR_N3_Msk = 0xff000000

	// IPR17: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR17_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR17_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR17_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR17_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR17_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR17_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR17_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR17_IPR_N3_Msk = 0xff000000

	// IPR18: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR18_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR18_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR18_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR18_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR18_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR18_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR18_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR18_IPR_N3_Msk = 0xff000000

	// IPR19: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR19_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR19_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR19_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR19_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR19_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR19_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR19_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR19_IPR_N3_Msk = 0xff000000

	// IPR20: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR20_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR20_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR20_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR20_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR20_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR20_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR20_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR20_IPR_N3_Msk = 0xff000000

	// IPR21: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR21_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR21_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR21_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR21_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR21_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR21_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR21_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR21_IPR_N3_Msk = 0xff000000

	// IPR22: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR22_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR22_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR22_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR22_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR22_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR22_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR22_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR22_IPR_N3_Msk = 0xff000000

	// IPR23: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR23_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR23_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR23_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR23_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR23_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR23_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR23_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR23_IPR_N3_Msk = 0xff000000

	// IPR24: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR24_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR24_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR24_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR24_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR24_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR24_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR24_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR24_IPR_N3_Msk = 0xff000000

	// IPR25: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR25_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR25_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR25_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR25_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR25_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR25_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR25_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR25_IPR_N3_Msk = 0xff000000

	// IPR26: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR26_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR26_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR26_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR26_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR26_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR26_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR26_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR26_IPR_N3_Msk = 0xff000000

	// IPR27: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR27_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR27_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR27_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR27_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR27_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR27_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR27_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR27_IPR_N3_Msk = 0xff000000

	// IPR28: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR28_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR28_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR28_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR28_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR28_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR28_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR28_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR28_IPR_N3_Msk = 0xff000000

	// IPR29: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR29_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR29_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR29_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR29_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR29_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR29_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR29_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR29_IPR_N3_Msk = 0xff000000

	// IPR30: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR30_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR30_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR30_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR30_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR30_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR30_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR30_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR30_IPR_N3_Msk = 0xff000000

	// IPR31: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR31_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR31_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR31_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR31_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR31_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR31_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR31_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR31_IPR_N3_Msk = 0xff000000

	// IPR32: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR32_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR32_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR32_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR32_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR32_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR32_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR32_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR32_IPR_N3_Msk = 0xff000000

	// IPR33: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR33_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR33_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR33_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR33_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR33_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR33_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR33_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR33_IPR_N3_Msk = 0xff000000

	// IPR34: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR34_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR34_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR34_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR34_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR34_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR34_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR34_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR34_IPR_N3_Msk = 0xff000000

	// IPR35: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR35_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR35_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR35_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR35_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR35_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR35_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR35_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR35_IPR_N3_Msk = 0xff000000

	// IPR36: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR36_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR36_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR36_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR36_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR36_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR36_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR36_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR36_IPR_N3_Msk = 0xff000000

	// IPR37: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR37_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR37_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR37_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR37_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR37_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR37_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR37_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR37_IPR_N3_Msk = 0xff000000

	// IPR38: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR38_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR38_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR38_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR38_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR38_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR38_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR38_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR38_IPR_N3_Msk = 0xff000000
)

// Bitfields for OTG: OTG
const (
	// OTG_GOTGCTL: The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
	// Position of SRQSCS field.
	OTG_OTG_GOTGCTL_SRQSCS_Pos = 0x0
	// Bit mask of SRQSCS field.
	OTG_OTG_GOTGCTL_SRQSCS_Msk = 0x1
	// Bit SRQSCS.
	OTG_OTG_GOTGCTL_SRQSCS = 0x1
	// Position of SRQ field.
	OTG_OTG_GOTGCTL_SRQ_Pos = 0x1
	// Bit mask of SRQ field.
	OTG_OTG_GOTGCTL_SRQ_Msk = 0x2
	// Bit SRQ.
	OTG_OTG_GOTGCTL_SRQ = 0x2
	// Position of VBVALOEN field.
	OTG_OTG_GOTGCTL_VBVALOEN_Pos = 0x2
	// Bit mask of VBVALOEN field.
	OTG_OTG_GOTGCTL_VBVALOEN_Msk = 0x4
	// Bit VBVALOEN.
	OTG_OTG_GOTGCTL_VBVALOEN = 0x4
	// Position of VBVALOVAL field.
	OTG_OTG_GOTGCTL_VBVALOVAL_Pos = 0x3
	// Bit mask of VBVALOVAL field.
	OTG_OTG_GOTGCTL_VBVALOVAL_Msk = 0x8
	// Bit VBVALOVAL.
	OTG_OTG_GOTGCTL_VBVALOVAL = 0x8
	// Position of AVALOEN field.
	OTG_OTG_GOTGCTL_AVALOEN_Pos = 0x4
	// Bit mask of AVALOEN field.
	OTG_OTG_GOTGCTL_AVALOEN_Msk = 0x10
	// Bit AVALOEN.
	OTG_OTG_GOTGCTL_AVALOEN = 0x10
	// Position of AVALOVAL field.
	OTG_OTG_GOTGCTL_AVALOVAL_Pos = 0x5
	// Bit mask of AVALOVAL field.
	OTG_OTG_GOTGCTL_AVALOVAL_Msk = 0x20
	// Bit AVALOVAL.
	OTG_OTG_GOTGCTL_AVALOVAL = 0x20
	// Position of BVALOEN field.
	OTG_OTG_GOTGCTL_BVALOEN_Pos = 0x6
	// Bit mask of BVALOEN field.
	OTG_OTG_GOTGCTL_BVALOEN_Msk = 0x40
	// Bit BVALOEN.
	OTG_OTG_GOTGCTL_BVALOEN = 0x40
	// Position of BVALOVAL field.
	OTG_OTG_GOTGCTL_BVALOVAL_Pos = 0x7
	// Bit mask of BVALOVAL field.
	OTG_OTG_GOTGCTL_BVALOVAL_Msk = 0x80
	// Bit BVALOVAL.
	OTG_OTG_GOTGCTL_BVALOVAL = 0x80
	// Position of HNGSCS field.
	OTG_OTG_GOTGCTL_HNGSCS_Pos = 0x8
	// Bit mask of HNGSCS field.
	OTG_OTG_GOTGCTL_HNGSCS_Msk = 0x100
	// Bit HNGSCS.
	OTG_OTG_GOTGCTL_HNGSCS = 0x100
	// Position of HNPRQ field.
	OTG_OTG_GOTGCTL_HNPRQ_Pos = 0x9
	// Bit mask of HNPRQ field.
	OTG_OTG_GOTGCTL_HNPRQ_Msk = 0x200
	// Bit HNPRQ.
	OTG_OTG_GOTGCTL_HNPRQ = 0x200
	// Position of HSHNPEN field.
	OTG_OTG_GOTGCTL_HSHNPEN_Pos = 0xa
	// Bit mask of HSHNPEN field.
	OTG_OTG_GOTGCTL_HSHNPEN_Msk = 0x400
	// Bit HSHNPEN.
	OTG_OTG_GOTGCTL_HSHNPEN = 0x400
	// Position of DHNPEN field.
	OTG_OTG_GOTGCTL_DHNPEN_Pos = 0xb
	// Bit mask of DHNPEN field.
	OTG_OTG_GOTGCTL_DHNPEN_Msk = 0x800
	// Bit DHNPEN.
	OTG_OTG_GOTGCTL_DHNPEN = 0x800
	// Position of EHEN field.
	OTG_OTG_GOTGCTL_EHEN_Pos = 0xc
	// Bit mask of EHEN field.
	OTG_OTG_GOTGCTL_EHEN_Msk = 0x1000
	// Bit EHEN.
	OTG_OTG_GOTGCTL_EHEN = 0x1000
	// Position of CIDSTS field.
	OTG_OTG_GOTGCTL_CIDSTS_Pos = 0x10
	// Bit mask of CIDSTS field.
	OTG_OTG_GOTGCTL_CIDSTS_Msk = 0x10000
	// Bit CIDSTS.
	OTG_OTG_GOTGCTL_CIDSTS = 0x10000
	// Position of DBCT field.
	OTG_OTG_GOTGCTL_DBCT_Pos = 0x11
	// Bit mask of DBCT field.
	OTG_OTG_GOTGCTL_DBCT_Msk = 0x20000
	// Bit DBCT.
	OTG_OTG_GOTGCTL_DBCT = 0x20000
	// Position of ASVLD field.
	OTG_OTG_GOTGCTL_ASVLD_Pos = 0x12
	// Bit mask of ASVLD field.
	OTG_OTG_GOTGCTL_ASVLD_Msk = 0x40000
	// Bit ASVLD.
	OTG_OTG_GOTGCTL_ASVLD = 0x40000
	// Position of BSVLD field.
	OTG_OTG_GOTGCTL_BSVLD_Pos = 0x13
	// Bit mask of BSVLD field.
	OTG_OTG_GOTGCTL_BSVLD_Msk = 0x80000
	// Bit BSVLD.
	OTG_OTG_GOTGCTL_BSVLD = 0x80000
	// Position of OTGVER field.
	OTG_OTG_GOTGCTL_OTGVER_Pos = 0x14
	// Bit mask of OTGVER field.
	OTG_OTG_GOTGCTL_OTGVER_Msk = 0x100000
	// Bit OTGVER.
	OTG_OTG_GOTGCTL_OTGVER = 0x100000
	// Position of CURMOD field.
	OTG_OTG_GOTGCTL_CURMOD_Pos = 0x15
	// Bit mask of CURMOD field.
	OTG_OTG_GOTGCTL_CURMOD_Msk = 0x200000
	// Bit CURMOD.
	OTG_OTG_GOTGCTL_CURMOD = 0x200000

	// OTG_GOTGINT: The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
	// Position of SEDET field.
	OTG_OTG_GOTGINT_SEDET_Pos = 0x2
	// Bit mask of SEDET field.
	OTG_OTG_GOTGINT_SEDET_Msk = 0x4
	// Bit SEDET.
	OTG_OTG_GOTGINT_SEDET = 0x4
	// Position of SRSSCHG field.
	OTG_OTG_GOTGINT_SRSSCHG_Pos = 0x8
	// Bit mask of SRSSCHG field.
	OTG_OTG_GOTGINT_SRSSCHG_Msk = 0x100
	// Bit SRSSCHG.
	OTG_OTG_GOTGINT_SRSSCHG = 0x100
	// Position of HNSSCHG field.
	OTG_OTG_GOTGINT_HNSSCHG_Pos = 0x9
	// Bit mask of HNSSCHG field.
	OTG_OTG_GOTGINT_HNSSCHG_Msk = 0x200
	// Bit HNSSCHG.
	OTG_OTG_GOTGINT_HNSSCHG = 0x200
	// Position of HNGDET field.
	OTG_OTG_GOTGINT_HNGDET_Pos = 0x11
	// Bit mask of HNGDET field.
	OTG_OTG_GOTGINT_HNGDET_Msk = 0x20000
	// Bit HNGDET.
	OTG_OTG_GOTGINT_HNGDET = 0x20000
	// Position of ADTOCHG field.
	OTG_OTG_GOTGINT_ADTOCHG_Pos = 0x12
	// Bit mask of ADTOCHG field.
	OTG_OTG_GOTGINT_ADTOCHG_Msk = 0x40000
	// Bit ADTOCHG.
	OTG_OTG_GOTGINT_ADTOCHG = 0x40000
	// Position of DBCDNE field.
	OTG_OTG_GOTGINT_DBCDNE_Pos = 0x13
	// Bit mask of DBCDNE field.
	OTG_OTG_GOTGINT_DBCDNE_Msk = 0x80000
	// Bit DBCDNE.
	OTG_OTG_GOTGINT_DBCDNE = 0x80000
	// Position of IDCHNG field.
	OTG_OTG_GOTGINT_IDCHNG_Pos = 0x14
	// Bit mask of IDCHNG field.
	OTG_OTG_GOTGINT_IDCHNG_Msk = 0x100000
	// Bit IDCHNG.
	OTG_OTG_GOTGINT_IDCHNG = 0x100000

	// OTG_GAHBCFG: This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
	// Position of GINTMSK field.
	OTG_OTG_GAHBCFG_GINTMSK_Pos = 0x0
	// Bit mask of GINTMSK field.
	OTG_OTG_GAHBCFG_GINTMSK_Msk = 0x1
	// Bit GINTMSK.
	OTG_OTG_GAHBCFG_GINTMSK = 0x1
	// Position of HBSTLEN field.
	OTG_OTG_GAHBCFG_HBSTLEN_Pos = 0x1
	// Bit mask of HBSTLEN field.
	OTG_OTG_GAHBCFG_HBSTLEN_Msk = 0x1e
	// Position of DMAEN field.
	OTG_OTG_GAHBCFG_DMAEN_Pos = 0x5
	// Bit mask of DMAEN field.
	OTG_OTG_GAHBCFG_DMAEN_Msk = 0x20
	// Bit DMAEN.
	OTG_OTG_GAHBCFG_DMAEN = 0x20
	// Position of TXFELVL field.
	OTG_OTG_GAHBCFG_TXFELVL_Pos = 0x7
	// Bit mask of TXFELVL field.
	OTG_OTG_GAHBCFG_TXFELVL_Msk = 0x80
	// Bit TXFELVL.
	OTG_OTG_GAHBCFG_TXFELVL = 0x80
	// Position of PTXFELVL field.
	OTG_OTG_GAHBCFG_PTXFELVL_Pos = 0x8
	// Bit mask of PTXFELVL field.
	OTG_OTG_GAHBCFG_PTXFELVL_Msk = 0x100
	// Bit PTXFELVL.
	OTG_OTG_GAHBCFG_PTXFELVL = 0x100

	// OTG_GUSBCFG: This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
	// Position of TOCAL field.
	OTG_OTG_GUSBCFG_TOCAL_Pos = 0x0
	// Bit mask of TOCAL field.
	OTG_OTG_GUSBCFG_TOCAL_Msk = 0x7
	// Position of PHYSEL field.
	OTG_OTG_GUSBCFG_PHYSEL_Pos = 0x6
	// Bit mask of PHYSEL field.
	OTG_OTG_GUSBCFG_PHYSEL_Msk = 0x40
	// Bit PHYSEL.
	OTG_OTG_GUSBCFG_PHYSEL = 0x40
	// Position of SRPCAP field.
	OTG_OTG_GUSBCFG_SRPCAP_Pos = 0x8
	// Bit mask of SRPCAP field.
	OTG_OTG_GUSBCFG_SRPCAP_Msk = 0x100
	// Bit SRPCAP.
	OTG_OTG_GUSBCFG_SRPCAP = 0x100
	// Position of HNPCAP field.
	OTG_OTG_GUSBCFG_HNPCAP_Pos = 0x9
	// Bit mask of HNPCAP field.
	OTG_OTG_GUSBCFG_HNPCAP_Msk = 0x200
	// Bit HNPCAP.
	OTG_OTG_GUSBCFG_HNPCAP = 0x200
	// Position of TRDT field.
	OTG_OTG_GUSBCFG_TRDT_Pos = 0xa
	// Bit mask of TRDT field.
	OTG_OTG_GUSBCFG_TRDT_Msk = 0x3c00
	// Position of PHYLPC field.
	OTG_OTG_GUSBCFG_PHYLPC_Pos = 0xf
	// Bit mask of PHYLPC field.
	OTG_OTG_GUSBCFG_PHYLPC_Msk = 0x8000
	// Bit PHYLPC.
	OTG_OTG_GUSBCFG_PHYLPC = 0x8000
	// Position of TSDPS field.
	OTG_OTG_GUSBCFG_TSDPS_Pos = 0x16
	// Bit mask of TSDPS field.
	OTG_OTG_GUSBCFG_TSDPS_Msk = 0x400000
	// Bit TSDPS.
	OTG_OTG_GUSBCFG_TSDPS = 0x400000
	// Position of FHMOD field.
	OTG_OTG_GUSBCFG_FHMOD_Pos = 0x1d
	// Bit mask of FHMOD field.
	OTG_OTG_GUSBCFG_FHMOD_Msk = 0x20000000
	// Bit FHMOD.
	OTG_OTG_GUSBCFG_FHMOD = 0x20000000
	// Position of FDMOD field.
	OTG_OTG_GUSBCFG_FDMOD_Pos = 0x1e
	// Bit mask of FDMOD field.
	OTG_OTG_GUSBCFG_FDMOD_Msk = 0x40000000
	// Bit FDMOD.
	OTG_OTG_GUSBCFG_FDMOD = 0x40000000

	// OTG_GRSTCTL: The application uses this register to reset various hardware features inside the core.
	// Position of CSRST field.
	OTG_OTG_GRSTCTL_CSRST_Pos = 0x0
	// Bit mask of CSRST field.
	OTG_OTG_GRSTCTL_CSRST_Msk = 0x1
	// Bit CSRST.
	OTG_OTG_GRSTCTL_CSRST = 0x1
	// Position of PSRST field.
	OTG_OTG_GRSTCTL_PSRST_Pos = 0x1
	// Bit mask of PSRST field.
	OTG_OTG_GRSTCTL_PSRST_Msk = 0x2
	// Bit PSRST.
	OTG_OTG_GRSTCTL_PSRST = 0x2
	// Position of RXFFLSH field.
	OTG_OTG_GRSTCTL_RXFFLSH_Pos = 0x4
	// Bit mask of RXFFLSH field.
	OTG_OTG_GRSTCTL_RXFFLSH_Msk = 0x10
	// Bit RXFFLSH.
	OTG_OTG_GRSTCTL_RXFFLSH = 0x10
	// Position of TXFFLSH field.
	OTG_OTG_GRSTCTL_TXFFLSH_Pos = 0x5
	// Bit mask of TXFFLSH field.
	OTG_OTG_GRSTCTL_TXFFLSH_Msk = 0x20
	// Bit TXFFLSH.
	OTG_OTG_GRSTCTL_TXFFLSH = 0x20
	// Position of TXFNUM field.
	OTG_OTG_GRSTCTL_TXFNUM_Pos = 0x6
	// Bit mask of TXFNUM field.
	OTG_OTG_GRSTCTL_TXFNUM_Msk = 0x7c0
	// Position of DMAREQ field.
	OTG_OTG_GRSTCTL_DMAREQ_Pos = 0x1e
	// Bit mask of DMAREQ field.
	OTG_OTG_GRSTCTL_DMAREQ_Msk = 0x40000000
	// Bit DMAREQ.
	OTG_OTG_GRSTCTL_DMAREQ = 0x40000000
	// Position of AHBIDL field.
	OTG_OTG_GRSTCTL_AHBIDL_Pos = 0x1f
	// Bit mask of AHBIDL field.
	OTG_OTG_GRSTCTL_AHBIDL_Msk = 0x80000000
	// Bit AHBIDL.
	OTG_OTG_GRSTCTL_AHBIDL = 0x80000000

	// OTG_GINTSTS: This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
	// Position of CMOD field.
	OTG_OTG_GINTSTS_CMOD_Pos = 0x0
	// Bit mask of CMOD field.
	OTG_OTG_GINTSTS_CMOD_Msk = 0x1
	// Bit CMOD.
	OTG_OTG_GINTSTS_CMOD = 0x1
	// Position of MMIS field.
	OTG_OTG_GINTSTS_MMIS_Pos = 0x1
	// Bit mask of MMIS field.
	OTG_OTG_GINTSTS_MMIS_Msk = 0x2
	// Bit MMIS.
	OTG_OTG_GINTSTS_MMIS = 0x2
	// Position of OTGINT field.
	OTG_OTG_GINTSTS_OTGINT_Pos = 0x2
	// Bit mask of OTGINT field.
	OTG_OTG_GINTSTS_OTGINT_Msk = 0x4
	// Bit OTGINT.
	OTG_OTG_GINTSTS_OTGINT = 0x4
	// Position of SOF field.
	OTG_OTG_GINTSTS_SOF_Pos = 0x3
	// Bit mask of SOF field.
	OTG_OTG_GINTSTS_SOF_Msk = 0x8
	// Bit SOF.
	OTG_OTG_GINTSTS_SOF = 0x8
	// Position of RXFLVL field.
	OTG_OTG_GINTSTS_RXFLVL_Pos = 0x4
	// Bit mask of RXFLVL field.
	OTG_OTG_GINTSTS_RXFLVL_Msk = 0x10
	// Bit RXFLVL.
	OTG_OTG_GINTSTS_RXFLVL = 0x10
	// Position of NPTXFE field.
	OTG_OTG_GINTSTS_NPTXFE_Pos = 0x5
	// Bit mask of NPTXFE field.
	OTG_OTG_GINTSTS_NPTXFE_Msk = 0x20
	// Bit NPTXFE.
	OTG_OTG_GINTSTS_NPTXFE = 0x20
	// Position of GINAKEFF field.
	OTG_OTG_GINTSTS_GINAKEFF_Pos = 0x6
	// Bit mask of GINAKEFF field.
	OTG_OTG_GINTSTS_GINAKEFF_Msk = 0x40
	// Bit GINAKEFF.
	OTG_OTG_GINTSTS_GINAKEFF = 0x40
	// Position of GONAKEFF field.
	OTG_OTG_GINTSTS_GONAKEFF_Pos = 0x7
	// Bit mask of GONAKEFF field.
	OTG_OTG_GINTSTS_GONAKEFF_Msk = 0x80
	// Bit GONAKEFF.
	OTG_OTG_GINTSTS_GONAKEFF = 0x80
	// Position of ESUSP field.
	OTG_OTG_GINTSTS_ESUSP_Pos = 0xa
	// Bit mask of ESUSP field.
	OTG_OTG_GINTSTS_ESUSP_Msk = 0x400
	// Bit ESUSP.
	OTG_OTG_GINTSTS_ESUSP = 0x400
	// Position of USBSUSP field.
	OTG_OTG_GINTSTS_USBSUSP_Pos = 0xb
	// Bit mask of USBSUSP field.
	OTG_OTG_GINTSTS_USBSUSP_Msk = 0x800
	// Bit USBSUSP.
	OTG_OTG_GINTSTS_USBSUSP = 0x800
	// Position of USBRST field.
	OTG_OTG_GINTSTS_USBRST_Pos = 0xc
	// Bit mask of USBRST field.
	OTG_OTG_GINTSTS_USBRST_Msk = 0x1000
	// Bit USBRST.
	OTG_OTG_GINTSTS_USBRST = 0x1000
	// Position of ENUMDNE field.
	OTG_OTG_GINTSTS_ENUMDNE_Pos = 0xd
	// Bit mask of ENUMDNE field.
	OTG_OTG_GINTSTS_ENUMDNE_Msk = 0x2000
	// Bit ENUMDNE.
	OTG_OTG_GINTSTS_ENUMDNE = 0x2000
	// Position of ISOODRP field.
	OTG_OTG_GINTSTS_ISOODRP_Pos = 0xe
	// Bit mask of ISOODRP field.
	OTG_OTG_GINTSTS_ISOODRP_Msk = 0x4000
	// Bit ISOODRP.
	OTG_OTG_GINTSTS_ISOODRP = 0x4000
	// Position of EOPF field.
	OTG_OTG_GINTSTS_EOPF_Pos = 0xf
	// Bit mask of EOPF field.
	OTG_OTG_GINTSTS_EOPF_Msk = 0x8000
	// Bit EOPF.
	OTG_OTG_GINTSTS_EOPF = 0x8000
	// Position of IEPINT field.
	OTG_OTG_GINTSTS_IEPINT_Pos = 0x12
	// Bit mask of IEPINT field.
	OTG_OTG_GINTSTS_IEPINT_Msk = 0x40000
	// Bit IEPINT.
	OTG_OTG_GINTSTS_IEPINT = 0x40000
	// Position of OEPINT field.
	OTG_OTG_GINTSTS_OEPINT_Pos = 0x13
	// Bit mask of OEPINT field.
	OTG_OTG_GINTSTS_OEPINT_Msk = 0x80000
	// Bit OEPINT.
	OTG_OTG_GINTSTS_OEPINT = 0x80000
	// Position of IISOIXFR field.
	OTG_OTG_GINTSTS_IISOIXFR_Pos = 0x14
	// Bit mask of IISOIXFR field.
	OTG_OTG_GINTSTS_IISOIXFR_Msk = 0x100000
	// Bit IISOIXFR.
	OTG_OTG_GINTSTS_IISOIXFR = 0x100000
	// Position of IPXFR field.
	OTG_OTG_GINTSTS_IPXFR_Pos = 0x15
	// Bit mask of IPXFR field.
	OTG_OTG_GINTSTS_IPXFR_Msk = 0x200000
	// Bit IPXFR.
	OTG_OTG_GINTSTS_IPXFR = 0x200000
	// Position of DATAFSUSP field.
	OTG_OTG_GINTSTS_DATAFSUSP_Pos = 0x16
	// Bit mask of DATAFSUSP field.
	OTG_OTG_GINTSTS_DATAFSUSP_Msk = 0x400000
	// Bit DATAFSUSP.
	OTG_OTG_GINTSTS_DATAFSUSP = 0x400000
	// Position of HPRTINT field.
	OTG_OTG_GINTSTS_HPRTINT_Pos = 0x18
	// Bit mask of HPRTINT field.
	OTG_OTG_GINTSTS_HPRTINT_Msk = 0x1000000
	// Bit HPRTINT.
	OTG_OTG_GINTSTS_HPRTINT = 0x1000000
	// Position of HCINT field.
	OTG_OTG_GINTSTS_HCINT_Pos = 0x19
	// Bit mask of HCINT field.
	OTG_OTG_GINTSTS_HCINT_Msk = 0x2000000
	// Bit HCINT.
	OTG_OTG_GINTSTS_HCINT = 0x2000000
	// Position of PTXFE field.
	OTG_OTG_GINTSTS_PTXFE_Pos = 0x1a
	// Bit mask of PTXFE field.
	OTG_OTG_GINTSTS_PTXFE_Msk = 0x4000000
	// Bit PTXFE.
	OTG_OTG_GINTSTS_PTXFE = 0x4000000
	// Position of CIDSCHG field.
	OTG_OTG_GINTSTS_CIDSCHG_Pos = 0x1c
	// Bit mask of CIDSCHG field.
	OTG_OTG_GINTSTS_CIDSCHG_Msk = 0x10000000
	// Bit CIDSCHG.
	OTG_OTG_GINTSTS_CIDSCHG = 0x10000000
	// Position of DISCINT field.
	OTG_OTG_GINTSTS_DISCINT_Pos = 0x1d
	// Bit mask of DISCINT field.
	OTG_OTG_GINTSTS_DISCINT_Msk = 0x20000000
	// Bit DISCINT.
	OTG_OTG_GINTSTS_DISCINT = 0x20000000
	// Position of SRQINT field.
	OTG_OTG_GINTSTS_SRQINT_Pos = 0x1e
	// Bit mask of SRQINT field.
	OTG_OTG_GINTSTS_SRQINT_Msk = 0x40000000
	// Bit SRQINT.
	OTG_OTG_GINTSTS_SRQINT = 0x40000000
	// Position of WKUPINT field.
	OTG_OTG_GINTSTS_WKUPINT_Pos = 0x1f
	// Bit mask of WKUPINT field.
	OTG_OTG_GINTSTS_WKUPINT_Msk = 0x80000000
	// Bit WKUPINT.
	OTG_OTG_GINTSTS_WKUPINT = 0x80000000

	// OTG_GINTMSK: This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
	// Position of MMISM field.
	OTG_OTG_GINTMSK_MMISM_Pos = 0x1
	// Bit mask of MMISM field.
	OTG_OTG_GINTMSK_MMISM_Msk = 0x2
	// Bit MMISM.
	OTG_OTG_GINTMSK_MMISM = 0x2
	// Position of OTGINT field.
	OTG_OTG_GINTMSK_OTGINT_Pos = 0x2
	// Bit mask of OTGINT field.
	OTG_OTG_GINTMSK_OTGINT_Msk = 0x4
	// Bit OTGINT.
	OTG_OTG_GINTMSK_OTGINT = 0x4
	// Position of SOFM field.
	OTG_OTG_GINTMSK_SOFM_Pos = 0x3
	// Bit mask of SOFM field.
	OTG_OTG_GINTMSK_SOFM_Msk = 0x8
	// Bit SOFM.
	OTG_OTG_GINTMSK_SOFM = 0x8
	// Position of RXFLVLM field.
	OTG_OTG_GINTMSK_RXFLVLM_Pos = 0x4
	// Bit mask of RXFLVLM field.
	OTG_OTG_GINTMSK_RXFLVLM_Msk = 0x10
	// Bit RXFLVLM.
	OTG_OTG_GINTMSK_RXFLVLM = 0x10
	// Position of NPTXFEM field.
	OTG_OTG_GINTMSK_NPTXFEM_Pos = 0x5
	// Bit mask of NPTXFEM field.
	OTG_OTG_GINTMSK_NPTXFEM_Msk = 0x20
	// Bit NPTXFEM.
	OTG_OTG_GINTMSK_NPTXFEM = 0x20
	// Position of GINAKEFFM field.
	OTG_OTG_GINTMSK_GINAKEFFM_Pos = 0x6
	// Bit mask of GINAKEFFM field.
	OTG_OTG_GINTMSK_GINAKEFFM_Msk = 0x40
	// Bit GINAKEFFM.
	OTG_OTG_GINTMSK_GINAKEFFM = 0x40
	// Position of GONAKEFFM field.
	OTG_OTG_GINTMSK_GONAKEFFM_Pos = 0x7
	// Bit mask of GONAKEFFM field.
	OTG_OTG_GINTMSK_GONAKEFFM_Msk = 0x80
	// Bit GONAKEFFM.
	OTG_OTG_GINTMSK_GONAKEFFM = 0x80
	// Position of ESUSPM field.
	OTG_OTG_GINTMSK_ESUSPM_Pos = 0xa
	// Bit mask of ESUSPM field.
	OTG_OTG_GINTMSK_ESUSPM_Msk = 0x400
	// Bit ESUSPM.
	OTG_OTG_GINTMSK_ESUSPM = 0x400
	// Position of USBSUSPM field.
	OTG_OTG_GINTMSK_USBSUSPM_Pos = 0xb
	// Bit mask of USBSUSPM field.
	OTG_OTG_GINTMSK_USBSUSPM_Msk = 0x800
	// Bit USBSUSPM.
	OTG_OTG_GINTMSK_USBSUSPM = 0x800
	// Position of USBRST field.
	OTG_OTG_GINTMSK_USBRST_Pos = 0xc
	// Bit mask of USBRST field.
	OTG_OTG_GINTMSK_USBRST_Msk = 0x1000
	// Bit USBRST.
	OTG_OTG_GINTMSK_USBRST = 0x1000
	// Position of ENUMDNEM field.
	OTG_OTG_GINTMSK_ENUMDNEM_Pos = 0xd
	// Bit mask of ENUMDNEM field.
	OTG_OTG_GINTMSK_ENUMDNEM_Msk = 0x2000
	// Bit ENUMDNEM.
	OTG_OTG_GINTMSK_ENUMDNEM = 0x2000
	// Position of ISOODRPM field.
	OTG_OTG_GINTMSK_ISOODRPM_Pos = 0xe
	// Bit mask of ISOODRPM field.
	OTG_OTG_GINTMSK_ISOODRPM_Msk = 0x4000
	// Bit ISOODRPM.
	OTG_OTG_GINTMSK_ISOODRPM = 0x4000
	// Position of EOPFM field.
	OTG_OTG_GINTMSK_EOPFM_Pos = 0xf
	// Bit mask of EOPFM field.
	OTG_OTG_GINTMSK_EOPFM_Msk = 0x8000
	// Bit EOPFM.
	OTG_OTG_GINTMSK_EOPFM = 0x8000
	// Position of IEPINT field.
	OTG_OTG_GINTMSK_IEPINT_Pos = 0x12
	// Bit mask of IEPINT field.
	OTG_OTG_GINTMSK_IEPINT_Msk = 0x40000
	// Bit IEPINT.
	OTG_OTG_GINTMSK_IEPINT = 0x40000
	// Position of OEPINT field.
	OTG_OTG_GINTMSK_OEPINT_Pos = 0x13
	// Bit mask of OEPINT field.
	OTG_OTG_GINTMSK_OEPINT_Msk = 0x80000
	// Bit OEPINT.
	OTG_OTG_GINTMSK_OEPINT = 0x80000
	// Position of IISOIXFRM field.
	OTG_OTG_GINTMSK_IISOIXFRM_Pos = 0x14
	// Bit mask of IISOIXFRM field.
	OTG_OTG_GINTMSK_IISOIXFRM_Msk = 0x100000
	// Bit IISOIXFRM.
	OTG_OTG_GINTMSK_IISOIXFRM = 0x100000
	// Position of IPXFRM field.
	OTG_OTG_GINTMSK_IPXFRM_Pos = 0x15
	// Bit mask of IPXFRM field.
	OTG_OTG_GINTMSK_IPXFRM_Msk = 0x200000
	// Bit IPXFRM.
	OTG_OTG_GINTMSK_IPXFRM = 0x200000
	// Position of FSUSPM field.
	OTG_OTG_GINTMSK_FSUSPM_Pos = 0x16
	// Bit mask of FSUSPM field.
	OTG_OTG_GINTMSK_FSUSPM_Msk = 0x400000
	// Bit FSUSPM.
	OTG_OTG_GINTMSK_FSUSPM = 0x400000
	// Position of RSTDETM field.
	OTG_OTG_GINTMSK_RSTDETM_Pos = 0x17
	// Bit mask of RSTDETM field.
	OTG_OTG_GINTMSK_RSTDETM_Msk = 0x800000
	// Bit RSTDETM.
	OTG_OTG_GINTMSK_RSTDETM = 0x800000
	// Position of PRTIM field.
	OTG_OTG_GINTMSK_PRTIM_Pos = 0x18
	// Bit mask of PRTIM field.
	OTG_OTG_GINTMSK_PRTIM_Msk = 0x1000000
	// Bit PRTIM.
	OTG_OTG_GINTMSK_PRTIM = 0x1000000
	// Position of HCIM field.
	OTG_OTG_GINTMSK_HCIM_Pos = 0x19
	// Bit mask of HCIM field.
	OTG_OTG_GINTMSK_HCIM_Msk = 0x2000000
	// Bit HCIM.
	OTG_OTG_GINTMSK_HCIM = 0x2000000
	// Position of PTXFEM field.
	OTG_OTG_GINTMSK_PTXFEM_Pos = 0x1a
	// Bit mask of PTXFEM field.
	OTG_OTG_GINTMSK_PTXFEM_Msk = 0x4000000
	// Bit PTXFEM.
	OTG_OTG_GINTMSK_PTXFEM = 0x4000000
	// Position of LPMINTM field.
	OTG_OTG_GINTMSK_LPMINTM_Pos = 0x1b
	// Bit mask of LPMINTM field.
	OTG_OTG_GINTMSK_LPMINTM_Msk = 0x8000000
	// Bit LPMINTM.
	OTG_OTG_GINTMSK_LPMINTM = 0x8000000
	// Position of CIDSCHGM field.
	OTG_OTG_GINTMSK_CIDSCHGM_Pos = 0x1c
	// Bit mask of CIDSCHGM field.
	OTG_OTG_GINTMSK_CIDSCHGM_Msk = 0x10000000
	// Bit CIDSCHGM.
	OTG_OTG_GINTMSK_CIDSCHGM = 0x10000000
	// Position of DISCINT field.
	OTG_OTG_GINTMSK_DISCINT_Pos = 0x1d
	// Bit mask of DISCINT field.
	OTG_OTG_GINTMSK_DISCINT_Msk = 0x20000000
	// Bit DISCINT.
	OTG_OTG_GINTMSK_DISCINT = 0x20000000
	// Position of SRQIM field.
	OTG_OTG_GINTMSK_SRQIM_Pos = 0x1e
	// Bit mask of SRQIM field.
	OTG_OTG_GINTMSK_SRQIM_Msk = 0x40000000
	// Bit SRQIM.
	OTG_OTG_GINTMSK_SRQIM = 0x40000000
	// Position of WUIM field.
	OTG_OTG_GINTMSK_WUIM_Pos = 0x1f
	// Bit mask of WUIM field.
	OTG_OTG_GINTMSK_WUIM_Msk = 0x80000000
	// Bit WUIM.
	OTG_OTG_GINTMSK_WUIM = 0x80000000

	// OTG_GRXSTSR: This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
	// Position of EPNUM field.
	OTG_OTG_GRXSTSR_EPNUM_Pos = 0x0
	// Bit mask of EPNUM field.
	OTG_OTG_GRXSTSR_EPNUM_Msk = 0xf
	// Position of BCNT field.
	OTG_OTG_GRXSTSR_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	OTG_OTG_GRXSTSR_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	OTG_OTG_GRXSTSR_DPID_Pos = 0xf
	// Bit mask of DPID field.
	OTG_OTG_GRXSTSR_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	OTG_OTG_GRXSTSR_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	OTG_OTG_GRXSTSR_PKTSTS_Msk = 0x1e0000
	// Position of FRMNUM field.
	OTG_OTG_GRXSTSR_FRMNUM_Pos = 0x15
	// Bit mask of FRMNUM field.
	OTG_OTG_GRXSTSR_FRMNUM_Msk = 0x1e00000
	// Position of STSPHST field.
	OTG_OTG_GRXSTSR_STSPHST_Pos = 0x1b
	// Bit mask of STSPHST field.
	OTG_OTG_GRXSTSR_STSPHST_Msk = 0x8000000
	// Bit STSPHST.
	OTG_OTG_GRXSTSR_STSPHST = 0x8000000

	// OTG_GRXSTSP: This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted.
	// Position of EPNUM field.
	OTG_OTG_GRXSTSP_EPNUM_Pos = 0x0
	// Bit mask of EPNUM field.
	OTG_OTG_GRXSTSP_EPNUM_Msk = 0xf
	// Position of BCNT field.
	OTG_OTG_GRXSTSP_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	OTG_OTG_GRXSTSP_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	OTG_OTG_GRXSTSP_DPID_Pos = 0xf
	// Bit mask of DPID field.
	OTG_OTG_GRXSTSP_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	OTG_OTG_GRXSTSP_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	OTG_OTG_GRXSTSP_PKTSTS_Msk = 0x1e0000
	// Position of FRMNUM field.
	OTG_OTG_GRXSTSP_FRMNUM_Pos = 0x15
	// Bit mask of FRMNUM field.
	OTG_OTG_GRXSTSP_FRMNUM_Msk = 0x1e00000
	// Position of STSPHST field.
	OTG_OTG_GRXSTSP_STSPHST_Pos = 0x1b
	// Bit mask of STSPHST field.
	OTG_OTG_GRXSTSP_STSPHST_Msk = 0x8000000
	// Bit STSPHST.
	OTG_OTG_GRXSTSP_STSPHST = 0x8000000

	// OTG_GRXFSIZ: The application can program the RAM size that must be allocated to the Rx FIFO.
	// Position of RXFD field.
	OTG_OTG_GRXFSIZ_RXFD_Pos = 0x0
	// Bit mask of RXFD field.
	OTG_OTG_GRXFSIZ_RXFD_Msk = 0xffff

	// OTG_HNPTXFSIZ: Host mode
	// Position of NPTXFSA field.
	OTG_OTG_HNPTXFSIZ_NPTXFSA_Pos = 0x0
	// Bit mask of NPTXFSA field.
	OTG_OTG_HNPTXFSIZ_NPTXFSA_Msk = 0xffff
	// Position of NPTXFD field.
	OTG_OTG_HNPTXFSIZ_NPTXFD_Pos = 0x10
	// Bit mask of NPTXFD field.
	OTG_OTG_HNPTXFSIZ_NPTXFD_Msk = 0xffff0000

	// OTG_HNPTXSTS: In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
	// Position of NPTXFSAV field.
	OTG_OTG_HNPTXSTS_NPTXFSAV_Pos = 0x0
	// Bit mask of NPTXFSAV field.
	OTG_OTG_HNPTXSTS_NPTXFSAV_Msk = 0xffff
	// Position of NPTQXSAV field.
	OTG_OTG_HNPTXSTS_NPTQXSAV_Pos = 0x10
	// Bit mask of NPTQXSAV field.
	OTG_OTG_HNPTXSTS_NPTQXSAV_Msk = 0xff0000
	// Position of NPTXQTOP field.
	OTG_OTG_HNPTXSTS_NPTXQTOP_Pos = 0x18
	// Bit mask of NPTXQTOP field.
	OTG_OTG_HNPTXSTS_NPTXQTOP_Msk = 0x7f000000

	// OTG_GCCFG: OTG general core configuration register
	// Position of PDET field.
	OTG_OTG_GCCFG_PDET_Pos = 0x1
	// Bit mask of PDET field.
	OTG_OTG_GCCFG_PDET_Msk = 0x2
	// Bit PDET.
	OTG_OTG_GCCFG_PDET = 0x2
	// Position of SDET field.
	OTG_OTG_GCCFG_SDET_Pos = 0x2
	// Bit mask of SDET field.
	OTG_OTG_GCCFG_SDET_Msk = 0x4
	// Bit SDET.
	OTG_OTG_GCCFG_SDET = 0x4
	// Position of PS2DET field.
	OTG_OTG_GCCFG_PS2DET_Pos = 0x3
	// Bit mask of PS2DET field.
	OTG_OTG_GCCFG_PS2DET_Msk = 0x8
	// Bit PS2DET.
	OTG_OTG_GCCFG_PS2DET = 0x8
	// Position of PWRDWN field.
	OTG_OTG_GCCFG_PWRDWN_Pos = 0x10
	// Bit mask of PWRDWN field.
	OTG_OTG_GCCFG_PWRDWN_Msk = 0x10000
	// Bit PWRDWN.
	OTG_OTG_GCCFG_PWRDWN = 0x10000
	// Position of BCDEN field.
	OTG_OTG_GCCFG_BCDEN_Pos = 0x11
	// Bit mask of BCDEN field.
	OTG_OTG_GCCFG_BCDEN_Msk = 0x20000
	// Bit BCDEN.
	OTG_OTG_GCCFG_BCDEN = 0x20000
	// Position of PDEN field.
	OTG_OTG_GCCFG_PDEN_Pos = 0x13
	// Bit mask of PDEN field.
	OTG_OTG_GCCFG_PDEN_Msk = 0x80000
	// Bit PDEN.
	OTG_OTG_GCCFG_PDEN = 0x80000
	// Position of SDEN field.
	OTG_OTG_GCCFG_SDEN_Pos = 0x14
	// Bit mask of SDEN field.
	OTG_OTG_GCCFG_SDEN_Msk = 0x100000
	// Bit SDEN.
	OTG_OTG_GCCFG_SDEN = 0x100000
	// Position of VBDEN field.
	OTG_OTG_GCCFG_VBDEN_Pos = 0x15
	// Bit mask of VBDEN field.
	OTG_OTG_GCCFG_VBDEN_Msk = 0x200000
	// Bit VBDEN.
	OTG_OTG_GCCFG_VBDEN = 0x200000
	// Position of IDEN field.
	OTG_OTG_GCCFG_IDEN_Pos = 0x16
	// Bit mask of IDEN field.
	OTG_OTG_GCCFG_IDEN_Msk = 0x400000
	// Bit IDEN.
	OTG_OTG_GCCFG_IDEN = 0x400000

	// OTG_CID: This is a register containing the Product ID as reset value.
	// Position of PRODUCT_ID field.
	OTG_OTG_CID_PRODUCT_ID_Pos = 0x0
	// Bit mask of PRODUCT_ID field.
	OTG_OTG_CID_PRODUCT_ID_Msk = 0xffffffff

	// OTG_GLPMCFG: OTG core LPM configuration register
	// Position of LPMEN field.
	OTG_OTG_GLPMCFG_LPMEN_Pos = 0x0
	// Bit mask of LPMEN field.
	OTG_OTG_GLPMCFG_LPMEN_Msk = 0x1
	// Bit LPMEN.
	OTG_OTG_GLPMCFG_LPMEN = 0x1
	// Position of LPMACK field.
	OTG_OTG_GLPMCFG_LPMACK_Pos = 0x1
	// Bit mask of LPMACK field.
	OTG_OTG_GLPMCFG_LPMACK_Msk = 0x2
	// Bit LPMACK.
	OTG_OTG_GLPMCFG_LPMACK = 0x2
	// Position of BESL field.
	OTG_OTG_GLPMCFG_BESL_Pos = 0x2
	// Bit mask of BESL field.
	OTG_OTG_GLPMCFG_BESL_Msk = 0x3c
	// Position of REMWAKE field.
	OTG_OTG_GLPMCFG_REMWAKE_Pos = 0x6
	// Bit mask of REMWAKE field.
	OTG_OTG_GLPMCFG_REMWAKE_Msk = 0x40
	// Bit REMWAKE.
	OTG_OTG_GLPMCFG_REMWAKE = 0x40
	// Position of L1SSEN field.
	OTG_OTG_GLPMCFG_L1SSEN_Pos = 0x7
	// Bit mask of L1SSEN field.
	OTG_OTG_GLPMCFG_L1SSEN_Msk = 0x80
	// Bit L1SSEN.
	OTG_OTG_GLPMCFG_L1SSEN = 0x80
	// Position of BESLTHRS field.
	OTG_OTG_GLPMCFG_BESLTHRS_Pos = 0x8
	// Bit mask of BESLTHRS field.
	OTG_OTG_GLPMCFG_BESLTHRS_Msk = 0xf00
	// Position of L1DSEN field.
	OTG_OTG_GLPMCFG_L1DSEN_Pos = 0xc
	// Bit mask of L1DSEN field.
	OTG_OTG_GLPMCFG_L1DSEN_Msk = 0x1000
	// Bit L1DSEN.
	OTG_OTG_GLPMCFG_L1DSEN = 0x1000
	// Position of LPMRSP field.
	OTG_OTG_GLPMCFG_LPMRSP_Pos = 0xd
	// Bit mask of LPMRSP field.
	OTG_OTG_GLPMCFG_LPMRSP_Msk = 0x6000
	// Position of SLPSTS field.
	OTG_OTG_GLPMCFG_SLPSTS_Pos = 0xf
	// Bit mask of SLPSTS field.
	OTG_OTG_GLPMCFG_SLPSTS_Msk = 0x8000
	// Bit SLPSTS.
	OTG_OTG_GLPMCFG_SLPSTS = 0x8000
	// Position of L1RSMOK field.
	OTG_OTG_GLPMCFG_L1RSMOK_Pos = 0x10
	// Bit mask of L1RSMOK field.
	OTG_OTG_GLPMCFG_L1RSMOK_Msk = 0x10000
	// Bit L1RSMOK.
	OTG_OTG_GLPMCFG_L1RSMOK = 0x10000
	// Position of LPMCHIDX field.
	OTG_OTG_GLPMCFG_LPMCHIDX_Pos = 0x11
	// Bit mask of LPMCHIDX field.
	OTG_OTG_GLPMCFG_LPMCHIDX_Msk = 0x1e0000
	// Position of LPMRCNT field.
	OTG_OTG_GLPMCFG_LPMRCNT_Pos = 0x15
	// Bit mask of LPMRCNT field.
	OTG_OTG_GLPMCFG_LPMRCNT_Msk = 0xe00000
	// Position of SNDLPM field.
	OTG_OTG_GLPMCFG_SNDLPM_Pos = 0x18
	// Bit mask of SNDLPM field.
	OTG_OTG_GLPMCFG_SNDLPM_Msk = 0x1000000
	// Bit SNDLPM.
	OTG_OTG_GLPMCFG_SNDLPM = 0x1000000
	// Position of LPMRCNTSTS field.
	OTG_OTG_GLPMCFG_LPMRCNTSTS_Pos = 0x19
	// Bit mask of LPMRCNTSTS field.
	OTG_OTG_GLPMCFG_LPMRCNTSTS_Msk = 0xe000000
	// Position of ENBESL field.
	OTG_OTG_GLPMCFG_ENBESL_Pos = 0x1c
	// Bit mask of ENBESL field.
	OTG_OTG_GLPMCFG_ENBESL_Msk = 0x10000000
	// Bit ENBESL.
	OTG_OTG_GLPMCFG_ENBESL = 0x10000000

	// OTG_HPTXFSIZ: OTG host periodic transmit FIFO size register
	// Position of PTXSA field.
	OTG_OTG_HPTXFSIZ_PTXSA_Pos = 0x0
	// Bit mask of PTXSA field.
	OTG_OTG_HPTXFSIZ_PTXSA_Msk = 0xffff
	// Position of PTXFSIZ field.
	OTG_OTG_HPTXFSIZ_PTXFSIZ_Pos = 0x10
	// Bit mask of PTXFSIZ field.
	OTG_OTG_HPTXFSIZ_PTXFSIZ_Msk = 0xffff0000

	// OTG_DIEPTXF1: OTG device IN endpoint transmit FIFO 1 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF1_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF1_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF1_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF1_INEPTXFD_Msk = 0xffff0000

	// OTG_DIEPTXF2: OTG device IN endpoint transmit FIFO 2 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF2_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF2_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF2_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF2_INEPTXFD_Msk = 0xffff0000

	// OTG_DIEPTXF3: OTG device IN endpoint transmit FIFO 3 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF3_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF3_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF3_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF3_INEPTXFD_Msk = 0xffff0000

	// OTG_DIEPTXF4: OTG device IN endpoint transmit FIFO 4 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF4_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF4_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF4_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF4_INEPTXFD_Msk = 0xffff0000

	// OTG_DIEPTXF5: OTG device IN endpoint transmit FIFO 5 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF5_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF5_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF5_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF5_INEPTXFD_Msk = 0xffff0000

	// OTG_DIEPTXF6: OTG device IN endpoint transmit FIFO 6 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF6_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF6_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF6_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF6_INEPTXFD_Msk = 0xffff0000

	// OTG_DIEPTXF7: OTG device IN endpoint transmit FIFO 7 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF7_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF7_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF7_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF7_INEPTXFD_Msk = 0xffff0000

	// OTG_DIEPTXF8: OTG device IN endpoint transmit FIFO 8 size register
	// Position of INEPTXSA field.
	OTG_OTG_DIEPTXF8_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_OTG_DIEPTXF8_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_OTG_DIEPTXF8_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_OTG_DIEPTXF8_INEPTXFD_Msk = 0xffff0000

	// OTG_HCFG: This register configures the core after power-on. Do not make changes to this register after initializing the host.
	// Position of FSLSPCS field.
	OTG_OTG_HCFG_FSLSPCS_Pos = 0x0
	// Bit mask of FSLSPCS field.
	OTG_OTG_HCFG_FSLSPCS_Msk = 0x3
	// Position of FSLSS field.
	OTG_OTG_HCFG_FSLSS_Pos = 0x2
	// Bit mask of FSLSS field.
	OTG_OTG_HCFG_FSLSS_Msk = 0x4
	// Bit FSLSS.
	OTG_OTG_HCFG_FSLSS = 0x4
	// Position of DESCDMA field.
	OTG_OTG_HCFG_DESCDMA_Pos = 0x17
	// Bit mask of DESCDMA field.
	OTG_OTG_HCFG_DESCDMA_Msk = 0x800000
	// Bit DESCDMA.
	OTG_OTG_HCFG_DESCDMA = 0x800000
	// Position of FRLSTEN field.
	OTG_OTG_HCFG_FRLSTEN_Pos = 0x18
	// Bit mask of FRLSTEN field.
	OTG_OTG_HCFG_FRLSTEN_Msk = 0x3000000
	// Position of PERSSCHEDENA field.
	OTG_OTG_HCFG_PERSSCHEDENA_Pos = 0x1a
	// Bit mask of PERSSCHEDENA field.
	OTG_OTG_HCFG_PERSSCHEDENA_Msk = 0x4000000
	// Bit PERSSCHEDENA.
	OTG_OTG_HCFG_PERSSCHEDENA = 0x4000000

	// OTG_HFIR: This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
	// Position of FRIVL field.
	OTG_OTG_HFIR_FRIVL_Pos = 0x0
	// Bit mask of FRIVL field.
	OTG_OTG_HFIR_FRIVL_Msk = 0xffff
	// Position of RLDCTRL field.
	OTG_OTG_HFIR_RLDCTRL_Pos = 0x10
	// Bit mask of RLDCTRL field.
	OTG_OTG_HFIR_RLDCTRL_Msk = 0x10000
	// Bit RLDCTRL.
	OTG_OTG_HFIR_RLDCTRL = 0x10000

	// OTG_HFNUM: This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
	// Position of FRNUM field.
	OTG_OTG_HFNUM_FRNUM_Pos = 0x0
	// Bit mask of FRNUM field.
	OTG_OTG_HFNUM_FRNUM_Msk = 0xffff
	// Position of FTREM field.
	OTG_OTG_HFNUM_FTREM_Pos = 0x10
	// Bit mask of FTREM field.
	OTG_OTG_HFNUM_FTREM_Msk = 0xffff0000

	// OTG_HPTXSTS: This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
	// Position of PTXFSAVL field.
	OTG_OTG_HPTXSTS_PTXFSAVL_Pos = 0x0
	// Bit mask of PTXFSAVL field.
	OTG_OTG_HPTXSTS_PTXFSAVL_Msk = 0xffff
	// Position of PTXQSAV field.
	OTG_OTG_HPTXSTS_PTXQSAV_Pos = 0x10
	// Bit mask of PTXQSAV field.
	OTG_OTG_HPTXSTS_PTXQSAV_Msk = 0xff0000
	// Position of PTXQTOP field.
	OTG_OTG_HPTXSTS_PTXQTOP_Pos = 0x18
	// Bit mask of PTXQTOP field.
	OTG_OTG_HPTXSTS_PTXQTOP_Msk = 0xff000000

	// OTG_HAINT: When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
	// Position of HAINT field.
	OTG_OTG_HAINT_HAINT_Pos = 0x0
	// Bit mask of HAINT field.
	OTG_OTG_HAINT_HAINT_Msk = 0xffff

	// OTG_HAINTMSK: The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
	// Position of HAINTM field.
	OTG_OTG_HAINTMSK_HAINTM_Pos = 0x0
	// Bit mask of HAINTM field.
	OTG_OTG_HAINTMSK_HAINTM_Msk = 0xffff

	// OTG_HFLBADDR: This register holds the starting address of the frame list information (scatter/gather mode).
	// Position of HFLBADDR field.
	OTG_OTG_HFLBADDR_HFLBADDR_Pos = 0x0
	// Bit mask of HFLBADDR field.
	OTG_OTG_HFLBADDR_HFLBADDR_Msk = 0xffffffff

	// OTG_HPRT: This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
	// Position of PCSTS field.
	OTG_OTG_HPRT_PCSTS_Pos = 0x0
	// Bit mask of PCSTS field.
	OTG_OTG_HPRT_PCSTS_Msk = 0x1
	// Bit PCSTS.
	OTG_OTG_HPRT_PCSTS = 0x1
	// Position of PCDET field.
	OTG_OTG_HPRT_PCDET_Pos = 0x1
	// Bit mask of PCDET field.
	OTG_OTG_HPRT_PCDET_Msk = 0x2
	// Bit PCDET.
	OTG_OTG_HPRT_PCDET = 0x2
	// Position of PENA field.
	OTG_OTG_HPRT_PENA_Pos = 0x2
	// Bit mask of PENA field.
	OTG_OTG_HPRT_PENA_Msk = 0x4
	// Bit PENA.
	OTG_OTG_HPRT_PENA = 0x4
	// Position of PENCHNG field.
	OTG_OTG_HPRT_PENCHNG_Pos = 0x3
	// Bit mask of PENCHNG field.
	OTG_OTG_HPRT_PENCHNG_Msk = 0x8
	// Bit PENCHNG.
	OTG_OTG_HPRT_PENCHNG = 0x8
	// Position of POCA field.
	OTG_OTG_HPRT_POCA_Pos = 0x4
	// Bit mask of POCA field.
	OTG_OTG_HPRT_POCA_Msk = 0x10
	// Bit POCA.
	OTG_OTG_HPRT_POCA = 0x10
	// Position of POCCHNG field.
	OTG_OTG_HPRT_POCCHNG_Pos = 0x5
	// Bit mask of POCCHNG field.
	OTG_OTG_HPRT_POCCHNG_Msk = 0x20
	// Bit POCCHNG.
	OTG_OTG_HPRT_POCCHNG = 0x20
	// Position of PRES field.
	OTG_OTG_HPRT_PRES_Pos = 0x6
	// Bit mask of PRES field.
	OTG_OTG_HPRT_PRES_Msk = 0x40
	// Bit PRES.
	OTG_OTG_HPRT_PRES = 0x40
	// Position of PSUSP field.
	OTG_OTG_HPRT_PSUSP_Pos = 0x7
	// Bit mask of PSUSP field.
	OTG_OTG_HPRT_PSUSP_Msk = 0x80
	// Bit PSUSP.
	OTG_OTG_HPRT_PSUSP = 0x80
	// Position of PRST field.
	OTG_OTG_HPRT_PRST_Pos = 0x8
	// Bit mask of PRST field.
	OTG_OTG_HPRT_PRST_Msk = 0x100
	// Bit PRST.
	OTG_OTG_HPRT_PRST = 0x100
	// Position of PLSTS field.
	OTG_OTG_HPRT_PLSTS_Pos = 0xa
	// Bit mask of PLSTS field.
	OTG_OTG_HPRT_PLSTS_Msk = 0xc00
	// Position of PPWR field.
	OTG_OTG_HPRT_PPWR_Pos = 0xc
	// Bit mask of PPWR field.
	OTG_OTG_HPRT_PPWR_Msk = 0x1000
	// Bit PPWR.
	OTG_OTG_HPRT_PPWR = 0x1000
	// Position of PTCTL field.
	OTG_OTG_HPRT_PTCTL_Pos = 0xd
	// Bit mask of PTCTL field.
	OTG_OTG_HPRT_PTCTL_Msk = 0x1e000
	// Position of PSPD field.
	OTG_OTG_HPRT_PSPD_Pos = 0x11
	// Bit mask of PSPD field.
	OTG_OTG_HPRT_PSPD_Msk = 0x60000

	// OTG_HCCHAR0: OTG host channel 0 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR0_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR0_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR0_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR0_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR0_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR0_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR0_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR0_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR0_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR0_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR0_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR0_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR0_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR0_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR0_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR0_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR0_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR0_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR0_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR0_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR0_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR0_CHENA = 0x80000000

	// OTG_HCSPLT0: OTG host channel 0 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT0_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT0_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT0_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT0_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT0_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT0_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT0_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT0_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT0_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT0_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT0_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT0_SPLITEN = 0x80000000

	// OTG_HCINT0: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT0_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT0_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT0_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT0_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT0_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT0_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT0_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT0_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT0_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT0_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT0_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT0_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT0_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT0_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT0_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT0_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT0_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT0_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT0_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT0_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT0_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT0_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT0_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT0_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT0_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT0_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT0_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT0_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT0_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT0_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT0_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT0_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT0_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT0_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT0_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT0_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT0_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT0_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT0_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT0_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT0_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT0_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK0: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK0_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK0_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK0_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK0_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK0_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK0_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK0_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK0_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK0_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK0_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK0_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK0_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK0_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK0_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK0_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK0_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK0_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK0_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK0_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK0_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK0_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK0_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK0_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK0_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK0_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK0_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK0_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK0_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK0_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK0_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK0_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK0_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK0_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK0_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK0_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK0_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK0_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK0_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK0_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ0: OTG host channel 0 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ0_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ0_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ0_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ0_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ0_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ0_DPID_Msk = 0x60000000

	// OTG_HCDMA0: OTG host channel 0 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA0_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA0_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB0: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB0_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB0_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR1: OTG host channel 1 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR1_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR1_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR1_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR1_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR1_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR1_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR1_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR1_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR1_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR1_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR1_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR1_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR1_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR1_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR1_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR1_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR1_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR1_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR1_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR1_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR1_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR1_CHENA = 0x80000000

	// OTG_HCSPLT1: OTG host channel 1 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT1_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT1_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT1_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT1_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT1_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT1_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT1_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT1_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT1_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT1_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT1_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT1_SPLITEN = 0x80000000

	// OTG_HCINT1: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT1_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT1_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT1_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT1_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT1_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT1_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT1_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT1_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT1_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT1_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT1_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT1_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT1_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT1_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT1_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT1_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT1_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT1_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT1_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT1_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT1_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT1_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT1_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT1_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT1_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT1_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT1_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT1_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT1_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT1_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT1_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT1_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT1_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT1_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT1_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT1_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT1_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT1_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT1_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT1_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT1_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT1_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK1: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK1_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK1_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK1_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK1_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK1_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK1_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK1_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK1_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK1_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK1_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK1_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK1_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK1_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK1_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK1_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK1_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK1_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK1_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK1_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK1_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK1_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK1_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK1_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK1_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK1_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK1_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK1_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK1_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK1_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK1_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK1_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK1_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK1_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK1_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK1_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK1_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK1_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK1_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK1_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ1: OTG host channel 1 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ1_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ1_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ1_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ1_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ1_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ1_DPID_Msk = 0x60000000

	// OTG_HCDMA1: OTG host channel 1 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA1_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA1_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB1: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB1_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB1_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR2: OTG host channel 2 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR2_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR2_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR2_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR2_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR2_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR2_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR2_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR2_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR2_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR2_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR2_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR2_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR2_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR2_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR2_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR2_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR2_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR2_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR2_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR2_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR2_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR2_CHENA = 0x80000000

	// OTG_HCSPLT2: OTG host channel 2 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT2_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT2_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT2_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT2_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT2_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT2_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT2_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT2_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT2_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT2_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT2_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT2_SPLITEN = 0x80000000

	// OTG_HCINT2: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT2_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT2_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT2_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT2_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT2_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT2_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT2_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT2_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT2_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT2_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT2_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT2_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT2_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT2_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT2_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT2_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT2_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT2_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT2_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT2_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT2_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT2_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT2_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT2_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT2_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT2_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT2_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT2_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT2_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT2_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT2_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT2_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT2_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT2_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT2_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT2_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT2_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT2_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT2_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT2_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT2_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT2_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK2: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK2_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK2_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK2_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK2_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK2_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK2_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK2_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK2_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK2_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK2_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK2_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK2_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK2_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK2_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK2_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK2_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK2_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK2_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK2_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK2_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK2_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK2_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK2_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK2_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK2_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK2_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK2_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK2_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK2_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK2_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK2_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK2_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK2_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK2_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK2_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK2_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK2_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK2_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK2_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ2: OTG host channel 2 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ2_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ2_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ2_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ2_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ2_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ2_DPID_Msk = 0x60000000

	// OTG_HCDMA2: OTG host channel 2 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA2_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA2_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB2: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB2_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB2_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR3: OTG host channel 3 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR3_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR3_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR3_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR3_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR3_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR3_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR3_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR3_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR3_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR3_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR3_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR3_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR3_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR3_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR3_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR3_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR3_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR3_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR3_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR3_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR3_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR3_CHENA = 0x80000000

	// OTG_HCSPLT3: OTG host channel 3 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT3_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT3_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT3_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT3_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT3_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT3_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT3_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT3_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT3_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT3_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT3_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT3_SPLITEN = 0x80000000

	// OTG_HCINT3: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT3_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT3_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT3_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT3_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT3_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT3_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT3_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT3_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT3_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT3_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT3_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT3_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT3_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT3_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT3_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT3_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT3_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT3_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT3_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT3_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT3_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT3_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT3_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT3_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT3_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT3_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT3_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT3_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT3_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT3_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT3_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT3_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT3_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT3_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT3_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT3_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT3_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT3_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT3_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT3_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT3_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT3_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK3: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK3_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK3_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK3_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK3_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK3_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK3_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK3_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK3_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK3_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK3_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK3_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK3_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK3_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK3_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK3_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK3_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK3_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK3_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK3_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK3_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK3_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK3_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK3_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK3_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK3_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK3_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK3_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK3_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK3_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK3_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK3_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK3_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK3_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK3_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK3_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK3_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK3_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK3_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK3_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ3: OTG host channel 3 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ3_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ3_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ3_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ3_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ3_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ3_DPID_Msk = 0x60000000

	// OTG_HCDMA3: OTG host channel 3 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA3_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA3_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB3: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB3_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB3_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR4: OTG host channel 4 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR4_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR4_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR4_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR4_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR4_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR4_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR4_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR4_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR4_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR4_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR4_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR4_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR4_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR4_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR4_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR4_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR4_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR4_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR4_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR4_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR4_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR4_CHENA = 0x80000000

	// OTG_HCSPLT4: OTG host channel 4 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT4_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT4_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT4_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT4_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT4_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT4_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT4_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT4_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT4_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT4_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT4_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT4_SPLITEN = 0x80000000

	// OTG_HCINT4: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT4_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT4_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT4_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT4_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT4_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT4_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT4_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT4_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT4_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT4_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT4_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT4_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT4_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT4_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT4_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT4_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT4_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT4_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT4_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT4_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT4_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT4_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT4_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT4_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT4_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT4_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT4_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT4_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT4_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT4_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT4_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT4_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT4_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT4_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT4_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT4_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT4_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT4_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT4_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT4_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT4_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT4_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK4: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK4_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK4_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK4_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK4_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK4_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK4_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK4_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK4_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK4_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK4_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK4_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK4_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK4_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK4_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK4_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK4_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK4_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK4_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK4_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK4_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK4_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK4_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK4_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK4_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK4_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK4_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK4_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK4_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK4_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK4_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK4_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK4_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK4_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK4_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK4_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK4_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK4_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK4_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK4_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ4: OTG host channel 4 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ4_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ4_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ4_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ4_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ4_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ4_DPID_Msk = 0x60000000

	// OTG_HCDMA4: OTG host channel 4 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA4_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA4_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB4: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB4_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB4_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR5: OTG host channel 5 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR5_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR5_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR5_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR5_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR5_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR5_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR5_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR5_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR5_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR5_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR5_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR5_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR5_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR5_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR5_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR5_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR5_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR5_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR5_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR5_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR5_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR5_CHENA = 0x80000000

	// OTG_HCSPLT5: OTG host channel 5 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT5_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT5_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT5_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT5_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT5_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT5_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT5_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT5_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT5_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT5_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT5_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT5_SPLITEN = 0x80000000

	// OTG_HCINT5: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT5_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT5_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT5_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT5_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT5_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT5_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT5_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT5_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT5_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT5_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT5_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT5_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT5_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT5_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT5_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT5_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT5_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT5_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT5_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT5_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT5_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT5_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT5_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT5_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT5_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT5_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT5_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT5_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT5_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT5_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT5_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT5_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT5_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT5_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT5_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT5_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT5_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT5_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT5_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT5_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT5_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT5_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK5: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK5_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK5_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK5_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK5_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK5_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK5_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK5_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK5_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK5_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK5_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK5_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK5_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK5_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK5_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK5_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK5_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK5_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK5_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK5_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK5_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK5_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK5_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK5_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK5_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK5_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK5_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK5_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK5_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK5_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK5_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK5_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK5_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK5_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK5_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK5_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK5_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK5_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK5_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK5_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ5: OTG host channel 5 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ5_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ5_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ5_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ5_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ5_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ5_DPID_Msk = 0x60000000

	// OTG_HCDMA5: OTG host channel 5 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA5_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA5_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB5: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB5_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB5_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR6: OTG host channel 6 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR6_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR6_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR6_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR6_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR6_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR6_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR6_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR6_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR6_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR6_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR6_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR6_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR6_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR6_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR6_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR6_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR6_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR6_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR6_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR6_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR6_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR6_CHENA = 0x80000000

	// OTG_HCSPLT6: OTG host channel 6 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT6_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT6_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT6_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT6_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT6_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT6_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT6_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT6_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT6_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT6_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT6_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT6_SPLITEN = 0x80000000

	// OTG_HCINT6: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT6_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT6_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT6_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT6_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT6_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT6_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT6_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT6_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT6_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT6_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT6_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT6_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT6_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT6_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT6_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT6_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT6_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT6_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT6_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT6_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT6_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT6_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT6_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT6_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT6_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT6_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT6_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT6_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT6_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT6_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT6_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT6_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT6_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT6_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT6_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT6_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT6_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT6_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT6_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT6_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT6_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT6_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK6: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK6_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK6_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK6_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK6_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK6_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK6_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK6_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK6_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK6_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK6_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK6_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK6_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK6_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK6_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK6_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK6_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK6_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK6_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK6_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK6_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK6_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK6_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK6_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK6_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK6_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK6_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK6_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK6_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK6_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK6_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK6_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK6_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK6_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK6_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK6_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK6_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK6_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK6_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK6_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ6: OTG host channel 6 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ6_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ6_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ6_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ6_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ6_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ6_DPID_Msk = 0x60000000

	// OTG_HCDMA6: OTG host channel 6 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA6_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA6_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB6: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB6_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB6_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR7: OTG host channel 7 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR7_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR7_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR7_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR7_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR7_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR7_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR7_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR7_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR7_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR7_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR7_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR7_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR7_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR7_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR7_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR7_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR7_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR7_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR7_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR7_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR7_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR7_CHENA = 0x80000000

	// OTG_HCSPLT7: OTG host channel 7 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT7_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT7_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT7_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT7_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT7_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT7_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT7_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT7_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT7_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT7_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT7_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT7_SPLITEN = 0x80000000

	// OTG_HCINT7: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT7_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT7_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT7_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT7_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT7_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT7_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT7_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT7_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT7_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT7_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT7_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT7_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT7_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT7_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT7_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT7_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT7_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT7_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT7_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT7_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT7_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT7_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT7_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT7_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT7_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT7_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT7_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT7_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT7_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT7_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT7_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT7_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT7_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT7_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT7_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT7_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT7_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT7_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT7_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT7_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT7_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT7_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK7: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK7_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK7_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK7_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK7_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK7_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK7_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK7_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK7_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK7_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK7_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK7_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK7_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK7_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK7_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK7_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK7_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK7_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK7_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK7_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK7_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK7_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK7_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK7_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK7_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK7_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK7_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK7_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK7_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK7_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK7_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK7_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK7_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK7_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK7_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK7_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK7_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK7_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK7_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK7_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ7: OTG host channel 7 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ7_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ7_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ7_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ7_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ7_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ7_DPID_Msk = 0x60000000

	// OTG_HCDMA7: OTG host channel 7 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA7_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA7_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB7: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB7_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB7_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR8: OTG host channel 8 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR8_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR8_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR8_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR8_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR8_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR8_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR8_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR8_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR8_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR8_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR8_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR8_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR8_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR8_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR8_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR8_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR8_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR8_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR8_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR8_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR8_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR8_CHENA = 0x80000000

	// OTG_HCSPLT8: OTG host channel 8 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT8_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT8_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT8_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT8_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT8_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT8_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT8_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT8_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT8_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT8_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT8_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT8_SPLITEN = 0x80000000

	// OTG_HCINT8: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT8_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT8_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT8_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT8_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT8_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT8_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT8_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT8_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT8_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT8_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT8_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT8_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT8_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT8_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT8_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT8_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT8_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT8_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT8_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT8_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT8_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT8_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT8_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT8_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT8_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT8_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT8_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT8_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT8_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT8_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT8_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT8_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT8_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT8_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT8_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT8_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT8_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT8_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT8_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT8_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT8_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT8_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK8: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK8_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK8_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK8_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK8_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK8_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK8_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK8_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK8_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK8_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK8_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK8_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK8_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK8_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK8_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK8_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK8_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK8_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK8_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK8_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK8_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK8_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK8_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK8_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK8_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK8_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK8_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK8_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK8_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK8_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK8_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK8_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK8_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK8_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK8_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK8_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK8_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK8_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK8_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK8_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ8: OTG host channel 8 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ8_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ8_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ8_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ8_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ8_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ8_DPID_Msk = 0x60000000

	// OTG_HCDMA8: OTG host channel 8 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA8_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA8_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB8: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB8_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB8_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR9: OTG host channel 9 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR9_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR9_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR9_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR9_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR9_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR9_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR9_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR9_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR9_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR9_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR9_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR9_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR9_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR9_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR9_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR9_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR9_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR9_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR9_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR9_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR9_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR9_CHENA = 0x80000000

	// OTG_HCSPLT9: OTG host channel 9 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT9_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT9_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT9_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT9_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT9_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT9_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT9_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT9_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT9_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT9_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT9_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT9_SPLITEN = 0x80000000

	// OTG_HCINT9: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT9_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT9_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT9_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT9_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT9_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT9_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT9_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT9_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT9_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT9_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT9_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT9_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT9_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT9_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT9_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT9_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT9_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT9_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT9_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT9_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT9_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT9_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT9_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT9_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT9_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT9_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT9_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT9_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT9_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT9_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT9_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT9_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT9_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT9_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT9_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT9_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT9_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT9_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT9_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT9_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT9_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT9_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK9: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK9_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK9_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK9_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK9_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK9_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK9_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK9_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK9_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK9_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK9_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK9_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK9_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK9_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK9_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK9_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK9_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK9_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK9_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK9_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK9_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK9_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK9_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK9_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK9_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK9_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK9_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK9_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK9_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK9_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK9_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK9_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK9_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK9_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK9_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK9_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK9_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK9_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK9_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK9_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ9: OTG host channel 9 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ9_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ9_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ9_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ9_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ9_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ9_DPID_Msk = 0x60000000

	// OTG_HCDMA9: OTG host channel 9 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA9_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA9_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB9: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB9_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB9_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR10: OTG host channel 10 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR10_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR10_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR10_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR10_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR10_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR10_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR10_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR10_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR10_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR10_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR10_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR10_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR10_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR10_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR10_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR10_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR10_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR10_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR10_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR10_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR10_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR10_CHENA = 0x80000000

	// OTG_HCSPLT10: OTG host channel 10 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT10_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT10_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT10_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT10_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT10_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT10_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT10_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT10_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT10_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT10_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT10_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT10_SPLITEN = 0x80000000

	// OTG_HCINT10: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT10_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT10_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT10_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT10_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT10_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT10_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT10_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT10_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT10_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT10_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT10_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT10_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT10_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT10_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT10_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT10_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT10_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT10_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT10_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT10_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT10_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT10_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT10_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT10_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT10_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT10_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT10_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT10_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT10_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT10_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT10_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT10_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT10_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT10_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT10_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT10_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT10_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT10_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT10_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT10_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT10_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT10_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK10: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK10_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK10_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK10_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK10_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK10_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK10_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK10_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK10_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK10_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK10_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK10_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK10_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK10_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK10_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK10_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK10_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK10_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK10_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK10_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK10_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK10_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK10_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK10_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK10_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK10_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK10_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK10_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK10_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK10_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK10_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK10_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK10_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK10_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK10_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK10_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK10_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK10_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK10_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK10_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ10: OTG host channel 10 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ10_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ10_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ10_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ10_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ10_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ10_DPID_Msk = 0x60000000

	// OTG_HCDMA10: OTG host channel 10 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA10_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA10_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB10: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB10_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB10_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR11: OTG host channel 11 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR11_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR11_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR11_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR11_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR11_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR11_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR11_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR11_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR11_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR11_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR11_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR11_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR11_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR11_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR11_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR11_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR11_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR11_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR11_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR11_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR11_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR11_CHENA = 0x80000000

	// OTG_HCSPLT11: OTG host channel 11 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT11_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT11_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT11_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT11_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT11_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT11_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT11_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT11_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT11_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT11_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT11_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT11_SPLITEN = 0x80000000

	// OTG_HCINT11: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT11_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT11_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT11_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT11_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT11_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT11_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT11_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT11_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT11_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT11_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT11_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT11_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT11_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT11_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT11_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT11_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT11_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT11_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT11_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT11_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT11_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT11_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT11_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT11_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT11_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT11_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT11_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT11_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT11_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT11_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT11_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT11_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT11_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT11_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT11_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT11_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT11_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT11_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT11_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT11_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT11_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT11_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK11: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK11_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK11_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK11_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK11_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK11_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK11_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK11_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK11_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK11_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK11_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK11_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK11_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK11_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK11_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK11_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK11_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK11_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK11_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK11_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK11_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK11_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK11_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK11_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK11_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK11_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK11_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK11_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK11_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK11_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK11_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK11_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK11_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK11_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK11_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK11_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK11_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK11_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK11_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK11_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ11: OTG host channel 11 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ11_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ11_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ11_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ11_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ11_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ11_DPID_Msk = 0x60000000

	// OTG_HCDMA11: OTG host channel 11 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA11_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA11_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB11: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB11_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB11_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR12: OTG host channel 12 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR12_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR12_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR12_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR12_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR12_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR12_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR12_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR12_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR12_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR12_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR12_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR12_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR12_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR12_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR12_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR12_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR12_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR12_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR12_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR12_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR12_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR12_CHENA = 0x80000000

	// OTG_HCSPLT12: OTG host channel 12 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT12_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT12_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT12_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT12_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT12_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT12_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT12_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT12_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT12_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT12_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT12_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT12_SPLITEN = 0x80000000

	// OTG_HCINT12: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT12_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT12_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT12_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT12_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT12_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT12_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT12_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT12_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT12_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT12_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT12_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT12_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT12_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT12_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT12_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT12_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT12_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT12_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT12_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT12_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT12_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT12_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT12_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT12_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT12_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT12_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT12_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT12_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT12_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT12_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT12_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT12_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT12_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT12_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT12_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT12_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT12_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT12_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT12_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT12_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT12_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT12_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK12: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK12_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK12_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK12_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK12_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK12_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK12_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK12_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK12_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK12_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK12_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK12_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK12_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK12_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK12_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK12_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK12_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK12_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK12_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK12_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK12_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK12_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK12_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK12_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK12_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK12_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK12_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK12_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK12_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK12_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK12_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK12_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK12_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK12_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK12_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK12_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK12_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK12_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK12_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK12_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ12: OTG host channel 12 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ12_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ12_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ12_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ12_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ12_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ12_DPID_Msk = 0x60000000

	// OTG_HCDMA12: OTG host channel 12 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA12_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA12_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB12: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB12_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB12_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR13: OTG host channel 13 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR13_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR13_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR13_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR13_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR13_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR13_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR13_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR13_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR13_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR13_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR13_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR13_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR13_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR13_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR13_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR13_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR13_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR13_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR13_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR13_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR13_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR13_CHENA = 0x80000000

	// OTG_HCSPLT13: OTG host channel 13 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT13_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT13_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT13_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT13_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT13_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT13_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT13_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT13_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT13_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT13_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT13_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT13_SPLITEN = 0x80000000

	// OTG_HCINT13: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT13_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT13_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT13_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT13_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT13_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT13_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT13_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT13_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT13_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT13_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT13_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT13_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT13_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT13_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT13_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT13_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT13_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT13_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT13_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT13_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT13_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT13_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT13_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT13_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT13_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT13_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT13_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT13_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT13_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT13_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT13_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT13_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT13_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT13_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT13_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT13_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT13_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT13_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT13_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT13_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT13_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT13_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK13: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK13_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK13_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK13_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK13_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK13_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK13_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK13_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK13_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK13_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK13_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK13_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK13_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK13_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK13_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK13_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK13_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK13_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK13_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK13_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK13_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK13_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK13_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK13_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK13_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK13_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK13_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK13_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK13_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK13_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK13_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK13_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK13_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK13_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK13_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK13_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK13_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK13_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK13_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK13_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ13: OTG host channel 13 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ13_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ13_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ13_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ13_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ13_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ13_DPID_Msk = 0x60000000

	// OTG_HCDMA13: OTG host channel 13 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA13_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA13_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB13: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB13_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB13_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR14: OTG host channel 14 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR14_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR14_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR14_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR14_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR14_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR14_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR14_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR14_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR14_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR14_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR14_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR14_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR14_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR14_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR14_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR14_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR14_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR14_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR14_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR14_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR14_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR14_CHENA = 0x80000000

	// OTG_HCSPLT14: OTG host channel 14 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT14_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT14_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT14_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT14_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT14_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT14_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT14_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT14_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT14_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT14_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT14_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT14_SPLITEN = 0x80000000

	// OTG_HCINT14: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT14_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT14_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT14_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT14_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT14_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT14_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT14_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT14_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT14_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT14_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT14_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT14_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT14_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT14_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT14_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT14_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT14_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT14_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT14_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT14_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT14_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT14_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT14_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT14_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT14_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT14_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT14_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT14_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT14_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT14_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT14_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT14_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT14_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT14_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT14_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT14_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT14_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT14_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT14_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT14_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT14_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT14_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK14: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK14_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK14_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK14_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK14_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK14_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK14_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK14_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK14_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK14_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK14_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK14_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK14_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK14_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK14_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK14_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK14_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK14_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK14_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK14_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK14_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK14_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK14_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK14_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK14_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK14_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK14_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK14_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK14_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK14_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK14_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK14_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK14_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK14_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK14_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK14_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK14_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK14_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK14_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK14_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ14: OTG host channel 14 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ14_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ14_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ14_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ14_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ14_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ14_DPID_Msk = 0x60000000

	// OTG_HCDMA14: OTG host channel 14 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA14_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA14_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB14: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB14_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB14_HCDMAB_Msk = 0xffffffff

	// OTG_HCCHAR15: OTG host channel 15 characteristics register
	// Position of MPSIZ field.
	OTG_OTG_HCCHAR15_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_HCCHAR15_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_OTG_HCCHAR15_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_OTG_HCCHAR15_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_OTG_HCCHAR15_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_OTG_HCCHAR15_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_OTG_HCCHAR15_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_OTG_HCCHAR15_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_OTG_HCCHAR15_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_OTG_HCCHAR15_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_OTG_HCCHAR15_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_HCCHAR15_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_OTG_HCCHAR15_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_OTG_HCCHAR15_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_OTG_HCCHAR15_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_OTG_HCCHAR15_DAD_Msk = 0x1fc00000
	// Position of CHDIS field.
	OTG_OTG_HCCHAR15_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_OTG_HCCHAR15_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_OTG_HCCHAR15_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_OTG_HCCHAR15_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_OTG_HCCHAR15_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_OTG_HCCHAR15_CHENA = 0x80000000

	// OTG_HCSPLT15: OTG host channel 15 split control register
	// Position of PRTADDR field.
	OTG_OTG_HCSPLT15_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_OTG_HCSPLT15_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_OTG_HCSPLT15_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_OTG_HCSPLT15_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_OTG_HCSPLT15_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_OTG_HCSPLT15_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_OTG_HCSPLT15_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_OTG_HCSPLT15_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_OTG_HCSPLT15_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_OTG_HCSPLT15_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_OTG_HCSPLT15_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_OTG_HCSPLT15_SPLITEN = 0x80000000

	// OTG_HCINT15: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_HCINT15_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_HCINT15_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_HCINT15_XFRC = 0x1
	// Position of CHH field.
	OTG_OTG_HCINT15_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_OTG_HCINT15_CHH_Msk = 0x2
	// Bit CHH.
	OTG_OTG_HCINT15_CHH = 0x2
	// Position of AHBERR field.
	OTG_OTG_HCINT15_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_HCINT15_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_HCINT15_AHBERR = 0x4
	// Position of STALL field.
	OTG_OTG_HCINT15_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_OTG_HCINT15_STALL_Msk = 0x8
	// Bit STALL.
	OTG_OTG_HCINT15_STALL = 0x8
	// Position of NAK field.
	OTG_OTG_HCINT15_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_OTG_HCINT15_NAK_Msk = 0x10
	// Bit NAK.
	OTG_OTG_HCINT15_NAK = 0x10
	// Position of ACK field.
	OTG_OTG_HCINT15_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_OTG_HCINT15_ACK_Msk = 0x20
	// Bit ACK.
	OTG_OTG_HCINT15_ACK = 0x20
	// Position of NYET field.
	OTG_OTG_HCINT15_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINT15_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINT15_NYET = 0x40
	// Position of TXERR field.
	OTG_OTG_HCINT15_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_OTG_HCINT15_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_OTG_HCINT15_TXERR = 0x80
	// Position of BBERR field.
	OTG_OTG_HCINT15_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_OTG_HCINT15_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_OTG_HCINT15_BBERR = 0x100
	// Position of FRMOR field.
	OTG_OTG_HCINT15_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_OTG_HCINT15_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_OTG_HCINT15_FRMOR = 0x200
	// Position of DTERR field.
	OTG_OTG_HCINT15_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_OTG_HCINT15_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_OTG_HCINT15_DTERR = 0x400
	// Position of BNA field.
	OTG_OTG_HCINT15_BNA_Pos = 0xb
	// Bit mask of BNA field.
	OTG_OTG_HCINT15_BNA_Msk = 0x800
	// Bit BNA.
	OTG_OTG_HCINT15_BNA = 0x800
	// Position of XCSXACTERR field.
	OTG_OTG_HCINT15_XCSXACTERR_Pos = 0xc
	// Bit mask of XCSXACTERR field.
	OTG_OTG_HCINT15_XCSXACTERR_Msk = 0x1000
	// Bit XCSXACTERR.
	OTG_OTG_HCINT15_XCSXACTERR = 0x1000
	// Position of DESCLSTROLL field.
	OTG_OTG_HCINT15_DESCLSTROLL_Pos = 0xd
	// Bit mask of DESCLSTROLL field.
	OTG_OTG_HCINT15_DESCLSTROLL_Msk = 0x2000
	// Bit DESCLSTROLL.
	OTG_OTG_HCINT15_DESCLSTROLL = 0x2000

	// OTG_HCINTMSK15: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_OTG_HCINTMSK15_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HCINTMSK15_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HCINTMSK15_XFRCM = 0x1
	// Position of CHHM field.
	OTG_OTG_HCINTMSK15_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_OTG_HCINTMSK15_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_OTG_HCINTMSK15_CHHM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HCINTMSK15_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HCINTMSK15_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HCINTMSK15_AHBERRM = 0x4
	// Position of STALLM field.
	OTG_OTG_HCINTMSK15_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_OTG_HCINTMSK15_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_OTG_HCINTMSK15_STALLM = 0x8
	// Position of NAKM field.
	OTG_OTG_HCINTMSK15_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_OTG_HCINTMSK15_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_OTG_HCINTMSK15_NAKM = 0x10
	// Position of ACKM field.
	OTG_OTG_HCINTMSK15_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_OTG_HCINTMSK15_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_OTG_HCINTMSK15_ACKM = 0x20
	// Position of NYET field.
	OTG_OTG_HCINTMSK15_NYET_Pos = 0x6
	// Bit mask of NYET field.
	OTG_OTG_HCINTMSK15_NYET_Msk = 0x40
	// Bit NYET.
	OTG_OTG_HCINTMSK15_NYET = 0x40
	// Position of TXERRM field.
	OTG_OTG_HCINTMSK15_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_OTG_HCINTMSK15_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_OTG_HCINTMSK15_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_OTG_HCINTMSK15_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_OTG_HCINTMSK15_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_OTG_HCINTMSK15_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_OTG_HCINTMSK15_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_OTG_HCINTMSK15_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_OTG_HCINTMSK15_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_OTG_HCINTMSK15_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_OTG_HCINTMSK15_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_OTG_HCINTMSK15_DTERRM = 0x400
	// Position of BNAMSK field.
	OTG_OTG_HCINTMSK15_BNAMSK_Pos = 0xb
	// Bit mask of BNAMSK field.
	OTG_OTG_HCINTMSK15_BNAMSK_Msk = 0x800
	// Bit BNAMSK.
	OTG_OTG_HCINTMSK15_BNAMSK = 0x800
	// Position of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK15_DESCLSTROLLMSK_Pos = 0xd
	// Bit mask of DESCLSTROLLMSK field.
	OTG_OTG_HCINTMSK15_DESCLSTROLLMSK_Msk = 0x2000
	// Bit DESCLSTROLLMSK.
	OTG_OTG_HCINTMSK15_DESCLSTROLLMSK = 0x2000

	// OTG_HCTSIZ15: OTG host channel 15 transfer size register
	// Position of XFRSIZ field.
	OTG_OTG_HCTSIZ15_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_HCTSIZ15_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_HCTSIZ15_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_HCTSIZ15_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_OTG_HCTSIZ15_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_OTG_HCTSIZ15_DPID_Msk = 0x60000000

	// OTG_HCDMA15: OTG host channel 15 DMA address register in buffer DMA [alternate]
	// Position of DMAADDR field.
	OTG_OTG_HCDMA15_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_HCDMA15_DMAADDR_Msk = 0xffffffff

	// OTG_HCDMAB15: OTG host channel-n DMA address buffer register
	// Position of HCDMAB field.
	OTG_OTG_HCDMAB15_HCDMAB_Pos = 0x0
	// Bit mask of HCDMAB field.
	OTG_OTG_HCDMAB15_HCDMAB_Msk = 0xffffffff

	// OTG_DCFG: This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
	// Position of DSPD field.
	OTG_OTG_DCFG_DSPD_Pos = 0x0
	// Bit mask of DSPD field.
	OTG_OTG_DCFG_DSPD_Msk = 0x3
	// Position of NZLSOHSK field.
	OTG_OTG_DCFG_NZLSOHSK_Pos = 0x2
	// Bit mask of NZLSOHSK field.
	OTG_OTG_DCFG_NZLSOHSK_Msk = 0x4
	// Bit NZLSOHSK.
	OTG_OTG_DCFG_NZLSOHSK = 0x4
	// Position of DAD field.
	OTG_OTG_DCFG_DAD_Pos = 0x4
	// Bit mask of DAD field.
	OTG_OTG_DCFG_DAD_Msk = 0x7f0
	// Position of PFIVL field.
	OTG_OTG_DCFG_PFIVL_Pos = 0xb
	// Bit mask of PFIVL field.
	OTG_OTG_DCFG_PFIVL_Msk = 0x1800
	// Position of XCVRDLY field.
	OTG_OTG_DCFG_XCVRDLY_Pos = 0xe
	// Bit mask of XCVRDLY field.
	OTG_OTG_DCFG_XCVRDLY_Msk = 0x4000
	// Bit XCVRDLY.
	OTG_OTG_DCFG_XCVRDLY = 0x4000
	// Position of ERRATIM field.
	OTG_OTG_DCFG_ERRATIM_Pos = 0xf
	// Bit mask of ERRATIM field.
	OTG_OTG_DCFG_ERRATIM_Msk = 0x8000
	// Bit ERRATIM.
	OTG_OTG_DCFG_ERRATIM = 0x8000
	// Position of PERSCHIVL field.
	OTG_OTG_DCFG_PERSCHIVL_Pos = 0x18
	// Bit mask of PERSCHIVL field.
	OTG_OTG_DCFG_PERSCHIVL_Msk = 0x3000000

	// OTG_DCTL: OTG device control register
	// Position of RWUSIG field.
	OTG_OTG_DCTL_RWUSIG_Pos = 0x0
	// Bit mask of RWUSIG field.
	OTG_OTG_DCTL_RWUSIG_Msk = 0x1
	// Bit RWUSIG.
	OTG_OTG_DCTL_RWUSIG = 0x1
	// Position of SDIS field.
	OTG_OTG_DCTL_SDIS_Pos = 0x1
	// Bit mask of SDIS field.
	OTG_OTG_DCTL_SDIS_Msk = 0x2
	// Bit SDIS.
	OTG_OTG_DCTL_SDIS = 0x2
	// Position of GINSTS field.
	OTG_OTG_DCTL_GINSTS_Pos = 0x2
	// Bit mask of GINSTS field.
	OTG_OTG_DCTL_GINSTS_Msk = 0x4
	// Bit GINSTS.
	OTG_OTG_DCTL_GINSTS = 0x4
	// Position of GONSTS field.
	OTG_OTG_DCTL_GONSTS_Pos = 0x3
	// Bit mask of GONSTS field.
	OTG_OTG_DCTL_GONSTS_Msk = 0x8
	// Bit GONSTS.
	OTG_OTG_DCTL_GONSTS = 0x8
	// Position of TCTL field.
	OTG_OTG_DCTL_TCTL_Pos = 0x4
	// Bit mask of TCTL field.
	OTG_OTG_DCTL_TCTL_Msk = 0x70
	// Position of SGINAK field.
	OTG_OTG_DCTL_SGINAK_Pos = 0x7
	// Bit mask of SGINAK field.
	OTG_OTG_DCTL_SGINAK_Msk = 0x80
	// Bit SGINAK.
	OTG_OTG_DCTL_SGINAK = 0x80
	// Position of CGINAK field.
	OTG_OTG_DCTL_CGINAK_Pos = 0x8
	// Bit mask of CGINAK field.
	OTG_OTG_DCTL_CGINAK_Msk = 0x100
	// Bit CGINAK.
	OTG_OTG_DCTL_CGINAK = 0x100
	// Position of SGONAK field.
	OTG_OTG_DCTL_SGONAK_Pos = 0x9
	// Bit mask of SGONAK field.
	OTG_OTG_DCTL_SGONAK_Msk = 0x200
	// Bit SGONAK.
	OTG_OTG_DCTL_SGONAK = 0x200
	// Position of CGONAK field.
	OTG_OTG_DCTL_CGONAK_Pos = 0xa
	// Bit mask of CGONAK field.
	OTG_OTG_DCTL_CGONAK_Msk = 0x400
	// Bit CGONAK.
	OTG_OTG_DCTL_CGONAK = 0x400
	// Position of POPRGDNE field.
	OTG_OTG_DCTL_POPRGDNE_Pos = 0xb
	// Bit mask of POPRGDNE field.
	OTG_OTG_DCTL_POPRGDNE_Msk = 0x800
	// Bit POPRGDNE.
	OTG_OTG_DCTL_POPRGDNE = 0x800
	// Position of DSBESLRJCT field.
	OTG_OTG_DCTL_DSBESLRJCT_Pos = 0x12
	// Bit mask of DSBESLRJCT field.
	OTG_OTG_DCTL_DSBESLRJCT_Msk = 0x40000
	// Bit DSBESLRJCT.
	OTG_OTG_DCTL_DSBESLRJCT = 0x40000

	// OTG_DSTS: This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register.
	// Position of SUSPSTS field.
	OTG_OTG_DSTS_SUSPSTS_Pos = 0x0
	// Bit mask of SUSPSTS field.
	OTG_OTG_DSTS_SUSPSTS_Msk = 0x1
	// Bit SUSPSTS.
	OTG_OTG_DSTS_SUSPSTS = 0x1
	// Position of ENUMSPD field.
	OTG_OTG_DSTS_ENUMSPD_Pos = 0x1
	// Bit mask of ENUMSPD field.
	OTG_OTG_DSTS_ENUMSPD_Msk = 0x6
	// Position of EERR field.
	OTG_OTG_DSTS_EERR_Pos = 0x3
	// Bit mask of EERR field.
	OTG_OTG_DSTS_EERR_Msk = 0x8
	// Bit EERR.
	OTG_OTG_DSTS_EERR = 0x8
	// Position of FNSOF field.
	OTG_OTG_DSTS_FNSOF_Pos = 0x8
	// Bit mask of FNSOF field.
	OTG_OTG_DSTS_FNSOF_Msk = 0x3fff00
	// Position of DEVLNSTS field.
	OTG_OTG_DSTS_DEVLNSTS_Pos = 0x16
	// Bit mask of DEVLNSTS field.
	OTG_OTG_DSTS_DEVLNSTS_Msk = 0xc00000

	// OTG_DIEPMSK: This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
	// Position of XFRCM field.
	OTG_OTG_DIEPMSK_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_DIEPMSK_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_DIEPMSK_XFRCM = 0x1
	// Position of EPDM field.
	OTG_OTG_DIEPMSK_EPDM_Pos = 0x1
	// Bit mask of EPDM field.
	OTG_OTG_DIEPMSK_EPDM_Msk = 0x2
	// Bit EPDM.
	OTG_OTG_DIEPMSK_EPDM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_DIEPMSK_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_DIEPMSK_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_DIEPMSK_AHBERRM = 0x4
	// Position of TOM field.
	OTG_OTG_DIEPMSK_TOM_Pos = 0x3
	// Bit mask of TOM field.
	OTG_OTG_DIEPMSK_TOM_Msk = 0x8
	// Bit TOM.
	OTG_OTG_DIEPMSK_TOM = 0x8
	// Position of ITTXFEMSK field.
	OTG_OTG_DIEPMSK_ITTXFEMSK_Pos = 0x4
	// Bit mask of ITTXFEMSK field.
	OTG_OTG_DIEPMSK_ITTXFEMSK_Msk = 0x10
	// Bit ITTXFEMSK.
	OTG_OTG_DIEPMSK_ITTXFEMSK = 0x10
	// Position of INEPNMM field.
	OTG_OTG_DIEPMSK_INEPNMM_Pos = 0x5
	// Bit mask of INEPNMM field.
	OTG_OTG_DIEPMSK_INEPNMM_Msk = 0x20
	// Bit INEPNMM.
	OTG_OTG_DIEPMSK_INEPNMM = 0x20
	// Position of INEPNEM field.
	OTG_OTG_DIEPMSK_INEPNEM_Pos = 0x6
	// Bit mask of INEPNEM field.
	OTG_OTG_DIEPMSK_INEPNEM_Msk = 0x40
	// Bit INEPNEM.
	OTG_OTG_DIEPMSK_INEPNEM = 0x40
	// Position of TXFURM field.
	OTG_OTG_DIEPMSK_TXFURM_Pos = 0x8
	// Bit mask of TXFURM field.
	OTG_OTG_DIEPMSK_TXFURM_Msk = 0x100
	// Bit TXFURM.
	OTG_OTG_DIEPMSK_TXFURM = 0x100
	// Position of BNAM field.
	OTG_OTG_DIEPMSK_BNAM_Pos = 0x9
	// Bit mask of BNAM field.
	OTG_OTG_DIEPMSK_BNAM_Msk = 0x200
	// Bit BNAM.
	OTG_OTG_DIEPMSK_BNAM = 0x200
	// Position of NAKM field.
	OTG_OTG_DIEPMSK_NAKM_Pos = 0xd
	// Bit mask of NAKM field.
	OTG_OTG_DIEPMSK_NAKM_Msk = 0x2000
	// Bit NAKM.
	OTG_OTG_DIEPMSK_NAKM = 0x2000

	// OTG_DOEPMSK: This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
	// Position of XFRCM field.
	OTG_OTG_DOEPMSK_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_DOEPMSK_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_DOEPMSK_XFRCM = 0x1
	// Position of EPDM field.
	OTG_OTG_DOEPMSK_EPDM_Pos = 0x1
	// Bit mask of EPDM field.
	OTG_OTG_DOEPMSK_EPDM_Msk = 0x2
	// Bit EPDM.
	OTG_OTG_DOEPMSK_EPDM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_DOEPMSK_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_DOEPMSK_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_DOEPMSK_AHBERRM = 0x4
	// Position of STUPM field.
	OTG_OTG_DOEPMSK_STUPM_Pos = 0x3
	// Bit mask of STUPM field.
	OTG_OTG_DOEPMSK_STUPM_Msk = 0x8
	// Bit STUPM.
	OTG_OTG_DOEPMSK_STUPM = 0x8
	// Position of OTEPDM field.
	OTG_OTG_DOEPMSK_OTEPDM_Pos = 0x4
	// Bit mask of OTEPDM field.
	OTG_OTG_DOEPMSK_OTEPDM_Msk = 0x10
	// Bit OTEPDM.
	OTG_OTG_DOEPMSK_OTEPDM = 0x10
	// Position of STSPHSRXM field.
	OTG_OTG_DOEPMSK_STSPHSRXM_Pos = 0x5
	// Bit mask of STSPHSRXM field.
	OTG_OTG_DOEPMSK_STSPHSRXM_Msk = 0x20
	// Bit STSPHSRXM.
	OTG_OTG_DOEPMSK_STSPHSRXM = 0x20
	// Position of B2BSTUPM field.
	OTG_OTG_DOEPMSK_B2BSTUPM_Pos = 0x6
	// Bit mask of B2BSTUPM field.
	OTG_OTG_DOEPMSK_B2BSTUPM_Msk = 0x40
	// Bit B2BSTUPM.
	OTG_OTG_DOEPMSK_B2BSTUPM = 0x40
	// Position of OUTPKTERRM field.
	OTG_OTG_DOEPMSK_OUTPKTERRM_Pos = 0x8
	// Bit mask of OUTPKTERRM field.
	OTG_OTG_DOEPMSK_OUTPKTERRM_Msk = 0x100
	// Bit OUTPKTERRM.
	OTG_OTG_DOEPMSK_OUTPKTERRM = 0x100
	// Position of BNAM field.
	OTG_OTG_DOEPMSK_BNAM_Pos = 0x9
	// Bit mask of BNAM field.
	OTG_OTG_DOEPMSK_BNAM_Msk = 0x200
	// Bit BNAM.
	OTG_OTG_DOEPMSK_BNAM = 0x200
	// Position of BERRM field.
	OTG_OTG_DOEPMSK_BERRM_Pos = 0xc
	// Bit mask of BERRM field.
	OTG_OTG_DOEPMSK_BERRM_Msk = 0x1000
	// Bit BERRM.
	OTG_OTG_DOEPMSK_BERRM = 0x1000
	// Position of NAKMSK field.
	OTG_OTG_DOEPMSK_NAKMSK_Pos = 0xd
	// Bit mask of NAKMSK field.
	OTG_OTG_DOEPMSK_NAKMSK_Msk = 0x2000
	// Bit NAKMSK.
	OTG_OTG_DOEPMSK_NAKMSK = 0x2000
	// Position of NYETMSK field.
	OTG_OTG_DOEPMSK_NYETMSK_Pos = 0xe
	// Bit mask of NYETMSK field.
	OTG_OTG_DOEPMSK_NYETMSK_Msk = 0x4000
	// Bit NYETMSK.
	OTG_OTG_DOEPMSK_NYETMSK = 0x4000

	// OTG_DAINT: When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).
	// Position of IEPINT field.
	OTG_OTG_DAINT_IEPINT_Pos = 0x0
	// Bit mask of IEPINT field.
	OTG_OTG_DAINT_IEPINT_Msk = 0xffff
	// Position of OEPINT field.
	OTG_OTG_DAINT_OEPINT_Pos = 0x10
	// Bit mask of OEPINT field.
	OTG_OTG_DAINT_OEPINT_Msk = 0xffff0000

	// OTG_DAINTMSK: The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set.
	// Position of IEPM field.
	OTG_OTG_DAINTMSK_IEPM_Pos = 0x0
	// Bit mask of IEPM field.
	OTG_OTG_DAINTMSK_IEPM_Msk = 0xffff
	// Position of OEPM field.
	OTG_OTG_DAINTMSK_OEPM_Pos = 0x10
	// Bit mask of OEPM field.
	OTG_OTG_DAINTMSK_OEPM_Msk = 0xffff0000

	// OTG_DVBUSDIS: This register specifies the VBUS discharge time after VBUS pulsing during SRP.
	// Position of VBUSDT field.
	OTG_OTG_DVBUSDIS_VBUSDT_Pos = 0x0
	// Bit mask of VBUSDT field.
	OTG_OTG_DVBUSDIS_VBUSDT_Msk = 0xffff

	// OTG_DVBUSPULSE: This register specifies the VBUS pulsing time during SRP.
	// Position of DVBUSP field.
	OTG_OTG_DVBUSPULSE_DVBUSP_Pos = 0x0
	// Bit mask of DVBUSP field.
	OTG_OTG_DVBUSPULSE_DVBUSP_Msk = 0xffff

	// OTG_DTHRCTL: OTG device threshold control register
	// Position of NONISOTHREN field.
	OTG_OTG_DTHRCTL_NONISOTHREN_Pos = 0x0
	// Bit mask of NONISOTHREN field.
	OTG_OTG_DTHRCTL_NONISOTHREN_Msk = 0x1
	// Bit NONISOTHREN.
	OTG_OTG_DTHRCTL_NONISOTHREN = 0x1
	// Position of ISOTHREN field.
	OTG_OTG_DTHRCTL_ISOTHREN_Pos = 0x1
	// Bit mask of ISOTHREN field.
	OTG_OTG_DTHRCTL_ISOTHREN_Msk = 0x2
	// Bit ISOTHREN.
	OTG_OTG_DTHRCTL_ISOTHREN = 0x2
	// Position of TXTHRLEN field.
	OTG_OTG_DTHRCTL_TXTHRLEN_Pos = 0x2
	// Bit mask of TXTHRLEN field.
	OTG_OTG_DTHRCTL_TXTHRLEN_Msk = 0x7fc
	// Position of RXTHREN field.
	OTG_OTG_DTHRCTL_RXTHREN_Pos = 0x10
	// Bit mask of RXTHREN field.
	OTG_OTG_DTHRCTL_RXTHREN_Msk = 0x10000
	// Bit RXTHREN.
	OTG_OTG_DTHRCTL_RXTHREN = 0x10000
	// Position of RXTHRLEN field.
	OTG_OTG_DTHRCTL_RXTHRLEN_Pos = 0x11
	// Bit mask of RXTHRLEN field.
	OTG_OTG_DTHRCTL_RXTHRLEN_Msk = 0x3fe0000
	// Position of ARPEN field.
	OTG_OTG_DTHRCTL_ARPEN_Pos = 0x1b
	// Bit mask of ARPEN field.
	OTG_OTG_DTHRCTL_ARPEN_Msk = 0x8000000
	// Bit ARPEN.
	OTG_OTG_DTHRCTL_ARPEN = 0x8000000

	// OTG_DIEPEMPMSK: This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx).
	// Position of INEPTXFEM field.
	OTG_OTG_DIEPEMPMSK_INEPTXFEM_Pos = 0x0
	// Bit mask of INEPTXFEM field.
	OTG_OTG_DIEPEMPMSK_INEPTXFEM_Msk = 0xffff

	// OTG_DEACHINT: OTG device each endpoint interrupt register
	// Position of IEP1INT field.
	OTG_OTG_DEACHINT_IEP1INT_Pos = 0x1
	// Bit mask of IEP1INT field.
	OTG_OTG_DEACHINT_IEP1INT_Msk = 0x2
	// Bit IEP1INT.
	OTG_OTG_DEACHINT_IEP1INT = 0x2
	// Position of OEP1INT field.
	OTG_OTG_DEACHINT_OEP1INT_Pos = 0x11
	// Bit mask of OEP1INT field.
	OTG_OTG_DEACHINT_OEP1INT_Msk = 0x20000
	// Bit OEP1INT.
	OTG_OTG_DEACHINT_OEP1INT = 0x20000

	// OTG_DEACHINTMSK: There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.
	// Position of IEP1INTM field.
	OTG_OTG_DEACHINTMSK_IEP1INTM_Pos = 0x1
	// Bit mask of IEP1INTM field.
	OTG_OTG_DEACHINTMSK_IEP1INTM_Msk = 0x2
	// Bit IEP1INTM.
	OTG_OTG_DEACHINTMSK_IEP1INTM = 0x2
	// Position of OEP1INTM field.
	OTG_OTG_DEACHINTMSK_OEP1INTM_Pos = 0x11
	// Bit mask of OEP1INTM field.
	OTG_OTG_DEACHINTMSK_OEP1INTM_Msk = 0x20000
	// Bit OEP1INTM.
	OTG_OTG_DEACHINTMSK_OEP1INTM = 0x20000

	// OTG_HS_DIEPEACHMSK1: This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
	// Position of XFRCM field.
	OTG_OTG_HS_DIEPEACHMSK1_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HS_DIEPEACHMSK1_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HS_DIEPEACHMSK1_XFRCM = 0x1
	// Position of EPDM field.
	OTG_OTG_HS_DIEPEACHMSK1_EPDM_Pos = 0x1
	// Bit mask of EPDM field.
	OTG_OTG_HS_DIEPEACHMSK1_EPDM_Msk = 0x2
	// Bit EPDM.
	OTG_OTG_HS_DIEPEACHMSK1_EPDM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HS_DIEPEACHMSK1_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HS_DIEPEACHMSK1_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HS_DIEPEACHMSK1_AHBERRM = 0x4
	// Position of TOM field.
	OTG_OTG_HS_DIEPEACHMSK1_TOM_Pos = 0x3
	// Bit mask of TOM field.
	OTG_OTG_HS_DIEPEACHMSK1_TOM_Msk = 0x8
	// Bit TOM.
	OTG_OTG_HS_DIEPEACHMSK1_TOM = 0x8
	// Position of ITTXFEMSK field.
	OTG_OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Pos = 0x4
	// Bit mask of ITTXFEMSK field.
	OTG_OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Msk = 0x10
	// Bit ITTXFEMSK.
	OTG_OTG_HS_DIEPEACHMSK1_ITTXFEMSK = 0x10
	// Position of INEPNEM field.
	OTG_OTG_HS_DIEPEACHMSK1_INEPNEM_Pos = 0x6
	// Bit mask of INEPNEM field.
	OTG_OTG_HS_DIEPEACHMSK1_INEPNEM_Msk = 0x40
	// Bit INEPNEM.
	OTG_OTG_HS_DIEPEACHMSK1_INEPNEM = 0x40
	// Position of TXFURM field.
	OTG_OTG_HS_DIEPEACHMSK1_TXFURM_Pos = 0x8
	// Bit mask of TXFURM field.
	OTG_OTG_HS_DIEPEACHMSK1_TXFURM_Msk = 0x100
	// Bit TXFURM.
	OTG_OTG_HS_DIEPEACHMSK1_TXFURM = 0x100
	// Position of BNAM field.
	OTG_OTG_HS_DIEPEACHMSK1_BNAM_Pos = 0x9
	// Bit mask of BNAM field.
	OTG_OTG_HS_DIEPEACHMSK1_BNAM_Msk = 0x200
	// Bit BNAM.
	OTG_OTG_HS_DIEPEACHMSK1_BNAM = 0x200
	// Position of NAKM field.
	OTG_OTG_HS_DIEPEACHMSK1_NAKM_Pos = 0xd
	// Bit mask of NAKM field.
	OTG_OTG_HS_DIEPEACHMSK1_NAKM_Msk = 0x2000
	// Bit NAKM.
	OTG_OTG_HS_DIEPEACHMSK1_NAKM = 0x2000

	// OTG_HS_DOEPEACHMSK1: This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
	// Position of XFRCM field.
	OTG_OTG_HS_DOEPEACHMSK1_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_OTG_HS_DOEPEACHMSK1_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_OTG_HS_DOEPEACHMSK1_XFRCM = 0x1
	// Position of EPDM field.
	OTG_OTG_HS_DOEPEACHMSK1_EPDM_Pos = 0x1
	// Bit mask of EPDM field.
	OTG_OTG_HS_DOEPEACHMSK1_EPDM_Msk = 0x2
	// Bit EPDM.
	OTG_OTG_HS_DOEPEACHMSK1_EPDM = 0x2
	// Position of AHBERRM field.
	OTG_OTG_HS_DOEPEACHMSK1_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_OTG_HS_DOEPEACHMSK1_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_OTG_HS_DOEPEACHMSK1_AHBERRM = 0x4
	// Position of STUPM field.
	OTG_OTG_HS_DOEPEACHMSK1_STUPM_Pos = 0x3
	// Bit mask of STUPM field.
	OTG_OTG_HS_DOEPEACHMSK1_STUPM_Msk = 0x8
	// Bit STUPM.
	OTG_OTG_HS_DOEPEACHMSK1_STUPM = 0x8
	// Position of OTEPDM field.
	OTG_OTG_HS_DOEPEACHMSK1_OTEPDM_Pos = 0x4
	// Bit mask of OTEPDM field.
	OTG_OTG_HS_DOEPEACHMSK1_OTEPDM_Msk = 0x10
	// Bit OTEPDM.
	OTG_OTG_HS_DOEPEACHMSK1_OTEPDM = 0x10
	// Position of B2BSTUPM field.
	OTG_OTG_HS_DOEPEACHMSK1_B2BSTUPM_Pos = 0x6
	// Bit mask of B2BSTUPM field.
	OTG_OTG_HS_DOEPEACHMSK1_B2BSTUPM_Msk = 0x40
	// Bit B2BSTUPM.
	OTG_OTG_HS_DOEPEACHMSK1_B2BSTUPM = 0x40
	// Position of OUTPKTERRM field.
	OTG_OTG_HS_DOEPEACHMSK1_OUTPKTERRM_Pos = 0x8
	// Bit mask of OUTPKTERRM field.
	OTG_OTG_HS_DOEPEACHMSK1_OUTPKTERRM_Msk = 0x100
	// Bit OUTPKTERRM.
	OTG_OTG_HS_DOEPEACHMSK1_OUTPKTERRM = 0x100
	// Position of BNAM field.
	OTG_OTG_HS_DOEPEACHMSK1_BNAM_Pos = 0x9
	// Bit mask of BNAM field.
	OTG_OTG_HS_DOEPEACHMSK1_BNAM_Msk = 0x200
	// Bit BNAM.
	OTG_OTG_HS_DOEPEACHMSK1_BNAM = 0x200
	// Position of BERRM field.
	OTG_OTG_HS_DOEPEACHMSK1_BERRM_Pos = 0xc
	// Bit mask of BERRM field.
	OTG_OTG_HS_DOEPEACHMSK1_BERRM_Msk = 0x1000
	// Bit BERRM.
	OTG_OTG_HS_DOEPEACHMSK1_BERRM = 0x1000
	// Position of NAKMSK field.
	OTG_OTG_HS_DOEPEACHMSK1_NAKMSK_Pos = 0xd
	// Bit mask of NAKMSK field.
	OTG_OTG_HS_DOEPEACHMSK1_NAKMSK_Msk = 0x2000
	// Bit NAKMSK.
	OTG_OTG_HS_DOEPEACHMSK1_NAKMSK = 0x2000
	// Position of NYETMSK field.
	OTG_OTG_HS_DOEPEACHMSK1_NYETMSK_Pos = 0xe
	// Bit mask of NYETMSK field.
	OTG_OTG_HS_DOEPEACHMSK1_NYETMSK_Msk = 0x4000
	// Bit NYETMSK.
	OTG_OTG_HS_DOEPEACHMSK1_NYETMSK = 0x4000

	// OTG_DIEPCTL0: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL0_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL0_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL0_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL0_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL0_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL0_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL0_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL0_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL0_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL0_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL0_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL0_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL0_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL0_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL0_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL0_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL0_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL0_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL0_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL0_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL0_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL0_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL0_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL0_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL0_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL0_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL0_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL0_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL0_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL0_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL0_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL0_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL0_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL0_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL0_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL0_EPENA = 0x80000000

	// OTG_DIEPINT0: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT0_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT0_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT0_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT0_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT0_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT0_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT0_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT0_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT0_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT0_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT0_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT0_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT0_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT0_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT0_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT0_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT0_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT0_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT0_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT0_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT0_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT0_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT0_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT0_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT0_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT0_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT0_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT0_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT0_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT0_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT0_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT0_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT0_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT0_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT0_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT0_NAK = 0x2000

	// OTG_DIEPTSIZ0: The application must modify this register before enabling endpoint 0.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ0_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ0_XFRSIZ_Msk = 0x7f
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ0_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ0_PKTCNT_Msk = 0x180000

	// OTG_DIEPDMA0: OTG device IN endpoint 0 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA0_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA0_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS0: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS0_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS0_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL1: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL1_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL1_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL1_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL1_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL1_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL1_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL1_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL1_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL1_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL1_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL1_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL1_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL1_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL1_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL1_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL1_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL1_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL1_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL1_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL1_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL1_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL1_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL1_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL1_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL1_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL1_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL1_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL1_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL1_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL1_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL1_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL1_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL1_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL1_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL1_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL1_EPENA = 0x80000000

	// OTG_DIEPINT1: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT1_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT1_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT1_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT1_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT1_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT1_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT1_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT1_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT1_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT1_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT1_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT1_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT1_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT1_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT1_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT1_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT1_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT1_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT1_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT1_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT1_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT1_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT1_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT1_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT1_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT1_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT1_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT1_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT1_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT1_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT1_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT1_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT1_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT1_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT1_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT1_NAK = 0x2000

	// OTG_DIEPTSIZ1: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ1_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ1_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ1_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ1_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ1_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ1_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA1: OTG device IN endpoint 1 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA1_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA1_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS1: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS1_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS1_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL2: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL2_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL2_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL2_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL2_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL2_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL2_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL2_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL2_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL2_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL2_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL2_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL2_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL2_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL2_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL2_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL2_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL2_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL2_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL2_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL2_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL2_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL2_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL2_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL2_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL2_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL2_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL2_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL2_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL2_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL2_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL2_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL2_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL2_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL2_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL2_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL2_EPENA = 0x80000000

	// OTG_DIEPINT2: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT2_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT2_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT2_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT2_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT2_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT2_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT2_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT2_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT2_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT2_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT2_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT2_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT2_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT2_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT2_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT2_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT2_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT2_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT2_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT2_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT2_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT2_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT2_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT2_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT2_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT2_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT2_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT2_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT2_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT2_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT2_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT2_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT2_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT2_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT2_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT2_NAK = 0x2000

	// OTG_DIEPTSIZ2: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ2_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ2_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ2_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ2_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ2_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ2_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA2: OTG device IN endpoint 2 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA2_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA2_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS2: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS2_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS2_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL3: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL3_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL3_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL3_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL3_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL3_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL3_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL3_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL3_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL3_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL3_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL3_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL3_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL3_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL3_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL3_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL3_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL3_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL3_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL3_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL3_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL3_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL3_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL3_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL3_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL3_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL3_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL3_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL3_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL3_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL3_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL3_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL3_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL3_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL3_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL3_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL3_EPENA = 0x80000000

	// OTG_DIEPINT3: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT3_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT3_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT3_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT3_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT3_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT3_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT3_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT3_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT3_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT3_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT3_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT3_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT3_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT3_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT3_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT3_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT3_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT3_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT3_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT3_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT3_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT3_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT3_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT3_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT3_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT3_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT3_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT3_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT3_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT3_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT3_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT3_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT3_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT3_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT3_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT3_NAK = 0x2000

	// OTG_DIEPTSIZ3: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ3_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ3_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ3_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ3_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ3_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ3_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA3: OTG device IN endpoint 3 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA3_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA3_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS3: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS3_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS3_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL4: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL4_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL4_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL4_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL4_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL4_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL4_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL4_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL4_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL4_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL4_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL4_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL4_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL4_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL4_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL4_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL4_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL4_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL4_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL4_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL4_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL4_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL4_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL4_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL4_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL4_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL4_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL4_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL4_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL4_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL4_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL4_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL4_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL4_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL4_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL4_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL4_EPENA = 0x80000000

	// OTG_DIEPINT4: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT4_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT4_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT4_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT4_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT4_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT4_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT4_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT4_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT4_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT4_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT4_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT4_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT4_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT4_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT4_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT4_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT4_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT4_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT4_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT4_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT4_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT4_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT4_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT4_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT4_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT4_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT4_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT4_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT4_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT4_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT4_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT4_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT4_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT4_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT4_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT4_NAK = 0x2000

	// OTG_DIEPTSIZ4: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ4_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ4_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ4_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ4_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ4_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ4_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA4: OTG device IN endpoint 4 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA4_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA4_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS4: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS4_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS4_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL5: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL5_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL5_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL5_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL5_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL5_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL5_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL5_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL5_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL5_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL5_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL5_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL5_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL5_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL5_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL5_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL5_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL5_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL5_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL5_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL5_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL5_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL5_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL5_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL5_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL5_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL5_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL5_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL5_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL5_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL5_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL5_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL5_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL5_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL5_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL5_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL5_EPENA = 0x80000000

	// OTG_DIEPINT5: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT5_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT5_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT5_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT5_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT5_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT5_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT5_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT5_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT5_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT5_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT5_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT5_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT5_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT5_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT5_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT5_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT5_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT5_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT5_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT5_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT5_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT5_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT5_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT5_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT5_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT5_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT5_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT5_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT5_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT5_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT5_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT5_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT5_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT5_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT5_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT5_NAK = 0x2000

	// OTG_DIEPTSIZ5: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ5_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ5_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ5_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ5_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ5_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ5_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA5: OTG device IN endpoint 5 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA5_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA5_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS5: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS5_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS5_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL6: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL6_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL6_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL6_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL6_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL6_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL6_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL6_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL6_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL6_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL6_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL6_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL6_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL6_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL6_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL6_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL6_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL6_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL6_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL6_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL6_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL6_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL6_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL6_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL6_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL6_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL6_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL6_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL6_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL6_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL6_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL6_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL6_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL6_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL6_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL6_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL6_EPENA = 0x80000000

	// OTG_DIEPINT6: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT6_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT6_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT6_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT6_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT6_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT6_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT6_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT6_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT6_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT6_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT6_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT6_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT6_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT6_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT6_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT6_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT6_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT6_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT6_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT6_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT6_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT6_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT6_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT6_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT6_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT6_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT6_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT6_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT6_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT6_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT6_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT6_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT6_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT6_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT6_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT6_NAK = 0x2000

	// OTG_DIEPTSIZ6: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ6_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ6_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ6_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ6_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ6_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ6_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA6: OTG device IN endpoint 6 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA6_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA6_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS6: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS6_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS6_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL7: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL7_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL7_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL7_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL7_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL7_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL7_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL7_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL7_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL7_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL7_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL7_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL7_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL7_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL7_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL7_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL7_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL7_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL7_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL7_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL7_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL7_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL7_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL7_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL7_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL7_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL7_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL7_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL7_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL7_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL7_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL7_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL7_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL7_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL7_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL7_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL7_EPENA = 0x80000000

	// OTG_DIEPINT7: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT7_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT7_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT7_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT7_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT7_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT7_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT7_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT7_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT7_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT7_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT7_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT7_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT7_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT7_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT7_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT7_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT7_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT7_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT7_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT7_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT7_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT7_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT7_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT7_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT7_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT7_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT7_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT7_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT7_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT7_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT7_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT7_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT7_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT7_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT7_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT7_NAK = 0x2000

	// OTG_DIEPTSIZ7: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ7_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ7_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ7_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ7_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ7_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ7_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA7: OTG device IN endpoint 7 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA7_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA7_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS7: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS7_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS7_INEPTFSAV_Msk = 0xffff

	// OTG_DIEPCTL8: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DIEPCTL8_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DIEPCTL8_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DIEPCTL8_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DIEPCTL8_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DIEPCTL8_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DIEPCTL8_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DIEPCTL8_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DIEPCTL8_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DIEPCTL8_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DIEPCTL8_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DIEPCTL8_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DIEPCTL8_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DIEPCTL8_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_OTG_DIEPCTL8_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DIEPCTL8_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DIEPCTL8_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_OTG_DIEPCTL8_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_OTG_DIEPCTL8_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_OTG_DIEPCTL8_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DIEPCTL8_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DIEPCTL8_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DIEPCTL8_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DIEPCTL8_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DIEPCTL8_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL8_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DIEPCTL8_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DIEPCTL8_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_OTG_DIEPCTL8_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_OTG_DIEPCTL8_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_OTG_DIEPCTL8_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DIEPCTL8_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DIEPCTL8_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DIEPCTL8_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DIEPCTL8_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DIEPCTL8_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DIEPCTL8_EPENA = 0x80000000

	// OTG_DIEPINT8: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DIEPINT8_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DIEPINT8_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DIEPINT8_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DIEPINT8_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DIEPINT8_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DIEPINT8_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DIEPINT8_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DIEPINT8_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DIEPINT8_AHBERR = 0x4
	// Position of TOC field.
	OTG_OTG_DIEPINT8_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_OTG_DIEPINT8_TOC_Msk = 0x8
	// Bit TOC.
	OTG_OTG_DIEPINT8_TOC = 0x8
	// Position of ITTXFE field.
	OTG_OTG_DIEPINT8_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_OTG_DIEPINT8_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_OTG_DIEPINT8_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_OTG_DIEPINT8_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_OTG_DIEPINT8_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_OTG_DIEPINT8_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_OTG_DIEPINT8_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_OTG_DIEPINT8_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_OTG_DIEPINT8_INEPNE = 0x40
	// Position of TXFE field.
	OTG_OTG_DIEPINT8_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_OTG_DIEPINT8_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_OTG_DIEPINT8_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_OTG_DIEPINT8_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_OTG_DIEPINT8_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_OTG_DIEPINT8_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_OTG_DIEPINT8_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DIEPINT8_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DIEPINT8_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_OTG_DIEPINT8_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_OTG_DIEPINT8_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_OTG_DIEPINT8_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_OTG_DIEPINT8_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DIEPINT8_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DIEPINT8_NAK = 0x2000

	// OTG_DIEPTSIZ8: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DIEPTSIZ8_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DIEPTSIZ8_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DIEPTSIZ8_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DIEPTSIZ8_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_OTG_DIEPTSIZ8_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_OTG_DIEPTSIZ8_MCNT_Msk = 0x60000000

	// OTG_DIEPDMA8: OTG device IN endpoint 8 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DIEPDMA8_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DIEPDMA8_DMAADDR_Msk = 0xffffffff

	// OTG_DTXFSTS8: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_OTG_DTXFSTS8_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_OTG_DTXFSTS8_INEPTFSAV_Msk = 0xffff

	// OTG_DOEPCTL0: This section describes the OTG_DOEPCTL0 register.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL0_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL0_MPSIZ_Msk = 0x3
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL0_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL0_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL0_USBAEP = 0x8000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL0_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL0_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL0_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL0_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL0_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL0_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL0_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL0_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL0_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL0_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL0_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL0_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL0_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL0_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL0_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL0_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL0_SNAK = 0x8000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL0_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL0_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL0_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL0_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL0_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL0_EPENA = 0x80000000

	// OTG_DOEPINT0: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT0_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT0_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT0_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT0_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT0_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT0_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT0_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT0_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT0_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT0_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT0_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT0_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT0_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT0_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT0_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT0_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT0_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT0_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT0_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT0_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT0_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT0_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT0_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT0_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT0_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT0_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT0_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT0_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT0_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT0_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT0_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT0_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT0_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT0_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT0_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT0_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT0_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT0_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT0_STPKTRX = 0x8000

	// OTG_DOEPTSIZ0: The application must modify this register before enabling endpoint 0.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ0_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ0_XFRSIZ_Msk = 0x7f
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ0_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ0_PKTCNT_Msk = 0x80000
	// Bit PKTCNT.
	OTG_OTG_DOEPTSIZ0_PKTCNT = 0x80000
	// Position of STUPCNT field.
	OTG_OTG_DOEPTSIZ0_STUPCNT_Pos = 0x1d
	// Bit mask of STUPCNT field.
	OTG_OTG_DOEPTSIZ0_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA0: OTG device OUT endpoint 0 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA0_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA0_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL1: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL1_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL1_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL1_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL1_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL1_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL1_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL1_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL1_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL1_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL1_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL1_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL1_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL1_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL1_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL1_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL1_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL1_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL1_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL1_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL1_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL1_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL1_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL1_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL1_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL1_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL1_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL1_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL1_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL1_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL1_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL1_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL1_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL1_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL1_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL1_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL1_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL1_EPENA = 0x80000000

	// OTG_DOEPINT1: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT1_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT1_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT1_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT1_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT1_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT1_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT1_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT1_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT1_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT1_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT1_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT1_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT1_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT1_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT1_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT1_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT1_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT1_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT1_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT1_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT1_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT1_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT1_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT1_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT1_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT1_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT1_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT1_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT1_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT1_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT1_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT1_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT1_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT1_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT1_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT1_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT1_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT1_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT1_STPKTRX = 0x8000

	// OTG_DOEPTSIZ1: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ1_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ1_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ1_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ1_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ1_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ1_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA1: OTG device OUT endpoint 1 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA1_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA1_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL2: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL2_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL2_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL2_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL2_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL2_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL2_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL2_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL2_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL2_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL2_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL2_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL2_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL2_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL2_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL2_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL2_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL2_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL2_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL2_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL2_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL2_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL2_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL2_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL2_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL2_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL2_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL2_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL2_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL2_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL2_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL2_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL2_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL2_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL2_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL2_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL2_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL2_EPENA = 0x80000000

	// OTG_DOEPINT2: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT2_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT2_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT2_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT2_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT2_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT2_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT2_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT2_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT2_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT2_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT2_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT2_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT2_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT2_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT2_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT2_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT2_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT2_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT2_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT2_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT2_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT2_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT2_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT2_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT2_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT2_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT2_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT2_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT2_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT2_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT2_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT2_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT2_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT2_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT2_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT2_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT2_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT2_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT2_STPKTRX = 0x8000

	// OTG_DOEPTSIZ2: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ2_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ2_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ2_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ2_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ2_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ2_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA2: OTG device OUT endpoint 2 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA2_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA2_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL3: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL3_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL3_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL3_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL3_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL3_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL3_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL3_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL3_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL3_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL3_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL3_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL3_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL3_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL3_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL3_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL3_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL3_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL3_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL3_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL3_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL3_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL3_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL3_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL3_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL3_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL3_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL3_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL3_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL3_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL3_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL3_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL3_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL3_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL3_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL3_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL3_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL3_EPENA = 0x80000000

	// OTG_DOEPINT3: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT3_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT3_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT3_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT3_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT3_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT3_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT3_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT3_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT3_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT3_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT3_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT3_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT3_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT3_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT3_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT3_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT3_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT3_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT3_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT3_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT3_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT3_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT3_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT3_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT3_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT3_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT3_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT3_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT3_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT3_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT3_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT3_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT3_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT3_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT3_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT3_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT3_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT3_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT3_STPKTRX = 0x8000

	// OTG_DOEPTSIZ3: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ3_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ3_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ3_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ3_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ3_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ3_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA3: OTG device OUT endpoint 3 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA3_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA3_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL4: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL4_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL4_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL4_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL4_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL4_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL4_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL4_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL4_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL4_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL4_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL4_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL4_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL4_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL4_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL4_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL4_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL4_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL4_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL4_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL4_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL4_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL4_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL4_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL4_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL4_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL4_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL4_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL4_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL4_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL4_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL4_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL4_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL4_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL4_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL4_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL4_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL4_EPENA = 0x80000000

	// OTG_DOEPINT4: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT4_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT4_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT4_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT4_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT4_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT4_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT4_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT4_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT4_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT4_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT4_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT4_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT4_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT4_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT4_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT4_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT4_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT4_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT4_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT4_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT4_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT4_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT4_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT4_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT4_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT4_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT4_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT4_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT4_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT4_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT4_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT4_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT4_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT4_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT4_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT4_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT4_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT4_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT4_STPKTRX = 0x8000

	// OTG_DOEPTSIZ4: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ4_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ4_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ4_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ4_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ4_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ4_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA4: OTG device OUT endpoint 4 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA4_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA4_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL5: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL5_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL5_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL5_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL5_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL5_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL5_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL5_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL5_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL5_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL5_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL5_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL5_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL5_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL5_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL5_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL5_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL5_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL5_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL5_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL5_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL5_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL5_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL5_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL5_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL5_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL5_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL5_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL5_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL5_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL5_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL5_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL5_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL5_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL5_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL5_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL5_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL5_EPENA = 0x80000000

	// OTG_DOEPINT5: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT5_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT5_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT5_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT5_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT5_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT5_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT5_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT5_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT5_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT5_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT5_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT5_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT5_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT5_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT5_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT5_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT5_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT5_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT5_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT5_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT5_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT5_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT5_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT5_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT5_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT5_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT5_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT5_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT5_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT5_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT5_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT5_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT5_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT5_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT5_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT5_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT5_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT5_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT5_STPKTRX = 0x8000

	// OTG_DOEPTSIZ5: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ5_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ5_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ5_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ5_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ5_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ5_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA5: OTG device OUT endpoint 5 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA5_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA5_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL6: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL6_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL6_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL6_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL6_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL6_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL6_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL6_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL6_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL6_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL6_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL6_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL6_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL6_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL6_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL6_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL6_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL6_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL6_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL6_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL6_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL6_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL6_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL6_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL6_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL6_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL6_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL6_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL6_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL6_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL6_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL6_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL6_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL6_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL6_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL6_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL6_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL6_EPENA = 0x80000000

	// OTG_DOEPINT6: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT6_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT6_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT6_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT6_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT6_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT6_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT6_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT6_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT6_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT6_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT6_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT6_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT6_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT6_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT6_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT6_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT6_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT6_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT6_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT6_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT6_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT6_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT6_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT6_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT6_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT6_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT6_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT6_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT6_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT6_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT6_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT6_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT6_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT6_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT6_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT6_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT6_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT6_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT6_STPKTRX = 0x8000

	// OTG_DOEPTSIZ6: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ6_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ6_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ6_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ6_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ6_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ6_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA6: OTG device OUT endpoint 6 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA6_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA6_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL7: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL7_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL7_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL7_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL7_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL7_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL7_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL7_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL7_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL7_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL7_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL7_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL7_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL7_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL7_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL7_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL7_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL7_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL7_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL7_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL7_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL7_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL7_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL7_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL7_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL7_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL7_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL7_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL7_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL7_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL7_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL7_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL7_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL7_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL7_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL7_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL7_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL7_EPENA = 0x80000000

	// OTG_DOEPINT7: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT7_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT7_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT7_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT7_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT7_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT7_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT7_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT7_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT7_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT7_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT7_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT7_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT7_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT7_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT7_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT7_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT7_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT7_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT7_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT7_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT7_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT7_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT7_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT7_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT7_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT7_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT7_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT7_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT7_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT7_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT7_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT7_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT7_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT7_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT7_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT7_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT7_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT7_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT7_STPKTRX = 0x8000

	// OTG_DOEPTSIZ7: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ7_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ7_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ7_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ7_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ7_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ7_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA7: OTG device OUT endpoint 7 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA7_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA7_DMAADDR_Msk = 0xffffffff

	// OTG_DOEPCTL8: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_OTG_DOEPCTL8_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_OTG_DOEPCTL8_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_OTG_DOEPCTL8_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_OTG_DOEPCTL8_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_OTG_DOEPCTL8_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_OTG_DOEPCTL8_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_OTG_DOEPCTL8_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_OTG_DOEPCTL8_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_OTG_DOEPCTL8_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_OTG_DOEPCTL8_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_OTG_DOEPCTL8_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_OTG_DOEPCTL8_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_OTG_DOEPCTL8_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_OTG_DOEPCTL8_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_OTG_DOEPCTL8_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_OTG_DOEPCTL8_SNPM = 0x100000
	// Position of STALL field.
	OTG_OTG_DOEPCTL8_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_OTG_DOEPCTL8_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_OTG_DOEPCTL8_STALL = 0x200000
	// Position of CNAK field.
	OTG_OTG_DOEPCTL8_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_OTG_DOEPCTL8_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_OTG_DOEPCTL8_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_OTG_DOEPCTL8_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_OTG_DOEPCTL8_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_OTG_DOEPCTL8_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL8_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_OTG_DOEPCTL8_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_OTG_DOEPCTL8_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL8_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_OTG_DOEPCTL8_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_OTG_DOEPCTL8_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_OTG_DOEPCTL8_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_OTG_DOEPCTL8_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_OTG_DOEPCTL8_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_OTG_DOEPCTL8_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_OTG_DOEPCTL8_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_OTG_DOEPCTL8_EPENA = 0x80000000

	// OTG_DOEPINT8: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
	// Position of XFRC field.
	OTG_OTG_DOEPINT8_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_OTG_DOEPINT8_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_OTG_DOEPINT8_XFRC = 0x1
	// Position of EPDISD field.
	OTG_OTG_DOEPINT8_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_OTG_DOEPINT8_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_OTG_DOEPINT8_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_OTG_DOEPINT8_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_OTG_DOEPINT8_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_OTG_DOEPINT8_AHBERR = 0x4
	// Position of STUP field.
	OTG_OTG_DOEPINT8_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_OTG_DOEPINT8_STUP_Msk = 0x8
	// Bit STUP.
	OTG_OTG_DOEPINT8_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_OTG_DOEPINT8_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_OTG_DOEPINT8_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_OTG_DOEPINT8_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_OTG_DOEPINT8_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_OTG_DOEPINT8_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_OTG_DOEPINT8_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_OTG_DOEPINT8_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_OTG_DOEPINT8_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_OTG_DOEPINT8_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_OTG_DOEPINT8_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_OTG_DOEPINT8_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_OTG_DOEPINT8_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_OTG_DOEPINT8_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_OTG_DOEPINT8_BNA_Msk = 0x200
	// Bit BNA.
	OTG_OTG_DOEPINT8_BNA = 0x200
	// Position of BERR field.
	OTG_OTG_DOEPINT8_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_OTG_DOEPINT8_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_OTG_DOEPINT8_BERR = 0x1000
	// Position of NAK field.
	OTG_OTG_DOEPINT8_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_OTG_DOEPINT8_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_OTG_DOEPINT8_NAK = 0x2000
	// Position of NYET field.
	OTG_OTG_DOEPINT8_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_OTG_DOEPINT8_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_OTG_DOEPINT8_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_OTG_DOEPINT8_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_OTG_DOEPINT8_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_OTG_DOEPINT8_STPKTRX = 0x8000

	// OTG_DOEPTSIZ8: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_OTG_DOEPTSIZ8_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_OTG_DOEPTSIZ8_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_OTG_DOEPTSIZ8_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_OTG_DOEPTSIZ8_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ8_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_OTG_DOEPTSIZ8_RXDPID_STUPCNT_Msk = 0x60000000

	// OTG_DOEPDMA8: OTG device OUT endpoint 8 DMA address register
	// Position of DMAADDR field.
	OTG_OTG_DOEPDMA8_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_OTG_DOEPDMA8_DMAADDR_Msk = 0xffffffff

	// OTG_PCGCCTL: This register is available in host and device modes.
	// Position of STPPCLK field.
	OTG_OTG_PCGCCTL_STPPCLK_Pos = 0x0
	// Bit mask of STPPCLK field.
	OTG_OTG_PCGCCTL_STPPCLK_Msk = 0x1
	// Bit STPPCLK.
	OTG_OTG_PCGCCTL_STPPCLK = 0x1
	// Position of GATEHCLK field.
	OTG_OTG_PCGCCTL_GATEHCLK_Pos = 0x1
	// Bit mask of GATEHCLK field.
	OTG_OTG_PCGCCTL_GATEHCLK_Msk = 0x2
	// Bit GATEHCLK.
	OTG_OTG_PCGCCTL_GATEHCLK = 0x2
	// Position of PHYSUSP field.
	OTG_OTG_PCGCCTL_PHYSUSP_Pos = 0x4
	// Bit mask of PHYSUSP field.
	OTG_OTG_PCGCCTL_PHYSUSP_Msk = 0x10
	// Bit PHYSUSP.
	OTG_OTG_PCGCCTL_PHYSUSP = 0x10
	// Position of ENL1GTG field.
	OTG_OTG_PCGCCTL_ENL1GTG_Pos = 0x5
	// Bit mask of ENL1GTG field.
	OTG_OTG_PCGCCTL_ENL1GTG_Msk = 0x20
	// Bit ENL1GTG.
	OTG_OTG_PCGCCTL_ENL1GTG = 0x20
	// Position of PHYSLEEP field.
	OTG_OTG_PCGCCTL_PHYSLEEP_Pos = 0x6
	// Bit mask of PHYSLEEP field.
	OTG_OTG_PCGCCTL_PHYSLEEP_Msk = 0x40
	// Bit PHYSLEEP.
	OTG_OTG_PCGCCTL_PHYSLEEP = 0x40
	// Position of SUSP field.
	OTG_OTG_PCGCCTL_SUSP_Pos = 0x7
	// Bit mask of SUSP field.
	OTG_OTG_PCGCCTL_SUSP_Msk = 0x80
	// Bit SUSP.
	OTG_OTG_PCGCCTL_SUSP = 0x80
)

// Bitfields for PWR: PWR
const (
	// PWR_CR1: Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value.
	// Position of LPDS field.
	PWR_PWR_CR1_LPDS_Pos = 0x0
	// Bit mask of LPDS field.
	PWR_PWR_CR1_LPDS_Msk = 0x1
	// Bit LPDS.
	PWR_PWR_CR1_LPDS = 0x1
	// Position of LPCFG field.
	PWR_PWR_CR1_LPCFG_Pos = 0x1
	// Bit mask of LPCFG field.
	PWR_PWR_CR1_LPCFG_Msk = 0x2
	// Bit LPCFG.
	PWR_PWR_CR1_LPCFG = 0x2
	// Position of LVDS field.
	PWR_PWR_CR1_LVDS_Pos = 0x2
	// Bit mask of LVDS field.
	PWR_PWR_CR1_LVDS_Msk = 0x4
	// Bit LVDS.
	PWR_PWR_CR1_LVDS = 0x4
	// Position of PVDEN field.
	PWR_PWR_CR1_PVDEN_Pos = 0x4
	// Bit mask of PVDEN field.
	PWR_PWR_CR1_PVDEN_Msk = 0x10
	// Bit PVDEN.
	PWR_PWR_CR1_PVDEN = 0x10
	// Position of PLS field.
	PWR_PWR_CR1_PLS_Pos = 0x5
	// Bit mask of PLS field.
	PWR_PWR_CR1_PLS_Msk = 0xe0
	// Position of DBP field.
	PWR_PWR_CR1_DBP_Pos = 0x8
	// Bit mask of DBP field.
	PWR_PWR_CR1_DBP_Msk = 0x100
	// Bit DBP.
	PWR_PWR_CR1_DBP = 0x100
	// Position of AVDEN field.
	PWR_PWR_CR1_AVDEN_Pos = 0x10
	// Bit mask of AVDEN field.
	PWR_PWR_CR1_AVDEN_Msk = 0x10000
	// Bit AVDEN.
	PWR_PWR_CR1_AVDEN = 0x10000
	// Position of ALS field.
	PWR_PWR_CR1_ALS_Pos = 0x11
	// Bit mask of ALS field.
	PWR_PWR_CR1_ALS_Msk = 0x60000

	// PWR_CSR1: Reset on any system reset.
	// Position of PVDO field.
	PWR_PWR_CSR1_PVDO_Pos = 0x4
	// Bit mask of PVDO field.
	PWR_PWR_CSR1_PVDO_Msk = 0x10
	// Bit PVDO.
	PWR_PWR_CSR1_PVDO = 0x10
	// Position of AVDO field.
	PWR_PWR_CSR1_AVDO_Pos = 0x10
	// Bit mask of AVDO field.
	PWR_PWR_CSR1_AVDO_Msk = 0x10000
	// Bit AVDO.
	PWR_PWR_CSR1_AVDO = 0x10000

	// PWR_CR2: Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
	// Position of BREN field.
	PWR_PWR_CR2_BREN_Pos = 0x0
	// Bit mask of BREN field.
	PWR_PWR_CR2_BREN_Msk = 0x1
	// Bit BREN.
	PWR_PWR_CR2_BREN = 0x1
	// Position of RREN field.
	PWR_PWR_CR2_RREN_Pos = 0x1
	// Bit mask of RREN field.
	PWR_PWR_CR2_RREN_Msk = 0x2
	// Bit RREN.
	PWR_PWR_CR2_RREN = 0x2
	// Position of MONEN field.
	PWR_PWR_CR2_MONEN_Pos = 0x4
	// Bit mask of MONEN field.
	PWR_PWR_CR2_MONEN_Msk = 0x10
	// Bit MONEN.
	PWR_PWR_CR2_MONEN = 0x10
	// Position of BRRDY field.
	PWR_PWR_CR2_BRRDY_Pos = 0x10
	// Bit mask of BRRDY field.
	PWR_PWR_CR2_BRRDY_Msk = 0x10000
	// Bit BRRDY.
	PWR_PWR_CR2_BRRDY = 0x10000
	// Position of RRRDY field.
	PWR_PWR_CR2_RRRDY_Pos = 0x11
	// Bit mask of RRRDY field.
	PWR_PWR_CR2_RRRDY_Msk = 0x20000
	// Bit RRRDY.
	PWR_PWR_CR2_RRRDY = 0x20000
	// Position of VBATL field.
	PWR_PWR_CR2_VBATL_Pos = 0x14
	// Bit mask of VBATL field.
	PWR_PWR_CR2_VBATL_Msk = 0x100000
	// Bit VBATL.
	PWR_PWR_CR2_VBATL = 0x100000
	// Position of VBATH field.
	PWR_PWR_CR2_VBATH_Pos = 0x15
	// Bit mask of VBATH field.
	PWR_PWR_CR2_VBATH_Msk = 0x200000
	// Bit VBATH.
	PWR_PWR_CR2_VBATH = 0x200000
	// Position of TEMPL field.
	PWR_PWR_CR2_TEMPL_Pos = 0x16
	// Bit mask of TEMPL field.
	PWR_PWR_CR2_TEMPL_Msk = 0x400000
	// Bit TEMPL.
	PWR_PWR_CR2_TEMPL = 0x400000
	// Position of TEMPH field.
	PWR_PWR_CR2_TEMPH_Pos = 0x17
	// Bit mask of TEMPH field.
	PWR_PWR_CR2_TEMPH_Msk = 0x800000
	// Bit TEMPH.
	PWR_PWR_CR2_TEMPH = 0x800000

	// PWR_CR3: Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
	// Position of VBE field.
	PWR_PWR_CR3_VBE_Pos = 0x8
	// Bit mask of VBE field.
	PWR_PWR_CR3_VBE_Msk = 0x100
	// Bit VBE.
	PWR_PWR_CR3_VBE = 0x100
	// Position of VBRS field.
	PWR_PWR_CR3_VBRS_Pos = 0x9
	// Bit mask of VBRS field.
	PWR_PWR_CR3_VBRS_Msk = 0x200
	// Bit VBRS.
	PWR_PWR_CR3_VBRS = 0x200
	// Position of DDRSREN field.
	PWR_PWR_CR3_DDRSREN_Pos = 0xa
	// Bit mask of DDRSREN field.
	PWR_PWR_CR3_DDRSREN_Msk = 0x400
	// Bit DDRSREN.
	PWR_PWR_CR3_DDRSREN = 0x400
	// Position of DDRSRDIS field.
	PWR_PWR_CR3_DDRSRDIS_Pos = 0xb
	// Bit mask of DDRSRDIS field.
	PWR_PWR_CR3_DDRSRDIS_Msk = 0x800
	// Bit DDRSRDIS.
	PWR_PWR_CR3_DDRSRDIS = 0x800
	// Position of DDRRETEN field.
	PWR_PWR_CR3_DDRRETEN_Pos = 0xc
	// Bit mask of DDRRETEN field.
	PWR_PWR_CR3_DDRRETEN_Msk = 0x1000
	// Bit DDRRETEN.
	PWR_PWR_CR3_DDRRETEN = 0x1000
	// Position of POPL field.
	PWR_PWR_CR3_POPL_Pos = 0x11
	// Bit mask of POPL field.
	PWR_PWR_CR3_POPL_Msk = 0x3e0000
	// Position of USB33DEN field.
	PWR_PWR_CR3_USB33DEN_Pos = 0x18
	// Bit mask of USB33DEN field.
	PWR_PWR_CR3_USB33DEN_Msk = 0x1000000
	// Bit USB33DEN.
	PWR_PWR_CR3_USB33DEN = 0x1000000
	// Position of USB33RDY field.
	PWR_PWR_CR3_USB33RDY_Pos = 0x1a
	// Bit mask of USB33RDY field.
	PWR_PWR_CR3_USB33RDY_Msk = 0x4000000
	// Bit USB33RDY.
	PWR_PWR_CR3_USB33RDY = 0x4000000
	// Position of REG18EN field.
	PWR_PWR_CR3_REG18EN_Pos = 0x1c
	// Bit mask of REG18EN field.
	PWR_PWR_CR3_REG18EN_Msk = 0x10000000
	// Bit REG18EN.
	PWR_PWR_CR3_REG18EN = 0x10000000
	// Position of REG18RDY field.
	PWR_PWR_CR3_REG18RDY_Pos = 0x1d
	// Bit mask of REG18RDY field.
	PWR_PWR_CR3_REG18RDY_Msk = 0x20000000
	// Bit REG18RDY.
	PWR_PWR_CR3_REG18RDY = 0x20000000
	// Position of REG11EN field.
	PWR_PWR_CR3_REG11EN_Pos = 0x1e
	// Bit mask of REG11EN field.
	PWR_PWR_CR3_REG11EN_Msk = 0x40000000
	// Bit REG11EN.
	PWR_PWR_CR3_REG11EN = 0x40000000
	// Position of REG11RDY field.
	PWR_PWR_CR3_REG11RDY_Pos = 0x1f
	// Bit mask of REG11RDY field.
	PWR_PWR_CR3_REG11RDY_Msk = 0x80000000
	// Bit REG11RDY.
	PWR_PWR_CR3_REG11RDY = 0x80000000

	// PWR_MPUCR: See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
	// Position of PDDS field.
	PWR_PWR_MPUCR_PDDS_Pos = 0x0
	// Bit mask of PDDS field.
	PWR_PWR_MPUCR_PDDS_Msk = 0x1
	// Bit PDDS.
	PWR_PWR_MPUCR_PDDS = 0x1
	// Position of CSTBYDIS field.
	PWR_PWR_MPUCR_CSTBYDIS_Pos = 0x3
	// Bit mask of CSTBYDIS field.
	PWR_PWR_MPUCR_CSTBYDIS_Msk = 0x8
	// Bit CSTBYDIS.
	PWR_PWR_MPUCR_CSTBYDIS = 0x8
	// Position of STOPF field.
	PWR_PWR_MPUCR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	PWR_PWR_MPUCR_STOPF_Msk = 0x20
	// Bit STOPF.
	PWR_PWR_MPUCR_STOPF = 0x20
	// Position of SBF field.
	PWR_PWR_MPUCR_SBF_Pos = 0x6
	// Bit mask of SBF field.
	PWR_PWR_MPUCR_SBF_Msk = 0x40
	// Bit SBF.
	PWR_PWR_MPUCR_SBF = 0x40
	// Position of SBFMPU field.
	PWR_PWR_MPUCR_SBFMPU_Pos = 0x7
	// Bit mask of SBFMPU field.
	PWR_PWR_MPUCR_SBFMPU_Msk = 0x80
	// Bit SBFMPU.
	PWR_PWR_MPUCR_SBFMPU = 0x80
	// Position of CSSF field.
	PWR_PWR_MPUCR_CSSF_Pos = 0x9
	// Bit mask of CSSF field.
	PWR_PWR_MPUCR_CSSF_Msk = 0x200
	// Bit CSSF.
	PWR_PWR_MPUCR_CSSF = 0x200
	// Position of STANDBYWFIL2 field.
	PWR_PWR_MPUCR_STANDBYWFIL2_Pos = 0xf
	// Bit mask of STANDBYWFIL2 field.
	PWR_PWR_MPUCR_STANDBYWFIL2_Msk = 0x8000
	// Bit STANDBYWFIL2.
	PWR_PWR_MPUCR_STANDBYWFIL2 = 0x8000

	// PWR_MCUCR: See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed.
	// Position of PDDS field.
	PWR_PWR_MCUCR_PDDS_Pos = 0x0
	// Bit mask of PDDS field.
	PWR_PWR_MCUCR_PDDS_Msk = 0x1
	// Bit PDDS.
	PWR_PWR_MCUCR_PDDS = 0x1
	// Position of STOPF field.
	PWR_PWR_MCUCR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	PWR_PWR_MCUCR_STOPF_Msk = 0x20
	// Bit STOPF.
	PWR_PWR_MCUCR_STOPF = 0x20
	// Position of SBF field.
	PWR_PWR_MCUCR_SBF_Pos = 0x6
	// Bit mask of SBF field.
	PWR_PWR_MCUCR_SBF_Msk = 0x40
	// Bit SBF.
	PWR_PWR_MCUCR_SBF = 0x40
	// Position of CSSF field.
	PWR_PWR_MCUCR_CSSF_Pos = 0x9
	// Bit mask of CSSF field.
	PWR_PWR_MCUCR_CSSF_Msk = 0x200
	// Bit CSSF.
	PWR_PWR_MCUCR_CSSF = 0x200
	// Position of DEEPSLEEP field.
	PWR_PWR_MCUCR_DEEPSLEEP_Pos = 0xf
	// Bit mask of DEEPSLEEP field.
	PWR_PWR_MCUCR_DEEPSLEEP_Msk = 0x8000
	// Bit DEEPSLEEP.
	PWR_PWR_MCUCR_DEEPSLEEP = 0x8000

	// PWR_WKUPCR: Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
	// Position of WKUPC1 field.
	PWR_PWR_WKUPCR_WKUPC1_Pos = 0x0
	// Bit mask of WKUPC1 field.
	PWR_PWR_WKUPCR_WKUPC1_Msk = 0x1
	// Bit WKUPC1.
	PWR_PWR_WKUPCR_WKUPC1 = 0x1
	// Position of WKUPC2 field.
	PWR_PWR_WKUPCR_WKUPC2_Pos = 0x1
	// Bit mask of WKUPC2 field.
	PWR_PWR_WKUPCR_WKUPC2_Msk = 0x2
	// Bit WKUPC2.
	PWR_PWR_WKUPCR_WKUPC2 = 0x2
	// Position of WKUPC3 field.
	PWR_PWR_WKUPCR_WKUPC3_Pos = 0x2
	// Bit mask of WKUPC3 field.
	PWR_PWR_WKUPCR_WKUPC3_Msk = 0x4
	// Bit WKUPC3.
	PWR_PWR_WKUPCR_WKUPC3 = 0x4
	// Position of WKUPC4 field.
	PWR_PWR_WKUPCR_WKUPC4_Pos = 0x3
	// Bit mask of WKUPC4 field.
	PWR_PWR_WKUPCR_WKUPC4_Msk = 0x8
	// Bit WKUPC4.
	PWR_PWR_WKUPCR_WKUPC4 = 0x8
	// Position of WKUPC5 field.
	PWR_PWR_WKUPCR_WKUPC5_Pos = 0x4
	// Bit mask of WKUPC5 field.
	PWR_PWR_WKUPCR_WKUPC5_Msk = 0x10
	// Bit WKUPC5.
	PWR_PWR_WKUPCR_WKUPC5 = 0x10
	// Position of WKUPC6 field.
	PWR_PWR_WKUPCR_WKUPC6_Pos = 0x5
	// Bit mask of WKUPC6 field.
	PWR_PWR_WKUPCR_WKUPC6_Msk = 0x20
	// Bit WKUPC6.
	PWR_PWR_WKUPCR_WKUPC6 = 0x20
	// Position of WKUPP1 field.
	PWR_PWR_WKUPCR_WKUPP1_Pos = 0x8
	// Bit mask of WKUPP1 field.
	PWR_PWR_WKUPCR_WKUPP1_Msk = 0x100
	// Bit WKUPP1.
	PWR_PWR_WKUPCR_WKUPP1 = 0x100
	// Position of WKUPP2 field.
	PWR_PWR_WKUPCR_WKUPP2_Pos = 0x9
	// Bit mask of WKUPP2 field.
	PWR_PWR_WKUPCR_WKUPP2_Msk = 0x200
	// Bit WKUPP2.
	PWR_PWR_WKUPCR_WKUPP2 = 0x200
	// Position of WKUPP3 field.
	PWR_PWR_WKUPCR_WKUPP3_Pos = 0xa
	// Bit mask of WKUPP3 field.
	PWR_PWR_WKUPCR_WKUPP3_Msk = 0x400
	// Bit WKUPP3.
	PWR_PWR_WKUPCR_WKUPP3 = 0x400
	// Position of WKUPP4 field.
	PWR_PWR_WKUPCR_WKUPP4_Pos = 0xb
	// Bit mask of WKUPP4 field.
	PWR_PWR_WKUPCR_WKUPP4_Msk = 0x800
	// Bit WKUPP4.
	PWR_PWR_WKUPCR_WKUPP4 = 0x800
	// Position of WKUPP5 field.
	PWR_PWR_WKUPCR_WKUPP5_Pos = 0xc
	// Bit mask of WKUPP5 field.
	PWR_PWR_WKUPCR_WKUPP5_Msk = 0x1000
	// Bit WKUPP5.
	PWR_PWR_WKUPCR_WKUPP5 = 0x1000
	// Position of WKUPP6 field.
	PWR_PWR_WKUPCR_WKUPP6_Pos = 0xd
	// Bit mask of WKUPP6 field.
	PWR_PWR_WKUPCR_WKUPP6_Msk = 0x2000
	// Bit WKUPP6.
	PWR_PWR_WKUPCR_WKUPP6 = 0x2000
	// Position of WKUPPUPD1 field.
	PWR_PWR_WKUPCR_WKUPPUPD1_Pos = 0x10
	// Bit mask of WKUPPUPD1 field.
	PWR_PWR_WKUPCR_WKUPPUPD1_Msk = 0x30000
	// Position of WKUPPUPD2 field.
	PWR_PWR_WKUPCR_WKUPPUPD2_Pos = 0x12
	// Bit mask of WKUPPUPD2 field.
	PWR_PWR_WKUPCR_WKUPPUPD2_Msk = 0xc0000
	// Position of WKUPPUPD3 field.
	PWR_PWR_WKUPCR_WKUPPUPD3_Pos = 0x14
	// Bit mask of WKUPPUPD3 field.
	PWR_PWR_WKUPCR_WKUPPUPD3_Msk = 0x300000
	// Position of WKUPPUPD4 field.
	PWR_PWR_WKUPCR_WKUPPUPD4_Pos = 0x16
	// Bit mask of WKUPPUPD4 field.
	PWR_PWR_WKUPCR_WKUPPUPD4_Msk = 0xc00000
	// Position of WKUPPUPD5 field.
	PWR_PWR_WKUPCR_WKUPPUPD5_Pos = 0x18
	// Bit mask of WKUPPUPD5 field.
	PWR_PWR_WKUPCR_WKUPPUPD5_Msk = 0x3000000
	// Position of WKUPPUPD6 field.
	PWR_PWR_WKUPCR_WKUPPUPD6_Pos = 0x1a
	// Bit mask of WKUPPUPD6 field.
	PWR_PWR_WKUPCR_WKUPPUPD6_Msk = 0xc000000

	// PWR_WKUPFR: Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...)
	// Position of WKUPF1 field.
	PWR_PWR_WKUPFR_WKUPF1_Pos = 0x0
	// Bit mask of WKUPF1 field.
	PWR_PWR_WKUPFR_WKUPF1_Msk = 0x1
	// Bit WKUPF1.
	PWR_PWR_WKUPFR_WKUPF1 = 0x1
	// Position of WKUPF2 field.
	PWR_PWR_WKUPFR_WKUPF2_Pos = 0x1
	// Bit mask of WKUPF2 field.
	PWR_PWR_WKUPFR_WKUPF2_Msk = 0x2
	// Bit WKUPF2.
	PWR_PWR_WKUPFR_WKUPF2 = 0x2
	// Position of WKUPF3 field.
	PWR_PWR_WKUPFR_WKUPF3_Pos = 0x2
	// Bit mask of WKUPF3 field.
	PWR_PWR_WKUPFR_WKUPF3_Msk = 0x4
	// Bit WKUPF3.
	PWR_PWR_WKUPFR_WKUPF3 = 0x4
	// Position of WKUPF4 field.
	PWR_PWR_WKUPFR_WKUPF4_Pos = 0x3
	// Bit mask of WKUPF4 field.
	PWR_PWR_WKUPFR_WKUPF4_Msk = 0x8
	// Bit WKUPF4.
	PWR_PWR_WKUPFR_WKUPF4 = 0x8
	// Position of WKUPF5 field.
	PWR_PWR_WKUPFR_WKUPF5_Pos = 0x4
	// Bit mask of WKUPF5 field.
	PWR_PWR_WKUPFR_WKUPF5_Msk = 0x10
	// Bit WKUPF5.
	PWR_PWR_WKUPFR_WKUPF5 = 0x10
	// Position of WKUPF6 field.
	PWR_PWR_WKUPFR_WKUPF6_Pos = 0x5
	// Bit mask of WKUPF6 field.
	PWR_PWR_WKUPFR_WKUPF6_Msk = 0x20
	// Bit WKUPF6.
	PWR_PWR_WKUPFR_WKUPF6 = 0x20

	// PWR_MPUWKUPENR: Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
	// Position of WKUPEN1 field.
	PWR_PWR_MPUWKUPENR_WKUPEN1_Pos = 0x0
	// Bit mask of WKUPEN1 field.
	PWR_PWR_MPUWKUPENR_WKUPEN1_Msk = 0x1
	// Bit WKUPEN1.
	PWR_PWR_MPUWKUPENR_WKUPEN1 = 0x1
	// Position of WKUPEN2 field.
	PWR_PWR_MPUWKUPENR_WKUPEN2_Pos = 0x1
	// Bit mask of WKUPEN2 field.
	PWR_PWR_MPUWKUPENR_WKUPEN2_Msk = 0x2
	// Bit WKUPEN2.
	PWR_PWR_MPUWKUPENR_WKUPEN2 = 0x2
	// Position of WKUPEN3 field.
	PWR_PWR_MPUWKUPENR_WKUPEN3_Pos = 0x2
	// Bit mask of WKUPEN3 field.
	PWR_PWR_MPUWKUPENR_WKUPEN3_Msk = 0x4
	// Bit WKUPEN3.
	PWR_PWR_MPUWKUPENR_WKUPEN3 = 0x4
	// Position of WKUPEN4 field.
	PWR_PWR_MPUWKUPENR_WKUPEN4_Pos = 0x3
	// Bit mask of WKUPEN4 field.
	PWR_PWR_MPUWKUPENR_WKUPEN4_Msk = 0x8
	// Bit WKUPEN4.
	PWR_PWR_MPUWKUPENR_WKUPEN4 = 0x8
	// Position of WKUPEN5 field.
	PWR_PWR_MPUWKUPENR_WKUPEN5_Pos = 0x4
	// Bit mask of WKUPEN5 field.
	PWR_PWR_MPUWKUPENR_WKUPEN5_Msk = 0x10
	// Bit WKUPEN5.
	PWR_PWR_MPUWKUPENR_WKUPEN5 = 0x10
	// Position of WKUPEN6 field.
	PWR_PWR_MPUWKUPENR_WKUPEN6_Pos = 0x5
	// Bit mask of WKUPEN6 field.
	PWR_PWR_MPUWKUPENR_WKUPEN6_Msk = 0x20
	// Bit WKUPEN6.
	PWR_PWR_MPUWKUPENR_WKUPEN6 = 0x20

	// PWR_MCUWKUPENR: Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed.
	// Position of WKUPEN1 field.
	PWR_PWR_MCUWKUPENR_WKUPEN1_Pos = 0x0
	// Bit mask of WKUPEN1 field.
	PWR_PWR_MCUWKUPENR_WKUPEN1_Msk = 0x1
	// Bit WKUPEN1.
	PWR_PWR_MCUWKUPENR_WKUPEN1 = 0x1
	// Position of WKUPEN2 field.
	PWR_PWR_MCUWKUPENR_WKUPEN2_Pos = 0x1
	// Bit mask of WKUPEN2 field.
	PWR_PWR_MCUWKUPENR_WKUPEN2_Msk = 0x2
	// Bit WKUPEN2.
	PWR_PWR_MCUWKUPENR_WKUPEN2 = 0x2
	// Position of WKUPEN3 field.
	PWR_PWR_MCUWKUPENR_WKUPEN3_Pos = 0x2
	// Bit mask of WKUPEN3 field.
	PWR_PWR_MCUWKUPENR_WKUPEN3_Msk = 0x4
	// Bit WKUPEN3.
	PWR_PWR_MCUWKUPENR_WKUPEN3 = 0x4
	// Position of WKUPEN4 field.
	PWR_PWR_MCUWKUPENR_WKUPEN4_Pos = 0x3
	// Bit mask of WKUPEN4 field.
	PWR_PWR_MCUWKUPENR_WKUPEN4_Msk = 0x8
	// Bit WKUPEN4.
	PWR_PWR_MCUWKUPENR_WKUPEN4 = 0x8
	// Position of WKUPEN5 field.
	PWR_PWR_MCUWKUPENR_WKUPEN5_Pos = 0x4
	// Bit mask of WKUPEN5 field.
	PWR_PWR_MCUWKUPENR_WKUPEN5_Msk = 0x10
	// Bit WKUPEN5.
	PWR_PWR_MCUWKUPENR_WKUPEN5 = 0x10
	// Position of WKUPEN6 field.
	PWR_PWR_MCUWKUPENR_WKUPEN6_Pos = 0x5
	// Bit mask of WKUPEN6 field.
	PWR_PWR_MCUWKUPENR_WKUPEN6_Msk = 0x20
	// Bit WKUPEN6.
	PWR_PWR_MCUWKUPENR_WKUPEN6 = 0x20

	// PWR_VER: PWR IP version register
	// Position of MINREV field.
	PWR_PWR_VER_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	PWR_PWR_VER_MINREV_Msk = 0xf
	// Position of MAJREV field.
	PWR_PWR_VER_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	PWR_PWR_VER_MAJREV_Msk = 0xf0

	// PWR_ID: PWR IP identification register
	// Position of IPID field.
	PWR_PWR_ID_IPID_Pos = 0x0
	// Bit mask of IPID field.
	PWR_PWR_ID_IPID_Msk = 0xffffffff

	// PWR_SID: PWR size ID register
	// Position of SID field.
	PWR_PWR_SID_SID_Pos = 0x0
	// Bit mask of SID field.
	PWR_PWR_SID_SID_Msk = 0xffffffff
)

// Bitfields for QUADSPI: QUADSPI1
const (
	// QUADSPI_CR: QUADSPI control register
	// Position of EN field.
	QUADSPI1_QUADSPI_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	QUADSPI1_QUADSPI_CR_EN_Msk = 0x1
	// Bit EN.
	QUADSPI1_QUADSPI_CR_EN = 0x1
	// Position of ABORT field.
	QUADSPI1_QUADSPI_CR_ABORT_Pos = 0x1
	// Bit mask of ABORT field.
	QUADSPI1_QUADSPI_CR_ABORT_Msk = 0x2
	// Bit ABORT.
	QUADSPI1_QUADSPI_CR_ABORT = 0x2
	// Position of DMAEN field.
	QUADSPI1_QUADSPI_CR_DMAEN_Pos = 0x2
	// Bit mask of DMAEN field.
	QUADSPI1_QUADSPI_CR_DMAEN_Msk = 0x4
	// Bit DMAEN.
	QUADSPI1_QUADSPI_CR_DMAEN = 0x4
	// Position of TCEN field.
	QUADSPI1_QUADSPI_CR_TCEN_Pos = 0x3
	// Bit mask of TCEN field.
	QUADSPI1_QUADSPI_CR_TCEN_Msk = 0x8
	// Bit TCEN.
	QUADSPI1_QUADSPI_CR_TCEN = 0x8
	// Position of SSHIFT field.
	QUADSPI1_QUADSPI_CR_SSHIFT_Pos = 0x4
	// Bit mask of SSHIFT field.
	QUADSPI1_QUADSPI_CR_SSHIFT_Msk = 0x10
	// Bit SSHIFT.
	QUADSPI1_QUADSPI_CR_SSHIFT = 0x10
	// Position of DFM field.
	QUADSPI1_QUADSPI_CR_DFM_Pos = 0x6
	// Bit mask of DFM field.
	QUADSPI1_QUADSPI_CR_DFM_Msk = 0x40
	// Bit DFM.
	QUADSPI1_QUADSPI_CR_DFM = 0x40
	// Position of FSEL field.
	QUADSPI1_QUADSPI_CR_FSEL_Pos = 0x7
	// Bit mask of FSEL field.
	QUADSPI1_QUADSPI_CR_FSEL_Msk = 0x80
	// Bit FSEL.
	QUADSPI1_QUADSPI_CR_FSEL = 0x80
	// Position of FTHRES field.
	QUADSPI1_QUADSPI_CR_FTHRES_Pos = 0x8
	// Bit mask of FTHRES field.
	QUADSPI1_QUADSPI_CR_FTHRES_Msk = 0xf00
	// Position of TEIE field.
	QUADSPI1_QUADSPI_CR_TEIE_Pos = 0x10
	// Bit mask of TEIE field.
	QUADSPI1_QUADSPI_CR_TEIE_Msk = 0x10000
	// Bit TEIE.
	QUADSPI1_QUADSPI_CR_TEIE = 0x10000
	// Position of TCIE field.
	QUADSPI1_QUADSPI_CR_TCIE_Pos = 0x11
	// Bit mask of TCIE field.
	QUADSPI1_QUADSPI_CR_TCIE_Msk = 0x20000
	// Bit TCIE.
	QUADSPI1_QUADSPI_CR_TCIE = 0x20000
	// Position of FTIE field.
	QUADSPI1_QUADSPI_CR_FTIE_Pos = 0x12
	// Bit mask of FTIE field.
	QUADSPI1_QUADSPI_CR_FTIE_Msk = 0x40000
	// Bit FTIE.
	QUADSPI1_QUADSPI_CR_FTIE = 0x40000
	// Position of SMIE field.
	QUADSPI1_QUADSPI_CR_SMIE_Pos = 0x13
	// Bit mask of SMIE field.
	QUADSPI1_QUADSPI_CR_SMIE_Msk = 0x80000
	// Bit SMIE.
	QUADSPI1_QUADSPI_CR_SMIE = 0x80000
	// Position of TOIE field.
	QUADSPI1_QUADSPI_CR_TOIE_Pos = 0x14
	// Bit mask of TOIE field.
	QUADSPI1_QUADSPI_CR_TOIE_Msk = 0x100000
	// Bit TOIE.
	QUADSPI1_QUADSPI_CR_TOIE = 0x100000
	// Position of APMS field.
	QUADSPI1_QUADSPI_CR_APMS_Pos = 0x16
	// Bit mask of APMS field.
	QUADSPI1_QUADSPI_CR_APMS_Msk = 0x400000
	// Bit APMS.
	QUADSPI1_QUADSPI_CR_APMS = 0x400000
	// Position of PMM field.
	QUADSPI1_QUADSPI_CR_PMM_Pos = 0x17
	// Bit mask of PMM field.
	QUADSPI1_QUADSPI_CR_PMM_Msk = 0x800000
	// Bit PMM.
	QUADSPI1_QUADSPI_CR_PMM = 0x800000
	// Position of PRESCALER field.
	QUADSPI1_QUADSPI_CR_PRESCALER_Pos = 0x18
	// Bit mask of PRESCALER field.
	QUADSPI1_QUADSPI_CR_PRESCALER_Msk = 0xff000000

	// QUADSPI_DCR: QUADSPI device configuration register
	// Position of CKMODE field.
	QUADSPI1_QUADSPI_DCR_CKMODE_Pos = 0x0
	// Bit mask of CKMODE field.
	QUADSPI1_QUADSPI_DCR_CKMODE_Msk = 0x1
	// Bit CKMODE.
	QUADSPI1_QUADSPI_DCR_CKMODE = 0x1
	// Position of CSHT field.
	QUADSPI1_QUADSPI_DCR_CSHT_Pos = 0x8
	// Bit mask of CSHT field.
	QUADSPI1_QUADSPI_DCR_CSHT_Msk = 0x700
	// Position of FSIZE field.
	QUADSPI1_QUADSPI_DCR_FSIZE_Pos = 0x10
	// Bit mask of FSIZE field.
	QUADSPI1_QUADSPI_DCR_FSIZE_Msk = 0x1f0000

	// QUADSPI_SR: QUADSPI status register
	// Position of TEF field.
	QUADSPI1_QUADSPI_SR_TEF_Pos = 0x0
	// Bit mask of TEF field.
	QUADSPI1_QUADSPI_SR_TEF_Msk = 0x1
	// Bit TEF.
	QUADSPI1_QUADSPI_SR_TEF = 0x1
	// Position of TCF field.
	QUADSPI1_QUADSPI_SR_TCF_Pos = 0x1
	// Bit mask of TCF field.
	QUADSPI1_QUADSPI_SR_TCF_Msk = 0x2
	// Bit TCF.
	QUADSPI1_QUADSPI_SR_TCF = 0x2
	// Position of FTF field.
	QUADSPI1_QUADSPI_SR_FTF_Pos = 0x2
	// Bit mask of FTF field.
	QUADSPI1_QUADSPI_SR_FTF_Msk = 0x4
	// Bit FTF.
	QUADSPI1_QUADSPI_SR_FTF = 0x4
	// Position of SMF field.
	QUADSPI1_QUADSPI_SR_SMF_Pos = 0x3
	// Bit mask of SMF field.
	QUADSPI1_QUADSPI_SR_SMF_Msk = 0x8
	// Bit SMF.
	QUADSPI1_QUADSPI_SR_SMF = 0x8
	// Position of TOF field.
	QUADSPI1_QUADSPI_SR_TOF_Pos = 0x4
	// Bit mask of TOF field.
	QUADSPI1_QUADSPI_SR_TOF_Msk = 0x10
	// Bit TOF.
	QUADSPI1_QUADSPI_SR_TOF = 0x10
	// Position of BUSY field.
	QUADSPI1_QUADSPI_SR_BUSY_Pos = 0x5
	// Bit mask of BUSY field.
	QUADSPI1_QUADSPI_SR_BUSY_Msk = 0x20
	// Bit BUSY.
	QUADSPI1_QUADSPI_SR_BUSY = 0x20
	// Position of FLEVEL field.
	QUADSPI1_QUADSPI_SR_FLEVEL_Pos = 0x8
	// Bit mask of FLEVEL field.
	QUADSPI1_QUADSPI_SR_FLEVEL_Msk = 0x1f00

	// QUADSPI_FCR: QUADSPI flag clear register
	// Position of CTEF field.
	QUADSPI1_QUADSPI_FCR_CTEF_Pos = 0x0
	// Bit mask of CTEF field.
	QUADSPI1_QUADSPI_FCR_CTEF_Msk = 0x1
	// Bit CTEF.
	QUADSPI1_QUADSPI_FCR_CTEF = 0x1
	// Position of CTCF field.
	QUADSPI1_QUADSPI_FCR_CTCF_Pos = 0x1
	// Bit mask of CTCF field.
	QUADSPI1_QUADSPI_FCR_CTCF_Msk = 0x2
	// Bit CTCF.
	QUADSPI1_QUADSPI_FCR_CTCF = 0x2
	// Position of CSMF field.
	QUADSPI1_QUADSPI_FCR_CSMF_Pos = 0x3
	// Bit mask of CSMF field.
	QUADSPI1_QUADSPI_FCR_CSMF_Msk = 0x8
	// Bit CSMF.
	QUADSPI1_QUADSPI_FCR_CSMF = 0x8
	// Position of CTOF field.
	QUADSPI1_QUADSPI_FCR_CTOF_Pos = 0x4
	// Bit mask of CTOF field.
	QUADSPI1_QUADSPI_FCR_CTOF_Msk = 0x10
	// Bit CTOF.
	QUADSPI1_QUADSPI_FCR_CTOF = 0x10

	// QUADSPI_DLR: QUADSPI data length register
	// Position of DL field.
	QUADSPI1_QUADSPI_DLR_DL_Pos = 0x0
	// Bit mask of DL field.
	QUADSPI1_QUADSPI_DLR_DL_Msk = 0xffffffff

	// QUADSPI_CCR: QUADSPI communication configuration register
	// Position of INSTRUCTION field.
	QUADSPI1_QUADSPI_CCR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	QUADSPI1_QUADSPI_CCR_INSTRUCTION_Msk = 0xff
	// Position of IMODE field.
	QUADSPI1_QUADSPI_CCR_IMODE_Pos = 0x8
	// Bit mask of IMODE field.
	QUADSPI1_QUADSPI_CCR_IMODE_Msk = 0x300
	// Position of ADMODE field.
	QUADSPI1_QUADSPI_CCR_ADMODE_Pos = 0xa
	// Bit mask of ADMODE field.
	QUADSPI1_QUADSPI_CCR_ADMODE_Msk = 0xc00
	// Position of ADSIZE field.
	QUADSPI1_QUADSPI_CCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	QUADSPI1_QUADSPI_CCR_ADSIZE_Msk = 0x3000
	// Position of ABMODE field.
	QUADSPI1_QUADSPI_CCR_ABMODE_Pos = 0xe
	// Bit mask of ABMODE field.
	QUADSPI1_QUADSPI_CCR_ABMODE_Msk = 0xc000
	// Position of ABSIZE field.
	QUADSPI1_QUADSPI_CCR_ABSIZE_Pos = 0x10
	// Bit mask of ABSIZE field.
	QUADSPI1_QUADSPI_CCR_ABSIZE_Msk = 0x30000
	// Position of DCYC field.
	QUADSPI1_QUADSPI_CCR_DCYC_Pos = 0x12
	// Bit mask of DCYC field.
	QUADSPI1_QUADSPI_CCR_DCYC_Msk = 0x7c0000
	// Position of DMODE field.
	QUADSPI1_QUADSPI_CCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	QUADSPI1_QUADSPI_CCR_DMODE_Msk = 0x3000000
	// Position of FMODE field.
	QUADSPI1_QUADSPI_CCR_FMODE_Pos = 0x1a
	// Bit mask of FMODE field.
	QUADSPI1_QUADSPI_CCR_FMODE_Msk = 0xc000000
	// Position of SIOO field.
	QUADSPI1_QUADSPI_CCR_SIOO_Pos = 0x1c
	// Bit mask of SIOO field.
	QUADSPI1_QUADSPI_CCR_SIOO_Msk = 0x10000000
	// Bit SIOO.
	QUADSPI1_QUADSPI_CCR_SIOO = 0x10000000
	// Position of FRCM field.
	QUADSPI1_QUADSPI_CCR_FRCM_Pos = 0x1d
	// Bit mask of FRCM field.
	QUADSPI1_QUADSPI_CCR_FRCM_Msk = 0x20000000
	// Bit FRCM.
	QUADSPI1_QUADSPI_CCR_FRCM = 0x20000000
	// Position of DHHC field.
	QUADSPI1_QUADSPI_CCR_DHHC_Pos = 0x1e
	// Bit mask of DHHC field.
	QUADSPI1_QUADSPI_CCR_DHHC_Msk = 0x40000000
	// Bit DHHC.
	QUADSPI1_QUADSPI_CCR_DHHC = 0x40000000
	// Position of DDRM field.
	QUADSPI1_QUADSPI_CCR_DDRM_Pos = 0x1f
	// Bit mask of DDRM field.
	QUADSPI1_QUADSPI_CCR_DDRM_Msk = 0x80000000
	// Bit DDRM.
	QUADSPI1_QUADSPI_CCR_DDRM = 0x80000000

	// QUADSPI_AR: QUADSPI address register
	// Position of ADDRESS field.
	QUADSPI1_QUADSPI_AR_ADDRESS_Pos = 0x0
	// Bit mask of ADDRESS field.
	QUADSPI1_QUADSPI_AR_ADDRESS_Msk = 0xffffffff

	// QUADSPI_ABR: QUADSPI alternate bytes registers
	// Position of ALTERNATE field.
	QUADSPI1_QUADSPI_ABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	QUADSPI1_QUADSPI_ABR_ALTERNATE_Msk = 0xffffffff

	// QUADSPI_DR: QUADSPI data register
	// Position of DATA field.
	QUADSPI1_QUADSPI_DR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	QUADSPI1_QUADSPI_DR_DATA_Msk = 0xffffffff

	// QUADSPI_PSMKR: QUADSPI polling status mask register
	// Position of MASK field.
	QUADSPI1_QUADSPI_PSMKR_MASK_Pos = 0x0
	// Bit mask of MASK field.
	QUADSPI1_QUADSPI_PSMKR_MASK_Msk = 0xffffffff

	// QUADSPI_PSMAR: QUADSPI polling status match register
	// Position of MATCH field.
	QUADSPI1_QUADSPI_PSMAR_MATCH_Pos = 0x0
	// Bit mask of MATCH field.
	QUADSPI1_QUADSPI_PSMAR_MATCH_Msk = 0xffffffff

	// QUADSPI_PIR: QUADSPI polling interval register
	// Position of INTERVAL field.
	QUADSPI1_QUADSPI_PIR_INTERVAL_Pos = 0x0
	// Bit mask of INTERVAL field.
	QUADSPI1_QUADSPI_PIR_INTERVAL_Msk = 0xffff

	// QUADSPI_LPTR: QUADSPI low-power timeout register
	// Position of TIMEOUT field.
	QUADSPI1_QUADSPI_LPTR_TIMEOUT_Pos = 0x0
	// Bit mask of TIMEOUT field.
	QUADSPI1_QUADSPI_LPTR_TIMEOUT_Msk = 0xffff

	// QUADSPI_HWCFGR: QUADSPI HW configuration register
	// Position of FIFOSIZE field.
	QUADSPI1_QUADSPI_HWCFGR_FIFOSIZE_Pos = 0x0
	// Bit mask of FIFOSIZE field.
	QUADSPI1_QUADSPI_HWCFGR_FIFOSIZE_Msk = 0xf
	// Position of FIFOPTR field.
	QUADSPI1_QUADSPI_HWCFGR_FIFOPTR_Pos = 0x4
	// Bit mask of FIFOPTR field.
	QUADSPI1_QUADSPI_HWCFGR_FIFOPTR_Msk = 0xf0
	// Position of PRESCVAL field.
	QUADSPI1_QUADSPI_HWCFGR_PRESCVAL_Pos = 0x8
	// Bit mask of PRESCVAL field.
	QUADSPI1_QUADSPI_HWCFGR_PRESCVAL_Msk = 0xf00
	// Position of IDLENGTH field.
	QUADSPI1_QUADSPI_HWCFGR_IDLENGTH_Pos = 0xc
	// Bit mask of IDLENGTH field.
	QUADSPI1_QUADSPI_HWCFGR_IDLENGTH_Msk = 0xf000

	// QUADSPI_VERR: QUADSPI version register
	// Position of MINREV field.
	QUADSPI1_QUADSPI_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	QUADSPI1_QUADSPI_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	QUADSPI1_QUADSPI_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	QUADSPI1_QUADSPI_VERR_MAJREV_Msk = 0xf0

	// QUADSPI_IPIDR: QUADSPI identification register
	// Position of ID field.
	QUADSPI1_QUADSPI_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	QUADSPI1_QUADSPI_IPIDR_ID_Msk = 0xffffffff

	// QUADSPI_SIDR: QUADSPI size identification register
	// Position of SID field.
	QUADSPI1_QUADSPI_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	QUADSPI1_QUADSPI_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for RCC: RCC
const (
	// RCC_TZCR: This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode.
	// Position of TZEN field.
	RCC_RCC_TZCR_TZEN_Pos = 0x0
	// Bit mask of TZEN field.
	RCC_RCC_TZCR_TZEN_Msk = 0x1
	// Bit TZEN.
	RCC_RCC_TZCR_TZEN = 0x1
	// Position of MCKPROT field.
	RCC_RCC_TZCR_MCKPROT_Pos = 0x1
	// Bit mask of MCKPROT field.
	RCC_RCC_TZCR_MCKPROT_Msk = 0x2
	// Bit MCKPROT.
	RCC_RCC_TZCR_MCKPROT = 0x2

	// RCC_OCENSETR: This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of HSION field.
	RCC_RCC_OCENSETR_HSION_Pos = 0x0
	// Bit mask of HSION field.
	RCC_RCC_OCENSETR_HSION_Msk = 0x1
	// Bit HSION.
	RCC_RCC_OCENSETR_HSION = 0x1
	// Position of HSIKERON field.
	RCC_RCC_OCENSETR_HSIKERON_Pos = 0x1
	// Bit mask of HSIKERON field.
	RCC_RCC_OCENSETR_HSIKERON_Msk = 0x2
	// Bit HSIKERON.
	RCC_RCC_OCENSETR_HSIKERON = 0x2
	// Position of CSION field.
	RCC_RCC_OCENSETR_CSION_Pos = 0x4
	// Bit mask of CSION field.
	RCC_RCC_OCENSETR_CSION_Msk = 0x10
	// Bit CSION.
	RCC_RCC_OCENSETR_CSION = 0x10
	// Position of CSIKERON field.
	RCC_RCC_OCENSETR_CSIKERON_Pos = 0x5
	// Bit mask of CSIKERON field.
	RCC_RCC_OCENSETR_CSIKERON_Msk = 0x20
	// Bit CSIKERON.
	RCC_RCC_OCENSETR_CSIKERON = 0x20
	// Position of DIGBYP field.
	RCC_RCC_OCENSETR_DIGBYP_Pos = 0x7
	// Bit mask of DIGBYP field.
	RCC_RCC_OCENSETR_DIGBYP_Msk = 0x80
	// Bit DIGBYP.
	RCC_RCC_OCENSETR_DIGBYP = 0x80
	// Position of HSEON field.
	RCC_RCC_OCENSETR_HSEON_Pos = 0x8
	// Bit mask of HSEON field.
	RCC_RCC_OCENSETR_HSEON_Msk = 0x100
	// Bit HSEON.
	RCC_RCC_OCENSETR_HSEON = 0x100
	// Position of HSEKERON field.
	RCC_RCC_OCENSETR_HSEKERON_Pos = 0x9
	// Bit mask of HSEKERON field.
	RCC_RCC_OCENSETR_HSEKERON_Msk = 0x200
	// Bit HSEKERON.
	RCC_RCC_OCENSETR_HSEKERON = 0x200
	// Position of HSEBYP field.
	RCC_RCC_OCENSETR_HSEBYP_Pos = 0xa
	// Bit mask of HSEBYP field.
	RCC_RCC_OCENSETR_HSEBYP_Msk = 0x400
	// Bit HSEBYP.
	RCC_RCC_OCENSETR_HSEBYP = 0x400
	// Position of HSECSSON field.
	RCC_RCC_OCENSETR_HSECSSON_Pos = 0xb
	// Bit mask of HSECSSON field.
	RCC_RCC_OCENSETR_HSECSSON_Msk = 0x800
	// Bit HSECSSON.
	RCC_RCC_OCENSETR_HSECSSON = 0x800

	// RCC_OCENCLRR: This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of HSION field.
	RCC_RCC_OCENCLRR_HSION_Pos = 0x0
	// Bit mask of HSION field.
	RCC_RCC_OCENCLRR_HSION_Msk = 0x1
	// Bit HSION.
	RCC_RCC_OCENCLRR_HSION = 0x1
	// Position of HSIKERON field.
	RCC_RCC_OCENCLRR_HSIKERON_Pos = 0x1
	// Bit mask of HSIKERON field.
	RCC_RCC_OCENCLRR_HSIKERON_Msk = 0x2
	// Bit HSIKERON.
	RCC_RCC_OCENCLRR_HSIKERON = 0x2
	// Position of CSION field.
	RCC_RCC_OCENCLRR_CSION_Pos = 0x4
	// Bit mask of CSION field.
	RCC_RCC_OCENCLRR_CSION_Msk = 0x10
	// Bit CSION.
	RCC_RCC_OCENCLRR_CSION = 0x10
	// Position of CSIKERON field.
	RCC_RCC_OCENCLRR_CSIKERON_Pos = 0x5
	// Bit mask of CSIKERON field.
	RCC_RCC_OCENCLRR_CSIKERON_Msk = 0x20
	// Bit CSIKERON.
	RCC_RCC_OCENCLRR_CSIKERON = 0x20
	// Position of DIGBYP field.
	RCC_RCC_OCENCLRR_DIGBYP_Pos = 0x7
	// Bit mask of DIGBYP field.
	RCC_RCC_OCENCLRR_DIGBYP_Msk = 0x80
	// Bit DIGBYP.
	RCC_RCC_OCENCLRR_DIGBYP = 0x80
	// Position of HSEON field.
	RCC_RCC_OCENCLRR_HSEON_Pos = 0x8
	// Bit mask of HSEON field.
	RCC_RCC_OCENCLRR_HSEON_Msk = 0x100
	// Bit HSEON.
	RCC_RCC_OCENCLRR_HSEON = 0x100
	// Position of HSEKERON field.
	RCC_RCC_OCENCLRR_HSEKERON_Pos = 0x9
	// Bit mask of HSEKERON field.
	RCC_RCC_OCENCLRR_HSEKERON_Msk = 0x200
	// Bit HSEKERON.
	RCC_RCC_OCENCLRR_HSEKERON = 0x200
	// Position of HSEBYP field.
	RCC_RCC_OCENCLRR_HSEBYP_Pos = 0xa
	// Bit mask of HSEBYP field.
	RCC_RCC_OCENCLRR_HSEBYP_Msk = 0x400
	// Bit HSEBYP.
	RCC_RCC_OCENCLRR_HSEBYP = 0x400

	// RCC_HSICFGR: This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of HSIDIV field.
	RCC_RCC_HSICFGR_HSIDIV_Pos = 0x0
	// Bit mask of HSIDIV field.
	RCC_RCC_HSICFGR_HSIDIV_Msk = 0x3
	// Position of HSITRIM field.
	RCC_RCC_HSICFGR_HSITRIM_Pos = 0x8
	// Bit mask of HSITRIM field.
	RCC_RCC_HSICFGR_HSITRIM_Msk = 0x7f00
	// Position of HSICAL field.
	RCC_RCC_HSICFGR_HSICAL_Pos = 0x10
	// Bit mask of HSICAL field.
	RCC_RCC_HSICFGR_HSICAL_Msk = 0xfff0000

	// RCC_CSICFGR: This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details.
	// Position of CSITRIM field.
	RCC_RCC_CSICFGR_CSITRIM_Pos = 0x8
	// Bit mask of CSITRIM field.
	RCC_RCC_CSICFGR_CSITRIM_Msk = 0x1f00
	// Position of CSICAL field.
	RCC_RCC_CSICFGR_CSICAL_Pos = 0x10
	// Bit mask of CSICAL field.
	RCC_RCC_CSICFGR_CSICAL_Msk = 0xff0000

	// RCC_MPCKSELR: This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of MPUSRC field.
	RCC_RCC_MPCKSELR_MPUSRC_Pos = 0x0
	// Bit mask of MPUSRC field.
	RCC_RCC_MPCKSELR_MPUSRC_Msk = 0x3
	// Position of MPUSRCRDY field.
	RCC_RCC_MPCKSELR_MPUSRCRDY_Pos = 0x1f
	// Bit mask of MPUSRCRDY field.
	RCC_RCC_MPCKSELR_MPUSRCRDY_Msk = 0x80000000
	// Bit MPUSRCRDY.
	RCC_RCC_MPCKSELR_MPUSRCRDY = 0x80000000

	// RCC_ASSCKSELR: This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of AXISSRC field.
	RCC_RCC_ASSCKSELR_AXISSRC_Pos = 0x0
	// Bit mask of AXISSRC field.
	RCC_RCC_ASSCKSELR_AXISSRC_Msk = 0x7
	// Position of AXISSRCRDY field.
	RCC_RCC_ASSCKSELR_AXISSRCRDY_Pos = 0x1f
	// Bit mask of AXISSRCRDY field.
	RCC_RCC_ASSCKSELR_AXISSRCRDY_Msk = 0x80000000
	// Bit AXISSRCRDY.
	RCC_RCC_ASSCKSELR_AXISSRCRDY = 0x80000000

	// RCC_RCK12SELR: This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of PLL12SRC field.
	RCC_RCC_RCK12SELR_PLL12SRC_Pos = 0x0
	// Bit mask of PLL12SRC field.
	RCC_RCC_RCK12SELR_PLL12SRC_Msk = 0x3
	// Position of PLL12SRCRDY field.
	RCC_RCC_RCK12SELR_PLL12SRCRDY_Pos = 0x1f
	// Bit mask of PLL12SRCRDY field.
	RCC_RCC_RCK12SELR_PLL12SRCRDY_Msk = 0x80000000
	// Bit PLL12SRCRDY.
	RCC_RCC_RCK12SELR_PLL12SRCRDY = 0x80000000

	// RCC_MPCKDIVR: This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
	// Position of MPUDIV field.
	RCC_RCC_MPCKDIVR_MPUDIV_Pos = 0x0
	// Bit mask of MPUDIV field.
	RCC_RCC_MPCKDIVR_MPUDIV_Msk = 0x7
	// Position of MPUDIVRDY field.
	RCC_RCC_MPCKDIVR_MPUDIVRDY_Pos = 0x1f
	// Bit mask of MPUDIVRDY field.
	RCC_RCC_MPCKDIVR_MPUDIVRDY_Msk = 0x80000000
	// Bit MPUDIVRDY.
	RCC_RCC_MPCKDIVR_MPUDIVRDY = 0x80000000

	// RCC_AXIDIVR: This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
	// Position of AXIDIV field.
	RCC_RCC_AXIDIVR_AXIDIV_Pos = 0x0
	// Bit mask of AXIDIV field.
	RCC_RCC_AXIDIVR_AXIDIV_Msk = 0x7
	// Position of AXIDIVRDY field.
	RCC_RCC_AXIDIVR_AXIDIVRDY_Pos = 0x1f
	// Bit mask of AXIDIVRDY field.
	RCC_RCC_AXIDIVR_AXIDIVRDY_Msk = 0x80000000
	// Bit AXIDIVRDY.
	RCC_RCC_AXIDIVR_AXIDIVRDY = 0x80000000

	// RCC_APB4DIVR: This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
	// Position of APB4DIV field.
	RCC_RCC_APB4DIVR_APB4DIV_Pos = 0x0
	// Bit mask of APB4DIV field.
	RCC_RCC_APB4DIVR_APB4DIV_Msk = 0x7
	// Position of APB4DIVRDY field.
	RCC_RCC_APB4DIVR_APB4DIVRDY_Pos = 0x1f
	// Bit mask of APB4DIVRDY field.
	RCC_RCC_APB4DIVR_APB4DIVRDY_Msk = 0x80000000
	// Bit APB4DIVRDY.
	RCC_RCC_APB4DIVR_APB4DIVRDY = 0x80000000

	// RCC_APB5DIVR: This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
	// Position of APB5DIV field.
	RCC_RCC_APB5DIVR_APB5DIV_Pos = 0x0
	// Bit mask of APB5DIV field.
	RCC_RCC_APB5DIVR_APB5DIV_Msk = 0x7
	// Position of APB5DIVRDY field.
	RCC_RCC_APB5DIVR_APB5DIVRDY_Pos = 0x1f
	// Bit mask of APB5DIVRDY field.
	RCC_RCC_APB5DIVR_APB5DIVRDY_Msk = 0x80000000
	// Bit APB5DIVRDY.
	RCC_RCC_APB5DIVR_APB5DIVRDY = 0x80000000

	// RCC_RTCDIVR: This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode.
	// Position of RTCDIV field.
	RCC_RCC_RTCDIVR_RTCDIV_Pos = 0x0
	// Bit mask of RTCDIV field.
	RCC_RCC_RTCDIVR_RTCDIV_Msk = 0x3f

	// RCC_MSSCKSELR: This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of MCUSSRC field.
	RCC_RCC_MSSCKSELR_MCUSSRC_Pos = 0x0
	// Bit mask of MCUSSRC field.
	RCC_RCC_MSSCKSELR_MCUSSRC_Msk = 0x3
	// Position of MCUSSRCRDY field.
	RCC_RCC_MSSCKSELR_MCUSSRCRDY_Pos = 0x1f
	// Bit mask of MCUSSRCRDY field.
	RCC_RCC_MSSCKSELR_MCUSSRCRDY_Msk = 0x80000000
	// Bit MCUSSRCRDY.
	RCC_RCC_MSSCKSELR_MCUSSRCRDY = 0x80000000

	// RCC_PLL1CR: This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of PLLON field.
	RCC_RCC_PLL1CR_PLLON_Pos = 0x0
	// Bit mask of PLLON field.
	RCC_RCC_PLL1CR_PLLON_Msk = 0x1
	// Bit PLLON.
	RCC_RCC_PLL1CR_PLLON = 0x1
	// Position of PLL1RDY field.
	RCC_RCC_PLL1CR_PLL1RDY_Pos = 0x1
	// Bit mask of PLL1RDY field.
	RCC_RCC_PLL1CR_PLL1RDY_Msk = 0x2
	// Bit PLL1RDY.
	RCC_RCC_PLL1CR_PLL1RDY = 0x2
	// Position of SSCG_CTRL field.
	RCC_RCC_PLL1CR_SSCG_CTRL_Pos = 0x2
	// Bit mask of SSCG_CTRL field.
	RCC_RCC_PLL1CR_SSCG_CTRL_Msk = 0x4
	// Bit SSCG_CTRL.
	RCC_RCC_PLL1CR_SSCG_CTRL = 0x4
	// Position of DIVPEN field.
	RCC_RCC_PLL1CR_DIVPEN_Pos = 0x4
	// Bit mask of DIVPEN field.
	RCC_RCC_PLL1CR_DIVPEN_Msk = 0x10
	// Bit DIVPEN.
	RCC_RCC_PLL1CR_DIVPEN = 0x10
	// Position of DIVQEN field.
	RCC_RCC_PLL1CR_DIVQEN_Pos = 0x5
	// Bit mask of DIVQEN field.
	RCC_RCC_PLL1CR_DIVQEN_Msk = 0x20
	// Bit DIVQEN.
	RCC_RCC_PLL1CR_DIVQEN = 0x20
	// Position of DIVREN field.
	RCC_RCC_PLL1CR_DIVREN_Pos = 0x6
	// Bit mask of DIVREN field.
	RCC_RCC_PLL1CR_DIVREN_Msk = 0x40
	// Bit DIVREN.
	RCC_RCC_PLL1CR_DIVREN = 0x40

	// RCC_PLL1CFGR1: This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of DIVN field.
	RCC_RCC_PLL1CFGR1_DIVN_Pos = 0x0
	// Bit mask of DIVN field.
	RCC_RCC_PLL1CFGR1_DIVN_Msk = 0x1ff
	// Position of DIVM1 field.
	RCC_RCC_PLL1CFGR1_DIVM1_Pos = 0x10
	// Bit mask of DIVM1 field.
	RCC_RCC_PLL1CFGR1_DIVM1_Msk = 0x3f0000

	// RCC_PLL1CFGR2: This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of DIVP field.
	RCC_RCC_PLL1CFGR2_DIVP_Pos = 0x0
	// Bit mask of DIVP field.
	RCC_RCC_PLL1CFGR2_DIVP_Msk = 0x7f
	// Position of DIVQ field.
	RCC_RCC_PLL1CFGR2_DIVQ_Pos = 0x8
	// Bit mask of DIVQ field.
	RCC_RCC_PLL1CFGR2_DIVQ_Msk = 0x7f00
	// Position of DIVR field.
	RCC_RCC_PLL1CFGR2_DIVR_Pos = 0x10
	// Bit mask of DIVR field.
	RCC_RCC_PLL1CFGR2_DIVR_Msk = 0x7f0000

	// RCC_PLL1FRACR: This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of FRACV field.
	RCC_RCC_PLL1FRACR_FRACV_Pos = 0x3
	// Bit mask of FRACV field.
	RCC_RCC_PLL1FRACR_FRACV_Msk = 0xfff8
	// Position of FRACLE field.
	RCC_RCC_PLL1FRACR_FRACLE_Pos = 0x10
	// Bit mask of FRACLE field.
	RCC_RCC_PLL1FRACR_FRACLE_Msk = 0x10000
	// Bit FRACLE.
	RCC_RCC_PLL1FRACR_FRACLE = 0x10000

	// RCC_PLL1CSGR: This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of MOD_PER field.
	RCC_RCC_PLL1CSGR_MOD_PER_Pos = 0x0
	// Bit mask of MOD_PER field.
	RCC_RCC_PLL1CSGR_MOD_PER_Msk = 0x1fff
	// Position of TPDFN_DIS field.
	RCC_RCC_PLL1CSGR_TPDFN_DIS_Pos = 0xd
	// Bit mask of TPDFN_DIS field.
	RCC_RCC_PLL1CSGR_TPDFN_DIS_Msk = 0x2000
	// Bit TPDFN_DIS.
	RCC_RCC_PLL1CSGR_TPDFN_DIS = 0x2000
	// Position of RPDFN_DIS field.
	RCC_RCC_PLL1CSGR_RPDFN_DIS_Pos = 0xe
	// Bit mask of RPDFN_DIS field.
	RCC_RCC_PLL1CSGR_RPDFN_DIS_Msk = 0x4000
	// Bit RPDFN_DIS.
	RCC_RCC_PLL1CSGR_RPDFN_DIS = 0x4000
	// Position of SSCG_MODE field.
	RCC_RCC_PLL1CSGR_SSCG_MODE_Pos = 0xf
	// Bit mask of SSCG_MODE field.
	RCC_RCC_PLL1CSGR_SSCG_MODE_Msk = 0x8000
	// Bit SSCG_MODE.
	RCC_RCC_PLL1CSGR_SSCG_MODE = 0x8000
	// Position of INC_STEP field.
	RCC_RCC_PLL1CSGR_INC_STEP_Pos = 0x10
	// Bit mask of INC_STEP field.
	RCC_RCC_PLL1CSGR_INC_STEP_Msk = 0x7fff0000

	// RCC_PLL2CR: This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of PLLON field.
	RCC_RCC_PLL2CR_PLLON_Pos = 0x0
	// Bit mask of PLLON field.
	RCC_RCC_PLL2CR_PLLON_Msk = 0x1
	// Bit PLLON.
	RCC_RCC_PLL2CR_PLLON = 0x1
	// Position of PLL2RDY field.
	RCC_RCC_PLL2CR_PLL2RDY_Pos = 0x1
	// Bit mask of PLL2RDY field.
	RCC_RCC_PLL2CR_PLL2RDY_Msk = 0x2
	// Bit PLL2RDY.
	RCC_RCC_PLL2CR_PLL2RDY = 0x2
	// Position of SSCG_CTRL field.
	RCC_RCC_PLL2CR_SSCG_CTRL_Pos = 0x2
	// Bit mask of SSCG_CTRL field.
	RCC_RCC_PLL2CR_SSCG_CTRL_Msk = 0x4
	// Bit SSCG_CTRL.
	RCC_RCC_PLL2CR_SSCG_CTRL = 0x4
	// Position of DIVPEN field.
	RCC_RCC_PLL2CR_DIVPEN_Pos = 0x4
	// Bit mask of DIVPEN field.
	RCC_RCC_PLL2CR_DIVPEN_Msk = 0x10
	// Bit DIVPEN.
	RCC_RCC_PLL2CR_DIVPEN = 0x10
	// Position of DIVQEN field.
	RCC_RCC_PLL2CR_DIVQEN_Pos = 0x5
	// Bit mask of DIVQEN field.
	RCC_RCC_PLL2CR_DIVQEN_Msk = 0x20
	// Bit DIVQEN.
	RCC_RCC_PLL2CR_DIVQEN = 0x20
	// Position of DIVREN field.
	RCC_RCC_PLL2CR_DIVREN_Pos = 0x6
	// Bit mask of DIVREN field.
	RCC_RCC_PLL2CR_DIVREN_Msk = 0x40
	// Bit DIVREN.
	RCC_RCC_PLL2CR_DIVREN = 0x40

	// RCC_PLL2CFGR1: This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of DIVN field.
	RCC_RCC_PLL2CFGR1_DIVN_Pos = 0x0
	// Bit mask of DIVN field.
	RCC_RCC_PLL2CFGR1_DIVN_Msk = 0x1ff
	// Position of DIVM2 field.
	RCC_RCC_PLL2CFGR1_DIVM2_Pos = 0x10
	// Bit mask of DIVM2 field.
	RCC_RCC_PLL2CFGR1_DIVM2_Msk = 0x3f0000

	// RCC_PLL2CFGR2: This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of DIVP field.
	RCC_RCC_PLL2CFGR2_DIVP_Pos = 0x0
	// Bit mask of DIVP field.
	RCC_RCC_PLL2CFGR2_DIVP_Msk = 0x7f
	// Position of DIVQ field.
	RCC_RCC_PLL2CFGR2_DIVQ_Pos = 0x8
	// Bit mask of DIVQ field.
	RCC_RCC_PLL2CFGR2_DIVQ_Msk = 0x7f00
	// Position of DIVR field.
	RCC_RCC_PLL2CFGR2_DIVR_Pos = 0x10
	// Bit mask of DIVR field.
	RCC_RCC_PLL2CFGR2_DIVR_Msk = 0x7f0000

	// RCC_PLL2FRACR: This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of FRACV field.
	RCC_RCC_PLL2FRACR_FRACV_Pos = 0x3
	// Bit mask of FRACV field.
	RCC_RCC_PLL2FRACR_FRACV_Msk = 0xfff8
	// Position of FRACLE field.
	RCC_RCC_PLL2FRACR_FRACLE_Pos = 0x10
	// Bit mask of FRACLE field.
	RCC_RCC_PLL2FRACR_FRACLE_Msk = 0x10000
	// Bit FRACLE.
	RCC_RCC_PLL2FRACR_FRACLE = 0x10000

	// RCC_PLL2CSGR: This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
	// Position of MOD_PER field.
	RCC_RCC_PLL2CSGR_MOD_PER_Pos = 0x0
	// Bit mask of MOD_PER field.
	RCC_RCC_PLL2CSGR_MOD_PER_Msk = 0x1fff
	// Position of TPDFN_DIS field.
	RCC_RCC_PLL2CSGR_TPDFN_DIS_Pos = 0xd
	// Bit mask of TPDFN_DIS field.
	RCC_RCC_PLL2CSGR_TPDFN_DIS_Msk = 0x2000
	// Bit TPDFN_DIS.
	RCC_RCC_PLL2CSGR_TPDFN_DIS = 0x2000
	// Position of RPDFN_DIS field.
	RCC_RCC_PLL2CSGR_RPDFN_DIS_Pos = 0xe
	// Bit mask of RPDFN_DIS field.
	RCC_RCC_PLL2CSGR_RPDFN_DIS_Msk = 0x4000
	// Bit RPDFN_DIS.
	RCC_RCC_PLL2CSGR_RPDFN_DIS = 0x4000
	// Position of SSCG_MODE field.
	RCC_RCC_PLL2CSGR_SSCG_MODE_Pos = 0xf
	// Bit mask of SSCG_MODE field.
	RCC_RCC_PLL2CSGR_SSCG_MODE_Msk = 0x8000
	// Bit SSCG_MODE.
	RCC_RCC_PLL2CSGR_SSCG_MODE = 0x8000
	// Position of INC_STEP field.
	RCC_RCC_PLL2CSGR_INC_STEP_Pos = 0x10
	// Bit mask of INC_STEP field.
	RCC_RCC_PLL2CSGR_INC_STEP_Msk = 0x7fff0000

	// RCC_I2C46CKSELR: This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
	// Position of I2C46SRC field.
	RCC_RCC_I2C46CKSELR_I2C46SRC_Pos = 0x0
	// Bit mask of I2C46SRC field.
	RCC_RCC_I2C46CKSELR_I2C46SRC_Msk = 0x7

	// RCC_SPI6CKSELR: This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
	// Position of SPI6SRC field.
	RCC_RCC_SPI6CKSELR_SPI6SRC_Pos = 0x0
	// Bit mask of SPI6SRC field.
	RCC_RCC_SPI6CKSELR_SPI6SRC_Msk = 0x7

	// RCC_UART1CKSELR: This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
	// Position of UART1SRC field.
	RCC_RCC_UART1CKSELR_UART1SRC_Pos = 0x0
	// Bit mask of UART1SRC field.
	RCC_RCC_UART1CKSELR_UART1SRC_Msk = 0x7

	// RCC_RNG1CKSELR: This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
	// Position of RNG1SRC field.
	RCC_RCC_RNG1CKSELR_RNG1SRC_Pos = 0x0
	// Bit mask of RNG1SRC field.
	RCC_RCC_RNG1CKSELR_RNG1SRC_Msk = 0x3

	// RCC_CPERCKSELR: This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays.
	// Position of CKPERSRC field.
	RCC_RCC_CPERCKSELR_CKPERSRC_Pos = 0x0
	// Bit mask of CKPERSRC field.
	RCC_RCC_CPERCKSELR_CKPERSRC_Msk = 0x3

	// RCC_STGENCKSELR: This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
	// Position of STGENSRC field.
	RCC_RCC_STGENCKSELR_STGENSRC_Pos = 0x0
	// Bit mask of STGENSRC field.
	RCC_RCC_STGENCKSELR_STGENSRC_Msk = 0x3

	// RCC_DDRITFCR: This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode.
	// Position of DDRC1EN field.
	RCC_RCC_DDRITFCR_DDRC1EN_Pos = 0x0
	// Bit mask of DDRC1EN field.
	RCC_RCC_DDRITFCR_DDRC1EN_Msk = 0x1
	// Bit DDRC1EN.
	RCC_RCC_DDRITFCR_DDRC1EN = 0x1
	// Position of DDRC1LPEN field.
	RCC_RCC_DDRITFCR_DDRC1LPEN_Pos = 0x1
	// Bit mask of DDRC1LPEN field.
	RCC_RCC_DDRITFCR_DDRC1LPEN_Msk = 0x2
	// Bit DDRC1LPEN.
	RCC_RCC_DDRITFCR_DDRC1LPEN = 0x2
	// Position of DDRC2EN field.
	RCC_RCC_DDRITFCR_DDRC2EN_Pos = 0x2
	// Bit mask of DDRC2EN field.
	RCC_RCC_DDRITFCR_DDRC2EN_Msk = 0x4
	// Bit DDRC2EN.
	RCC_RCC_DDRITFCR_DDRC2EN = 0x4
	// Position of DDRC2LPEN field.
	RCC_RCC_DDRITFCR_DDRC2LPEN_Pos = 0x3
	// Bit mask of DDRC2LPEN field.
	RCC_RCC_DDRITFCR_DDRC2LPEN_Msk = 0x8
	// Bit DDRC2LPEN.
	RCC_RCC_DDRITFCR_DDRC2LPEN = 0x8
	// Position of DDRPHYCEN field.
	RCC_RCC_DDRITFCR_DDRPHYCEN_Pos = 0x4
	// Bit mask of DDRPHYCEN field.
	RCC_RCC_DDRITFCR_DDRPHYCEN_Msk = 0x10
	// Bit DDRPHYCEN.
	RCC_RCC_DDRITFCR_DDRPHYCEN = 0x10
	// Position of DDRPHYCLPEN field.
	RCC_RCC_DDRITFCR_DDRPHYCLPEN_Pos = 0x5
	// Bit mask of DDRPHYCLPEN field.
	RCC_RCC_DDRITFCR_DDRPHYCLPEN_Msk = 0x20
	// Bit DDRPHYCLPEN.
	RCC_RCC_DDRITFCR_DDRPHYCLPEN = 0x20
	// Position of DDRCAPBEN field.
	RCC_RCC_DDRITFCR_DDRCAPBEN_Pos = 0x6
	// Bit mask of DDRCAPBEN field.
	RCC_RCC_DDRITFCR_DDRCAPBEN_Msk = 0x40
	// Bit DDRCAPBEN.
	RCC_RCC_DDRITFCR_DDRCAPBEN = 0x40
	// Position of DDRCAPBLPEN field.
	RCC_RCC_DDRITFCR_DDRCAPBLPEN_Pos = 0x7
	// Bit mask of DDRCAPBLPEN field.
	RCC_RCC_DDRITFCR_DDRCAPBLPEN_Msk = 0x80
	// Bit DDRCAPBLPEN.
	RCC_RCC_DDRITFCR_DDRCAPBLPEN = 0x80
	// Position of AXIDCGEN field.
	RCC_RCC_DDRITFCR_AXIDCGEN_Pos = 0x8
	// Bit mask of AXIDCGEN field.
	RCC_RCC_DDRITFCR_AXIDCGEN_Msk = 0x100
	// Bit AXIDCGEN.
	RCC_RCC_DDRITFCR_AXIDCGEN = 0x100
	// Position of DDRPHYCAPBEN field.
	RCC_RCC_DDRITFCR_DDRPHYCAPBEN_Pos = 0x9
	// Bit mask of DDRPHYCAPBEN field.
	RCC_RCC_DDRITFCR_DDRPHYCAPBEN_Msk = 0x200
	// Bit DDRPHYCAPBEN.
	RCC_RCC_DDRITFCR_DDRPHYCAPBEN = 0x200
	// Position of DDRPHYCAPBLPEN field.
	RCC_RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos = 0xa
	// Bit mask of DDRPHYCAPBLPEN field.
	RCC_RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk = 0x400
	// Bit DDRPHYCAPBLPEN.
	RCC_RCC_DDRITFCR_DDRPHYCAPBLPEN = 0x400
	// Position of KERDCG_DLY field.
	RCC_RCC_DDRITFCR_KERDCG_DLY_Pos = 0xb
	// Bit mask of KERDCG_DLY field.
	RCC_RCC_DDRITFCR_KERDCG_DLY_Msk = 0x3800
	// Position of DDRCAPBRST field.
	RCC_RCC_DDRITFCR_DDRCAPBRST_Pos = 0xe
	// Bit mask of DDRCAPBRST field.
	RCC_RCC_DDRITFCR_DDRCAPBRST_Msk = 0x4000
	// Bit DDRCAPBRST.
	RCC_RCC_DDRITFCR_DDRCAPBRST = 0x4000
	// Position of DDRCAXIRST field.
	RCC_RCC_DDRITFCR_DDRCAXIRST_Pos = 0xf
	// Bit mask of DDRCAXIRST field.
	RCC_RCC_DDRITFCR_DDRCAXIRST_Msk = 0x8000
	// Bit DDRCAXIRST.
	RCC_RCC_DDRITFCR_DDRCAXIRST = 0x8000
	// Position of DDRCORERST field.
	RCC_RCC_DDRITFCR_DDRCORERST_Pos = 0x10
	// Bit mask of DDRCORERST field.
	RCC_RCC_DDRITFCR_DDRCORERST_Msk = 0x10000
	// Bit DDRCORERST.
	RCC_RCC_DDRITFCR_DDRCORERST = 0x10000
	// Position of DPHYAPBRST field.
	RCC_RCC_DDRITFCR_DPHYAPBRST_Pos = 0x11
	// Bit mask of DPHYAPBRST field.
	RCC_RCC_DDRITFCR_DPHYAPBRST_Msk = 0x20000
	// Bit DPHYAPBRST.
	RCC_RCC_DDRITFCR_DPHYAPBRST = 0x20000
	// Position of DPHYRST field.
	RCC_RCC_DDRITFCR_DPHYRST_Pos = 0x12
	// Bit mask of DPHYRST field.
	RCC_RCC_DDRITFCR_DPHYRST_Msk = 0x40000
	// Bit DPHYRST.
	RCC_RCC_DDRITFCR_DPHYRST = 0x40000
	// Position of DPHYCTLRST field.
	RCC_RCC_DDRITFCR_DPHYCTLRST_Pos = 0x13
	// Bit mask of DPHYCTLRST field.
	RCC_RCC_DDRITFCR_DPHYCTLRST_Msk = 0x80000
	// Bit DPHYCTLRST.
	RCC_RCC_DDRITFCR_DPHYCTLRST = 0x80000
	// Position of DDRCKMOD field.
	RCC_RCC_DDRITFCR_DDRCKMOD_Pos = 0x14
	// Bit mask of DDRCKMOD field.
	RCC_RCC_DDRITFCR_DDRCKMOD_Msk = 0x700000
	// Position of GSKPMOD field.
	RCC_RCC_DDRITFCR_GSKPMOD_Pos = 0x17
	// Bit mask of GSKPMOD field.
	RCC_RCC_DDRITFCR_GSKPMOD_Msk = 0x800000
	// Bit GSKPMOD.
	RCC_RCC_DDRITFCR_GSKPMOD = 0x800000
	// Position of GSKPCTRL field.
	RCC_RCC_DDRITFCR_GSKPCTRL_Pos = 0x18
	// Bit mask of GSKPCTRL field.
	RCC_RCC_DDRITFCR_GSKPCTRL_Msk = 0x1000000
	// Bit GSKPCTRL.
	RCC_RCC_DDRITFCR_GSKPCTRL = 0x1000000
	// Position of DFILP_WIDTH field.
	RCC_RCC_DDRITFCR_DFILP_WIDTH_Pos = 0x19
	// Bit mask of DFILP_WIDTH field.
	RCC_RCC_DDRITFCR_DFILP_WIDTH_Msk = 0xe000000
	// Position of GSKP_DUR field.
	RCC_RCC_DDRITFCR_GSKP_DUR_Pos = 0x1c
	// Bit mask of GSKP_DUR field.
	RCC_RCC_DDRITFCR_GSKP_DUR_Msk = 0xf0000000

	// RCC_MP_BOOTCR: This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU.
	// Position of MCU_BEN field.
	RCC_RCC_MP_BOOTCR_MCU_BEN_Pos = 0x0
	// Bit mask of MCU_BEN field.
	RCC_RCC_MP_BOOTCR_MCU_BEN_Msk = 0x1
	// Bit MCU_BEN.
	RCC_RCC_MP_BOOTCR_MCU_BEN = 0x1
	// Position of MPU_BEN field.
	RCC_RCC_MP_BOOTCR_MPU_BEN_Pos = 0x1
	// Bit mask of MPU_BEN field.
	RCC_RCC_MP_BOOTCR_MPU_BEN_Msk = 0x2
	// Bit MPU_BEN.
	RCC_RCC_MP_BOOTCR_MPU_BEN = 0x2

	// RCC_MP_SREQSETR: Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
	// Position of STPREQ_P0 field.
	RCC_RCC_MP_SREQSETR_STPREQ_P0_Pos = 0x0
	// Bit mask of STPREQ_P0 field.
	RCC_RCC_MP_SREQSETR_STPREQ_P0_Msk = 0x1
	// Bit STPREQ_P0.
	RCC_RCC_MP_SREQSETR_STPREQ_P0 = 0x1
	// Position of STPREQ_P1 field.
	RCC_RCC_MP_SREQSETR_STPREQ_P1_Pos = 0x1
	// Bit mask of STPREQ_P1 field.
	RCC_RCC_MP_SREQSETR_STPREQ_P1_Msk = 0x2
	// Bit STPREQ_P1.
	RCC_RCC_MP_SREQSETR_STPREQ_P1 = 0x2

	// RCC_MP_SREQCLRR: Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
	// Position of STPREQ_P0 field.
	RCC_RCC_MP_SREQCLRR_STPREQ_P0_Pos = 0x0
	// Bit mask of STPREQ_P0 field.
	RCC_RCC_MP_SREQCLRR_STPREQ_P0_Msk = 0x1
	// Bit STPREQ_P0.
	RCC_RCC_MP_SREQCLRR_STPREQ_P0 = 0x1
	// Position of STPREQ_P1 field.
	RCC_RCC_MP_SREQCLRR_STPREQ_P1_Pos = 0x1
	// Bit mask of STPREQ_P1 field.
	RCC_RCC_MP_SREQCLRR_STPREQ_P1_Msk = 0x2
	// Bit STPREQ_P1.
	RCC_RCC_MP_SREQCLRR_STPREQ_P1 = 0x2

	// RCC_MP_GCR: The register contains global control bits. If TZEN = , this register can only be modified in secure mode.
	// Position of BOOT_MCU field.
	RCC_RCC_MP_GCR_BOOT_MCU_Pos = 0x0
	// Bit mask of BOOT_MCU field.
	RCC_RCC_MP_GCR_BOOT_MCU_Msk = 0x1
	// Bit BOOT_MCU.
	RCC_RCC_MP_GCR_BOOT_MCU = 0x1

	// RCC_MP_APRSTCR: This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode.
	// Position of RDCTLEN field.
	RCC_RCC_MP_APRSTCR_RDCTLEN_Pos = 0x0
	// Bit mask of RDCTLEN field.
	RCC_RCC_MP_APRSTCR_RDCTLEN_Msk = 0x1
	// Bit RDCTLEN.
	RCC_RCC_MP_APRSTCR_RDCTLEN = 0x1
	// Position of RSTTO field.
	RCC_RCC_MP_APRSTCR_RSTTO_Pos = 0x8
	// Bit mask of RSTTO field.
	RCC_RCC_MP_APRSTCR_RSTTO_Msk = 0x7f00

	// RCC_MP_APRSTSR: This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode.
	// Position of RSTTOV field.
	RCC_RCC_MP_APRSTSR_RSTTOV_Pos = 0x8
	// Bit mask of RSTTOV field.
	RCC_RCC_MP_APRSTSR_RSTTOV_Msk = 0x7f00

	// RCC_BDCR: This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode.
	// Position of LSEON field.
	RCC_RCC_BDCR_LSEON_Pos = 0x0
	// Bit mask of LSEON field.
	RCC_RCC_BDCR_LSEON_Msk = 0x1
	// Bit LSEON.
	RCC_RCC_BDCR_LSEON = 0x1
	// Position of LSEBYP field.
	RCC_RCC_BDCR_LSEBYP_Pos = 0x1
	// Bit mask of LSEBYP field.
	RCC_RCC_BDCR_LSEBYP_Msk = 0x2
	// Bit LSEBYP.
	RCC_RCC_BDCR_LSEBYP = 0x2
	// Position of LSERDY field.
	RCC_RCC_BDCR_LSERDY_Pos = 0x2
	// Bit mask of LSERDY field.
	RCC_RCC_BDCR_LSERDY_Msk = 0x4
	// Bit LSERDY.
	RCC_RCC_BDCR_LSERDY = 0x4
	// Position of DIGBYP field.
	RCC_RCC_BDCR_DIGBYP_Pos = 0x3
	// Bit mask of DIGBYP field.
	RCC_RCC_BDCR_DIGBYP_Msk = 0x8
	// Bit DIGBYP.
	RCC_RCC_BDCR_DIGBYP = 0x8
	// Position of LSEDRV field.
	RCC_RCC_BDCR_LSEDRV_Pos = 0x4
	// Bit mask of LSEDRV field.
	RCC_RCC_BDCR_LSEDRV_Msk = 0x30
	// Position of LSECSSON field.
	RCC_RCC_BDCR_LSECSSON_Pos = 0x8
	// Bit mask of LSECSSON field.
	RCC_RCC_BDCR_LSECSSON_Msk = 0x100
	// Bit LSECSSON.
	RCC_RCC_BDCR_LSECSSON = 0x100
	// Position of LSECSSD field.
	RCC_RCC_BDCR_LSECSSD_Pos = 0x9
	// Bit mask of LSECSSD field.
	RCC_RCC_BDCR_LSECSSD_Msk = 0x200
	// Bit LSECSSD.
	RCC_RCC_BDCR_LSECSSD = 0x200
	// Position of RTCSRC field.
	RCC_RCC_BDCR_RTCSRC_Pos = 0x10
	// Bit mask of RTCSRC field.
	RCC_RCC_BDCR_RTCSRC_Msk = 0x30000
	// Position of RTCCKEN field.
	RCC_RCC_BDCR_RTCCKEN_Pos = 0x14
	// Bit mask of RTCCKEN field.
	RCC_RCC_BDCR_RTCCKEN_Msk = 0x100000
	// Bit RTCCKEN.
	RCC_RCC_BDCR_RTCCKEN = 0x100000
	// Position of VSWRST field.
	RCC_RCC_BDCR_VSWRST_Pos = 0x1f
	// Bit mask of VSWRST field.
	RCC_RCC_BDCR_VSWRST_Msk = 0x80000000
	// Bit VSWRST.
	RCC_RCC_BDCR_VSWRST = 0x80000000

	// RCC_RDLSICR: This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode.
	// Position of LSION field.
	RCC_RCC_RDLSICR_LSION_Pos = 0x0
	// Bit mask of LSION field.
	RCC_RCC_RDLSICR_LSION_Msk = 0x1
	// Bit LSION.
	RCC_RCC_RDLSICR_LSION = 0x1
	// Position of LSIRDY field.
	RCC_RCC_RDLSICR_LSIRDY_Pos = 0x1
	// Bit mask of LSIRDY field.
	RCC_RCC_RDLSICR_LSIRDY_Msk = 0x2
	// Bit LSIRDY.
	RCC_RCC_RDLSICR_LSIRDY = 0x2
	// Position of MRD field.
	RCC_RCC_RDLSICR_MRD_Pos = 0x10
	// Bit mask of MRD field.
	RCC_RCC_RDLSICR_MRD_Msk = 0x1f0000
	// Position of EADLY field.
	RCC_RCC_RDLSICR_EADLY_Pos = 0x18
	// Bit mask of EADLY field.
	RCC_RCC_RDLSICR_EADLY_Msk = 0x7000000
	// Position of SPARE field.
	RCC_RCC_RDLSICR_SPARE_Pos = 0x1b
	// Bit mask of SPARE field.
	RCC_RCC_RDLSICR_SPARE_Msk = 0xf8000000

	// RCC_APB4RSTSETR: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
	// Position of LTDCRST field.
	RCC_RCC_APB4RSTSETR_LTDCRST_Pos = 0x0
	// Bit mask of LTDCRST field.
	RCC_RCC_APB4RSTSETR_LTDCRST_Msk = 0x1
	// Bit LTDCRST.
	RCC_RCC_APB4RSTSETR_LTDCRST = 0x1
	// Position of DSIRST field.
	RCC_RCC_APB4RSTSETR_DSIRST_Pos = 0x4
	// Bit mask of DSIRST field.
	RCC_RCC_APB4RSTSETR_DSIRST_Msk = 0x10
	// Bit DSIRST.
	RCC_RCC_APB4RSTSETR_DSIRST = 0x10
	// Position of DDRPERFMRST field.
	RCC_RCC_APB4RSTSETR_DDRPERFMRST_Pos = 0x8
	// Bit mask of DDRPERFMRST field.
	RCC_RCC_APB4RSTSETR_DDRPERFMRST_Msk = 0x100
	// Bit DDRPERFMRST.
	RCC_RCC_APB4RSTSETR_DDRPERFMRST = 0x100
	// Position of USBPHYRST field.
	RCC_RCC_APB4RSTSETR_USBPHYRST_Pos = 0x10
	// Bit mask of USBPHYRST field.
	RCC_RCC_APB4RSTSETR_USBPHYRST_Msk = 0x10000
	// Bit USBPHYRST.
	RCC_RCC_APB4RSTSETR_USBPHYRST = 0x10000

	// RCC_APB4RSTCLRR: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
	// Position of LTDCRST field.
	RCC_RCC_APB4RSTCLRR_LTDCRST_Pos = 0x0
	// Bit mask of LTDCRST field.
	RCC_RCC_APB4RSTCLRR_LTDCRST_Msk = 0x1
	// Bit LTDCRST.
	RCC_RCC_APB4RSTCLRR_LTDCRST = 0x1
	// Position of DSIRST field.
	RCC_RCC_APB4RSTCLRR_DSIRST_Pos = 0x4
	// Bit mask of DSIRST field.
	RCC_RCC_APB4RSTCLRR_DSIRST_Msk = 0x10
	// Bit DSIRST.
	RCC_RCC_APB4RSTCLRR_DSIRST = 0x10
	// Position of DDRPERFMRST field.
	RCC_RCC_APB4RSTCLRR_DDRPERFMRST_Pos = 0x8
	// Bit mask of DDRPERFMRST field.
	RCC_RCC_APB4RSTCLRR_DDRPERFMRST_Msk = 0x100
	// Bit DDRPERFMRST.
	RCC_RCC_APB4RSTCLRR_DDRPERFMRST = 0x100
	// Position of USBPHYRST field.
	RCC_RCC_APB4RSTCLRR_USBPHYRST_Pos = 0x10
	// Bit mask of USBPHYRST field.
	RCC_RCC_APB4RSTCLRR_USBPHYRST_Msk = 0x10000
	// Bit USBPHYRST.
	RCC_RCC_APB4RSTCLRR_USBPHYRST = 0x10000

	// RCC_APB5RSTSETR: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
	// Position of SPI6RST field.
	RCC_RCC_APB5RSTSETR_SPI6RST_Pos = 0x0
	// Bit mask of SPI6RST field.
	RCC_RCC_APB5RSTSETR_SPI6RST_Msk = 0x1
	// Bit SPI6RST.
	RCC_RCC_APB5RSTSETR_SPI6RST = 0x1
	// Position of I2C4RST field.
	RCC_RCC_APB5RSTSETR_I2C4RST_Pos = 0x2
	// Bit mask of I2C4RST field.
	RCC_RCC_APB5RSTSETR_I2C4RST_Msk = 0x4
	// Bit I2C4RST.
	RCC_RCC_APB5RSTSETR_I2C4RST = 0x4
	// Position of I2C6RST field.
	RCC_RCC_APB5RSTSETR_I2C6RST_Pos = 0x3
	// Bit mask of I2C6RST field.
	RCC_RCC_APB5RSTSETR_I2C6RST_Msk = 0x8
	// Bit I2C6RST.
	RCC_RCC_APB5RSTSETR_I2C6RST = 0x8
	// Position of USART1RST field.
	RCC_RCC_APB5RSTSETR_USART1RST_Pos = 0x4
	// Bit mask of USART1RST field.
	RCC_RCC_APB5RSTSETR_USART1RST_Msk = 0x10
	// Bit USART1RST.
	RCC_RCC_APB5RSTSETR_USART1RST = 0x10
	// Position of STGENRST field.
	RCC_RCC_APB5RSTSETR_STGENRST_Pos = 0x14
	// Bit mask of STGENRST field.
	RCC_RCC_APB5RSTSETR_STGENRST_Msk = 0x100000
	// Bit STGENRST.
	RCC_RCC_APB5RSTSETR_STGENRST = 0x100000

	// RCC_APB5RSTCLRR: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
	// Position of SPI6RST field.
	RCC_RCC_APB5RSTCLRR_SPI6RST_Pos = 0x0
	// Bit mask of SPI6RST field.
	RCC_RCC_APB5RSTCLRR_SPI6RST_Msk = 0x1
	// Bit SPI6RST.
	RCC_RCC_APB5RSTCLRR_SPI6RST = 0x1
	// Position of I2C4RST field.
	RCC_RCC_APB5RSTCLRR_I2C4RST_Pos = 0x2
	// Bit mask of I2C4RST field.
	RCC_RCC_APB5RSTCLRR_I2C4RST_Msk = 0x4
	// Bit I2C4RST.
	RCC_RCC_APB5RSTCLRR_I2C4RST = 0x4
	// Position of I2C6RST field.
	RCC_RCC_APB5RSTCLRR_I2C6RST_Pos = 0x3
	// Bit mask of I2C6RST field.
	RCC_RCC_APB5RSTCLRR_I2C6RST_Msk = 0x8
	// Bit I2C6RST.
	RCC_RCC_APB5RSTCLRR_I2C6RST = 0x8
	// Position of USART1RST field.
	RCC_RCC_APB5RSTCLRR_USART1RST_Pos = 0x4
	// Bit mask of USART1RST field.
	RCC_RCC_APB5RSTCLRR_USART1RST_Msk = 0x10
	// Bit USART1RST.
	RCC_RCC_APB5RSTCLRR_USART1RST = 0x10
	// Position of STGENRST field.
	RCC_RCC_APB5RSTCLRR_STGENRST_Pos = 0x14
	// Bit mask of STGENRST field.
	RCC_RCC_APB5RSTCLRR_STGENRST_Msk = 0x100000
	// Bit STGENRST.
	RCC_RCC_APB5RSTCLRR_STGENRST = 0x100000

	// RCC_AHB5RSTSETR: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZRST field.
	RCC_RCC_AHB5RSTSETR_GPIOZRST_Pos = 0x0
	// Bit mask of GPIOZRST field.
	RCC_RCC_AHB5RSTSETR_GPIOZRST_Msk = 0x1
	// Bit GPIOZRST.
	RCC_RCC_AHB5RSTSETR_GPIOZRST = 0x1
	// Position of CRYP1RST field.
	RCC_RCC_AHB5RSTSETR_CRYP1RST_Pos = 0x4
	// Bit mask of CRYP1RST field.
	RCC_RCC_AHB5RSTSETR_CRYP1RST_Msk = 0x10
	// Bit CRYP1RST.
	RCC_RCC_AHB5RSTSETR_CRYP1RST = 0x10
	// Position of HASH1RST field.
	RCC_RCC_AHB5RSTSETR_HASH1RST_Pos = 0x5
	// Bit mask of HASH1RST field.
	RCC_RCC_AHB5RSTSETR_HASH1RST_Msk = 0x20
	// Bit HASH1RST.
	RCC_RCC_AHB5RSTSETR_HASH1RST = 0x20
	// Position of RNG1RST field.
	RCC_RCC_AHB5RSTSETR_RNG1RST_Pos = 0x6
	// Bit mask of RNG1RST field.
	RCC_RCC_AHB5RSTSETR_RNG1RST_Msk = 0x40
	// Bit RNG1RST.
	RCC_RCC_AHB5RSTSETR_RNG1RST = 0x40
	// Position of AXIMCRST field.
	RCC_RCC_AHB5RSTSETR_AXIMCRST_Pos = 0x10
	// Bit mask of AXIMCRST field.
	RCC_RCC_AHB5RSTSETR_AXIMCRST_Msk = 0x10000
	// Bit AXIMCRST.
	RCC_RCC_AHB5RSTSETR_AXIMCRST = 0x10000

	// RCC_AHB5RSTCLRR: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZRST field.
	RCC_RCC_AHB5RSTCLRR_GPIOZRST_Pos = 0x0
	// Bit mask of GPIOZRST field.
	RCC_RCC_AHB5RSTCLRR_GPIOZRST_Msk = 0x1
	// Bit GPIOZRST.
	RCC_RCC_AHB5RSTCLRR_GPIOZRST = 0x1
	// Position of CRYP1RST field.
	RCC_RCC_AHB5RSTCLRR_CRYP1RST_Pos = 0x4
	// Bit mask of CRYP1RST field.
	RCC_RCC_AHB5RSTCLRR_CRYP1RST_Msk = 0x10
	// Bit CRYP1RST.
	RCC_RCC_AHB5RSTCLRR_CRYP1RST = 0x10
	// Position of HASH1RST field.
	RCC_RCC_AHB5RSTCLRR_HASH1RST_Pos = 0x5
	// Bit mask of HASH1RST field.
	RCC_RCC_AHB5RSTCLRR_HASH1RST_Msk = 0x20
	// Bit HASH1RST.
	RCC_RCC_AHB5RSTCLRR_HASH1RST = 0x20
	// Position of RNG1RST field.
	RCC_RCC_AHB5RSTCLRR_RNG1RST_Pos = 0x6
	// Bit mask of RNG1RST field.
	RCC_RCC_AHB5RSTCLRR_RNG1RST_Msk = 0x40
	// Bit RNG1RST.
	RCC_RCC_AHB5RSTCLRR_RNG1RST = 0x40
	// Position of AXIMCRST field.
	RCC_RCC_AHB5RSTCLRR_AXIMCRST_Pos = 0x10
	// Bit mask of AXIMCRST field.
	RCC_RCC_AHB5RSTCLRR_AXIMCRST_Msk = 0x10000
	// Bit AXIMCRST.
	RCC_RCC_AHB5RSTCLRR_AXIMCRST = 0x10000

	// RCC_AHB6RSTSETR: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
	// Position of GPURST field.
	RCC_RCC_AHB6RSTSETR_GPURST_Pos = 0x5
	// Bit mask of GPURST field.
	RCC_RCC_AHB6RSTSETR_GPURST_Msk = 0x20
	// Bit GPURST.
	RCC_RCC_AHB6RSTSETR_GPURST = 0x20
	// Position of ETHMACRST field.
	RCC_RCC_AHB6RSTSETR_ETHMACRST_Pos = 0xa
	// Bit mask of ETHMACRST field.
	RCC_RCC_AHB6RSTSETR_ETHMACRST_Msk = 0x400
	// Bit ETHMACRST.
	RCC_RCC_AHB6RSTSETR_ETHMACRST = 0x400
	// Position of FMCRST field.
	RCC_RCC_AHB6RSTSETR_FMCRST_Pos = 0xc
	// Bit mask of FMCRST field.
	RCC_RCC_AHB6RSTSETR_FMCRST_Msk = 0x1000
	// Bit FMCRST.
	RCC_RCC_AHB6RSTSETR_FMCRST = 0x1000
	// Position of QSPIRST field.
	RCC_RCC_AHB6RSTSETR_QSPIRST_Pos = 0xe
	// Bit mask of QSPIRST field.
	RCC_RCC_AHB6RSTSETR_QSPIRST_Msk = 0x4000
	// Bit QSPIRST.
	RCC_RCC_AHB6RSTSETR_QSPIRST = 0x4000
	// Position of SDMMC1RST field.
	RCC_RCC_AHB6RSTSETR_SDMMC1RST_Pos = 0x10
	// Bit mask of SDMMC1RST field.
	RCC_RCC_AHB6RSTSETR_SDMMC1RST_Msk = 0x10000
	// Bit SDMMC1RST.
	RCC_RCC_AHB6RSTSETR_SDMMC1RST = 0x10000
	// Position of SDMMC2RST field.
	RCC_RCC_AHB6RSTSETR_SDMMC2RST_Pos = 0x11
	// Bit mask of SDMMC2RST field.
	RCC_RCC_AHB6RSTSETR_SDMMC2RST_Msk = 0x20000
	// Bit SDMMC2RST.
	RCC_RCC_AHB6RSTSETR_SDMMC2RST = 0x20000
	// Position of CRC1RST field.
	RCC_RCC_AHB6RSTSETR_CRC1RST_Pos = 0x14
	// Bit mask of CRC1RST field.
	RCC_RCC_AHB6RSTSETR_CRC1RST_Msk = 0x100000
	// Bit CRC1RST.
	RCC_RCC_AHB6RSTSETR_CRC1RST = 0x100000
	// Position of USBHRST field.
	RCC_RCC_AHB6RSTSETR_USBHRST_Pos = 0x18
	// Bit mask of USBHRST field.
	RCC_RCC_AHB6RSTSETR_USBHRST_Msk = 0x1000000
	// Bit USBHRST.
	RCC_RCC_AHB6RSTSETR_USBHRST = 0x1000000

	// RCC_AHB6RSTCLRR: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
	// Position of ETHMACRST field.
	RCC_RCC_AHB6RSTCLRR_ETHMACRST_Pos = 0xa
	// Bit mask of ETHMACRST field.
	RCC_RCC_AHB6RSTCLRR_ETHMACRST_Msk = 0x400
	// Bit ETHMACRST.
	RCC_RCC_AHB6RSTCLRR_ETHMACRST = 0x400
	// Position of FMCRST field.
	RCC_RCC_AHB6RSTCLRR_FMCRST_Pos = 0xc
	// Bit mask of FMCRST field.
	RCC_RCC_AHB6RSTCLRR_FMCRST_Msk = 0x1000
	// Bit FMCRST.
	RCC_RCC_AHB6RSTCLRR_FMCRST = 0x1000
	// Position of QSPIRST field.
	RCC_RCC_AHB6RSTCLRR_QSPIRST_Pos = 0xe
	// Bit mask of QSPIRST field.
	RCC_RCC_AHB6RSTCLRR_QSPIRST_Msk = 0x4000
	// Bit QSPIRST.
	RCC_RCC_AHB6RSTCLRR_QSPIRST = 0x4000
	// Position of SDMMC1RST field.
	RCC_RCC_AHB6RSTCLRR_SDMMC1RST_Pos = 0x10
	// Bit mask of SDMMC1RST field.
	RCC_RCC_AHB6RSTCLRR_SDMMC1RST_Msk = 0x10000
	// Bit SDMMC1RST.
	RCC_RCC_AHB6RSTCLRR_SDMMC1RST = 0x10000
	// Position of SDMMC2RST field.
	RCC_RCC_AHB6RSTCLRR_SDMMC2RST_Pos = 0x11
	// Bit mask of SDMMC2RST field.
	RCC_RCC_AHB6RSTCLRR_SDMMC2RST_Msk = 0x20000
	// Bit SDMMC2RST.
	RCC_RCC_AHB6RSTCLRR_SDMMC2RST = 0x20000
	// Position of CRC1RST field.
	RCC_RCC_AHB6RSTCLRR_CRC1RST_Pos = 0x14
	// Bit mask of CRC1RST field.
	RCC_RCC_AHB6RSTCLRR_CRC1RST_Msk = 0x100000
	// Bit CRC1RST.
	RCC_RCC_AHB6RSTCLRR_CRC1RST = 0x100000
	// Position of USBHRST field.
	RCC_RCC_AHB6RSTCLRR_USBHRST_Pos = 0x18
	// Bit mask of USBHRST field.
	RCC_RCC_AHB6RSTCLRR_USBHRST_Msk = 0x1000000
	// Bit USBHRST.
	RCC_RCC_AHB6RSTCLRR_USBHRST = 0x1000000

	// RCC_TZAHB6RSTSETR: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
	// Position of MDMARST field.
	RCC_RCC_TZAHB6RSTSETR_MDMARST_Pos = 0x0
	// Bit mask of MDMARST field.
	RCC_RCC_TZAHB6RSTSETR_MDMARST_Msk = 0x1
	// Bit MDMARST.
	RCC_RCC_TZAHB6RSTSETR_MDMARST = 0x1

	// RCC_TZAHB6RSTCLRR: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
	// Position of MDMARST field.
	RCC_RCC_TZAHB6RSTCLRR_MDMARST_Pos = 0x0
	// Bit mask of MDMARST field.
	RCC_RCC_TZAHB6RSTCLRR_MDMARST_Msk = 0x1
	// Bit MDMARST.
	RCC_RCC_TZAHB6RSTCLRR_MDMARST = 0x1

	// RCC_MP_APB4ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
	// Position of LTDCEN field.
	RCC_RCC_MP_APB4ENSETR_LTDCEN_Pos = 0x0
	// Bit mask of LTDCEN field.
	RCC_RCC_MP_APB4ENSETR_LTDCEN_Msk = 0x1
	// Bit LTDCEN.
	RCC_RCC_MP_APB4ENSETR_LTDCEN = 0x1
	// Position of DSIEN field.
	RCC_RCC_MP_APB4ENSETR_DSIEN_Pos = 0x4
	// Bit mask of DSIEN field.
	RCC_RCC_MP_APB4ENSETR_DSIEN_Msk = 0x10
	// Bit DSIEN.
	RCC_RCC_MP_APB4ENSETR_DSIEN = 0x10
	// Position of DDRPERFMEN field.
	RCC_RCC_MP_APB4ENSETR_DDRPERFMEN_Pos = 0x8
	// Bit mask of DDRPERFMEN field.
	RCC_RCC_MP_APB4ENSETR_DDRPERFMEN_Msk = 0x100
	// Bit DDRPERFMEN.
	RCC_RCC_MP_APB4ENSETR_DDRPERFMEN = 0x100
	// Position of IWDG2APBEN field.
	RCC_RCC_MP_APB4ENSETR_IWDG2APBEN_Pos = 0xf
	// Bit mask of IWDG2APBEN field.
	RCC_RCC_MP_APB4ENSETR_IWDG2APBEN_Msk = 0x8000
	// Bit IWDG2APBEN.
	RCC_RCC_MP_APB4ENSETR_IWDG2APBEN = 0x8000
	// Position of USBPHYEN field.
	RCC_RCC_MP_APB4ENSETR_USBPHYEN_Pos = 0x10
	// Bit mask of USBPHYEN field.
	RCC_RCC_MP_APB4ENSETR_USBPHYEN_Msk = 0x10000
	// Bit USBPHYEN.
	RCC_RCC_MP_APB4ENSETR_USBPHYEN = 0x10000
	// Position of STGENROEN field.
	RCC_RCC_MP_APB4ENSETR_STGENROEN_Pos = 0x14
	// Bit mask of STGENROEN field.
	RCC_RCC_MP_APB4ENSETR_STGENROEN_Msk = 0x100000
	// Bit STGENROEN.
	RCC_RCC_MP_APB4ENSETR_STGENROEN = 0x100000

	// RCC_MP_APB4ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
	// Position of LTDCEN field.
	RCC_RCC_MP_APB4ENCLRR_LTDCEN_Pos = 0x0
	// Bit mask of LTDCEN field.
	RCC_RCC_MP_APB4ENCLRR_LTDCEN_Msk = 0x1
	// Bit LTDCEN.
	RCC_RCC_MP_APB4ENCLRR_LTDCEN = 0x1
	// Position of DSIEN field.
	RCC_RCC_MP_APB4ENCLRR_DSIEN_Pos = 0x4
	// Bit mask of DSIEN field.
	RCC_RCC_MP_APB4ENCLRR_DSIEN_Msk = 0x10
	// Bit DSIEN.
	RCC_RCC_MP_APB4ENCLRR_DSIEN = 0x10
	// Position of DDRPERFMEN field.
	RCC_RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos = 0x8
	// Bit mask of DDRPERFMEN field.
	RCC_RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk = 0x100
	// Bit DDRPERFMEN.
	RCC_RCC_MP_APB4ENCLRR_DDRPERFMEN = 0x100
	// Position of IWDG2APBEN field.
	RCC_RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos = 0xf
	// Bit mask of IWDG2APBEN field.
	RCC_RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk = 0x8000
	// Bit IWDG2APBEN.
	RCC_RCC_MP_APB4ENCLRR_IWDG2APBEN = 0x8000
	// Position of USBPHYEN field.
	RCC_RCC_MP_APB4ENCLRR_USBPHYEN_Pos = 0x10
	// Bit mask of USBPHYEN field.
	RCC_RCC_MP_APB4ENCLRR_USBPHYEN_Msk = 0x10000
	// Bit USBPHYEN.
	RCC_RCC_MP_APB4ENCLRR_USBPHYEN = 0x10000
	// Position of STGENROEN field.
	RCC_RCC_MP_APB4ENCLRR_STGENROEN_Pos = 0x14
	// Bit mask of STGENROEN field.
	RCC_RCC_MP_APB4ENCLRR_STGENROEN_Msk = 0x100000
	// Bit STGENROEN.
	RCC_RCC_MP_APB4ENCLRR_STGENROEN = 0x100000

	// RCC_MP_APB5ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
	// Position of SPI6EN field.
	RCC_RCC_MP_APB5ENSETR_SPI6EN_Pos = 0x0
	// Bit mask of SPI6EN field.
	RCC_RCC_MP_APB5ENSETR_SPI6EN_Msk = 0x1
	// Bit SPI6EN.
	RCC_RCC_MP_APB5ENSETR_SPI6EN = 0x1
	// Position of I2C4EN field.
	RCC_RCC_MP_APB5ENSETR_I2C4EN_Pos = 0x2
	// Bit mask of I2C4EN field.
	RCC_RCC_MP_APB5ENSETR_I2C4EN_Msk = 0x4
	// Bit I2C4EN.
	RCC_RCC_MP_APB5ENSETR_I2C4EN = 0x4
	// Position of I2C6EN field.
	RCC_RCC_MP_APB5ENSETR_I2C6EN_Pos = 0x3
	// Bit mask of I2C6EN field.
	RCC_RCC_MP_APB5ENSETR_I2C6EN_Msk = 0x8
	// Bit I2C6EN.
	RCC_RCC_MP_APB5ENSETR_I2C6EN = 0x8
	// Position of USART1EN field.
	RCC_RCC_MP_APB5ENSETR_USART1EN_Pos = 0x4
	// Bit mask of USART1EN field.
	RCC_RCC_MP_APB5ENSETR_USART1EN_Msk = 0x10
	// Bit USART1EN.
	RCC_RCC_MP_APB5ENSETR_USART1EN = 0x10
	// Position of RTCAPBEN field.
	RCC_RCC_MP_APB5ENSETR_RTCAPBEN_Pos = 0x8
	// Bit mask of RTCAPBEN field.
	RCC_RCC_MP_APB5ENSETR_RTCAPBEN_Msk = 0x100
	// Bit RTCAPBEN.
	RCC_RCC_MP_APB5ENSETR_RTCAPBEN = 0x100
	// Position of TZC1EN field.
	RCC_RCC_MP_APB5ENSETR_TZC1EN_Pos = 0xb
	// Bit mask of TZC1EN field.
	RCC_RCC_MP_APB5ENSETR_TZC1EN_Msk = 0x800
	// Bit TZC1EN.
	RCC_RCC_MP_APB5ENSETR_TZC1EN = 0x800
	// Position of TZC2EN field.
	RCC_RCC_MP_APB5ENSETR_TZC2EN_Pos = 0xc
	// Bit mask of TZC2EN field.
	RCC_RCC_MP_APB5ENSETR_TZC2EN_Msk = 0x1000
	// Bit TZC2EN.
	RCC_RCC_MP_APB5ENSETR_TZC2EN = 0x1000
	// Position of TZPCEN field.
	RCC_RCC_MP_APB5ENSETR_TZPCEN_Pos = 0xd
	// Bit mask of TZPCEN field.
	RCC_RCC_MP_APB5ENSETR_TZPCEN_Msk = 0x2000
	// Bit TZPCEN.
	RCC_RCC_MP_APB5ENSETR_TZPCEN = 0x2000
	// Position of IWDG1APBEN field.
	RCC_RCC_MP_APB5ENSETR_IWDG1APBEN_Pos = 0xf
	// Bit mask of IWDG1APBEN field.
	RCC_RCC_MP_APB5ENSETR_IWDG1APBEN_Msk = 0x8000
	// Bit IWDG1APBEN.
	RCC_RCC_MP_APB5ENSETR_IWDG1APBEN = 0x8000
	// Position of BSECEN field.
	RCC_RCC_MP_APB5ENSETR_BSECEN_Pos = 0x10
	// Bit mask of BSECEN field.
	RCC_RCC_MP_APB5ENSETR_BSECEN_Msk = 0x10000
	// Bit BSECEN.
	RCC_RCC_MP_APB5ENSETR_BSECEN = 0x10000
	// Position of STGENEN field.
	RCC_RCC_MP_APB5ENSETR_STGENEN_Pos = 0x14
	// Bit mask of STGENEN field.
	RCC_RCC_MP_APB5ENSETR_STGENEN_Msk = 0x100000
	// Bit STGENEN.
	RCC_RCC_MP_APB5ENSETR_STGENEN = 0x100000

	// RCC_MP_APB5ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
	// Position of SPI6EN field.
	RCC_RCC_MP_APB5ENCLRR_SPI6EN_Pos = 0x0
	// Bit mask of SPI6EN field.
	RCC_RCC_MP_APB5ENCLRR_SPI6EN_Msk = 0x1
	// Bit SPI6EN.
	RCC_RCC_MP_APB5ENCLRR_SPI6EN = 0x1
	// Position of I2C4EN field.
	RCC_RCC_MP_APB5ENCLRR_I2C4EN_Pos = 0x2
	// Bit mask of I2C4EN field.
	RCC_RCC_MP_APB5ENCLRR_I2C4EN_Msk = 0x4
	// Bit I2C4EN.
	RCC_RCC_MP_APB5ENCLRR_I2C4EN = 0x4
	// Position of I2C6EN field.
	RCC_RCC_MP_APB5ENCLRR_I2C6EN_Pos = 0x3
	// Bit mask of I2C6EN field.
	RCC_RCC_MP_APB5ENCLRR_I2C6EN_Msk = 0x8
	// Bit I2C6EN.
	RCC_RCC_MP_APB5ENCLRR_I2C6EN = 0x8
	// Position of USART1EN field.
	RCC_RCC_MP_APB5ENCLRR_USART1EN_Pos = 0x4
	// Bit mask of USART1EN field.
	RCC_RCC_MP_APB5ENCLRR_USART1EN_Msk = 0x10
	// Bit USART1EN.
	RCC_RCC_MP_APB5ENCLRR_USART1EN = 0x10
	// Position of RTCAPBEN field.
	RCC_RCC_MP_APB5ENCLRR_RTCAPBEN_Pos = 0x8
	// Bit mask of RTCAPBEN field.
	RCC_RCC_MP_APB5ENCLRR_RTCAPBEN_Msk = 0x100
	// Bit RTCAPBEN.
	RCC_RCC_MP_APB5ENCLRR_RTCAPBEN = 0x100
	// Position of TZC1EN field.
	RCC_RCC_MP_APB5ENCLRR_TZC1EN_Pos = 0xb
	// Bit mask of TZC1EN field.
	RCC_RCC_MP_APB5ENCLRR_TZC1EN_Msk = 0x800
	// Bit TZC1EN.
	RCC_RCC_MP_APB5ENCLRR_TZC1EN = 0x800
	// Position of TZC2EN field.
	RCC_RCC_MP_APB5ENCLRR_TZC2EN_Pos = 0xc
	// Bit mask of TZC2EN field.
	RCC_RCC_MP_APB5ENCLRR_TZC2EN_Msk = 0x1000
	// Bit TZC2EN.
	RCC_RCC_MP_APB5ENCLRR_TZC2EN = 0x1000
	// Position of TZPCEN field.
	RCC_RCC_MP_APB5ENCLRR_TZPCEN_Pos = 0xd
	// Bit mask of TZPCEN field.
	RCC_RCC_MP_APB5ENCLRR_TZPCEN_Msk = 0x2000
	// Bit TZPCEN.
	RCC_RCC_MP_APB5ENCLRR_TZPCEN = 0x2000
	// Position of IWDG1APBEN field.
	RCC_RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos = 0xf
	// Bit mask of IWDG1APBEN field.
	RCC_RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk = 0x8000
	// Bit IWDG1APBEN.
	RCC_RCC_MP_APB5ENCLRR_IWDG1APBEN = 0x8000
	// Position of BSECEN field.
	RCC_RCC_MP_APB5ENCLRR_BSECEN_Pos = 0x10
	// Bit mask of BSECEN field.
	RCC_RCC_MP_APB5ENCLRR_BSECEN_Msk = 0x10000
	// Bit BSECEN.
	RCC_RCC_MP_APB5ENCLRR_BSECEN = 0x10000
	// Position of STGENEN field.
	RCC_RCC_MP_APB5ENCLRR_STGENEN_Pos = 0x14
	// Bit mask of STGENEN field.
	RCC_RCC_MP_APB5ENCLRR_STGENEN_Msk = 0x100000
	// Bit STGENEN.
	RCC_RCC_MP_APB5ENCLRR_STGENEN = 0x100000

	// RCC_MP_AHB5ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZEN field.
	RCC_RCC_MP_AHB5ENSETR_GPIOZEN_Pos = 0x0
	// Bit mask of GPIOZEN field.
	RCC_RCC_MP_AHB5ENSETR_GPIOZEN_Msk = 0x1
	// Bit GPIOZEN.
	RCC_RCC_MP_AHB5ENSETR_GPIOZEN = 0x1
	// Position of CRYP1EN field.
	RCC_RCC_MP_AHB5ENSETR_CRYP1EN_Pos = 0x4
	// Bit mask of CRYP1EN field.
	RCC_RCC_MP_AHB5ENSETR_CRYP1EN_Msk = 0x10
	// Bit CRYP1EN.
	RCC_RCC_MP_AHB5ENSETR_CRYP1EN = 0x10
	// Position of HASH1EN field.
	RCC_RCC_MP_AHB5ENSETR_HASH1EN_Pos = 0x5
	// Bit mask of HASH1EN field.
	RCC_RCC_MP_AHB5ENSETR_HASH1EN_Msk = 0x20
	// Bit HASH1EN.
	RCC_RCC_MP_AHB5ENSETR_HASH1EN = 0x20
	// Position of RNG1EN field.
	RCC_RCC_MP_AHB5ENSETR_RNG1EN_Pos = 0x6
	// Bit mask of RNG1EN field.
	RCC_RCC_MP_AHB5ENSETR_RNG1EN_Msk = 0x40
	// Bit RNG1EN.
	RCC_RCC_MP_AHB5ENSETR_RNG1EN = 0x40
	// Position of BKPSRAMEN field.
	RCC_RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos = 0x8
	// Bit mask of BKPSRAMEN field.
	RCC_RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk = 0x100
	// Bit BKPSRAMEN.
	RCC_RCC_MP_AHB5ENSETR_BKPSRAMEN = 0x100
	// Position of AXIMCEN field.
	RCC_RCC_MP_AHB5ENSETR_AXIMCEN_Pos = 0x10
	// Bit mask of AXIMCEN field.
	RCC_RCC_MP_AHB5ENSETR_AXIMCEN_Msk = 0x10000
	// Bit AXIMCEN.
	RCC_RCC_MP_AHB5ENSETR_AXIMCEN = 0x10000

	// RCC_MP_AHB5ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZEN field.
	RCC_RCC_MP_AHB5ENCLRR_GPIOZEN_Pos = 0x0
	// Bit mask of GPIOZEN field.
	RCC_RCC_MP_AHB5ENCLRR_GPIOZEN_Msk = 0x1
	// Bit GPIOZEN.
	RCC_RCC_MP_AHB5ENCLRR_GPIOZEN = 0x1
	// Position of CRYP1EN field.
	RCC_RCC_MP_AHB5ENCLRR_CRYP1EN_Pos = 0x4
	// Bit mask of CRYP1EN field.
	RCC_RCC_MP_AHB5ENCLRR_CRYP1EN_Msk = 0x10
	// Bit CRYP1EN.
	RCC_RCC_MP_AHB5ENCLRR_CRYP1EN = 0x10
	// Position of HASH1EN field.
	RCC_RCC_MP_AHB5ENCLRR_HASH1EN_Pos = 0x5
	// Bit mask of HASH1EN field.
	RCC_RCC_MP_AHB5ENCLRR_HASH1EN_Msk = 0x20
	// Bit HASH1EN.
	RCC_RCC_MP_AHB5ENCLRR_HASH1EN = 0x20
	// Position of RNG1EN field.
	RCC_RCC_MP_AHB5ENCLRR_RNG1EN_Pos = 0x6
	// Bit mask of RNG1EN field.
	RCC_RCC_MP_AHB5ENCLRR_RNG1EN_Msk = 0x40
	// Bit RNG1EN.
	RCC_RCC_MP_AHB5ENCLRR_RNG1EN = 0x40
	// Position of BKPSRAMEN field.
	RCC_RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos = 0x8
	// Bit mask of BKPSRAMEN field.
	RCC_RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk = 0x100
	// Bit BKPSRAMEN.
	RCC_RCC_MP_AHB5ENCLRR_BKPSRAMEN = 0x100
	// Position of AXIMCEN field.
	RCC_RCC_MP_AHB5ENCLRR_AXIMCEN_Pos = 0x10
	// Bit mask of AXIMCEN field.
	RCC_RCC_MP_AHB5ENCLRR_AXIMCEN_Msk = 0x10000
	// Bit AXIMCEN.
	RCC_RCC_MP_AHB5ENCLRR_AXIMCEN = 0x10000

	// RCC_MP_AHB6ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
	// Position of MDMAEN field.
	RCC_RCC_MP_AHB6ENSETR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_RCC_MP_AHB6ENSETR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_RCC_MP_AHB6ENSETR_MDMAEN = 0x1
	// Position of GPUEN field.
	RCC_RCC_MP_AHB6ENSETR_GPUEN_Pos = 0x5
	// Bit mask of GPUEN field.
	RCC_RCC_MP_AHB6ENSETR_GPUEN_Msk = 0x20
	// Bit GPUEN.
	RCC_RCC_MP_AHB6ENSETR_GPUEN = 0x20
	// Position of ETHCKEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHCKEN_Pos = 0x7
	// Bit mask of ETHCKEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHCKEN_Msk = 0x80
	// Bit ETHCKEN.
	RCC_RCC_MP_AHB6ENSETR_ETHCKEN = 0x80
	// Position of ETHTXEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHTXEN_Pos = 0x8
	// Bit mask of ETHTXEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHTXEN_Msk = 0x100
	// Bit ETHTXEN.
	RCC_RCC_MP_AHB6ENSETR_ETHTXEN = 0x100
	// Position of ETHRXEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHRXEN_Pos = 0x9
	// Bit mask of ETHRXEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHRXEN_Msk = 0x200
	// Bit ETHRXEN.
	RCC_RCC_MP_AHB6ENSETR_ETHRXEN = 0x200
	// Position of ETHMACEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHMACEN_Pos = 0xa
	// Bit mask of ETHMACEN field.
	RCC_RCC_MP_AHB6ENSETR_ETHMACEN_Msk = 0x400
	// Bit ETHMACEN.
	RCC_RCC_MP_AHB6ENSETR_ETHMACEN = 0x400
	// Position of FMCEN field.
	RCC_RCC_MP_AHB6ENSETR_FMCEN_Pos = 0xc
	// Bit mask of FMCEN field.
	RCC_RCC_MP_AHB6ENSETR_FMCEN_Msk = 0x1000
	// Bit FMCEN.
	RCC_RCC_MP_AHB6ENSETR_FMCEN = 0x1000
	// Position of QSPIEN field.
	RCC_RCC_MP_AHB6ENSETR_QSPIEN_Pos = 0xe
	// Bit mask of QSPIEN field.
	RCC_RCC_MP_AHB6ENSETR_QSPIEN_Msk = 0x4000
	// Bit QSPIEN.
	RCC_RCC_MP_AHB6ENSETR_QSPIEN = 0x4000
	// Position of SDMMC1EN field.
	RCC_RCC_MP_AHB6ENSETR_SDMMC1EN_Pos = 0x10
	// Bit mask of SDMMC1EN field.
	RCC_RCC_MP_AHB6ENSETR_SDMMC1EN_Msk = 0x10000
	// Bit SDMMC1EN.
	RCC_RCC_MP_AHB6ENSETR_SDMMC1EN = 0x10000
	// Position of SDMMC2EN field.
	RCC_RCC_MP_AHB6ENSETR_SDMMC2EN_Pos = 0x11
	// Bit mask of SDMMC2EN field.
	RCC_RCC_MP_AHB6ENSETR_SDMMC2EN_Msk = 0x20000
	// Bit SDMMC2EN.
	RCC_RCC_MP_AHB6ENSETR_SDMMC2EN = 0x20000
	// Position of CRC1EN field.
	RCC_RCC_MP_AHB6ENSETR_CRC1EN_Pos = 0x14
	// Bit mask of CRC1EN field.
	RCC_RCC_MP_AHB6ENSETR_CRC1EN_Msk = 0x100000
	// Bit CRC1EN.
	RCC_RCC_MP_AHB6ENSETR_CRC1EN = 0x100000
	// Position of USBHEN field.
	RCC_RCC_MP_AHB6ENSETR_USBHEN_Pos = 0x18
	// Bit mask of USBHEN field.
	RCC_RCC_MP_AHB6ENSETR_USBHEN_Msk = 0x1000000
	// Bit USBHEN.
	RCC_RCC_MP_AHB6ENSETR_USBHEN = 0x1000000

	// RCC_MP_AHB6ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
	// Position of MDMAEN field.
	RCC_RCC_MP_AHB6ENCLRR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_RCC_MP_AHB6ENCLRR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_RCC_MP_AHB6ENCLRR_MDMAEN = 0x1
	// Position of GPUEN field.
	RCC_RCC_MP_AHB6ENCLRR_GPUEN_Pos = 0x5
	// Bit mask of GPUEN field.
	RCC_RCC_MP_AHB6ENCLRR_GPUEN_Msk = 0x20
	// Bit GPUEN.
	RCC_RCC_MP_AHB6ENCLRR_GPUEN = 0x20
	// Position of ETHCKEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHCKEN_Pos = 0x7
	// Bit mask of ETHCKEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHCKEN_Msk = 0x80
	// Bit ETHCKEN.
	RCC_RCC_MP_AHB6ENCLRR_ETHCKEN = 0x80
	// Position of ETHTXEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHTXEN_Pos = 0x8
	// Bit mask of ETHTXEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHTXEN_Msk = 0x100
	// Bit ETHTXEN.
	RCC_RCC_MP_AHB6ENCLRR_ETHTXEN = 0x100
	// Position of ETHRXEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHRXEN_Pos = 0x9
	// Bit mask of ETHRXEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHRXEN_Msk = 0x200
	// Bit ETHRXEN.
	RCC_RCC_MP_AHB6ENCLRR_ETHRXEN = 0x200
	// Position of ETHMACEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHMACEN_Pos = 0xa
	// Bit mask of ETHMACEN field.
	RCC_RCC_MP_AHB6ENCLRR_ETHMACEN_Msk = 0x400
	// Bit ETHMACEN.
	RCC_RCC_MP_AHB6ENCLRR_ETHMACEN = 0x400
	// Position of FMCEN field.
	RCC_RCC_MP_AHB6ENCLRR_FMCEN_Pos = 0xc
	// Bit mask of FMCEN field.
	RCC_RCC_MP_AHB6ENCLRR_FMCEN_Msk = 0x1000
	// Bit FMCEN.
	RCC_RCC_MP_AHB6ENCLRR_FMCEN = 0x1000
	// Position of QSPIEN field.
	RCC_RCC_MP_AHB6ENCLRR_QSPIEN_Pos = 0xe
	// Bit mask of QSPIEN field.
	RCC_RCC_MP_AHB6ENCLRR_QSPIEN_Msk = 0x4000
	// Bit QSPIEN.
	RCC_RCC_MP_AHB6ENCLRR_QSPIEN = 0x4000
	// Position of SDMMC1EN field.
	RCC_RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos = 0x10
	// Bit mask of SDMMC1EN field.
	RCC_RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk = 0x10000
	// Bit SDMMC1EN.
	RCC_RCC_MP_AHB6ENCLRR_SDMMC1EN = 0x10000
	// Position of SDMMC2EN field.
	RCC_RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos = 0x11
	// Bit mask of SDMMC2EN field.
	RCC_RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk = 0x20000
	// Bit SDMMC2EN.
	RCC_RCC_MP_AHB6ENCLRR_SDMMC2EN = 0x20000
	// Position of CRC1EN field.
	RCC_RCC_MP_AHB6ENCLRR_CRC1EN_Pos = 0x14
	// Bit mask of CRC1EN field.
	RCC_RCC_MP_AHB6ENCLRR_CRC1EN_Msk = 0x100000
	// Bit CRC1EN.
	RCC_RCC_MP_AHB6ENCLRR_CRC1EN = 0x100000
	// Position of USBHEN field.
	RCC_RCC_MP_AHB6ENCLRR_USBHEN_Pos = 0x18
	// Bit mask of USBHEN field.
	RCC_RCC_MP_AHB6ENCLRR_USBHEN_Msk = 0x1000000
	// Bit USBHEN.
	RCC_RCC_MP_AHB6ENCLRR_USBHEN = 0x1000000

	// RCC_MP_TZAHB6ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
	// Position of MDMAEN field.
	RCC_RCC_MP_TZAHB6ENSETR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_RCC_MP_TZAHB6ENSETR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_RCC_MP_TZAHB6ENSETR_MDMAEN = 0x1

	// RCC_MP_TZAHB6ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
	// Position of MDMAEN field.
	RCC_RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_RCC_MP_TZAHB6ENCLRR_MDMAEN = 0x1

	// RCC_MC_APB4ENSETR: This register is used to set the peripheral clock enable bit
	// Position of LTDCEN field.
	RCC_RCC_MC_APB4ENSETR_LTDCEN_Pos = 0x0
	// Bit mask of LTDCEN field.
	RCC_RCC_MC_APB4ENSETR_LTDCEN_Msk = 0x1
	// Bit LTDCEN.
	RCC_RCC_MC_APB4ENSETR_LTDCEN = 0x1
	// Position of DSIEN field.
	RCC_RCC_MC_APB4ENSETR_DSIEN_Pos = 0x4
	// Bit mask of DSIEN field.
	RCC_RCC_MC_APB4ENSETR_DSIEN_Msk = 0x10
	// Bit DSIEN.
	RCC_RCC_MC_APB4ENSETR_DSIEN = 0x10
	// Position of DDRPERFMEN field.
	RCC_RCC_MC_APB4ENSETR_DDRPERFMEN_Pos = 0x8
	// Bit mask of DDRPERFMEN field.
	RCC_RCC_MC_APB4ENSETR_DDRPERFMEN_Msk = 0x100
	// Bit DDRPERFMEN.
	RCC_RCC_MC_APB4ENSETR_DDRPERFMEN = 0x100
	// Position of USBPHYEN field.
	RCC_RCC_MC_APB4ENSETR_USBPHYEN_Pos = 0x10
	// Bit mask of USBPHYEN field.
	RCC_RCC_MC_APB4ENSETR_USBPHYEN_Msk = 0x10000
	// Bit USBPHYEN.
	RCC_RCC_MC_APB4ENSETR_USBPHYEN = 0x10000
	// Position of STGENROEN field.
	RCC_RCC_MC_APB4ENSETR_STGENROEN_Pos = 0x14
	// Bit mask of STGENROEN field.
	RCC_RCC_MC_APB4ENSETR_STGENROEN_Msk = 0x100000
	// Bit STGENROEN.
	RCC_RCC_MC_APB4ENSETR_STGENROEN = 0x100000

	// RCC_MC_APB4ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of LTDCEN field.
	RCC_RCC_MC_APB4ENCLRR_LTDCEN_Pos = 0x0
	// Bit mask of LTDCEN field.
	RCC_RCC_MC_APB4ENCLRR_LTDCEN_Msk = 0x1
	// Bit LTDCEN.
	RCC_RCC_MC_APB4ENCLRR_LTDCEN = 0x1
	// Position of DSIEN field.
	RCC_RCC_MC_APB4ENCLRR_DSIEN_Pos = 0x4
	// Bit mask of DSIEN field.
	RCC_RCC_MC_APB4ENCLRR_DSIEN_Msk = 0x10
	// Bit DSIEN.
	RCC_RCC_MC_APB4ENCLRR_DSIEN = 0x10
	// Position of DDRPERFMEN field.
	RCC_RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos = 0x8
	// Bit mask of DDRPERFMEN field.
	RCC_RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk = 0x100
	// Bit DDRPERFMEN.
	RCC_RCC_MC_APB4ENCLRR_DDRPERFMEN = 0x100
	// Position of USBPHYEN field.
	RCC_RCC_MC_APB4ENCLRR_USBPHYEN_Pos = 0x10
	// Bit mask of USBPHYEN field.
	RCC_RCC_MC_APB4ENCLRR_USBPHYEN_Msk = 0x10000
	// Bit USBPHYEN.
	RCC_RCC_MC_APB4ENCLRR_USBPHYEN = 0x10000
	// Position of STGENROEN field.
	RCC_RCC_MC_APB4ENCLRR_STGENROEN_Pos = 0x14
	// Bit mask of STGENROEN field.
	RCC_RCC_MC_APB4ENCLRR_STGENROEN_Msk = 0x100000
	// Bit STGENROEN.
	RCC_RCC_MC_APB4ENCLRR_STGENROEN = 0x100000

	// RCC_MC_APB5ENSETR: This register is used to set the peripheral clock enable bit
	// Position of SPI6EN field.
	RCC_RCC_MC_APB5ENSETR_SPI6EN_Pos = 0x0
	// Bit mask of SPI6EN field.
	RCC_RCC_MC_APB5ENSETR_SPI6EN_Msk = 0x1
	// Bit SPI6EN.
	RCC_RCC_MC_APB5ENSETR_SPI6EN = 0x1
	// Position of I2C4EN field.
	RCC_RCC_MC_APB5ENSETR_I2C4EN_Pos = 0x2
	// Bit mask of I2C4EN field.
	RCC_RCC_MC_APB5ENSETR_I2C4EN_Msk = 0x4
	// Bit I2C4EN.
	RCC_RCC_MC_APB5ENSETR_I2C4EN = 0x4
	// Position of I2C6EN field.
	RCC_RCC_MC_APB5ENSETR_I2C6EN_Pos = 0x3
	// Bit mask of I2C6EN field.
	RCC_RCC_MC_APB5ENSETR_I2C6EN_Msk = 0x8
	// Bit I2C6EN.
	RCC_RCC_MC_APB5ENSETR_I2C6EN = 0x8
	// Position of USART1EN field.
	RCC_RCC_MC_APB5ENSETR_USART1EN_Pos = 0x4
	// Bit mask of USART1EN field.
	RCC_RCC_MC_APB5ENSETR_USART1EN_Msk = 0x10
	// Bit USART1EN.
	RCC_RCC_MC_APB5ENSETR_USART1EN = 0x10
	// Position of RTCAPBEN field.
	RCC_RCC_MC_APB5ENSETR_RTCAPBEN_Pos = 0x8
	// Bit mask of RTCAPBEN field.
	RCC_RCC_MC_APB5ENSETR_RTCAPBEN_Msk = 0x100
	// Bit RTCAPBEN.
	RCC_RCC_MC_APB5ENSETR_RTCAPBEN = 0x100
	// Position of TZC1EN field.
	RCC_RCC_MC_APB5ENSETR_TZC1EN_Pos = 0xb
	// Bit mask of TZC1EN field.
	RCC_RCC_MC_APB5ENSETR_TZC1EN_Msk = 0x800
	// Bit TZC1EN.
	RCC_RCC_MC_APB5ENSETR_TZC1EN = 0x800
	// Position of TZC2EN field.
	RCC_RCC_MC_APB5ENSETR_TZC2EN_Pos = 0xc
	// Bit mask of TZC2EN field.
	RCC_RCC_MC_APB5ENSETR_TZC2EN_Msk = 0x1000
	// Bit TZC2EN.
	RCC_RCC_MC_APB5ENSETR_TZC2EN = 0x1000
	// Position of TZPCEN field.
	RCC_RCC_MC_APB5ENSETR_TZPCEN_Pos = 0xd
	// Bit mask of TZPCEN field.
	RCC_RCC_MC_APB5ENSETR_TZPCEN_Msk = 0x2000
	// Bit TZPCEN.
	RCC_RCC_MC_APB5ENSETR_TZPCEN = 0x2000
	// Position of BSECEN field.
	RCC_RCC_MC_APB5ENSETR_BSECEN_Pos = 0x10
	// Bit mask of BSECEN field.
	RCC_RCC_MC_APB5ENSETR_BSECEN_Msk = 0x10000
	// Bit BSECEN.
	RCC_RCC_MC_APB5ENSETR_BSECEN = 0x10000
	// Position of STGENEN field.
	RCC_RCC_MC_APB5ENSETR_STGENEN_Pos = 0x14
	// Bit mask of STGENEN field.
	RCC_RCC_MC_APB5ENSETR_STGENEN_Msk = 0x100000
	// Bit STGENEN.
	RCC_RCC_MC_APB5ENSETR_STGENEN = 0x100000

	// RCC_MC_APB5ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of SPI6EN field.
	RCC_RCC_MC_APB5ENCLRR_SPI6EN_Pos = 0x0
	// Bit mask of SPI6EN field.
	RCC_RCC_MC_APB5ENCLRR_SPI6EN_Msk = 0x1
	// Bit SPI6EN.
	RCC_RCC_MC_APB5ENCLRR_SPI6EN = 0x1
	// Position of I2C4EN field.
	RCC_RCC_MC_APB5ENCLRR_I2C4EN_Pos = 0x2
	// Bit mask of I2C4EN field.
	RCC_RCC_MC_APB5ENCLRR_I2C4EN_Msk = 0x4
	// Bit I2C4EN.
	RCC_RCC_MC_APB5ENCLRR_I2C4EN = 0x4
	// Position of I2C6EN field.
	RCC_RCC_MC_APB5ENCLRR_I2C6EN_Pos = 0x3
	// Bit mask of I2C6EN field.
	RCC_RCC_MC_APB5ENCLRR_I2C6EN_Msk = 0x8
	// Bit I2C6EN.
	RCC_RCC_MC_APB5ENCLRR_I2C6EN = 0x8
	// Position of USART1EN field.
	RCC_RCC_MC_APB5ENCLRR_USART1EN_Pos = 0x4
	// Bit mask of USART1EN field.
	RCC_RCC_MC_APB5ENCLRR_USART1EN_Msk = 0x10
	// Bit USART1EN.
	RCC_RCC_MC_APB5ENCLRR_USART1EN = 0x10
	// Position of RTCAPBEN field.
	RCC_RCC_MC_APB5ENCLRR_RTCAPBEN_Pos = 0x8
	// Bit mask of RTCAPBEN field.
	RCC_RCC_MC_APB5ENCLRR_RTCAPBEN_Msk = 0x100
	// Bit RTCAPBEN.
	RCC_RCC_MC_APB5ENCLRR_RTCAPBEN = 0x100
	// Position of TZC1EN field.
	RCC_RCC_MC_APB5ENCLRR_TZC1EN_Pos = 0xb
	// Bit mask of TZC1EN field.
	RCC_RCC_MC_APB5ENCLRR_TZC1EN_Msk = 0x800
	// Bit TZC1EN.
	RCC_RCC_MC_APB5ENCLRR_TZC1EN = 0x800
	// Position of TZC2EN field.
	RCC_RCC_MC_APB5ENCLRR_TZC2EN_Pos = 0xc
	// Bit mask of TZC2EN field.
	RCC_RCC_MC_APB5ENCLRR_TZC2EN_Msk = 0x1000
	// Bit TZC2EN.
	RCC_RCC_MC_APB5ENCLRR_TZC2EN = 0x1000
	// Position of TZPCEN field.
	RCC_RCC_MC_APB5ENCLRR_TZPCEN_Pos = 0xd
	// Bit mask of TZPCEN field.
	RCC_RCC_MC_APB5ENCLRR_TZPCEN_Msk = 0x2000
	// Bit TZPCEN.
	RCC_RCC_MC_APB5ENCLRR_TZPCEN = 0x2000
	// Position of BSECEN field.
	RCC_RCC_MC_APB5ENCLRR_BSECEN_Pos = 0x10
	// Bit mask of BSECEN field.
	RCC_RCC_MC_APB5ENCLRR_BSECEN_Msk = 0x10000
	// Bit BSECEN.
	RCC_RCC_MC_APB5ENCLRR_BSECEN = 0x10000
	// Position of STGENEN field.
	RCC_RCC_MC_APB5ENCLRR_STGENEN_Pos = 0x14
	// Bit mask of STGENEN field.
	RCC_RCC_MC_APB5ENCLRR_STGENEN_Msk = 0x100000
	// Bit STGENEN.
	RCC_RCC_MC_APB5ENCLRR_STGENEN = 0x100000

	// RCC_MC_AHB5ENSETR: This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZEN field.
	RCC_RCC_MC_AHB5ENSETR_GPIOZEN_Pos = 0x0
	// Bit mask of GPIOZEN field.
	RCC_RCC_MC_AHB5ENSETR_GPIOZEN_Msk = 0x1
	// Bit GPIOZEN.
	RCC_RCC_MC_AHB5ENSETR_GPIOZEN = 0x1
	// Position of CRYP1EN field.
	RCC_RCC_MC_AHB5ENSETR_CRYP1EN_Pos = 0x4
	// Bit mask of CRYP1EN field.
	RCC_RCC_MC_AHB5ENSETR_CRYP1EN_Msk = 0x10
	// Bit CRYP1EN.
	RCC_RCC_MC_AHB5ENSETR_CRYP1EN = 0x10
	// Position of HASH1EN field.
	RCC_RCC_MC_AHB5ENSETR_HASH1EN_Pos = 0x5
	// Bit mask of HASH1EN field.
	RCC_RCC_MC_AHB5ENSETR_HASH1EN_Msk = 0x20
	// Bit HASH1EN.
	RCC_RCC_MC_AHB5ENSETR_HASH1EN = 0x20
	// Position of RNG1EN field.
	RCC_RCC_MC_AHB5ENSETR_RNG1EN_Pos = 0x6
	// Bit mask of RNG1EN field.
	RCC_RCC_MC_AHB5ENSETR_RNG1EN_Msk = 0x40
	// Bit RNG1EN.
	RCC_RCC_MC_AHB5ENSETR_RNG1EN = 0x40
	// Position of BKPSRAMEN field.
	RCC_RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos = 0x8
	// Bit mask of BKPSRAMEN field.
	RCC_RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk = 0x100
	// Bit BKPSRAMEN.
	RCC_RCC_MC_AHB5ENSETR_BKPSRAMEN = 0x100

	// RCC_MC_AHB5ENCLRR: This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZEN field.
	RCC_RCC_MC_AHB5ENCLRR_GPIOZEN_Pos = 0x0
	// Bit mask of GPIOZEN field.
	RCC_RCC_MC_AHB5ENCLRR_GPIOZEN_Msk = 0x1
	// Bit GPIOZEN.
	RCC_RCC_MC_AHB5ENCLRR_GPIOZEN = 0x1
	// Position of CRYP1EN field.
	RCC_RCC_MC_AHB5ENCLRR_CRYP1EN_Pos = 0x4
	// Bit mask of CRYP1EN field.
	RCC_RCC_MC_AHB5ENCLRR_CRYP1EN_Msk = 0x10
	// Bit CRYP1EN.
	RCC_RCC_MC_AHB5ENCLRR_CRYP1EN = 0x10
	// Position of HASH1EN field.
	RCC_RCC_MC_AHB5ENCLRR_HASH1EN_Pos = 0x5
	// Bit mask of HASH1EN field.
	RCC_RCC_MC_AHB5ENCLRR_HASH1EN_Msk = 0x20
	// Bit HASH1EN.
	RCC_RCC_MC_AHB5ENCLRR_HASH1EN = 0x20
	// Position of RNG1EN field.
	RCC_RCC_MC_AHB5ENCLRR_RNG1EN_Pos = 0x6
	// Bit mask of RNG1EN field.
	RCC_RCC_MC_AHB5ENCLRR_RNG1EN_Msk = 0x40
	// Bit RNG1EN.
	RCC_RCC_MC_AHB5ENCLRR_RNG1EN = 0x40
	// Position of BKPSRAMEN field.
	RCC_RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos = 0x8
	// Bit mask of BKPSRAMEN field.
	RCC_RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk = 0x100
	// Bit BKPSRAMEN.
	RCC_RCC_MC_AHB5ENCLRR_BKPSRAMEN = 0x100

	// RCC_MC_AHB6ENSETR: This register is used to set the peripheral clock enable bit
	// Position of MDMAEN field.
	RCC_RCC_MC_AHB6ENSETR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_RCC_MC_AHB6ENSETR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_RCC_MC_AHB6ENSETR_MDMAEN = 0x1
	// Position of GPUEN field.
	RCC_RCC_MC_AHB6ENSETR_GPUEN_Pos = 0x5
	// Bit mask of GPUEN field.
	RCC_RCC_MC_AHB6ENSETR_GPUEN_Msk = 0x20
	// Bit GPUEN.
	RCC_RCC_MC_AHB6ENSETR_GPUEN = 0x20
	// Position of ETHCKEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHCKEN_Pos = 0x7
	// Bit mask of ETHCKEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHCKEN_Msk = 0x80
	// Bit ETHCKEN.
	RCC_RCC_MC_AHB6ENSETR_ETHCKEN = 0x80
	// Position of ETHTXEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHTXEN_Pos = 0x8
	// Bit mask of ETHTXEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHTXEN_Msk = 0x100
	// Bit ETHTXEN.
	RCC_RCC_MC_AHB6ENSETR_ETHTXEN = 0x100
	// Position of ETHRXEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHRXEN_Pos = 0x9
	// Bit mask of ETHRXEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHRXEN_Msk = 0x200
	// Bit ETHRXEN.
	RCC_RCC_MC_AHB6ENSETR_ETHRXEN = 0x200
	// Position of ETHMACEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHMACEN_Pos = 0xa
	// Bit mask of ETHMACEN field.
	RCC_RCC_MC_AHB6ENSETR_ETHMACEN_Msk = 0x400
	// Bit ETHMACEN.
	RCC_RCC_MC_AHB6ENSETR_ETHMACEN = 0x400
	// Position of FMCEN field.
	RCC_RCC_MC_AHB6ENSETR_FMCEN_Pos = 0xc
	// Bit mask of FMCEN field.
	RCC_RCC_MC_AHB6ENSETR_FMCEN_Msk = 0x1000
	// Bit FMCEN.
	RCC_RCC_MC_AHB6ENSETR_FMCEN = 0x1000
	// Position of QSPIEN field.
	RCC_RCC_MC_AHB6ENSETR_QSPIEN_Pos = 0xe
	// Bit mask of QSPIEN field.
	RCC_RCC_MC_AHB6ENSETR_QSPIEN_Msk = 0x4000
	// Bit QSPIEN.
	RCC_RCC_MC_AHB6ENSETR_QSPIEN = 0x4000
	// Position of SDMMC1EN field.
	RCC_RCC_MC_AHB6ENSETR_SDMMC1EN_Pos = 0x10
	// Bit mask of SDMMC1EN field.
	RCC_RCC_MC_AHB6ENSETR_SDMMC1EN_Msk = 0x10000
	// Bit SDMMC1EN.
	RCC_RCC_MC_AHB6ENSETR_SDMMC1EN = 0x10000
	// Position of SDMMC2EN field.
	RCC_RCC_MC_AHB6ENSETR_SDMMC2EN_Pos = 0x11
	// Bit mask of SDMMC2EN field.
	RCC_RCC_MC_AHB6ENSETR_SDMMC2EN_Msk = 0x20000
	// Bit SDMMC2EN.
	RCC_RCC_MC_AHB6ENSETR_SDMMC2EN = 0x20000
	// Position of CRC1EN field.
	RCC_RCC_MC_AHB6ENSETR_CRC1EN_Pos = 0x14
	// Bit mask of CRC1EN field.
	RCC_RCC_MC_AHB6ENSETR_CRC1EN_Msk = 0x100000
	// Bit CRC1EN.
	RCC_RCC_MC_AHB6ENSETR_CRC1EN = 0x100000
	// Position of USBHEN field.
	RCC_RCC_MC_AHB6ENSETR_USBHEN_Pos = 0x18
	// Bit mask of USBHEN field.
	RCC_RCC_MC_AHB6ENSETR_USBHEN_Msk = 0x1000000
	// Bit USBHEN.
	RCC_RCC_MC_AHB6ENSETR_USBHEN = 0x1000000

	// RCC_MC_AHB6ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of MDMAEN field.
	RCC_RCC_MC_AHB6ENCLRR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_RCC_MC_AHB6ENCLRR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_RCC_MC_AHB6ENCLRR_MDMAEN = 0x1
	// Position of GPUEN field.
	RCC_RCC_MC_AHB6ENCLRR_GPUEN_Pos = 0x5
	// Bit mask of GPUEN field.
	RCC_RCC_MC_AHB6ENCLRR_GPUEN_Msk = 0x20
	// Bit GPUEN.
	RCC_RCC_MC_AHB6ENCLRR_GPUEN = 0x20
	// Position of ETHCKEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHCKEN_Pos = 0x7
	// Bit mask of ETHCKEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHCKEN_Msk = 0x80
	// Bit ETHCKEN.
	RCC_RCC_MC_AHB6ENCLRR_ETHCKEN = 0x80
	// Position of ETHTXEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHTXEN_Pos = 0x8
	// Bit mask of ETHTXEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHTXEN_Msk = 0x100
	// Bit ETHTXEN.
	RCC_RCC_MC_AHB6ENCLRR_ETHTXEN = 0x100
	// Position of ETHRXEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHRXEN_Pos = 0x9
	// Bit mask of ETHRXEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHRXEN_Msk = 0x200
	// Bit ETHRXEN.
	RCC_RCC_MC_AHB6ENCLRR_ETHRXEN = 0x200
	// Position of ETHMACEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHMACEN_Pos = 0xa
	// Bit mask of ETHMACEN field.
	RCC_RCC_MC_AHB6ENCLRR_ETHMACEN_Msk = 0x400
	// Bit ETHMACEN.
	RCC_RCC_MC_AHB6ENCLRR_ETHMACEN = 0x400
	// Position of FMCEN field.
	RCC_RCC_MC_AHB6ENCLRR_FMCEN_Pos = 0xc
	// Bit mask of FMCEN field.
	RCC_RCC_MC_AHB6ENCLRR_FMCEN_Msk = 0x1000
	// Bit FMCEN.
	RCC_RCC_MC_AHB6ENCLRR_FMCEN = 0x1000
	// Position of QSPIEN field.
	RCC_RCC_MC_AHB6ENCLRR_QSPIEN_Pos = 0xe
	// Bit mask of QSPIEN field.
	RCC_RCC_MC_AHB6ENCLRR_QSPIEN_Msk = 0x4000
	// Bit QSPIEN.
	RCC_RCC_MC_AHB6ENCLRR_QSPIEN = 0x4000
	// Position of SDMMC1EN field.
	RCC_RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos = 0x10
	// Bit mask of SDMMC1EN field.
	RCC_RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk = 0x10000
	// Bit SDMMC1EN.
	RCC_RCC_MC_AHB6ENCLRR_SDMMC1EN = 0x10000
	// Position of SDMMC2EN field.
	RCC_RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos = 0x11
	// Bit mask of SDMMC2EN field.
	RCC_RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk = 0x20000
	// Bit SDMMC2EN.
	RCC_RCC_MC_AHB6ENCLRR_SDMMC2EN = 0x20000
	// Position of CRC1EN field.
	RCC_RCC_MC_AHB6ENCLRR_CRC1EN_Pos = 0x14
	// Bit mask of CRC1EN field.
	RCC_RCC_MC_AHB6ENCLRR_CRC1EN_Msk = 0x100000
	// Bit CRC1EN.
	RCC_RCC_MC_AHB6ENCLRR_CRC1EN = 0x100000
	// Position of USBHEN field.
	RCC_RCC_MC_AHB6ENCLRR_USBHEN_Pos = 0x18
	// Bit mask of USBHEN field.
	RCC_RCC_MC_AHB6ENCLRR_USBHEN_Msk = 0x1000000
	// Bit USBHEN.
	RCC_RCC_MC_AHB6ENCLRR_USBHEN = 0x1000000

	// RCC_MP_APB4LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of LTDCLPEN field.
	RCC_RCC_MP_APB4LPENSETR_LTDCLPEN_Pos = 0x0
	// Bit mask of LTDCLPEN field.
	RCC_RCC_MP_APB4LPENSETR_LTDCLPEN_Msk = 0x1
	// Bit LTDCLPEN.
	RCC_RCC_MP_APB4LPENSETR_LTDCLPEN = 0x1
	// Position of DSILPEN field.
	RCC_RCC_MP_APB4LPENSETR_DSILPEN_Pos = 0x4
	// Bit mask of DSILPEN field.
	RCC_RCC_MP_APB4LPENSETR_DSILPEN_Msk = 0x10
	// Bit DSILPEN.
	RCC_RCC_MP_APB4LPENSETR_DSILPEN = 0x10
	// Position of DDRPERFMLPEN field.
	RCC_RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos = 0x8
	// Bit mask of DDRPERFMLPEN field.
	RCC_RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk = 0x100
	// Bit DDRPERFMLPEN.
	RCC_RCC_MP_APB4LPENSETR_DDRPERFMLPEN = 0x100
	// Position of IWDG2APBLPEN field.
	RCC_RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos = 0xf
	// Bit mask of IWDG2APBLPEN field.
	RCC_RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk = 0x8000
	// Bit IWDG2APBLPEN.
	RCC_RCC_MP_APB4LPENSETR_IWDG2APBLPEN = 0x8000
	// Position of USBPHYLPEN field.
	RCC_RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos = 0x10
	// Bit mask of USBPHYLPEN field.
	RCC_RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk = 0x10000
	// Bit USBPHYLPEN.
	RCC_RCC_MP_APB4LPENSETR_USBPHYLPEN = 0x10000
	// Position of STGENROLPEN field.
	RCC_RCC_MP_APB4LPENSETR_STGENROLPEN_Pos = 0x14
	// Bit mask of STGENROLPEN field.
	RCC_RCC_MP_APB4LPENSETR_STGENROLPEN_Msk = 0x100000
	// Bit STGENROLPEN.
	RCC_RCC_MP_APB4LPENSETR_STGENROLPEN = 0x100000
	// Position of STGENROSTPEN field.
	RCC_RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos = 0x15
	// Bit mask of STGENROSTPEN field.
	RCC_RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk = 0x200000
	// Bit STGENROSTPEN.
	RCC_RCC_MP_APB4LPENSETR_STGENROSTPEN = 0x200000

	// RCC_MP_APB4LPENCLRR: This register is used by the MCU
	// Position of LTDCLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos = 0x0
	// Bit mask of LTDCLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk = 0x1
	// Bit LTDCLPEN.
	RCC_RCC_MP_APB4LPENCLRR_LTDCLPEN = 0x1
	// Position of DSILPEN field.
	RCC_RCC_MP_APB4LPENCLRR_DSILPEN_Pos = 0x4
	// Bit mask of DSILPEN field.
	RCC_RCC_MP_APB4LPENCLRR_DSILPEN_Msk = 0x10
	// Bit DSILPEN.
	RCC_RCC_MP_APB4LPENCLRR_DSILPEN = 0x10
	// Position of DDRPERFMLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos = 0x8
	// Bit mask of DDRPERFMLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk = 0x100
	// Bit DDRPERFMLPEN.
	RCC_RCC_MP_APB4LPENCLRR_DDRPERFMLPEN = 0x100
	// Position of IWDG2APBLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos = 0xf
	// Bit mask of IWDG2APBLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk = 0x8000
	// Bit IWDG2APBLPEN.
	RCC_RCC_MP_APB4LPENCLRR_IWDG2APBLPEN = 0x8000
	// Position of USBPHYLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos = 0x10
	// Bit mask of USBPHYLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk = 0x10000
	// Bit USBPHYLPEN.
	RCC_RCC_MP_APB4LPENCLRR_USBPHYLPEN = 0x10000
	// Position of STGENROLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos = 0x14
	// Bit mask of STGENROLPEN field.
	RCC_RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk = 0x100000
	// Bit STGENROLPEN.
	RCC_RCC_MP_APB4LPENCLRR_STGENROLPEN = 0x100000
	// Position of STGENROSTPEN field.
	RCC_RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos = 0x15
	// Bit mask of STGENROSTPEN field.
	RCC_RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk = 0x200000
	// Bit STGENROSTPEN.
	RCC_RCC_MP_APB4LPENCLRR_STGENROSTPEN = 0x200000

	// RCC_MP_APB5LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
	// Position of SPI6LPEN field.
	RCC_RCC_MP_APB5LPENSETR_SPI6LPEN_Pos = 0x0
	// Bit mask of SPI6LPEN field.
	RCC_RCC_MP_APB5LPENSETR_SPI6LPEN_Msk = 0x1
	// Bit SPI6LPEN.
	RCC_RCC_MP_APB5LPENSETR_SPI6LPEN = 0x1
	// Position of I2C4LPEN field.
	RCC_RCC_MP_APB5LPENSETR_I2C4LPEN_Pos = 0x2
	// Bit mask of I2C4LPEN field.
	RCC_RCC_MP_APB5LPENSETR_I2C4LPEN_Msk = 0x4
	// Bit I2C4LPEN.
	RCC_RCC_MP_APB5LPENSETR_I2C4LPEN = 0x4
	// Position of I2C6LPEN field.
	RCC_RCC_MP_APB5LPENSETR_I2C6LPEN_Pos = 0x3
	// Bit mask of I2C6LPEN field.
	RCC_RCC_MP_APB5LPENSETR_I2C6LPEN_Msk = 0x8
	// Bit I2C6LPEN.
	RCC_RCC_MP_APB5LPENSETR_I2C6LPEN = 0x8
	// Position of USART1LPEN field.
	RCC_RCC_MP_APB5LPENSETR_USART1LPEN_Pos = 0x4
	// Bit mask of USART1LPEN field.
	RCC_RCC_MP_APB5LPENSETR_USART1LPEN_Msk = 0x10
	// Bit USART1LPEN.
	RCC_RCC_MP_APB5LPENSETR_USART1LPEN = 0x10
	// Position of RTCAPBLPEN field.
	RCC_RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos = 0x8
	// Bit mask of RTCAPBLPEN field.
	RCC_RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk = 0x100
	// Bit RTCAPBLPEN.
	RCC_RCC_MP_APB5LPENSETR_RTCAPBLPEN = 0x100
	// Position of TZC1LPEN field.
	RCC_RCC_MP_APB5LPENSETR_TZC1LPEN_Pos = 0xb
	// Bit mask of TZC1LPEN field.
	RCC_RCC_MP_APB5LPENSETR_TZC1LPEN_Msk = 0x800
	// Bit TZC1LPEN.
	RCC_RCC_MP_APB5LPENSETR_TZC1LPEN = 0x800
	// Position of TZC2LPEN field.
	RCC_RCC_MP_APB5LPENSETR_TZC2LPEN_Pos = 0xc
	// Bit mask of TZC2LPEN field.
	RCC_RCC_MP_APB5LPENSETR_TZC2LPEN_Msk = 0x1000
	// Bit TZC2LPEN.
	RCC_RCC_MP_APB5LPENSETR_TZC2LPEN = 0x1000
	// Position of TZPCLPEN field.
	RCC_RCC_MP_APB5LPENSETR_TZPCLPEN_Pos = 0xd
	// Bit mask of TZPCLPEN field.
	RCC_RCC_MP_APB5LPENSETR_TZPCLPEN_Msk = 0x2000
	// Bit TZPCLPEN.
	RCC_RCC_MP_APB5LPENSETR_TZPCLPEN = 0x2000
	// Position of IWDG1APBLPEN field.
	RCC_RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos = 0xf
	// Bit mask of IWDG1APBLPEN field.
	RCC_RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk = 0x8000
	// Bit IWDG1APBLPEN.
	RCC_RCC_MP_APB5LPENSETR_IWDG1APBLPEN = 0x8000
	// Position of BSECLPEN field.
	RCC_RCC_MP_APB5LPENSETR_BSECLPEN_Pos = 0x10
	// Bit mask of BSECLPEN field.
	RCC_RCC_MP_APB5LPENSETR_BSECLPEN_Msk = 0x10000
	// Bit BSECLPEN.
	RCC_RCC_MP_APB5LPENSETR_BSECLPEN = 0x10000
	// Position of STGENLPEN field.
	RCC_RCC_MP_APB5LPENSETR_STGENLPEN_Pos = 0x14
	// Bit mask of STGENLPEN field.
	RCC_RCC_MP_APB5LPENSETR_STGENLPEN_Msk = 0x100000
	// Bit STGENLPEN.
	RCC_RCC_MP_APB5LPENSETR_STGENLPEN = 0x100000
	// Position of STGENSTPEN field.
	RCC_RCC_MP_APB5LPENSETR_STGENSTPEN_Pos = 0x15
	// Bit mask of STGENSTPEN field.
	RCC_RCC_MP_APB5LPENSETR_STGENSTPEN_Msk = 0x200000
	// Bit STGENSTPEN.
	RCC_RCC_MP_APB5LPENSETR_STGENSTPEN = 0x200000

	// RCC_MP_APB5LPENCLRR: This register is used by the Mpu.
	// Position of SPI6LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos = 0x0
	// Bit mask of SPI6LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk = 0x1
	// Bit SPI6LPEN.
	RCC_RCC_MP_APB5LPENCLRR_SPI6LPEN = 0x1
	// Position of I2C4LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos = 0x2
	// Bit mask of I2C4LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk = 0x4
	// Bit I2C4LPEN.
	RCC_RCC_MP_APB5LPENCLRR_I2C4LPEN = 0x4
	// Position of I2C6LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos = 0x3
	// Bit mask of I2C6LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk = 0x8
	// Bit I2C6LPEN.
	RCC_RCC_MP_APB5LPENCLRR_I2C6LPEN = 0x8
	// Position of USART1LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_USART1LPEN_Pos = 0x4
	// Bit mask of USART1LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_USART1LPEN_Msk = 0x10
	// Bit USART1LPEN.
	RCC_RCC_MP_APB5LPENCLRR_USART1LPEN = 0x10
	// Position of RTCAPBLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos = 0x8
	// Bit mask of RTCAPBLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk = 0x100
	// Bit RTCAPBLPEN.
	RCC_RCC_MP_APB5LPENCLRR_RTCAPBLPEN = 0x100
	// Position of TZC1LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos = 0xb
	// Bit mask of TZC1LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk = 0x800
	// Bit TZC1LPEN.
	RCC_RCC_MP_APB5LPENCLRR_TZC1LPEN = 0x800
	// Position of TZC2LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos = 0xc
	// Bit mask of TZC2LPEN field.
	RCC_RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk = 0x1000
	// Bit TZC2LPEN.
	RCC_RCC_MP_APB5LPENCLRR_TZC2LPEN = 0x1000
	// Position of TZPCLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos = 0xd
	// Bit mask of TZPCLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk = 0x2000
	// Bit TZPCLPEN.
	RCC_RCC_MP_APB5LPENCLRR_TZPCLPEN = 0x2000
	// Position of IWDG1APBLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos = 0xf
	// Bit mask of IWDG1APBLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk = 0x8000
	// Bit IWDG1APBLPEN.
	RCC_RCC_MP_APB5LPENCLRR_IWDG1APBLPEN = 0x8000
	// Position of BSECLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_BSECLPEN_Pos = 0x10
	// Bit mask of BSECLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_BSECLPEN_Msk = 0x10000
	// Bit BSECLPEN.
	RCC_RCC_MP_APB5LPENCLRR_BSECLPEN = 0x10000
	// Position of STGENLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_STGENLPEN_Pos = 0x14
	// Bit mask of STGENLPEN field.
	RCC_RCC_MP_APB5LPENCLRR_STGENLPEN_Msk = 0x100000
	// Bit STGENLPEN.
	RCC_RCC_MP_APB5LPENCLRR_STGENLPEN = 0x100000
	// Position of STGENSTPEN field.
	RCC_RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos = 0x15
	// Bit mask of STGENSTPEN field.
	RCC_RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk = 0x200000
	// Bit STGENSTPEN.
	RCC_RCC_MP_APB5LPENCLRR_STGENSTPEN = 0x200000

	// RCC_MP_AHB5LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZLPEN field.
	RCC_RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos = 0x0
	// Bit mask of GPIOZLPEN field.
	RCC_RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk = 0x1
	// Bit GPIOZLPEN.
	RCC_RCC_MP_AHB5LPENSETR_GPIOZLPEN = 0x1
	// Position of CRYP1LPEN field.
	RCC_RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos = 0x4
	// Bit mask of CRYP1LPEN field.
	RCC_RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk = 0x10
	// Bit CRYP1LPEN.
	RCC_RCC_MP_AHB5LPENSETR_CRYP1LPEN = 0x10
	// Position of HASH1LPEN field.
	RCC_RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos = 0x5
	// Bit mask of HASH1LPEN field.
	RCC_RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk = 0x20
	// Bit HASH1LPEN.
	RCC_RCC_MP_AHB5LPENSETR_HASH1LPEN = 0x20
	// Position of RNG1LPEN field.
	RCC_RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos = 0x6
	// Bit mask of RNG1LPEN field.
	RCC_RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk = 0x40
	// Bit RNG1LPEN.
	RCC_RCC_MP_AHB5LPENSETR_RNG1LPEN = 0x40
	// Position of BKPSRAMLPEN field.
	RCC_RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos = 0x8
	// Bit mask of BKPSRAMLPEN field.
	RCC_RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk = 0x100
	// Bit BKPSRAMLPEN.
	RCC_RCC_MP_AHB5LPENSETR_BKPSRAMLPEN = 0x100

	// RCC_MP_AHB5LPENCLRR: This register is used by the MCU
	// Position of GPIOZLPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos = 0x0
	// Bit mask of GPIOZLPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk = 0x1
	// Bit GPIOZLPEN.
	RCC_RCC_MP_AHB5LPENCLRR_GPIOZLPEN = 0x1
	// Position of CRYP1LPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos = 0x4
	// Bit mask of CRYP1LPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk = 0x10
	// Bit CRYP1LPEN.
	RCC_RCC_MP_AHB5LPENCLRR_CRYP1LPEN = 0x10
	// Position of HASH1LPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos = 0x5
	// Bit mask of HASH1LPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk = 0x20
	// Bit HASH1LPEN.
	RCC_RCC_MP_AHB5LPENCLRR_HASH1LPEN = 0x20
	// Position of RNG1LPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos = 0x6
	// Bit mask of RNG1LPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk = 0x40
	// Bit RNG1LPEN.
	RCC_RCC_MP_AHB5LPENCLRR_RNG1LPEN = 0x40
	// Position of BKPSRAMLPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos = 0x8
	// Bit mask of BKPSRAMLPEN field.
	RCC_RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk = 0x100
	// Bit BKPSRAMLPEN.
	RCC_RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN = 0x100

	// RCC_MP_AHB6LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of MDMALPEN field.
	RCC_RCC_MP_AHB6LPENSETR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_RCC_MP_AHB6LPENSETR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_RCC_MP_AHB6LPENSETR_MDMALPEN = 0x1
	// Position of GPULPEN field.
	RCC_RCC_MP_AHB6LPENSETR_GPULPEN_Pos = 0x5
	// Bit mask of GPULPEN field.
	RCC_RCC_MP_AHB6LPENSETR_GPULPEN_Msk = 0x20
	// Bit GPULPEN.
	RCC_RCC_MP_AHB6LPENSETR_GPULPEN = 0x20
	// Position of ETHCKLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos = 0x7
	// Bit mask of ETHCKLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk = 0x80
	// Bit ETHCKLPEN.
	RCC_RCC_MP_AHB6LPENSETR_ETHCKLPEN = 0x80
	// Position of ETHTXLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos = 0x8
	// Bit mask of ETHTXLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk = 0x100
	// Bit ETHTXLPEN.
	RCC_RCC_MP_AHB6LPENSETR_ETHTXLPEN = 0x100
	// Position of ETHRXLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos = 0x9
	// Bit mask of ETHRXLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk = 0x200
	// Bit ETHRXLPEN.
	RCC_RCC_MP_AHB6LPENSETR_ETHRXLPEN = 0x200
	// Position of ETHMACLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos = 0xa
	// Bit mask of ETHMACLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk = 0x400
	// Bit ETHMACLPEN.
	RCC_RCC_MP_AHB6LPENSETR_ETHMACLPEN = 0x400
	// Position of ETHSTPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos = 0xb
	// Bit mask of ETHSTPEN field.
	RCC_RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk = 0x800
	// Bit ETHSTPEN.
	RCC_RCC_MP_AHB6LPENSETR_ETHSTPEN = 0x800
	// Position of FMCLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_FMCLPEN_Pos = 0xc
	// Bit mask of FMCLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_FMCLPEN_Msk = 0x1000
	// Bit FMCLPEN.
	RCC_RCC_MP_AHB6LPENSETR_FMCLPEN = 0x1000
	// Position of QSPILPEN field.
	RCC_RCC_MP_AHB6LPENSETR_QSPILPEN_Pos = 0xe
	// Bit mask of QSPILPEN field.
	RCC_RCC_MP_AHB6LPENSETR_QSPILPEN_Msk = 0x4000
	// Bit QSPILPEN.
	RCC_RCC_MP_AHB6LPENSETR_QSPILPEN = 0x4000
	// Position of SDMMC1LPEN field.
	RCC_RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos = 0x10
	// Bit mask of SDMMC1LPEN field.
	RCC_RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk = 0x10000
	// Bit SDMMC1LPEN.
	RCC_RCC_MP_AHB6LPENSETR_SDMMC1LPEN = 0x10000
	// Position of SDMMC2LPEN field.
	RCC_RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos = 0x11
	// Bit mask of SDMMC2LPEN field.
	RCC_RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk = 0x20000
	// Bit SDMMC2LPEN.
	RCC_RCC_MP_AHB6LPENSETR_SDMMC2LPEN = 0x20000
	// Position of CRC1LPEN field.
	RCC_RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos = 0x14
	// Bit mask of CRC1LPEN field.
	RCC_RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk = 0x100000
	// Bit CRC1LPEN.
	RCC_RCC_MP_AHB6LPENSETR_CRC1LPEN = 0x100000
	// Position of USBHLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_USBHLPEN_Pos = 0x18
	// Bit mask of USBHLPEN field.
	RCC_RCC_MP_AHB6LPENSETR_USBHLPEN_Msk = 0x1000000
	// Bit USBHLPEN.
	RCC_RCC_MP_AHB6LPENSETR_USBHLPEN = 0x1000000

	// RCC_MP_AHB6LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of MDMALPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_RCC_MP_AHB6LPENCLRR_MDMALPEN = 0x1
	// Position of GPULPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_GPULPEN_Pos = 0x5
	// Bit mask of GPULPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_GPULPEN_Msk = 0x20
	// Bit GPULPEN.
	RCC_RCC_MP_AHB6LPENCLRR_GPULPEN = 0x20
	// Position of ETHCKLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos = 0x7
	// Bit mask of ETHCKLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk = 0x80
	// Bit ETHCKLPEN.
	RCC_RCC_MP_AHB6LPENCLRR_ETHCKLPEN = 0x80
	// Position of ETHTXLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos = 0x8
	// Bit mask of ETHTXLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk = 0x100
	// Bit ETHTXLPEN.
	RCC_RCC_MP_AHB6LPENCLRR_ETHTXLPEN = 0x100
	// Position of ETHRXLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos = 0x9
	// Bit mask of ETHRXLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk = 0x200
	// Bit ETHRXLPEN.
	RCC_RCC_MP_AHB6LPENCLRR_ETHRXLPEN = 0x200
	// Position of ETHMACLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos = 0xa
	// Bit mask of ETHMACLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk = 0x400
	// Bit ETHMACLPEN.
	RCC_RCC_MP_AHB6LPENCLRR_ETHMACLPEN = 0x400
	// Position of ETHSTPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos = 0xb
	// Bit mask of ETHSTPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk = 0x800
	// Bit ETHSTPEN.
	RCC_RCC_MP_AHB6LPENCLRR_ETHSTPEN = 0x800
	// Position of FMCLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos = 0xc
	// Bit mask of FMCLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk = 0x1000
	// Bit FMCLPEN.
	RCC_RCC_MP_AHB6LPENCLRR_FMCLPEN = 0x1000
	// Position of QSPILPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos = 0xe
	// Bit mask of QSPILPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk = 0x4000
	// Bit QSPILPEN.
	RCC_RCC_MP_AHB6LPENCLRR_QSPILPEN = 0x4000
	// Position of SDMMC1LPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos = 0x10
	// Bit mask of SDMMC1LPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk = 0x10000
	// Bit SDMMC1LPEN.
	RCC_RCC_MP_AHB6LPENCLRR_SDMMC1LPEN = 0x10000
	// Position of SDMMC2LPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos = 0x11
	// Bit mask of SDMMC2LPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk = 0x20000
	// Bit SDMMC2LPEN.
	RCC_RCC_MP_AHB6LPENCLRR_SDMMC2LPEN = 0x20000
	// Position of CRC1LPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos = 0x14
	// Bit mask of CRC1LPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk = 0x100000
	// Bit CRC1LPEN.
	RCC_RCC_MP_AHB6LPENCLRR_CRC1LPEN = 0x100000
	// Position of USBHLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos = 0x18
	// Bit mask of USBHLPEN field.
	RCC_RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk = 0x1000000
	// Bit USBHLPEN.
	RCC_RCC_MP_AHB6LPENCLRR_USBHLPEN = 0x1000000

	// RCC_MP_TZAHB6LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
	// Position of MDMALPEN field.
	RCC_RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_RCC_MP_TZAHB6LPENSETR_MDMALPEN = 0x1

	// RCC_MP_TZAHB6LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
	// Position of MDMALPEN field.
	RCC_RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_RCC_MP_TZAHB6LPENCLRR_MDMALPEN = 0x1

	// RCC_MC_APB4LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of LTDCLPEN field.
	RCC_RCC_MC_APB4LPENSETR_LTDCLPEN_Pos = 0x0
	// Bit mask of LTDCLPEN field.
	RCC_RCC_MC_APB4LPENSETR_LTDCLPEN_Msk = 0x1
	// Bit LTDCLPEN.
	RCC_RCC_MC_APB4LPENSETR_LTDCLPEN = 0x1
	// Position of DSILPEN field.
	RCC_RCC_MC_APB4LPENSETR_DSILPEN_Pos = 0x4
	// Bit mask of DSILPEN field.
	RCC_RCC_MC_APB4LPENSETR_DSILPEN_Msk = 0x10
	// Bit DSILPEN.
	RCC_RCC_MC_APB4LPENSETR_DSILPEN = 0x10
	// Position of DDRPERFMLPEN field.
	RCC_RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos = 0x8
	// Bit mask of DDRPERFMLPEN field.
	RCC_RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk = 0x100
	// Bit DDRPERFMLPEN.
	RCC_RCC_MC_APB4LPENSETR_DDRPERFMLPEN = 0x100
	// Position of USBPHYLPEN field.
	RCC_RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos = 0x10
	// Bit mask of USBPHYLPEN field.
	RCC_RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk = 0x10000
	// Bit USBPHYLPEN.
	RCC_RCC_MC_APB4LPENSETR_USBPHYLPEN = 0x10000
	// Position of STGENROLPEN field.
	RCC_RCC_MC_APB4LPENSETR_STGENROLPEN_Pos = 0x14
	// Bit mask of STGENROLPEN field.
	RCC_RCC_MC_APB4LPENSETR_STGENROLPEN_Msk = 0x100000
	// Bit STGENROLPEN.
	RCC_RCC_MC_APB4LPENSETR_STGENROLPEN = 0x100000
	// Position of STGENROSTPEN field.
	RCC_RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos = 0x15
	// Bit mask of STGENROSTPEN field.
	RCC_RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk = 0x200000
	// Bit STGENROSTPEN.
	RCC_RCC_MC_APB4LPENSETR_STGENROSTPEN = 0x200000

	// RCC_MC_APB4LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit
	// Position of LTDCLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos = 0x0
	// Bit mask of LTDCLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk = 0x1
	// Bit LTDCLPEN.
	RCC_RCC_MC_APB4LPENCLRR_LTDCLPEN = 0x1
	// Position of DSILPEN field.
	RCC_RCC_MC_APB4LPENCLRR_DSILPEN_Pos = 0x4
	// Bit mask of DSILPEN field.
	RCC_RCC_MC_APB4LPENCLRR_DSILPEN_Msk = 0x10
	// Bit DSILPEN.
	RCC_RCC_MC_APB4LPENCLRR_DSILPEN = 0x10
	// Position of DDRPERFMLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos = 0x8
	// Bit mask of DDRPERFMLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk = 0x100
	// Bit DDRPERFMLPEN.
	RCC_RCC_MC_APB4LPENCLRR_DDRPERFMLPEN = 0x100
	// Position of USBPHYLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos = 0x10
	// Bit mask of USBPHYLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk = 0x10000
	// Bit USBPHYLPEN.
	RCC_RCC_MC_APB4LPENCLRR_USBPHYLPEN = 0x10000
	// Position of STGENROLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos = 0x14
	// Bit mask of STGENROLPEN field.
	RCC_RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk = 0x100000
	// Bit STGENROLPEN.
	RCC_RCC_MC_APB4LPENCLRR_STGENROLPEN = 0x100000
	// Position of STGENROSTPEN field.
	RCC_RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos = 0x15
	// Bit mask of STGENROSTPEN field.
	RCC_RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk = 0x200000
	// Bit STGENROSTPEN.
	RCC_RCC_MC_APB4LPENCLRR_STGENROSTPEN = 0x200000

	// RCC_MC_APB5LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of SPI6LPEN field.
	RCC_RCC_MC_APB5LPENSETR_SPI6LPEN_Pos = 0x0
	// Bit mask of SPI6LPEN field.
	RCC_RCC_MC_APB5LPENSETR_SPI6LPEN_Msk = 0x1
	// Bit SPI6LPEN.
	RCC_RCC_MC_APB5LPENSETR_SPI6LPEN = 0x1
	// Position of I2C4LPEN field.
	RCC_RCC_MC_APB5LPENSETR_I2C4LPEN_Pos = 0x2
	// Bit mask of I2C4LPEN field.
	RCC_RCC_MC_APB5LPENSETR_I2C4LPEN_Msk = 0x4
	// Bit I2C4LPEN.
	RCC_RCC_MC_APB5LPENSETR_I2C4LPEN = 0x4
	// Position of I2C6LPEN field.
	RCC_RCC_MC_APB5LPENSETR_I2C6LPEN_Pos = 0x3
	// Bit mask of I2C6LPEN field.
	RCC_RCC_MC_APB5LPENSETR_I2C6LPEN_Msk = 0x8
	// Bit I2C6LPEN.
	RCC_RCC_MC_APB5LPENSETR_I2C6LPEN = 0x8
	// Position of USART1LPEN field.
	RCC_RCC_MC_APB5LPENSETR_USART1LPEN_Pos = 0x4
	// Bit mask of USART1LPEN field.
	RCC_RCC_MC_APB5LPENSETR_USART1LPEN_Msk = 0x10
	// Bit USART1LPEN.
	RCC_RCC_MC_APB5LPENSETR_USART1LPEN = 0x10
	// Position of RTCAPBLPEN field.
	RCC_RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos = 0x8
	// Bit mask of RTCAPBLPEN field.
	RCC_RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk = 0x100
	// Bit RTCAPBLPEN.
	RCC_RCC_MC_APB5LPENSETR_RTCAPBLPEN = 0x100
	// Position of TZC1LPEN field.
	RCC_RCC_MC_APB5LPENSETR_TZC1LPEN_Pos = 0xb
	// Bit mask of TZC1LPEN field.
	RCC_RCC_MC_APB5LPENSETR_TZC1LPEN_Msk = 0x800
	// Bit TZC1LPEN.
	RCC_RCC_MC_APB5LPENSETR_TZC1LPEN = 0x800
	// Position of TZC2LPEN field.
	RCC_RCC_MC_APB5LPENSETR_TZC2LPEN_Pos = 0xc
	// Bit mask of TZC2LPEN field.
	RCC_RCC_MC_APB5LPENSETR_TZC2LPEN_Msk = 0x1000
	// Bit TZC2LPEN.
	RCC_RCC_MC_APB5LPENSETR_TZC2LPEN = 0x1000
	// Position of TZPCLPEN field.
	RCC_RCC_MC_APB5LPENSETR_TZPCLPEN_Pos = 0xd
	// Bit mask of TZPCLPEN field.
	RCC_RCC_MC_APB5LPENSETR_TZPCLPEN_Msk = 0x2000
	// Bit TZPCLPEN.
	RCC_RCC_MC_APB5LPENSETR_TZPCLPEN = 0x2000
	// Position of BSECLPEN field.
	RCC_RCC_MC_APB5LPENSETR_BSECLPEN_Pos = 0x10
	// Bit mask of BSECLPEN field.
	RCC_RCC_MC_APB5LPENSETR_BSECLPEN_Msk = 0x10000
	// Bit BSECLPEN.
	RCC_RCC_MC_APB5LPENSETR_BSECLPEN = 0x10000
	// Position of STGENLPEN field.
	RCC_RCC_MC_APB5LPENSETR_STGENLPEN_Pos = 0x14
	// Bit mask of STGENLPEN field.
	RCC_RCC_MC_APB5LPENSETR_STGENLPEN_Msk = 0x100000
	// Bit STGENLPEN.
	RCC_RCC_MC_APB5LPENSETR_STGENLPEN = 0x100000
	// Position of STGENSTPEN field.
	RCC_RCC_MC_APB5LPENSETR_STGENSTPEN_Pos = 0x15
	// Bit mask of STGENSTPEN field.
	RCC_RCC_MC_APB5LPENSETR_STGENSTPEN_Msk = 0x200000
	// Bit STGENSTPEN.
	RCC_RCC_MC_APB5LPENSETR_STGENSTPEN = 0x200000

	// RCC_MC_APB5LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit
	// Position of SPI6LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos = 0x0
	// Bit mask of SPI6LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk = 0x1
	// Bit SPI6LPEN.
	RCC_RCC_MC_APB5LPENCLRR_SPI6LPEN = 0x1
	// Position of I2C4LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos = 0x2
	// Bit mask of I2C4LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk = 0x4
	// Bit I2C4LPEN.
	RCC_RCC_MC_APB5LPENCLRR_I2C4LPEN = 0x4
	// Position of I2C6LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos = 0x3
	// Bit mask of I2C6LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk = 0x8
	// Bit I2C6LPEN.
	RCC_RCC_MC_APB5LPENCLRR_I2C6LPEN = 0x8
	// Position of USART1LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_USART1LPEN_Pos = 0x4
	// Bit mask of USART1LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_USART1LPEN_Msk = 0x10
	// Bit USART1LPEN.
	RCC_RCC_MC_APB5LPENCLRR_USART1LPEN = 0x10
	// Position of RTCAPBLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos = 0x8
	// Bit mask of RTCAPBLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk = 0x100
	// Bit RTCAPBLPEN.
	RCC_RCC_MC_APB5LPENCLRR_RTCAPBLPEN = 0x100
	// Position of TZC1LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos = 0xb
	// Bit mask of TZC1LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk = 0x800
	// Bit TZC1LPEN.
	RCC_RCC_MC_APB5LPENCLRR_TZC1LPEN = 0x800
	// Position of TZC2LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos = 0xc
	// Bit mask of TZC2LPEN field.
	RCC_RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk = 0x1000
	// Bit TZC2LPEN.
	RCC_RCC_MC_APB5LPENCLRR_TZC2LPEN = 0x1000
	// Position of TZPCLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos = 0xd
	// Bit mask of TZPCLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk = 0x2000
	// Bit TZPCLPEN.
	RCC_RCC_MC_APB5LPENCLRR_TZPCLPEN = 0x2000
	// Position of BSECLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_BSECLPEN_Pos = 0x10
	// Bit mask of BSECLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_BSECLPEN_Msk = 0x10000
	// Bit BSECLPEN.
	RCC_RCC_MC_APB5LPENCLRR_BSECLPEN = 0x10000
	// Position of STGENLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_STGENLPEN_Pos = 0x14
	// Bit mask of STGENLPEN field.
	RCC_RCC_MC_APB5LPENCLRR_STGENLPEN_Msk = 0x100000
	// Bit STGENLPEN.
	RCC_RCC_MC_APB5LPENCLRR_STGENLPEN = 0x100000
	// Position of STGENSTPEN field.
	RCC_RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos = 0x15
	// Bit mask of STGENSTPEN field.
	RCC_RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk = 0x200000
	// Bit STGENSTPEN.
	RCC_RCC_MC_APB5LPENCLRR_STGENSTPEN = 0x200000

	// RCC_MC_AHB5LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZLPEN field.
	RCC_RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos = 0x0
	// Bit mask of GPIOZLPEN field.
	RCC_RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk = 0x1
	// Bit GPIOZLPEN.
	RCC_RCC_MC_AHB5LPENSETR_GPIOZLPEN = 0x1
	// Position of CRYP1LPEN field.
	RCC_RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos = 0x4
	// Bit mask of CRYP1LPEN field.
	RCC_RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk = 0x10
	// Bit CRYP1LPEN.
	RCC_RCC_MC_AHB5LPENSETR_CRYP1LPEN = 0x10
	// Position of HASH1LPEN field.
	RCC_RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos = 0x5
	// Bit mask of HASH1LPEN field.
	RCC_RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk = 0x20
	// Bit HASH1LPEN.
	RCC_RCC_MC_AHB5LPENSETR_HASH1LPEN = 0x20
	// Position of RNG1LPEN field.
	RCC_RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos = 0x6
	// Bit mask of RNG1LPEN field.
	RCC_RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk = 0x40
	// Bit RNG1LPEN.
	RCC_RCC_MC_AHB5LPENSETR_RNG1LPEN = 0x40
	// Position of BKPSRAMLPEN field.
	RCC_RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos = 0x8
	// Bit mask of BKPSRAMLPEN field.
	RCC_RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk = 0x100
	// Bit BKPSRAMLPEN.
	RCC_RCC_MC_AHB5LPENSETR_BKPSRAMLPEN = 0x100

	// RCC_MC_AHB5LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode.
	// Position of GPIOZLPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos = 0x0
	// Bit mask of GPIOZLPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk = 0x1
	// Bit GPIOZLPEN.
	RCC_RCC_MC_AHB5LPENCLRR_GPIOZLPEN = 0x1
	// Position of CRYP1LPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos = 0x4
	// Bit mask of CRYP1LPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk = 0x10
	// Bit CRYP1LPEN.
	RCC_RCC_MC_AHB5LPENCLRR_CRYP1LPEN = 0x10
	// Position of HASH1LPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos = 0x5
	// Bit mask of HASH1LPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk = 0x20
	// Bit HASH1LPEN.
	RCC_RCC_MC_AHB5LPENCLRR_HASH1LPEN = 0x20
	// Position of RNG1LPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos = 0x6
	// Bit mask of RNG1LPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk = 0x40
	// Bit RNG1LPEN.
	RCC_RCC_MC_AHB5LPENCLRR_RNG1LPEN = 0x40
	// Position of BKPSRAMLPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos = 0x8
	// Bit mask of BKPSRAMLPEN field.
	RCC_RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk = 0x100
	// Bit BKPSRAMLPEN.
	RCC_RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN = 0x100

	// RCC_MC_AHB6LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of MDMALPEN field.
	RCC_RCC_MC_AHB6LPENSETR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_RCC_MC_AHB6LPENSETR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_RCC_MC_AHB6LPENSETR_MDMALPEN = 0x1
	// Position of GPULPEN field.
	RCC_RCC_MC_AHB6LPENSETR_GPULPEN_Pos = 0x5
	// Bit mask of GPULPEN field.
	RCC_RCC_MC_AHB6LPENSETR_GPULPEN_Msk = 0x20
	// Bit GPULPEN.
	RCC_RCC_MC_AHB6LPENSETR_GPULPEN = 0x20
	// Position of ETHCKLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos = 0x7
	// Bit mask of ETHCKLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk = 0x80
	// Bit ETHCKLPEN.
	RCC_RCC_MC_AHB6LPENSETR_ETHCKLPEN = 0x80
	// Position of ETHTXLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos = 0x8
	// Bit mask of ETHTXLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk = 0x100
	// Bit ETHTXLPEN.
	RCC_RCC_MC_AHB6LPENSETR_ETHTXLPEN = 0x100
	// Position of ETHRXLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos = 0x9
	// Bit mask of ETHRXLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk = 0x200
	// Bit ETHRXLPEN.
	RCC_RCC_MC_AHB6LPENSETR_ETHRXLPEN = 0x200
	// Position of ETHMACLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos = 0xa
	// Bit mask of ETHMACLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk = 0x400
	// Bit ETHMACLPEN.
	RCC_RCC_MC_AHB6LPENSETR_ETHMACLPEN = 0x400
	// Position of ETHSTPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos = 0xb
	// Bit mask of ETHSTPEN field.
	RCC_RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk = 0x800
	// Bit ETHSTPEN.
	RCC_RCC_MC_AHB6LPENSETR_ETHSTPEN = 0x800
	// Position of FMCLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_FMCLPEN_Pos = 0xc
	// Bit mask of FMCLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_FMCLPEN_Msk = 0x1000
	// Bit FMCLPEN.
	RCC_RCC_MC_AHB6LPENSETR_FMCLPEN = 0x1000
	// Position of QSPILPEN field.
	RCC_RCC_MC_AHB6LPENSETR_QSPILPEN_Pos = 0xe
	// Bit mask of QSPILPEN field.
	RCC_RCC_MC_AHB6LPENSETR_QSPILPEN_Msk = 0x4000
	// Bit QSPILPEN.
	RCC_RCC_MC_AHB6LPENSETR_QSPILPEN = 0x4000
	// Position of SDMMC1LPEN field.
	RCC_RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos = 0x10
	// Bit mask of SDMMC1LPEN field.
	RCC_RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk = 0x10000
	// Bit SDMMC1LPEN.
	RCC_RCC_MC_AHB6LPENSETR_SDMMC1LPEN = 0x10000
	// Position of SDMMC2LPEN field.
	RCC_RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos = 0x11
	// Bit mask of SDMMC2LPEN field.
	RCC_RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk = 0x20000
	// Bit SDMMC2LPEN.
	RCC_RCC_MC_AHB6LPENSETR_SDMMC2LPEN = 0x20000
	// Position of CRC1LPEN field.
	RCC_RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos = 0x14
	// Bit mask of CRC1LPEN field.
	RCC_RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk = 0x100000
	// Bit CRC1LPEN.
	RCC_RCC_MC_AHB6LPENSETR_CRC1LPEN = 0x100000
	// Position of USBHLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_USBHLPEN_Pos = 0x18
	// Bit mask of USBHLPEN field.
	RCC_RCC_MC_AHB6LPENSETR_USBHLPEN_Msk = 0x1000000
	// Bit USBHLPEN.
	RCC_RCC_MC_AHB6LPENSETR_USBHLPEN = 0x1000000

	// RCC_MC_AHB6LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit
	// Position of MDMALPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_RCC_MC_AHB6LPENCLRR_MDMALPEN = 0x1
	// Position of GPULPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_GPULPEN_Pos = 0x5
	// Bit mask of GPULPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_GPULPEN_Msk = 0x20
	// Bit GPULPEN.
	RCC_RCC_MC_AHB6LPENCLRR_GPULPEN = 0x20
	// Position of ETHCKLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos = 0x7
	// Bit mask of ETHCKLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk = 0x80
	// Bit ETHCKLPEN.
	RCC_RCC_MC_AHB6LPENCLRR_ETHCKLPEN = 0x80
	// Position of ETHTXLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos = 0x8
	// Bit mask of ETHTXLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk = 0x100
	// Bit ETHTXLPEN.
	RCC_RCC_MC_AHB6LPENCLRR_ETHTXLPEN = 0x100
	// Position of ETHRXLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos = 0x9
	// Bit mask of ETHRXLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk = 0x200
	// Bit ETHRXLPEN.
	RCC_RCC_MC_AHB6LPENCLRR_ETHRXLPEN = 0x200
	// Position of ETHMACLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos = 0xa
	// Bit mask of ETHMACLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk = 0x400
	// Bit ETHMACLPEN.
	RCC_RCC_MC_AHB6LPENCLRR_ETHMACLPEN = 0x400
	// Position of ETHSTPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos = 0xb
	// Bit mask of ETHSTPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk = 0x800
	// Bit ETHSTPEN.
	RCC_RCC_MC_AHB6LPENCLRR_ETHSTPEN = 0x800
	// Position of FMCLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos = 0xc
	// Bit mask of FMCLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk = 0x1000
	// Bit FMCLPEN.
	RCC_RCC_MC_AHB6LPENCLRR_FMCLPEN = 0x1000
	// Position of QSPILPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos = 0xe
	// Bit mask of QSPILPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk = 0x4000
	// Bit QSPILPEN.
	RCC_RCC_MC_AHB6LPENCLRR_QSPILPEN = 0x4000
	// Position of SDMMC1LPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos = 0x10
	// Bit mask of SDMMC1LPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk = 0x10000
	// Bit SDMMC1LPEN.
	RCC_RCC_MC_AHB6LPENCLRR_SDMMC1LPEN = 0x10000
	// Position of SDMMC2LPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos = 0x11
	// Bit mask of SDMMC2LPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk = 0x20000
	// Bit SDMMC2LPEN.
	RCC_RCC_MC_AHB6LPENCLRR_SDMMC2LPEN = 0x20000
	// Position of CRC1LPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos = 0x14
	// Bit mask of CRC1LPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk = 0x100000
	// Bit CRC1LPEN.
	RCC_RCC_MC_AHB6LPENCLRR_CRC1LPEN = 0x100000
	// Position of USBHLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos = 0x18
	// Bit mask of USBHLPEN field.
	RCC_RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk = 0x1000000
	// Bit USBHLPEN.
	RCC_RCC_MC_AHB6LPENCLRR_USBHLPEN = 0x1000000

	// RCC_BR_RSTSCLRR: This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode.
	// Position of PORRSTF field.
	RCC_RCC_BR_RSTSCLRR_PORRSTF_Pos = 0x0
	// Bit mask of PORRSTF field.
	RCC_RCC_BR_RSTSCLRR_PORRSTF_Msk = 0x1
	// Bit PORRSTF.
	RCC_RCC_BR_RSTSCLRR_PORRSTF = 0x1
	// Position of BORRSTF field.
	RCC_RCC_BR_RSTSCLRR_BORRSTF_Pos = 0x1
	// Bit mask of BORRSTF field.
	RCC_RCC_BR_RSTSCLRR_BORRSTF_Msk = 0x2
	// Bit BORRSTF.
	RCC_RCC_BR_RSTSCLRR_BORRSTF = 0x2
	// Position of PADRSTF field.
	RCC_RCC_BR_RSTSCLRR_PADRSTF_Pos = 0x2
	// Bit mask of PADRSTF field.
	RCC_RCC_BR_RSTSCLRR_PADRSTF_Msk = 0x4
	// Bit PADRSTF.
	RCC_RCC_BR_RSTSCLRR_PADRSTF = 0x4
	// Position of HCSSRSTF field.
	RCC_RCC_BR_RSTSCLRR_HCSSRSTF_Pos = 0x3
	// Bit mask of HCSSRSTF field.
	RCC_RCC_BR_RSTSCLRR_HCSSRSTF_Msk = 0x8
	// Bit HCSSRSTF.
	RCC_RCC_BR_RSTSCLRR_HCSSRSTF = 0x8
	// Position of VCORERSTF field.
	RCC_RCC_BR_RSTSCLRR_VCORERSTF_Pos = 0x4
	// Bit mask of VCORERSTF field.
	RCC_RCC_BR_RSTSCLRR_VCORERSTF_Msk = 0x10
	// Bit VCORERSTF.
	RCC_RCC_BR_RSTSCLRR_VCORERSTF = 0x10
	// Position of MPSYSRSTF field.
	RCC_RCC_BR_RSTSCLRR_MPSYSRSTF_Pos = 0x6
	// Bit mask of MPSYSRSTF field.
	RCC_RCC_BR_RSTSCLRR_MPSYSRSTF_Msk = 0x40
	// Bit MPSYSRSTF.
	RCC_RCC_BR_RSTSCLRR_MPSYSRSTF = 0x40
	// Position of MCSYSRSTF field.
	RCC_RCC_BR_RSTSCLRR_MCSYSRSTF_Pos = 0x7
	// Bit mask of MCSYSRSTF field.
	RCC_RCC_BR_RSTSCLRR_MCSYSRSTF_Msk = 0x80
	// Bit MCSYSRSTF.
	RCC_RCC_BR_RSTSCLRR_MCSYSRSTF = 0x80
	// Position of IWDG1RSTF field.
	RCC_RCC_BR_RSTSCLRR_IWDG1RSTF_Pos = 0x8
	// Bit mask of IWDG1RSTF field.
	RCC_RCC_BR_RSTSCLRR_IWDG1RSTF_Msk = 0x100
	// Bit IWDG1RSTF.
	RCC_RCC_BR_RSTSCLRR_IWDG1RSTF = 0x100
	// Position of IWDG2RSTF field.
	RCC_RCC_BR_RSTSCLRR_IWDG2RSTF_Pos = 0x9
	// Bit mask of IWDG2RSTF field.
	RCC_RCC_BR_RSTSCLRR_IWDG2RSTF_Msk = 0x200
	// Bit IWDG2RSTF.
	RCC_RCC_BR_RSTSCLRR_IWDG2RSTF = 0x200
	// Position of MPUP0RSTF field.
	RCC_RCC_BR_RSTSCLRR_MPUP0RSTF_Pos = 0xd
	// Bit mask of MPUP0RSTF field.
	RCC_RCC_BR_RSTSCLRR_MPUP0RSTF_Msk = 0x2000
	// Bit MPUP0RSTF.
	RCC_RCC_BR_RSTSCLRR_MPUP0RSTF = 0x2000
	// Position of MPUP1RSTF field.
	RCC_RCC_BR_RSTSCLRR_MPUP1RSTF_Pos = 0xe
	// Bit mask of MPUP1RSTF field.
	RCC_RCC_BR_RSTSCLRR_MPUP1RSTF_Msk = 0x4000
	// Bit MPUP1RSTF.
	RCC_RCC_BR_RSTSCLRR_MPUP1RSTF = 0x4000

	// RCC_MP_GRSTCSETR: This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset.
	// Position of MPSYSRST field.
	RCC_RCC_MP_GRSTCSETR_MPSYSRST_Pos = 0x0
	// Bit mask of MPSYSRST field.
	RCC_RCC_MP_GRSTCSETR_MPSYSRST_Msk = 0x1
	// Bit MPSYSRST.
	RCC_RCC_MP_GRSTCSETR_MPSYSRST = 0x1
	// Position of MCURST field.
	RCC_RCC_MP_GRSTCSETR_MCURST_Pos = 0x1
	// Bit mask of MCURST field.
	RCC_RCC_MP_GRSTCSETR_MCURST_Msk = 0x2
	// Bit MCURST.
	RCC_RCC_MP_GRSTCSETR_MCURST = 0x2
	// Position of MPUP0RST field.
	RCC_RCC_MP_GRSTCSETR_MPUP0RST_Pos = 0x4
	// Bit mask of MPUP0RST field.
	RCC_RCC_MP_GRSTCSETR_MPUP0RST_Msk = 0x10
	// Bit MPUP0RST.
	RCC_RCC_MP_GRSTCSETR_MPUP0RST = 0x10
	// Position of MPUP1RST field.
	RCC_RCC_MP_GRSTCSETR_MPUP1RST_Pos = 0x5
	// Bit mask of MPUP1RST field.
	RCC_RCC_MP_GRSTCSETR_MPUP1RST_Msk = 0x20
	// Bit MPUP1RST.
	RCC_RCC_MP_GRSTCSETR_MPUP1RST = 0x20

	// RCC_MP_RSTSCLRR: This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.
	// Position of PORRSTF field.
	RCC_RCC_MP_RSTSCLRR_PORRSTF_Pos = 0x0
	// Bit mask of PORRSTF field.
	RCC_RCC_MP_RSTSCLRR_PORRSTF_Msk = 0x1
	// Bit PORRSTF.
	RCC_RCC_MP_RSTSCLRR_PORRSTF = 0x1
	// Position of BORRSTF field.
	RCC_RCC_MP_RSTSCLRR_BORRSTF_Pos = 0x1
	// Bit mask of BORRSTF field.
	RCC_RCC_MP_RSTSCLRR_BORRSTF_Msk = 0x2
	// Bit BORRSTF.
	RCC_RCC_MP_RSTSCLRR_BORRSTF = 0x2
	// Position of PADRSTF field.
	RCC_RCC_MP_RSTSCLRR_PADRSTF_Pos = 0x2
	// Bit mask of PADRSTF field.
	RCC_RCC_MP_RSTSCLRR_PADRSTF_Msk = 0x4
	// Bit PADRSTF.
	RCC_RCC_MP_RSTSCLRR_PADRSTF = 0x4
	// Position of HCSSRSTF field.
	RCC_RCC_MP_RSTSCLRR_HCSSRSTF_Pos = 0x3
	// Bit mask of HCSSRSTF field.
	RCC_RCC_MP_RSTSCLRR_HCSSRSTF_Msk = 0x8
	// Bit HCSSRSTF.
	RCC_RCC_MP_RSTSCLRR_HCSSRSTF = 0x8
	// Position of VCORERSTF field.
	RCC_RCC_MP_RSTSCLRR_VCORERSTF_Pos = 0x4
	// Bit mask of VCORERSTF field.
	RCC_RCC_MP_RSTSCLRR_VCORERSTF_Msk = 0x10
	// Bit VCORERSTF.
	RCC_RCC_MP_RSTSCLRR_VCORERSTF = 0x10
	// Position of MPSYSRSTF field.
	RCC_RCC_MP_RSTSCLRR_MPSYSRSTF_Pos = 0x6
	// Bit mask of MPSYSRSTF field.
	RCC_RCC_MP_RSTSCLRR_MPSYSRSTF_Msk = 0x40
	// Bit MPSYSRSTF.
	RCC_RCC_MP_RSTSCLRR_MPSYSRSTF = 0x40
	// Position of MCSYSRSTF field.
	RCC_RCC_MP_RSTSCLRR_MCSYSRSTF_Pos = 0x7
	// Bit mask of MCSYSRSTF field.
	RCC_RCC_MP_RSTSCLRR_MCSYSRSTF_Msk = 0x80
	// Bit MCSYSRSTF.
	RCC_RCC_MP_RSTSCLRR_MCSYSRSTF = 0x80
	// Position of IWDG1RSTF field.
	RCC_RCC_MP_RSTSCLRR_IWDG1RSTF_Pos = 0x8
	// Bit mask of IWDG1RSTF field.
	RCC_RCC_MP_RSTSCLRR_IWDG1RSTF_Msk = 0x100
	// Bit IWDG1RSTF.
	RCC_RCC_MP_RSTSCLRR_IWDG1RSTF = 0x100
	// Position of IWDG2RSTF field.
	RCC_RCC_MP_RSTSCLRR_IWDG2RSTF_Pos = 0x9
	// Bit mask of IWDG2RSTF field.
	RCC_RCC_MP_RSTSCLRR_IWDG2RSTF_Msk = 0x200
	// Bit IWDG2RSTF.
	RCC_RCC_MP_RSTSCLRR_IWDG2RSTF = 0x200
	// Position of STDBYRSTF field.
	RCC_RCC_MP_RSTSCLRR_STDBYRSTF_Pos = 0xb
	// Bit mask of STDBYRSTF field.
	RCC_RCC_MP_RSTSCLRR_STDBYRSTF_Msk = 0x800
	// Bit STDBYRSTF.
	RCC_RCC_MP_RSTSCLRR_STDBYRSTF = 0x800
	// Position of CSTDBYRSTF field.
	RCC_RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos = 0xc
	// Bit mask of CSTDBYRSTF field.
	RCC_RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk = 0x1000
	// Bit CSTDBYRSTF.
	RCC_RCC_MP_RSTSCLRR_CSTDBYRSTF = 0x1000
	// Position of MPUP0RSTF field.
	RCC_RCC_MP_RSTSCLRR_MPUP0RSTF_Pos = 0xd
	// Bit mask of MPUP0RSTF field.
	RCC_RCC_MP_RSTSCLRR_MPUP0RSTF_Msk = 0x2000
	// Bit MPUP0RSTF.
	RCC_RCC_MP_RSTSCLRR_MPUP0RSTF = 0x2000
	// Position of MPUP1RSTF field.
	RCC_RCC_MP_RSTSCLRR_MPUP1RSTF_Pos = 0xe
	// Bit mask of MPUP1RSTF field.
	RCC_RCC_MP_RSTSCLRR_MPUP1RSTF_Msk = 0x4000
	// Bit MPUP1RSTF.
	RCC_RCC_MP_RSTSCLRR_MPUP1RSTF = 0x4000
	// Position of SPARE field.
	RCC_RCC_MP_RSTSCLRR_SPARE_Pos = 0xf
	// Bit mask of SPARE field.
	RCC_RCC_MP_RSTSCLRR_SPARE_Msk = 0x8000
	// Bit SPARE.
	RCC_RCC_MP_RSTSCLRR_SPARE = 0x8000

	// RCC_MP_IWDGFZSETR: This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
	// Position of FZ_IWDG1 field.
	RCC_RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos = 0x0
	// Bit mask of FZ_IWDG1 field.
	RCC_RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk = 0x1
	// Bit FZ_IWDG1.
	RCC_RCC_MP_IWDGFZSETR_FZ_IWDG1 = 0x1
	// Position of FZ_IWDG2 field.
	RCC_RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos = 0x1
	// Bit mask of FZ_IWDG2 field.
	RCC_RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk = 0x2
	// Bit FZ_IWDG2.
	RCC_RCC_MP_IWDGFZSETR_FZ_IWDG2 = 0x2

	// RCC_MP_IWDGFZCLRR: This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
	// Position of FZ_IWDG1 field.
	RCC_RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos = 0x0
	// Bit mask of FZ_IWDG1 field.
	RCC_RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk = 0x1
	// Bit FZ_IWDG1.
	RCC_RCC_MP_IWDGFZCLRR_FZ_IWDG1 = 0x1
	// Position of FZ_IWDG2 field.
	RCC_RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos = 0x1
	// Bit mask of FZ_IWDG2 field.
	RCC_RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk = 0x2
	// Bit FZ_IWDG2.
	RCC_RCC_MP_IWDGFZCLRR_FZ_IWDG2 = 0x2

	// RCC_MP_CIER: This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.
	// Position of LSIRDYIE field.
	RCC_RCC_MP_CIER_LSIRDYIE_Pos = 0x0
	// Bit mask of LSIRDYIE field.
	RCC_RCC_MP_CIER_LSIRDYIE_Msk = 0x1
	// Bit LSIRDYIE.
	RCC_RCC_MP_CIER_LSIRDYIE = 0x1
	// Position of LSERDYIE field.
	RCC_RCC_MP_CIER_LSERDYIE_Pos = 0x1
	// Bit mask of LSERDYIE field.
	RCC_RCC_MP_CIER_LSERDYIE_Msk = 0x2
	// Bit LSERDYIE.
	RCC_RCC_MP_CIER_LSERDYIE = 0x2
	// Position of HSIRDYIE field.
	RCC_RCC_MP_CIER_HSIRDYIE_Pos = 0x2
	// Bit mask of HSIRDYIE field.
	RCC_RCC_MP_CIER_HSIRDYIE_Msk = 0x4
	// Bit HSIRDYIE.
	RCC_RCC_MP_CIER_HSIRDYIE = 0x4
	// Position of HSERDYIE field.
	RCC_RCC_MP_CIER_HSERDYIE_Pos = 0x3
	// Bit mask of HSERDYIE field.
	RCC_RCC_MP_CIER_HSERDYIE_Msk = 0x8
	// Bit HSERDYIE.
	RCC_RCC_MP_CIER_HSERDYIE = 0x8
	// Position of CSIRDYIE field.
	RCC_RCC_MP_CIER_CSIRDYIE_Pos = 0x4
	// Bit mask of CSIRDYIE field.
	RCC_RCC_MP_CIER_CSIRDYIE_Msk = 0x10
	// Bit CSIRDYIE.
	RCC_RCC_MP_CIER_CSIRDYIE = 0x10
	// Position of PLL1DYIE field.
	RCC_RCC_MP_CIER_PLL1DYIE_Pos = 0x8
	// Bit mask of PLL1DYIE field.
	RCC_RCC_MP_CIER_PLL1DYIE_Msk = 0x100
	// Bit PLL1DYIE.
	RCC_RCC_MP_CIER_PLL1DYIE = 0x100
	// Position of PLL2DYIE field.
	RCC_RCC_MP_CIER_PLL2DYIE_Pos = 0x9
	// Bit mask of PLL2DYIE field.
	RCC_RCC_MP_CIER_PLL2DYIE_Msk = 0x200
	// Bit PLL2DYIE.
	RCC_RCC_MP_CIER_PLL2DYIE = 0x200
	// Position of PLL3DYIE field.
	RCC_RCC_MP_CIER_PLL3DYIE_Pos = 0xa
	// Bit mask of PLL3DYIE field.
	RCC_RCC_MP_CIER_PLL3DYIE_Msk = 0x400
	// Bit PLL3DYIE.
	RCC_RCC_MP_CIER_PLL3DYIE = 0x400
	// Position of PLL4DYIE field.
	RCC_RCC_MP_CIER_PLL4DYIE_Pos = 0xb
	// Bit mask of PLL4DYIE field.
	RCC_RCC_MP_CIER_PLL4DYIE_Msk = 0x800
	// Bit PLL4DYIE.
	RCC_RCC_MP_CIER_PLL4DYIE = 0x800
	// Position of LSECSSIE field.
	RCC_RCC_MP_CIER_LSECSSIE_Pos = 0x10
	// Bit mask of LSECSSIE field.
	RCC_RCC_MP_CIER_LSECSSIE_Msk = 0x10000
	// Bit LSECSSIE.
	RCC_RCC_MP_CIER_LSECSSIE = 0x10000
	// Position of WKUPIE field.
	RCC_RCC_MP_CIER_WKUPIE_Pos = 0x14
	// Bit mask of WKUPIE field.
	RCC_RCC_MP_CIER_WKUPIE_Msk = 0x100000
	// Bit WKUPIE.
	RCC_RCC_MP_CIER_WKUPIE = 0x100000

	// RCC_MP_CIFR: This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.
	// Position of LSIRDYF field.
	RCC_RCC_MP_CIFR_LSIRDYF_Pos = 0x0
	// Bit mask of LSIRDYF field.
	RCC_RCC_MP_CIFR_LSIRDYF_Msk = 0x1
	// Bit LSIRDYF.
	RCC_RCC_MP_CIFR_LSIRDYF = 0x1
	// Position of LSERDYF field.
	RCC_RCC_MP_CIFR_LSERDYF_Pos = 0x1
	// Bit mask of LSERDYF field.
	RCC_RCC_MP_CIFR_LSERDYF_Msk = 0x2
	// Bit LSERDYF.
	RCC_RCC_MP_CIFR_LSERDYF = 0x2
	// Position of HSIRDYF field.
	RCC_RCC_MP_CIFR_HSIRDYF_Pos = 0x2
	// Bit mask of HSIRDYF field.
	RCC_RCC_MP_CIFR_HSIRDYF_Msk = 0x4
	// Bit HSIRDYF.
	RCC_RCC_MP_CIFR_HSIRDYF = 0x4
	// Position of HSERDYF field.
	RCC_RCC_MP_CIFR_HSERDYF_Pos = 0x3
	// Bit mask of HSERDYF field.
	RCC_RCC_MP_CIFR_HSERDYF_Msk = 0x8
	// Bit HSERDYF.
	RCC_RCC_MP_CIFR_HSERDYF = 0x8
	// Position of CSIRDYF field.
	RCC_RCC_MP_CIFR_CSIRDYF_Pos = 0x4
	// Bit mask of CSIRDYF field.
	RCC_RCC_MP_CIFR_CSIRDYF_Msk = 0x10
	// Bit CSIRDYF.
	RCC_RCC_MP_CIFR_CSIRDYF = 0x10
	// Position of PLL1DYF field.
	RCC_RCC_MP_CIFR_PLL1DYF_Pos = 0x8
	// Bit mask of PLL1DYF field.
	RCC_RCC_MP_CIFR_PLL1DYF_Msk = 0x100
	// Bit PLL1DYF.
	RCC_RCC_MP_CIFR_PLL1DYF = 0x100
	// Position of PLL2DYF field.
	RCC_RCC_MP_CIFR_PLL2DYF_Pos = 0x9
	// Bit mask of PLL2DYF field.
	RCC_RCC_MP_CIFR_PLL2DYF_Msk = 0x200
	// Bit PLL2DYF.
	RCC_RCC_MP_CIFR_PLL2DYF = 0x200
	// Position of PLL3DYF field.
	RCC_RCC_MP_CIFR_PLL3DYF_Pos = 0xa
	// Bit mask of PLL3DYF field.
	RCC_RCC_MP_CIFR_PLL3DYF_Msk = 0x400
	// Bit PLL3DYF.
	RCC_RCC_MP_CIFR_PLL3DYF = 0x400
	// Position of PLL4DYF field.
	RCC_RCC_MP_CIFR_PLL4DYF_Pos = 0xb
	// Bit mask of PLL4DYF field.
	RCC_RCC_MP_CIFR_PLL4DYF_Msk = 0x800
	// Bit PLL4DYF.
	RCC_RCC_MP_CIFR_PLL4DYF = 0x800
	// Position of LSECSSF field.
	RCC_RCC_MP_CIFR_LSECSSF_Pos = 0x10
	// Bit mask of LSECSSF field.
	RCC_RCC_MP_CIFR_LSECSSF_Msk = 0x10000
	// Bit LSECSSF.
	RCC_RCC_MP_CIFR_LSECSSF = 0x10000
	// Position of WKUPF field.
	RCC_RCC_MP_CIFR_WKUPF_Pos = 0x14
	// Bit mask of WKUPF field.
	RCC_RCC_MP_CIFR_WKUPF_Msk = 0x100000
	// Bit WKUPF.
	RCC_RCC_MP_CIFR_WKUPF = 0x100000

	// RCC_PWRLPDLYCR: This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode.
	// Position of PWRLP_DLY field.
	RCC_RCC_PWRLPDLYCR_PWRLP_DLY_Pos = 0x0
	// Bit mask of PWRLP_DLY field.
	RCC_RCC_PWRLPDLYCR_PWRLP_DLY_Msk = 0x3fffff
	// Position of MCTMPSKP field.
	RCC_RCC_PWRLPDLYCR_MCTMPSKP_Pos = 0x18
	// Bit mask of MCTMPSKP field.
	RCC_RCC_PWRLPDLYCR_MCTMPSKP_Msk = 0x1000000
	// Bit MCTMPSKP.
	RCC_RCC_PWRLPDLYCR_MCTMPSKP = 0x1000000

	// RCC_MP_RSTSSETR: This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.
	// Position of PORRSTF field.
	RCC_RCC_MP_RSTSSETR_PORRSTF_Pos = 0x0
	// Bit mask of PORRSTF field.
	RCC_RCC_MP_RSTSSETR_PORRSTF_Msk = 0x1
	// Bit PORRSTF.
	RCC_RCC_MP_RSTSSETR_PORRSTF = 0x1
	// Position of BORRSTF field.
	RCC_RCC_MP_RSTSSETR_BORRSTF_Pos = 0x1
	// Bit mask of BORRSTF field.
	RCC_RCC_MP_RSTSSETR_BORRSTF_Msk = 0x2
	// Bit BORRSTF.
	RCC_RCC_MP_RSTSSETR_BORRSTF = 0x2
	// Position of PADRSTF field.
	RCC_RCC_MP_RSTSSETR_PADRSTF_Pos = 0x2
	// Bit mask of PADRSTF field.
	RCC_RCC_MP_RSTSSETR_PADRSTF_Msk = 0x4
	// Bit PADRSTF.
	RCC_RCC_MP_RSTSSETR_PADRSTF = 0x4
	// Position of HCSSRSTF field.
	RCC_RCC_MP_RSTSSETR_HCSSRSTF_Pos = 0x3
	// Bit mask of HCSSRSTF field.
	RCC_RCC_MP_RSTSSETR_HCSSRSTF_Msk = 0x8
	// Bit HCSSRSTF.
	RCC_RCC_MP_RSTSSETR_HCSSRSTF = 0x8
	// Position of VCORERSTF field.
	RCC_RCC_MP_RSTSSETR_VCORERSTF_Pos = 0x4
	// Bit mask of VCORERSTF field.
	RCC_RCC_MP_RSTSSETR_VCORERSTF_Msk = 0x10
	// Bit VCORERSTF.
	RCC_RCC_MP_RSTSSETR_VCORERSTF = 0x10
	// Position of MPSYSRSTF field.
	RCC_RCC_MP_RSTSSETR_MPSYSRSTF_Pos = 0x6
	// Bit mask of MPSYSRSTF field.
	RCC_RCC_MP_RSTSSETR_MPSYSRSTF_Msk = 0x40
	// Bit MPSYSRSTF.
	RCC_RCC_MP_RSTSSETR_MPSYSRSTF = 0x40
	// Position of MCSYSRSTF field.
	RCC_RCC_MP_RSTSSETR_MCSYSRSTF_Pos = 0x7
	// Bit mask of MCSYSRSTF field.
	RCC_RCC_MP_RSTSSETR_MCSYSRSTF_Msk = 0x80
	// Bit MCSYSRSTF.
	RCC_RCC_MP_RSTSSETR_MCSYSRSTF = 0x80
	// Position of IWDG1RSTF field.
	RCC_RCC_MP_RSTSSETR_IWDG1RSTF_Pos = 0x8
	// Bit mask of IWDG1RSTF field.
	RCC_RCC_MP_RSTSSETR_IWDG1RSTF_Msk = 0x100
	// Bit IWDG1RSTF.
	RCC_RCC_MP_RSTSSETR_IWDG1RSTF = 0x100
	// Position of IWDG2RSTF field.
	RCC_RCC_MP_RSTSSETR_IWDG2RSTF_Pos = 0x9
	// Bit mask of IWDG2RSTF field.
	RCC_RCC_MP_RSTSSETR_IWDG2RSTF_Msk = 0x200
	// Bit IWDG2RSTF.
	RCC_RCC_MP_RSTSSETR_IWDG2RSTF = 0x200
	// Position of STDBYRSTF field.
	RCC_RCC_MP_RSTSSETR_STDBYRSTF_Pos = 0xb
	// Bit mask of STDBYRSTF field.
	RCC_RCC_MP_RSTSSETR_STDBYRSTF_Msk = 0x800
	// Bit STDBYRSTF.
	RCC_RCC_MP_RSTSSETR_STDBYRSTF = 0x800
	// Position of CSTDBYRSTF field.
	RCC_RCC_MP_RSTSSETR_CSTDBYRSTF_Pos = 0xc
	// Bit mask of CSTDBYRSTF field.
	RCC_RCC_MP_RSTSSETR_CSTDBYRSTF_Msk = 0x1000
	// Bit CSTDBYRSTF.
	RCC_RCC_MP_RSTSSETR_CSTDBYRSTF = 0x1000
	// Position of MPUP0RSTF field.
	RCC_RCC_MP_RSTSSETR_MPUP0RSTF_Pos = 0xd
	// Bit mask of MPUP0RSTF field.
	RCC_RCC_MP_RSTSSETR_MPUP0RSTF_Msk = 0x2000
	// Bit MPUP0RSTF.
	RCC_RCC_MP_RSTSSETR_MPUP0RSTF = 0x2000
	// Position of MPUP1RSTF field.
	RCC_RCC_MP_RSTSSETR_MPUP1RSTF_Pos = 0xe
	// Bit mask of MPUP1RSTF field.
	RCC_RCC_MP_RSTSSETR_MPUP1RSTF_Msk = 0x4000
	// Bit MPUP1RSTF.
	RCC_RCC_MP_RSTSSETR_MPUP1RSTF = 0x4000
	// Position of SPARE field.
	RCC_RCC_MP_RSTSSETR_SPARE_Pos = 0xf
	// Bit mask of SPARE field.
	RCC_RCC_MP_RSTSSETR_SPARE_Msk = 0x8000
	// Bit SPARE.
	RCC_RCC_MP_RSTSSETR_SPARE = 0x8000

	// RCC_MCO1CFGR: This register is used to select the clock generated on MCO1 output.
	// Position of MCO1SEL field.
	RCC_RCC_MCO1CFGR_MCO1SEL_Pos = 0x0
	// Bit mask of MCO1SEL field.
	RCC_RCC_MCO1CFGR_MCO1SEL_Msk = 0x7
	// Position of MCO1DIV field.
	RCC_RCC_MCO1CFGR_MCO1DIV_Pos = 0x4
	// Bit mask of MCO1DIV field.
	RCC_RCC_MCO1CFGR_MCO1DIV_Msk = 0xf0
	// Position of MCO1ON field.
	RCC_RCC_MCO1CFGR_MCO1ON_Pos = 0xc
	// Bit mask of MCO1ON field.
	RCC_RCC_MCO1CFGR_MCO1ON_Msk = 0x1000
	// Bit MCO1ON.
	RCC_RCC_MCO1CFGR_MCO1ON = 0x1000

	// RCC_MCO2CFGR: This register is used to select the clock generated on MCO2 output.
	// Position of MCO2SEL field.
	RCC_RCC_MCO2CFGR_MCO2SEL_Pos = 0x0
	// Bit mask of MCO2SEL field.
	RCC_RCC_MCO2CFGR_MCO2SEL_Msk = 0x7
	// Position of MCO2DIV field.
	RCC_RCC_MCO2CFGR_MCO2DIV_Pos = 0x4
	// Bit mask of MCO2DIV field.
	RCC_RCC_MCO2CFGR_MCO2DIV_Msk = 0xf0
	// Position of MCO2ON field.
	RCC_RCC_MCO2CFGR_MCO2ON_Pos = 0xc
	// Bit mask of MCO2ON field.
	RCC_RCC_MCO2CFGR_MCO2ON_Msk = 0x1000
	// Bit MCO2ON.
	RCC_RCC_MCO2CFGR_MCO2ON = 0x1000

	// RCC_OCRDYR: This is a read-only access register, It contains the status flags of oscillators. Writing has no effect.
	// Position of HSIRDY field.
	RCC_RCC_OCRDYR_HSIRDY_Pos = 0x0
	// Bit mask of HSIRDY field.
	RCC_RCC_OCRDYR_HSIRDY_Msk = 0x1
	// Bit HSIRDY.
	RCC_RCC_OCRDYR_HSIRDY = 0x1
	// Position of HSIDIVRDY field.
	RCC_RCC_OCRDYR_HSIDIVRDY_Pos = 0x2
	// Bit mask of HSIDIVRDY field.
	RCC_RCC_OCRDYR_HSIDIVRDY_Msk = 0x4
	// Bit HSIDIVRDY.
	RCC_RCC_OCRDYR_HSIDIVRDY = 0x4
	// Position of CSIRDY field.
	RCC_RCC_OCRDYR_CSIRDY_Pos = 0x4
	// Bit mask of CSIRDY field.
	RCC_RCC_OCRDYR_CSIRDY_Msk = 0x10
	// Bit CSIRDY.
	RCC_RCC_OCRDYR_CSIRDY = 0x10
	// Position of HSERDY field.
	RCC_RCC_OCRDYR_HSERDY_Pos = 0x8
	// Bit mask of HSERDY field.
	RCC_RCC_OCRDYR_HSERDY_Msk = 0x100
	// Bit HSERDY.
	RCC_RCC_OCRDYR_HSERDY = 0x100
	// Position of MPUCKRDY field.
	RCC_RCC_OCRDYR_MPUCKRDY_Pos = 0x17
	// Bit mask of MPUCKRDY field.
	RCC_RCC_OCRDYR_MPUCKRDY_Msk = 0x800000
	// Bit MPUCKRDY.
	RCC_RCC_OCRDYR_MPUCKRDY = 0x800000
	// Position of AXICKRDY field.
	RCC_RCC_OCRDYR_AXICKRDY_Pos = 0x18
	// Bit mask of AXICKRDY field.
	RCC_RCC_OCRDYR_AXICKRDY_Msk = 0x1000000
	// Bit AXICKRDY.
	RCC_RCC_OCRDYR_AXICKRDY = 0x1000000
	// Position of CKREST field.
	RCC_RCC_OCRDYR_CKREST_Pos = 0x19
	// Bit mask of CKREST field.
	RCC_RCC_OCRDYR_CKREST_Msk = 0x2000000
	// Bit CKREST.
	RCC_RCC_OCRDYR_CKREST = 0x2000000

	// RCC_DBGCFGR: This is register contains the enable control of the debug and trace function, and the clock divider for the trace function.
	// Position of TRACEDIV field.
	RCC_RCC_DBGCFGR_TRACEDIV_Pos = 0x0
	// Bit mask of TRACEDIV field.
	RCC_RCC_DBGCFGR_TRACEDIV_Msk = 0x7
	// Position of DBGCKEN field.
	RCC_RCC_DBGCFGR_DBGCKEN_Pos = 0x8
	// Bit mask of DBGCKEN field.
	RCC_RCC_DBGCFGR_DBGCKEN_Msk = 0x100
	// Bit DBGCKEN.
	RCC_RCC_DBGCFGR_DBGCKEN = 0x100
	// Position of TRACECKEN field.
	RCC_RCC_DBGCFGR_TRACECKEN_Pos = 0x9
	// Bit mask of TRACECKEN field.
	RCC_RCC_DBGCFGR_TRACECKEN_Msk = 0x200
	// Bit TRACECKEN.
	RCC_RCC_DBGCFGR_TRACECKEN = 0x200
	// Position of DBGRST field.
	RCC_RCC_DBGCFGR_DBGRST_Pos = 0xc
	// Bit mask of DBGRST field.
	RCC_RCC_DBGCFGR_DBGRST_Msk = 0x1000
	// Bit DBGRST.
	RCC_RCC_DBGCFGR_DBGRST = 0x1000

	// RCC_RCK3SELR: This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
	// Position of PLL3SRC field.
	RCC_RCC_RCK3SELR_PLL3SRC_Pos = 0x0
	// Bit mask of PLL3SRC field.
	RCC_RCC_RCK3SELR_PLL3SRC_Msk = 0x3
	// Position of PLL3SRCRDY field.
	RCC_RCC_RCK3SELR_PLL3SRCRDY_Pos = 0x1f
	// Bit mask of PLL3SRCRDY field.
	RCC_RCC_RCK3SELR_PLL3SRCRDY_Msk = 0x80000000
	// Bit PLL3SRCRDY.
	RCC_RCC_RCK3SELR_PLL3SRCRDY = 0x80000000

	// RCC_RCK4SELR: This register is used to select the reference clock for PLL4.
	// Position of PLL4SRC field.
	RCC_RCC_RCK4SELR_PLL4SRC_Pos = 0x0
	// Bit mask of PLL4SRC field.
	RCC_RCC_RCK4SELR_PLL4SRC_Msk = 0x3
	// Position of PLL4SRCRDY field.
	RCC_RCC_RCK4SELR_PLL4SRCRDY_Pos = 0x1f
	// Bit mask of PLL4SRCRDY field.
	RCC_RCC_RCK4SELR_PLL4SRCRDY_Msk = 0x80000000
	// Bit PLL4SRCRDY.
	RCC_RCC_RCK4SELR_PLL4SRCRDY = 0x80000000

	// RCC_TIMG1PRER: This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information.
	// Position of TIMG1PRE field.
	RCC_RCC_TIMG1PRER_TIMG1PRE_Pos = 0x0
	// Bit mask of TIMG1PRE field.
	RCC_RCC_TIMG1PRER_TIMG1PRE_Msk = 0x1
	// Bit TIMG1PRE.
	RCC_RCC_TIMG1PRER_TIMG1PRE = 0x1
	// Position of TIMG1PRERDY field.
	RCC_RCC_TIMG1PRER_TIMG1PRERDY_Pos = 0x1f
	// Bit mask of TIMG1PRERDY field.
	RCC_RCC_TIMG1PRER_TIMG1PRERDY_Msk = 0x80000000
	// Bit TIMG1PRERDY.
	RCC_RCC_TIMG1PRER_TIMG1PRERDY = 0x80000000

	// RCC_TIMG2PRER: This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information.
	// Position of TIMG2PRE field.
	RCC_RCC_TIMG2PRER_TIMG2PRE_Pos = 0x0
	// Bit mask of TIMG2PRE field.
	RCC_RCC_TIMG2PRER_TIMG2PRE_Msk = 0x1
	// Bit TIMG2PRE.
	RCC_RCC_TIMG2PRER_TIMG2PRE = 0x1
	// Position of TIMG2PRERDY field.
	RCC_RCC_TIMG2PRER_TIMG2PRERDY_Pos = 0x1f
	// Bit mask of TIMG2PRERDY field.
	RCC_RCC_TIMG2PRER_TIMG2PRERDY_Msk = 0x80000000
	// Bit TIMG2PRERDY.
	RCC_RCC_TIMG2PRER_TIMG2PRERDY = 0x80000000

	// RCC_MCUDIVR: This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
	// Position of MCUDIV field.
	RCC_RCC_MCUDIVR_MCUDIV_Pos = 0x0
	// Bit mask of MCUDIV field.
	RCC_RCC_MCUDIVR_MCUDIV_Msk = 0xf
	// Position of MCUDIVRDY field.
	RCC_RCC_MCUDIVR_MCUDIVRDY_Pos = 0x1f
	// Bit mask of MCUDIVRDY field.
	RCC_RCC_MCUDIVR_MCUDIVRDY_Msk = 0x80000000
	// Bit MCUDIVRDY.
	RCC_RCC_MCUDIVR_MCUDIVRDY = 0x80000000

	// RCC_APB1DIVR: This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information.
	// Position of APB1DIV field.
	RCC_RCC_APB1DIVR_APB1DIV_Pos = 0x0
	// Bit mask of APB1DIV field.
	RCC_RCC_APB1DIVR_APB1DIV_Msk = 0x7
	// Position of APB1DIVRDY field.
	RCC_RCC_APB1DIVR_APB1DIVRDY_Pos = 0x1f
	// Bit mask of APB1DIVRDY field.
	RCC_RCC_APB1DIVR_APB1DIVRDY_Msk = 0x80000000
	// Bit APB1DIVRDY.
	RCC_RCC_APB1DIVR_APB1DIVRDY = 0x80000000

	// RCC_APB2DIVR: This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information.
	// Position of APB2DIV field.
	RCC_RCC_APB2DIVR_APB2DIV_Pos = 0x0
	// Bit mask of APB2DIV field.
	RCC_RCC_APB2DIVR_APB2DIV_Msk = 0x7
	// Position of APB2DIVRDY field.
	RCC_RCC_APB2DIVR_APB2DIVRDY_Pos = 0x1f
	// Bit mask of APB2DIVRDY field.
	RCC_RCC_APB2DIVR_APB2DIVRDY_Msk = 0x80000000
	// Bit APB2DIVRDY.
	RCC_RCC_APB2DIVR_APB2DIVRDY = 0x80000000

	// RCC_APB3DIVR: This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information.
	// Position of APB3DIV field.
	RCC_RCC_APB3DIVR_APB3DIV_Pos = 0x0
	// Bit mask of APB3DIV field.
	RCC_RCC_APB3DIVR_APB3DIV_Msk = 0x7
	// Position of APB3DIVRDY field.
	RCC_RCC_APB3DIVR_APB3DIVRDY_Pos = 0x1f
	// Bit mask of APB3DIVRDY field.
	RCC_RCC_APB3DIVR_APB3DIVRDY_Msk = 0x80000000
	// Bit APB3DIVRDY.
	RCC_RCC_APB3DIVR_APB3DIVRDY = 0x80000000

	// RCC_PLL3CR: This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
	// Position of PLLON field.
	RCC_RCC_PLL3CR_PLLON_Pos = 0x0
	// Bit mask of PLLON field.
	RCC_RCC_PLL3CR_PLLON_Msk = 0x1
	// Bit PLLON.
	RCC_RCC_PLL3CR_PLLON = 0x1
	// Position of PLL3RDY field.
	RCC_RCC_PLL3CR_PLL3RDY_Pos = 0x1
	// Bit mask of PLL3RDY field.
	RCC_RCC_PLL3CR_PLL3RDY_Msk = 0x2
	// Bit PLL3RDY.
	RCC_RCC_PLL3CR_PLL3RDY = 0x2
	// Position of SSCG_CTRL field.
	RCC_RCC_PLL3CR_SSCG_CTRL_Pos = 0x2
	// Bit mask of SSCG_CTRL field.
	RCC_RCC_PLL3CR_SSCG_CTRL_Msk = 0x4
	// Bit SSCG_CTRL.
	RCC_RCC_PLL3CR_SSCG_CTRL = 0x4
	// Position of DIVPEN field.
	RCC_RCC_PLL3CR_DIVPEN_Pos = 0x4
	// Bit mask of DIVPEN field.
	RCC_RCC_PLL3CR_DIVPEN_Msk = 0x10
	// Bit DIVPEN.
	RCC_RCC_PLL3CR_DIVPEN = 0x10
	// Position of DIVQEN field.
	RCC_RCC_PLL3CR_DIVQEN_Pos = 0x5
	// Bit mask of DIVQEN field.
	RCC_RCC_PLL3CR_DIVQEN_Msk = 0x20
	// Bit DIVQEN.
	RCC_RCC_PLL3CR_DIVQEN = 0x20
	// Position of DIVREN field.
	RCC_RCC_PLL3CR_DIVREN_Pos = 0x6
	// Bit mask of DIVREN field.
	RCC_RCC_PLL3CR_DIVREN_Msk = 0x40
	// Bit DIVREN.
	RCC_RCC_PLL3CR_DIVREN = 0x40

	// RCC_PLL3CFGR1: This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
	// Position of DIVN field.
	RCC_RCC_PLL3CFGR1_DIVN_Pos = 0x0
	// Bit mask of DIVN field.
	RCC_RCC_PLL3CFGR1_DIVN_Msk = 0x1ff
	// Position of DIVM3 field.
	RCC_RCC_PLL3CFGR1_DIVM3_Pos = 0x10
	// Bit mask of DIVM3 field.
	RCC_RCC_PLL3CFGR1_DIVM3_Msk = 0x3f0000
	// Position of IFRGE field.
	RCC_RCC_PLL3CFGR1_IFRGE_Pos = 0x18
	// Bit mask of IFRGE field.
	RCC_RCC_PLL3CFGR1_IFRGE_Msk = 0x3000000

	// RCC_PLL3CFGR2: This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
	// Position of DIVP field.
	RCC_RCC_PLL3CFGR2_DIVP_Pos = 0x0
	// Bit mask of DIVP field.
	RCC_RCC_PLL3CFGR2_DIVP_Msk = 0x7f
	// Position of DIVQ field.
	RCC_RCC_PLL3CFGR2_DIVQ_Pos = 0x8
	// Bit mask of DIVQ field.
	RCC_RCC_PLL3CFGR2_DIVQ_Msk = 0x7f00
	// Position of DIVR field.
	RCC_RCC_PLL3CFGR2_DIVR_Pos = 0x10
	// Bit mask of DIVR field.
	RCC_RCC_PLL3CFGR2_DIVR_Msk = 0x7f0000

	// RCC_PLL3FRACR: This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode.
	// Position of FRACV field.
	RCC_RCC_PLL3FRACR_FRACV_Pos = 0x3
	// Bit mask of FRACV field.
	RCC_RCC_PLL3FRACR_FRACV_Msk = 0xfff8
	// Position of FRACLE field.
	RCC_RCC_PLL3FRACR_FRACLE_Pos = 0x10
	// Bit mask of FRACLE field.
	RCC_RCC_PLL3FRACR_FRACLE_Msk = 0x10000
	// Bit FRACLE.
	RCC_RCC_PLL3FRACR_FRACLE = 0x10000

	// RCC_PLL3CSGR: This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
	// Position of MOD_PER field.
	RCC_RCC_PLL3CSGR_MOD_PER_Pos = 0x0
	// Bit mask of MOD_PER field.
	RCC_RCC_PLL3CSGR_MOD_PER_Msk = 0x1fff
	// Position of TPDFN_DIS field.
	RCC_RCC_PLL3CSGR_TPDFN_DIS_Pos = 0xd
	// Bit mask of TPDFN_DIS field.
	RCC_RCC_PLL3CSGR_TPDFN_DIS_Msk = 0x2000
	// Bit TPDFN_DIS.
	RCC_RCC_PLL3CSGR_TPDFN_DIS = 0x2000
	// Position of RPDFN_DIS field.
	RCC_RCC_PLL3CSGR_RPDFN_DIS_Pos = 0xe
	// Bit mask of RPDFN_DIS field.
	RCC_RCC_PLL3CSGR_RPDFN_DIS_Msk = 0x4000
	// Bit RPDFN_DIS.
	RCC_RCC_PLL3CSGR_RPDFN_DIS = 0x4000
	// Position of SSCG_MODE field.
	RCC_RCC_PLL3CSGR_SSCG_MODE_Pos = 0xf
	// Bit mask of SSCG_MODE field.
	RCC_RCC_PLL3CSGR_SSCG_MODE_Msk = 0x8000
	// Bit SSCG_MODE.
	RCC_RCC_PLL3CSGR_SSCG_MODE = 0x8000
	// Position of INC_STEP field.
	RCC_RCC_PLL3CSGR_INC_STEP_Pos = 0x10
	// Bit mask of INC_STEP field.
	RCC_RCC_PLL3CSGR_INC_STEP_Msk = 0x7fff0000

	// RCC_PLL4CR: This register is used to control the PLL4.
	// Position of PLLON field.
	RCC_RCC_PLL4CR_PLLON_Pos = 0x0
	// Bit mask of PLLON field.
	RCC_RCC_PLL4CR_PLLON_Msk = 0x1
	// Bit PLLON.
	RCC_RCC_PLL4CR_PLLON = 0x1
	// Position of PLL4RDY field.
	RCC_RCC_PLL4CR_PLL4RDY_Pos = 0x1
	// Bit mask of PLL4RDY field.
	RCC_RCC_PLL4CR_PLL4RDY_Msk = 0x2
	// Bit PLL4RDY.
	RCC_RCC_PLL4CR_PLL4RDY = 0x2
	// Position of SSCG_CTRL field.
	RCC_RCC_PLL4CR_SSCG_CTRL_Pos = 0x2
	// Bit mask of SSCG_CTRL field.
	RCC_RCC_PLL4CR_SSCG_CTRL_Msk = 0x4
	// Bit SSCG_CTRL.
	RCC_RCC_PLL4CR_SSCG_CTRL = 0x4
	// Position of DIVPEN field.
	RCC_RCC_PLL4CR_DIVPEN_Pos = 0x4
	// Bit mask of DIVPEN field.
	RCC_RCC_PLL4CR_DIVPEN_Msk = 0x10
	// Bit DIVPEN.
	RCC_RCC_PLL4CR_DIVPEN = 0x10
	// Position of DIVQEN field.
	RCC_RCC_PLL4CR_DIVQEN_Pos = 0x5
	// Bit mask of DIVQEN field.
	RCC_RCC_PLL4CR_DIVQEN_Msk = 0x20
	// Bit DIVQEN.
	RCC_RCC_PLL4CR_DIVQEN = 0x20
	// Position of DIVREN field.
	RCC_RCC_PLL4CR_DIVREN_Pos = 0x6
	// Bit mask of DIVREN field.
	RCC_RCC_PLL4CR_DIVREN_Msk = 0x40
	// Bit DIVREN.
	RCC_RCC_PLL4CR_DIVREN = 0x40

	// RCC_PLL4CFGR1: This register is used to configure the PLL4.
	// Position of DIVN field.
	RCC_RCC_PLL4CFGR1_DIVN_Pos = 0x0
	// Bit mask of DIVN field.
	RCC_RCC_PLL4CFGR1_DIVN_Msk = 0x1ff
	// Position of DIVM4 field.
	RCC_RCC_PLL4CFGR1_DIVM4_Pos = 0x10
	// Bit mask of DIVM4 field.
	RCC_RCC_PLL4CFGR1_DIVM4_Msk = 0x3f0000
	// Position of IFRGE field.
	RCC_RCC_PLL4CFGR1_IFRGE_Pos = 0x18
	// Bit mask of IFRGE field.
	RCC_RCC_PLL4CFGR1_IFRGE_Msk = 0x3000000

	// RCC_PLL4CFGR2: This register is used to configure the PLL4.
	// Position of DIVP field.
	RCC_RCC_PLL4CFGR2_DIVP_Pos = 0x0
	// Bit mask of DIVP field.
	RCC_RCC_PLL4CFGR2_DIVP_Msk = 0x7f
	// Position of DIVQ field.
	RCC_RCC_PLL4CFGR2_DIVQ_Pos = 0x8
	// Bit mask of DIVQ field.
	RCC_RCC_PLL4CFGR2_DIVQ_Msk = 0x7f00
	// Position of DIVR field.
	RCC_RCC_PLL4CFGR2_DIVR_Pos = 0x10
	// Bit mask of DIVR field.
	RCC_RCC_PLL4CFGR2_DIVR_Msk = 0x7f0000

	// RCC_PLL4FRACR: This register is used to fine-tune the frequency of the PLL4 VCO.
	// Position of FRACV field.
	RCC_RCC_PLL4FRACR_FRACV_Pos = 0x3
	// Bit mask of FRACV field.
	RCC_RCC_PLL4FRACR_FRACV_Msk = 0xfff8
	// Position of FRACLE field.
	RCC_RCC_PLL4FRACR_FRACLE_Pos = 0x10
	// Bit mask of FRACLE field.
	RCC_RCC_PLL4FRACR_FRACLE_Msk = 0x10000
	// Bit FRACLE.
	RCC_RCC_PLL4FRACR_FRACLE = 0x10000

	// RCC_PLL4CSGR: This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
	// Position of MOD_PER field.
	RCC_RCC_PLL4CSGR_MOD_PER_Pos = 0x0
	// Bit mask of MOD_PER field.
	RCC_RCC_PLL4CSGR_MOD_PER_Msk = 0x1fff
	// Position of TPDFN_DIS field.
	RCC_RCC_PLL4CSGR_TPDFN_DIS_Pos = 0xd
	// Bit mask of TPDFN_DIS field.
	RCC_RCC_PLL4CSGR_TPDFN_DIS_Msk = 0x2000
	// Bit TPDFN_DIS.
	RCC_RCC_PLL4CSGR_TPDFN_DIS = 0x2000
	// Position of RPDFN_DIS field.
	RCC_RCC_PLL4CSGR_RPDFN_DIS_Pos = 0xe
	// Bit mask of RPDFN_DIS field.
	RCC_RCC_PLL4CSGR_RPDFN_DIS_Msk = 0x4000
	// Bit RPDFN_DIS.
	RCC_RCC_PLL4CSGR_RPDFN_DIS = 0x4000
	// Position of SSCG_MODE field.
	RCC_RCC_PLL4CSGR_SSCG_MODE_Pos = 0xf
	// Bit mask of SSCG_MODE field.
	RCC_RCC_PLL4CSGR_SSCG_MODE_Msk = 0x8000
	// Bit SSCG_MODE.
	RCC_RCC_PLL4CSGR_SSCG_MODE = 0x8000
	// Position of INC_STEP field.
	RCC_RCC_PLL4CSGR_INC_STEP_Pos = 0x10
	// Bit mask of INC_STEP field.
	RCC_RCC_PLL4CSGR_INC_STEP_Msk = 0x7fff0000

	// RCC_I2C12CKSELR: This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of I2C12SRC field.
	RCC_RCC_I2C12CKSELR_I2C12SRC_Pos = 0x0
	// Bit mask of I2C12SRC field.
	RCC_RCC_I2C12CKSELR_I2C12SRC_Msk = 0x7

	// RCC_I2C35CKSELR: This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of I2C35SRC field.
	RCC_RCC_I2C35CKSELR_I2C35SRC_Pos = 0x0
	// Bit mask of I2C35SRC field.
	RCC_RCC_I2C35CKSELR_I2C35SRC_Msk = 0x7

	// RCC_SAI1CKSELR: This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SAI1SRC field.
	RCC_RCC_SAI1CKSELR_SAI1SRC_Pos = 0x0
	// Bit mask of SAI1SRC field.
	RCC_RCC_SAI1CKSELR_SAI1SRC_Msk = 0x7

	// RCC_SAI2CKSELR: This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SAI2SRC field.
	RCC_RCC_SAI2CKSELR_SAI2SRC_Pos = 0x0
	// Bit mask of SAI2SRC field.
	RCC_RCC_SAI2CKSELR_SAI2SRC_Msk = 0x7

	// RCC_SAI3CKSELR: This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SAI3SRC field.
	RCC_RCC_SAI3CKSELR_SAI3SRC_Pos = 0x0
	// Bit mask of SAI3SRC field.
	RCC_RCC_SAI3CKSELR_SAI3SRC_Msk = 0x7

	// RCC_SAI4CKSELR: This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SAI4SRC field.
	RCC_RCC_SAI4CKSELR_SAI4SRC_Pos = 0x0
	// Bit mask of SAI4SRC field.
	RCC_RCC_SAI4CKSELR_SAI4SRC_Msk = 0x7

	// RCC_SPI2S1CKSELR: This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SPI1SRC field.
	RCC_RCC_SPI2S1CKSELR_SPI1SRC_Pos = 0x0
	// Bit mask of SPI1SRC field.
	RCC_RCC_SPI2S1CKSELR_SPI1SRC_Msk = 0x7

	// RCC_SPI2S23CKSELR: This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SPI23SRC field.
	RCC_RCC_SPI2S23CKSELR_SPI23SRC_Pos = 0x0
	// Bit mask of SPI23SRC field.
	RCC_RCC_SPI2S23CKSELR_SPI23SRC_Msk = 0x7

	// RCC_SPI45CKSELR: This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SPI45SRC field.
	RCC_RCC_SPI45CKSELR_SPI45SRC_Pos = 0x0
	// Bit mask of SPI45SRC field.
	RCC_RCC_SPI45CKSELR_SPI45SRC_Msk = 0x7

	// RCC_UART6CKSELR: This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of UART6SRC field.
	RCC_RCC_UART6CKSELR_UART6SRC_Pos = 0x0
	// Bit mask of UART6SRC field.
	RCC_RCC_UART6CKSELR_UART6SRC_Msk = 0x7

	// RCC_UART24CKSELR: This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of UART24SRC field.
	RCC_RCC_UART24CKSELR_UART24SRC_Pos = 0x0
	// Bit mask of UART24SRC field.
	RCC_RCC_UART24CKSELR_UART24SRC_Msk = 0x7

	// RCC_UART35CKSELR: This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of UART35SRC field.
	RCC_RCC_UART35CKSELR_UART35SRC_Pos = 0x0
	// Bit mask of UART35SRC field.
	RCC_RCC_UART35CKSELR_UART35SRC_Msk = 0x7

	// RCC_UART78CKSELR: This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of UART78SRC field.
	RCC_RCC_UART78CKSELR_UART78SRC_Pos = 0x0
	// Bit mask of UART78SRC field.
	RCC_RCC_UART78CKSELR_UART78SRC_Msk = 0x7

	// RCC_SDMMC12CKSELR: This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SDMMC12SRC field.
	RCC_RCC_SDMMC12CKSELR_SDMMC12SRC_Pos = 0x0
	// Bit mask of SDMMC12SRC field.
	RCC_RCC_SDMMC12CKSELR_SDMMC12SRC_Msk = 0x7

	// RCC_SDMMC3CKSELR: This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SDMMC3SRC field.
	RCC_RCC_SDMMC3CKSELR_SDMMC3SRC_Pos = 0x0
	// Bit mask of SDMMC3SRC field.
	RCC_RCC_SDMMC3CKSELR_SDMMC3SRC_Msk = 0x7

	// RCC_ETHCKSELR: This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of ETHSRC field.
	RCC_RCC_ETHCKSELR_ETHSRC_Pos = 0x0
	// Bit mask of ETHSRC field.
	RCC_RCC_ETHCKSELR_ETHSRC_Msk = 0x3
	// Position of ETHPTPDIV field.
	RCC_RCC_ETHCKSELR_ETHPTPDIV_Pos = 0x4
	// Bit mask of ETHPTPDIV field.
	RCC_RCC_ETHCKSELR_ETHPTPDIV_Msk = 0xf0

	// RCC_QSPICKSELR: This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of QSPISRC field.
	RCC_RCC_QSPICKSELR_QSPISRC_Pos = 0x0
	// Bit mask of QSPISRC field.
	RCC_RCC_QSPICKSELR_QSPISRC_Msk = 0x3

	// RCC_FMCCKSELR: This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of FMCSRC field.
	RCC_RCC_FMCCKSELR_FMCSRC_Pos = 0x0
	// Bit mask of FMCSRC field.
	RCC_RCC_FMCCKSELR_FMCSRC_Msk = 0x3

	// RCC_FDCANCKSELR: This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of FDCANSRC field.
	RCC_RCC_FDCANCKSELR_FDCANSRC_Pos = 0x0
	// Bit mask of FDCANSRC field.
	RCC_RCC_FDCANCKSELR_FDCANSRC_Msk = 0x3

	// RCC_SPDIFCKSELR: This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
	// Position of SPDIFSRC field.
	RCC_RCC_SPDIFCKSELR_SPDIFSRC_Pos = 0x0
	// Bit mask of SPDIFSRC field.
	RCC_RCC_SPDIFCKSELR_SPDIFSRC_Msk = 0x3

	// RCC_CECCKSELR: This register is used to control the selection of the kernel clock for the CEC-HDMI.
	// Position of CECSRC field.
	RCC_RCC_CECCKSELR_CECSRC_Pos = 0x0
	// Bit mask of CECSRC field.
	RCC_RCC_CECCKSELR_CECSRC_Msk = 0x3

	// RCC_USBCKSELR: This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG
	// Position of USBPHYSRC field.
	RCC_RCC_USBCKSELR_USBPHYSRC_Pos = 0x0
	// Bit mask of USBPHYSRC field.
	RCC_RCC_USBCKSELR_USBPHYSRC_Msk = 0x3
	// Position of USBOSRC field.
	RCC_RCC_USBCKSELR_USBOSRC_Pos = 0x4
	// Bit mask of USBOSRC field.
	RCC_RCC_USBCKSELR_USBOSRC_Msk = 0x10
	// Bit USBOSRC.
	RCC_RCC_USBCKSELR_USBOSRC = 0x10

	// RCC_RNG2CKSELR: This register is used to control the selection of the kernel clock for the RNG2.
	// Position of RNG2SRC field.
	RCC_RCC_RNG2CKSELR_RNG2SRC_Pos = 0x0
	// Bit mask of RNG2SRC field.
	RCC_RCC_RNG2CKSELR_RNG2SRC_Msk = 0x3

	// RCC_DSICKSELR: This register is used to control the selection of the kernel clock for the DSI block.
	// Position of DSISRC field.
	RCC_RCC_DSICKSELR_DSISRC_Pos = 0x0
	// Bit mask of DSISRC field.
	RCC_RCC_DSICKSELR_DSISRC_Msk = 0x1
	// Bit DSISRC.
	RCC_RCC_DSICKSELR_DSISRC = 0x1

	// RCC_ADCCKSELR: This register is used to control the selection of the kernel clock for the ADC block.
	// Position of ADCSRC field.
	RCC_RCC_ADCCKSELR_ADCSRC_Pos = 0x0
	// Bit mask of ADCSRC field.
	RCC_RCC_ADCCKSELR_ADCSRC_Msk = 0x3

	// RCC_LPTIM45CKSELR: This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks.
	// Position of LPTIM45SRC field.
	RCC_RCC_LPTIM45CKSELR_LPTIM45SRC_Pos = 0x0
	// Bit mask of LPTIM45SRC field.
	RCC_RCC_LPTIM45CKSELR_LPTIM45SRC_Msk = 0x7

	// RCC_LPTIM23CKSELR: This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks.
	// Position of LPTIM23SRC field.
	RCC_RCC_LPTIM23CKSELR_LPTIM23SRC_Pos = 0x0
	// Bit mask of LPTIM23SRC field.
	RCC_RCC_LPTIM23CKSELR_LPTIM23SRC_Msk = 0x7

	// RCC_LPTIM1CKSELR: This register is used to control the selection of the kernel clock for the LPTIM1 block.
	// Position of LPTIM1SRC field.
	RCC_RCC_LPTIM1CKSELR_LPTIM1SRC_Pos = 0x0
	// Bit mask of LPTIM1SRC field.
	RCC_RCC_LPTIM1CKSELR_LPTIM1SRC_Msk = 0x7

	// RCC_APB1RSTSETR: This register is used to activate the reset of the corresponding peripheral.
	// Position of TIM2RST field.
	RCC_RCC_APB1RSTSETR_TIM2RST_Pos = 0x0
	// Bit mask of TIM2RST field.
	RCC_RCC_APB1RSTSETR_TIM2RST_Msk = 0x1
	// Bit TIM2RST.
	RCC_RCC_APB1RSTSETR_TIM2RST = 0x1
	// Position of TIM3RST field.
	RCC_RCC_APB1RSTSETR_TIM3RST_Pos = 0x1
	// Bit mask of TIM3RST field.
	RCC_RCC_APB1RSTSETR_TIM3RST_Msk = 0x2
	// Bit TIM3RST.
	RCC_RCC_APB1RSTSETR_TIM3RST = 0x2
	// Position of TIM4RST field.
	RCC_RCC_APB1RSTSETR_TIM4RST_Pos = 0x2
	// Bit mask of TIM4RST field.
	RCC_RCC_APB1RSTSETR_TIM4RST_Msk = 0x4
	// Bit TIM4RST.
	RCC_RCC_APB1RSTSETR_TIM4RST = 0x4
	// Position of TIM5RST field.
	RCC_RCC_APB1RSTSETR_TIM5RST_Pos = 0x3
	// Bit mask of TIM5RST field.
	RCC_RCC_APB1RSTSETR_TIM5RST_Msk = 0x8
	// Bit TIM5RST.
	RCC_RCC_APB1RSTSETR_TIM5RST = 0x8
	// Position of TIM6RST field.
	RCC_RCC_APB1RSTSETR_TIM6RST_Pos = 0x4
	// Bit mask of TIM6RST field.
	RCC_RCC_APB1RSTSETR_TIM6RST_Msk = 0x10
	// Bit TIM6RST.
	RCC_RCC_APB1RSTSETR_TIM6RST = 0x10
	// Position of TIM7RST field.
	RCC_RCC_APB1RSTSETR_TIM7RST_Pos = 0x5
	// Bit mask of TIM7RST field.
	RCC_RCC_APB1RSTSETR_TIM7RST_Msk = 0x20
	// Bit TIM7RST.
	RCC_RCC_APB1RSTSETR_TIM7RST = 0x20
	// Position of TIM12RST field.
	RCC_RCC_APB1RSTSETR_TIM12RST_Pos = 0x6
	// Bit mask of TIM12RST field.
	RCC_RCC_APB1RSTSETR_TIM12RST_Msk = 0x40
	// Bit TIM12RST.
	RCC_RCC_APB1RSTSETR_TIM12RST = 0x40
	// Position of TIM13RST field.
	RCC_RCC_APB1RSTSETR_TIM13RST_Pos = 0x7
	// Bit mask of TIM13RST field.
	RCC_RCC_APB1RSTSETR_TIM13RST_Msk = 0x80
	// Bit TIM13RST.
	RCC_RCC_APB1RSTSETR_TIM13RST = 0x80
	// Position of TIM14RST field.
	RCC_RCC_APB1RSTSETR_TIM14RST_Pos = 0x8
	// Bit mask of TIM14RST field.
	RCC_RCC_APB1RSTSETR_TIM14RST_Msk = 0x100
	// Bit TIM14RST.
	RCC_RCC_APB1RSTSETR_TIM14RST = 0x100
	// Position of LPTIM1RST field.
	RCC_RCC_APB1RSTSETR_LPTIM1RST_Pos = 0x9
	// Bit mask of LPTIM1RST field.
	RCC_RCC_APB1RSTSETR_LPTIM1RST_Msk = 0x200
	// Bit LPTIM1RST.
	RCC_RCC_APB1RSTSETR_LPTIM1RST = 0x200
	// Position of SPI2RST field.
	RCC_RCC_APB1RSTSETR_SPI2RST_Pos = 0xb
	// Bit mask of SPI2RST field.
	RCC_RCC_APB1RSTSETR_SPI2RST_Msk = 0x800
	// Bit SPI2RST.
	RCC_RCC_APB1RSTSETR_SPI2RST = 0x800
	// Position of SPI3RST field.
	RCC_RCC_APB1RSTSETR_SPI3RST_Pos = 0xc
	// Bit mask of SPI3RST field.
	RCC_RCC_APB1RSTSETR_SPI3RST_Msk = 0x1000
	// Bit SPI3RST.
	RCC_RCC_APB1RSTSETR_SPI3RST = 0x1000
	// Position of USART2RST field.
	RCC_RCC_APB1RSTSETR_USART2RST_Pos = 0xe
	// Bit mask of USART2RST field.
	RCC_RCC_APB1RSTSETR_USART2RST_Msk = 0x4000
	// Bit USART2RST.
	RCC_RCC_APB1RSTSETR_USART2RST = 0x4000
	// Position of USART3RST field.
	RCC_RCC_APB1RSTSETR_USART3RST_Pos = 0xf
	// Bit mask of USART3RST field.
	RCC_RCC_APB1RSTSETR_USART3RST_Msk = 0x8000
	// Bit USART3RST.
	RCC_RCC_APB1RSTSETR_USART3RST = 0x8000
	// Position of UART4RST field.
	RCC_RCC_APB1RSTSETR_UART4RST_Pos = 0x10
	// Bit mask of UART4RST field.
	RCC_RCC_APB1RSTSETR_UART4RST_Msk = 0x10000
	// Bit UART4RST.
	RCC_RCC_APB1RSTSETR_UART4RST = 0x10000
	// Position of UART5RST field.
	RCC_RCC_APB1RSTSETR_UART5RST_Pos = 0x11
	// Bit mask of UART5RST field.
	RCC_RCC_APB1RSTSETR_UART5RST_Msk = 0x20000
	// Bit UART5RST.
	RCC_RCC_APB1RSTSETR_UART5RST = 0x20000
	// Position of UART7RST field.
	RCC_RCC_APB1RSTSETR_UART7RST_Pos = 0x12
	// Bit mask of UART7RST field.
	RCC_RCC_APB1RSTSETR_UART7RST_Msk = 0x40000
	// Bit UART7RST.
	RCC_RCC_APB1RSTSETR_UART7RST = 0x40000
	// Position of UART8RST field.
	RCC_RCC_APB1RSTSETR_UART8RST_Pos = 0x13
	// Bit mask of UART8RST field.
	RCC_RCC_APB1RSTSETR_UART8RST_Msk = 0x80000
	// Bit UART8RST.
	RCC_RCC_APB1RSTSETR_UART8RST = 0x80000
	// Position of I2C1RST field.
	RCC_RCC_APB1RSTSETR_I2C1RST_Pos = 0x15
	// Bit mask of I2C1RST field.
	RCC_RCC_APB1RSTSETR_I2C1RST_Msk = 0x200000
	// Bit I2C1RST.
	RCC_RCC_APB1RSTSETR_I2C1RST = 0x200000
	// Position of I2C2RST field.
	RCC_RCC_APB1RSTSETR_I2C2RST_Pos = 0x16
	// Bit mask of I2C2RST field.
	RCC_RCC_APB1RSTSETR_I2C2RST_Msk = 0x400000
	// Bit I2C2RST.
	RCC_RCC_APB1RSTSETR_I2C2RST = 0x400000
	// Position of I2C3RST field.
	RCC_RCC_APB1RSTSETR_I2C3RST_Pos = 0x17
	// Bit mask of I2C3RST field.
	RCC_RCC_APB1RSTSETR_I2C3RST_Msk = 0x800000
	// Bit I2C3RST.
	RCC_RCC_APB1RSTSETR_I2C3RST = 0x800000
	// Position of I2C5RST field.
	RCC_RCC_APB1RSTSETR_I2C5RST_Pos = 0x18
	// Bit mask of I2C5RST field.
	RCC_RCC_APB1RSTSETR_I2C5RST_Msk = 0x1000000
	// Bit I2C5RST.
	RCC_RCC_APB1RSTSETR_I2C5RST = 0x1000000
	// Position of SPDIFRST field.
	RCC_RCC_APB1RSTSETR_SPDIFRST_Pos = 0x1a
	// Bit mask of SPDIFRST field.
	RCC_RCC_APB1RSTSETR_SPDIFRST_Msk = 0x4000000
	// Bit SPDIFRST.
	RCC_RCC_APB1RSTSETR_SPDIFRST = 0x4000000
	// Position of CECRST field.
	RCC_RCC_APB1RSTSETR_CECRST_Pos = 0x1b
	// Bit mask of CECRST field.
	RCC_RCC_APB1RSTSETR_CECRST_Msk = 0x8000000
	// Bit CECRST.
	RCC_RCC_APB1RSTSETR_CECRST = 0x8000000
	// Position of DAC12RST field.
	RCC_RCC_APB1RSTSETR_DAC12RST_Pos = 0x1d
	// Bit mask of DAC12RST field.
	RCC_RCC_APB1RSTSETR_DAC12RST_Msk = 0x20000000
	// Bit DAC12RST.
	RCC_RCC_APB1RSTSETR_DAC12RST = 0x20000000
	// Position of MDIOSRST field.
	RCC_RCC_APB1RSTSETR_MDIOSRST_Pos = 0x1f
	// Bit mask of MDIOSRST field.
	RCC_RCC_APB1RSTSETR_MDIOSRST_Msk = 0x80000000
	// Bit MDIOSRST.
	RCC_RCC_APB1RSTSETR_MDIOSRST = 0x80000000

	// RCC_APB1RSTCLRR: This register is used to release the reset of the corresponding peripheral.
	// Position of TIM2RST field.
	RCC_RCC_APB1RSTCLRR_TIM2RST_Pos = 0x0
	// Bit mask of TIM2RST field.
	RCC_RCC_APB1RSTCLRR_TIM2RST_Msk = 0x1
	// Bit TIM2RST.
	RCC_RCC_APB1RSTCLRR_TIM2RST = 0x1
	// Position of TIM3RST field.
	RCC_RCC_APB1RSTCLRR_TIM3RST_Pos = 0x1
	// Bit mask of TIM3RST field.
	RCC_RCC_APB1RSTCLRR_TIM3RST_Msk = 0x2
	// Bit TIM3RST.
	RCC_RCC_APB1RSTCLRR_TIM3RST = 0x2
	// Position of TIM4RST field.
	RCC_RCC_APB1RSTCLRR_TIM4RST_Pos = 0x2
	// Bit mask of TIM4RST field.
	RCC_RCC_APB1RSTCLRR_TIM4RST_Msk = 0x4
	// Bit TIM4RST.
	RCC_RCC_APB1RSTCLRR_TIM4RST = 0x4
	// Position of TIM5RST field.
	RCC_RCC_APB1RSTCLRR_TIM5RST_Pos = 0x3
	// Bit mask of TIM5RST field.
	RCC_RCC_APB1RSTCLRR_TIM5RST_Msk = 0x8
	// Bit TIM5RST.
	RCC_RCC_APB1RSTCLRR_TIM5RST = 0x8
	// Position of TIM6RST field.
	RCC_RCC_APB1RSTCLRR_TIM6RST_Pos = 0x4
	// Bit mask of TIM6RST field.
	RCC_RCC_APB1RSTCLRR_TIM6RST_Msk = 0x10
	// Bit TIM6RST.
	RCC_RCC_APB1RSTCLRR_TIM6RST = 0x10
	// Position of TIM7RST field.
	RCC_RCC_APB1RSTCLRR_TIM7RST_Pos = 0x5
	// Bit mask of TIM7RST field.
	RCC_RCC_APB1RSTCLRR_TIM7RST_Msk = 0x20
	// Bit TIM7RST.
	RCC_RCC_APB1RSTCLRR_TIM7RST = 0x20
	// Position of TIM12RST field.
	RCC_RCC_APB1RSTCLRR_TIM12RST_Pos = 0x6
	// Bit mask of TIM12RST field.
	RCC_RCC_APB1RSTCLRR_TIM12RST_Msk = 0x40
	// Bit TIM12RST.
	RCC_RCC_APB1RSTCLRR_TIM12RST = 0x40
	// Position of TIM13RST field.
	RCC_RCC_APB1RSTCLRR_TIM13RST_Pos = 0x7
	// Bit mask of TIM13RST field.
	RCC_RCC_APB1RSTCLRR_TIM13RST_Msk = 0x80
	// Bit TIM13RST.
	RCC_RCC_APB1RSTCLRR_TIM13RST = 0x80
	// Position of TIM14RST field.
	RCC_RCC_APB1RSTCLRR_TIM14RST_Pos = 0x8
	// Bit mask of TIM14RST field.
	RCC_RCC_APB1RSTCLRR_TIM14RST_Msk = 0x100
	// Bit TIM14RST.
	RCC_RCC_APB1RSTCLRR_TIM14RST = 0x100
	// Position of LPTIM1RST field.
	RCC_RCC_APB1RSTCLRR_LPTIM1RST_Pos = 0x9
	// Bit mask of LPTIM1RST field.
	RCC_RCC_APB1RSTCLRR_LPTIM1RST_Msk = 0x200
	// Bit LPTIM1RST.
	RCC_RCC_APB1RSTCLRR_LPTIM1RST = 0x200
	// Position of SPI2RST field.
	RCC_RCC_APB1RSTCLRR_SPI2RST_Pos = 0xb
	// Bit mask of SPI2RST field.
	RCC_RCC_APB1RSTCLRR_SPI2RST_Msk = 0x800
	// Bit SPI2RST.
	RCC_RCC_APB1RSTCLRR_SPI2RST = 0x800
	// Position of SPI3RST field.
	RCC_RCC_APB1RSTCLRR_SPI3RST_Pos = 0xc
	// Bit mask of SPI3RST field.
	RCC_RCC_APB1RSTCLRR_SPI3RST_Msk = 0x1000
	// Bit SPI3RST.
	RCC_RCC_APB1RSTCLRR_SPI3RST = 0x1000
	// Position of USART2RST field.
	RCC_RCC_APB1RSTCLRR_USART2RST_Pos = 0xe
	// Bit mask of USART2RST field.
	RCC_RCC_APB1RSTCLRR_USART2RST_Msk = 0x4000
	// Bit USART2RST.
	RCC_RCC_APB1RSTCLRR_USART2RST = 0x4000
	// Position of USART3RST field.
	RCC_RCC_APB1RSTCLRR_USART3RST_Pos = 0xf
	// Bit mask of USART3RST field.
	RCC_RCC_APB1RSTCLRR_USART3RST_Msk = 0x8000
	// Bit USART3RST.
	RCC_RCC_APB1RSTCLRR_USART3RST = 0x8000
	// Position of UART4RST field.
	RCC_RCC_APB1RSTCLRR_UART4RST_Pos = 0x10
	// Bit mask of UART4RST field.
	RCC_RCC_APB1RSTCLRR_UART4RST_Msk = 0x10000
	// Bit UART4RST.
	RCC_RCC_APB1RSTCLRR_UART4RST = 0x10000
	// Position of UART5RST field.
	RCC_RCC_APB1RSTCLRR_UART5RST_Pos = 0x11
	// Bit mask of UART5RST field.
	RCC_RCC_APB1RSTCLRR_UART5RST_Msk = 0x20000
	// Bit UART5RST.
	RCC_RCC_APB1RSTCLRR_UART5RST = 0x20000
	// Position of UART7RST field.
	RCC_RCC_APB1RSTCLRR_UART7RST_Pos = 0x12
	// Bit mask of UART7RST field.
	RCC_RCC_APB1RSTCLRR_UART7RST_Msk = 0x40000
	// Bit UART7RST.
	RCC_RCC_APB1RSTCLRR_UART7RST = 0x40000
	// Position of UART8RST field.
	RCC_RCC_APB1RSTCLRR_UART8RST_Pos = 0x13
	// Bit mask of UART8RST field.
	RCC_RCC_APB1RSTCLRR_UART8RST_Msk = 0x80000
	// Bit UART8RST.
	RCC_RCC_APB1RSTCLRR_UART8RST = 0x80000
	// Position of I2C1RST field.
	RCC_RCC_APB1RSTCLRR_I2C1RST_Pos = 0x15
	// Bit mask of I2C1RST field.
	RCC_RCC_APB1RSTCLRR_I2C1RST_Msk = 0x200000
	// Bit I2C1RST.
	RCC_RCC_APB1RSTCLRR_I2C1RST = 0x200000
	// Position of I2C2RST field.
	RCC_RCC_APB1RSTCLRR_I2C2RST_Pos = 0x16
	// Bit mask of I2C2RST field.
	RCC_RCC_APB1RSTCLRR_I2C2RST_Msk = 0x400000
	// Bit I2C2RST.
	RCC_RCC_APB1RSTCLRR_I2C2RST = 0x400000
	// Position of I2C3RST field.
	RCC_RCC_APB1RSTCLRR_I2C3RST_Pos = 0x17
	// Bit mask of I2C3RST field.
	RCC_RCC_APB1RSTCLRR_I2C3RST_Msk = 0x800000
	// Bit I2C3RST.
	RCC_RCC_APB1RSTCLRR_I2C3RST = 0x800000
	// Position of I2C5RST field.
	RCC_RCC_APB1RSTCLRR_I2C5RST_Pos = 0x18
	// Bit mask of I2C5RST field.
	RCC_RCC_APB1RSTCLRR_I2C5RST_Msk = 0x1000000
	// Bit I2C5RST.
	RCC_RCC_APB1RSTCLRR_I2C5RST = 0x1000000
	// Position of SPDIFRST field.
	RCC_RCC_APB1RSTCLRR_SPDIFRST_Pos = 0x1a
	// Bit mask of SPDIFRST field.
	RCC_RCC_APB1RSTCLRR_SPDIFRST_Msk = 0x4000000
	// Bit SPDIFRST.
	RCC_RCC_APB1RSTCLRR_SPDIFRST = 0x4000000
	// Position of CECRST field.
	RCC_RCC_APB1RSTCLRR_CECRST_Pos = 0x1b
	// Bit mask of CECRST field.
	RCC_RCC_APB1RSTCLRR_CECRST_Msk = 0x8000000
	// Bit CECRST.
	RCC_RCC_APB1RSTCLRR_CECRST = 0x8000000
	// Position of DAC12RST field.
	RCC_RCC_APB1RSTCLRR_DAC12RST_Pos = 0x1d
	// Bit mask of DAC12RST field.
	RCC_RCC_APB1RSTCLRR_DAC12RST_Msk = 0x20000000
	// Bit DAC12RST.
	RCC_RCC_APB1RSTCLRR_DAC12RST = 0x20000000
	// Position of MDIOSRST field.
	RCC_RCC_APB1RSTCLRR_MDIOSRST_Pos = 0x1f
	// Bit mask of MDIOSRST field.
	RCC_RCC_APB1RSTCLRR_MDIOSRST_Msk = 0x80000000
	// Bit MDIOSRST.
	RCC_RCC_APB1RSTCLRR_MDIOSRST = 0x80000000

	// RCC_APB2RSTSETR: This register is used to activate the reset of the corresponding peripheral.
	// Position of TIM1RST field.
	RCC_RCC_APB2RSTSETR_TIM1RST_Pos = 0x0
	// Bit mask of TIM1RST field.
	RCC_RCC_APB2RSTSETR_TIM1RST_Msk = 0x1
	// Bit TIM1RST.
	RCC_RCC_APB2RSTSETR_TIM1RST = 0x1
	// Position of TIM8RST field.
	RCC_RCC_APB2RSTSETR_TIM8RST_Pos = 0x1
	// Bit mask of TIM8RST field.
	RCC_RCC_APB2RSTSETR_TIM8RST_Msk = 0x2
	// Bit TIM8RST.
	RCC_RCC_APB2RSTSETR_TIM8RST = 0x2
	// Position of TIM15RST field.
	RCC_RCC_APB2RSTSETR_TIM15RST_Pos = 0x2
	// Bit mask of TIM15RST field.
	RCC_RCC_APB2RSTSETR_TIM15RST_Msk = 0x4
	// Bit TIM15RST.
	RCC_RCC_APB2RSTSETR_TIM15RST = 0x4
	// Position of TIM16RST field.
	RCC_RCC_APB2RSTSETR_TIM16RST_Pos = 0x3
	// Bit mask of TIM16RST field.
	RCC_RCC_APB2RSTSETR_TIM16RST_Msk = 0x8
	// Bit TIM16RST.
	RCC_RCC_APB2RSTSETR_TIM16RST = 0x8
	// Position of TIM17RST field.
	RCC_RCC_APB2RSTSETR_TIM17RST_Pos = 0x4
	// Bit mask of TIM17RST field.
	RCC_RCC_APB2RSTSETR_TIM17RST_Msk = 0x10
	// Bit TIM17RST.
	RCC_RCC_APB2RSTSETR_TIM17RST = 0x10
	// Position of SPI1RST field.
	RCC_RCC_APB2RSTSETR_SPI1RST_Pos = 0x8
	// Bit mask of SPI1RST field.
	RCC_RCC_APB2RSTSETR_SPI1RST_Msk = 0x100
	// Bit SPI1RST.
	RCC_RCC_APB2RSTSETR_SPI1RST = 0x100
	// Position of SPI4RST field.
	RCC_RCC_APB2RSTSETR_SPI4RST_Pos = 0x9
	// Bit mask of SPI4RST field.
	RCC_RCC_APB2RSTSETR_SPI4RST_Msk = 0x200
	// Bit SPI4RST.
	RCC_RCC_APB2RSTSETR_SPI4RST = 0x200
	// Position of SPI5RST field.
	RCC_RCC_APB2RSTSETR_SPI5RST_Pos = 0xa
	// Bit mask of SPI5RST field.
	RCC_RCC_APB2RSTSETR_SPI5RST_Msk = 0x400
	// Bit SPI5RST.
	RCC_RCC_APB2RSTSETR_SPI5RST = 0x400
	// Position of USART6RST field.
	RCC_RCC_APB2RSTSETR_USART6RST_Pos = 0xd
	// Bit mask of USART6RST field.
	RCC_RCC_APB2RSTSETR_USART6RST_Msk = 0x2000
	// Bit USART6RST.
	RCC_RCC_APB2RSTSETR_USART6RST = 0x2000
	// Position of SAI1RST field.
	RCC_RCC_APB2RSTSETR_SAI1RST_Pos = 0x10
	// Bit mask of SAI1RST field.
	RCC_RCC_APB2RSTSETR_SAI1RST_Msk = 0x10000
	// Bit SAI1RST.
	RCC_RCC_APB2RSTSETR_SAI1RST = 0x10000
	// Position of SAI2RST field.
	RCC_RCC_APB2RSTSETR_SAI2RST_Pos = 0x11
	// Bit mask of SAI2RST field.
	RCC_RCC_APB2RSTSETR_SAI2RST_Msk = 0x20000
	// Bit SAI2RST.
	RCC_RCC_APB2RSTSETR_SAI2RST = 0x20000
	// Position of SAI3RST field.
	RCC_RCC_APB2RSTSETR_SAI3RST_Pos = 0x12
	// Bit mask of SAI3RST field.
	RCC_RCC_APB2RSTSETR_SAI3RST_Msk = 0x40000
	// Bit SAI3RST.
	RCC_RCC_APB2RSTSETR_SAI3RST = 0x40000
	// Position of DFSDMRST field.
	RCC_RCC_APB2RSTSETR_DFSDMRST_Pos = 0x14
	// Bit mask of DFSDMRST field.
	RCC_RCC_APB2RSTSETR_DFSDMRST_Msk = 0x100000
	// Bit DFSDMRST.
	RCC_RCC_APB2RSTSETR_DFSDMRST = 0x100000
	// Position of FDCANRST field.
	RCC_RCC_APB2RSTSETR_FDCANRST_Pos = 0x18
	// Bit mask of FDCANRST field.
	RCC_RCC_APB2RSTSETR_FDCANRST_Msk = 0x1000000
	// Bit FDCANRST.
	RCC_RCC_APB2RSTSETR_FDCANRST = 0x1000000

	// RCC_APB2RSTCLRR: This register is used to release the reset of the corresponding peripheral.
	// Position of TIM1RST field.
	RCC_RCC_APB2RSTCLRR_TIM1RST_Pos = 0x0
	// Bit mask of TIM1RST field.
	RCC_RCC_APB2RSTCLRR_TIM1RST_Msk = 0x1
	// Bit TIM1RST.
	RCC_RCC_APB2RSTCLRR_TIM1RST = 0x1
	// Position of TIM8RST field.
	RCC_RCC_APB2RSTCLRR_TIM8RST_Pos = 0x1
	// Bit mask of TIM8RST field.
	RCC_RCC_APB2RSTCLRR_TIM8RST_Msk = 0x2
	// Bit TIM8RST.
	RCC_RCC_APB2RSTCLRR_TIM8RST = 0x2
	// Position of TIM15RST field.
	RCC_RCC_APB2RSTCLRR_TIM15RST_Pos = 0x2
	// Bit mask of TIM15RST field.
	RCC_RCC_APB2RSTCLRR_TIM15RST_Msk = 0x4
	// Bit TIM15RST.
	RCC_RCC_APB2RSTCLRR_TIM15RST = 0x4
	// Position of TIM16RST field.
	RCC_RCC_APB2RSTCLRR_TIM16RST_Pos = 0x3
	// Bit mask of TIM16RST field.
	RCC_RCC_APB2RSTCLRR_TIM16RST_Msk = 0x8
	// Bit TIM16RST.
	RCC_RCC_APB2RSTCLRR_TIM16RST = 0x8
	// Position of TIM17RST field.
	RCC_RCC_APB2RSTCLRR_TIM17RST_Pos = 0x4
	// Bit mask of TIM17RST field.
	RCC_RCC_APB2RSTCLRR_TIM17RST_Msk = 0x10
	// Bit TIM17RST.
	RCC_RCC_APB2RSTCLRR_TIM17RST = 0x10
	// Position of SPI1RST field.
	RCC_RCC_APB2RSTCLRR_SPI1RST_Pos = 0x8
	// Bit mask of SPI1RST field.
	RCC_RCC_APB2RSTCLRR_SPI1RST_Msk = 0x100
	// Bit SPI1RST.
	RCC_RCC_APB2RSTCLRR_SPI1RST = 0x100
	// Position of SPI4RST field.
	RCC_RCC_APB2RSTCLRR_SPI4RST_Pos = 0x9
	// Bit mask of SPI4RST field.
	RCC_RCC_APB2RSTCLRR_SPI4RST_Msk = 0x200
	// Bit SPI4RST.
	RCC_RCC_APB2RSTCLRR_SPI4RST = 0x200
	// Position of SPI5RST field.
	RCC_RCC_APB2RSTCLRR_SPI5RST_Pos = 0xa
	// Bit mask of SPI5RST field.
	RCC_RCC_APB2RSTCLRR_SPI5RST_Msk = 0x400
	// Bit SPI5RST.
	RCC_RCC_APB2RSTCLRR_SPI5RST = 0x400
	// Position of USART6RST field.
	RCC_RCC_APB2RSTCLRR_USART6RST_Pos = 0xd
	// Bit mask of USART6RST field.
	RCC_RCC_APB2RSTCLRR_USART6RST_Msk = 0x2000
	// Bit USART6RST.
	RCC_RCC_APB2RSTCLRR_USART6RST = 0x2000
	// Position of SAI1RST field.
	RCC_RCC_APB2RSTCLRR_SAI1RST_Pos = 0x10
	// Bit mask of SAI1RST field.
	RCC_RCC_APB2RSTCLRR_SAI1RST_Msk = 0x10000
	// Bit SAI1RST.
	RCC_RCC_APB2RSTCLRR_SAI1RST = 0x10000
	// Position of SAI2RST field.
	RCC_RCC_APB2RSTCLRR_SAI2RST_Pos = 0x11
	// Bit mask of SAI2RST field.
	RCC_RCC_APB2RSTCLRR_SAI2RST_Msk = 0x20000
	// Bit SAI2RST.
	RCC_RCC_APB2RSTCLRR_SAI2RST = 0x20000
	// Position of SAI3RST field.
	RCC_RCC_APB2RSTCLRR_SAI3RST_Pos = 0x12
	// Bit mask of SAI3RST field.
	RCC_RCC_APB2RSTCLRR_SAI3RST_Msk = 0x40000
	// Bit SAI3RST.
	RCC_RCC_APB2RSTCLRR_SAI3RST = 0x40000
	// Position of DFSDMRST field.
	RCC_RCC_APB2RSTCLRR_DFSDMRST_Pos = 0x14
	// Bit mask of DFSDMRST field.
	RCC_RCC_APB2RSTCLRR_DFSDMRST_Msk = 0x100000
	// Bit DFSDMRST.
	RCC_RCC_APB2RSTCLRR_DFSDMRST = 0x100000
	// Position of FDCANRST field.
	RCC_RCC_APB2RSTCLRR_FDCANRST_Pos = 0x18
	// Bit mask of FDCANRST field.
	RCC_RCC_APB2RSTCLRR_FDCANRST_Msk = 0x1000000
	// Bit FDCANRST.
	RCC_RCC_APB2RSTCLRR_FDCANRST = 0x1000000

	// RCC_APB3RSTSETR: This register is used to activate the reset of the corresponding peripheral.
	// Position of LPTIM2RST field.
	RCC_RCC_APB3RSTSETR_LPTIM2RST_Pos = 0x0
	// Bit mask of LPTIM2RST field.
	RCC_RCC_APB3RSTSETR_LPTIM2RST_Msk = 0x1
	// Bit LPTIM2RST.
	RCC_RCC_APB3RSTSETR_LPTIM2RST = 0x1
	// Position of LPTIM3RST field.
	RCC_RCC_APB3RSTSETR_LPTIM3RST_Pos = 0x1
	// Bit mask of LPTIM3RST field.
	RCC_RCC_APB3RSTSETR_LPTIM3RST_Msk = 0x2
	// Bit LPTIM3RST.
	RCC_RCC_APB3RSTSETR_LPTIM3RST = 0x2
	// Position of LPTIM4RST field.
	RCC_RCC_APB3RSTSETR_LPTIM4RST_Pos = 0x2
	// Bit mask of LPTIM4RST field.
	RCC_RCC_APB3RSTSETR_LPTIM4RST_Msk = 0x4
	// Bit LPTIM4RST.
	RCC_RCC_APB3RSTSETR_LPTIM4RST = 0x4
	// Position of LPTIM5RST field.
	RCC_RCC_APB3RSTSETR_LPTIM5RST_Pos = 0x3
	// Bit mask of LPTIM5RST field.
	RCC_RCC_APB3RSTSETR_LPTIM5RST_Msk = 0x8
	// Bit LPTIM5RST.
	RCC_RCC_APB3RSTSETR_LPTIM5RST = 0x8
	// Position of SAI4RST field.
	RCC_RCC_APB3RSTSETR_SAI4RST_Pos = 0x8
	// Bit mask of SAI4RST field.
	RCC_RCC_APB3RSTSETR_SAI4RST_Msk = 0x100
	// Bit SAI4RST.
	RCC_RCC_APB3RSTSETR_SAI4RST = 0x100
	// Position of SYSCFGRST field.
	RCC_RCC_APB3RSTSETR_SYSCFGRST_Pos = 0xb
	// Bit mask of SYSCFGRST field.
	RCC_RCC_APB3RSTSETR_SYSCFGRST_Msk = 0x800
	// Bit SYSCFGRST.
	RCC_RCC_APB3RSTSETR_SYSCFGRST = 0x800
	// Position of VREFRST field.
	RCC_RCC_APB3RSTSETR_VREFRST_Pos = 0xd
	// Bit mask of VREFRST field.
	RCC_RCC_APB3RSTSETR_VREFRST_Msk = 0x2000
	// Bit VREFRST.
	RCC_RCC_APB3RSTSETR_VREFRST = 0x2000
	// Position of DTSRST field.
	RCC_RCC_APB3RSTSETR_DTSRST_Pos = 0x10
	// Bit mask of DTSRST field.
	RCC_RCC_APB3RSTSETR_DTSRST_Msk = 0x10000
	// Bit DTSRST.
	RCC_RCC_APB3RSTSETR_DTSRST = 0x10000

	// RCC_APB3RSTCLRR: This register is used to release the reset of the corresponding peripheral.
	// Position of LPTIM2RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM2RST_Pos = 0x0
	// Bit mask of LPTIM2RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM2RST_Msk = 0x1
	// Bit LPTIM2RST.
	RCC_RCC_APB3RSTCLRR_LPTIM2RST = 0x1
	// Position of LPTIM3RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM3RST_Pos = 0x1
	// Bit mask of LPTIM3RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM3RST_Msk = 0x2
	// Bit LPTIM3RST.
	RCC_RCC_APB3RSTCLRR_LPTIM3RST = 0x2
	// Position of LPTIM4RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM4RST_Pos = 0x2
	// Bit mask of LPTIM4RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM4RST_Msk = 0x4
	// Bit LPTIM4RST.
	RCC_RCC_APB3RSTCLRR_LPTIM4RST = 0x4
	// Position of LPTIM5RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM5RST_Pos = 0x3
	// Bit mask of LPTIM5RST field.
	RCC_RCC_APB3RSTCLRR_LPTIM5RST_Msk = 0x8
	// Bit LPTIM5RST.
	RCC_RCC_APB3RSTCLRR_LPTIM5RST = 0x8
	// Position of SAI4RST field.
	RCC_RCC_APB3RSTCLRR_SAI4RST_Pos = 0x8
	// Bit mask of SAI4RST field.
	RCC_RCC_APB3RSTCLRR_SAI4RST_Msk = 0x100
	// Bit SAI4RST.
	RCC_RCC_APB3RSTCLRR_SAI4RST = 0x100
	// Position of SYSCFGRST field.
	RCC_RCC_APB3RSTCLRR_SYSCFGRST_Pos = 0xb
	// Bit mask of SYSCFGRST field.
	RCC_RCC_APB3RSTCLRR_SYSCFGRST_Msk = 0x800
	// Bit SYSCFGRST.
	RCC_RCC_APB3RSTCLRR_SYSCFGRST = 0x800
	// Position of VREFRST field.
	RCC_RCC_APB3RSTCLRR_VREFRST_Pos = 0xd
	// Bit mask of VREFRST field.
	RCC_RCC_APB3RSTCLRR_VREFRST_Msk = 0x2000
	// Bit VREFRST.
	RCC_RCC_APB3RSTCLRR_VREFRST = 0x2000
	// Position of DTSRST field.
	RCC_RCC_APB3RSTCLRR_DTSRST_Pos = 0x10
	// Bit mask of DTSRST field.
	RCC_RCC_APB3RSTCLRR_DTSRST_Msk = 0x10000
	// Bit DTSRST.
	RCC_RCC_APB3RSTCLRR_DTSRST = 0x10000

	// RCC_AHB2RSTSETR: This register is used to activate the reset of the corresponding peripheral.
	// Position of DMA1RST field.
	RCC_RCC_AHB2RSTSETR_DMA1RST_Pos = 0x0
	// Bit mask of DMA1RST field.
	RCC_RCC_AHB2RSTSETR_DMA1RST_Msk = 0x1
	// Bit DMA1RST.
	RCC_RCC_AHB2RSTSETR_DMA1RST = 0x1
	// Position of DMA2RST field.
	RCC_RCC_AHB2RSTSETR_DMA2RST_Pos = 0x1
	// Bit mask of DMA2RST field.
	RCC_RCC_AHB2RSTSETR_DMA2RST_Msk = 0x2
	// Bit DMA2RST.
	RCC_RCC_AHB2RSTSETR_DMA2RST = 0x2
	// Position of DMAMUXRST field.
	RCC_RCC_AHB2RSTSETR_DMAMUXRST_Pos = 0x2
	// Bit mask of DMAMUXRST field.
	RCC_RCC_AHB2RSTSETR_DMAMUXRST_Msk = 0x4
	// Bit DMAMUXRST.
	RCC_RCC_AHB2RSTSETR_DMAMUXRST = 0x4
	// Position of ADC12RST field.
	RCC_RCC_AHB2RSTSETR_ADC12RST_Pos = 0x5
	// Bit mask of ADC12RST field.
	RCC_RCC_AHB2RSTSETR_ADC12RST_Msk = 0x20
	// Bit ADC12RST.
	RCC_RCC_AHB2RSTSETR_ADC12RST = 0x20
	// Position of USBORST field.
	RCC_RCC_AHB2RSTSETR_USBORST_Pos = 0x8
	// Bit mask of USBORST field.
	RCC_RCC_AHB2RSTSETR_USBORST_Msk = 0x100
	// Bit USBORST.
	RCC_RCC_AHB2RSTSETR_USBORST = 0x100
	// Position of SDMMC3RST field.
	RCC_RCC_AHB2RSTSETR_SDMMC3RST_Pos = 0x10
	// Bit mask of SDMMC3RST field.
	RCC_RCC_AHB2RSTSETR_SDMMC3RST_Msk = 0x10000
	// Bit SDMMC3RST.
	RCC_RCC_AHB2RSTSETR_SDMMC3RST = 0x10000

	// RCC_AHB2RSTCLRR: This register is used to release the reset of the corresponding peripheral.
	// Position of DMA1RST field.
	RCC_RCC_AHB2RSTCLRR_DMA1RST_Pos = 0x0
	// Bit mask of DMA1RST field.
	RCC_RCC_AHB2RSTCLRR_DMA1RST_Msk = 0x1
	// Bit DMA1RST.
	RCC_RCC_AHB2RSTCLRR_DMA1RST = 0x1
	// Position of DMA2RST field.
	RCC_RCC_AHB2RSTCLRR_DMA2RST_Pos = 0x1
	// Bit mask of DMA2RST field.
	RCC_RCC_AHB2RSTCLRR_DMA2RST_Msk = 0x2
	// Bit DMA2RST.
	RCC_RCC_AHB2RSTCLRR_DMA2RST = 0x2
	// Position of DMAMUXRST field.
	RCC_RCC_AHB2RSTCLRR_DMAMUXRST_Pos = 0x2
	// Bit mask of DMAMUXRST field.
	RCC_RCC_AHB2RSTCLRR_DMAMUXRST_Msk = 0x4
	// Bit DMAMUXRST.
	RCC_RCC_AHB2RSTCLRR_DMAMUXRST = 0x4
	// Position of ADC12RST field.
	RCC_RCC_AHB2RSTCLRR_ADC12RST_Pos = 0x5
	// Bit mask of ADC12RST field.
	RCC_RCC_AHB2RSTCLRR_ADC12RST_Msk = 0x20
	// Bit ADC12RST.
	RCC_RCC_AHB2RSTCLRR_ADC12RST = 0x20
	// Position of USBORST field.
	RCC_RCC_AHB2RSTCLRR_USBORST_Pos = 0x8
	// Bit mask of USBORST field.
	RCC_RCC_AHB2RSTCLRR_USBORST_Msk = 0x100
	// Bit USBORST.
	RCC_RCC_AHB2RSTCLRR_USBORST = 0x100
	// Position of SDMMC3RST field.
	RCC_RCC_AHB2RSTCLRR_SDMMC3RST_Pos = 0x10
	// Bit mask of SDMMC3RST field.
	RCC_RCC_AHB2RSTCLRR_SDMMC3RST_Msk = 0x10000
	// Bit SDMMC3RST.
	RCC_RCC_AHB2RSTCLRR_SDMMC3RST = 0x10000

	// RCC_AHB3RSTSETR: This register is used to activate the reset of the corresponding peripheral.
	// Position of DCMIRST field.
	RCC_RCC_AHB3RSTSETR_DCMIRST_Pos = 0x0
	// Bit mask of DCMIRST field.
	RCC_RCC_AHB3RSTSETR_DCMIRST_Msk = 0x1
	// Bit DCMIRST.
	RCC_RCC_AHB3RSTSETR_DCMIRST = 0x1
	// Position of CRYP2RST field.
	RCC_RCC_AHB3RSTSETR_CRYP2RST_Pos = 0x4
	// Bit mask of CRYP2RST field.
	RCC_RCC_AHB3RSTSETR_CRYP2RST_Msk = 0x10
	// Bit CRYP2RST.
	RCC_RCC_AHB3RSTSETR_CRYP2RST = 0x10
	// Position of HASH2RST field.
	RCC_RCC_AHB3RSTSETR_HASH2RST_Pos = 0x5
	// Bit mask of HASH2RST field.
	RCC_RCC_AHB3RSTSETR_HASH2RST_Msk = 0x20
	// Bit HASH2RST.
	RCC_RCC_AHB3RSTSETR_HASH2RST = 0x20
	// Position of RNG2RST field.
	RCC_RCC_AHB3RSTSETR_RNG2RST_Pos = 0x6
	// Bit mask of RNG2RST field.
	RCC_RCC_AHB3RSTSETR_RNG2RST_Msk = 0x40
	// Bit RNG2RST.
	RCC_RCC_AHB3RSTSETR_RNG2RST = 0x40
	// Position of CRC2RST field.
	RCC_RCC_AHB3RSTSETR_CRC2RST_Pos = 0x7
	// Bit mask of CRC2RST field.
	RCC_RCC_AHB3RSTSETR_CRC2RST_Msk = 0x80
	// Bit CRC2RST.
	RCC_RCC_AHB3RSTSETR_CRC2RST = 0x80
	// Position of HSEMRST field.
	RCC_RCC_AHB3RSTSETR_HSEMRST_Pos = 0xb
	// Bit mask of HSEMRST field.
	RCC_RCC_AHB3RSTSETR_HSEMRST_Msk = 0x800
	// Bit HSEMRST.
	RCC_RCC_AHB3RSTSETR_HSEMRST = 0x800
	// Position of IPCCRST field.
	RCC_RCC_AHB3RSTSETR_IPCCRST_Pos = 0xc
	// Bit mask of IPCCRST field.
	RCC_RCC_AHB3RSTSETR_IPCCRST_Msk = 0x1000
	// Bit IPCCRST.
	RCC_RCC_AHB3RSTSETR_IPCCRST = 0x1000

	// RCC_AHB3RSTCLRR: This register is used to release the reset of the corresponding peripheral.
	// Position of DCMIRST field.
	RCC_RCC_AHB3RSTCLRR_DCMIRST_Pos = 0x0
	// Bit mask of DCMIRST field.
	RCC_RCC_AHB3RSTCLRR_DCMIRST_Msk = 0x1
	// Bit DCMIRST.
	RCC_RCC_AHB3RSTCLRR_DCMIRST = 0x1
	// Position of CRYP2RST field.
	RCC_RCC_AHB3RSTCLRR_CRYP2RST_Pos = 0x4
	// Bit mask of CRYP2RST field.
	RCC_RCC_AHB3RSTCLRR_CRYP2RST_Msk = 0x10
	// Bit CRYP2RST.
	RCC_RCC_AHB3RSTCLRR_CRYP2RST = 0x10
	// Position of HASH2RST field.
	RCC_RCC_AHB3RSTCLRR_HASH2RST_Pos = 0x5
	// Bit mask of HASH2RST field.
	RCC_RCC_AHB3RSTCLRR_HASH2RST_Msk = 0x20
	// Bit HASH2RST.
	RCC_RCC_AHB3RSTCLRR_HASH2RST = 0x20
	// Position of RNG2RST field.
	RCC_RCC_AHB3RSTCLRR_RNG2RST_Pos = 0x6
	// Bit mask of RNG2RST field.
	RCC_RCC_AHB3RSTCLRR_RNG2RST_Msk = 0x40
	// Bit RNG2RST.
	RCC_RCC_AHB3RSTCLRR_RNG2RST = 0x40
	// Position of CRC2RST field.
	RCC_RCC_AHB3RSTCLRR_CRC2RST_Pos = 0x7
	// Bit mask of CRC2RST field.
	RCC_RCC_AHB3RSTCLRR_CRC2RST_Msk = 0x80
	// Bit CRC2RST.
	RCC_RCC_AHB3RSTCLRR_CRC2RST = 0x80
	// Position of HSEMRST field.
	RCC_RCC_AHB3RSTCLRR_HSEMRST_Pos = 0xb
	// Bit mask of HSEMRST field.
	RCC_RCC_AHB3RSTCLRR_HSEMRST_Msk = 0x800
	// Bit HSEMRST.
	RCC_RCC_AHB3RSTCLRR_HSEMRST = 0x800
	// Position of IPCCRST field.
	RCC_RCC_AHB3RSTCLRR_IPCCRST_Pos = 0xc
	// Bit mask of IPCCRST field.
	RCC_RCC_AHB3RSTCLRR_IPCCRST_Msk = 0x1000
	// Bit IPCCRST.
	RCC_RCC_AHB3RSTCLRR_IPCCRST = 0x1000

	// RCC_AHB4RSTSETR: This register is used to activate the reset of the corresponding peripheral
	// Position of GPIOARST field.
	RCC_RCC_AHB4RSTSETR_GPIOARST_Pos = 0x0
	// Bit mask of GPIOARST field.
	RCC_RCC_AHB4RSTSETR_GPIOARST_Msk = 0x1
	// Bit GPIOARST.
	RCC_RCC_AHB4RSTSETR_GPIOARST = 0x1
	// Position of GPIOBRST field.
	RCC_RCC_AHB4RSTSETR_GPIOBRST_Pos = 0x1
	// Bit mask of GPIOBRST field.
	RCC_RCC_AHB4RSTSETR_GPIOBRST_Msk = 0x2
	// Bit GPIOBRST.
	RCC_RCC_AHB4RSTSETR_GPIOBRST = 0x2
	// Position of GPIOCRST field.
	RCC_RCC_AHB4RSTSETR_GPIOCRST_Pos = 0x2
	// Bit mask of GPIOCRST field.
	RCC_RCC_AHB4RSTSETR_GPIOCRST_Msk = 0x4
	// Bit GPIOCRST.
	RCC_RCC_AHB4RSTSETR_GPIOCRST = 0x4
	// Position of GPIODRST field.
	RCC_RCC_AHB4RSTSETR_GPIODRST_Pos = 0x3
	// Bit mask of GPIODRST field.
	RCC_RCC_AHB4RSTSETR_GPIODRST_Msk = 0x8
	// Bit GPIODRST.
	RCC_RCC_AHB4RSTSETR_GPIODRST = 0x8
	// Position of GPIOERST field.
	RCC_RCC_AHB4RSTSETR_GPIOERST_Pos = 0x4
	// Bit mask of GPIOERST field.
	RCC_RCC_AHB4RSTSETR_GPIOERST_Msk = 0x10
	// Bit GPIOERST.
	RCC_RCC_AHB4RSTSETR_GPIOERST = 0x10
	// Position of GPIOFRST field.
	RCC_RCC_AHB4RSTSETR_GPIOFRST_Pos = 0x5
	// Bit mask of GPIOFRST field.
	RCC_RCC_AHB4RSTSETR_GPIOFRST_Msk = 0x20
	// Bit GPIOFRST.
	RCC_RCC_AHB4RSTSETR_GPIOFRST = 0x20
	// Position of GPIOGRST field.
	RCC_RCC_AHB4RSTSETR_GPIOGRST_Pos = 0x6
	// Bit mask of GPIOGRST field.
	RCC_RCC_AHB4RSTSETR_GPIOGRST_Msk = 0x40
	// Bit GPIOGRST.
	RCC_RCC_AHB4RSTSETR_GPIOGRST = 0x40
	// Position of GPIOHRST field.
	RCC_RCC_AHB4RSTSETR_GPIOHRST_Pos = 0x7
	// Bit mask of GPIOHRST field.
	RCC_RCC_AHB4RSTSETR_GPIOHRST_Msk = 0x80
	// Bit GPIOHRST.
	RCC_RCC_AHB4RSTSETR_GPIOHRST = 0x80
	// Position of GPIOIRST field.
	RCC_RCC_AHB4RSTSETR_GPIOIRST_Pos = 0x8
	// Bit mask of GPIOIRST field.
	RCC_RCC_AHB4RSTSETR_GPIOIRST_Msk = 0x100
	// Bit GPIOIRST.
	RCC_RCC_AHB4RSTSETR_GPIOIRST = 0x100
	// Position of GPIOJRST field.
	RCC_RCC_AHB4RSTSETR_GPIOJRST_Pos = 0x9
	// Bit mask of GPIOJRST field.
	RCC_RCC_AHB4RSTSETR_GPIOJRST_Msk = 0x200
	// Bit GPIOJRST.
	RCC_RCC_AHB4RSTSETR_GPIOJRST = 0x200
	// Position of GPIOKRST field.
	RCC_RCC_AHB4RSTSETR_GPIOKRST_Pos = 0xa
	// Bit mask of GPIOKRST field.
	RCC_RCC_AHB4RSTSETR_GPIOKRST_Msk = 0x400
	// Bit GPIOKRST.
	RCC_RCC_AHB4RSTSETR_GPIOKRST = 0x400

	// RCC_AHB4RSTCLRR: This register is used to release the reset of the corresponding peripheral.
	// Position of GPIOARST field.
	RCC_RCC_AHB4RSTCLRR_GPIOARST_Pos = 0x0
	// Bit mask of GPIOARST field.
	RCC_RCC_AHB4RSTCLRR_GPIOARST_Msk = 0x1
	// Bit GPIOARST.
	RCC_RCC_AHB4RSTCLRR_GPIOARST = 0x1
	// Position of GPIOBRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOBRST_Pos = 0x1
	// Bit mask of GPIOBRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOBRST_Msk = 0x2
	// Bit GPIOBRST.
	RCC_RCC_AHB4RSTCLRR_GPIOBRST = 0x2
	// Position of GPIOCRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOCRST_Pos = 0x2
	// Bit mask of GPIOCRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOCRST_Msk = 0x4
	// Bit GPIOCRST.
	RCC_RCC_AHB4RSTCLRR_GPIOCRST = 0x4
	// Position of GPIODRST field.
	RCC_RCC_AHB4RSTCLRR_GPIODRST_Pos = 0x3
	// Bit mask of GPIODRST field.
	RCC_RCC_AHB4RSTCLRR_GPIODRST_Msk = 0x8
	// Bit GPIODRST.
	RCC_RCC_AHB4RSTCLRR_GPIODRST = 0x8
	// Position of GPIOERST field.
	RCC_RCC_AHB4RSTCLRR_GPIOERST_Pos = 0x4
	// Bit mask of GPIOERST field.
	RCC_RCC_AHB4RSTCLRR_GPIOERST_Msk = 0x10
	// Bit GPIOERST.
	RCC_RCC_AHB4RSTCLRR_GPIOERST = 0x10
	// Position of GPIOFRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOFRST_Pos = 0x5
	// Bit mask of GPIOFRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOFRST_Msk = 0x20
	// Bit GPIOFRST.
	RCC_RCC_AHB4RSTCLRR_GPIOFRST = 0x20
	// Position of GPIOGRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOGRST_Pos = 0x6
	// Bit mask of GPIOGRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOGRST_Msk = 0x40
	// Bit GPIOGRST.
	RCC_RCC_AHB4RSTCLRR_GPIOGRST = 0x40
	// Position of GPIOHRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOHRST_Pos = 0x7
	// Bit mask of GPIOHRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOHRST_Msk = 0x80
	// Bit GPIOHRST.
	RCC_RCC_AHB4RSTCLRR_GPIOHRST = 0x80
	// Position of GPIOIRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOIRST_Pos = 0x8
	// Bit mask of GPIOIRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOIRST_Msk = 0x100
	// Bit GPIOIRST.
	RCC_RCC_AHB4RSTCLRR_GPIOIRST = 0x100
	// Position of GPIOJRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOJRST_Pos = 0x9
	// Bit mask of GPIOJRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOJRST_Msk = 0x200
	// Bit GPIOJRST.
	RCC_RCC_AHB4RSTCLRR_GPIOJRST = 0x200
	// Position of GPIOKRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOKRST_Pos = 0xa
	// Bit mask of GPIOKRST field.
	RCC_RCC_AHB4RSTCLRR_GPIOKRST_Msk = 0x400
	// Bit GPIOKRST.
	RCC_RCC_AHB4RSTCLRR_GPIOKRST = 0x400

	// RCC_MP_APB1ENSETR: This register is used to set the peripheral clock enable bit
	// Position of TIM2EN field.
	RCC_RCC_MP_APB1ENSETR_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_RCC_MP_APB1ENSETR_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_RCC_MP_APB1ENSETR_TIM2EN = 0x1
	// Position of TIM3EN field.
	RCC_RCC_MP_APB1ENSETR_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_RCC_MP_APB1ENSETR_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_RCC_MP_APB1ENSETR_TIM3EN = 0x2
	// Position of TIM4EN field.
	RCC_RCC_MP_APB1ENSETR_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_RCC_MP_APB1ENSETR_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_RCC_MP_APB1ENSETR_TIM4EN = 0x4
	// Position of TIM5EN field.
	RCC_RCC_MP_APB1ENSETR_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_RCC_MP_APB1ENSETR_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_RCC_MP_APB1ENSETR_TIM5EN = 0x8
	// Position of TIM6EN field.
	RCC_RCC_MP_APB1ENSETR_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_RCC_MP_APB1ENSETR_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_RCC_MP_APB1ENSETR_TIM6EN = 0x10
	// Position of TIM7EN field.
	RCC_RCC_MP_APB1ENSETR_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_RCC_MP_APB1ENSETR_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_RCC_MP_APB1ENSETR_TIM7EN = 0x20
	// Position of TIM12EN field.
	RCC_RCC_MP_APB1ENSETR_TIM12EN_Pos = 0x6
	// Bit mask of TIM12EN field.
	RCC_RCC_MP_APB1ENSETR_TIM12EN_Msk = 0x40
	// Bit TIM12EN.
	RCC_RCC_MP_APB1ENSETR_TIM12EN = 0x40
	// Position of TIM13EN field.
	RCC_RCC_MP_APB1ENSETR_TIM13EN_Pos = 0x7
	// Bit mask of TIM13EN field.
	RCC_RCC_MP_APB1ENSETR_TIM13EN_Msk = 0x80
	// Bit TIM13EN.
	RCC_RCC_MP_APB1ENSETR_TIM13EN = 0x80
	// Position of TIM14EN field.
	RCC_RCC_MP_APB1ENSETR_TIM14EN_Pos = 0x8
	// Bit mask of TIM14EN field.
	RCC_RCC_MP_APB1ENSETR_TIM14EN_Msk = 0x100
	// Bit TIM14EN.
	RCC_RCC_MP_APB1ENSETR_TIM14EN = 0x100
	// Position of LPTIM1EN field.
	RCC_RCC_MP_APB1ENSETR_LPTIM1EN_Pos = 0x9
	// Bit mask of LPTIM1EN field.
	RCC_RCC_MP_APB1ENSETR_LPTIM1EN_Msk = 0x200
	// Bit LPTIM1EN.
	RCC_RCC_MP_APB1ENSETR_LPTIM1EN = 0x200
	// Position of SPI2EN field.
	RCC_RCC_MP_APB1ENSETR_SPI2EN_Pos = 0xb
	// Bit mask of SPI2EN field.
	RCC_RCC_MP_APB1ENSETR_SPI2EN_Msk = 0x800
	// Bit SPI2EN.
	RCC_RCC_MP_APB1ENSETR_SPI2EN = 0x800
	// Position of SPI3EN field.
	RCC_RCC_MP_APB1ENSETR_SPI3EN_Pos = 0xc
	// Bit mask of SPI3EN field.
	RCC_RCC_MP_APB1ENSETR_SPI3EN_Msk = 0x1000
	// Bit SPI3EN.
	RCC_RCC_MP_APB1ENSETR_SPI3EN = 0x1000
	// Position of USART2EN field.
	RCC_RCC_MP_APB1ENSETR_USART2EN_Pos = 0xe
	// Bit mask of USART2EN field.
	RCC_RCC_MP_APB1ENSETR_USART2EN_Msk = 0x4000
	// Bit USART2EN.
	RCC_RCC_MP_APB1ENSETR_USART2EN = 0x4000
	// Position of USART3EN field.
	RCC_RCC_MP_APB1ENSETR_USART3EN_Pos = 0xf
	// Bit mask of USART3EN field.
	RCC_RCC_MP_APB1ENSETR_USART3EN_Msk = 0x8000
	// Bit USART3EN.
	RCC_RCC_MP_APB1ENSETR_USART3EN = 0x8000
	// Position of UART4EN field.
	RCC_RCC_MP_APB1ENSETR_UART4EN_Pos = 0x10
	// Bit mask of UART4EN field.
	RCC_RCC_MP_APB1ENSETR_UART4EN_Msk = 0x10000
	// Bit UART4EN.
	RCC_RCC_MP_APB1ENSETR_UART4EN = 0x10000
	// Position of UART5EN field.
	RCC_RCC_MP_APB1ENSETR_UART5EN_Pos = 0x11
	// Bit mask of UART5EN field.
	RCC_RCC_MP_APB1ENSETR_UART5EN_Msk = 0x20000
	// Bit UART5EN.
	RCC_RCC_MP_APB1ENSETR_UART5EN = 0x20000
	// Position of UART7EN field.
	RCC_RCC_MP_APB1ENSETR_UART7EN_Pos = 0x12
	// Bit mask of UART7EN field.
	RCC_RCC_MP_APB1ENSETR_UART7EN_Msk = 0x40000
	// Bit UART7EN.
	RCC_RCC_MP_APB1ENSETR_UART7EN = 0x40000
	// Position of UART8EN field.
	RCC_RCC_MP_APB1ENSETR_UART8EN_Pos = 0x13
	// Bit mask of UART8EN field.
	RCC_RCC_MP_APB1ENSETR_UART8EN_Msk = 0x80000
	// Bit UART8EN.
	RCC_RCC_MP_APB1ENSETR_UART8EN = 0x80000
	// Position of I2C1EN field.
	RCC_RCC_MP_APB1ENSETR_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_RCC_MP_APB1ENSETR_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_RCC_MP_APB1ENSETR_I2C1EN = 0x200000
	// Position of I2C2EN field.
	RCC_RCC_MP_APB1ENSETR_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_RCC_MP_APB1ENSETR_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_RCC_MP_APB1ENSETR_I2C2EN = 0x400000
	// Position of I2C3EN field.
	RCC_RCC_MP_APB1ENSETR_I2C3EN_Pos = 0x17
	// Bit mask of I2C3EN field.
	RCC_RCC_MP_APB1ENSETR_I2C3EN_Msk = 0x800000
	// Bit I2C3EN.
	RCC_RCC_MP_APB1ENSETR_I2C3EN = 0x800000
	// Position of I2C5EN field.
	RCC_RCC_MP_APB1ENSETR_I2C5EN_Pos = 0x18
	// Bit mask of I2C5EN field.
	RCC_RCC_MP_APB1ENSETR_I2C5EN_Msk = 0x1000000
	// Bit I2C5EN.
	RCC_RCC_MP_APB1ENSETR_I2C5EN = 0x1000000
	// Position of SPDIFEN field.
	RCC_RCC_MP_APB1ENSETR_SPDIFEN_Pos = 0x1a
	// Bit mask of SPDIFEN field.
	RCC_RCC_MP_APB1ENSETR_SPDIFEN_Msk = 0x4000000
	// Bit SPDIFEN.
	RCC_RCC_MP_APB1ENSETR_SPDIFEN = 0x4000000
	// Position of CECEN field.
	RCC_RCC_MP_APB1ENSETR_CECEN_Pos = 0x1b
	// Bit mask of CECEN field.
	RCC_RCC_MP_APB1ENSETR_CECEN_Msk = 0x8000000
	// Bit CECEN.
	RCC_RCC_MP_APB1ENSETR_CECEN = 0x8000000
	// Position of DAC12EN field.
	RCC_RCC_MP_APB1ENSETR_DAC12EN_Pos = 0x1d
	// Bit mask of DAC12EN field.
	RCC_RCC_MP_APB1ENSETR_DAC12EN_Msk = 0x20000000
	// Bit DAC12EN.
	RCC_RCC_MP_APB1ENSETR_DAC12EN = 0x20000000
	// Position of MDIOSEN field.
	RCC_RCC_MP_APB1ENSETR_MDIOSEN_Pos = 0x1f
	// Bit mask of MDIOSEN field.
	RCC_RCC_MP_APB1ENSETR_MDIOSEN_Msk = 0x80000000
	// Bit MDIOSEN.
	RCC_RCC_MP_APB1ENSETR_MDIOSEN = 0x80000000

	// RCC_MP_APB1ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of TIM2EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_RCC_MP_APB1ENCLRR_TIM2EN = 0x1
	// Position of TIM3EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_RCC_MP_APB1ENCLRR_TIM3EN = 0x2
	// Position of TIM4EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_RCC_MP_APB1ENCLRR_TIM4EN = 0x4
	// Position of TIM5EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_RCC_MP_APB1ENCLRR_TIM5EN = 0x8
	// Position of TIM6EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_RCC_MP_APB1ENCLRR_TIM6EN = 0x10
	// Position of TIM7EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_RCC_MP_APB1ENCLRR_TIM7EN = 0x20
	// Position of TIM12EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM12EN_Pos = 0x6
	// Bit mask of TIM12EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM12EN_Msk = 0x40
	// Bit TIM12EN.
	RCC_RCC_MP_APB1ENCLRR_TIM12EN = 0x40
	// Position of TIM13EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM13EN_Pos = 0x7
	// Bit mask of TIM13EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM13EN_Msk = 0x80
	// Bit TIM13EN.
	RCC_RCC_MP_APB1ENCLRR_TIM13EN = 0x80
	// Position of TIM14EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM14EN_Pos = 0x8
	// Bit mask of TIM14EN field.
	RCC_RCC_MP_APB1ENCLRR_TIM14EN_Msk = 0x100
	// Bit TIM14EN.
	RCC_RCC_MP_APB1ENCLRR_TIM14EN = 0x100
	// Position of LPTIM1EN field.
	RCC_RCC_MP_APB1ENCLRR_LPTIM1EN_Pos = 0x9
	// Bit mask of LPTIM1EN field.
	RCC_RCC_MP_APB1ENCLRR_LPTIM1EN_Msk = 0x200
	// Bit LPTIM1EN.
	RCC_RCC_MP_APB1ENCLRR_LPTIM1EN = 0x200
	// Position of SPI2EN field.
	RCC_RCC_MP_APB1ENCLRR_SPI2EN_Pos = 0xb
	// Bit mask of SPI2EN field.
	RCC_RCC_MP_APB1ENCLRR_SPI2EN_Msk = 0x800
	// Bit SPI2EN.
	RCC_RCC_MP_APB1ENCLRR_SPI2EN = 0x800
	// Position of SPI3EN field.
	RCC_RCC_MP_APB1ENCLRR_SPI3EN_Pos = 0xc
	// Bit mask of SPI3EN field.
	RCC_RCC_MP_APB1ENCLRR_SPI3EN_Msk = 0x1000
	// Bit SPI3EN.
	RCC_RCC_MP_APB1ENCLRR_SPI3EN = 0x1000
	// Position of USART2EN field.
	RCC_RCC_MP_APB1ENCLRR_USART2EN_Pos = 0xe
	// Bit mask of USART2EN field.
	RCC_RCC_MP_APB1ENCLRR_USART2EN_Msk = 0x4000
	// Bit USART2EN.
	RCC_RCC_MP_APB1ENCLRR_USART2EN = 0x4000
	// Position of USART3EN field.
	RCC_RCC_MP_APB1ENCLRR_USART3EN_Pos = 0xf
	// Bit mask of USART3EN field.
	RCC_RCC_MP_APB1ENCLRR_USART3EN_Msk = 0x8000
	// Bit USART3EN.
	RCC_RCC_MP_APB1ENCLRR_USART3EN = 0x8000
	// Position of UART4EN field.
	RCC_RCC_MP_APB1ENCLRR_UART4EN_Pos = 0x10
	// Bit mask of UART4EN field.
	RCC_RCC_MP_APB1ENCLRR_UART4EN_Msk = 0x10000
	// Bit UART4EN.
	RCC_RCC_MP_APB1ENCLRR_UART4EN = 0x10000
	// Position of UART5EN field.
	RCC_RCC_MP_APB1ENCLRR_UART5EN_Pos = 0x11
	// Bit mask of UART5EN field.
	RCC_RCC_MP_APB1ENCLRR_UART5EN_Msk = 0x20000
	// Bit UART5EN.
	RCC_RCC_MP_APB1ENCLRR_UART5EN = 0x20000
	// Position of UART7EN field.
	RCC_RCC_MP_APB1ENCLRR_UART7EN_Pos = 0x12
	// Bit mask of UART7EN field.
	RCC_RCC_MP_APB1ENCLRR_UART7EN_Msk = 0x40000
	// Bit UART7EN.
	RCC_RCC_MP_APB1ENCLRR_UART7EN = 0x40000
	// Position of UART8EN field.
	RCC_RCC_MP_APB1ENCLRR_UART8EN_Pos = 0x13
	// Bit mask of UART8EN field.
	RCC_RCC_MP_APB1ENCLRR_UART8EN_Msk = 0x80000
	// Bit UART8EN.
	RCC_RCC_MP_APB1ENCLRR_UART8EN = 0x80000
	// Position of I2C1EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_RCC_MP_APB1ENCLRR_I2C1EN = 0x200000
	// Position of I2C2EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_RCC_MP_APB1ENCLRR_I2C2EN = 0x400000
	// Position of I2C3EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C3EN_Pos = 0x17
	// Bit mask of I2C3EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C3EN_Msk = 0x800000
	// Bit I2C3EN.
	RCC_RCC_MP_APB1ENCLRR_I2C3EN = 0x800000
	// Position of I2C5EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C5EN_Pos = 0x18
	// Bit mask of I2C5EN field.
	RCC_RCC_MP_APB1ENCLRR_I2C5EN_Msk = 0x1000000
	// Bit I2C5EN.
	RCC_RCC_MP_APB1ENCLRR_I2C5EN = 0x1000000
	// Position of SPDIFEN field.
	RCC_RCC_MP_APB1ENCLRR_SPDIFEN_Pos = 0x1a
	// Bit mask of SPDIFEN field.
	RCC_RCC_MP_APB1ENCLRR_SPDIFEN_Msk = 0x4000000
	// Bit SPDIFEN.
	RCC_RCC_MP_APB1ENCLRR_SPDIFEN = 0x4000000
	// Position of CECEN field.
	RCC_RCC_MP_APB1ENCLRR_CECEN_Pos = 0x1b
	// Bit mask of CECEN field.
	RCC_RCC_MP_APB1ENCLRR_CECEN_Msk = 0x8000000
	// Bit CECEN.
	RCC_RCC_MP_APB1ENCLRR_CECEN = 0x8000000
	// Position of DAC12EN field.
	RCC_RCC_MP_APB1ENCLRR_DAC12EN_Pos = 0x1d
	// Bit mask of DAC12EN field.
	RCC_RCC_MP_APB1ENCLRR_DAC12EN_Msk = 0x20000000
	// Bit DAC12EN.
	RCC_RCC_MP_APB1ENCLRR_DAC12EN = 0x20000000
	// Position of MDIOSEN field.
	RCC_RCC_MP_APB1ENCLRR_MDIOSEN_Pos = 0x1f
	// Bit mask of MDIOSEN field.
	RCC_RCC_MP_APB1ENCLRR_MDIOSEN_Msk = 0x80000000
	// Bit MDIOSEN.
	RCC_RCC_MP_APB1ENCLRR_MDIOSEN = 0x80000000

	// RCC_MP_APB2ENSETR: This register is used to set the peripheral clock enable bit
	// Position of TIM1EN field.
	RCC_RCC_MP_APB2ENSETR_TIM1EN_Pos = 0x0
	// Bit mask of TIM1EN field.
	RCC_RCC_MP_APB2ENSETR_TIM1EN_Msk = 0x1
	// Bit TIM1EN.
	RCC_RCC_MP_APB2ENSETR_TIM1EN = 0x1
	// Position of TIM8EN field.
	RCC_RCC_MP_APB2ENSETR_TIM8EN_Pos = 0x1
	// Bit mask of TIM8EN field.
	RCC_RCC_MP_APB2ENSETR_TIM8EN_Msk = 0x2
	// Bit TIM8EN.
	RCC_RCC_MP_APB2ENSETR_TIM8EN = 0x2
	// Position of TIM15EN field.
	RCC_RCC_MP_APB2ENSETR_TIM15EN_Pos = 0x2
	// Bit mask of TIM15EN field.
	RCC_RCC_MP_APB2ENSETR_TIM15EN_Msk = 0x4
	// Bit TIM15EN.
	RCC_RCC_MP_APB2ENSETR_TIM15EN = 0x4
	// Position of TIM16EN field.
	RCC_RCC_MP_APB2ENSETR_TIM16EN_Pos = 0x3
	// Bit mask of TIM16EN field.
	RCC_RCC_MP_APB2ENSETR_TIM16EN_Msk = 0x8
	// Bit TIM16EN.
	RCC_RCC_MP_APB2ENSETR_TIM16EN = 0x8
	// Position of TIM17EN field.
	RCC_RCC_MP_APB2ENSETR_TIM17EN_Pos = 0x4
	// Bit mask of TIM17EN field.
	RCC_RCC_MP_APB2ENSETR_TIM17EN_Msk = 0x10
	// Bit TIM17EN.
	RCC_RCC_MP_APB2ENSETR_TIM17EN = 0x10
	// Position of SPI1EN field.
	RCC_RCC_MP_APB2ENSETR_SPI1EN_Pos = 0x8
	// Bit mask of SPI1EN field.
	RCC_RCC_MP_APB2ENSETR_SPI1EN_Msk = 0x100
	// Bit SPI1EN.
	RCC_RCC_MP_APB2ENSETR_SPI1EN = 0x100
	// Position of SPI4EN field.
	RCC_RCC_MP_APB2ENSETR_SPI4EN_Pos = 0x9
	// Bit mask of SPI4EN field.
	RCC_RCC_MP_APB2ENSETR_SPI4EN_Msk = 0x200
	// Bit SPI4EN.
	RCC_RCC_MP_APB2ENSETR_SPI4EN = 0x200
	// Position of SPI5EN field.
	RCC_RCC_MP_APB2ENSETR_SPI5EN_Pos = 0xa
	// Bit mask of SPI5EN field.
	RCC_RCC_MP_APB2ENSETR_SPI5EN_Msk = 0x400
	// Bit SPI5EN.
	RCC_RCC_MP_APB2ENSETR_SPI5EN = 0x400
	// Position of USART6EN field.
	RCC_RCC_MP_APB2ENSETR_USART6EN_Pos = 0xd
	// Bit mask of USART6EN field.
	RCC_RCC_MP_APB2ENSETR_USART6EN_Msk = 0x2000
	// Bit USART6EN.
	RCC_RCC_MP_APB2ENSETR_USART6EN = 0x2000
	// Position of SAI1EN field.
	RCC_RCC_MP_APB2ENSETR_SAI1EN_Pos = 0x10
	// Bit mask of SAI1EN field.
	RCC_RCC_MP_APB2ENSETR_SAI1EN_Msk = 0x10000
	// Bit SAI1EN.
	RCC_RCC_MP_APB2ENSETR_SAI1EN = 0x10000
	// Position of SAI2EN field.
	RCC_RCC_MP_APB2ENSETR_SAI2EN_Pos = 0x11
	// Bit mask of SAI2EN field.
	RCC_RCC_MP_APB2ENSETR_SAI2EN_Msk = 0x20000
	// Bit SAI2EN.
	RCC_RCC_MP_APB2ENSETR_SAI2EN = 0x20000
	// Position of SAI3EN field.
	RCC_RCC_MP_APB2ENSETR_SAI3EN_Pos = 0x12
	// Bit mask of SAI3EN field.
	RCC_RCC_MP_APB2ENSETR_SAI3EN_Msk = 0x40000
	// Bit SAI3EN.
	RCC_RCC_MP_APB2ENSETR_SAI3EN = 0x40000
	// Position of DFSDMEN field.
	RCC_RCC_MP_APB2ENSETR_DFSDMEN_Pos = 0x14
	// Bit mask of DFSDMEN field.
	RCC_RCC_MP_APB2ENSETR_DFSDMEN_Msk = 0x100000
	// Bit DFSDMEN.
	RCC_RCC_MP_APB2ENSETR_DFSDMEN = 0x100000
	// Position of ADFSDMEN field.
	RCC_RCC_MP_APB2ENSETR_ADFSDMEN_Pos = 0x15
	// Bit mask of ADFSDMEN field.
	RCC_RCC_MP_APB2ENSETR_ADFSDMEN_Msk = 0x200000
	// Bit ADFSDMEN.
	RCC_RCC_MP_APB2ENSETR_ADFSDMEN = 0x200000
	// Position of FDCANEN field.
	RCC_RCC_MP_APB2ENSETR_FDCANEN_Pos = 0x18
	// Bit mask of FDCANEN field.
	RCC_RCC_MP_APB2ENSETR_FDCANEN_Msk = 0x1000000
	// Bit FDCANEN.
	RCC_RCC_MP_APB2ENSETR_FDCANEN = 0x1000000

	// RCC_MP_APB2ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
	// Position of TIM1EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM1EN_Pos = 0x0
	// Bit mask of TIM1EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM1EN_Msk = 0x1
	// Bit TIM1EN.
	RCC_RCC_MP_APB2ENCLRR_TIM1EN = 0x1
	// Position of TIM8EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM8EN_Pos = 0x1
	// Bit mask of TIM8EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM8EN_Msk = 0x2
	// Bit TIM8EN.
	RCC_RCC_MP_APB2ENCLRR_TIM8EN = 0x2
	// Position of TIM15EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM15EN_Pos = 0x2
	// Bit mask of TIM15EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM15EN_Msk = 0x4
	// Bit TIM15EN.
	RCC_RCC_MP_APB2ENCLRR_TIM15EN = 0x4
	// Position of TIM16EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM16EN_Pos = 0x3
	// Bit mask of TIM16EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM16EN_Msk = 0x8
	// Bit TIM16EN.
	RCC_RCC_MP_APB2ENCLRR_TIM16EN = 0x8
	// Position of TIM17EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM17EN_Pos = 0x4
	// Bit mask of TIM17EN field.
	RCC_RCC_MP_APB2ENCLRR_TIM17EN_Msk = 0x10
	// Bit TIM17EN.
	RCC_RCC_MP_APB2ENCLRR_TIM17EN = 0x10
	// Position of SPI1EN field.
	RCC_RCC_MP_APB2ENCLRR_SPI1EN_Pos = 0x8
	// Bit mask of SPI1EN field.
	RCC_RCC_MP_APB2ENCLRR_SPI1EN_Msk = 0x100
	// Bit SPI1EN.
	RCC_RCC_MP_APB2ENCLRR_SPI1EN = 0x100
	// Position of SPI4EN field.
	RCC_RCC_MP_APB2ENCLRR_SPI4EN_Pos = 0x9
	// Bit mask of SPI4EN field.
	RCC_RCC_MP_APB2ENCLRR_SPI4EN_Msk = 0x200
	// Bit SPI4EN.
	RCC_RCC_MP_APB2ENCLRR_SPI4EN = 0x200
	// Position of SPI5EN field.
	RCC_RCC_MP_APB2ENCLRR_SPI5EN_Pos = 0xa
	// Bit mask of SPI5EN field.
	RCC_RCC_MP_APB2ENCLRR_SPI5EN_Msk = 0x400
	// Bit SPI5EN.
	RCC_RCC_MP_APB2ENCLRR_SPI5EN = 0x400
	// Position of USART6EN field.
	RCC_RCC_MP_APB2ENCLRR_USART6EN_Pos = 0xd
	// Bit mask of USART6EN field.
	RCC_RCC_MP_APB2ENCLRR_USART6EN_Msk = 0x2000
	// Bit USART6EN.
	RCC_RCC_MP_APB2ENCLRR_USART6EN = 0x2000
	// Position of SAI1EN field.
	RCC_RCC_MP_APB2ENCLRR_SAI1EN_Pos = 0x10
	// Bit mask of SAI1EN field.
	RCC_RCC_MP_APB2ENCLRR_SAI1EN_Msk = 0x10000
	// Bit SAI1EN.
	RCC_RCC_MP_APB2ENCLRR_SAI1EN = 0x10000
	// Position of SAI2EN field.
	RCC_RCC_MP_APB2ENCLRR_SAI2EN_Pos = 0x11
	// Bit mask of SAI2EN field.
	RCC_RCC_MP_APB2ENCLRR_SAI2EN_Msk = 0x20000
	// Bit SAI2EN.
	RCC_RCC_MP_APB2ENCLRR_SAI2EN = 0x20000
	// Position of SAI3EN field.
	RCC_RCC_MP_APB2ENCLRR_SAI3EN_Pos = 0x12
	// Bit mask of SAI3EN field.
	RCC_RCC_MP_APB2ENCLRR_SAI3EN_Msk = 0x40000
	// Bit SAI3EN.
	RCC_RCC_MP_APB2ENCLRR_SAI3EN = 0x40000
	// Position of DFSDMEN field.
	RCC_RCC_MP_APB2ENCLRR_DFSDMEN_Pos = 0x14
	// Bit mask of DFSDMEN field.
	RCC_RCC_MP_APB2ENCLRR_DFSDMEN_Msk = 0x100000
	// Bit DFSDMEN.
	RCC_RCC_MP_APB2ENCLRR_DFSDMEN = 0x100000
	// Position of ADFSDMEN field.
	RCC_RCC_MP_APB2ENCLRR_ADFSDMEN_Pos = 0x15
	// Bit mask of ADFSDMEN field.
	RCC_RCC_MP_APB2ENCLRR_ADFSDMEN_Msk = 0x200000
	// Bit ADFSDMEN.
	RCC_RCC_MP_APB2ENCLRR_ADFSDMEN = 0x200000
	// Position of FDCANEN field.
	RCC_RCC_MP_APB2ENCLRR_FDCANEN_Pos = 0x18
	// Bit mask of FDCANEN field.
	RCC_RCC_MP_APB2ENCLRR_FDCANEN_Msk = 0x1000000
	// Bit FDCANEN.
	RCC_RCC_MP_APB2ENCLRR_FDCANEN = 0x1000000

	// RCC_MP_APB3ENSETR: This register is used to set the peripheral clock enable bit
	// Position of LPTIM2EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM2EN_Pos = 0x0
	// Bit mask of LPTIM2EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM2EN_Msk = 0x1
	// Bit LPTIM2EN.
	RCC_RCC_MP_APB3ENSETR_LPTIM2EN = 0x1
	// Position of LPTIM3EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM3EN_Pos = 0x1
	// Bit mask of LPTIM3EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM3EN_Msk = 0x2
	// Bit LPTIM3EN.
	RCC_RCC_MP_APB3ENSETR_LPTIM3EN = 0x2
	// Position of LPTIM4EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM4EN_Pos = 0x2
	// Bit mask of LPTIM4EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM4EN_Msk = 0x4
	// Bit LPTIM4EN.
	RCC_RCC_MP_APB3ENSETR_LPTIM4EN = 0x4
	// Position of LPTIM5EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM5EN_Pos = 0x3
	// Bit mask of LPTIM5EN field.
	RCC_RCC_MP_APB3ENSETR_LPTIM5EN_Msk = 0x8
	// Bit LPTIM5EN.
	RCC_RCC_MP_APB3ENSETR_LPTIM5EN = 0x8
	// Position of SAI4EN field.
	RCC_RCC_MP_APB3ENSETR_SAI4EN_Pos = 0x8
	// Bit mask of SAI4EN field.
	RCC_RCC_MP_APB3ENSETR_SAI4EN_Msk = 0x100
	// Bit SAI4EN.
	RCC_RCC_MP_APB3ENSETR_SAI4EN = 0x100
	// Position of SYSCFGEN field.
	RCC_RCC_MP_APB3ENSETR_SYSCFGEN_Pos = 0xb
	// Bit mask of SYSCFGEN field.
	RCC_RCC_MP_APB3ENSETR_SYSCFGEN_Msk = 0x800
	// Bit SYSCFGEN.
	RCC_RCC_MP_APB3ENSETR_SYSCFGEN = 0x800
	// Position of VREFEN field.
	RCC_RCC_MP_APB3ENSETR_VREFEN_Pos = 0xd
	// Bit mask of VREFEN field.
	RCC_RCC_MP_APB3ENSETR_VREFEN_Msk = 0x2000
	// Bit VREFEN.
	RCC_RCC_MP_APB3ENSETR_VREFEN = 0x2000
	// Position of DTSEN field.
	RCC_RCC_MP_APB3ENSETR_DTSEN_Pos = 0x10
	// Bit mask of DTSEN field.
	RCC_RCC_MP_APB3ENSETR_DTSEN_Msk = 0x10000
	// Bit DTSEN.
	RCC_RCC_MP_APB3ENSETR_DTSEN = 0x10000
	// Position of HDPEN field.
	RCC_RCC_MP_APB3ENSETR_HDPEN_Pos = 0x14
	// Bit mask of HDPEN field.
	RCC_RCC_MP_APB3ENSETR_HDPEN_Msk = 0x100000
	// Bit HDPEN.
	RCC_RCC_MP_APB3ENSETR_HDPEN = 0x100000

	// RCC_MP_APB3ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
	// Position of LPTIM2EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM2EN_Pos = 0x0
	// Bit mask of LPTIM2EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM2EN_Msk = 0x1
	// Bit LPTIM2EN.
	RCC_RCC_MP_APB3ENCLRR_LPTIM2EN = 0x1
	// Position of LPTIM3EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM3EN_Pos = 0x1
	// Bit mask of LPTIM3EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM3EN_Msk = 0x2
	// Bit LPTIM3EN.
	RCC_RCC_MP_APB3ENCLRR_LPTIM3EN = 0x2
	// Position of LPTIM4EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM4EN_Pos = 0x2
	// Bit mask of LPTIM4EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM4EN_Msk = 0x4
	// Bit LPTIM4EN.
	RCC_RCC_MP_APB3ENCLRR_LPTIM4EN = 0x4
	// Position of LPTIM5EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM5EN_Pos = 0x3
	// Bit mask of LPTIM5EN field.
	RCC_RCC_MP_APB3ENCLRR_LPTIM5EN_Msk = 0x8
	// Bit LPTIM5EN.
	RCC_RCC_MP_APB3ENCLRR_LPTIM5EN = 0x8
	// Position of SAI4EN field.
	RCC_RCC_MP_APB3ENCLRR_SAI4EN_Pos = 0x8
	// Bit mask of SAI4EN field.
	RCC_RCC_MP_APB3ENCLRR_SAI4EN_Msk = 0x100
	// Bit SAI4EN.
	RCC_RCC_MP_APB3ENCLRR_SAI4EN = 0x100
	// Position of SYSCFGEN field.
	RCC_RCC_MP_APB3ENCLRR_SYSCFGEN_Pos = 0xb
	// Bit mask of SYSCFGEN field.
	RCC_RCC_MP_APB3ENCLRR_SYSCFGEN_Msk = 0x800
	// Bit SYSCFGEN.
	RCC_RCC_MP_APB3ENCLRR_SYSCFGEN = 0x800
	// Position of VREFEN field.
	RCC_RCC_MP_APB3ENCLRR_VREFEN_Pos = 0xd
	// Bit mask of VREFEN field.
	RCC_RCC_MP_APB3ENCLRR_VREFEN_Msk = 0x2000
	// Bit VREFEN.
	RCC_RCC_MP_APB3ENCLRR_VREFEN = 0x2000
	// Position of DTSEN field.
	RCC_RCC_MP_APB3ENCLRR_DTSEN_Pos = 0x10
	// Bit mask of DTSEN field.
	RCC_RCC_MP_APB3ENCLRR_DTSEN_Msk = 0x10000
	// Bit DTSEN.
	RCC_RCC_MP_APB3ENCLRR_DTSEN = 0x10000
	// Position of HDPEN field.
	RCC_RCC_MP_APB3ENCLRR_HDPEN_Pos = 0x14
	// Bit mask of HDPEN field.
	RCC_RCC_MP_APB3ENCLRR_HDPEN_Msk = 0x100000
	// Bit HDPEN.
	RCC_RCC_MP_APB3ENCLRR_HDPEN = 0x100000

	// RCC_MP_AHB2ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral
	// Position of DMA1EN field.
	RCC_RCC_MP_AHB2ENSETR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_RCC_MP_AHB2ENSETR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_RCC_MP_AHB2ENSETR_DMA1EN = 0x1
	// Position of DMA2EN field.
	RCC_RCC_MP_AHB2ENSETR_DMA2EN_Pos = 0x1
	// Bit mask of DMA2EN field.
	RCC_RCC_MP_AHB2ENSETR_DMA2EN_Msk = 0x2
	// Bit DMA2EN.
	RCC_RCC_MP_AHB2ENSETR_DMA2EN = 0x2
	// Position of DMAMUXEN field.
	RCC_RCC_MP_AHB2ENSETR_DMAMUXEN_Pos = 0x2
	// Bit mask of DMAMUXEN field.
	RCC_RCC_MP_AHB2ENSETR_DMAMUXEN_Msk = 0x4
	// Bit DMAMUXEN.
	RCC_RCC_MP_AHB2ENSETR_DMAMUXEN = 0x4
	// Position of ADC12EN field.
	RCC_RCC_MP_AHB2ENSETR_ADC12EN_Pos = 0x5
	// Bit mask of ADC12EN field.
	RCC_RCC_MP_AHB2ENSETR_ADC12EN_Msk = 0x20
	// Bit ADC12EN.
	RCC_RCC_MP_AHB2ENSETR_ADC12EN = 0x20
	// Position of USBOEN field.
	RCC_RCC_MP_AHB2ENSETR_USBOEN_Pos = 0x8
	// Bit mask of USBOEN field.
	RCC_RCC_MP_AHB2ENSETR_USBOEN_Msk = 0x100
	// Bit USBOEN.
	RCC_RCC_MP_AHB2ENSETR_USBOEN = 0x100
	// Position of SDMMC3EN field.
	RCC_RCC_MP_AHB2ENSETR_SDMMC3EN_Pos = 0x10
	// Bit mask of SDMMC3EN field.
	RCC_RCC_MP_AHB2ENSETR_SDMMC3EN_Msk = 0x10000
	// Bit SDMMC3EN.
	RCC_RCC_MP_AHB2ENSETR_SDMMC3EN = 0x10000

	// RCC_MP_AHB2ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
	// Position of DMA1EN field.
	RCC_RCC_MP_AHB2ENCLRR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_RCC_MP_AHB2ENCLRR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_RCC_MP_AHB2ENCLRR_DMA1EN = 0x1
	// Position of DMA2EN field.
	RCC_RCC_MP_AHB2ENCLRR_DMA2EN_Pos = 0x1
	// Bit mask of DMA2EN field.
	RCC_RCC_MP_AHB2ENCLRR_DMA2EN_Msk = 0x2
	// Bit DMA2EN.
	RCC_RCC_MP_AHB2ENCLRR_DMA2EN = 0x2
	// Position of DMAMUXEN field.
	RCC_RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos = 0x2
	// Bit mask of DMAMUXEN field.
	RCC_RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk = 0x4
	// Bit DMAMUXEN.
	RCC_RCC_MP_AHB2ENCLRR_DMAMUXEN = 0x4
	// Position of ADC12EN field.
	RCC_RCC_MP_AHB2ENCLRR_ADC12EN_Pos = 0x5
	// Bit mask of ADC12EN field.
	RCC_RCC_MP_AHB2ENCLRR_ADC12EN_Msk = 0x20
	// Bit ADC12EN.
	RCC_RCC_MP_AHB2ENCLRR_ADC12EN = 0x20
	// Position of USBOEN field.
	RCC_RCC_MP_AHB2ENCLRR_USBOEN_Pos = 0x8
	// Bit mask of USBOEN field.
	RCC_RCC_MP_AHB2ENCLRR_USBOEN_Msk = 0x100
	// Bit USBOEN.
	RCC_RCC_MP_AHB2ENCLRR_USBOEN = 0x100
	// Position of SDMMC3EN field.
	RCC_RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos = 0x10
	// Bit mask of SDMMC3EN field.
	RCC_RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk = 0x10000
	// Bit SDMMC3EN.
	RCC_RCC_MP_AHB2ENCLRR_SDMMC3EN = 0x10000

	// RCC_MP_AHB3ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral
	// Position of DCMIEN field.
	RCC_RCC_MP_AHB3ENSETR_DCMIEN_Pos = 0x0
	// Bit mask of DCMIEN field.
	RCC_RCC_MP_AHB3ENSETR_DCMIEN_Msk = 0x1
	// Bit DCMIEN.
	RCC_RCC_MP_AHB3ENSETR_DCMIEN = 0x1
	// Position of CRYP2EN field.
	RCC_RCC_MP_AHB3ENSETR_CRYP2EN_Pos = 0x4
	// Bit mask of CRYP2EN field.
	RCC_RCC_MP_AHB3ENSETR_CRYP2EN_Msk = 0x10
	// Bit CRYP2EN.
	RCC_RCC_MP_AHB3ENSETR_CRYP2EN = 0x10
	// Position of HASH2EN field.
	RCC_RCC_MP_AHB3ENSETR_HASH2EN_Pos = 0x5
	// Bit mask of HASH2EN field.
	RCC_RCC_MP_AHB3ENSETR_HASH2EN_Msk = 0x20
	// Bit HASH2EN.
	RCC_RCC_MP_AHB3ENSETR_HASH2EN = 0x20
	// Position of RNG2EN field.
	RCC_RCC_MP_AHB3ENSETR_RNG2EN_Pos = 0x6
	// Bit mask of RNG2EN field.
	RCC_RCC_MP_AHB3ENSETR_RNG2EN_Msk = 0x40
	// Bit RNG2EN.
	RCC_RCC_MP_AHB3ENSETR_RNG2EN = 0x40
	// Position of CRC2EN field.
	RCC_RCC_MP_AHB3ENSETR_CRC2EN_Pos = 0x7
	// Bit mask of CRC2EN field.
	RCC_RCC_MP_AHB3ENSETR_CRC2EN_Msk = 0x80
	// Bit CRC2EN.
	RCC_RCC_MP_AHB3ENSETR_CRC2EN = 0x80
	// Position of HSEMEN field.
	RCC_RCC_MP_AHB3ENSETR_HSEMEN_Pos = 0xb
	// Bit mask of HSEMEN field.
	RCC_RCC_MP_AHB3ENSETR_HSEMEN_Msk = 0x800
	// Bit HSEMEN.
	RCC_RCC_MP_AHB3ENSETR_HSEMEN = 0x800
	// Position of IPCCEN field.
	RCC_RCC_MP_AHB3ENSETR_IPCCEN_Pos = 0xc
	// Bit mask of IPCCEN field.
	RCC_RCC_MP_AHB3ENSETR_IPCCEN_Msk = 0x1000
	// Bit IPCCEN.
	RCC_RCC_MP_AHB3ENSETR_IPCCEN = 0x1000

	// RCC_MP_AHB3ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
	// Position of DCMIEN field.
	RCC_RCC_MP_AHB3ENCLRR_DCMIEN_Pos = 0x0
	// Bit mask of DCMIEN field.
	RCC_RCC_MP_AHB3ENCLRR_DCMIEN_Msk = 0x1
	// Bit DCMIEN.
	RCC_RCC_MP_AHB3ENCLRR_DCMIEN = 0x1
	// Position of CRYP2EN field.
	RCC_RCC_MP_AHB3ENCLRR_CRYP2EN_Pos = 0x4
	// Bit mask of CRYP2EN field.
	RCC_RCC_MP_AHB3ENCLRR_CRYP2EN_Msk = 0x10
	// Bit CRYP2EN.
	RCC_RCC_MP_AHB3ENCLRR_CRYP2EN = 0x10
	// Position of HASH2EN field.
	RCC_RCC_MP_AHB3ENCLRR_HASH2EN_Pos = 0x5
	// Bit mask of HASH2EN field.
	RCC_RCC_MP_AHB3ENCLRR_HASH2EN_Msk = 0x20
	// Bit HASH2EN.
	RCC_RCC_MP_AHB3ENCLRR_HASH2EN = 0x20
	// Position of RNG2EN field.
	RCC_RCC_MP_AHB3ENCLRR_RNG2EN_Pos = 0x6
	// Bit mask of RNG2EN field.
	RCC_RCC_MP_AHB3ENCLRR_RNG2EN_Msk = 0x40
	// Bit RNG2EN.
	RCC_RCC_MP_AHB3ENCLRR_RNG2EN = 0x40
	// Position of CRC2EN field.
	RCC_RCC_MP_AHB3ENCLRR_CRC2EN_Pos = 0x7
	// Bit mask of CRC2EN field.
	RCC_RCC_MP_AHB3ENCLRR_CRC2EN_Msk = 0x80
	// Bit CRC2EN.
	RCC_RCC_MP_AHB3ENCLRR_CRC2EN = 0x80
	// Position of HSEMEN field.
	RCC_RCC_MP_AHB3ENCLRR_HSEMEN_Pos = 0xb
	// Bit mask of HSEMEN field.
	RCC_RCC_MP_AHB3ENCLRR_HSEMEN_Msk = 0x800
	// Bit HSEMEN.
	RCC_RCC_MP_AHB3ENCLRR_HSEMEN = 0x800
	// Position of IPCCEN field.
	RCC_RCC_MP_AHB3ENCLRR_IPCCEN_Pos = 0xc
	// Bit mask of IPCCEN field.
	RCC_RCC_MP_AHB3ENCLRR_IPCCEN_Msk = 0x1000
	// Bit IPCCEN.
	RCC_RCC_MP_AHB3ENCLRR_IPCCEN = 0x1000

	// RCC_MP_AHB4ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU.
	// Position of GPIOAEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOAEN = 0x1
	// Position of GPIOBEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOBEN = 0x2
	// Position of GPIOCEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOCEN = 0x4
	// Position of GPIODEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_RCC_MP_AHB4ENSETR_GPIODEN = 0x8
	// Position of GPIOEEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOEEN = 0x10
	// Position of GPIOFEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOFEN = 0x20
	// Position of GPIOGEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOGEN = 0x40
	// Position of GPIOHEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOHEN = 0x80
	// Position of GPIOIEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOIEN_Pos = 0x8
	// Bit mask of GPIOIEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOIEN_Msk = 0x100
	// Bit GPIOIEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOIEN = 0x100
	// Position of GPIOJEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOJEN_Pos = 0x9
	// Bit mask of GPIOJEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOJEN_Msk = 0x200
	// Bit GPIOJEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOJEN = 0x200
	// Position of GPIOKEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOKEN_Pos = 0xa
	// Bit mask of GPIOKEN field.
	RCC_RCC_MP_AHB4ENSETR_GPIOKEN_Msk = 0x400
	// Bit GPIOKEN.
	RCC_RCC_MP_AHB4ENSETR_GPIOKEN = 0x400

	// RCC_MP_AHB4ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of GPIOAEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOAEN = 0x1
	// Position of GPIOBEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOBEN = 0x2
	// Position of GPIOCEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOCEN = 0x4
	// Position of GPIODEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIODEN = 0x8
	// Position of GPIOEEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOEEN = 0x10
	// Position of GPIOFEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOFEN = 0x20
	// Position of GPIOGEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOGEN = 0x40
	// Position of GPIOHEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOHEN = 0x80
	// Position of GPIOIEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOIEN_Pos = 0x8
	// Bit mask of GPIOIEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOIEN_Msk = 0x100
	// Bit GPIOIEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOIEN = 0x100
	// Position of GPIOJEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOJEN_Pos = 0x9
	// Bit mask of GPIOJEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOJEN_Msk = 0x200
	// Bit GPIOJEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOJEN = 0x200
	// Position of GPIOKEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOKEN_Pos = 0xa
	// Bit mask of GPIOKEN field.
	RCC_RCC_MP_AHB4ENCLRR_GPIOKEN_Msk = 0x400
	// Bit GPIOKEN.
	RCC_RCC_MP_AHB4ENCLRR_GPIOKEN = 0x400

	// RCC_MP_MLAHBENSETR: This register is used to set the peripheral clock enable bit
	// Position of RETRAMEN field.
	RCC_RCC_MP_MLAHBENSETR_RETRAMEN_Pos = 0x4
	// Bit mask of RETRAMEN field.
	RCC_RCC_MP_MLAHBENSETR_RETRAMEN_Msk = 0x10
	// Bit RETRAMEN.
	RCC_RCC_MP_MLAHBENSETR_RETRAMEN = 0x10

	// RCC_MP_MLAHBENCLRR: This register is used to clear the peripheral clock enable bit.
	// Position of RETRAMEN field.
	RCC_RCC_MP_MLAHBENCLRR_RETRAMEN_Pos = 0x4
	// Bit mask of RETRAMEN field.
	RCC_RCC_MP_MLAHBENCLRR_RETRAMEN_Msk = 0x10
	// Bit RETRAMEN.
	RCC_RCC_MP_MLAHBENCLRR_RETRAMEN = 0x10

	// RCC_MC_APB1ENSETR: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to .
	// Position of TIM2EN field.
	RCC_RCC_MC_APB1ENSETR_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_RCC_MC_APB1ENSETR_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_RCC_MC_APB1ENSETR_TIM2EN = 0x1
	// Position of TIM3EN field.
	RCC_RCC_MC_APB1ENSETR_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_RCC_MC_APB1ENSETR_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_RCC_MC_APB1ENSETR_TIM3EN = 0x2
	// Position of TIM4EN field.
	RCC_RCC_MC_APB1ENSETR_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_RCC_MC_APB1ENSETR_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_RCC_MC_APB1ENSETR_TIM4EN = 0x4
	// Position of TIM5EN field.
	RCC_RCC_MC_APB1ENSETR_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_RCC_MC_APB1ENSETR_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_RCC_MC_APB1ENSETR_TIM5EN = 0x8
	// Position of TIM6EN field.
	RCC_RCC_MC_APB1ENSETR_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_RCC_MC_APB1ENSETR_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_RCC_MC_APB1ENSETR_TIM6EN = 0x10
	// Position of TIM7EN field.
	RCC_RCC_MC_APB1ENSETR_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_RCC_MC_APB1ENSETR_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_RCC_MC_APB1ENSETR_TIM7EN = 0x20
	// Position of TIM12EN field.
	RCC_RCC_MC_APB1ENSETR_TIM12EN_Pos = 0x6
	// Bit mask of TIM12EN field.
	RCC_RCC_MC_APB1ENSETR_TIM12EN_Msk = 0x40
	// Bit TIM12EN.
	RCC_RCC_MC_APB1ENSETR_TIM12EN = 0x40
	// Position of TIM13EN field.
	RCC_RCC_MC_APB1ENSETR_TIM13EN_Pos = 0x7
	// Bit mask of TIM13EN field.
	RCC_RCC_MC_APB1ENSETR_TIM13EN_Msk = 0x80
	// Bit TIM13EN.
	RCC_RCC_MC_APB1ENSETR_TIM13EN = 0x80
	// Position of TIM14EN field.
	RCC_RCC_MC_APB1ENSETR_TIM14EN_Pos = 0x8
	// Bit mask of TIM14EN field.
	RCC_RCC_MC_APB1ENSETR_TIM14EN_Msk = 0x100
	// Bit TIM14EN.
	RCC_RCC_MC_APB1ENSETR_TIM14EN = 0x100
	// Position of LPTIM1EN field.
	RCC_RCC_MC_APB1ENSETR_LPTIM1EN_Pos = 0x9
	// Bit mask of LPTIM1EN field.
	RCC_RCC_MC_APB1ENSETR_LPTIM1EN_Msk = 0x200
	// Bit LPTIM1EN.
	RCC_RCC_MC_APB1ENSETR_LPTIM1EN = 0x200
	// Position of SPI2EN field.
	RCC_RCC_MC_APB1ENSETR_SPI2EN_Pos = 0xb
	// Bit mask of SPI2EN field.
	RCC_RCC_MC_APB1ENSETR_SPI2EN_Msk = 0x800
	// Bit SPI2EN.
	RCC_RCC_MC_APB1ENSETR_SPI2EN = 0x800
	// Position of SPI3EN field.
	RCC_RCC_MC_APB1ENSETR_SPI3EN_Pos = 0xc
	// Bit mask of SPI3EN field.
	RCC_RCC_MC_APB1ENSETR_SPI3EN_Msk = 0x1000
	// Bit SPI3EN.
	RCC_RCC_MC_APB1ENSETR_SPI3EN = 0x1000
	// Position of USART2EN field.
	RCC_RCC_MC_APB1ENSETR_USART2EN_Pos = 0xe
	// Bit mask of USART2EN field.
	RCC_RCC_MC_APB1ENSETR_USART2EN_Msk = 0x4000
	// Bit USART2EN.
	RCC_RCC_MC_APB1ENSETR_USART2EN = 0x4000
	// Position of USART3EN field.
	RCC_RCC_MC_APB1ENSETR_USART3EN_Pos = 0xf
	// Bit mask of USART3EN field.
	RCC_RCC_MC_APB1ENSETR_USART3EN_Msk = 0x8000
	// Bit USART3EN.
	RCC_RCC_MC_APB1ENSETR_USART3EN = 0x8000
	// Position of UART4EN field.
	RCC_RCC_MC_APB1ENSETR_UART4EN_Pos = 0x10
	// Bit mask of UART4EN field.
	RCC_RCC_MC_APB1ENSETR_UART4EN_Msk = 0x10000
	// Bit UART4EN.
	RCC_RCC_MC_APB1ENSETR_UART4EN = 0x10000
	// Position of UART5EN field.
	RCC_RCC_MC_APB1ENSETR_UART5EN_Pos = 0x11
	// Bit mask of UART5EN field.
	RCC_RCC_MC_APB1ENSETR_UART5EN_Msk = 0x20000
	// Bit UART5EN.
	RCC_RCC_MC_APB1ENSETR_UART5EN = 0x20000
	// Position of UART7EN field.
	RCC_RCC_MC_APB1ENSETR_UART7EN_Pos = 0x12
	// Bit mask of UART7EN field.
	RCC_RCC_MC_APB1ENSETR_UART7EN_Msk = 0x40000
	// Bit UART7EN.
	RCC_RCC_MC_APB1ENSETR_UART7EN = 0x40000
	// Position of UART8EN field.
	RCC_RCC_MC_APB1ENSETR_UART8EN_Pos = 0x13
	// Bit mask of UART8EN field.
	RCC_RCC_MC_APB1ENSETR_UART8EN_Msk = 0x80000
	// Bit UART8EN.
	RCC_RCC_MC_APB1ENSETR_UART8EN = 0x80000
	// Position of I2C1EN field.
	RCC_RCC_MC_APB1ENSETR_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_RCC_MC_APB1ENSETR_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_RCC_MC_APB1ENSETR_I2C1EN = 0x200000
	// Position of I2C2EN field.
	RCC_RCC_MC_APB1ENSETR_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_RCC_MC_APB1ENSETR_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_RCC_MC_APB1ENSETR_I2C2EN = 0x400000
	// Position of I2C3EN field.
	RCC_RCC_MC_APB1ENSETR_I2C3EN_Pos = 0x17
	// Bit mask of I2C3EN field.
	RCC_RCC_MC_APB1ENSETR_I2C3EN_Msk = 0x800000
	// Bit I2C3EN.
	RCC_RCC_MC_APB1ENSETR_I2C3EN = 0x800000
	// Position of I2C5EN field.
	RCC_RCC_MC_APB1ENSETR_I2C5EN_Pos = 0x18
	// Bit mask of I2C5EN field.
	RCC_RCC_MC_APB1ENSETR_I2C5EN_Msk = 0x1000000
	// Bit I2C5EN.
	RCC_RCC_MC_APB1ENSETR_I2C5EN = 0x1000000
	// Position of SPDIFEN field.
	RCC_RCC_MC_APB1ENSETR_SPDIFEN_Pos = 0x1a
	// Bit mask of SPDIFEN field.
	RCC_RCC_MC_APB1ENSETR_SPDIFEN_Msk = 0x4000000
	// Bit SPDIFEN.
	RCC_RCC_MC_APB1ENSETR_SPDIFEN = 0x4000000
	// Position of CECEN field.
	RCC_RCC_MC_APB1ENSETR_CECEN_Pos = 0x1b
	// Bit mask of CECEN field.
	RCC_RCC_MC_APB1ENSETR_CECEN_Msk = 0x8000000
	// Bit CECEN.
	RCC_RCC_MC_APB1ENSETR_CECEN = 0x8000000
	// Position of WWDG1EN field.
	RCC_RCC_MC_APB1ENSETR_WWDG1EN_Pos = 0x1c
	// Bit mask of WWDG1EN field.
	RCC_RCC_MC_APB1ENSETR_WWDG1EN_Msk = 0x10000000
	// Bit WWDG1EN.
	RCC_RCC_MC_APB1ENSETR_WWDG1EN = 0x10000000
	// Position of DAC12EN field.
	RCC_RCC_MC_APB1ENSETR_DAC12EN_Pos = 0x1d
	// Bit mask of DAC12EN field.
	RCC_RCC_MC_APB1ENSETR_DAC12EN_Msk = 0x20000000
	// Bit DAC12EN.
	RCC_RCC_MC_APB1ENSETR_DAC12EN = 0x20000000
	// Position of MDIOSEN field.
	RCC_RCC_MC_APB1ENSETR_MDIOSEN_Pos = 0x1f
	// Bit mask of MDIOSEN field.
	RCC_RCC_MC_APB1ENSETR_MDIOSEN_Msk = 0x80000000
	// Bit MDIOSEN.
	RCC_RCC_MC_APB1ENSETR_MDIOSEN = 0x80000000

	// RCC_MC_APB1ENCLRR: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
	// Position of TIM2EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_RCC_MC_APB1ENCLRR_TIM2EN = 0x1
	// Position of TIM3EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_RCC_MC_APB1ENCLRR_TIM3EN = 0x2
	// Position of TIM4EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_RCC_MC_APB1ENCLRR_TIM4EN = 0x4
	// Position of TIM5EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_RCC_MC_APB1ENCLRR_TIM5EN = 0x8
	// Position of TIM6EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_RCC_MC_APB1ENCLRR_TIM6EN = 0x10
	// Position of TIM7EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_RCC_MC_APB1ENCLRR_TIM7EN = 0x20
	// Position of TIM12EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM12EN_Pos = 0x6
	// Bit mask of TIM12EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM12EN_Msk = 0x40
	// Bit TIM12EN.
	RCC_RCC_MC_APB1ENCLRR_TIM12EN = 0x40
	// Position of TIM13EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM13EN_Pos = 0x7
	// Bit mask of TIM13EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM13EN_Msk = 0x80
	// Bit TIM13EN.
	RCC_RCC_MC_APB1ENCLRR_TIM13EN = 0x80
	// Position of TIM14EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM14EN_Pos = 0x8
	// Bit mask of TIM14EN field.
	RCC_RCC_MC_APB1ENCLRR_TIM14EN_Msk = 0x100
	// Bit TIM14EN.
	RCC_RCC_MC_APB1ENCLRR_TIM14EN = 0x100
	// Position of LPTIM1EN field.
	RCC_RCC_MC_APB1ENCLRR_LPTIM1EN_Pos = 0x9
	// Bit mask of LPTIM1EN field.
	RCC_RCC_MC_APB1ENCLRR_LPTIM1EN_Msk = 0x200
	// Bit LPTIM1EN.
	RCC_RCC_MC_APB1ENCLRR_LPTIM1EN = 0x200
	// Position of SPI2EN field.
	RCC_RCC_MC_APB1ENCLRR_SPI2EN_Pos = 0xb
	// Bit mask of SPI2EN field.
	RCC_RCC_MC_APB1ENCLRR_SPI2EN_Msk = 0x800
	// Bit SPI2EN.
	RCC_RCC_MC_APB1ENCLRR_SPI2EN = 0x800
	// Position of SPI3EN field.
	RCC_RCC_MC_APB1ENCLRR_SPI3EN_Pos = 0xc
	// Bit mask of SPI3EN field.
	RCC_RCC_MC_APB1ENCLRR_SPI3EN_Msk = 0x1000
	// Bit SPI3EN.
	RCC_RCC_MC_APB1ENCLRR_SPI3EN = 0x1000
	// Position of USART2EN field.
	RCC_RCC_MC_APB1ENCLRR_USART2EN_Pos = 0xe
	// Bit mask of USART2EN field.
	RCC_RCC_MC_APB1ENCLRR_USART2EN_Msk = 0x4000
	// Bit USART2EN.
	RCC_RCC_MC_APB1ENCLRR_USART2EN = 0x4000
	// Position of USART3EN field.
	RCC_RCC_MC_APB1ENCLRR_USART3EN_Pos = 0xf
	// Bit mask of USART3EN field.
	RCC_RCC_MC_APB1ENCLRR_USART3EN_Msk = 0x8000
	// Bit USART3EN.
	RCC_RCC_MC_APB1ENCLRR_USART3EN = 0x8000
	// Position of UART4EN field.
	RCC_RCC_MC_APB1ENCLRR_UART4EN_Pos = 0x10
	// Bit mask of UART4EN field.
	RCC_RCC_MC_APB1ENCLRR_UART4EN_Msk = 0x10000
	// Bit UART4EN.
	RCC_RCC_MC_APB1ENCLRR_UART4EN = 0x10000
	// Position of UART5EN field.
	RCC_RCC_MC_APB1ENCLRR_UART5EN_Pos = 0x11
	// Bit mask of UART5EN field.
	RCC_RCC_MC_APB1ENCLRR_UART5EN_Msk = 0x20000
	// Bit UART5EN.
	RCC_RCC_MC_APB1ENCLRR_UART5EN = 0x20000
	// Position of UART7EN field.
	RCC_RCC_MC_APB1ENCLRR_UART7EN_Pos = 0x12
	// Bit mask of UART7EN field.
	RCC_RCC_MC_APB1ENCLRR_UART7EN_Msk = 0x40000
	// Bit UART7EN.
	RCC_RCC_MC_APB1ENCLRR_UART7EN = 0x40000
	// Position of UART8EN field.
	RCC_RCC_MC_APB1ENCLRR_UART8EN_Pos = 0x13
	// Bit mask of UART8EN field.
	RCC_RCC_MC_APB1ENCLRR_UART8EN_Msk = 0x80000
	// Bit UART8EN.
	RCC_RCC_MC_APB1ENCLRR_UART8EN = 0x80000
	// Position of I2C1EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_RCC_MC_APB1ENCLRR_I2C1EN = 0x200000
	// Position of I2C2EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_RCC_MC_APB1ENCLRR_I2C2EN = 0x400000
	// Position of I2C3EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C3EN_Pos = 0x17
	// Bit mask of I2C3EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C3EN_Msk = 0x800000
	// Bit I2C3EN.
	RCC_RCC_MC_APB1ENCLRR_I2C3EN = 0x800000
	// Position of I2C5EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C5EN_Pos = 0x18
	// Bit mask of I2C5EN field.
	RCC_RCC_MC_APB1ENCLRR_I2C5EN_Msk = 0x1000000
	// Bit I2C5EN.
	RCC_RCC_MC_APB1ENCLRR_I2C5EN = 0x1000000
	// Position of SPDIFEN field.
	RCC_RCC_MC_APB1ENCLRR_SPDIFEN_Pos = 0x1a
	// Bit mask of SPDIFEN field.
	RCC_RCC_MC_APB1ENCLRR_SPDIFEN_Msk = 0x4000000
	// Bit SPDIFEN.
	RCC_RCC_MC_APB1ENCLRR_SPDIFEN = 0x4000000
	// Position of CECEN field.
	RCC_RCC_MC_APB1ENCLRR_CECEN_Pos = 0x1b
	// Bit mask of CECEN field.
	RCC_RCC_MC_APB1ENCLRR_CECEN_Msk = 0x8000000
	// Bit CECEN.
	RCC_RCC_MC_APB1ENCLRR_CECEN = 0x8000000
	// Position of DAC12EN field.
	RCC_RCC_MC_APB1ENCLRR_DAC12EN_Pos = 0x1d
	// Bit mask of DAC12EN field.
	RCC_RCC_MC_APB1ENCLRR_DAC12EN_Msk = 0x20000000
	// Bit DAC12EN.
	RCC_RCC_MC_APB1ENCLRR_DAC12EN = 0x20000000
	// Position of MDIOSEN field.
	RCC_RCC_MC_APB1ENCLRR_MDIOSEN_Pos = 0x1f
	// Bit mask of MDIOSEN field.
	RCC_RCC_MC_APB1ENCLRR_MDIOSEN_Msk = 0x80000000
	// Bit MDIOSEN.
	RCC_RCC_MC_APB1ENCLRR_MDIOSEN = 0x80000000

	// RCC_MC_APB2ENSETR: This register is used to set the peripheral clock enable bit
	// Position of TIM1EN field.
	RCC_RCC_MC_APB2ENSETR_TIM1EN_Pos = 0x0
	// Bit mask of TIM1EN field.
	RCC_RCC_MC_APB2ENSETR_TIM1EN_Msk = 0x1
	// Bit TIM1EN.
	RCC_RCC_MC_APB2ENSETR_TIM1EN = 0x1
	// Position of TIM8EN field.
	RCC_RCC_MC_APB2ENSETR_TIM8EN_Pos = 0x1
	// Bit mask of TIM8EN field.
	RCC_RCC_MC_APB2ENSETR_TIM8EN_Msk = 0x2
	// Bit TIM8EN.
	RCC_RCC_MC_APB2ENSETR_TIM8EN = 0x2
	// Position of TIM15EN field.
	RCC_RCC_MC_APB2ENSETR_TIM15EN_Pos = 0x2
	// Bit mask of TIM15EN field.
	RCC_RCC_MC_APB2ENSETR_TIM15EN_Msk = 0x4
	// Bit TIM15EN.
	RCC_RCC_MC_APB2ENSETR_TIM15EN = 0x4
	// Position of TIM16EN field.
	RCC_RCC_MC_APB2ENSETR_TIM16EN_Pos = 0x3
	// Bit mask of TIM16EN field.
	RCC_RCC_MC_APB2ENSETR_TIM16EN_Msk = 0x8
	// Bit TIM16EN.
	RCC_RCC_MC_APB2ENSETR_TIM16EN = 0x8
	// Position of TIM17EN field.
	RCC_RCC_MC_APB2ENSETR_TIM17EN_Pos = 0x4
	// Bit mask of TIM17EN field.
	RCC_RCC_MC_APB2ENSETR_TIM17EN_Msk = 0x10
	// Bit TIM17EN.
	RCC_RCC_MC_APB2ENSETR_TIM17EN = 0x10
	// Position of SPI1EN field.
	RCC_RCC_MC_APB2ENSETR_SPI1EN_Pos = 0x8
	// Bit mask of SPI1EN field.
	RCC_RCC_MC_APB2ENSETR_SPI1EN_Msk = 0x100
	// Bit SPI1EN.
	RCC_RCC_MC_APB2ENSETR_SPI1EN = 0x100
	// Position of SPI4EN field.
	RCC_RCC_MC_APB2ENSETR_SPI4EN_Pos = 0x9
	// Bit mask of SPI4EN field.
	RCC_RCC_MC_APB2ENSETR_SPI4EN_Msk = 0x200
	// Bit SPI4EN.
	RCC_RCC_MC_APB2ENSETR_SPI4EN = 0x200
	// Position of SPI5EN field.
	RCC_RCC_MC_APB2ENSETR_SPI5EN_Pos = 0xa
	// Bit mask of SPI5EN field.
	RCC_RCC_MC_APB2ENSETR_SPI5EN_Msk = 0x400
	// Bit SPI5EN.
	RCC_RCC_MC_APB2ENSETR_SPI5EN = 0x400
	// Position of USART6EN field.
	RCC_RCC_MC_APB2ENSETR_USART6EN_Pos = 0xd
	// Bit mask of USART6EN field.
	RCC_RCC_MC_APB2ENSETR_USART6EN_Msk = 0x2000
	// Bit USART6EN.
	RCC_RCC_MC_APB2ENSETR_USART6EN = 0x2000
	// Position of SAI1EN field.
	RCC_RCC_MC_APB2ENSETR_SAI1EN_Pos = 0x10
	// Bit mask of SAI1EN field.
	RCC_RCC_MC_APB2ENSETR_SAI1EN_Msk = 0x10000
	// Bit SAI1EN.
	RCC_RCC_MC_APB2ENSETR_SAI1EN = 0x10000
	// Position of SAI2EN field.
	RCC_RCC_MC_APB2ENSETR_SAI2EN_Pos = 0x11
	// Bit mask of SAI2EN field.
	RCC_RCC_MC_APB2ENSETR_SAI2EN_Msk = 0x20000
	// Bit SAI2EN.
	RCC_RCC_MC_APB2ENSETR_SAI2EN = 0x20000
	// Position of SAI3EN field.
	RCC_RCC_MC_APB2ENSETR_SAI3EN_Pos = 0x12
	// Bit mask of SAI3EN field.
	RCC_RCC_MC_APB2ENSETR_SAI3EN_Msk = 0x40000
	// Bit SAI3EN.
	RCC_RCC_MC_APB2ENSETR_SAI3EN = 0x40000
	// Position of DFSDMEN field.
	RCC_RCC_MC_APB2ENSETR_DFSDMEN_Pos = 0x14
	// Bit mask of DFSDMEN field.
	RCC_RCC_MC_APB2ENSETR_DFSDMEN_Msk = 0x100000
	// Bit DFSDMEN.
	RCC_RCC_MC_APB2ENSETR_DFSDMEN = 0x100000
	// Position of ADFSDMEN field.
	RCC_RCC_MC_APB2ENSETR_ADFSDMEN_Pos = 0x15
	// Bit mask of ADFSDMEN field.
	RCC_RCC_MC_APB2ENSETR_ADFSDMEN_Msk = 0x200000
	// Bit ADFSDMEN.
	RCC_RCC_MC_APB2ENSETR_ADFSDMEN = 0x200000
	// Position of FDCANEN field.
	RCC_RCC_MC_APB2ENSETR_FDCANEN_Pos = 0x18
	// Bit mask of FDCANEN field.
	RCC_RCC_MC_APB2ENSETR_FDCANEN_Msk = 0x1000000
	// Bit FDCANEN.
	RCC_RCC_MC_APB2ENSETR_FDCANEN = 0x1000000

	// RCC_MC_APB2ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of TIM1EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM1EN_Pos = 0x0
	// Bit mask of TIM1EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM1EN_Msk = 0x1
	// Bit TIM1EN.
	RCC_RCC_MC_APB2ENCLRR_TIM1EN = 0x1
	// Position of TIM8EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM8EN_Pos = 0x1
	// Bit mask of TIM8EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM8EN_Msk = 0x2
	// Bit TIM8EN.
	RCC_RCC_MC_APB2ENCLRR_TIM8EN = 0x2
	// Position of TIM15EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM15EN_Pos = 0x2
	// Bit mask of TIM15EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM15EN_Msk = 0x4
	// Bit TIM15EN.
	RCC_RCC_MC_APB2ENCLRR_TIM15EN = 0x4
	// Position of TIM16EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM16EN_Pos = 0x3
	// Bit mask of TIM16EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM16EN_Msk = 0x8
	// Bit TIM16EN.
	RCC_RCC_MC_APB2ENCLRR_TIM16EN = 0x8
	// Position of TIM17EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM17EN_Pos = 0x4
	// Bit mask of TIM17EN field.
	RCC_RCC_MC_APB2ENCLRR_TIM17EN_Msk = 0x10
	// Bit TIM17EN.
	RCC_RCC_MC_APB2ENCLRR_TIM17EN = 0x10
	// Position of SPI1EN field.
	RCC_RCC_MC_APB2ENCLRR_SPI1EN_Pos = 0x8
	// Bit mask of SPI1EN field.
	RCC_RCC_MC_APB2ENCLRR_SPI1EN_Msk = 0x100
	// Bit SPI1EN.
	RCC_RCC_MC_APB2ENCLRR_SPI1EN = 0x100
	// Position of SPI4EN field.
	RCC_RCC_MC_APB2ENCLRR_SPI4EN_Pos = 0x9
	// Bit mask of SPI4EN field.
	RCC_RCC_MC_APB2ENCLRR_SPI4EN_Msk = 0x200
	// Bit SPI4EN.
	RCC_RCC_MC_APB2ENCLRR_SPI4EN = 0x200
	// Position of SPI5EN field.
	RCC_RCC_MC_APB2ENCLRR_SPI5EN_Pos = 0xa
	// Bit mask of SPI5EN field.
	RCC_RCC_MC_APB2ENCLRR_SPI5EN_Msk = 0x400
	// Bit SPI5EN.
	RCC_RCC_MC_APB2ENCLRR_SPI5EN = 0x400
	// Position of USART6EN field.
	RCC_RCC_MC_APB2ENCLRR_USART6EN_Pos = 0xd
	// Bit mask of USART6EN field.
	RCC_RCC_MC_APB2ENCLRR_USART6EN_Msk = 0x2000
	// Bit USART6EN.
	RCC_RCC_MC_APB2ENCLRR_USART6EN = 0x2000
	// Position of SAI1EN field.
	RCC_RCC_MC_APB2ENCLRR_SAI1EN_Pos = 0x10
	// Bit mask of SAI1EN field.
	RCC_RCC_MC_APB2ENCLRR_SAI1EN_Msk = 0x10000
	// Bit SAI1EN.
	RCC_RCC_MC_APB2ENCLRR_SAI1EN = 0x10000
	// Position of SAI2EN field.
	RCC_RCC_MC_APB2ENCLRR_SAI2EN_Pos = 0x11
	// Bit mask of SAI2EN field.
	RCC_RCC_MC_APB2ENCLRR_SAI2EN_Msk = 0x20000
	// Bit SAI2EN.
	RCC_RCC_MC_APB2ENCLRR_SAI2EN = 0x20000
	// Position of SAI3EN field.
	RCC_RCC_MC_APB2ENCLRR_SAI3EN_Pos = 0x12
	// Bit mask of SAI3EN field.
	RCC_RCC_MC_APB2ENCLRR_SAI3EN_Msk = 0x40000
	// Bit SAI3EN.
	RCC_RCC_MC_APB2ENCLRR_SAI3EN = 0x40000
	// Position of DFSDMEN field.
	RCC_RCC_MC_APB2ENCLRR_DFSDMEN_Pos = 0x14
	// Bit mask of DFSDMEN field.
	RCC_RCC_MC_APB2ENCLRR_DFSDMEN_Msk = 0x100000
	// Bit DFSDMEN.
	RCC_RCC_MC_APB2ENCLRR_DFSDMEN = 0x100000
	// Position of ADFSDMEN field.
	RCC_RCC_MC_APB2ENCLRR_ADFSDMEN_Pos = 0x15
	// Bit mask of ADFSDMEN field.
	RCC_RCC_MC_APB2ENCLRR_ADFSDMEN_Msk = 0x200000
	// Bit ADFSDMEN.
	RCC_RCC_MC_APB2ENCLRR_ADFSDMEN = 0x200000
	// Position of FDCANEN field.
	RCC_RCC_MC_APB2ENCLRR_FDCANEN_Pos = 0x18
	// Bit mask of FDCANEN field.
	RCC_RCC_MC_APB2ENCLRR_FDCANEN_Msk = 0x1000000
	// Bit FDCANEN.
	RCC_RCC_MC_APB2ENCLRR_FDCANEN = 0x1000000

	// RCC_MC_APB3ENSETR: This register is used to set the peripheral clock enable bit
	// Position of LPTIM2EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM2EN_Pos = 0x0
	// Bit mask of LPTIM2EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM2EN_Msk = 0x1
	// Bit LPTIM2EN.
	RCC_RCC_MC_APB3ENSETR_LPTIM2EN = 0x1
	// Position of LPTIM3EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM3EN_Pos = 0x1
	// Bit mask of LPTIM3EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM3EN_Msk = 0x2
	// Bit LPTIM3EN.
	RCC_RCC_MC_APB3ENSETR_LPTIM3EN = 0x2
	// Position of LPTIM4EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM4EN_Pos = 0x2
	// Bit mask of LPTIM4EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM4EN_Msk = 0x4
	// Bit LPTIM4EN.
	RCC_RCC_MC_APB3ENSETR_LPTIM4EN = 0x4
	// Position of LPTIM5EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM5EN_Pos = 0x3
	// Bit mask of LPTIM5EN field.
	RCC_RCC_MC_APB3ENSETR_LPTIM5EN_Msk = 0x8
	// Bit LPTIM5EN.
	RCC_RCC_MC_APB3ENSETR_LPTIM5EN = 0x8
	// Position of SAI4EN field.
	RCC_RCC_MC_APB3ENSETR_SAI4EN_Pos = 0x8
	// Bit mask of SAI4EN field.
	RCC_RCC_MC_APB3ENSETR_SAI4EN_Msk = 0x100
	// Bit SAI4EN.
	RCC_RCC_MC_APB3ENSETR_SAI4EN = 0x100
	// Position of SYSCFGEN field.
	RCC_RCC_MC_APB3ENSETR_SYSCFGEN_Pos = 0xb
	// Bit mask of SYSCFGEN field.
	RCC_RCC_MC_APB3ENSETR_SYSCFGEN_Msk = 0x800
	// Bit SYSCFGEN.
	RCC_RCC_MC_APB3ENSETR_SYSCFGEN = 0x800
	// Position of VREFEN field.
	RCC_RCC_MC_APB3ENSETR_VREFEN_Pos = 0xd
	// Bit mask of VREFEN field.
	RCC_RCC_MC_APB3ENSETR_VREFEN_Msk = 0x2000
	// Bit VREFEN.
	RCC_RCC_MC_APB3ENSETR_VREFEN = 0x2000
	// Position of DTSEN field.
	RCC_RCC_MC_APB3ENSETR_DTSEN_Pos = 0x10
	// Bit mask of DTSEN field.
	RCC_RCC_MC_APB3ENSETR_DTSEN_Msk = 0x10000
	// Bit DTSEN.
	RCC_RCC_MC_APB3ENSETR_DTSEN = 0x10000
	// Position of HDPEN field.
	RCC_RCC_MC_APB3ENSETR_HDPEN_Pos = 0x14
	// Bit mask of HDPEN field.
	RCC_RCC_MC_APB3ENSETR_HDPEN_Msk = 0x100000
	// Bit HDPEN.
	RCC_RCC_MC_APB3ENSETR_HDPEN = 0x100000

	// RCC_MC_APB3ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of LPTIM2EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM2EN_Pos = 0x0
	// Bit mask of LPTIM2EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM2EN_Msk = 0x1
	// Bit LPTIM2EN.
	RCC_RCC_MC_APB3ENCLRR_LPTIM2EN = 0x1
	// Position of LPTIM3EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM3EN_Pos = 0x1
	// Bit mask of LPTIM3EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM3EN_Msk = 0x2
	// Bit LPTIM3EN.
	RCC_RCC_MC_APB3ENCLRR_LPTIM3EN = 0x2
	// Position of LPTIM4EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM4EN_Pos = 0x2
	// Bit mask of LPTIM4EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM4EN_Msk = 0x4
	// Bit LPTIM4EN.
	RCC_RCC_MC_APB3ENCLRR_LPTIM4EN = 0x4
	// Position of LPTIM5EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM5EN_Pos = 0x3
	// Bit mask of LPTIM5EN field.
	RCC_RCC_MC_APB3ENCLRR_LPTIM5EN_Msk = 0x8
	// Bit LPTIM5EN.
	RCC_RCC_MC_APB3ENCLRR_LPTIM5EN = 0x8
	// Position of SAI4EN field.
	RCC_RCC_MC_APB3ENCLRR_SAI4EN_Pos = 0x8
	// Bit mask of SAI4EN field.
	RCC_RCC_MC_APB3ENCLRR_SAI4EN_Msk = 0x100
	// Bit SAI4EN.
	RCC_RCC_MC_APB3ENCLRR_SAI4EN = 0x100
	// Position of SYSCFGEN field.
	RCC_RCC_MC_APB3ENCLRR_SYSCFGEN_Pos = 0xb
	// Bit mask of SYSCFGEN field.
	RCC_RCC_MC_APB3ENCLRR_SYSCFGEN_Msk = 0x800
	// Bit SYSCFGEN.
	RCC_RCC_MC_APB3ENCLRR_SYSCFGEN = 0x800
	// Position of VREFEN field.
	RCC_RCC_MC_APB3ENCLRR_VREFEN_Pos = 0xd
	// Bit mask of VREFEN field.
	RCC_RCC_MC_APB3ENCLRR_VREFEN_Msk = 0x2000
	// Bit VREFEN.
	RCC_RCC_MC_APB3ENCLRR_VREFEN = 0x2000
	// Position of DTSEN field.
	RCC_RCC_MC_APB3ENCLRR_DTSEN_Pos = 0x10
	// Bit mask of DTSEN field.
	RCC_RCC_MC_APB3ENCLRR_DTSEN_Msk = 0x10000
	// Bit DTSEN.
	RCC_RCC_MC_APB3ENCLRR_DTSEN = 0x10000
	// Position of HDPEN field.
	RCC_RCC_MC_APB3ENCLRR_HDPEN_Pos = 0x14
	// Bit mask of HDPEN field.
	RCC_RCC_MC_APB3ENCLRR_HDPEN_Msk = 0x100000
	// Bit HDPEN.
	RCC_RCC_MC_APB3ENCLRR_HDPEN = 0x100000

	// RCC_MC_AHB2ENSETR: This register is used to set the peripheral clock enable bit
	// Position of DMA1EN field.
	RCC_RCC_MC_AHB2ENSETR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_RCC_MC_AHB2ENSETR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_RCC_MC_AHB2ENSETR_DMA1EN = 0x1
	// Position of DMA2EN field.
	RCC_RCC_MC_AHB2ENSETR_DMA2EN_Pos = 0x1
	// Bit mask of DMA2EN field.
	RCC_RCC_MC_AHB2ENSETR_DMA2EN_Msk = 0x2
	// Bit DMA2EN.
	RCC_RCC_MC_AHB2ENSETR_DMA2EN = 0x2
	// Position of DMAMUXEN field.
	RCC_RCC_MC_AHB2ENSETR_DMAMUXEN_Pos = 0x2
	// Bit mask of DMAMUXEN field.
	RCC_RCC_MC_AHB2ENSETR_DMAMUXEN_Msk = 0x4
	// Bit DMAMUXEN.
	RCC_RCC_MC_AHB2ENSETR_DMAMUXEN = 0x4
	// Position of ADC12EN field.
	RCC_RCC_MC_AHB2ENSETR_ADC12EN_Pos = 0x5
	// Bit mask of ADC12EN field.
	RCC_RCC_MC_AHB2ENSETR_ADC12EN_Msk = 0x20
	// Bit ADC12EN.
	RCC_RCC_MC_AHB2ENSETR_ADC12EN = 0x20
	// Position of USBOEN field.
	RCC_RCC_MC_AHB2ENSETR_USBOEN_Pos = 0x8
	// Bit mask of USBOEN field.
	RCC_RCC_MC_AHB2ENSETR_USBOEN_Msk = 0x100
	// Bit USBOEN.
	RCC_RCC_MC_AHB2ENSETR_USBOEN = 0x100
	// Position of SDMMC3EN field.
	RCC_RCC_MC_AHB2ENSETR_SDMMC3EN_Pos = 0x10
	// Bit mask of SDMMC3EN field.
	RCC_RCC_MC_AHB2ENSETR_SDMMC3EN_Msk = 0x10000
	// Bit SDMMC3EN.
	RCC_RCC_MC_AHB2ENSETR_SDMMC3EN = 0x10000

	// RCC_MC_AHB2ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of DMA1EN field.
	RCC_RCC_MC_AHB2ENCLRR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_RCC_MC_AHB2ENCLRR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_RCC_MC_AHB2ENCLRR_DMA1EN = 0x1
	// Position of DMA2EN field.
	RCC_RCC_MC_AHB2ENCLRR_DMA2EN_Pos = 0x1
	// Bit mask of DMA2EN field.
	RCC_RCC_MC_AHB2ENCLRR_DMA2EN_Msk = 0x2
	// Bit DMA2EN.
	RCC_RCC_MC_AHB2ENCLRR_DMA2EN = 0x2
	// Position of DMAMUXEN field.
	RCC_RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos = 0x2
	// Bit mask of DMAMUXEN field.
	RCC_RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk = 0x4
	// Bit DMAMUXEN.
	RCC_RCC_MC_AHB2ENCLRR_DMAMUXEN = 0x4
	// Position of ADC12EN field.
	RCC_RCC_MC_AHB2ENCLRR_ADC12EN_Pos = 0x5
	// Bit mask of ADC12EN field.
	RCC_RCC_MC_AHB2ENCLRR_ADC12EN_Msk = 0x20
	// Bit ADC12EN.
	RCC_RCC_MC_AHB2ENCLRR_ADC12EN = 0x20
	// Position of USBOEN field.
	RCC_RCC_MC_AHB2ENCLRR_USBOEN_Pos = 0x8
	// Bit mask of USBOEN field.
	RCC_RCC_MC_AHB2ENCLRR_USBOEN_Msk = 0x100
	// Bit USBOEN.
	RCC_RCC_MC_AHB2ENCLRR_USBOEN = 0x100
	// Position of SDMMC3EN field.
	RCC_RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos = 0x10
	// Bit mask of SDMMC3EN field.
	RCC_RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk = 0x10000
	// Bit SDMMC3EN.
	RCC_RCC_MC_AHB2ENCLRR_SDMMC3EN = 0x10000

	// RCC_MC_AHB3ENSETR: This register is used to set the peripheral clock enable bit
	// Position of DCMIEN field.
	RCC_RCC_MC_AHB3ENSETR_DCMIEN_Pos = 0x0
	// Bit mask of DCMIEN field.
	RCC_RCC_MC_AHB3ENSETR_DCMIEN_Msk = 0x1
	// Bit DCMIEN.
	RCC_RCC_MC_AHB3ENSETR_DCMIEN = 0x1
	// Position of CRYP2EN field.
	RCC_RCC_MC_AHB3ENSETR_CRYP2EN_Pos = 0x4
	// Bit mask of CRYP2EN field.
	RCC_RCC_MC_AHB3ENSETR_CRYP2EN_Msk = 0x10
	// Bit CRYP2EN.
	RCC_RCC_MC_AHB3ENSETR_CRYP2EN = 0x10
	// Position of HASH2EN field.
	RCC_RCC_MC_AHB3ENSETR_HASH2EN_Pos = 0x5
	// Bit mask of HASH2EN field.
	RCC_RCC_MC_AHB3ENSETR_HASH2EN_Msk = 0x20
	// Bit HASH2EN.
	RCC_RCC_MC_AHB3ENSETR_HASH2EN = 0x20
	// Position of RNG2EN field.
	RCC_RCC_MC_AHB3ENSETR_RNG2EN_Pos = 0x6
	// Bit mask of RNG2EN field.
	RCC_RCC_MC_AHB3ENSETR_RNG2EN_Msk = 0x40
	// Bit RNG2EN.
	RCC_RCC_MC_AHB3ENSETR_RNG2EN = 0x40
	// Position of CRC2EN field.
	RCC_RCC_MC_AHB3ENSETR_CRC2EN_Pos = 0x7
	// Bit mask of CRC2EN field.
	RCC_RCC_MC_AHB3ENSETR_CRC2EN_Msk = 0x80
	// Bit CRC2EN.
	RCC_RCC_MC_AHB3ENSETR_CRC2EN = 0x80
	// Position of HSEMEN field.
	RCC_RCC_MC_AHB3ENSETR_HSEMEN_Pos = 0xb
	// Bit mask of HSEMEN field.
	RCC_RCC_MC_AHB3ENSETR_HSEMEN_Msk = 0x800
	// Bit HSEMEN.
	RCC_RCC_MC_AHB3ENSETR_HSEMEN = 0x800
	// Position of IPCCEN field.
	RCC_RCC_MC_AHB3ENSETR_IPCCEN_Pos = 0xc
	// Bit mask of IPCCEN field.
	RCC_RCC_MC_AHB3ENSETR_IPCCEN_Msk = 0x1000
	// Bit IPCCEN.
	RCC_RCC_MC_AHB3ENSETR_IPCCEN = 0x1000

	// RCC_MC_AHB3ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of DCMIEN field.
	RCC_RCC_MC_AHB3ENCLRR_DCMIEN_Pos = 0x0
	// Bit mask of DCMIEN field.
	RCC_RCC_MC_AHB3ENCLRR_DCMIEN_Msk = 0x1
	// Bit DCMIEN.
	RCC_RCC_MC_AHB3ENCLRR_DCMIEN = 0x1
	// Position of CRYP2EN field.
	RCC_RCC_MC_AHB3ENCLRR_CRYP2EN_Pos = 0x4
	// Bit mask of CRYP2EN field.
	RCC_RCC_MC_AHB3ENCLRR_CRYP2EN_Msk = 0x10
	// Bit CRYP2EN.
	RCC_RCC_MC_AHB3ENCLRR_CRYP2EN = 0x10
	// Position of HASH2EN field.
	RCC_RCC_MC_AHB3ENCLRR_HASH2EN_Pos = 0x5
	// Bit mask of HASH2EN field.
	RCC_RCC_MC_AHB3ENCLRR_HASH2EN_Msk = 0x20
	// Bit HASH2EN.
	RCC_RCC_MC_AHB3ENCLRR_HASH2EN = 0x20
	// Position of RNG2EN field.
	RCC_RCC_MC_AHB3ENCLRR_RNG2EN_Pos = 0x6
	// Bit mask of RNG2EN field.
	RCC_RCC_MC_AHB3ENCLRR_RNG2EN_Msk = 0x40
	// Bit RNG2EN.
	RCC_RCC_MC_AHB3ENCLRR_RNG2EN = 0x40
	// Position of CRC2EN field.
	RCC_RCC_MC_AHB3ENCLRR_CRC2EN_Pos = 0x7
	// Bit mask of CRC2EN field.
	RCC_RCC_MC_AHB3ENCLRR_CRC2EN_Msk = 0x80
	// Bit CRC2EN.
	RCC_RCC_MC_AHB3ENCLRR_CRC2EN = 0x80
	// Position of HSEMEN field.
	RCC_RCC_MC_AHB3ENCLRR_HSEMEN_Pos = 0xb
	// Bit mask of HSEMEN field.
	RCC_RCC_MC_AHB3ENCLRR_HSEMEN_Msk = 0x800
	// Bit HSEMEN.
	RCC_RCC_MC_AHB3ENCLRR_HSEMEN = 0x800
	// Position of IPCCEN field.
	RCC_RCC_MC_AHB3ENCLRR_IPCCEN_Pos = 0xc
	// Bit mask of IPCCEN field.
	RCC_RCC_MC_AHB3ENCLRR_IPCCEN_Msk = 0x1000
	// Bit IPCCEN.
	RCC_RCC_MC_AHB3ENCLRR_IPCCEN = 0x1000

	// RCC_MC_AHB4ENSETR: This register is used to set the peripheral clock enable bit
	// Position of GPIOAEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOAEN = 0x1
	// Position of GPIOBEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOBEN = 0x2
	// Position of GPIOCEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOCEN = 0x4
	// Position of GPIODEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_RCC_MC_AHB4ENSETR_GPIODEN = 0x8
	// Position of GPIOEEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOEEN = 0x10
	// Position of GPIOFEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOFEN = 0x20
	// Position of GPIOGEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOGEN = 0x40
	// Position of GPIOHEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOHEN = 0x80
	// Position of GPIOIEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOIEN_Pos = 0x8
	// Bit mask of GPIOIEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOIEN_Msk = 0x100
	// Bit GPIOIEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOIEN = 0x100
	// Position of GPIOJEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOJEN_Pos = 0x9
	// Bit mask of GPIOJEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOJEN_Msk = 0x200
	// Bit GPIOJEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOJEN = 0x200
	// Position of GPIOKEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOKEN_Pos = 0xa
	// Bit mask of GPIOKEN field.
	RCC_RCC_MC_AHB4ENSETR_GPIOKEN_Msk = 0x400
	// Bit GPIOKEN.
	RCC_RCC_MC_AHB4ENSETR_GPIOKEN = 0x400

	// RCC_MC_AHB4ENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of GPIOAEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOAEN = 0x1
	// Position of GPIOBEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOBEN = 0x2
	// Position of GPIOCEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOCEN = 0x4
	// Position of GPIODEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIODEN = 0x8
	// Position of GPIOEEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOEEN = 0x10
	// Position of GPIOFEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOFEN = 0x20
	// Position of GPIOGEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOGEN = 0x40
	// Position of GPIOHEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOHEN = 0x80
	// Position of GPIOIEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOIEN_Pos = 0x8
	// Bit mask of GPIOIEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOIEN_Msk = 0x100
	// Bit GPIOIEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOIEN = 0x100
	// Position of GPIOJEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOJEN_Pos = 0x9
	// Bit mask of GPIOJEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOJEN_Msk = 0x200
	// Bit GPIOJEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOJEN = 0x200
	// Position of GPIOKEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOKEN_Pos = 0xa
	// Bit mask of GPIOKEN field.
	RCC_RCC_MC_AHB4ENCLRR_GPIOKEN_Msk = 0x400
	// Bit GPIOKEN.
	RCC_RCC_MC_AHB4ENCLRR_GPIOKEN = 0x400

	// RCC_MC_AXIMENSETR: This register is used to set the peripheral clock enable bit
	// Position of SYSRAMEN field.
	RCC_RCC_MC_AXIMENSETR_SYSRAMEN_Pos = 0x0
	// Bit mask of SYSRAMEN field.
	RCC_RCC_MC_AXIMENSETR_SYSRAMEN_Msk = 0x1
	// Bit SYSRAMEN.
	RCC_RCC_MC_AXIMENSETR_SYSRAMEN = 0x1

	// RCC_MC_AXIMENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of SYSRAMEN field.
	RCC_RCC_MC_AXIMENCLRR_SYSRAMEN_Pos = 0x0
	// Bit mask of SYSRAMEN field.
	RCC_RCC_MC_AXIMENCLRR_SYSRAMEN_Msk = 0x1
	// Bit SYSRAMEN.
	RCC_RCC_MC_AXIMENCLRR_SYSRAMEN = 0x1

	// RCC_MC_MLAHBENSETR: This register is used to set the peripheral clock enable bit
	// Position of RETRAMEN field.
	RCC_RCC_MC_MLAHBENSETR_RETRAMEN_Pos = 0x4
	// Bit mask of RETRAMEN field.
	RCC_RCC_MC_MLAHBENSETR_RETRAMEN_Msk = 0x10
	// Bit RETRAMEN.
	RCC_RCC_MC_MLAHBENSETR_RETRAMEN = 0x10

	// RCC_MC_MLAHBENCLRR: This register is used to clear the peripheral clock enable bit
	// Position of RETRAMEN field.
	RCC_RCC_MC_MLAHBENCLRR_RETRAMEN_Pos = 0x4
	// Bit mask of RETRAMEN field.
	RCC_RCC_MC_MLAHBENCLRR_RETRAMEN_Msk = 0x10
	// Bit RETRAMEN.
	RCC_RCC_MC_MLAHBENCLRR_RETRAMEN = 0x10

	// RCC_MP_APB1LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of TIM2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM2LPEN_Pos = 0x0
	// Bit mask of TIM2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM2LPEN_Msk = 0x1
	// Bit TIM2LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM2LPEN = 0x1
	// Position of TIM3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM3LPEN_Pos = 0x1
	// Bit mask of TIM3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM3LPEN_Msk = 0x2
	// Bit TIM3LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM3LPEN = 0x2
	// Position of TIM4LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM4LPEN_Pos = 0x2
	// Bit mask of TIM4LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM4LPEN_Msk = 0x4
	// Bit TIM4LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM4LPEN = 0x4
	// Position of TIM5LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM5LPEN_Pos = 0x3
	// Bit mask of TIM5LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM5LPEN_Msk = 0x8
	// Bit TIM5LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM5LPEN = 0x8
	// Position of TIM6LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM6LPEN_Pos = 0x4
	// Bit mask of TIM6LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM6LPEN_Msk = 0x10
	// Bit TIM6LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM6LPEN = 0x10
	// Position of TIM7LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM7LPEN_Pos = 0x5
	// Bit mask of TIM7LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM7LPEN_Msk = 0x20
	// Bit TIM7LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM7LPEN = 0x20
	// Position of TIM12LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM12LPEN_Pos = 0x6
	// Bit mask of TIM12LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM12LPEN_Msk = 0x40
	// Bit TIM12LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM12LPEN = 0x40
	// Position of TIM13LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM13LPEN_Pos = 0x7
	// Bit mask of TIM13LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM13LPEN_Msk = 0x80
	// Bit TIM13LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM13LPEN = 0x80
	// Position of TIM14LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM14LPEN_Pos = 0x8
	// Bit mask of TIM14LPEN field.
	RCC_RCC_MP_APB1LPENSETR_TIM14LPEN_Msk = 0x100
	// Bit TIM14LPEN.
	RCC_RCC_MP_APB1LPENSETR_TIM14LPEN = 0x100
	// Position of LPTIM1LPEN field.
	RCC_RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos = 0x9
	// Bit mask of LPTIM1LPEN field.
	RCC_RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk = 0x200
	// Bit LPTIM1LPEN.
	RCC_RCC_MP_APB1LPENSETR_LPTIM1LPEN = 0x200
	// Position of SPI2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_SPI2LPEN_Pos = 0xb
	// Bit mask of SPI2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_SPI2LPEN_Msk = 0x800
	// Bit SPI2LPEN.
	RCC_RCC_MP_APB1LPENSETR_SPI2LPEN = 0x800
	// Position of SPI3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_SPI3LPEN_Pos = 0xc
	// Bit mask of SPI3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_SPI3LPEN_Msk = 0x1000
	// Bit SPI3LPEN.
	RCC_RCC_MP_APB1LPENSETR_SPI3LPEN = 0x1000
	// Position of USART2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_USART2LPEN_Pos = 0xe
	// Bit mask of USART2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_USART2LPEN_Msk = 0x4000
	// Bit USART2LPEN.
	RCC_RCC_MP_APB1LPENSETR_USART2LPEN = 0x4000
	// Position of USART3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_USART3LPEN_Pos = 0xf
	// Bit mask of USART3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_USART3LPEN_Msk = 0x8000
	// Bit USART3LPEN.
	RCC_RCC_MP_APB1LPENSETR_USART3LPEN = 0x8000
	// Position of UART4LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART4LPEN_Pos = 0x10
	// Bit mask of UART4LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART4LPEN_Msk = 0x10000
	// Bit UART4LPEN.
	RCC_RCC_MP_APB1LPENSETR_UART4LPEN = 0x10000
	// Position of UART5LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART5LPEN_Pos = 0x11
	// Bit mask of UART5LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART5LPEN_Msk = 0x20000
	// Bit UART5LPEN.
	RCC_RCC_MP_APB1LPENSETR_UART5LPEN = 0x20000
	// Position of UART7LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART7LPEN_Pos = 0x12
	// Bit mask of UART7LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART7LPEN_Msk = 0x40000
	// Bit UART7LPEN.
	RCC_RCC_MP_APB1LPENSETR_UART7LPEN = 0x40000
	// Position of UART8LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART8LPEN_Pos = 0x13
	// Bit mask of UART8LPEN field.
	RCC_RCC_MP_APB1LPENSETR_UART8LPEN_Msk = 0x80000
	// Bit UART8LPEN.
	RCC_RCC_MP_APB1LPENSETR_UART8LPEN = 0x80000
	// Position of I2C1LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C1LPEN_Pos = 0x15
	// Bit mask of I2C1LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C1LPEN_Msk = 0x200000
	// Bit I2C1LPEN.
	RCC_RCC_MP_APB1LPENSETR_I2C1LPEN = 0x200000
	// Position of I2C2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C2LPEN_Pos = 0x16
	// Bit mask of I2C2LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C2LPEN_Msk = 0x400000
	// Bit I2C2LPEN.
	RCC_RCC_MP_APB1LPENSETR_I2C2LPEN = 0x400000
	// Position of I2C3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C3LPEN_Pos = 0x17
	// Bit mask of I2C3LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C3LPEN_Msk = 0x800000
	// Bit I2C3LPEN.
	RCC_RCC_MP_APB1LPENSETR_I2C3LPEN = 0x800000
	// Position of I2C5LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C5LPEN_Pos = 0x18
	// Bit mask of I2C5LPEN field.
	RCC_RCC_MP_APB1LPENSETR_I2C5LPEN_Msk = 0x1000000
	// Bit I2C5LPEN.
	RCC_RCC_MP_APB1LPENSETR_I2C5LPEN = 0x1000000
	// Position of SPDIFLPEN field.
	RCC_RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos = 0x1a
	// Bit mask of SPDIFLPEN field.
	RCC_RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk = 0x4000000
	// Bit SPDIFLPEN.
	RCC_RCC_MP_APB1LPENSETR_SPDIFLPEN = 0x4000000
	// Position of CECLPEN field.
	RCC_RCC_MP_APB1LPENSETR_CECLPEN_Pos = 0x1b
	// Bit mask of CECLPEN field.
	RCC_RCC_MP_APB1LPENSETR_CECLPEN_Msk = 0x8000000
	// Bit CECLPEN.
	RCC_RCC_MP_APB1LPENSETR_CECLPEN = 0x8000000
	// Position of DAC12LPEN field.
	RCC_RCC_MP_APB1LPENSETR_DAC12LPEN_Pos = 0x1d
	// Bit mask of DAC12LPEN field.
	RCC_RCC_MP_APB1LPENSETR_DAC12LPEN_Msk = 0x20000000
	// Bit DAC12LPEN.
	RCC_RCC_MP_APB1LPENSETR_DAC12LPEN = 0x20000000
	// Position of MDIOSLPEN field.
	RCC_RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos = 0x1f
	// Bit mask of MDIOSLPEN field.
	RCC_RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk = 0x80000000
	// Bit MDIOSLPEN.
	RCC_RCC_MP_APB1LPENSETR_MDIOSLPEN = 0x80000000

	// RCC_MP_APB1LPENCLRR: This register is used by the MPU in order to clear the PERxLPEN bits .
	// Position of TIM2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos = 0x0
	// Bit mask of TIM2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk = 0x1
	// Bit TIM2LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM2LPEN = 0x1
	// Position of TIM3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos = 0x1
	// Bit mask of TIM3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk = 0x2
	// Bit TIM3LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM3LPEN = 0x2
	// Position of TIM4LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos = 0x2
	// Bit mask of TIM4LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk = 0x4
	// Bit TIM4LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM4LPEN = 0x4
	// Position of TIM5LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos = 0x3
	// Bit mask of TIM5LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk = 0x8
	// Bit TIM5LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM5LPEN = 0x8
	// Position of TIM6LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos = 0x4
	// Bit mask of TIM6LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk = 0x10
	// Bit TIM6LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM6LPEN = 0x10
	// Position of TIM7LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos = 0x5
	// Bit mask of TIM7LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk = 0x20
	// Bit TIM7LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM7LPEN = 0x20
	// Position of TIM12LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos = 0x6
	// Bit mask of TIM12LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk = 0x40
	// Bit TIM12LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM12LPEN = 0x40
	// Position of TIM13LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos = 0x7
	// Bit mask of TIM13LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk = 0x80
	// Bit TIM13LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM13LPEN = 0x80
	// Position of TIM14LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos = 0x8
	// Bit mask of TIM14LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk = 0x100
	// Bit TIM14LPEN.
	RCC_RCC_MP_APB1LPENCLRR_TIM14LPEN = 0x100
	// Position of LPTIM1LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos = 0x9
	// Bit mask of LPTIM1LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk = 0x200
	// Bit LPTIM1LPEN.
	RCC_RCC_MP_APB1LPENCLRR_LPTIM1LPEN = 0x200
	// Position of SPI2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos = 0xb
	// Bit mask of SPI2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk = 0x800
	// Bit SPI2LPEN.
	RCC_RCC_MP_APB1LPENCLRR_SPI2LPEN = 0x800
	// Position of SPI3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos = 0xc
	// Bit mask of SPI3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk = 0x1000
	// Bit SPI3LPEN.
	RCC_RCC_MP_APB1LPENCLRR_SPI3LPEN = 0x1000
	// Position of USART2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_USART2LPEN_Pos = 0xe
	// Bit mask of USART2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_USART2LPEN_Msk = 0x4000
	// Bit USART2LPEN.
	RCC_RCC_MP_APB1LPENCLRR_USART2LPEN = 0x4000
	// Position of USART3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_USART3LPEN_Pos = 0xf
	// Bit mask of USART3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_USART3LPEN_Msk = 0x8000
	// Bit USART3LPEN.
	RCC_RCC_MP_APB1LPENCLRR_USART3LPEN = 0x8000
	// Position of UART4LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART4LPEN_Pos = 0x10
	// Bit mask of UART4LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART4LPEN_Msk = 0x10000
	// Bit UART4LPEN.
	RCC_RCC_MP_APB1LPENCLRR_UART4LPEN = 0x10000
	// Position of UART5LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART5LPEN_Pos = 0x11
	// Bit mask of UART5LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART5LPEN_Msk = 0x20000
	// Bit UART5LPEN.
	RCC_RCC_MP_APB1LPENCLRR_UART5LPEN = 0x20000
	// Position of UART7LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART7LPEN_Pos = 0x12
	// Bit mask of UART7LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART7LPEN_Msk = 0x40000
	// Bit UART7LPEN.
	RCC_RCC_MP_APB1LPENCLRR_UART7LPEN = 0x40000
	// Position of UART8LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART8LPEN_Pos = 0x13
	// Bit mask of UART8LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_UART8LPEN_Msk = 0x80000
	// Bit UART8LPEN.
	RCC_RCC_MP_APB1LPENCLRR_UART8LPEN = 0x80000
	// Position of I2C1LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos = 0x15
	// Bit mask of I2C1LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk = 0x200000
	// Bit I2C1LPEN.
	RCC_RCC_MP_APB1LPENCLRR_I2C1LPEN = 0x200000
	// Position of I2C2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos = 0x16
	// Bit mask of I2C2LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk = 0x400000
	// Bit I2C2LPEN.
	RCC_RCC_MP_APB1LPENCLRR_I2C2LPEN = 0x400000
	// Position of I2C3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos = 0x17
	// Bit mask of I2C3LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk = 0x800000
	// Bit I2C3LPEN.
	RCC_RCC_MP_APB1LPENCLRR_I2C3LPEN = 0x800000
	// Position of I2C5LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos = 0x18
	// Bit mask of I2C5LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk = 0x1000000
	// Bit I2C5LPEN.
	RCC_RCC_MP_APB1LPENCLRR_I2C5LPEN = 0x1000000
	// Position of SPDIFLPEN field.
	RCC_RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos = 0x1a
	// Bit mask of SPDIFLPEN field.
	RCC_RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk = 0x4000000
	// Bit SPDIFLPEN.
	RCC_RCC_MP_APB1LPENCLRR_SPDIFLPEN = 0x4000000
	// Position of CECLPEN field.
	RCC_RCC_MP_APB1LPENCLRR_CECLPEN_Pos = 0x1b
	// Bit mask of CECLPEN field.
	RCC_RCC_MP_APB1LPENCLRR_CECLPEN_Msk = 0x8000000
	// Bit CECLPEN.
	RCC_RCC_MP_APB1LPENCLRR_CECLPEN = 0x8000000
	// Position of DAC12LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos = 0x1d
	// Bit mask of DAC12LPEN field.
	RCC_RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk = 0x20000000
	// Bit DAC12LPEN.
	RCC_RCC_MP_APB1LPENCLRR_DAC12LPEN = 0x20000000
	// Position of MDIOSLPEN field.
	RCC_RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos = 0x1f
	// Bit mask of MDIOSLPEN field.
	RCC_RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk = 0x80000000
	// Bit MDIOSLPEN.
	RCC_RCC_MP_APB1LPENCLRR_MDIOSLPEN = 0x80000000

	// RCC_MP_APB2LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of TIM1LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM1LPEN_Pos = 0x0
	// Bit mask of TIM1LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM1LPEN_Msk = 0x1
	// Bit TIM1LPEN.
	RCC_RCC_MP_APB2LPENSETR_TIM1LPEN = 0x1
	// Position of TIM8LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM8LPEN_Pos = 0x1
	// Bit mask of TIM8LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM8LPEN_Msk = 0x2
	// Bit TIM8LPEN.
	RCC_RCC_MP_APB2LPENSETR_TIM8LPEN = 0x2
	// Position of TIM15LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM15LPEN_Pos = 0x2
	// Bit mask of TIM15LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM15LPEN_Msk = 0x4
	// Bit TIM15LPEN.
	RCC_RCC_MP_APB2LPENSETR_TIM15LPEN = 0x4
	// Position of TIM16LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM16LPEN_Pos = 0x3
	// Bit mask of TIM16LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM16LPEN_Msk = 0x8
	// Bit TIM16LPEN.
	RCC_RCC_MP_APB2LPENSETR_TIM16LPEN = 0x8
	// Position of TIM17LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM17LPEN_Pos = 0x4
	// Bit mask of TIM17LPEN field.
	RCC_RCC_MP_APB2LPENSETR_TIM17LPEN_Msk = 0x10
	// Bit TIM17LPEN.
	RCC_RCC_MP_APB2LPENSETR_TIM17LPEN = 0x10
	// Position of SPI1LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SPI1LPEN_Pos = 0x8
	// Bit mask of SPI1LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SPI1LPEN_Msk = 0x100
	// Bit SPI1LPEN.
	RCC_RCC_MP_APB2LPENSETR_SPI1LPEN = 0x100
	// Position of SPI4LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SPI4LPEN_Pos = 0x9
	// Bit mask of SPI4LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SPI4LPEN_Msk = 0x200
	// Bit SPI4LPEN.
	RCC_RCC_MP_APB2LPENSETR_SPI4LPEN = 0x200
	// Position of SPI5LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SPI5LPEN_Pos = 0xa
	// Bit mask of SPI5LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SPI5LPEN_Msk = 0x400
	// Bit SPI5LPEN.
	RCC_RCC_MP_APB2LPENSETR_SPI5LPEN = 0x400
	// Position of USART6LPEN field.
	RCC_RCC_MP_APB2LPENSETR_USART6LPEN_Pos = 0xd
	// Bit mask of USART6LPEN field.
	RCC_RCC_MP_APB2LPENSETR_USART6LPEN_Msk = 0x2000
	// Bit USART6LPEN.
	RCC_RCC_MP_APB2LPENSETR_USART6LPEN = 0x2000
	// Position of SAI1LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SAI1LPEN_Pos = 0x10
	// Bit mask of SAI1LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SAI1LPEN_Msk = 0x10000
	// Bit SAI1LPEN.
	RCC_RCC_MP_APB2LPENSETR_SAI1LPEN = 0x10000
	// Position of SAI2LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SAI2LPEN_Pos = 0x11
	// Bit mask of SAI2LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SAI2LPEN_Msk = 0x20000
	// Bit SAI2LPEN.
	RCC_RCC_MP_APB2LPENSETR_SAI2LPEN = 0x20000
	// Position of SAI3LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SAI3LPEN_Pos = 0x12
	// Bit mask of SAI3LPEN field.
	RCC_RCC_MP_APB2LPENSETR_SAI3LPEN_Msk = 0x40000
	// Bit SAI3LPEN.
	RCC_RCC_MP_APB2LPENSETR_SAI3LPEN = 0x40000
	// Position of DFSDMLPEN field.
	RCC_RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos = 0x14
	// Bit mask of DFSDMLPEN field.
	RCC_RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk = 0x100000
	// Bit DFSDMLPEN.
	RCC_RCC_MP_APB2LPENSETR_DFSDMLPEN = 0x100000
	// Position of ADFSDMLPEN field.
	RCC_RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos = 0x15
	// Bit mask of ADFSDMLPEN field.
	RCC_RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk = 0x200000
	// Bit ADFSDMLPEN.
	RCC_RCC_MP_APB2LPENSETR_ADFSDMLPEN = 0x200000
	// Position of FDCANLPEN field.
	RCC_RCC_MP_APB2LPENSETR_FDCANLPEN_Pos = 0x18
	// Bit mask of FDCANLPEN field.
	RCC_RCC_MP_APB2LPENSETR_FDCANLPEN_Msk = 0x1000000
	// Bit FDCANLPEN.
	RCC_RCC_MP_APB2LPENSETR_FDCANLPEN = 0x1000000

	// RCC_MP_APB2LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of TIM1LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos = 0x0
	// Bit mask of TIM1LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk = 0x1
	// Bit TIM1LPEN.
	RCC_RCC_MP_APB2LPENCLRR_TIM1LPEN = 0x1
	// Position of TIM8LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos = 0x1
	// Bit mask of TIM8LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk = 0x2
	// Bit TIM8LPEN.
	RCC_RCC_MP_APB2LPENCLRR_TIM8LPEN = 0x2
	// Position of TIM15LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos = 0x2
	// Bit mask of TIM15LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk = 0x4
	// Bit TIM15LPEN.
	RCC_RCC_MP_APB2LPENCLRR_TIM15LPEN = 0x4
	// Position of TIM16LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos = 0x3
	// Bit mask of TIM16LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk = 0x8
	// Bit TIM16LPEN.
	RCC_RCC_MP_APB2LPENCLRR_TIM16LPEN = 0x8
	// Position of TIM17LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos = 0x4
	// Bit mask of TIM17LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk = 0x10
	// Bit TIM17LPEN.
	RCC_RCC_MP_APB2LPENCLRR_TIM17LPEN = 0x10
	// Position of SPI1LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos = 0x8
	// Bit mask of SPI1LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk = 0x100
	// Bit SPI1LPEN.
	RCC_RCC_MP_APB2LPENCLRR_SPI1LPEN = 0x100
	// Position of SPI4LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos = 0x9
	// Bit mask of SPI4LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk = 0x200
	// Bit SPI4LPEN.
	RCC_RCC_MP_APB2LPENCLRR_SPI4LPEN = 0x200
	// Position of SPI5LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos = 0xa
	// Bit mask of SPI5LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk = 0x400
	// Bit SPI5LPEN.
	RCC_RCC_MP_APB2LPENCLRR_SPI5LPEN = 0x400
	// Position of USART6LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_USART6LPEN_Pos = 0xd
	// Bit mask of USART6LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_USART6LPEN_Msk = 0x2000
	// Bit USART6LPEN.
	RCC_RCC_MP_APB2LPENCLRR_USART6LPEN = 0x2000
	// Position of SAI1LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos = 0x10
	// Bit mask of SAI1LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk = 0x10000
	// Bit SAI1LPEN.
	RCC_RCC_MP_APB2LPENCLRR_SAI1LPEN = 0x10000
	// Position of SAI2LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos = 0x11
	// Bit mask of SAI2LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk = 0x20000
	// Bit SAI2LPEN.
	RCC_RCC_MP_APB2LPENCLRR_SAI2LPEN = 0x20000
	// Position of SAI3LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos = 0x12
	// Bit mask of SAI3LPEN field.
	RCC_RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk = 0x40000
	// Bit SAI3LPEN.
	RCC_RCC_MP_APB2LPENCLRR_SAI3LPEN = 0x40000
	// Position of DFSDMLPEN field.
	RCC_RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos = 0x14
	// Bit mask of DFSDMLPEN field.
	RCC_RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk = 0x100000
	// Bit DFSDMLPEN.
	RCC_RCC_MP_APB2LPENCLRR_DFSDMLPEN = 0x100000
	// Position of ADFSDMLPEN field.
	RCC_RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos = 0x15
	// Bit mask of ADFSDMLPEN field.
	RCC_RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk = 0x200000
	// Bit ADFSDMLPEN.
	RCC_RCC_MP_APB2LPENCLRR_ADFSDMLPEN = 0x200000
	// Position of FDCANLPEN field.
	RCC_RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos = 0x18
	// Bit mask of FDCANLPEN field.
	RCC_RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk = 0x1000000
	// Bit FDCANLPEN.
	RCC_RCC_MP_APB2LPENCLRR_FDCANLPEN = 0x1000000

	// RCC_MP_APB3LPENSETR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of LPTIM2LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos = 0x0
	// Bit mask of LPTIM2LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk = 0x1
	// Bit LPTIM2LPEN.
	RCC_RCC_MP_APB3LPENSETR_LPTIM2LPEN = 0x1
	// Position of LPTIM3LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos = 0x1
	// Bit mask of LPTIM3LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk = 0x2
	// Bit LPTIM3LPEN.
	RCC_RCC_MP_APB3LPENSETR_LPTIM3LPEN = 0x2
	// Position of LPTIM4LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos = 0x2
	// Bit mask of LPTIM4LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk = 0x4
	// Bit LPTIM4LPEN.
	RCC_RCC_MP_APB3LPENSETR_LPTIM4LPEN = 0x4
	// Position of LPTIM5LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos = 0x3
	// Bit mask of LPTIM5LPEN field.
	RCC_RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk = 0x8
	// Bit LPTIM5LPEN.
	RCC_RCC_MP_APB3LPENSETR_LPTIM5LPEN = 0x8
	// Position of SAI4LPEN field.
	RCC_RCC_MP_APB3LPENSETR_SAI4LPEN_Pos = 0x8
	// Bit mask of SAI4LPEN field.
	RCC_RCC_MP_APB3LPENSETR_SAI4LPEN_Msk = 0x100
	// Bit SAI4LPEN.
	RCC_RCC_MP_APB3LPENSETR_SAI4LPEN = 0x100
	// Position of SYSCFGLPEN field.
	RCC_RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos = 0xb
	// Bit mask of SYSCFGLPEN field.
	RCC_RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk = 0x800
	// Bit SYSCFGLPEN.
	RCC_RCC_MP_APB3LPENSETR_SYSCFGLPEN = 0x800
	// Position of VREFLPEN field.
	RCC_RCC_MP_APB3LPENSETR_VREFLPEN_Pos = 0xd
	// Bit mask of VREFLPEN field.
	RCC_RCC_MP_APB3LPENSETR_VREFLPEN_Msk = 0x2000
	// Bit VREFLPEN.
	RCC_RCC_MP_APB3LPENSETR_VREFLPEN = 0x2000
	// Position of DTSLPEN field.
	RCC_RCC_MP_APB3LPENSETR_DTSLPEN_Pos = 0x10
	// Bit mask of DTSLPEN field.
	RCC_RCC_MP_APB3LPENSETR_DTSLPEN_Msk = 0x10000
	// Bit DTSLPEN.
	RCC_RCC_MP_APB3LPENSETR_DTSLPEN = 0x10000

	// RCC_MP_APB3LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of LPTIM2LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos = 0x0
	// Bit mask of LPTIM2LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk = 0x1
	// Bit LPTIM2LPEN.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM2LPEN = 0x1
	// Position of LPTIM3LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos = 0x1
	// Bit mask of LPTIM3LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk = 0x2
	// Bit LPTIM3LPEN.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM3LPEN = 0x2
	// Position of LPTIM4LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos = 0x2
	// Bit mask of LPTIM4LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk = 0x4
	// Bit LPTIM4LPEN.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM4LPEN = 0x4
	// Position of LPTIM5LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos = 0x3
	// Bit mask of LPTIM5LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk = 0x8
	// Bit LPTIM5LPEN.
	RCC_RCC_MP_APB3LPENCLRR_LPTIM5LPEN = 0x8
	// Position of SAI4LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos = 0x8
	// Bit mask of SAI4LPEN field.
	RCC_RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk = 0x100
	// Bit SAI4LPEN.
	RCC_RCC_MP_APB3LPENCLRR_SAI4LPEN = 0x100
	// Position of SYSCFGLPEN field.
	RCC_RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos = 0xb
	// Bit mask of SYSCFGLPEN field.
	RCC_RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk = 0x800
	// Bit SYSCFGLPEN.
	RCC_RCC_MP_APB3LPENCLRR_SYSCFGLPEN = 0x800
	// Position of VREFLPEN field.
	RCC_RCC_MP_APB3LPENCLRR_VREFLPEN_Pos = 0xd
	// Bit mask of VREFLPEN field.
	RCC_RCC_MP_APB3LPENCLRR_VREFLPEN_Msk = 0x2000
	// Bit VREFLPEN.
	RCC_RCC_MP_APB3LPENCLRR_VREFLPEN = 0x2000
	// Position of DTSLPEN field.
	RCC_RCC_MP_APB3LPENCLRR_DTSLPEN_Pos = 0x10
	// Bit mask of DTSLPEN field.
	RCC_RCC_MP_APB3LPENCLRR_DTSLPEN_Msk = 0x10000
	// Bit DTSLPEN.
	RCC_RCC_MP_APB3LPENCLRR_DTSLPEN = 0x10000

	// RCC_MP_AHB2LPENSETR: This register is used by the MPU in order to set the PERxLPEN bit.
	// Position of DMA1LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos = 0x0
	// Bit mask of DMA1LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk = 0x1
	// Bit DMA1LPEN.
	RCC_RCC_MP_AHB2LPENSETR_DMA1LPEN = 0x1
	// Position of DMA2LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos = 0x1
	// Bit mask of DMA2LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk = 0x2
	// Bit DMA2LPEN.
	RCC_RCC_MP_AHB2LPENSETR_DMA2LPEN = 0x2
	// Position of DMAMUXLPEN field.
	RCC_RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos = 0x2
	// Bit mask of DMAMUXLPEN field.
	RCC_RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk = 0x4
	// Bit DMAMUXLPEN.
	RCC_RCC_MP_AHB2LPENSETR_DMAMUXLPEN = 0x4
	// Position of ADC12LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos = 0x5
	// Bit mask of ADC12LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk = 0x20
	// Bit ADC12LPEN.
	RCC_RCC_MP_AHB2LPENSETR_ADC12LPEN = 0x20
	// Position of USBOLPEN field.
	RCC_RCC_MP_AHB2LPENSETR_USBOLPEN_Pos = 0x8
	// Bit mask of USBOLPEN field.
	RCC_RCC_MP_AHB2LPENSETR_USBOLPEN_Msk = 0x100
	// Bit USBOLPEN.
	RCC_RCC_MP_AHB2LPENSETR_USBOLPEN = 0x100
	// Position of SDMMC3LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos = 0x10
	// Bit mask of SDMMC3LPEN field.
	RCC_RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk = 0x10000
	// Bit SDMMC3LPEN.
	RCC_RCC_MP_AHB2LPENSETR_SDMMC3LPEN = 0x10000

	// RCC_MP_AHB2LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of DMA1LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos = 0x0
	// Bit mask of DMA1LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk = 0x1
	// Bit DMA1LPEN.
	RCC_RCC_MP_AHB2LPENCLRR_DMA1LPEN = 0x1
	// Position of DMA2LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos = 0x1
	// Bit mask of DMA2LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk = 0x2
	// Bit DMA2LPEN.
	RCC_RCC_MP_AHB2LPENCLRR_DMA2LPEN = 0x2
	// Position of DMAMUXLPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos = 0x2
	// Bit mask of DMAMUXLPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk = 0x4
	// Bit DMAMUXLPEN.
	RCC_RCC_MP_AHB2LPENCLRR_DMAMUXLPEN = 0x4
	// Position of ADC12LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos = 0x5
	// Bit mask of ADC12LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk = 0x20
	// Bit ADC12LPEN.
	RCC_RCC_MP_AHB2LPENCLRR_ADC12LPEN = 0x20
	// Position of USBOLPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos = 0x8
	// Bit mask of USBOLPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk = 0x100
	// Bit USBOLPEN.
	RCC_RCC_MP_AHB2LPENCLRR_USBOLPEN = 0x100
	// Position of SDMMC3LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos = 0x10
	// Bit mask of SDMMC3LPEN field.
	RCC_RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk = 0x10000
	// Bit SDMMC3LPEN.
	RCC_RCC_MP_AHB2LPENCLRR_SDMMC3LPEN = 0x10000

	// RCC_MP_AHB3LPENSETR: This register is used by the MPU
	// Position of DCMILPEN field.
	RCC_RCC_MP_AHB3LPENSETR_DCMILPEN_Pos = 0x0
	// Bit mask of DCMILPEN field.
	RCC_RCC_MP_AHB3LPENSETR_DCMILPEN_Msk = 0x1
	// Bit DCMILPEN.
	RCC_RCC_MP_AHB3LPENSETR_DCMILPEN = 0x1
	// Position of CRYP2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos = 0x4
	// Bit mask of CRYP2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk = 0x10
	// Bit CRYP2LPEN.
	RCC_RCC_MP_AHB3LPENSETR_CRYP2LPEN = 0x10
	// Position of HASH2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos = 0x5
	// Bit mask of HASH2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk = 0x20
	// Bit HASH2LPEN.
	RCC_RCC_MP_AHB3LPENSETR_HASH2LPEN = 0x20
	// Position of RNG2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos = 0x6
	// Bit mask of RNG2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk = 0x40
	// Bit RNG2LPEN.
	RCC_RCC_MP_AHB3LPENSETR_RNG2LPEN = 0x40
	// Position of CRC2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos = 0x7
	// Bit mask of CRC2LPEN field.
	RCC_RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk = 0x80
	// Bit CRC2LPEN.
	RCC_RCC_MP_AHB3LPENSETR_CRC2LPEN = 0x80
	// Position of HSEMLPEN field.
	RCC_RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos = 0xb
	// Bit mask of HSEMLPEN field.
	RCC_RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk = 0x800
	// Bit HSEMLPEN.
	RCC_RCC_MP_AHB3LPENSETR_HSEMLPEN = 0x800
	// Position of IPCCLPEN field.
	RCC_RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos = 0xc
	// Bit mask of IPCCLPEN field.
	RCC_RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk = 0x1000
	// Bit IPCCLPEN.
	RCC_RCC_MP_AHB3LPENSETR_IPCCLPEN = 0x1000

	// RCC_MP_AHB3LPENCLRR: This register is used by the MPU in order to clear the PERxLPEN bit
	// Position of DCMILPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos = 0x0
	// Bit mask of DCMILPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk = 0x1
	// Bit DCMILPEN.
	RCC_RCC_MP_AHB3LPENCLRR_DCMILPEN = 0x1
	// Position of CRYP2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos = 0x4
	// Bit mask of CRYP2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk = 0x10
	// Bit CRYP2LPEN.
	RCC_RCC_MP_AHB3LPENCLRR_CRYP2LPEN = 0x10
	// Position of HASH2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos = 0x5
	// Bit mask of HASH2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk = 0x20
	// Bit HASH2LPEN.
	RCC_RCC_MP_AHB3LPENCLRR_HASH2LPEN = 0x20
	// Position of RNG2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos = 0x6
	// Bit mask of RNG2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk = 0x40
	// Bit RNG2LPEN.
	RCC_RCC_MP_AHB3LPENCLRR_RNG2LPEN = 0x40
	// Position of CRC2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos = 0x7
	// Bit mask of CRC2LPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk = 0x80
	// Bit CRC2LPEN.
	RCC_RCC_MP_AHB3LPENCLRR_CRC2LPEN = 0x80
	// Position of HSEMLPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos = 0xb
	// Bit mask of HSEMLPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk = 0x800
	// Bit HSEMLPEN.
	RCC_RCC_MP_AHB3LPENCLRR_HSEMLPEN = 0x800
	// Position of IPCCLPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos = 0xc
	// Bit mask of IPCCLPEN field.
	RCC_RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk = 0x1000
	// Bit IPCCLPEN.
	RCC_RCC_MP_AHB3LPENCLRR_IPCCLPEN = 0x1000

	// RCC_MP_AHB4LPENSETR: This register is used by the MPU
	// Position of GPIOALPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos = 0x0
	// Bit mask of GPIOALPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk = 0x1
	// Bit GPIOALPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOALPEN = 0x1
	// Position of GPIOBLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos = 0x1
	// Bit mask of GPIOBLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk = 0x2
	// Bit GPIOBLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOBLPEN = 0x2
	// Position of GPIOCLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos = 0x2
	// Bit mask of GPIOCLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk = 0x4
	// Bit GPIOCLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOCLPEN = 0x4
	// Position of GPIODLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos = 0x3
	// Bit mask of GPIODLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk = 0x8
	// Bit GPIODLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIODLPEN = 0x8
	// Position of GPIOELPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos = 0x4
	// Bit mask of GPIOELPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk = 0x10
	// Bit GPIOELPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOELPEN = 0x10
	// Position of GPIOFLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos = 0x5
	// Bit mask of GPIOFLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk = 0x20
	// Bit GPIOFLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOFLPEN = 0x20
	// Position of GPIOGLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos = 0x6
	// Bit mask of GPIOGLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk = 0x40
	// Bit GPIOGLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOGLPEN = 0x40
	// Position of GPIOHLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos = 0x7
	// Bit mask of GPIOHLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk = 0x80
	// Bit GPIOHLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOHLPEN = 0x80
	// Position of GPIOILPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos = 0x8
	// Bit mask of GPIOILPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk = 0x100
	// Bit GPIOILPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOILPEN = 0x100
	// Position of GPIOJLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos = 0x9
	// Bit mask of GPIOJLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk = 0x200
	// Bit GPIOJLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOJLPEN = 0x200
	// Position of GPIOKLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos = 0xa
	// Bit mask of GPIOKLPEN field.
	RCC_RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk = 0x400
	// Bit GPIOKLPEN.
	RCC_RCC_MP_AHB4LPENSETR_GPIOKLPEN = 0x400

	// RCC_MP_AHB4LPENCLRR: This register is used by the MPU
	// Position of GPIOALPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos = 0x0
	// Bit mask of GPIOALPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk = 0x1
	// Bit GPIOALPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOALPEN = 0x1
	// Position of GPIOBLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos = 0x1
	// Bit mask of GPIOBLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk = 0x2
	// Bit GPIOBLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOBLPEN = 0x2
	// Position of GPIOCLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos = 0x2
	// Bit mask of GPIOCLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk = 0x4
	// Bit GPIOCLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOCLPEN = 0x4
	// Position of GPIODLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos = 0x3
	// Bit mask of GPIODLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk = 0x8
	// Bit GPIODLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIODLPEN = 0x8
	// Position of GPIOELPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos = 0x4
	// Bit mask of GPIOELPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk = 0x10
	// Bit GPIOELPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOELPEN = 0x10
	// Position of GPIOFLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos = 0x5
	// Bit mask of GPIOFLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk = 0x20
	// Bit GPIOFLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOFLPEN = 0x20
	// Position of GPIOGLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos = 0x6
	// Bit mask of GPIOGLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk = 0x40
	// Bit GPIOGLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOGLPEN = 0x40
	// Position of GPIOHLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos = 0x7
	// Bit mask of GPIOHLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk = 0x80
	// Bit GPIOHLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOHLPEN = 0x80
	// Position of GPIOILPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos = 0x8
	// Bit mask of GPIOILPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk = 0x100
	// Bit GPIOILPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOILPEN = 0x100
	// Position of GPIOJLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos = 0x9
	// Bit mask of GPIOJLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk = 0x200
	// Bit GPIOJLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOJLPEN = 0x200
	// Position of GPIOKLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos = 0xa
	// Bit mask of GPIOKLPEN field.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk = 0x400
	// Bit GPIOKLPEN.
	RCC_RCC_MP_AHB4LPENCLRR_GPIOKLPEN = 0x400

	// RCC_MP_AXIMLPENSETR: This register is used by the MPU
	// Position of SYSRAMLPEN field.
	RCC_RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos = 0x0
	// Bit mask of SYSRAMLPEN field.
	RCC_RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk = 0x1
	// Bit SYSRAMLPEN.
	RCC_RCC_MP_AXIMLPENSETR_SYSRAMLPEN = 0x1

	// RCC_MP_AXIMLPENCLRR: This register is used by the MPU
	// Position of SYSRAMLPEN field.
	RCC_RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos = 0x0
	// Bit mask of SYSRAMLPEN field.
	RCC_RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk = 0x1
	// Bit SYSRAMLPEN.
	RCC_RCC_MP_AXIMLPENCLRR_SYSRAMLPEN = 0x1

	// RCC_MP_MLAHBLPENSETR: This register is used by the MPU in order to set the PERxLPEN bit
	// Position of SRAM1LPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos = 0x0
	// Bit mask of SRAM1LPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk = 0x1
	// Bit SRAM1LPEN.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM1LPEN = 0x1
	// Position of SRAM2LPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos = 0x1
	// Bit mask of SRAM2LPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk = 0x2
	// Bit SRAM2LPEN.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM2LPEN = 0x2
	// Position of SRAM34LPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos = 0x2
	// Bit mask of SRAM34LPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk = 0x4
	// Bit SRAM34LPEN.
	RCC_RCC_MP_MLAHBLPENSETR_SRAM34LPEN = 0x4
	// Position of RETRAMLPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos = 0x4
	// Bit mask of RETRAMLPEN field.
	RCC_RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk = 0x10
	// Bit RETRAMLPEN.
	RCC_RCC_MP_MLAHBLPENSETR_RETRAMLPEN = 0x10

	// RCC_MP_MLAHBLPENCLRR: This register is used by the MPU in order to clear the PERxLPEN bit
	// Position of SRAM1LPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos = 0x0
	// Bit mask of SRAM1LPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk = 0x1
	// Bit SRAM1LPEN.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM1LPEN = 0x1
	// Position of SRAM2LPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos = 0x1
	// Bit mask of SRAM2LPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk = 0x2
	// Bit SRAM2LPEN.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM2LPEN = 0x2
	// Position of SRAM34LPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos = 0x2
	// Bit mask of SRAM34LPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk = 0x4
	// Bit SRAM34LPEN.
	RCC_RCC_MP_MLAHBLPENCLRR_SRAM34LPEN = 0x4
	// Position of RETRAMLPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos = 0x4
	// Bit mask of RETRAMLPEN field.
	RCC_RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk = 0x10
	// Bit RETRAMLPEN.
	RCC_RCC_MP_MLAHBLPENCLRR_RETRAMLPEN = 0x10

	// RCC_MC_APB1LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of TIM2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM2LPEN_Pos = 0x0
	// Bit mask of TIM2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM2LPEN_Msk = 0x1
	// Bit TIM2LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM2LPEN = 0x1
	// Position of TIM3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM3LPEN_Pos = 0x1
	// Bit mask of TIM3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM3LPEN_Msk = 0x2
	// Bit TIM3LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM3LPEN = 0x2
	// Position of TIM4LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM4LPEN_Pos = 0x2
	// Bit mask of TIM4LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM4LPEN_Msk = 0x4
	// Bit TIM4LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM4LPEN = 0x4
	// Position of TIM5LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM5LPEN_Pos = 0x3
	// Bit mask of TIM5LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM5LPEN_Msk = 0x8
	// Bit TIM5LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM5LPEN = 0x8
	// Position of TIM6LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM6LPEN_Pos = 0x4
	// Bit mask of TIM6LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM6LPEN_Msk = 0x10
	// Bit TIM6LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM6LPEN = 0x10
	// Position of TIM7LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM7LPEN_Pos = 0x5
	// Bit mask of TIM7LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM7LPEN_Msk = 0x20
	// Bit TIM7LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM7LPEN = 0x20
	// Position of TIM12LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM12LPEN_Pos = 0x6
	// Bit mask of TIM12LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM12LPEN_Msk = 0x40
	// Bit TIM12LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM12LPEN = 0x40
	// Position of TIM13LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM13LPEN_Pos = 0x7
	// Bit mask of TIM13LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM13LPEN_Msk = 0x80
	// Bit TIM13LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM13LPEN = 0x80
	// Position of TIM14LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM14LPEN_Pos = 0x8
	// Bit mask of TIM14LPEN field.
	RCC_RCC_MC_APB1LPENSETR_TIM14LPEN_Msk = 0x100
	// Bit TIM14LPEN.
	RCC_RCC_MC_APB1LPENSETR_TIM14LPEN = 0x100
	// Position of LPTIM1LPEN field.
	RCC_RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos = 0x9
	// Bit mask of LPTIM1LPEN field.
	RCC_RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk = 0x200
	// Bit LPTIM1LPEN.
	RCC_RCC_MC_APB1LPENSETR_LPTIM1LPEN = 0x200
	// Position of SPI2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_SPI2LPEN_Pos = 0xb
	// Bit mask of SPI2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_SPI2LPEN_Msk = 0x800
	// Bit SPI2LPEN.
	RCC_RCC_MC_APB1LPENSETR_SPI2LPEN = 0x800
	// Position of SPI3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_SPI3LPEN_Pos = 0xc
	// Bit mask of SPI3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_SPI3LPEN_Msk = 0x1000
	// Bit SPI3LPEN.
	RCC_RCC_MC_APB1LPENSETR_SPI3LPEN = 0x1000
	// Position of USART2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_USART2LPEN_Pos = 0xe
	// Bit mask of USART2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_USART2LPEN_Msk = 0x4000
	// Bit USART2LPEN.
	RCC_RCC_MC_APB1LPENSETR_USART2LPEN = 0x4000
	// Position of USART3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_USART3LPEN_Pos = 0xf
	// Bit mask of USART3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_USART3LPEN_Msk = 0x8000
	// Bit USART3LPEN.
	RCC_RCC_MC_APB1LPENSETR_USART3LPEN = 0x8000
	// Position of UART4LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART4LPEN_Pos = 0x10
	// Bit mask of UART4LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART4LPEN_Msk = 0x10000
	// Bit UART4LPEN.
	RCC_RCC_MC_APB1LPENSETR_UART4LPEN = 0x10000
	// Position of UART5LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART5LPEN_Pos = 0x11
	// Bit mask of UART5LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART5LPEN_Msk = 0x20000
	// Bit UART5LPEN.
	RCC_RCC_MC_APB1LPENSETR_UART5LPEN = 0x20000
	// Position of UART7LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART7LPEN_Pos = 0x12
	// Bit mask of UART7LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART7LPEN_Msk = 0x40000
	// Bit UART7LPEN.
	RCC_RCC_MC_APB1LPENSETR_UART7LPEN = 0x40000
	// Position of UART8LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART8LPEN_Pos = 0x13
	// Bit mask of UART8LPEN field.
	RCC_RCC_MC_APB1LPENSETR_UART8LPEN_Msk = 0x80000
	// Bit UART8LPEN.
	RCC_RCC_MC_APB1LPENSETR_UART8LPEN = 0x80000
	// Position of I2C1LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C1LPEN_Pos = 0x15
	// Bit mask of I2C1LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C1LPEN_Msk = 0x200000
	// Bit I2C1LPEN.
	RCC_RCC_MC_APB1LPENSETR_I2C1LPEN = 0x200000
	// Position of I2C2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C2LPEN_Pos = 0x16
	// Bit mask of I2C2LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C2LPEN_Msk = 0x400000
	// Bit I2C2LPEN.
	RCC_RCC_MC_APB1LPENSETR_I2C2LPEN = 0x400000
	// Position of I2C3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C3LPEN_Pos = 0x17
	// Bit mask of I2C3LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C3LPEN_Msk = 0x800000
	// Bit I2C3LPEN.
	RCC_RCC_MC_APB1LPENSETR_I2C3LPEN = 0x800000
	// Position of I2C5LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C5LPEN_Pos = 0x18
	// Bit mask of I2C5LPEN field.
	RCC_RCC_MC_APB1LPENSETR_I2C5LPEN_Msk = 0x1000000
	// Bit I2C5LPEN.
	RCC_RCC_MC_APB1LPENSETR_I2C5LPEN = 0x1000000
	// Position of SPDIFLPEN field.
	RCC_RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos = 0x1a
	// Bit mask of SPDIFLPEN field.
	RCC_RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk = 0x4000000
	// Bit SPDIFLPEN.
	RCC_RCC_MC_APB1LPENSETR_SPDIFLPEN = 0x4000000
	// Position of CECLPEN field.
	RCC_RCC_MC_APB1LPENSETR_CECLPEN_Pos = 0x1b
	// Bit mask of CECLPEN field.
	RCC_RCC_MC_APB1LPENSETR_CECLPEN_Msk = 0x8000000
	// Bit CECLPEN.
	RCC_RCC_MC_APB1LPENSETR_CECLPEN = 0x8000000
	// Position of WWDG1LPEN field.
	RCC_RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos = 0x1c
	// Bit mask of WWDG1LPEN field.
	RCC_RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk = 0x10000000
	// Bit WWDG1LPEN.
	RCC_RCC_MC_APB1LPENSETR_WWDG1LPEN = 0x10000000
	// Position of DAC12LPEN field.
	RCC_RCC_MC_APB1LPENSETR_DAC12LPEN_Pos = 0x1d
	// Bit mask of DAC12LPEN field.
	RCC_RCC_MC_APB1LPENSETR_DAC12LPEN_Msk = 0x20000000
	// Bit DAC12LPEN.
	RCC_RCC_MC_APB1LPENSETR_DAC12LPEN = 0x20000000
	// Position of MDIOSLPEN field.
	RCC_RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos = 0x1f
	// Bit mask of MDIOSLPEN field.
	RCC_RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk = 0x80000000
	// Bit MDIOSLPEN.
	RCC_RCC_MC_APB1LPENSETR_MDIOSLPEN = 0x80000000

	// RCC_MC_APB1LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bits
	// Position of TIM2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos = 0x0
	// Bit mask of TIM2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk = 0x1
	// Bit TIM2LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM2LPEN = 0x1
	// Position of TIM3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos = 0x1
	// Bit mask of TIM3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk = 0x2
	// Bit TIM3LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM3LPEN = 0x2
	// Position of TIM4LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos = 0x2
	// Bit mask of TIM4LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk = 0x4
	// Bit TIM4LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM4LPEN = 0x4
	// Position of TIM5LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos = 0x3
	// Bit mask of TIM5LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk = 0x8
	// Bit TIM5LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM5LPEN = 0x8
	// Position of TIM6LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos = 0x4
	// Bit mask of TIM6LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk = 0x10
	// Bit TIM6LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM6LPEN = 0x10
	// Position of TIM7LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos = 0x5
	// Bit mask of TIM7LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk = 0x20
	// Bit TIM7LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM7LPEN = 0x20
	// Position of TIM12LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos = 0x6
	// Bit mask of TIM12LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk = 0x40
	// Bit TIM12LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM12LPEN = 0x40
	// Position of TIM13LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos = 0x7
	// Bit mask of TIM13LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk = 0x80
	// Bit TIM13LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM13LPEN = 0x80
	// Position of TIM14LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos = 0x8
	// Bit mask of TIM14LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk = 0x100
	// Bit TIM14LPEN.
	RCC_RCC_MC_APB1LPENCLRR_TIM14LPEN = 0x100
	// Position of LPTIM1LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos = 0x9
	// Bit mask of LPTIM1LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk = 0x200
	// Bit LPTIM1LPEN.
	RCC_RCC_MC_APB1LPENCLRR_LPTIM1LPEN = 0x200
	// Position of SPI2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos = 0xb
	// Bit mask of SPI2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk = 0x800
	// Bit SPI2LPEN.
	RCC_RCC_MC_APB1LPENCLRR_SPI2LPEN = 0x800
	// Position of SPI3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos = 0xc
	// Bit mask of SPI3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk = 0x1000
	// Bit SPI3LPEN.
	RCC_RCC_MC_APB1LPENCLRR_SPI3LPEN = 0x1000
	// Position of USART2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_USART2LPEN_Pos = 0xe
	// Bit mask of USART2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_USART2LPEN_Msk = 0x4000
	// Bit USART2LPEN.
	RCC_RCC_MC_APB1LPENCLRR_USART2LPEN = 0x4000
	// Position of USART3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_USART3LPEN_Pos = 0xf
	// Bit mask of USART3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_USART3LPEN_Msk = 0x8000
	// Bit USART3LPEN.
	RCC_RCC_MC_APB1LPENCLRR_USART3LPEN = 0x8000
	// Position of UART4LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART4LPEN_Pos = 0x10
	// Bit mask of UART4LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART4LPEN_Msk = 0x10000
	// Bit UART4LPEN.
	RCC_RCC_MC_APB1LPENCLRR_UART4LPEN = 0x10000
	// Position of UART5LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART5LPEN_Pos = 0x11
	// Bit mask of UART5LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART5LPEN_Msk = 0x20000
	// Bit UART5LPEN.
	RCC_RCC_MC_APB1LPENCLRR_UART5LPEN = 0x20000
	// Position of UART7LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART7LPEN_Pos = 0x12
	// Bit mask of UART7LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART7LPEN_Msk = 0x40000
	// Bit UART7LPEN.
	RCC_RCC_MC_APB1LPENCLRR_UART7LPEN = 0x40000
	// Position of UART8LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART8LPEN_Pos = 0x13
	// Bit mask of UART8LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_UART8LPEN_Msk = 0x80000
	// Bit UART8LPEN.
	RCC_RCC_MC_APB1LPENCLRR_UART8LPEN = 0x80000
	// Position of I2C1LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos = 0x15
	// Bit mask of I2C1LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk = 0x200000
	// Bit I2C1LPEN.
	RCC_RCC_MC_APB1LPENCLRR_I2C1LPEN = 0x200000
	// Position of I2C2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos = 0x16
	// Bit mask of I2C2LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk = 0x400000
	// Bit I2C2LPEN.
	RCC_RCC_MC_APB1LPENCLRR_I2C2LPEN = 0x400000
	// Position of I2C3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos = 0x17
	// Bit mask of I2C3LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk = 0x800000
	// Bit I2C3LPEN.
	RCC_RCC_MC_APB1LPENCLRR_I2C3LPEN = 0x800000
	// Position of I2C5LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos = 0x18
	// Bit mask of I2C5LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk = 0x1000000
	// Bit I2C5LPEN.
	RCC_RCC_MC_APB1LPENCLRR_I2C5LPEN = 0x1000000
	// Position of SPDIFLPEN field.
	RCC_RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos = 0x1a
	// Bit mask of SPDIFLPEN field.
	RCC_RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk = 0x4000000
	// Bit SPDIFLPEN.
	RCC_RCC_MC_APB1LPENCLRR_SPDIFLPEN = 0x4000000
	// Position of CECLPEN field.
	RCC_RCC_MC_APB1LPENCLRR_CECLPEN_Pos = 0x1b
	// Bit mask of CECLPEN field.
	RCC_RCC_MC_APB1LPENCLRR_CECLPEN_Msk = 0x8000000
	// Bit CECLPEN.
	RCC_RCC_MC_APB1LPENCLRR_CECLPEN = 0x8000000
	// Position of WWDG1LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos = 0x1c
	// Bit mask of WWDG1LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk = 0x10000000
	// Bit WWDG1LPEN.
	RCC_RCC_MC_APB1LPENCLRR_WWDG1LPEN = 0x10000000
	// Position of DAC12LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos = 0x1d
	// Bit mask of DAC12LPEN field.
	RCC_RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk = 0x20000000
	// Bit DAC12LPEN.
	RCC_RCC_MC_APB1LPENCLRR_DAC12LPEN = 0x20000000
	// Position of MDIOSLPEN field.
	RCC_RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos = 0x1f
	// Bit mask of MDIOSLPEN field.
	RCC_RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk = 0x80000000
	// Bit MDIOSLPEN.
	RCC_RCC_MC_APB1LPENCLRR_MDIOSLPEN = 0x80000000

	// RCC_MC_APB2LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of TIM1LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM1LPEN_Pos = 0x0
	// Bit mask of TIM1LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM1LPEN_Msk = 0x1
	// Bit TIM1LPEN.
	RCC_RCC_MC_APB2LPENSETR_TIM1LPEN = 0x1
	// Position of TIM8LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM8LPEN_Pos = 0x1
	// Bit mask of TIM8LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM8LPEN_Msk = 0x2
	// Bit TIM8LPEN.
	RCC_RCC_MC_APB2LPENSETR_TIM8LPEN = 0x2
	// Position of TIM15LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM15LPEN_Pos = 0x2
	// Bit mask of TIM15LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM15LPEN_Msk = 0x4
	// Bit TIM15LPEN.
	RCC_RCC_MC_APB2LPENSETR_TIM15LPEN = 0x4
	// Position of TIM16LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM16LPEN_Pos = 0x3
	// Bit mask of TIM16LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM16LPEN_Msk = 0x8
	// Bit TIM16LPEN.
	RCC_RCC_MC_APB2LPENSETR_TIM16LPEN = 0x8
	// Position of TIM17LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM17LPEN_Pos = 0x4
	// Bit mask of TIM17LPEN field.
	RCC_RCC_MC_APB2LPENSETR_TIM17LPEN_Msk = 0x10
	// Bit TIM17LPEN.
	RCC_RCC_MC_APB2LPENSETR_TIM17LPEN = 0x10
	// Position of SPI1LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SPI1LPEN_Pos = 0x8
	// Bit mask of SPI1LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SPI1LPEN_Msk = 0x100
	// Bit SPI1LPEN.
	RCC_RCC_MC_APB2LPENSETR_SPI1LPEN = 0x100
	// Position of SPI4LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SPI4LPEN_Pos = 0x9
	// Bit mask of SPI4LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SPI4LPEN_Msk = 0x200
	// Bit SPI4LPEN.
	RCC_RCC_MC_APB2LPENSETR_SPI4LPEN = 0x200
	// Position of SPI5LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SPI5LPEN_Pos = 0xa
	// Bit mask of SPI5LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SPI5LPEN_Msk = 0x400
	// Bit SPI5LPEN.
	RCC_RCC_MC_APB2LPENSETR_SPI5LPEN = 0x400
	// Position of USART6LPEN field.
	RCC_RCC_MC_APB2LPENSETR_USART6LPEN_Pos = 0xd
	// Bit mask of USART6LPEN field.
	RCC_RCC_MC_APB2LPENSETR_USART6LPEN_Msk = 0x2000
	// Bit USART6LPEN.
	RCC_RCC_MC_APB2LPENSETR_USART6LPEN = 0x2000
	// Position of SAI1LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SAI1LPEN_Pos = 0x10
	// Bit mask of SAI1LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SAI1LPEN_Msk = 0x10000
	// Bit SAI1LPEN.
	RCC_RCC_MC_APB2LPENSETR_SAI1LPEN = 0x10000
	// Position of SAI2LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SAI2LPEN_Pos = 0x11
	// Bit mask of SAI2LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SAI2LPEN_Msk = 0x20000
	// Bit SAI2LPEN.
	RCC_RCC_MC_APB2LPENSETR_SAI2LPEN = 0x20000
	// Position of SAI3LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SAI3LPEN_Pos = 0x12
	// Bit mask of SAI3LPEN field.
	RCC_RCC_MC_APB2LPENSETR_SAI3LPEN_Msk = 0x40000
	// Bit SAI3LPEN.
	RCC_RCC_MC_APB2LPENSETR_SAI3LPEN = 0x40000
	// Position of DFSDMLPEN field.
	RCC_RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos = 0x14
	// Bit mask of DFSDMLPEN field.
	RCC_RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk = 0x100000
	// Bit DFSDMLPEN.
	RCC_RCC_MC_APB2LPENSETR_DFSDMLPEN = 0x100000
	// Position of ADFSDMLPEN field.
	RCC_RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos = 0x15
	// Bit mask of ADFSDMLPEN field.
	RCC_RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk = 0x200000
	// Bit ADFSDMLPEN.
	RCC_RCC_MC_APB2LPENSETR_ADFSDMLPEN = 0x200000
	// Position of FDCANLPEN field.
	RCC_RCC_MC_APB2LPENSETR_FDCANLPEN_Pos = 0x18
	// Bit mask of FDCANLPEN field.
	RCC_RCC_MC_APB2LPENSETR_FDCANLPEN_Msk = 0x1000000
	// Bit FDCANLPEN.
	RCC_RCC_MC_APB2LPENSETR_FDCANLPEN = 0x1000000

	// RCC_MC_APB2LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit
	// Position of TIM1LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos = 0x0
	// Bit mask of TIM1LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk = 0x1
	// Bit TIM1LPEN.
	RCC_RCC_MC_APB2LPENCLRR_TIM1LPEN = 0x1
	// Position of TIM8LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos = 0x1
	// Bit mask of TIM8LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk = 0x2
	// Bit TIM8LPEN.
	RCC_RCC_MC_APB2LPENCLRR_TIM8LPEN = 0x2
	// Position of TIM15LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos = 0x2
	// Bit mask of TIM15LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk = 0x4
	// Bit TIM15LPEN.
	RCC_RCC_MC_APB2LPENCLRR_TIM15LPEN = 0x4
	// Position of TIM16LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos = 0x3
	// Bit mask of TIM16LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk = 0x8
	// Bit TIM16LPEN.
	RCC_RCC_MC_APB2LPENCLRR_TIM16LPEN = 0x8
	// Position of TIM17LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos = 0x4
	// Bit mask of TIM17LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk = 0x10
	// Bit TIM17LPEN.
	RCC_RCC_MC_APB2LPENCLRR_TIM17LPEN = 0x10
	// Position of SPI1LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos = 0x8
	// Bit mask of SPI1LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk = 0x100
	// Bit SPI1LPEN.
	RCC_RCC_MC_APB2LPENCLRR_SPI1LPEN = 0x100
	// Position of SPI4LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos = 0x9
	// Bit mask of SPI4LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk = 0x200
	// Bit SPI4LPEN.
	RCC_RCC_MC_APB2LPENCLRR_SPI4LPEN = 0x200
	// Position of SPI5LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos = 0xa
	// Bit mask of SPI5LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk = 0x400
	// Bit SPI5LPEN.
	RCC_RCC_MC_APB2LPENCLRR_SPI5LPEN = 0x400
	// Position of USART6LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_USART6LPEN_Pos = 0xd
	// Bit mask of USART6LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_USART6LPEN_Msk = 0x2000
	// Bit USART6LPEN.
	RCC_RCC_MC_APB2LPENCLRR_USART6LPEN = 0x2000
	// Position of SAI1LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos = 0x10
	// Bit mask of SAI1LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk = 0x10000
	// Bit SAI1LPEN.
	RCC_RCC_MC_APB2LPENCLRR_SAI1LPEN = 0x10000
	// Position of SAI2LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos = 0x11
	// Bit mask of SAI2LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk = 0x20000
	// Bit SAI2LPEN.
	RCC_RCC_MC_APB2LPENCLRR_SAI2LPEN = 0x20000
	// Position of SAI3LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos = 0x12
	// Bit mask of SAI3LPEN field.
	RCC_RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk = 0x40000
	// Bit SAI3LPEN.
	RCC_RCC_MC_APB2LPENCLRR_SAI3LPEN = 0x40000
	// Position of DFSDMLPEN field.
	RCC_RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos = 0x14
	// Bit mask of DFSDMLPEN field.
	RCC_RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk = 0x100000
	// Bit DFSDMLPEN.
	RCC_RCC_MC_APB2LPENCLRR_DFSDMLPEN = 0x100000
	// Position of ADFSDMLPEN field.
	RCC_RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos = 0x15
	// Bit mask of ADFSDMLPEN field.
	RCC_RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk = 0x200000
	// Bit ADFSDMLPEN.
	RCC_RCC_MC_APB2LPENCLRR_ADFSDMLPEN = 0x200000
	// Position of FDCANLPEN field.
	RCC_RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos = 0x18
	// Bit mask of FDCANLPEN field.
	RCC_RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk = 0x1000000
	// Bit FDCANLPEN.
	RCC_RCC_MC_APB2LPENCLRR_FDCANLPEN = 0x1000000

	// RCC_MC_APB3LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of LPTIM2LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos = 0x0
	// Bit mask of LPTIM2LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk = 0x1
	// Bit LPTIM2LPEN.
	RCC_RCC_MC_APB3LPENSETR_LPTIM2LPEN = 0x1
	// Position of LPTIM3LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos = 0x1
	// Bit mask of LPTIM3LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk = 0x2
	// Bit LPTIM3LPEN.
	RCC_RCC_MC_APB3LPENSETR_LPTIM3LPEN = 0x2
	// Position of LPTIM4LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos = 0x2
	// Bit mask of LPTIM4LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk = 0x4
	// Bit LPTIM4LPEN.
	RCC_RCC_MC_APB3LPENSETR_LPTIM4LPEN = 0x4
	// Position of LPTIM5LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos = 0x3
	// Bit mask of LPTIM5LPEN field.
	RCC_RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk = 0x8
	// Bit LPTIM5LPEN.
	RCC_RCC_MC_APB3LPENSETR_LPTIM5LPEN = 0x8
	// Position of SAI4LPEN field.
	RCC_RCC_MC_APB3LPENSETR_SAI4LPEN_Pos = 0x8
	// Bit mask of SAI4LPEN field.
	RCC_RCC_MC_APB3LPENSETR_SAI4LPEN_Msk = 0x100
	// Bit SAI4LPEN.
	RCC_RCC_MC_APB3LPENSETR_SAI4LPEN = 0x100
	// Position of SYSCFGLPEN field.
	RCC_RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos = 0xb
	// Bit mask of SYSCFGLPEN field.
	RCC_RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk = 0x800
	// Bit SYSCFGLPEN.
	RCC_RCC_MC_APB3LPENSETR_SYSCFGLPEN = 0x800
	// Position of VREFLPEN field.
	RCC_RCC_MC_APB3LPENSETR_VREFLPEN_Pos = 0xd
	// Bit mask of VREFLPEN field.
	RCC_RCC_MC_APB3LPENSETR_VREFLPEN_Msk = 0x2000
	// Bit VREFLPEN.
	RCC_RCC_MC_APB3LPENSETR_VREFLPEN = 0x2000
	// Position of DTSLPEN field.
	RCC_RCC_MC_APB3LPENSETR_DTSLPEN_Pos = 0x10
	// Bit mask of DTSLPEN field.
	RCC_RCC_MC_APB3LPENSETR_DTSLPEN_Msk = 0x10000
	// Bit DTSLPEN.
	RCC_RCC_MC_APB3LPENSETR_DTSLPEN = 0x10000

	// RCC_MC_APB3LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit
	// Position of LPTIM2LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos = 0x0
	// Bit mask of LPTIM2LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk = 0x1
	// Bit LPTIM2LPEN.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM2LPEN = 0x1
	// Position of LPTIM3LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos = 0x1
	// Bit mask of LPTIM3LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk = 0x2
	// Bit LPTIM3LPEN.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM3LPEN = 0x2
	// Position of LPTIM4LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos = 0x2
	// Bit mask of LPTIM4LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk = 0x4
	// Bit LPTIM4LPEN.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM4LPEN = 0x4
	// Position of LPTIM5LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos = 0x3
	// Bit mask of LPTIM5LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk = 0x8
	// Bit LPTIM5LPEN.
	RCC_RCC_MC_APB3LPENCLRR_LPTIM5LPEN = 0x8
	// Position of SAI4LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos = 0x8
	// Bit mask of SAI4LPEN field.
	RCC_RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk = 0x100
	// Bit SAI4LPEN.
	RCC_RCC_MC_APB3LPENCLRR_SAI4LPEN = 0x100
	// Position of SYSCFGLPEN field.
	RCC_RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos = 0xb
	// Bit mask of SYSCFGLPEN field.
	RCC_RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk = 0x800
	// Bit SYSCFGLPEN.
	RCC_RCC_MC_APB3LPENCLRR_SYSCFGLPEN = 0x800
	// Position of VREFLPEN field.
	RCC_RCC_MC_APB3LPENCLRR_VREFLPEN_Pos = 0xd
	// Bit mask of VREFLPEN field.
	RCC_RCC_MC_APB3LPENCLRR_VREFLPEN_Msk = 0x2000
	// Bit VREFLPEN.
	RCC_RCC_MC_APB3LPENCLRR_VREFLPEN = 0x2000
	// Position of DTSLPEN field.
	RCC_RCC_MC_APB3LPENCLRR_DTSLPEN_Pos = 0x10
	// Bit mask of DTSLPEN field.
	RCC_RCC_MC_APB3LPENCLRR_DTSLPEN_Msk = 0x10000
	// Bit DTSLPEN.
	RCC_RCC_MC_APB3LPENCLRR_DTSLPEN = 0x10000

	// RCC_MC_AHB2LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of DMA1LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos = 0x0
	// Bit mask of DMA1LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk = 0x1
	// Bit DMA1LPEN.
	RCC_RCC_MC_AHB2LPENSETR_DMA1LPEN = 0x1
	// Position of DMA2LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos = 0x1
	// Bit mask of DMA2LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk = 0x2
	// Bit DMA2LPEN.
	RCC_RCC_MC_AHB2LPENSETR_DMA2LPEN = 0x2
	// Position of DMAMUXLPEN field.
	RCC_RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos = 0x2
	// Bit mask of DMAMUXLPEN field.
	RCC_RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk = 0x4
	// Bit DMAMUXLPEN.
	RCC_RCC_MC_AHB2LPENSETR_DMAMUXLPEN = 0x4
	// Position of ADC12LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos = 0x5
	// Bit mask of ADC12LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk = 0x20
	// Bit ADC12LPEN.
	RCC_RCC_MC_AHB2LPENSETR_ADC12LPEN = 0x20
	// Position of USBOLPEN field.
	RCC_RCC_MC_AHB2LPENSETR_USBOLPEN_Pos = 0x8
	// Bit mask of USBOLPEN field.
	RCC_RCC_MC_AHB2LPENSETR_USBOLPEN_Msk = 0x100
	// Bit USBOLPEN.
	RCC_RCC_MC_AHB2LPENSETR_USBOLPEN = 0x100
	// Position of SDMMC3LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos = 0x10
	// Bit mask of SDMMC3LPEN field.
	RCC_RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk = 0x10000
	// Bit SDMMC3LPEN.
	RCC_RCC_MC_AHB2LPENSETR_SDMMC3LPEN = 0x10000

	// RCC_MC_AHB2LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit
	// Position of DMA1LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos = 0x0
	// Bit mask of DMA1LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk = 0x1
	// Bit DMA1LPEN.
	RCC_RCC_MC_AHB2LPENCLRR_DMA1LPEN = 0x1
	// Position of DMA2LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos = 0x1
	// Bit mask of DMA2LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk = 0x2
	// Bit DMA2LPEN.
	RCC_RCC_MC_AHB2LPENCLRR_DMA2LPEN = 0x2
	// Position of DMAMUXLPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos = 0x2
	// Bit mask of DMAMUXLPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk = 0x4
	// Bit DMAMUXLPEN.
	RCC_RCC_MC_AHB2LPENCLRR_DMAMUXLPEN = 0x4
	// Position of ADC12LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos = 0x5
	// Bit mask of ADC12LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk = 0x20
	// Bit ADC12LPEN.
	RCC_RCC_MC_AHB2LPENCLRR_ADC12LPEN = 0x20
	// Position of USBOLPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos = 0x8
	// Bit mask of USBOLPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk = 0x100
	// Bit USBOLPEN.
	RCC_RCC_MC_AHB2LPENCLRR_USBOLPEN = 0x100
	// Position of SDMMC3LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos = 0x10
	// Bit mask of SDMMC3LPEN field.
	RCC_RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk = 0x10000
	// Bit SDMMC3LPEN.
	RCC_RCC_MC_AHB2LPENCLRR_SDMMC3LPEN = 0x10000

	// RCC_MC_AHB3LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of DCMILPEN field.
	RCC_RCC_MC_AHB3LPENSETR_DCMILPEN_Pos = 0x0
	// Bit mask of DCMILPEN field.
	RCC_RCC_MC_AHB3LPENSETR_DCMILPEN_Msk = 0x1
	// Bit DCMILPEN.
	RCC_RCC_MC_AHB3LPENSETR_DCMILPEN = 0x1
	// Position of CRYP2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos = 0x4
	// Bit mask of CRYP2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk = 0x10
	// Bit CRYP2LPEN.
	RCC_RCC_MC_AHB3LPENSETR_CRYP2LPEN = 0x10
	// Position of HASH2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos = 0x5
	// Bit mask of HASH2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk = 0x20
	// Bit HASH2LPEN.
	RCC_RCC_MC_AHB3LPENSETR_HASH2LPEN = 0x20
	// Position of RNG2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos = 0x6
	// Bit mask of RNG2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk = 0x40
	// Bit RNG2LPEN.
	RCC_RCC_MC_AHB3LPENSETR_RNG2LPEN = 0x40
	// Position of CRC2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos = 0x7
	// Bit mask of CRC2LPEN field.
	RCC_RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk = 0x80
	// Bit CRC2LPEN.
	RCC_RCC_MC_AHB3LPENSETR_CRC2LPEN = 0x80
	// Position of HSEMLPEN field.
	RCC_RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos = 0xb
	// Bit mask of HSEMLPEN field.
	RCC_RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk = 0x800
	// Bit HSEMLPEN.
	RCC_RCC_MC_AHB3LPENSETR_HSEMLPEN = 0x800
	// Position of IPCCLPEN field.
	RCC_RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos = 0xc
	// Bit mask of IPCCLPEN field.
	RCC_RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk = 0x1000
	// Bit IPCCLPEN.
	RCC_RCC_MC_AHB3LPENSETR_IPCCLPEN = 0x1000

	// RCC_MC_AHB3LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit
	// Position of DCMILPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos = 0x0
	// Bit mask of DCMILPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk = 0x1
	// Bit DCMILPEN.
	RCC_RCC_MC_AHB3LPENCLRR_DCMILPEN = 0x1
	// Position of CRYP2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos = 0x4
	// Bit mask of CRYP2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk = 0x10
	// Bit CRYP2LPEN.
	RCC_RCC_MC_AHB3LPENCLRR_CRYP2LPEN = 0x10
	// Position of HASH2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos = 0x5
	// Bit mask of HASH2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk = 0x20
	// Bit HASH2LPEN.
	RCC_RCC_MC_AHB3LPENCLRR_HASH2LPEN = 0x20
	// Position of RNG2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos = 0x6
	// Bit mask of RNG2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk = 0x40
	// Bit RNG2LPEN.
	RCC_RCC_MC_AHB3LPENCLRR_RNG2LPEN = 0x40
	// Position of CRC2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos = 0x7
	// Bit mask of CRC2LPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk = 0x80
	// Bit CRC2LPEN.
	RCC_RCC_MC_AHB3LPENCLRR_CRC2LPEN = 0x80
	// Position of HSEMLPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos = 0xb
	// Bit mask of HSEMLPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk = 0x800
	// Bit HSEMLPEN.
	RCC_RCC_MC_AHB3LPENCLRR_HSEMLPEN = 0x800
	// Position of IPCCLPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos = 0xc
	// Bit mask of IPCCLPEN field.
	RCC_RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk = 0x1000
	// Bit IPCCLPEN.
	RCC_RCC_MC_AHB3LPENCLRR_IPCCLPEN = 0x1000

	// RCC_MC_AHB4LPENSETR: This register is used by the MCU in order to set the PERxLPEN bit.
	// Position of GPIOALPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos = 0x0
	// Bit mask of GPIOALPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk = 0x1
	// Bit GPIOALPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOALPEN = 0x1
	// Position of GPIOBLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos = 0x1
	// Bit mask of GPIOBLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk = 0x2
	// Bit GPIOBLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOBLPEN = 0x2
	// Position of GPIOCLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos = 0x2
	// Bit mask of GPIOCLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk = 0x4
	// Bit GPIOCLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOCLPEN = 0x4
	// Position of GPIODLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos = 0x3
	// Bit mask of GPIODLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk = 0x8
	// Bit GPIODLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIODLPEN = 0x8
	// Position of GPIOELPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos = 0x4
	// Bit mask of GPIOELPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk = 0x10
	// Bit GPIOELPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOELPEN = 0x10
	// Position of GPIOFLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos = 0x5
	// Bit mask of GPIOFLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk = 0x20
	// Bit GPIOFLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOFLPEN = 0x20
	// Position of GPIOGLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos = 0x6
	// Bit mask of GPIOGLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk = 0x40
	// Bit GPIOGLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOGLPEN = 0x40
	// Position of GPIOHLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos = 0x7
	// Bit mask of GPIOHLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk = 0x80
	// Bit GPIOHLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOHLPEN = 0x80
	// Position of GPIOILPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos = 0x8
	// Bit mask of GPIOILPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk = 0x100
	// Bit GPIOILPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOILPEN = 0x100
	// Position of GPIOJLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos = 0x9
	// Bit mask of GPIOJLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk = 0x200
	// Bit GPIOJLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOJLPEN = 0x200
	// Position of GPIOKLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos = 0xa
	// Bit mask of GPIOKLPEN field.
	RCC_RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk = 0x400
	// Bit GPIOKLPEN.
	RCC_RCC_MC_AHB4LPENSETR_GPIOKLPEN = 0x400

	// RCC_MC_AHB4LPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
	// Position of GPIOALPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos = 0x0
	// Bit mask of GPIOALPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk = 0x1
	// Bit GPIOALPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOALPEN = 0x1
	// Position of GPIOBLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos = 0x1
	// Bit mask of GPIOBLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk = 0x2
	// Bit GPIOBLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOBLPEN = 0x2
	// Position of GPIOCLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos = 0x2
	// Bit mask of GPIOCLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk = 0x4
	// Bit GPIOCLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOCLPEN = 0x4
	// Position of GPIODLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos = 0x3
	// Bit mask of GPIODLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk = 0x8
	// Bit GPIODLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIODLPEN = 0x8
	// Position of GPIOELPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos = 0x4
	// Bit mask of GPIOELPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk = 0x10
	// Bit GPIOELPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOELPEN = 0x10
	// Position of GPIOFLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos = 0x5
	// Bit mask of GPIOFLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk = 0x20
	// Bit GPIOFLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOFLPEN = 0x20
	// Position of GPIOGLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos = 0x6
	// Bit mask of GPIOGLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk = 0x40
	// Bit GPIOGLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOGLPEN = 0x40
	// Position of GPIOHLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos = 0x7
	// Bit mask of GPIOHLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk = 0x80
	// Bit GPIOHLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOHLPEN = 0x80
	// Position of GPIOILPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos = 0x8
	// Bit mask of GPIOILPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk = 0x100
	// Bit GPIOILPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOILPEN = 0x100
	// Position of GPIOJLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos = 0x9
	// Bit mask of GPIOJLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk = 0x200
	// Bit GPIOJLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOJLPEN = 0x200
	// Position of GPIOKLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos = 0xa
	// Bit mask of GPIOKLPEN field.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk = 0x400
	// Bit GPIOKLPEN.
	RCC_RCC_MC_AHB4LPENCLRR_GPIOKLPEN = 0x400

	// RCC_MC_AXIMLPENSETR: This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
	// Position of SYSRAMLPEN field.
	RCC_RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos = 0x0
	// Bit mask of SYSRAMLPEN field.
	RCC_RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk = 0x1
	// Bit SYSRAMLPEN.
	RCC_RCC_MC_AXIMLPENSETR_SYSRAMLPEN = 0x1

	// RCC_MC_AXIMLPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
	// Position of SYSRAMLPEN field.
	RCC_RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos = 0x0
	// Bit mask of SYSRAMLPEN field.
	RCC_RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk = 0x1
	// Bit SYSRAMLPEN.
	RCC_RCC_MC_AXIMLPENCLRR_SYSRAMLPEN = 0x1

	// RCC_MC_MLAHBLPENSETR: This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
	// Position of SRAM1LPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos = 0x0
	// Bit mask of SRAM1LPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk = 0x1
	// Bit SRAM1LPEN.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM1LPEN = 0x1
	// Position of SRAM2LPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos = 0x1
	// Bit mask of SRAM2LPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk = 0x2
	// Bit SRAM2LPEN.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM2LPEN = 0x2
	// Position of SRAM34LPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos = 0x2
	// Bit mask of SRAM34LPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk = 0x4
	// Bit SRAM34LPEN.
	RCC_RCC_MC_MLAHBLPENSETR_SRAM34LPEN = 0x4
	// Position of RETRAMLPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos = 0x4
	// Bit mask of RETRAMLPEN field.
	RCC_RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk = 0x10
	// Bit RETRAMLPEN.
	RCC_RCC_MC_MLAHBLPENSETR_RETRAMLPEN = 0x10

	// RCC_MC_MLAHBLPENCLRR: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
	// Position of SRAM1LPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos = 0x0
	// Bit mask of SRAM1LPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk = 0x1
	// Bit SRAM1LPEN.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM1LPEN = 0x1
	// Position of SRAM2LPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos = 0x1
	// Bit mask of SRAM2LPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk = 0x2
	// Bit SRAM2LPEN.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM2LPEN = 0x2
	// Position of SRAM34LPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos = 0x2
	// Bit mask of SRAM34LPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk = 0x4
	// Bit SRAM34LPEN.
	RCC_RCC_MC_MLAHBLPENCLRR_SRAM34LPEN = 0x4
	// Position of RETRAMLPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos = 0x4
	// Bit mask of RETRAMLPEN field.
	RCC_RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk = 0x10
	// Bit RETRAMLPEN.
	RCC_RCC_MC_MLAHBLPENCLRR_RETRAMLPEN = 0x10

	// RCC_MC_RSTSCLRR: This register is used by the MCU to check the reset source.
	// Position of PORRSTF field.
	RCC_RCC_MC_RSTSCLRR_PORRSTF_Pos = 0x0
	// Bit mask of PORRSTF field.
	RCC_RCC_MC_RSTSCLRR_PORRSTF_Msk = 0x1
	// Bit PORRSTF.
	RCC_RCC_MC_RSTSCLRR_PORRSTF = 0x1
	// Position of BORRSTF field.
	RCC_RCC_MC_RSTSCLRR_BORRSTF_Pos = 0x1
	// Bit mask of BORRSTF field.
	RCC_RCC_MC_RSTSCLRR_BORRSTF_Msk = 0x2
	// Bit BORRSTF.
	RCC_RCC_MC_RSTSCLRR_BORRSTF = 0x2
	// Position of PADRSTF field.
	RCC_RCC_MC_RSTSCLRR_PADRSTF_Pos = 0x2
	// Bit mask of PADRSTF field.
	RCC_RCC_MC_RSTSCLRR_PADRSTF_Msk = 0x4
	// Bit PADRSTF.
	RCC_RCC_MC_RSTSCLRR_PADRSTF = 0x4
	// Position of HCSSRSTF field.
	RCC_RCC_MC_RSTSCLRR_HCSSRSTF_Pos = 0x3
	// Bit mask of HCSSRSTF field.
	RCC_RCC_MC_RSTSCLRR_HCSSRSTF_Msk = 0x8
	// Bit HCSSRSTF.
	RCC_RCC_MC_RSTSCLRR_HCSSRSTF = 0x8
	// Position of VCORERSTF field.
	RCC_RCC_MC_RSTSCLRR_VCORERSTF_Pos = 0x4
	// Bit mask of VCORERSTF field.
	RCC_RCC_MC_RSTSCLRR_VCORERSTF_Msk = 0x10
	// Bit VCORERSTF.
	RCC_RCC_MC_RSTSCLRR_VCORERSTF = 0x10
	// Position of MCURSTF field.
	RCC_RCC_MC_RSTSCLRR_MCURSTF_Pos = 0x5
	// Bit mask of MCURSTF field.
	RCC_RCC_MC_RSTSCLRR_MCURSTF_Msk = 0x20
	// Bit MCURSTF.
	RCC_RCC_MC_RSTSCLRR_MCURSTF = 0x20
	// Position of MPSYSRSTF field.
	RCC_RCC_MC_RSTSCLRR_MPSYSRSTF_Pos = 0x6
	// Bit mask of MPSYSRSTF field.
	RCC_RCC_MC_RSTSCLRR_MPSYSRSTF_Msk = 0x40
	// Bit MPSYSRSTF.
	RCC_RCC_MC_RSTSCLRR_MPSYSRSTF = 0x40
	// Position of MCSYSRSTF field.
	RCC_RCC_MC_RSTSCLRR_MCSYSRSTF_Pos = 0x7
	// Bit mask of MCSYSRSTF field.
	RCC_RCC_MC_RSTSCLRR_MCSYSRSTF_Msk = 0x80
	// Bit MCSYSRSTF.
	RCC_RCC_MC_RSTSCLRR_MCSYSRSTF = 0x80
	// Position of IWDG1RSTF field.
	RCC_RCC_MC_RSTSCLRR_IWDG1RSTF_Pos = 0x8
	// Bit mask of IWDG1RSTF field.
	RCC_RCC_MC_RSTSCLRR_IWDG1RSTF_Msk = 0x100
	// Bit IWDG1RSTF.
	RCC_RCC_MC_RSTSCLRR_IWDG1RSTF = 0x100
	// Position of IWDG2RSTF field.
	RCC_RCC_MC_RSTSCLRR_IWDG2RSTF_Pos = 0x9
	// Bit mask of IWDG2RSTF field.
	RCC_RCC_MC_RSTSCLRR_IWDG2RSTF_Msk = 0x200
	// Bit IWDG2RSTF.
	RCC_RCC_MC_RSTSCLRR_IWDG2RSTF = 0x200
	// Position of WWDG1RSTF field.
	RCC_RCC_MC_RSTSCLRR_WWDG1RSTF_Pos = 0xa
	// Bit mask of WWDG1RSTF field.
	RCC_RCC_MC_RSTSCLRR_WWDG1RSTF_Msk = 0x400
	// Bit WWDG1RSTF.
	RCC_RCC_MC_RSTSCLRR_WWDG1RSTF = 0x400

	// RCC_MC_CIER: This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details.
	// Position of LSIRDYIE field.
	RCC_RCC_MC_CIER_LSIRDYIE_Pos = 0x0
	// Bit mask of LSIRDYIE field.
	RCC_RCC_MC_CIER_LSIRDYIE_Msk = 0x1
	// Bit LSIRDYIE.
	RCC_RCC_MC_CIER_LSIRDYIE = 0x1
	// Position of LSERDYIE field.
	RCC_RCC_MC_CIER_LSERDYIE_Pos = 0x1
	// Bit mask of LSERDYIE field.
	RCC_RCC_MC_CIER_LSERDYIE_Msk = 0x2
	// Bit LSERDYIE.
	RCC_RCC_MC_CIER_LSERDYIE = 0x2
	// Position of HSIRDYIE field.
	RCC_RCC_MC_CIER_HSIRDYIE_Pos = 0x2
	// Bit mask of HSIRDYIE field.
	RCC_RCC_MC_CIER_HSIRDYIE_Msk = 0x4
	// Bit HSIRDYIE.
	RCC_RCC_MC_CIER_HSIRDYIE = 0x4
	// Position of HSERDYIE field.
	RCC_RCC_MC_CIER_HSERDYIE_Pos = 0x3
	// Bit mask of HSERDYIE field.
	RCC_RCC_MC_CIER_HSERDYIE_Msk = 0x8
	// Bit HSERDYIE.
	RCC_RCC_MC_CIER_HSERDYIE = 0x8
	// Position of CSIRDYIE field.
	RCC_RCC_MC_CIER_CSIRDYIE_Pos = 0x4
	// Bit mask of CSIRDYIE field.
	RCC_RCC_MC_CIER_CSIRDYIE_Msk = 0x10
	// Bit CSIRDYIE.
	RCC_RCC_MC_CIER_CSIRDYIE = 0x10
	// Position of PLL1DYIE field.
	RCC_RCC_MC_CIER_PLL1DYIE_Pos = 0x8
	// Bit mask of PLL1DYIE field.
	RCC_RCC_MC_CIER_PLL1DYIE_Msk = 0x100
	// Bit PLL1DYIE.
	RCC_RCC_MC_CIER_PLL1DYIE = 0x100
	// Position of PLL2DYIE field.
	RCC_RCC_MC_CIER_PLL2DYIE_Pos = 0x9
	// Bit mask of PLL2DYIE field.
	RCC_RCC_MC_CIER_PLL2DYIE_Msk = 0x200
	// Bit PLL2DYIE.
	RCC_RCC_MC_CIER_PLL2DYIE = 0x200
	// Position of PLL3DYIE field.
	RCC_RCC_MC_CIER_PLL3DYIE_Pos = 0xa
	// Bit mask of PLL3DYIE field.
	RCC_RCC_MC_CIER_PLL3DYIE_Msk = 0x400
	// Bit PLL3DYIE.
	RCC_RCC_MC_CIER_PLL3DYIE = 0x400
	// Position of PLL4DYIE field.
	RCC_RCC_MC_CIER_PLL4DYIE_Pos = 0xb
	// Bit mask of PLL4DYIE field.
	RCC_RCC_MC_CIER_PLL4DYIE_Msk = 0x800
	// Bit PLL4DYIE.
	RCC_RCC_MC_CIER_PLL4DYIE = 0x800
	// Position of LSECSSIE field.
	RCC_RCC_MC_CIER_LSECSSIE_Pos = 0x10
	// Bit mask of LSECSSIE field.
	RCC_RCC_MC_CIER_LSECSSIE_Msk = 0x10000
	// Bit LSECSSIE.
	RCC_RCC_MC_CIER_LSECSSIE = 0x10000
	// Position of WKUPIE field.
	RCC_RCC_MC_CIER_WKUPIE_Pos = 0x14
	// Bit mask of WKUPIE field.
	RCC_RCC_MC_CIER_WKUPIE_Msk = 0x100000
	// Bit WKUPIE.
	RCC_RCC_MC_CIER_WKUPIE = 0x100000

	// RCC_MC_CIFR: This register shall be used by the MCU in order to read and clear the interrupt flags.
	// Position of LSIRDYF field.
	RCC_RCC_MC_CIFR_LSIRDYF_Pos = 0x0
	// Bit mask of LSIRDYF field.
	RCC_RCC_MC_CIFR_LSIRDYF_Msk = 0x1
	// Bit LSIRDYF.
	RCC_RCC_MC_CIFR_LSIRDYF = 0x1
	// Position of LSERDYF field.
	RCC_RCC_MC_CIFR_LSERDYF_Pos = 0x1
	// Bit mask of LSERDYF field.
	RCC_RCC_MC_CIFR_LSERDYF_Msk = 0x2
	// Bit LSERDYF.
	RCC_RCC_MC_CIFR_LSERDYF = 0x2
	// Position of HSIRDYF field.
	RCC_RCC_MC_CIFR_HSIRDYF_Pos = 0x2
	// Bit mask of HSIRDYF field.
	RCC_RCC_MC_CIFR_HSIRDYF_Msk = 0x4
	// Bit HSIRDYF.
	RCC_RCC_MC_CIFR_HSIRDYF = 0x4
	// Position of HSERDYF field.
	RCC_RCC_MC_CIFR_HSERDYF_Pos = 0x3
	// Bit mask of HSERDYF field.
	RCC_RCC_MC_CIFR_HSERDYF_Msk = 0x8
	// Bit HSERDYF.
	RCC_RCC_MC_CIFR_HSERDYF = 0x8
	// Position of CSIRDYF field.
	RCC_RCC_MC_CIFR_CSIRDYF_Pos = 0x4
	// Bit mask of CSIRDYF field.
	RCC_RCC_MC_CIFR_CSIRDYF_Msk = 0x10
	// Bit CSIRDYF.
	RCC_RCC_MC_CIFR_CSIRDYF = 0x10
	// Position of PLL1DYF field.
	RCC_RCC_MC_CIFR_PLL1DYF_Pos = 0x8
	// Bit mask of PLL1DYF field.
	RCC_RCC_MC_CIFR_PLL1DYF_Msk = 0x100
	// Bit PLL1DYF.
	RCC_RCC_MC_CIFR_PLL1DYF = 0x100
	// Position of PLL2DYF field.
	RCC_RCC_MC_CIFR_PLL2DYF_Pos = 0x9
	// Bit mask of PLL2DYF field.
	RCC_RCC_MC_CIFR_PLL2DYF_Msk = 0x200
	// Bit PLL2DYF.
	RCC_RCC_MC_CIFR_PLL2DYF = 0x200
	// Position of PLL3DYF field.
	RCC_RCC_MC_CIFR_PLL3DYF_Pos = 0xa
	// Bit mask of PLL3DYF field.
	RCC_RCC_MC_CIFR_PLL3DYF_Msk = 0x400
	// Bit PLL3DYF.
	RCC_RCC_MC_CIFR_PLL3DYF = 0x400
	// Position of PLL4DYF field.
	RCC_RCC_MC_CIFR_PLL4DYF_Pos = 0xb
	// Bit mask of PLL4DYF field.
	RCC_RCC_MC_CIFR_PLL4DYF_Msk = 0x800
	// Bit PLL4DYF.
	RCC_RCC_MC_CIFR_PLL4DYF = 0x800
	// Position of LSECSSF field.
	RCC_RCC_MC_CIFR_LSECSSF_Pos = 0x10
	// Bit mask of LSECSSF field.
	RCC_RCC_MC_CIFR_LSECSSF_Msk = 0x10000
	// Bit LSECSSF.
	RCC_RCC_MC_CIFR_LSECSSF = 0x10000
	// Position of WKUPF field.
	RCC_RCC_MC_CIFR_WKUPF_Pos = 0x14
	// Bit mask of WKUPF field.
	RCC_RCC_MC_CIFR_WKUPF_Msk = 0x100000
	// Bit WKUPF.
	RCC_RCC_MC_CIFR_WKUPF = 0x100000

	// RCC_VERR: This register gives the IP version
	// Position of MINREV field.
	RCC_RCC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	RCC_RCC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	RCC_RCC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	RCC_RCC_VERR_MAJREV_Msk = 0xf0

	// RCC_IDR: This register gives the unique identifier of the RCC
	// Position of ID field.
	RCC_RCC_IDR_ID_Pos = 0x0
	// Bit mask of ID field.
	RCC_RCC_IDR_ID_Msk = 0xffffffff

	// RCC_SIDR: This register gives the decoding space, which is for the RCC of 4 kB.
	// Position of SID field.
	RCC_RCC_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	RCC_RCC_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for RNG1: RNG1
const (
	// RNG_CR: RNG control register
	// Position of RNGEN field.
	RNG1_RNG_CR_RNGEN_Pos = 0x2
	// Bit mask of RNGEN field.
	RNG1_RNG_CR_RNGEN_Msk = 0x4
	// Bit RNGEN.
	RNG1_RNG_CR_RNGEN = 0x4
	// Position of IE field.
	RNG1_RNG_CR_IE_Pos = 0x3
	// Bit mask of IE field.
	RNG1_RNG_CR_IE_Msk = 0x8
	// Bit IE.
	RNG1_RNG_CR_IE = 0x8
	// Position of CED field.
	RNG1_RNG_CR_CED_Pos = 0x5
	// Bit mask of CED field.
	RNG1_RNG_CR_CED_Msk = 0x20
	// Bit CED.
	RNG1_RNG_CR_CED = 0x20

	// RNG_SR: RNG status register
	// Position of DRDY field.
	RNG1_RNG_SR_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	RNG1_RNG_SR_DRDY_Msk = 0x1
	// Bit DRDY.
	RNG1_RNG_SR_DRDY = 0x1
	// Position of CECS field.
	RNG1_RNG_SR_CECS_Pos = 0x1
	// Bit mask of CECS field.
	RNG1_RNG_SR_CECS_Msk = 0x2
	// Bit CECS.
	RNG1_RNG_SR_CECS = 0x2
	// Position of SECS field.
	RNG1_RNG_SR_SECS_Pos = 0x2
	// Bit mask of SECS field.
	RNG1_RNG_SR_SECS_Msk = 0x4
	// Bit SECS.
	RNG1_RNG_SR_SECS = 0x4
	// Position of CEIS field.
	RNG1_RNG_SR_CEIS_Pos = 0x5
	// Bit mask of CEIS field.
	RNG1_RNG_SR_CEIS_Msk = 0x20
	// Bit CEIS.
	RNG1_RNG_SR_CEIS = 0x20
	// Position of SEIS field.
	RNG1_RNG_SR_SEIS_Pos = 0x6
	// Bit mask of SEIS field.
	RNG1_RNG_SR_SEIS_Msk = 0x40
	// Bit SEIS.
	RNG1_RNG_SR_SEIS = 0x40

	// RNG_DR: The RNG_DR register is a read-only register.
	// Position of RNDATA field.
	RNG1_RNG_DR_RNDATA_Pos = 0x0
	// Bit mask of RNDATA field.
	RNG1_RNG_DR_RNDATA_Msk = 0xffffffff

	// RNG_VERR: RNG version register
	// Position of MINREV field.
	RNG1_RNG_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	RNG1_RNG_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	RNG1_RNG_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	RNG1_RNG_VERR_MAJREV_Msk = 0xf0

	// RNG_IPIDR: RNG identification register
	// Position of ID field.
	RNG1_RNG_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	RNG1_RNG_IPIDR_ID_Msk = 0xffffffff

	// RNG_SIDR: RNG size ID register
	// Position of SID field.
	RNG1_RNG_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	RNG1_RNG_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for RTC: RTC
const (
	// RTC_TR: The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SU field.
	RTC_RTC_TR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_RTC_TR_SU_Msk = 0xf
	// Position of ST field.
	RTC_RTC_TR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_RTC_TR_ST_Msk = 0x70
	// Position of MNU field.
	RTC_RTC_TR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_RTC_TR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_RTC_TR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_RTC_TR_MNT_Msk = 0x7000
	// Position of HU field.
	RTC_RTC_TR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_RTC_TR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_RTC_TR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_RTC_TR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_RTC_TR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_RTC_TR_PM_Msk = 0x400000
	// Bit PM.
	RTC_RTC_TR_PM = 0x400000

	// RTC_DR: The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of DU field.
	RTC_RTC_DR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_RTC_DR_DU_Msk = 0xf
	// Position of DT field.
	RTC_RTC_DR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_RTC_DR_DT_Msk = 0x30
	// Position of MU field.
	RTC_RTC_DR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_RTC_DR_MU_Msk = 0xf00
	// Position of MT field.
	RTC_RTC_DR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_RTC_DR_MT_Msk = 0x1000
	// Bit MT.
	RTC_RTC_DR_MT = 0x1000
	// Position of WDU field.
	RTC_RTC_DR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_RTC_DR_WDU_Msk = 0xe000
	// Position of YU field.
	RTC_RTC_DR_YU_Pos = 0x10
	// Bit mask of YU field.
	RTC_RTC_DR_YU_Msk = 0xf0000
	// Position of YT field.
	RTC_RTC_DR_YT_Pos = 0x14
	// Bit mask of YT field.
	RTC_RTC_DR_YT_Msk = 0xf00000

	// RTC_SSR: RTC sub second register
	// Position of SS field.
	RTC_RTC_SSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_RTC_SSR_SS_Msk = 0xffff

	// RTC_ICSR: This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of ALRAWF field.
	RTC_RTC_ICSR_ALRAWF_Pos = 0x0
	// Bit mask of ALRAWF field.
	RTC_RTC_ICSR_ALRAWF_Msk = 0x1
	// Bit ALRAWF.
	RTC_RTC_ICSR_ALRAWF = 0x1
	// Position of ALRBWF field.
	RTC_RTC_ICSR_ALRBWF_Pos = 0x1
	// Bit mask of ALRBWF field.
	RTC_RTC_ICSR_ALRBWF_Msk = 0x2
	// Bit ALRBWF.
	RTC_RTC_ICSR_ALRBWF = 0x2
	// Position of WUTWF field.
	RTC_RTC_ICSR_WUTWF_Pos = 0x2
	// Bit mask of WUTWF field.
	RTC_RTC_ICSR_WUTWF_Msk = 0x4
	// Bit WUTWF.
	RTC_RTC_ICSR_WUTWF = 0x4
	// Position of SHPF field.
	RTC_RTC_ICSR_SHPF_Pos = 0x3
	// Bit mask of SHPF field.
	RTC_RTC_ICSR_SHPF_Msk = 0x8
	// Bit SHPF.
	RTC_RTC_ICSR_SHPF = 0x8
	// Position of INITS field.
	RTC_RTC_ICSR_INITS_Pos = 0x4
	// Bit mask of INITS field.
	RTC_RTC_ICSR_INITS_Msk = 0x10
	// Bit INITS.
	RTC_RTC_ICSR_INITS = 0x10
	// Position of RSF field.
	RTC_RTC_ICSR_RSF_Pos = 0x5
	// Bit mask of RSF field.
	RTC_RTC_ICSR_RSF_Msk = 0x20
	// Bit RSF.
	RTC_RTC_ICSR_RSF = 0x20
	// Position of INITF field.
	RTC_RTC_ICSR_INITF_Pos = 0x6
	// Bit mask of INITF field.
	RTC_RTC_ICSR_INITF_Msk = 0x40
	// Bit INITF.
	RTC_RTC_ICSR_INITF = 0x40
	// Position of INIT field.
	RTC_RTC_ICSR_INIT_Pos = 0x7
	// Bit mask of INIT field.
	RTC_RTC_ICSR_INIT_Msk = 0x80
	// Bit INIT.
	RTC_RTC_ICSR_INIT = 0x80
	// Position of RECALPF field.
	RTC_RTC_ICSR_RECALPF_Pos = 0x10
	// Bit mask of RECALPF field.
	RTC_RTC_ICSR_RECALPF_Msk = 0x10000
	// Bit RECALPF.
	RTC_RTC_ICSR_RECALPF = 0x10000

	// RTC_PRER: This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of PREDIV_S field.
	RTC_RTC_PRER_PREDIV_S_Pos = 0x0
	// Bit mask of PREDIV_S field.
	RTC_RTC_PRER_PREDIV_S_Msk = 0x7fff
	// Position of PREDIV_A field.
	RTC_RTC_PRER_PREDIV_A_Pos = 0x10
	// Bit mask of PREDIV_A field.
	RTC_RTC_PRER_PREDIV_A_Msk = 0x7f0000

	// RTC_WUTR: This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of WUT field.
	RTC_RTC_WUTR_WUT_Pos = 0x0
	// Bit mask of WUT field.
	RTC_RTC_WUTR_WUT_Msk = 0xffff

	// RTC_CR: This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of WUCKSEL field.
	RTC_RTC_CR_WUCKSEL_Pos = 0x0
	// Bit mask of WUCKSEL field.
	RTC_RTC_CR_WUCKSEL_Msk = 0x7
	// Position of TSEDGE field.
	RTC_RTC_CR_TSEDGE_Pos = 0x3
	// Bit mask of TSEDGE field.
	RTC_RTC_CR_TSEDGE_Msk = 0x8
	// Bit TSEDGE.
	RTC_RTC_CR_TSEDGE = 0x8
	// Position of REFCKON field.
	RTC_RTC_CR_REFCKON_Pos = 0x4
	// Bit mask of REFCKON field.
	RTC_RTC_CR_REFCKON_Msk = 0x10
	// Bit REFCKON.
	RTC_RTC_CR_REFCKON = 0x10
	// Position of BYPSHAD field.
	RTC_RTC_CR_BYPSHAD_Pos = 0x5
	// Bit mask of BYPSHAD field.
	RTC_RTC_CR_BYPSHAD_Msk = 0x20
	// Bit BYPSHAD.
	RTC_RTC_CR_BYPSHAD = 0x20
	// Position of FMT field.
	RTC_RTC_CR_FMT_Pos = 0x6
	// Bit mask of FMT field.
	RTC_RTC_CR_FMT_Msk = 0x40
	// Bit FMT.
	RTC_RTC_CR_FMT = 0x40
	// Position of ALRAE field.
	RTC_RTC_CR_ALRAE_Pos = 0x8
	// Bit mask of ALRAE field.
	RTC_RTC_CR_ALRAE_Msk = 0x100
	// Bit ALRAE.
	RTC_RTC_CR_ALRAE = 0x100
	// Position of ALRBE field.
	RTC_RTC_CR_ALRBE_Pos = 0x9
	// Bit mask of ALRBE field.
	RTC_RTC_CR_ALRBE_Msk = 0x200
	// Bit ALRBE.
	RTC_RTC_CR_ALRBE = 0x200
	// Position of WUTE field.
	RTC_RTC_CR_WUTE_Pos = 0xa
	// Bit mask of WUTE field.
	RTC_RTC_CR_WUTE_Msk = 0x400
	// Bit WUTE.
	RTC_RTC_CR_WUTE = 0x400
	// Position of TSE field.
	RTC_RTC_CR_TSE_Pos = 0xb
	// Bit mask of TSE field.
	RTC_RTC_CR_TSE_Msk = 0x800
	// Bit TSE.
	RTC_RTC_CR_TSE = 0x800
	// Position of ALRAIE field.
	RTC_RTC_CR_ALRAIE_Pos = 0xc
	// Bit mask of ALRAIE field.
	RTC_RTC_CR_ALRAIE_Msk = 0x1000
	// Bit ALRAIE.
	RTC_RTC_CR_ALRAIE = 0x1000
	// Position of ALRBIE field.
	RTC_RTC_CR_ALRBIE_Pos = 0xd
	// Bit mask of ALRBIE field.
	RTC_RTC_CR_ALRBIE_Msk = 0x2000
	// Bit ALRBIE.
	RTC_RTC_CR_ALRBIE = 0x2000
	// Position of WUTIE field.
	RTC_RTC_CR_WUTIE_Pos = 0xe
	// Bit mask of WUTIE field.
	RTC_RTC_CR_WUTIE_Msk = 0x4000
	// Bit WUTIE.
	RTC_RTC_CR_WUTIE = 0x4000
	// Position of TSIE field.
	RTC_RTC_CR_TSIE_Pos = 0xf
	// Bit mask of TSIE field.
	RTC_RTC_CR_TSIE_Msk = 0x8000
	// Bit TSIE.
	RTC_RTC_CR_TSIE = 0x8000
	// Position of ADD1H field.
	RTC_RTC_CR_ADD1H_Pos = 0x10
	// Bit mask of ADD1H field.
	RTC_RTC_CR_ADD1H_Msk = 0x10000
	// Bit ADD1H.
	RTC_RTC_CR_ADD1H = 0x10000
	// Position of SUB1H field.
	RTC_RTC_CR_SUB1H_Pos = 0x11
	// Bit mask of SUB1H field.
	RTC_RTC_CR_SUB1H_Msk = 0x20000
	// Bit SUB1H.
	RTC_RTC_CR_SUB1H = 0x20000
	// Position of BKP field.
	RTC_RTC_CR_BKP_Pos = 0x12
	// Bit mask of BKP field.
	RTC_RTC_CR_BKP_Msk = 0x40000
	// Bit BKP.
	RTC_RTC_CR_BKP = 0x40000
	// Position of COSEL field.
	RTC_RTC_CR_COSEL_Pos = 0x13
	// Bit mask of COSEL field.
	RTC_RTC_CR_COSEL_Msk = 0x80000
	// Bit COSEL.
	RTC_RTC_CR_COSEL = 0x80000
	// Position of POL field.
	RTC_RTC_CR_POL_Pos = 0x14
	// Bit mask of POL field.
	RTC_RTC_CR_POL_Msk = 0x100000
	// Bit POL.
	RTC_RTC_CR_POL = 0x100000
	// Position of OSEL field.
	RTC_RTC_CR_OSEL_Pos = 0x15
	// Bit mask of OSEL field.
	RTC_RTC_CR_OSEL_Msk = 0x600000
	// Position of COE field.
	RTC_RTC_CR_COE_Pos = 0x17
	// Bit mask of COE field.
	RTC_RTC_CR_COE_Msk = 0x800000
	// Bit COE.
	RTC_RTC_CR_COE = 0x800000
	// Position of ITSE field.
	RTC_RTC_CR_ITSE_Pos = 0x18
	// Bit mask of ITSE field.
	RTC_RTC_CR_ITSE_Msk = 0x1000000
	// Bit ITSE.
	RTC_RTC_CR_ITSE = 0x1000000
	// Position of TAMPTS field.
	RTC_RTC_CR_TAMPTS_Pos = 0x19
	// Bit mask of TAMPTS field.
	RTC_RTC_CR_TAMPTS_Msk = 0x2000000
	// Bit TAMPTS.
	RTC_RTC_CR_TAMPTS = 0x2000000
	// Position of TAMPOE field.
	RTC_RTC_CR_TAMPOE_Pos = 0x1a
	// Bit mask of TAMPOE field.
	RTC_RTC_CR_TAMPOE_Msk = 0x4000000
	// Bit TAMPOE.
	RTC_RTC_CR_TAMPOE = 0x4000000
	// Position of TAMPALRM_PU field.
	RTC_RTC_CR_TAMPALRM_PU_Pos = 0x1d
	// Bit mask of TAMPALRM_PU field.
	RTC_RTC_CR_TAMPALRM_PU_Msk = 0x20000000
	// Bit TAMPALRM_PU.
	RTC_RTC_CR_TAMPALRM_PU = 0x20000000
	// Position of TAMPALRM_TYPE field.
	RTC_RTC_CR_TAMPALRM_TYPE_Pos = 0x1e
	// Bit mask of TAMPALRM_TYPE field.
	RTC_RTC_CR_TAMPALRM_TYPE_Msk = 0x40000000
	// Bit TAMPALRM_TYPE.
	RTC_RTC_CR_TAMPALRM_TYPE = 0x40000000
	// Position of OUT2EN field.
	RTC_RTC_CR_OUT2EN_Pos = 0x1f
	// Bit mask of OUT2EN field.
	RTC_RTC_CR_OUT2EN_Msk = 0x80000000
	// Bit OUT2EN.
	RTC_RTC_CR_OUT2EN = 0x80000000

	// RTC_SMCR: This register can be written only when the APB access is secure.
	// Position of ALRADPROT field.
	RTC_RTC_SMCR_ALRADPROT_Pos = 0x0
	// Bit mask of ALRADPROT field.
	RTC_RTC_SMCR_ALRADPROT_Msk = 0x1
	// Bit ALRADPROT.
	RTC_RTC_SMCR_ALRADPROT = 0x1
	// Position of ALRBDPROT field.
	RTC_RTC_SMCR_ALRBDPROT_Pos = 0x1
	// Bit mask of ALRBDPROT field.
	RTC_RTC_SMCR_ALRBDPROT_Msk = 0x2
	// Bit ALRBDPROT.
	RTC_RTC_SMCR_ALRBDPROT = 0x2
	// Position of WUTDPROT field.
	RTC_RTC_SMCR_WUTDPROT_Pos = 0x2
	// Bit mask of WUTDPROT field.
	RTC_RTC_SMCR_WUTDPROT_Msk = 0x4
	// Bit WUTDPROT.
	RTC_RTC_SMCR_WUTDPROT = 0x4
	// Position of TSDPROT field.
	RTC_RTC_SMCR_TSDPROT_Pos = 0x3
	// Bit mask of TSDPROT field.
	RTC_RTC_SMCR_TSDPROT_Msk = 0x8
	// Bit TSDPROT.
	RTC_RTC_SMCR_TSDPROT = 0x8
	// Position of CALDPROT field.
	RTC_RTC_SMCR_CALDPROT_Pos = 0xd
	// Bit mask of CALDPROT field.
	RTC_RTC_SMCR_CALDPROT_Msk = 0x2000
	// Bit CALDPROT.
	RTC_RTC_SMCR_CALDPROT = 0x2000
	// Position of INITDPROT field.
	RTC_RTC_SMCR_INITDPROT_Pos = 0xe
	// Bit mask of INITDPROT field.
	RTC_RTC_SMCR_INITDPROT_Msk = 0x4000
	// Bit INITDPROT.
	RTC_RTC_SMCR_INITDPROT = 0x4000
	// Position of DECPROT field.
	RTC_RTC_SMCR_DECPROT_Pos = 0xf
	// Bit mask of DECPROT field.
	RTC_RTC_SMCR_DECPROT_Msk = 0x8000
	// Bit DECPROT.
	RTC_RTC_SMCR_DECPROT = 0x8000

	// RTC_WPR: RTC write protection register
	// Position of KEY field.
	RTC_RTC_WPR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	RTC_RTC_WPR_KEY_Msk = 0xff

	// RTC_CALR: This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of CALM field.
	RTC_RTC_CALR_CALM_Pos = 0x0
	// Bit mask of CALM field.
	RTC_RTC_CALR_CALM_Msk = 0x1ff
	// Position of CALW16 field.
	RTC_RTC_CALR_CALW16_Pos = 0xd
	// Bit mask of CALW16 field.
	RTC_RTC_CALR_CALW16_Msk = 0x2000
	// Bit CALW16.
	RTC_RTC_CALR_CALW16 = 0x2000
	// Position of CALW8 field.
	RTC_RTC_CALR_CALW8_Pos = 0xe
	// Bit mask of CALW8 field.
	RTC_RTC_CALR_CALW8_Msk = 0x4000
	// Bit CALW8.
	RTC_RTC_CALR_CALW8 = 0x4000
	// Position of CALP field.
	RTC_RTC_CALR_CALP_Pos = 0xf
	// Bit mask of CALP field.
	RTC_RTC_CALR_CALP_Msk = 0x8000
	// Bit CALP.
	RTC_RTC_CALR_CALP = 0x8000

	// RTC_SHIFTR: This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SUBFS field.
	RTC_RTC_SHIFTR_SUBFS_Pos = 0x0
	// Bit mask of SUBFS field.
	RTC_RTC_SHIFTR_SUBFS_Msk = 0x7fff
	// Position of ADD1S field.
	RTC_RTC_SHIFTR_ADD1S_Pos = 0x1f
	// Bit mask of ADD1S field.
	RTC_RTC_SHIFTR_ADD1S_Msk = 0x80000000
	// Bit ADD1S.
	RTC_RTC_SHIFTR_ADD1S = 0x80000000

	// RTC_TSTR: The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SU field.
	RTC_RTC_TSTR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_RTC_TSTR_SU_Msk = 0xf
	// Position of ST field.
	RTC_RTC_TSTR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_RTC_TSTR_ST_Msk = 0x70
	// Position of MNU field.
	RTC_RTC_TSTR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_RTC_TSTR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_RTC_TSTR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_RTC_TSTR_MNT_Msk = 0x7000
	// Position of HU field.
	RTC_RTC_TSTR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_RTC_TSTR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_RTC_TSTR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_RTC_TSTR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_RTC_TSTR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_RTC_TSTR_PM_Msk = 0x400000
	// Bit PM.
	RTC_RTC_TSTR_PM = 0x400000

	// RTC_TSDR: The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of DU field.
	RTC_RTC_TSDR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_RTC_TSDR_DU_Msk = 0xf
	// Position of DT field.
	RTC_RTC_TSDR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_RTC_TSDR_DT_Msk = 0x30
	// Position of MU field.
	RTC_RTC_TSDR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_RTC_TSDR_MU_Msk = 0xf00
	// Position of MT field.
	RTC_RTC_TSDR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_RTC_TSDR_MT_Msk = 0x1000
	// Bit MT.
	RTC_RTC_TSDR_MT = 0x1000
	// Position of WDU field.
	RTC_RTC_TSDR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_RTC_TSDR_WDU_Msk = 0xe000

	// RTC_TSSSR: The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SS field.
	RTC_RTC_TSSSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_RTC_TSSSR_SS_Msk = 0xffff

	// RTC_ALRMAR: This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SU field.
	RTC_RTC_ALRMAR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_RTC_ALRMAR_SU_Msk = 0xf
	// Position of ST field.
	RTC_RTC_ALRMAR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_RTC_ALRMAR_ST_Msk = 0x70
	// Position of MSK1 field.
	RTC_RTC_ALRMAR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_RTC_ALRMAR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_RTC_ALRMAR_MSK1 = 0x80
	// Position of MNU field.
	RTC_RTC_ALRMAR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_RTC_ALRMAR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_RTC_ALRMAR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_RTC_ALRMAR_MNT_Msk = 0x7000
	// Position of MSK2 field.
	RTC_RTC_ALRMAR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_RTC_ALRMAR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_RTC_ALRMAR_MSK2 = 0x8000
	// Position of HU field.
	RTC_RTC_ALRMAR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_RTC_ALRMAR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_RTC_ALRMAR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_RTC_ALRMAR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_RTC_ALRMAR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_RTC_ALRMAR_PM_Msk = 0x400000
	// Bit PM.
	RTC_RTC_ALRMAR_PM = 0x400000
	// Position of MSK3 field.
	RTC_RTC_ALRMAR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_RTC_ALRMAR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_RTC_ALRMAR_MSK3 = 0x800000
	// Position of DU field.
	RTC_RTC_ALRMAR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_RTC_ALRMAR_DU_Msk = 0xf000000
	// Position of DT field.
	RTC_RTC_ALRMAR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_RTC_ALRMAR_DT_Msk = 0x30000000
	// Position of WDSEL field.
	RTC_RTC_ALRMAR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_RTC_ALRMAR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_RTC_ALRMAR_WDSEL = 0x40000000
	// Position of MSK4 field.
	RTC_RTC_ALRMAR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_RTC_ALRMAR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_RTC_ALRMAR_MSK4 = 0x80000000

	// RTC_ALRMASSR: This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SS field.
	RTC_RTC_ALRMASSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_RTC_ALRMASSR_SS_Msk = 0x7fff
	// Position of MASKSS field.
	RTC_RTC_ALRMASSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_RTC_ALRMASSR_MASKSS_Msk = 0xf000000

	// RTC_ALRMBR: This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SU field.
	RTC_RTC_ALRMBR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_RTC_ALRMBR_SU_Msk = 0xf
	// Position of ST field.
	RTC_RTC_ALRMBR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_RTC_ALRMBR_ST_Msk = 0x70
	// Position of MSK1 field.
	RTC_RTC_ALRMBR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_RTC_ALRMBR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_RTC_ALRMBR_MSK1 = 0x80
	// Position of MNU field.
	RTC_RTC_ALRMBR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_RTC_ALRMBR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_RTC_ALRMBR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_RTC_ALRMBR_MNT_Msk = 0x7000
	// Position of MSK2 field.
	RTC_RTC_ALRMBR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_RTC_ALRMBR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_RTC_ALRMBR_MSK2 = 0x8000
	// Position of HU field.
	RTC_RTC_ALRMBR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_RTC_ALRMBR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_RTC_ALRMBR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_RTC_ALRMBR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_RTC_ALRMBR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_RTC_ALRMBR_PM_Msk = 0x400000
	// Bit PM.
	RTC_RTC_ALRMBR_PM = 0x400000
	// Position of MSK3 field.
	RTC_RTC_ALRMBR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_RTC_ALRMBR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_RTC_ALRMBR_MSK3 = 0x800000
	// Position of DU field.
	RTC_RTC_ALRMBR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_RTC_ALRMBR_DU_Msk = 0xf000000
	// Position of DT field.
	RTC_RTC_ALRMBR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_RTC_ALRMBR_DT_Msk = 0x30000000
	// Position of WDSEL field.
	RTC_RTC_ALRMBR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_RTC_ALRMBR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_RTC_ALRMBR_WDSEL = 0x40000000
	// Position of MSK4 field.
	RTC_RTC_ALRMBR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_RTC_ALRMBR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_RTC_ALRMBR_MSK4 = 0x80000000

	// RTC_ALRMBSSR: This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of SS field.
	RTC_RTC_ALRMBSSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_RTC_ALRMBSSR_SS_Msk = 0x7fff
	// Position of MASKSS field.
	RTC_RTC_ALRMBSSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_RTC_ALRMBSSR_MASKSS_Msk = 0xf000000

	// RTC_SR: This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of ALRAF field.
	RTC_RTC_SR_ALRAF_Pos = 0x0
	// Bit mask of ALRAF field.
	RTC_RTC_SR_ALRAF_Msk = 0x1
	// Bit ALRAF.
	RTC_RTC_SR_ALRAF = 0x1
	// Position of ALRBF field.
	RTC_RTC_SR_ALRBF_Pos = 0x1
	// Bit mask of ALRBF field.
	RTC_RTC_SR_ALRBF_Msk = 0x2
	// Bit ALRBF.
	RTC_RTC_SR_ALRBF = 0x2
	// Position of WUTF field.
	RTC_RTC_SR_WUTF_Pos = 0x2
	// Bit mask of WUTF field.
	RTC_RTC_SR_WUTF_Msk = 0x4
	// Bit WUTF.
	RTC_RTC_SR_WUTF = 0x4
	// Position of TSF field.
	RTC_RTC_SR_TSF_Pos = 0x3
	// Bit mask of TSF field.
	RTC_RTC_SR_TSF_Msk = 0x8
	// Bit TSF.
	RTC_RTC_SR_TSF = 0x8
	// Position of TSOVF field.
	RTC_RTC_SR_TSOVF_Pos = 0x4
	// Bit mask of TSOVF field.
	RTC_RTC_SR_TSOVF_Msk = 0x10
	// Bit TSOVF.
	RTC_RTC_SR_TSOVF = 0x10
	// Position of ITSF field.
	RTC_RTC_SR_ITSF_Pos = 0x5
	// Bit mask of ITSF field.
	RTC_RTC_SR_ITSF_Msk = 0x20
	// Bit ITSF.
	RTC_RTC_SR_ITSF = 0x20

	// RTC_MISR: RTC non-secure masked interrupt status register
	// Position of ALRAMF field.
	RTC_RTC_MISR_ALRAMF_Pos = 0x0
	// Bit mask of ALRAMF field.
	RTC_RTC_MISR_ALRAMF_Msk = 0x1
	// Bit ALRAMF.
	RTC_RTC_MISR_ALRAMF = 0x1
	// Position of ALRBMF field.
	RTC_RTC_MISR_ALRBMF_Pos = 0x1
	// Bit mask of ALRBMF field.
	RTC_RTC_MISR_ALRBMF_Msk = 0x2
	// Bit ALRBMF.
	RTC_RTC_MISR_ALRBMF = 0x2
	// Position of WUTMF field.
	RTC_RTC_MISR_WUTMF_Pos = 0x2
	// Bit mask of WUTMF field.
	RTC_RTC_MISR_WUTMF_Msk = 0x4
	// Bit WUTMF.
	RTC_RTC_MISR_WUTMF = 0x4
	// Position of TSMF field.
	RTC_RTC_MISR_TSMF_Pos = 0x3
	// Bit mask of TSMF field.
	RTC_RTC_MISR_TSMF_Msk = 0x8
	// Bit TSMF.
	RTC_RTC_MISR_TSMF = 0x8
	// Position of TSOVMF field.
	RTC_RTC_MISR_TSOVMF_Pos = 0x4
	// Bit mask of TSOVMF field.
	RTC_RTC_MISR_TSOVMF_Msk = 0x10
	// Bit TSOVMF.
	RTC_RTC_MISR_TSOVMF = 0x10
	// Position of ITSMF field.
	RTC_RTC_MISR_ITSMF_Pos = 0x5
	// Bit mask of ITSMF field.
	RTC_RTC_MISR_ITSMF_Msk = 0x20
	// Bit ITSMF.
	RTC_RTC_MISR_ITSMF = 0x20

	// RTC_SMISR: This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of ALRAMF field.
	RTC_RTC_SMISR_ALRAMF_Pos = 0x0
	// Bit mask of ALRAMF field.
	RTC_RTC_SMISR_ALRAMF_Msk = 0x1
	// Bit ALRAMF.
	RTC_RTC_SMISR_ALRAMF = 0x1
	// Position of ALRBMF field.
	RTC_RTC_SMISR_ALRBMF_Pos = 0x1
	// Bit mask of ALRBMF field.
	RTC_RTC_SMISR_ALRBMF_Msk = 0x2
	// Bit ALRBMF.
	RTC_RTC_SMISR_ALRBMF = 0x2
	// Position of WUTMF field.
	RTC_RTC_SMISR_WUTMF_Pos = 0x2
	// Bit mask of WUTMF field.
	RTC_RTC_SMISR_WUTMF_Msk = 0x4
	// Bit WUTMF.
	RTC_RTC_SMISR_WUTMF = 0x4
	// Position of TSMF field.
	RTC_RTC_SMISR_TSMF_Pos = 0x3
	// Bit mask of TSMF field.
	RTC_RTC_SMISR_TSMF_Msk = 0x8
	// Bit TSMF.
	RTC_RTC_SMISR_TSMF = 0x8
	// Position of TSOVMF field.
	RTC_RTC_SMISR_TSOVMF_Pos = 0x4
	// Bit mask of TSOVMF field.
	RTC_RTC_SMISR_TSOVMF_Msk = 0x10
	// Bit TSOVMF.
	RTC_RTC_SMISR_TSOVMF = 0x10
	// Position of ITSMF field.
	RTC_RTC_SMISR_ITSMF_Pos = 0x5
	// Bit mask of ITSMF field.
	RTC_RTC_SMISR_ITSMF_Msk = 0x20
	// Bit ITSMF.
	RTC_RTC_SMISR_ITSMF = 0x20

	// RTC_SCR: This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
	// Position of CALRAF field.
	RTC_RTC_SCR_CALRAF_Pos = 0x0
	// Bit mask of CALRAF field.
	RTC_RTC_SCR_CALRAF_Msk = 0x1
	// Bit CALRAF.
	RTC_RTC_SCR_CALRAF = 0x1
	// Position of CALRBF field.
	RTC_RTC_SCR_CALRBF_Pos = 0x1
	// Bit mask of CALRBF field.
	RTC_RTC_SCR_CALRBF_Msk = 0x2
	// Bit CALRBF.
	RTC_RTC_SCR_CALRBF = 0x2
	// Position of CWUTF field.
	RTC_RTC_SCR_CWUTF_Pos = 0x2
	// Bit mask of CWUTF field.
	RTC_RTC_SCR_CWUTF_Msk = 0x4
	// Bit CWUTF.
	RTC_RTC_SCR_CWUTF = 0x4
	// Position of CTSF field.
	RTC_RTC_SCR_CTSF_Pos = 0x3
	// Bit mask of CTSF field.
	RTC_RTC_SCR_CTSF_Msk = 0x8
	// Bit CTSF.
	RTC_RTC_SCR_CTSF = 0x8
	// Position of CTSOVF field.
	RTC_RTC_SCR_CTSOVF_Pos = 0x4
	// Bit mask of CTSOVF field.
	RTC_RTC_SCR_CTSOVF_Msk = 0x10
	// Bit CTSOVF.
	RTC_RTC_SCR_CTSOVF = 0x10
	// Position of CITSF field.
	RTC_RTC_SCR_CITSF_Pos = 0x5
	// Bit mask of CITSF field.
	RTC_RTC_SCR_CITSF_Msk = 0x20
	// Bit CITSF.
	RTC_RTC_SCR_CITSF = 0x20

	// RTC_CFGR: RTC configuration register
	// Position of OUT2_RMP field.
	RTC_RTC_CFGR_OUT2_RMP_Pos = 0x0
	// Bit mask of OUT2_RMP field.
	RTC_RTC_CFGR_OUT2_RMP_Msk = 0x1
	// Bit OUT2_RMP.
	RTC_RTC_CFGR_OUT2_RMP = 0x1
	// Position of LSCOEN field.
	RTC_RTC_CFGR_LSCOEN_Pos = 0x1
	// Bit mask of LSCOEN field.
	RTC_RTC_CFGR_LSCOEN_Msk = 0x6

	// RTC_HWCFGR: RTC hardware configuration register
	// Position of ALARMB field.
	RTC_RTC_HWCFGR_ALARMB_Pos = 0x0
	// Bit mask of ALARMB field.
	RTC_RTC_HWCFGR_ALARMB_Msk = 0xf
	// Position of WAKEUP field.
	RTC_RTC_HWCFGR_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	RTC_RTC_HWCFGR_WAKEUP_Msk = 0xf0
	// Position of SMOOTH_CALIB field.
	RTC_RTC_HWCFGR_SMOOTH_CALIB_Pos = 0x8
	// Bit mask of SMOOTH_CALIB field.
	RTC_RTC_HWCFGR_SMOOTH_CALIB_Msk = 0xf00
	// Position of TIMESTAMP field.
	RTC_RTC_HWCFGR_TIMESTAMP_Pos = 0xc
	// Bit mask of TIMESTAMP field.
	RTC_RTC_HWCFGR_TIMESTAMP_Msk = 0xf000
	// Position of OPTIONREG_OUT field.
	RTC_RTC_HWCFGR_OPTIONREG_OUT_Pos = 0x10
	// Bit mask of OPTIONREG_OUT field.
	RTC_RTC_HWCFGR_OPTIONREG_OUT_Msk = 0xff0000
	// Position of TRUST_ZONE field.
	RTC_RTC_HWCFGR_TRUST_ZONE_Pos = 0x18
	// Bit mask of TRUST_ZONE field.
	RTC_RTC_HWCFGR_TRUST_ZONE_Msk = 0xf000000

	// RTC_VERR: RTC version register
	// Position of MINREV field.
	RTC_RTC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	RTC_RTC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	RTC_RTC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	RTC_RTC_VERR_MAJREV_Msk = 0xf0

	// RTC_IPIDR: RTC identification register
	// Position of ID field.
	RTC_RTC_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	RTC_RTC_IPIDR_ID_Msk = 0xffffffff

	// RTC_SIDR: RTC size identification register
	// Position of SID field.
	RTC_RTC_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	RTC_RTC_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for SAI1: SAI1 register block
const (
	// SAI_GCR: Global configuration register
	// Position of SYNCIN field.
	SAI_SAI_GCR_SYNCIN_Pos = 0x0
	// Bit mask of SYNCIN field.
	SAI_SAI_GCR_SYNCIN_Msk = 0x3
	// Position of SYNCOUT field.
	SAI_SAI_GCR_SYNCOUT_Pos = 0x4
	// Bit mask of SYNCOUT field.
	SAI_SAI_GCR_SYNCOUT_Msk = 0x30

	// SAI_ACR1: Configuration register 1
	// Position of MODE field.
	SAI_SAI_ACR1_MODE_Pos = 0x0
	// Bit mask of MODE field.
	SAI_SAI_ACR1_MODE_Msk = 0x3
	// Position of PRTCFG field.
	SAI_SAI_ACR1_PRTCFG_Pos = 0x2
	// Bit mask of PRTCFG field.
	SAI_SAI_ACR1_PRTCFG_Msk = 0xc
	// Position of DS field.
	SAI_SAI_ACR1_DS_Pos = 0x5
	// Bit mask of DS field.
	SAI_SAI_ACR1_DS_Msk = 0xe0
	// Position of LSBFIRST field.
	SAI_SAI_ACR1_LSBFIRST_Pos = 0x8
	// Bit mask of LSBFIRST field.
	SAI_SAI_ACR1_LSBFIRST_Msk = 0x100
	// Bit LSBFIRST.
	SAI_SAI_ACR1_LSBFIRST = 0x100
	// Position of CKSTR field.
	SAI_SAI_ACR1_CKSTR_Pos = 0x9
	// Bit mask of CKSTR field.
	SAI_SAI_ACR1_CKSTR_Msk = 0x200
	// Bit CKSTR.
	SAI_SAI_ACR1_CKSTR = 0x200
	// Position of SYNCEN field.
	SAI_SAI_ACR1_SYNCEN_Pos = 0xa
	// Bit mask of SYNCEN field.
	SAI_SAI_ACR1_SYNCEN_Msk = 0xc00
	// Position of MONO field.
	SAI_SAI_ACR1_MONO_Pos = 0xc
	// Bit mask of MONO field.
	SAI_SAI_ACR1_MONO_Msk = 0x1000
	// Bit MONO.
	SAI_SAI_ACR1_MONO = 0x1000
	// Position of OUTDRIV field.
	SAI_SAI_ACR1_OUTDRIV_Pos = 0xd
	// Bit mask of OUTDRIV field.
	SAI_SAI_ACR1_OUTDRIV_Msk = 0x2000
	// Bit OUTDRIV.
	SAI_SAI_ACR1_OUTDRIV = 0x2000
	// Position of SAIEN field.
	SAI_SAI_ACR1_SAIEN_Pos = 0x10
	// Bit mask of SAIEN field.
	SAI_SAI_ACR1_SAIEN_Msk = 0x10000
	// Bit SAIEN.
	SAI_SAI_ACR1_SAIEN = 0x10000
	// Position of DMAEN field.
	SAI_SAI_ACR1_DMAEN_Pos = 0x11
	// Bit mask of DMAEN field.
	SAI_SAI_ACR1_DMAEN_Msk = 0x20000
	// Bit DMAEN.
	SAI_SAI_ACR1_DMAEN = 0x20000
	// Position of NODIV field.
	SAI_SAI_ACR1_NODIV_Pos = 0x13
	// Bit mask of NODIV field.
	SAI_SAI_ACR1_NODIV_Msk = 0x80000
	// Bit NODIV.
	SAI_SAI_ACR1_NODIV = 0x80000
	// Position of MCKDIV field.
	SAI_SAI_ACR1_MCKDIV_Pos = 0x14
	// Bit mask of MCKDIV field.
	SAI_SAI_ACR1_MCKDIV_Msk = 0x3f00000
	// Position of OSR field.
	SAI_SAI_ACR1_OSR_Pos = 0x1a
	// Bit mask of OSR field.
	SAI_SAI_ACR1_OSR_Msk = 0x4000000
	// Bit OSR.
	SAI_SAI_ACR1_OSR = 0x4000000
	// Position of MCKEN field.
	SAI_SAI_ACR1_MCKEN_Pos = 0x1b
	// Bit mask of MCKEN field.
	SAI_SAI_ACR1_MCKEN_Msk = 0x8000000
	// Bit MCKEN.
	SAI_SAI_ACR1_MCKEN = 0x8000000

	// SAI_ACR2: Configuration register 2
	// Position of FTH field.
	SAI_SAI_ACR2_FTH_Pos = 0x0
	// Bit mask of FTH field.
	SAI_SAI_ACR2_FTH_Msk = 0x7
	// Position of FFLUSH field.
	SAI_SAI_ACR2_FFLUSH_Pos = 0x3
	// Bit mask of FFLUSH field.
	SAI_SAI_ACR2_FFLUSH_Msk = 0x8
	// Bit FFLUSH.
	SAI_SAI_ACR2_FFLUSH = 0x8
	// Position of TRIS field.
	SAI_SAI_ACR2_TRIS_Pos = 0x4
	// Bit mask of TRIS field.
	SAI_SAI_ACR2_TRIS_Msk = 0x10
	// Bit TRIS.
	SAI_SAI_ACR2_TRIS = 0x10
	// Position of MUTE field.
	SAI_SAI_ACR2_MUTE_Pos = 0x5
	// Bit mask of MUTE field.
	SAI_SAI_ACR2_MUTE_Msk = 0x20
	// Bit MUTE.
	SAI_SAI_ACR2_MUTE = 0x20
	// Position of MUTEVAL field.
	SAI_SAI_ACR2_MUTEVAL_Pos = 0x6
	// Bit mask of MUTEVAL field.
	SAI_SAI_ACR2_MUTEVAL_Msk = 0x40
	// Bit MUTEVAL.
	SAI_SAI_ACR2_MUTEVAL = 0x40
	// Position of MUTECNT field.
	SAI_SAI_ACR2_MUTECNT_Pos = 0x7
	// Bit mask of MUTECNT field.
	SAI_SAI_ACR2_MUTECNT_Msk = 0x1f80
	// Position of CPL field.
	SAI_SAI_ACR2_CPL_Pos = 0xd
	// Bit mask of CPL field.
	SAI_SAI_ACR2_CPL_Msk = 0x2000
	// Bit CPL.
	SAI_SAI_ACR2_CPL = 0x2000
	// Position of COMP field.
	SAI_SAI_ACR2_COMP_Pos = 0xe
	// Bit mask of COMP field.
	SAI_SAI_ACR2_COMP_Msk = 0xc000

	// SAI_AFRCR: This register has no meaning in and SPDIF audio protocol
	// Position of FRL field.
	SAI_SAI_AFRCR_FRL_Pos = 0x0
	// Bit mask of FRL field.
	SAI_SAI_AFRCR_FRL_Msk = 0xff
	// Position of FSALL field.
	SAI_SAI_AFRCR_FSALL_Pos = 0x8
	// Bit mask of FSALL field.
	SAI_SAI_AFRCR_FSALL_Msk = 0x7f00
	// Position of FSDEF field.
	SAI_SAI_AFRCR_FSDEF_Pos = 0x10
	// Bit mask of FSDEF field.
	SAI_SAI_AFRCR_FSDEF_Msk = 0x10000
	// Bit FSDEF.
	SAI_SAI_AFRCR_FSDEF = 0x10000
	// Position of FSPOL field.
	SAI_SAI_AFRCR_FSPOL_Pos = 0x11
	// Bit mask of FSPOL field.
	SAI_SAI_AFRCR_FSPOL_Msk = 0x20000
	// Bit FSPOL.
	SAI_SAI_AFRCR_FSPOL = 0x20000
	// Position of FSOFF field.
	SAI_SAI_AFRCR_FSOFF_Pos = 0x12
	// Bit mask of FSOFF field.
	SAI_SAI_AFRCR_FSOFF_Msk = 0x40000
	// Bit FSOFF.
	SAI_SAI_AFRCR_FSOFF = 0x40000

	// SAI_ASLOTR: This register has no meaning in and SPDIF audio protocol
	// Position of FBOFF field.
	SAI_SAI_ASLOTR_FBOFF_Pos = 0x0
	// Bit mask of FBOFF field.
	SAI_SAI_ASLOTR_FBOFF_Msk = 0x1f
	// Position of SLOTSZ field.
	SAI_SAI_ASLOTR_SLOTSZ_Pos = 0x6
	// Bit mask of SLOTSZ field.
	SAI_SAI_ASLOTR_SLOTSZ_Msk = 0xc0
	// Position of NBSLOT field.
	SAI_SAI_ASLOTR_NBSLOT_Pos = 0x8
	// Bit mask of NBSLOT field.
	SAI_SAI_ASLOTR_NBSLOT_Msk = 0xf00
	// Position of SLOTEN field.
	SAI_SAI_ASLOTR_SLOTEN_Pos = 0x10
	// Bit mask of SLOTEN field.
	SAI_SAI_ASLOTR_SLOTEN_Msk = 0xffff0000

	// SAI_AIM: Interrupt mask register
	// Position of OVRUDRIE field.
	SAI_SAI_AIM_OVRUDRIE_Pos = 0x0
	// Bit mask of OVRUDRIE field.
	SAI_SAI_AIM_OVRUDRIE_Msk = 0x1
	// Bit OVRUDRIE.
	SAI_SAI_AIM_OVRUDRIE = 0x1
	// Position of MUTEDETIE field.
	SAI_SAI_AIM_MUTEDETIE_Pos = 0x1
	// Bit mask of MUTEDETIE field.
	SAI_SAI_AIM_MUTEDETIE_Msk = 0x2
	// Bit MUTEDETIE.
	SAI_SAI_AIM_MUTEDETIE = 0x2
	// Position of WCKCFGIE field.
	SAI_SAI_AIM_WCKCFGIE_Pos = 0x2
	// Bit mask of WCKCFGIE field.
	SAI_SAI_AIM_WCKCFGIE_Msk = 0x4
	// Bit WCKCFGIE.
	SAI_SAI_AIM_WCKCFGIE = 0x4
	// Position of FREQIE field.
	SAI_SAI_AIM_FREQIE_Pos = 0x3
	// Bit mask of FREQIE field.
	SAI_SAI_AIM_FREQIE_Msk = 0x8
	// Bit FREQIE.
	SAI_SAI_AIM_FREQIE = 0x8
	// Position of CNRDYIE field.
	SAI_SAI_AIM_CNRDYIE_Pos = 0x4
	// Bit mask of CNRDYIE field.
	SAI_SAI_AIM_CNRDYIE_Msk = 0x10
	// Bit CNRDYIE.
	SAI_SAI_AIM_CNRDYIE = 0x10
	// Position of AFSDETIE field.
	SAI_SAI_AIM_AFSDETIE_Pos = 0x5
	// Bit mask of AFSDETIE field.
	SAI_SAI_AIM_AFSDETIE_Msk = 0x20
	// Bit AFSDETIE.
	SAI_SAI_AIM_AFSDETIE = 0x20
	// Position of LFSDETIE field.
	SAI_SAI_AIM_LFSDETIE_Pos = 0x6
	// Bit mask of LFSDETIE field.
	SAI_SAI_AIM_LFSDETIE_Msk = 0x40
	// Bit LFSDETIE.
	SAI_SAI_AIM_LFSDETIE = 0x40

	// SAI_ASR: Status register
	// Position of OVRUDR field.
	SAI_SAI_ASR_OVRUDR_Pos = 0x0
	// Bit mask of OVRUDR field.
	SAI_SAI_ASR_OVRUDR_Msk = 0x1
	// Bit OVRUDR.
	SAI_SAI_ASR_OVRUDR = 0x1
	// Position of MUTEDET field.
	SAI_SAI_ASR_MUTEDET_Pos = 0x1
	// Bit mask of MUTEDET field.
	SAI_SAI_ASR_MUTEDET_Msk = 0x2
	// Bit MUTEDET.
	SAI_SAI_ASR_MUTEDET = 0x2
	// Position of WCKCFG field.
	SAI_SAI_ASR_WCKCFG_Pos = 0x2
	// Bit mask of WCKCFG field.
	SAI_SAI_ASR_WCKCFG_Msk = 0x4
	// Bit WCKCFG.
	SAI_SAI_ASR_WCKCFG = 0x4
	// Position of FREQ field.
	SAI_SAI_ASR_FREQ_Pos = 0x3
	// Bit mask of FREQ field.
	SAI_SAI_ASR_FREQ_Msk = 0x8
	// Bit FREQ.
	SAI_SAI_ASR_FREQ = 0x8
	// Position of CNRDY field.
	SAI_SAI_ASR_CNRDY_Pos = 0x4
	// Bit mask of CNRDY field.
	SAI_SAI_ASR_CNRDY_Msk = 0x10
	// Bit CNRDY.
	SAI_SAI_ASR_CNRDY = 0x10
	// Position of AFSDET field.
	SAI_SAI_ASR_AFSDET_Pos = 0x5
	// Bit mask of AFSDET field.
	SAI_SAI_ASR_AFSDET_Msk = 0x20
	// Bit AFSDET.
	SAI_SAI_ASR_AFSDET = 0x20
	// Position of LFSDET field.
	SAI_SAI_ASR_LFSDET_Pos = 0x6
	// Bit mask of LFSDET field.
	SAI_SAI_ASR_LFSDET_Msk = 0x40
	// Bit LFSDET.
	SAI_SAI_ASR_LFSDET = 0x40
	// Position of FLVL field.
	SAI_SAI_ASR_FLVL_Pos = 0x10
	// Bit mask of FLVL field.
	SAI_SAI_ASR_FLVL_Msk = 0x70000

	// SAI_ACLRFR: Clear flag register
	// Position of COVRUDR field.
	SAI_SAI_ACLRFR_COVRUDR_Pos = 0x0
	// Bit mask of COVRUDR field.
	SAI_SAI_ACLRFR_COVRUDR_Msk = 0x1
	// Bit COVRUDR.
	SAI_SAI_ACLRFR_COVRUDR = 0x1
	// Position of CMUTEDET field.
	SAI_SAI_ACLRFR_CMUTEDET_Pos = 0x1
	// Bit mask of CMUTEDET field.
	SAI_SAI_ACLRFR_CMUTEDET_Msk = 0x2
	// Bit CMUTEDET.
	SAI_SAI_ACLRFR_CMUTEDET = 0x2
	// Position of CWCKCFG field.
	SAI_SAI_ACLRFR_CWCKCFG_Pos = 0x2
	// Bit mask of CWCKCFG field.
	SAI_SAI_ACLRFR_CWCKCFG_Msk = 0x4
	// Bit CWCKCFG.
	SAI_SAI_ACLRFR_CWCKCFG = 0x4
	// Position of CCNRDY field.
	SAI_SAI_ACLRFR_CCNRDY_Pos = 0x4
	// Bit mask of CCNRDY field.
	SAI_SAI_ACLRFR_CCNRDY_Msk = 0x10
	// Bit CCNRDY.
	SAI_SAI_ACLRFR_CCNRDY = 0x10
	// Position of CAFSDET field.
	SAI_SAI_ACLRFR_CAFSDET_Pos = 0x5
	// Bit mask of CAFSDET field.
	SAI_SAI_ACLRFR_CAFSDET_Msk = 0x20
	// Bit CAFSDET.
	SAI_SAI_ACLRFR_CAFSDET = 0x20
	// Position of CLFSDET field.
	SAI_SAI_ACLRFR_CLFSDET_Pos = 0x6
	// Bit mask of CLFSDET field.
	SAI_SAI_ACLRFR_CLFSDET_Msk = 0x40
	// Bit CLFSDET.
	SAI_SAI_ACLRFR_CLFSDET = 0x40

	// SAI_ADR: Data register
	// Position of DATA field.
	SAI_SAI_ADR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SAI_SAI_ADR_DATA_Msk = 0xffffffff

	// SAI_BCR1: Configuration register 1
	// Position of MODE field.
	SAI_SAI_BCR1_MODE_Pos = 0x0
	// Bit mask of MODE field.
	SAI_SAI_BCR1_MODE_Msk = 0x3
	// Position of PRTCFG field.
	SAI_SAI_BCR1_PRTCFG_Pos = 0x2
	// Bit mask of PRTCFG field.
	SAI_SAI_BCR1_PRTCFG_Msk = 0xc
	// Position of DS field.
	SAI_SAI_BCR1_DS_Pos = 0x5
	// Bit mask of DS field.
	SAI_SAI_BCR1_DS_Msk = 0xe0
	// Position of LSBFIRST field.
	SAI_SAI_BCR1_LSBFIRST_Pos = 0x8
	// Bit mask of LSBFIRST field.
	SAI_SAI_BCR1_LSBFIRST_Msk = 0x100
	// Bit LSBFIRST.
	SAI_SAI_BCR1_LSBFIRST = 0x100
	// Position of CKSTR field.
	SAI_SAI_BCR1_CKSTR_Pos = 0x9
	// Bit mask of CKSTR field.
	SAI_SAI_BCR1_CKSTR_Msk = 0x200
	// Bit CKSTR.
	SAI_SAI_BCR1_CKSTR = 0x200
	// Position of SYNCEN field.
	SAI_SAI_BCR1_SYNCEN_Pos = 0xa
	// Bit mask of SYNCEN field.
	SAI_SAI_BCR1_SYNCEN_Msk = 0xc00
	// Position of MONO field.
	SAI_SAI_BCR1_MONO_Pos = 0xc
	// Bit mask of MONO field.
	SAI_SAI_BCR1_MONO_Msk = 0x1000
	// Bit MONO.
	SAI_SAI_BCR1_MONO = 0x1000
	// Position of OUTDRIV field.
	SAI_SAI_BCR1_OUTDRIV_Pos = 0xd
	// Bit mask of OUTDRIV field.
	SAI_SAI_BCR1_OUTDRIV_Msk = 0x2000
	// Bit OUTDRIV.
	SAI_SAI_BCR1_OUTDRIV = 0x2000
	// Position of SAIEN field.
	SAI_SAI_BCR1_SAIEN_Pos = 0x10
	// Bit mask of SAIEN field.
	SAI_SAI_BCR1_SAIEN_Msk = 0x10000
	// Bit SAIEN.
	SAI_SAI_BCR1_SAIEN = 0x10000
	// Position of DMAEN field.
	SAI_SAI_BCR1_DMAEN_Pos = 0x11
	// Bit mask of DMAEN field.
	SAI_SAI_BCR1_DMAEN_Msk = 0x20000
	// Bit DMAEN.
	SAI_SAI_BCR1_DMAEN = 0x20000
	// Position of NODIV field.
	SAI_SAI_BCR1_NODIV_Pos = 0x13
	// Bit mask of NODIV field.
	SAI_SAI_BCR1_NODIV_Msk = 0x80000
	// Bit NODIV.
	SAI_SAI_BCR1_NODIV = 0x80000
	// Position of MCKDIV field.
	SAI_SAI_BCR1_MCKDIV_Pos = 0x14
	// Bit mask of MCKDIV field.
	SAI_SAI_BCR1_MCKDIV_Msk = 0x3f00000
	// Position of OSR field.
	SAI_SAI_BCR1_OSR_Pos = 0x1a
	// Bit mask of OSR field.
	SAI_SAI_BCR1_OSR_Msk = 0x4000000
	// Bit OSR.
	SAI_SAI_BCR1_OSR = 0x4000000
	// Position of MCKEN field.
	SAI_SAI_BCR1_MCKEN_Pos = 0x1b
	// Bit mask of MCKEN field.
	SAI_SAI_BCR1_MCKEN_Msk = 0x8000000
	// Bit MCKEN.
	SAI_SAI_BCR1_MCKEN = 0x8000000

	// SAI_BCR2: Configuration register 2
	// Position of FTH field.
	SAI_SAI_BCR2_FTH_Pos = 0x0
	// Bit mask of FTH field.
	SAI_SAI_BCR2_FTH_Msk = 0x7
	// Position of FFLUSH field.
	SAI_SAI_BCR2_FFLUSH_Pos = 0x3
	// Bit mask of FFLUSH field.
	SAI_SAI_BCR2_FFLUSH_Msk = 0x8
	// Bit FFLUSH.
	SAI_SAI_BCR2_FFLUSH = 0x8
	// Position of TRIS field.
	SAI_SAI_BCR2_TRIS_Pos = 0x4
	// Bit mask of TRIS field.
	SAI_SAI_BCR2_TRIS_Msk = 0x10
	// Bit TRIS.
	SAI_SAI_BCR2_TRIS = 0x10
	// Position of MUTE field.
	SAI_SAI_BCR2_MUTE_Pos = 0x5
	// Bit mask of MUTE field.
	SAI_SAI_BCR2_MUTE_Msk = 0x20
	// Bit MUTE.
	SAI_SAI_BCR2_MUTE = 0x20
	// Position of MUTEVAL field.
	SAI_SAI_BCR2_MUTEVAL_Pos = 0x6
	// Bit mask of MUTEVAL field.
	SAI_SAI_BCR2_MUTEVAL_Msk = 0x40
	// Bit MUTEVAL.
	SAI_SAI_BCR2_MUTEVAL = 0x40
	// Position of MUTECNT field.
	SAI_SAI_BCR2_MUTECNT_Pos = 0x7
	// Bit mask of MUTECNT field.
	SAI_SAI_BCR2_MUTECNT_Msk = 0x1f80
	// Position of CPL field.
	SAI_SAI_BCR2_CPL_Pos = 0xd
	// Bit mask of CPL field.
	SAI_SAI_BCR2_CPL_Msk = 0x2000
	// Bit CPL.
	SAI_SAI_BCR2_CPL = 0x2000
	// Position of COMP field.
	SAI_SAI_BCR2_COMP_Pos = 0xe
	// Bit mask of COMP field.
	SAI_SAI_BCR2_COMP_Msk = 0xc000

	// SAI_BFRCR: This register has no meaning in and SPDIF audio protocol
	// Position of FRL field.
	SAI_SAI_BFRCR_FRL_Pos = 0x0
	// Bit mask of FRL field.
	SAI_SAI_BFRCR_FRL_Msk = 0xff
	// Position of FSALL field.
	SAI_SAI_BFRCR_FSALL_Pos = 0x8
	// Bit mask of FSALL field.
	SAI_SAI_BFRCR_FSALL_Msk = 0x7f00
	// Position of FSDEF field.
	SAI_SAI_BFRCR_FSDEF_Pos = 0x10
	// Bit mask of FSDEF field.
	SAI_SAI_BFRCR_FSDEF_Msk = 0x10000
	// Bit FSDEF.
	SAI_SAI_BFRCR_FSDEF = 0x10000
	// Position of FSPOL field.
	SAI_SAI_BFRCR_FSPOL_Pos = 0x11
	// Bit mask of FSPOL field.
	SAI_SAI_BFRCR_FSPOL_Msk = 0x20000
	// Bit FSPOL.
	SAI_SAI_BFRCR_FSPOL = 0x20000
	// Position of FSOFF field.
	SAI_SAI_BFRCR_FSOFF_Pos = 0x12
	// Bit mask of FSOFF field.
	SAI_SAI_BFRCR_FSOFF_Msk = 0x40000
	// Bit FSOFF.
	SAI_SAI_BFRCR_FSOFF = 0x40000

	// SAI_BSLOTR: This register has no meaning in and SPDIF audio protocol
	// Position of FBOFF field.
	SAI_SAI_BSLOTR_FBOFF_Pos = 0x0
	// Bit mask of FBOFF field.
	SAI_SAI_BSLOTR_FBOFF_Msk = 0x1f
	// Position of SLOTSZ field.
	SAI_SAI_BSLOTR_SLOTSZ_Pos = 0x6
	// Bit mask of SLOTSZ field.
	SAI_SAI_BSLOTR_SLOTSZ_Msk = 0xc0
	// Position of NBSLOT field.
	SAI_SAI_BSLOTR_NBSLOT_Pos = 0x8
	// Bit mask of NBSLOT field.
	SAI_SAI_BSLOTR_NBSLOT_Msk = 0xf00
	// Position of SLOTEN field.
	SAI_SAI_BSLOTR_SLOTEN_Pos = 0x10
	// Bit mask of SLOTEN field.
	SAI_SAI_BSLOTR_SLOTEN_Msk = 0xffff0000

	// SAI_BIM: Interrupt mask register
	// Position of OVRUDRIE field.
	SAI_SAI_BIM_OVRUDRIE_Pos = 0x0
	// Bit mask of OVRUDRIE field.
	SAI_SAI_BIM_OVRUDRIE_Msk = 0x1
	// Bit OVRUDRIE.
	SAI_SAI_BIM_OVRUDRIE = 0x1
	// Position of MUTEDETIE field.
	SAI_SAI_BIM_MUTEDETIE_Pos = 0x1
	// Bit mask of MUTEDETIE field.
	SAI_SAI_BIM_MUTEDETIE_Msk = 0x2
	// Bit MUTEDETIE.
	SAI_SAI_BIM_MUTEDETIE = 0x2
	// Position of WCKCFGIE field.
	SAI_SAI_BIM_WCKCFGIE_Pos = 0x2
	// Bit mask of WCKCFGIE field.
	SAI_SAI_BIM_WCKCFGIE_Msk = 0x4
	// Bit WCKCFGIE.
	SAI_SAI_BIM_WCKCFGIE = 0x4
	// Position of FREQIE field.
	SAI_SAI_BIM_FREQIE_Pos = 0x3
	// Bit mask of FREQIE field.
	SAI_SAI_BIM_FREQIE_Msk = 0x8
	// Bit FREQIE.
	SAI_SAI_BIM_FREQIE = 0x8
	// Position of CNRDYIE field.
	SAI_SAI_BIM_CNRDYIE_Pos = 0x4
	// Bit mask of CNRDYIE field.
	SAI_SAI_BIM_CNRDYIE_Msk = 0x10
	// Bit CNRDYIE.
	SAI_SAI_BIM_CNRDYIE = 0x10
	// Position of AFSDETIE field.
	SAI_SAI_BIM_AFSDETIE_Pos = 0x5
	// Bit mask of AFSDETIE field.
	SAI_SAI_BIM_AFSDETIE_Msk = 0x20
	// Bit AFSDETIE.
	SAI_SAI_BIM_AFSDETIE = 0x20
	// Position of LFSDETIE field.
	SAI_SAI_BIM_LFSDETIE_Pos = 0x6
	// Bit mask of LFSDETIE field.
	SAI_SAI_BIM_LFSDETIE_Msk = 0x40
	// Bit LFSDETIE.
	SAI_SAI_BIM_LFSDETIE = 0x40

	// SAI_BSR: Status register
	// Position of OVRUDR field.
	SAI_SAI_BSR_OVRUDR_Pos = 0x0
	// Bit mask of OVRUDR field.
	SAI_SAI_BSR_OVRUDR_Msk = 0x1
	// Bit OVRUDR.
	SAI_SAI_BSR_OVRUDR = 0x1
	// Position of MUTEDET field.
	SAI_SAI_BSR_MUTEDET_Pos = 0x1
	// Bit mask of MUTEDET field.
	SAI_SAI_BSR_MUTEDET_Msk = 0x2
	// Bit MUTEDET.
	SAI_SAI_BSR_MUTEDET = 0x2
	// Position of WCKCFG field.
	SAI_SAI_BSR_WCKCFG_Pos = 0x2
	// Bit mask of WCKCFG field.
	SAI_SAI_BSR_WCKCFG_Msk = 0x4
	// Bit WCKCFG.
	SAI_SAI_BSR_WCKCFG = 0x4
	// Position of FREQ field.
	SAI_SAI_BSR_FREQ_Pos = 0x3
	// Bit mask of FREQ field.
	SAI_SAI_BSR_FREQ_Msk = 0x8
	// Bit FREQ.
	SAI_SAI_BSR_FREQ = 0x8
	// Position of CNRDY field.
	SAI_SAI_BSR_CNRDY_Pos = 0x4
	// Bit mask of CNRDY field.
	SAI_SAI_BSR_CNRDY_Msk = 0x10
	// Bit CNRDY.
	SAI_SAI_BSR_CNRDY = 0x10
	// Position of AFSDET field.
	SAI_SAI_BSR_AFSDET_Pos = 0x5
	// Bit mask of AFSDET field.
	SAI_SAI_BSR_AFSDET_Msk = 0x20
	// Bit AFSDET.
	SAI_SAI_BSR_AFSDET = 0x20
	// Position of LFSDET field.
	SAI_SAI_BSR_LFSDET_Pos = 0x6
	// Bit mask of LFSDET field.
	SAI_SAI_BSR_LFSDET_Msk = 0x40
	// Bit LFSDET.
	SAI_SAI_BSR_LFSDET = 0x40
	// Position of FLVL field.
	SAI_SAI_BSR_FLVL_Pos = 0x10
	// Bit mask of FLVL field.
	SAI_SAI_BSR_FLVL_Msk = 0x70000

	// SAI_BCLRFR: Clear flag register
	// Position of COVRUDR field.
	SAI_SAI_BCLRFR_COVRUDR_Pos = 0x0
	// Bit mask of COVRUDR field.
	SAI_SAI_BCLRFR_COVRUDR_Msk = 0x1
	// Bit COVRUDR.
	SAI_SAI_BCLRFR_COVRUDR = 0x1
	// Position of CMUTEDET field.
	SAI_SAI_BCLRFR_CMUTEDET_Pos = 0x1
	// Bit mask of CMUTEDET field.
	SAI_SAI_BCLRFR_CMUTEDET_Msk = 0x2
	// Bit CMUTEDET.
	SAI_SAI_BCLRFR_CMUTEDET = 0x2
	// Position of CWCKCFG field.
	SAI_SAI_BCLRFR_CWCKCFG_Pos = 0x2
	// Bit mask of CWCKCFG field.
	SAI_SAI_BCLRFR_CWCKCFG_Msk = 0x4
	// Bit CWCKCFG.
	SAI_SAI_BCLRFR_CWCKCFG = 0x4
	// Position of CCNRDY field.
	SAI_SAI_BCLRFR_CCNRDY_Pos = 0x4
	// Bit mask of CCNRDY field.
	SAI_SAI_BCLRFR_CCNRDY_Msk = 0x10
	// Bit CCNRDY.
	SAI_SAI_BCLRFR_CCNRDY = 0x10
	// Position of CAFSDET field.
	SAI_SAI_BCLRFR_CAFSDET_Pos = 0x5
	// Bit mask of CAFSDET field.
	SAI_SAI_BCLRFR_CAFSDET_Msk = 0x20
	// Bit CAFSDET.
	SAI_SAI_BCLRFR_CAFSDET = 0x20
	// Position of CLFSDET field.
	SAI_SAI_BCLRFR_CLFSDET_Pos = 0x6
	// Bit mask of CLFSDET field.
	SAI_SAI_BCLRFR_CLFSDET_Msk = 0x40
	// Bit CLFSDET.
	SAI_SAI_BCLRFR_CLFSDET = 0x40

	// SAI_BDR: Data register
	// Position of DATA field.
	SAI_SAI_BDR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SAI_SAI_BDR_DATA_Msk = 0xffffffff

	// SAI_PDMCR: PDM control register
	// Position of PDMEN field.
	SAI_SAI_PDMCR_PDMEN_Pos = 0x0
	// Bit mask of PDMEN field.
	SAI_SAI_PDMCR_PDMEN_Msk = 0x1
	// Bit PDMEN.
	SAI_SAI_PDMCR_PDMEN = 0x1
	// Position of MICNBR field.
	SAI_SAI_PDMCR_MICNBR_Pos = 0x4
	// Bit mask of MICNBR field.
	SAI_SAI_PDMCR_MICNBR_Msk = 0x30
	// Position of CKEN1 field.
	SAI_SAI_PDMCR_CKEN1_Pos = 0x8
	// Bit mask of CKEN1 field.
	SAI_SAI_PDMCR_CKEN1_Msk = 0x100
	// Bit CKEN1.
	SAI_SAI_PDMCR_CKEN1 = 0x100
	// Position of CKEN2 field.
	SAI_SAI_PDMCR_CKEN2_Pos = 0x9
	// Bit mask of CKEN2 field.
	SAI_SAI_PDMCR_CKEN2_Msk = 0x200
	// Bit CKEN2.
	SAI_SAI_PDMCR_CKEN2 = 0x200
	// Position of CKEN3 field.
	SAI_SAI_PDMCR_CKEN3_Pos = 0xa
	// Bit mask of CKEN3 field.
	SAI_SAI_PDMCR_CKEN3_Msk = 0x400
	// Bit CKEN3.
	SAI_SAI_PDMCR_CKEN3 = 0x400
	// Position of CKEN4 field.
	SAI_SAI_PDMCR_CKEN4_Pos = 0xb
	// Bit mask of CKEN4 field.
	SAI_SAI_PDMCR_CKEN4_Msk = 0x800
	// Bit CKEN4.
	SAI_SAI_PDMCR_CKEN4 = 0x800

	// SAI_PDMDLY: PDM delay register
	// Position of DLYM1L field.
	SAI_SAI_PDMDLY_DLYM1L_Pos = 0x0
	// Bit mask of DLYM1L field.
	SAI_SAI_PDMDLY_DLYM1L_Msk = 0x7
	// Position of DLYM1R field.
	SAI_SAI_PDMDLY_DLYM1R_Pos = 0x4
	// Bit mask of DLYM1R field.
	SAI_SAI_PDMDLY_DLYM1R_Msk = 0x70
	// Position of DLYM2L field.
	SAI_SAI_PDMDLY_DLYM2L_Pos = 0x8
	// Bit mask of DLYM2L field.
	SAI_SAI_PDMDLY_DLYM2L_Msk = 0x700
	// Position of DLYM2R field.
	SAI_SAI_PDMDLY_DLYM2R_Pos = 0xc
	// Bit mask of DLYM2R field.
	SAI_SAI_PDMDLY_DLYM2R_Msk = 0x7000
	// Position of DLYM3L field.
	SAI_SAI_PDMDLY_DLYM3L_Pos = 0x10
	// Bit mask of DLYM3L field.
	SAI_SAI_PDMDLY_DLYM3L_Msk = 0x70000
	// Position of DLYM3R field.
	SAI_SAI_PDMDLY_DLYM3R_Pos = 0x14
	// Bit mask of DLYM3R field.
	SAI_SAI_PDMDLY_DLYM3R_Msk = 0x700000
	// Position of DLYM4L field.
	SAI_SAI_PDMDLY_DLYM4L_Pos = 0x18
	// Bit mask of DLYM4L field.
	SAI_SAI_PDMDLY_DLYM4L_Msk = 0x7000000
	// Position of DLYM4R field.
	SAI_SAI_PDMDLY_DLYM4R_Pos = 0x1c
	// Bit mask of DLYM4R field.
	SAI_SAI_PDMDLY_DLYM4R_Msk = 0x70000000

	// SAI_HWCFGR: SAI hardware configuration register
	// Position of FIFO_SIZE field.
	SAI_SAI_HWCFGR_FIFO_SIZE_Pos = 0x0
	// Bit mask of FIFO_SIZE field.
	SAI_SAI_HWCFGR_FIFO_SIZE_Msk = 0xff
	// Position of SPDIF_PDM field.
	SAI_SAI_HWCFGR_SPDIF_PDM_Pos = 0x8
	// Bit mask of SPDIF_PDM field.
	SAI_SAI_HWCFGR_SPDIF_PDM_Msk = 0xf00
	// Position of OPTION_REGOUT field.
	SAI_SAI_HWCFGR_OPTION_REGOUT_Pos = 0xc
	// Bit mask of OPTION_REGOUT field.
	SAI_SAI_HWCFGR_OPTION_REGOUT_Msk = 0xff000

	// SAI_VERR: SAI version register
	// Position of MINREV field.
	SAI_SAI_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	SAI_SAI_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	SAI_SAI_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	SAI_SAI_VERR_MAJREV_Msk = 0xf0

	// SAI_IPIDR: SAI identification register
	// Position of ID field.
	SAI_SAI_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	SAI_SAI_IPIDR_ID_Msk = 0xffffffff

	// SAI_SIDR: SAI size identification register
	// Position of SID field.
	SAI_SAI_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	SAI_SAI_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for SDMMC1: SDMMC1
const (
	// SDMMC_POWER: SDMMC power control register
	// Position of PWRCTRL field.
	SDMMC2_SDMMC_POWER_PWRCTRL_Pos = 0x0
	// Bit mask of PWRCTRL field.
	SDMMC2_SDMMC_POWER_PWRCTRL_Msk = 0x3
	// Position of VSWITCH field.
	SDMMC2_SDMMC_POWER_VSWITCH_Pos = 0x2
	// Bit mask of VSWITCH field.
	SDMMC2_SDMMC_POWER_VSWITCH_Msk = 0x4
	// Bit VSWITCH.
	SDMMC2_SDMMC_POWER_VSWITCH = 0x4
	// Position of VSWITCHEN field.
	SDMMC2_SDMMC_POWER_VSWITCHEN_Pos = 0x3
	// Bit mask of VSWITCHEN field.
	SDMMC2_SDMMC_POWER_VSWITCHEN_Msk = 0x8
	// Bit VSWITCHEN.
	SDMMC2_SDMMC_POWER_VSWITCHEN = 0x8
	// Position of DIRPOL field.
	SDMMC2_SDMMC_POWER_DIRPOL_Pos = 0x4
	// Bit mask of DIRPOL field.
	SDMMC2_SDMMC_POWER_DIRPOL_Msk = 0x10
	// Bit DIRPOL.
	SDMMC2_SDMMC_POWER_DIRPOL = 0x10

	// SDMMC_CLKCR: The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width.
	// Position of CLKDIV field.
	SDMMC2_SDMMC_CLKCR_CLKDIV_Pos = 0x0
	// Bit mask of CLKDIV field.
	SDMMC2_SDMMC_CLKCR_CLKDIV_Msk = 0x3ff
	// Position of PWRSAV field.
	SDMMC2_SDMMC_CLKCR_PWRSAV_Pos = 0xc
	// Bit mask of PWRSAV field.
	SDMMC2_SDMMC_CLKCR_PWRSAV_Msk = 0x1000
	// Bit PWRSAV.
	SDMMC2_SDMMC_CLKCR_PWRSAV = 0x1000
	// Position of WIDBUS field.
	SDMMC2_SDMMC_CLKCR_WIDBUS_Pos = 0xe
	// Bit mask of WIDBUS field.
	SDMMC2_SDMMC_CLKCR_WIDBUS_Msk = 0xc000
	// Position of NEGEDGE field.
	SDMMC2_SDMMC_CLKCR_NEGEDGE_Pos = 0x10
	// Bit mask of NEGEDGE field.
	SDMMC2_SDMMC_CLKCR_NEGEDGE_Msk = 0x10000
	// Bit NEGEDGE.
	SDMMC2_SDMMC_CLKCR_NEGEDGE = 0x10000
	// Position of HWFC_EN field.
	SDMMC2_SDMMC_CLKCR_HWFC_EN_Pos = 0x11
	// Bit mask of HWFC_EN field.
	SDMMC2_SDMMC_CLKCR_HWFC_EN_Msk = 0x20000
	// Bit HWFC_EN.
	SDMMC2_SDMMC_CLKCR_HWFC_EN = 0x20000
	// Position of DDR field.
	SDMMC2_SDMMC_CLKCR_DDR_Pos = 0x12
	// Bit mask of DDR field.
	SDMMC2_SDMMC_CLKCR_DDR_Msk = 0x40000
	// Bit DDR.
	SDMMC2_SDMMC_CLKCR_DDR = 0x40000
	// Position of BUSSPEED field.
	SDMMC2_SDMMC_CLKCR_BUSSPEED_Pos = 0x13
	// Bit mask of BUSSPEED field.
	SDMMC2_SDMMC_CLKCR_BUSSPEED_Msk = 0x80000
	// Bit BUSSPEED.
	SDMMC2_SDMMC_CLKCR_BUSSPEED = 0x80000
	// Position of SELCLKRX field.
	SDMMC2_SDMMC_CLKCR_SELCLKRX_Pos = 0x14
	// Bit mask of SELCLKRX field.
	SDMMC2_SDMMC_CLKCR_SELCLKRX_Msk = 0x300000

	// SDMMC_ARGR: The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.
	// Position of CMDARG field.
	SDMMC2_SDMMC_ARGR_CMDARG_Pos = 0x0
	// Bit mask of CMDARG field.
	SDMMC2_SDMMC_ARGR_CMDARG_Msk = 0xffffffff

	// SDMMC_CMDR: The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
	// Position of CMDINDEX field.
	SDMMC2_SDMMC_CMDR_CMDINDEX_Pos = 0x0
	// Bit mask of CMDINDEX field.
	SDMMC2_SDMMC_CMDR_CMDINDEX_Msk = 0x3f
	// Position of CMDTRANS field.
	SDMMC2_SDMMC_CMDR_CMDTRANS_Pos = 0x6
	// Bit mask of CMDTRANS field.
	SDMMC2_SDMMC_CMDR_CMDTRANS_Msk = 0x40
	// Bit CMDTRANS.
	SDMMC2_SDMMC_CMDR_CMDTRANS = 0x40
	// Position of CMDSTOP field.
	SDMMC2_SDMMC_CMDR_CMDSTOP_Pos = 0x7
	// Bit mask of CMDSTOP field.
	SDMMC2_SDMMC_CMDR_CMDSTOP_Msk = 0x80
	// Bit CMDSTOP.
	SDMMC2_SDMMC_CMDR_CMDSTOP = 0x80
	// Position of WAITRESP field.
	SDMMC2_SDMMC_CMDR_WAITRESP_Pos = 0x8
	// Bit mask of WAITRESP field.
	SDMMC2_SDMMC_CMDR_WAITRESP_Msk = 0x300
	// Position of WAITINT field.
	SDMMC2_SDMMC_CMDR_WAITINT_Pos = 0xa
	// Bit mask of WAITINT field.
	SDMMC2_SDMMC_CMDR_WAITINT_Msk = 0x400
	// Bit WAITINT.
	SDMMC2_SDMMC_CMDR_WAITINT = 0x400
	// Position of WAITPEND field.
	SDMMC2_SDMMC_CMDR_WAITPEND_Pos = 0xb
	// Bit mask of WAITPEND field.
	SDMMC2_SDMMC_CMDR_WAITPEND_Msk = 0x800
	// Bit WAITPEND.
	SDMMC2_SDMMC_CMDR_WAITPEND = 0x800
	// Position of CPSMEN field.
	SDMMC2_SDMMC_CMDR_CPSMEN_Pos = 0xc
	// Bit mask of CPSMEN field.
	SDMMC2_SDMMC_CMDR_CPSMEN_Msk = 0x1000
	// Bit CPSMEN.
	SDMMC2_SDMMC_CMDR_CPSMEN = 0x1000
	// Position of DTHOLD field.
	SDMMC2_SDMMC_CMDR_DTHOLD_Pos = 0xd
	// Bit mask of DTHOLD field.
	SDMMC2_SDMMC_CMDR_DTHOLD_Msk = 0x2000
	// Bit DTHOLD.
	SDMMC2_SDMMC_CMDR_DTHOLD = 0x2000
	// Position of BOOTMODE field.
	SDMMC2_SDMMC_CMDR_BOOTMODE_Pos = 0xe
	// Bit mask of BOOTMODE field.
	SDMMC2_SDMMC_CMDR_BOOTMODE_Msk = 0x4000
	// Bit BOOTMODE.
	SDMMC2_SDMMC_CMDR_BOOTMODE = 0x4000
	// Position of BOOTEN field.
	SDMMC2_SDMMC_CMDR_BOOTEN_Pos = 0xf
	// Bit mask of BOOTEN field.
	SDMMC2_SDMMC_CMDR_BOOTEN_Msk = 0x8000
	// Bit BOOTEN.
	SDMMC2_SDMMC_CMDR_BOOTEN = 0x8000
	// Position of CMDSUSPEND field.
	SDMMC2_SDMMC_CMDR_CMDSUSPEND_Pos = 0x10
	// Bit mask of CMDSUSPEND field.
	SDMMC2_SDMMC_CMDR_CMDSUSPEND_Msk = 0x10000
	// Bit CMDSUSPEND.
	SDMMC2_SDMMC_CMDR_CMDSUSPEND = 0x10000

	// SDMMC_RESPCMDR: The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).
	// Position of RESPCMD field.
	SDMMC2_SDMMC_RESPCMDR_RESPCMD_Pos = 0x0
	// Bit mask of RESPCMD field.
	SDMMC2_SDMMC_RESPCMDR_RESPCMD_Msk = 0x3f

	// SDMMC_RESP1R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS1 field.
	SDMMC2_SDMMC_RESP1R_CARDSTATUS1_Pos = 0x0
	// Bit mask of CARDSTATUS1 field.
	SDMMC2_SDMMC_RESP1R_CARDSTATUS1_Msk = 0xffffffff

	// SDMMC_RESP2R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS2 field.
	SDMMC2_SDMMC_RESP2R_CARDSTATUS2_Pos = 0x0
	// Bit mask of CARDSTATUS2 field.
	SDMMC2_SDMMC_RESP2R_CARDSTATUS2_Msk = 0xffffffff

	// SDMMC_RESP3R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS3 field.
	SDMMC2_SDMMC_RESP3R_CARDSTATUS3_Pos = 0x0
	// Bit mask of CARDSTATUS3 field.
	SDMMC2_SDMMC_RESP3R_CARDSTATUS3_Msk = 0xffffffff

	// SDMMC_RESP4R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS4 field.
	SDMMC2_SDMMC_RESP4R_CARDSTATUS4_Pos = 0x0
	// Bit mask of CARDSTATUS4 field.
	SDMMC2_SDMMC_RESP4R_CARDSTATUS4_Msk = 0xffffffff

	// SDMMC_DTIMER: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
	// Position of DATATIME field.
	SDMMC2_SDMMC_DTIMER_DATATIME_Pos = 0x0
	// Bit mask of DATATIME field.
	SDMMC2_SDMMC_DTIMER_DATATIME_Msk = 0xffffffff

	// SDMMC_DLENR: The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.
	// Position of DATALENGTH field.
	SDMMC2_SDMMC_DLENR_DATALENGTH_Pos = 0x0
	// Bit mask of DATALENGTH field.
	SDMMC2_SDMMC_DLENR_DATALENGTH_Msk = 0x1ffffff

	// SDMMC_DCTRL: The SDMMC_DCTRL register control the data path state machine (DPSM).
	// Position of DTEN field.
	SDMMC2_SDMMC_DCTRL_DTEN_Pos = 0x0
	// Bit mask of DTEN field.
	SDMMC2_SDMMC_DCTRL_DTEN_Msk = 0x1
	// Bit DTEN.
	SDMMC2_SDMMC_DCTRL_DTEN = 0x1
	// Position of DTDIR field.
	SDMMC2_SDMMC_DCTRL_DTDIR_Pos = 0x1
	// Bit mask of DTDIR field.
	SDMMC2_SDMMC_DCTRL_DTDIR_Msk = 0x2
	// Bit DTDIR.
	SDMMC2_SDMMC_DCTRL_DTDIR = 0x2
	// Position of DTMODE field.
	SDMMC2_SDMMC_DCTRL_DTMODE_Pos = 0x2
	// Bit mask of DTMODE field.
	SDMMC2_SDMMC_DCTRL_DTMODE_Msk = 0xc
	// Position of DBLOCKSIZE field.
	SDMMC2_SDMMC_DCTRL_DBLOCKSIZE_Pos = 0x4
	// Bit mask of DBLOCKSIZE field.
	SDMMC2_SDMMC_DCTRL_DBLOCKSIZE_Msk = 0xf0
	// Position of RWSTART field.
	SDMMC2_SDMMC_DCTRL_RWSTART_Pos = 0x8
	// Bit mask of RWSTART field.
	SDMMC2_SDMMC_DCTRL_RWSTART_Msk = 0x100
	// Bit RWSTART.
	SDMMC2_SDMMC_DCTRL_RWSTART = 0x100
	// Position of RWSTOP field.
	SDMMC2_SDMMC_DCTRL_RWSTOP_Pos = 0x9
	// Bit mask of RWSTOP field.
	SDMMC2_SDMMC_DCTRL_RWSTOP_Msk = 0x200
	// Bit RWSTOP.
	SDMMC2_SDMMC_DCTRL_RWSTOP = 0x200
	// Position of RWMOD field.
	SDMMC2_SDMMC_DCTRL_RWMOD_Pos = 0xa
	// Bit mask of RWMOD field.
	SDMMC2_SDMMC_DCTRL_RWMOD_Msk = 0x400
	// Bit RWMOD.
	SDMMC2_SDMMC_DCTRL_RWMOD = 0x400
	// Position of SDIOEN field.
	SDMMC2_SDMMC_DCTRL_SDIOEN_Pos = 0xb
	// Bit mask of SDIOEN field.
	SDMMC2_SDMMC_DCTRL_SDIOEN_Msk = 0x800
	// Bit SDIOEN.
	SDMMC2_SDMMC_DCTRL_SDIOEN = 0x800
	// Position of BOOTACKEN field.
	SDMMC2_SDMMC_DCTRL_BOOTACKEN_Pos = 0xc
	// Bit mask of BOOTACKEN field.
	SDMMC2_SDMMC_DCTRL_BOOTACKEN_Msk = 0x1000
	// Bit BOOTACKEN.
	SDMMC2_SDMMC_DCTRL_BOOTACKEN = 0x1000
	// Position of FIFORST field.
	SDMMC2_SDMMC_DCTRL_FIFORST_Pos = 0xd
	// Bit mask of FIFORST field.
	SDMMC2_SDMMC_DCTRL_FIFORST_Msk = 0x2000
	// Bit FIFORST.
	SDMMC2_SDMMC_DCTRL_FIFORST = 0x2000

	// SDMMC_DCNTR: The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.
	// Position of DATACOUNT field.
	SDMMC2_SDMMC_DCNTR_DATACOUNT_Pos = 0x0
	// Bit mask of DATACOUNT field.
	SDMMC2_SDMMC_DCNTR_DATACOUNT_Msk = 0x1ffffff

	// SDMMC_STAR: The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)
	// Position of CCRCFAIL field.
	SDMMC2_SDMMC_STAR_CCRCFAIL_Pos = 0x0
	// Bit mask of CCRCFAIL field.
	SDMMC2_SDMMC_STAR_CCRCFAIL_Msk = 0x1
	// Bit CCRCFAIL.
	SDMMC2_SDMMC_STAR_CCRCFAIL = 0x1
	// Position of DCRCFAIL field.
	SDMMC2_SDMMC_STAR_DCRCFAIL_Pos = 0x1
	// Bit mask of DCRCFAIL field.
	SDMMC2_SDMMC_STAR_DCRCFAIL_Msk = 0x2
	// Bit DCRCFAIL.
	SDMMC2_SDMMC_STAR_DCRCFAIL = 0x2
	// Position of CTIMEOUT field.
	SDMMC2_SDMMC_STAR_CTIMEOUT_Pos = 0x2
	// Bit mask of CTIMEOUT field.
	SDMMC2_SDMMC_STAR_CTIMEOUT_Msk = 0x4
	// Bit CTIMEOUT.
	SDMMC2_SDMMC_STAR_CTIMEOUT = 0x4
	// Position of DTIMEOUT field.
	SDMMC2_SDMMC_STAR_DTIMEOUT_Pos = 0x3
	// Bit mask of DTIMEOUT field.
	SDMMC2_SDMMC_STAR_DTIMEOUT_Msk = 0x8
	// Bit DTIMEOUT.
	SDMMC2_SDMMC_STAR_DTIMEOUT = 0x8
	// Position of TXUNDERR field.
	SDMMC2_SDMMC_STAR_TXUNDERR_Pos = 0x4
	// Bit mask of TXUNDERR field.
	SDMMC2_SDMMC_STAR_TXUNDERR_Msk = 0x10
	// Bit TXUNDERR.
	SDMMC2_SDMMC_STAR_TXUNDERR = 0x10
	// Position of RXOVERR field.
	SDMMC2_SDMMC_STAR_RXOVERR_Pos = 0x5
	// Bit mask of RXOVERR field.
	SDMMC2_SDMMC_STAR_RXOVERR_Msk = 0x20
	// Bit RXOVERR.
	SDMMC2_SDMMC_STAR_RXOVERR = 0x20
	// Position of CMDREND field.
	SDMMC2_SDMMC_STAR_CMDREND_Pos = 0x6
	// Bit mask of CMDREND field.
	SDMMC2_SDMMC_STAR_CMDREND_Msk = 0x40
	// Bit CMDREND.
	SDMMC2_SDMMC_STAR_CMDREND = 0x40
	// Position of CMDSENT field.
	SDMMC2_SDMMC_STAR_CMDSENT_Pos = 0x7
	// Bit mask of CMDSENT field.
	SDMMC2_SDMMC_STAR_CMDSENT_Msk = 0x80
	// Bit CMDSENT.
	SDMMC2_SDMMC_STAR_CMDSENT = 0x80
	// Position of DATAEND field.
	SDMMC2_SDMMC_STAR_DATAEND_Pos = 0x8
	// Bit mask of DATAEND field.
	SDMMC2_SDMMC_STAR_DATAEND_Msk = 0x100
	// Bit DATAEND.
	SDMMC2_SDMMC_STAR_DATAEND = 0x100
	// Position of DHOLD field.
	SDMMC2_SDMMC_STAR_DHOLD_Pos = 0x9
	// Bit mask of DHOLD field.
	SDMMC2_SDMMC_STAR_DHOLD_Msk = 0x200
	// Bit DHOLD.
	SDMMC2_SDMMC_STAR_DHOLD = 0x200
	// Position of DBCKEND field.
	SDMMC2_SDMMC_STAR_DBCKEND_Pos = 0xa
	// Bit mask of DBCKEND field.
	SDMMC2_SDMMC_STAR_DBCKEND_Msk = 0x400
	// Bit DBCKEND.
	SDMMC2_SDMMC_STAR_DBCKEND = 0x400
	// Position of DABORT field.
	SDMMC2_SDMMC_STAR_DABORT_Pos = 0xb
	// Bit mask of DABORT field.
	SDMMC2_SDMMC_STAR_DABORT_Msk = 0x800
	// Bit DABORT.
	SDMMC2_SDMMC_STAR_DABORT = 0x800
	// Position of DPSMACT field.
	SDMMC2_SDMMC_STAR_DPSMACT_Pos = 0xc
	// Bit mask of DPSMACT field.
	SDMMC2_SDMMC_STAR_DPSMACT_Msk = 0x1000
	// Bit DPSMACT.
	SDMMC2_SDMMC_STAR_DPSMACT = 0x1000
	// Position of CPSMACT field.
	SDMMC2_SDMMC_STAR_CPSMACT_Pos = 0xd
	// Bit mask of CPSMACT field.
	SDMMC2_SDMMC_STAR_CPSMACT_Msk = 0x2000
	// Bit CPSMACT.
	SDMMC2_SDMMC_STAR_CPSMACT = 0x2000
	// Position of TXFIFOHE field.
	SDMMC2_SDMMC_STAR_TXFIFOHE_Pos = 0xe
	// Bit mask of TXFIFOHE field.
	SDMMC2_SDMMC_STAR_TXFIFOHE_Msk = 0x4000
	// Bit TXFIFOHE.
	SDMMC2_SDMMC_STAR_TXFIFOHE = 0x4000
	// Position of RXFIFOHF field.
	SDMMC2_SDMMC_STAR_RXFIFOHF_Pos = 0xf
	// Bit mask of RXFIFOHF field.
	SDMMC2_SDMMC_STAR_RXFIFOHF_Msk = 0x8000
	// Bit RXFIFOHF.
	SDMMC2_SDMMC_STAR_RXFIFOHF = 0x8000
	// Position of TXFIFOF field.
	SDMMC2_SDMMC_STAR_TXFIFOF_Pos = 0x10
	// Bit mask of TXFIFOF field.
	SDMMC2_SDMMC_STAR_TXFIFOF_Msk = 0x10000
	// Bit TXFIFOF.
	SDMMC2_SDMMC_STAR_TXFIFOF = 0x10000
	// Position of RXFIFOF field.
	SDMMC2_SDMMC_STAR_RXFIFOF_Pos = 0x11
	// Bit mask of RXFIFOF field.
	SDMMC2_SDMMC_STAR_RXFIFOF_Msk = 0x20000
	// Bit RXFIFOF.
	SDMMC2_SDMMC_STAR_RXFIFOF = 0x20000
	// Position of TXFIFOE field.
	SDMMC2_SDMMC_STAR_TXFIFOE_Pos = 0x12
	// Bit mask of TXFIFOE field.
	SDMMC2_SDMMC_STAR_TXFIFOE_Msk = 0x40000
	// Bit TXFIFOE.
	SDMMC2_SDMMC_STAR_TXFIFOE = 0x40000
	// Position of RXFIFOE field.
	SDMMC2_SDMMC_STAR_RXFIFOE_Pos = 0x13
	// Bit mask of RXFIFOE field.
	SDMMC2_SDMMC_STAR_RXFIFOE_Msk = 0x80000
	// Bit RXFIFOE.
	SDMMC2_SDMMC_STAR_RXFIFOE = 0x80000
	// Position of BUSYD0 field.
	SDMMC2_SDMMC_STAR_BUSYD0_Pos = 0x14
	// Bit mask of BUSYD0 field.
	SDMMC2_SDMMC_STAR_BUSYD0_Msk = 0x100000
	// Bit BUSYD0.
	SDMMC2_SDMMC_STAR_BUSYD0 = 0x100000
	// Position of BUSYD0END field.
	SDMMC2_SDMMC_STAR_BUSYD0END_Pos = 0x15
	// Bit mask of BUSYD0END field.
	SDMMC2_SDMMC_STAR_BUSYD0END_Msk = 0x200000
	// Bit BUSYD0END.
	SDMMC2_SDMMC_STAR_BUSYD0END = 0x200000
	// Position of SDIOIT field.
	SDMMC2_SDMMC_STAR_SDIOIT_Pos = 0x16
	// Bit mask of SDIOIT field.
	SDMMC2_SDMMC_STAR_SDIOIT_Msk = 0x400000
	// Bit SDIOIT.
	SDMMC2_SDMMC_STAR_SDIOIT = 0x400000
	// Position of ACKFAIL field.
	SDMMC2_SDMMC_STAR_ACKFAIL_Pos = 0x17
	// Bit mask of ACKFAIL field.
	SDMMC2_SDMMC_STAR_ACKFAIL_Msk = 0x800000
	// Bit ACKFAIL.
	SDMMC2_SDMMC_STAR_ACKFAIL = 0x800000
	// Position of ACKTIMEOUT field.
	SDMMC2_SDMMC_STAR_ACKTIMEOUT_Pos = 0x18
	// Bit mask of ACKTIMEOUT field.
	SDMMC2_SDMMC_STAR_ACKTIMEOUT_Msk = 0x1000000
	// Bit ACKTIMEOUT.
	SDMMC2_SDMMC_STAR_ACKTIMEOUT = 0x1000000
	// Position of VSWEND field.
	SDMMC2_SDMMC_STAR_VSWEND_Pos = 0x19
	// Bit mask of VSWEND field.
	SDMMC2_SDMMC_STAR_VSWEND_Msk = 0x2000000
	// Bit VSWEND.
	SDMMC2_SDMMC_STAR_VSWEND = 0x2000000
	// Position of CKSTOP field.
	SDMMC2_SDMMC_STAR_CKSTOP_Pos = 0x1a
	// Bit mask of CKSTOP field.
	SDMMC2_SDMMC_STAR_CKSTOP_Msk = 0x4000000
	// Bit CKSTOP.
	SDMMC2_SDMMC_STAR_CKSTOP = 0x4000000
	// Position of IDMATE field.
	SDMMC2_SDMMC_STAR_IDMATE_Pos = 0x1b
	// Bit mask of IDMATE field.
	SDMMC2_SDMMC_STAR_IDMATE_Msk = 0x8000000
	// Bit IDMATE.
	SDMMC2_SDMMC_STAR_IDMATE = 0x8000000
	// Position of IDMABTC field.
	SDMMC2_SDMMC_STAR_IDMABTC_Pos = 0x1c
	// Bit mask of IDMABTC field.
	SDMMC2_SDMMC_STAR_IDMABTC_Msk = 0x10000000
	// Bit IDMABTC.
	SDMMC2_SDMMC_STAR_IDMABTC = 0x10000000

	// SDMMC_ICR: The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.
	// Position of CCRCFAILC field.
	SDMMC2_SDMMC_ICR_CCRCFAILC_Pos = 0x0
	// Bit mask of CCRCFAILC field.
	SDMMC2_SDMMC_ICR_CCRCFAILC_Msk = 0x1
	// Bit CCRCFAILC.
	SDMMC2_SDMMC_ICR_CCRCFAILC = 0x1
	// Position of DCRCFAILC field.
	SDMMC2_SDMMC_ICR_DCRCFAILC_Pos = 0x1
	// Bit mask of DCRCFAILC field.
	SDMMC2_SDMMC_ICR_DCRCFAILC_Msk = 0x2
	// Bit DCRCFAILC.
	SDMMC2_SDMMC_ICR_DCRCFAILC = 0x2
	// Position of CTIMEOUTC field.
	SDMMC2_SDMMC_ICR_CTIMEOUTC_Pos = 0x2
	// Bit mask of CTIMEOUTC field.
	SDMMC2_SDMMC_ICR_CTIMEOUTC_Msk = 0x4
	// Bit CTIMEOUTC.
	SDMMC2_SDMMC_ICR_CTIMEOUTC = 0x4
	// Position of DTIMEOUTC field.
	SDMMC2_SDMMC_ICR_DTIMEOUTC_Pos = 0x3
	// Bit mask of DTIMEOUTC field.
	SDMMC2_SDMMC_ICR_DTIMEOUTC_Msk = 0x8
	// Bit DTIMEOUTC.
	SDMMC2_SDMMC_ICR_DTIMEOUTC = 0x8
	// Position of TXUNDERRC field.
	SDMMC2_SDMMC_ICR_TXUNDERRC_Pos = 0x4
	// Bit mask of TXUNDERRC field.
	SDMMC2_SDMMC_ICR_TXUNDERRC_Msk = 0x10
	// Bit TXUNDERRC.
	SDMMC2_SDMMC_ICR_TXUNDERRC = 0x10
	// Position of RXOVERRC field.
	SDMMC2_SDMMC_ICR_RXOVERRC_Pos = 0x5
	// Bit mask of RXOVERRC field.
	SDMMC2_SDMMC_ICR_RXOVERRC_Msk = 0x20
	// Bit RXOVERRC.
	SDMMC2_SDMMC_ICR_RXOVERRC = 0x20
	// Position of CMDRENDC field.
	SDMMC2_SDMMC_ICR_CMDRENDC_Pos = 0x6
	// Bit mask of CMDRENDC field.
	SDMMC2_SDMMC_ICR_CMDRENDC_Msk = 0x40
	// Bit CMDRENDC.
	SDMMC2_SDMMC_ICR_CMDRENDC = 0x40
	// Position of CMDSENTC field.
	SDMMC2_SDMMC_ICR_CMDSENTC_Pos = 0x7
	// Bit mask of CMDSENTC field.
	SDMMC2_SDMMC_ICR_CMDSENTC_Msk = 0x80
	// Bit CMDSENTC.
	SDMMC2_SDMMC_ICR_CMDSENTC = 0x80
	// Position of DATAENDC field.
	SDMMC2_SDMMC_ICR_DATAENDC_Pos = 0x8
	// Bit mask of DATAENDC field.
	SDMMC2_SDMMC_ICR_DATAENDC_Msk = 0x100
	// Bit DATAENDC.
	SDMMC2_SDMMC_ICR_DATAENDC = 0x100
	// Position of DHOLDC field.
	SDMMC2_SDMMC_ICR_DHOLDC_Pos = 0x9
	// Bit mask of DHOLDC field.
	SDMMC2_SDMMC_ICR_DHOLDC_Msk = 0x200
	// Bit DHOLDC.
	SDMMC2_SDMMC_ICR_DHOLDC = 0x200
	// Position of DBCKENDC field.
	SDMMC2_SDMMC_ICR_DBCKENDC_Pos = 0xa
	// Bit mask of DBCKENDC field.
	SDMMC2_SDMMC_ICR_DBCKENDC_Msk = 0x400
	// Bit DBCKENDC.
	SDMMC2_SDMMC_ICR_DBCKENDC = 0x400
	// Position of DABORTC field.
	SDMMC2_SDMMC_ICR_DABORTC_Pos = 0xb
	// Bit mask of DABORTC field.
	SDMMC2_SDMMC_ICR_DABORTC_Msk = 0x800
	// Bit DABORTC.
	SDMMC2_SDMMC_ICR_DABORTC = 0x800
	// Position of BUSYD0ENDC field.
	SDMMC2_SDMMC_ICR_BUSYD0ENDC_Pos = 0x15
	// Bit mask of BUSYD0ENDC field.
	SDMMC2_SDMMC_ICR_BUSYD0ENDC_Msk = 0x200000
	// Bit BUSYD0ENDC.
	SDMMC2_SDMMC_ICR_BUSYD0ENDC = 0x200000
	// Position of SDIOITC field.
	SDMMC2_SDMMC_ICR_SDIOITC_Pos = 0x16
	// Bit mask of SDIOITC field.
	SDMMC2_SDMMC_ICR_SDIOITC_Msk = 0x400000
	// Bit SDIOITC.
	SDMMC2_SDMMC_ICR_SDIOITC = 0x400000
	// Position of ACKFAILC field.
	SDMMC2_SDMMC_ICR_ACKFAILC_Pos = 0x17
	// Bit mask of ACKFAILC field.
	SDMMC2_SDMMC_ICR_ACKFAILC_Msk = 0x800000
	// Bit ACKFAILC.
	SDMMC2_SDMMC_ICR_ACKFAILC = 0x800000
	// Position of ACKTIMEOUTC field.
	SDMMC2_SDMMC_ICR_ACKTIMEOUTC_Pos = 0x18
	// Bit mask of ACKTIMEOUTC field.
	SDMMC2_SDMMC_ICR_ACKTIMEOUTC_Msk = 0x1000000
	// Bit ACKTIMEOUTC.
	SDMMC2_SDMMC_ICR_ACKTIMEOUTC = 0x1000000
	// Position of VSWENDC field.
	SDMMC2_SDMMC_ICR_VSWENDC_Pos = 0x19
	// Bit mask of VSWENDC field.
	SDMMC2_SDMMC_ICR_VSWENDC_Msk = 0x2000000
	// Bit VSWENDC.
	SDMMC2_SDMMC_ICR_VSWENDC = 0x2000000
	// Position of CKSTOPC field.
	SDMMC2_SDMMC_ICR_CKSTOPC_Pos = 0x1a
	// Bit mask of CKSTOPC field.
	SDMMC2_SDMMC_ICR_CKSTOPC_Msk = 0x4000000
	// Bit CKSTOPC.
	SDMMC2_SDMMC_ICR_CKSTOPC = 0x4000000
	// Position of IDMATEC field.
	SDMMC2_SDMMC_ICR_IDMATEC_Pos = 0x1b
	// Bit mask of IDMATEC field.
	SDMMC2_SDMMC_ICR_IDMATEC_Msk = 0x8000000
	// Bit IDMATEC.
	SDMMC2_SDMMC_ICR_IDMATEC = 0x8000000
	// Position of IDMABTCC field.
	SDMMC2_SDMMC_ICR_IDMABTCC_Pos = 0x1c
	// Bit mask of IDMABTCC field.
	SDMMC2_SDMMC_ICR_IDMABTCC_Msk = 0x10000000
	// Bit IDMABTCC.
	SDMMC2_SDMMC_ICR_IDMABTCC = 0x10000000

	// SDMMC_MASKR: The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
	// Position of CCRCFAILIE field.
	SDMMC2_SDMMC_MASKR_CCRCFAILIE_Pos = 0x0
	// Bit mask of CCRCFAILIE field.
	SDMMC2_SDMMC_MASKR_CCRCFAILIE_Msk = 0x1
	// Bit CCRCFAILIE.
	SDMMC2_SDMMC_MASKR_CCRCFAILIE = 0x1
	// Position of DCRCFAILIE field.
	SDMMC2_SDMMC_MASKR_DCRCFAILIE_Pos = 0x1
	// Bit mask of DCRCFAILIE field.
	SDMMC2_SDMMC_MASKR_DCRCFAILIE_Msk = 0x2
	// Bit DCRCFAILIE.
	SDMMC2_SDMMC_MASKR_DCRCFAILIE = 0x2
	// Position of CTIMEOUTIE field.
	SDMMC2_SDMMC_MASKR_CTIMEOUTIE_Pos = 0x2
	// Bit mask of CTIMEOUTIE field.
	SDMMC2_SDMMC_MASKR_CTIMEOUTIE_Msk = 0x4
	// Bit CTIMEOUTIE.
	SDMMC2_SDMMC_MASKR_CTIMEOUTIE = 0x4
	// Position of DTIMEOUTIE field.
	SDMMC2_SDMMC_MASKR_DTIMEOUTIE_Pos = 0x3
	// Bit mask of DTIMEOUTIE field.
	SDMMC2_SDMMC_MASKR_DTIMEOUTIE_Msk = 0x8
	// Bit DTIMEOUTIE.
	SDMMC2_SDMMC_MASKR_DTIMEOUTIE = 0x8
	// Position of TXUNDERRIE field.
	SDMMC2_SDMMC_MASKR_TXUNDERRIE_Pos = 0x4
	// Bit mask of TXUNDERRIE field.
	SDMMC2_SDMMC_MASKR_TXUNDERRIE_Msk = 0x10
	// Bit TXUNDERRIE.
	SDMMC2_SDMMC_MASKR_TXUNDERRIE = 0x10
	// Position of RXOVERRIE field.
	SDMMC2_SDMMC_MASKR_RXOVERRIE_Pos = 0x5
	// Bit mask of RXOVERRIE field.
	SDMMC2_SDMMC_MASKR_RXOVERRIE_Msk = 0x20
	// Bit RXOVERRIE.
	SDMMC2_SDMMC_MASKR_RXOVERRIE = 0x20
	// Position of CMDRENDIE field.
	SDMMC2_SDMMC_MASKR_CMDRENDIE_Pos = 0x6
	// Bit mask of CMDRENDIE field.
	SDMMC2_SDMMC_MASKR_CMDRENDIE_Msk = 0x40
	// Bit CMDRENDIE.
	SDMMC2_SDMMC_MASKR_CMDRENDIE = 0x40
	// Position of CMDSENTIE field.
	SDMMC2_SDMMC_MASKR_CMDSENTIE_Pos = 0x7
	// Bit mask of CMDSENTIE field.
	SDMMC2_SDMMC_MASKR_CMDSENTIE_Msk = 0x80
	// Bit CMDSENTIE.
	SDMMC2_SDMMC_MASKR_CMDSENTIE = 0x80
	// Position of DATAENDIE field.
	SDMMC2_SDMMC_MASKR_DATAENDIE_Pos = 0x8
	// Bit mask of DATAENDIE field.
	SDMMC2_SDMMC_MASKR_DATAENDIE_Msk = 0x100
	// Bit DATAENDIE.
	SDMMC2_SDMMC_MASKR_DATAENDIE = 0x100
	// Position of DHOLDIE field.
	SDMMC2_SDMMC_MASKR_DHOLDIE_Pos = 0x9
	// Bit mask of DHOLDIE field.
	SDMMC2_SDMMC_MASKR_DHOLDIE_Msk = 0x200
	// Bit DHOLDIE.
	SDMMC2_SDMMC_MASKR_DHOLDIE = 0x200
	// Position of DBCKENDIE field.
	SDMMC2_SDMMC_MASKR_DBCKENDIE_Pos = 0xa
	// Bit mask of DBCKENDIE field.
	SDMMC2_SDMMC_MASKR_DBCKENDIE_Msk = 0x400
	// Bit DBCKENDIE.
	SDMMC2_SDMMC_MASKR_DBCKENDIE = 0x400
	// Position of DABORTIE field.
	SDMMC2_SDMMC_MASKR_DABORTIE_Pos = 0xb
	// Bit mask of DABORTIE field.
	SDMMC2_SDMMC_MASKR_DABORTIE_Msk = 0x800
	// Bit DABORTIE.
	SDMMC2_SDMMC_MASKR_DABORTIE = 0x800
	// Position of TXFIFOHEIE field.
	SDMMC2_SDMMC_MASKR_TXFIFOHEIE_Pos = 0xe
	// Bit mask of TXFIFOHEIE field.
	SDMMC2_SDMMC_MASKR_TXFIFOHEIE_Msk = 0x4000
	// Bit TXFIFOHEIE.
	SDMMC2_SDMMC_MASKR_TXFIFOHEIE = 0x4000
	// Position of RXFIFOHFIE field.
	SDMMC2_SDMMC_MASKR_RXFIFOHFIE_Pos = 0xf
	// Bit mask of RXFIFOHFIE field.
	SDMMC2_SDMMC_MASKR_RXFIFOHFIE_Msk = 0x8000
	// Bit RXFIFOHFIE.
	SDMMC2_SDMMC_MASKR_RXFIFOHFIE = 0x8000
	// Position of RXFIFOFIE field.
	SDMMC2_SDMMC_MASKR_RXFIFOFIE_Pos = 0x11
	// Bit mask of RXFIFOFIE field.
	SDMMC2_SDMMC_MASKR_RXFIFOFIE_Msk = 0x20000
	// Bit RXFIFOFIE.
	SDMMC2_SDMMC_MASKR_RXFIFOFIE = 0x20000
	// Position of TXFIFOEIE field.
	SDMMC2_SDMMC_MASKR_TXFIFOEIE_Pos = 0x12
	// Bit mask of TXFIFOEIE field.
	SDMMC2_SDMMC_MASKR_TXFIFOEIE_Msk = 0x40000
	// Bit TXFIFOEIE.
	SDMMC2_SDMMC_MASKR_TXFIFOEIE = 0x40000
	// Position of BUSYD0ENDIE field.
	SDMMC2_SDMMC_MASKR_BUSYD0ENDIE_Pos = 0x15
	// Bit mask of BUSYD0ENDIE field.
	SDMMC2_SDMMC_MASKR_BUSYD0ENDIE_Msk = 0x200000
	// Bit BUSYD0ENDIE.
	SDMMC2_SDMMC_MASKR_BUSYD0ENDIE = 0x200000
	// Position of SDIOITIE field.
	SDMMC2_SDMMC_MASKR_SDIOITIE_Pos = 0x16
	// Bit mask of SDIOITIE field.
	SDMMC2_SDMMC_MASKR_SDIOITIE_Msk = 0x400000
	// Bit SDIOITIE.
	SDMMC2_SDMMC_MASKR_SDIOITIE = 0x400000
	// Position of ACKFAILIE field.
	SDMMC2_SDMMC_MASKR_ACKFAILIE_Pos = 0x17
	// Bit mask of ACKFAILIE field.
	SDMMC2_SDMMC_MASKR_ACKFAILIE_Msk = 0x800000
	// Bit ACKFAILIE.
	SDMMC2_SDMMC_MASKR_ACKFAILIE = 0x800000
	// Position of ACKTIMEOUTIE field.
	SDMMC2_SDMMC_MASKR_ACKTIMEOUTIE_Pos = 0x18
	// Bit mask of ACKTIMEOUTIE field.
	SDMMC2_SDMMC_MASKR_ACKTIMEOUTIE_Msk = 0x1000000
	// Bit ACKTIMEOUTIE.
	SDMMC2_SDMMC_MASKR_ACKTIMEOUTIE = 0x1000000
	// Position of VSWENDIE field.
	SDMMC2_SDMMC_MASKR_VSWENDIE_Pos = 0x19
	// Bit mask of VSWENDIE field.
	SDMMC2_SDMMC_MASKR_VSWENDIE_Msk = 0x2000000
	// Bit VSWENDIE.
	SDMMC2_SDMMC_MASKR_VSWENDIE = 0x2000000
	// Position of CKSTOPIE field.
	SDMMC2_SDMMC_MASKR_CKSTOPIE_Pos = 0x1a
	// Bit mask of CKSTOPIE field.
	SDMMC2_SDMMC_MASKR_CKSTOPIE_Msk = 0x4000000
	// Bit CKSTOPIE.
	SDMMC2_SDMMC_MASKR_CKSTOPIE = 0x4000000
	// Position of IDMABTCIE field.
	SDMMC2_SDMMC_MASKR_IDMABTCIE_Pos = 0x1c
	// Bit mask of IDMABTCIE field.
	SDMMC2_SDMMC_MASKR_IDMABTCIE_Msk = 0x10000000
	// Bit IDMABTCIE.
	SDMMC2_SDMMC_MASKR_IDMABTCIE = 0x10000000

	// SDMMC_ACKTIMER: The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.
	// Position of ACKTIME field.
	SDMMC2_SDMMC_ACKTIMER_ACKTIME_Pos = 0x0
	// Bit mask of ACKTIME field.
	SDMMC2_SDMMC_ACKTIMER_ACKTIME_Msk = 0x1ffffff

	// SDMMC_IDMACTRLR: The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
	// Position of IDMAEN field.
	SDMMC2_SDMMC_IDMACTRLR_IDMAEN_Pos = 0x0
	// Bit mask of IDMAEN field.
	SDMMC2_SDMMC_IDMACTRLR_IDMAEN_Msk = 0x1
	// Bit IDMAEN.
	SDMMC2_SDMMC_IDMACTRLR_IDMAEN = 0x1
	// Position of IDMABMODE field.
	SDMMC2_SDMMC_IDMACTRLR_IDMABMODE_Pos = 0x1
	// Bit mask of IDMABMODE field.
	SDMMC2_SDMMC_IDMACTRLR_IDMABMODE_Msk = 0x2
	// Bit IDMABMODE.
	SDMMC2_SDMMC_IDMACTRLR_IDMABMODE = 0x2

	// SDMMC_IDMABSIZER: The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration.
	// Position of IDMABNDT field.
	SDMMC2_SDMMC_IDMABSIZER_IDMABNDT_Pos = 0x5
	// Bit mask of IDMABNDT field.
	SDMMC2_SDMMC_IDMABSIZER_IDMABNDT_Msk = 0x1ffe0

	// SDMMC_IDMABASER: The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration.
	// Position of IDMABASE field.
	SDMMC2_SDMMC_IDMABASER_IDMABASE_Pos = 0x0
	// Bit mask of IDMABASE field.
	SDMMC2_SDMMC_IDMABASER_IDMABASE_Msk = 0xffffffff

	// SDMMC_IDMALAR: SDMMC IDMA linked list address register
	// Position of IDMALA field.
	SDMMC2_SDMMC_IDMALAR_IDMALA_Pos = 0x2
	// Bit mask of IDMALA field.
	SDMMC2_SDMMC_IDMALAR_IDMALA_Msk = 0xfffc
	// Position of ABR field.
	SDMMC2_SDMMC_IDMALAR_ABR_Pos = 0x1d
	// Bit mask of ABR field.
	SDMMC2_SDMMC_IDMALAR_ABR_Msk = 0x20000000
	// Bit ABR.
	SDMMC2_SDMMC_IDMALAR_ABR = 0x20000000
	// Position of ULS field.
	SDMMC2_SDMMC_IDMALAR_ULS_Pos = 0x1e
	// Bit mask of ULS field.
	SDMMC2_SDMMC_IDMALAR_ULS_Msk = 0x40000000
	// Bit ULS.
	SDMMC2_SDMMC_IDMALAR_ULS = 0x40000000
	// Position of ULA field.
	SDMMC2_SDMMC_IDMALAR_ULA_Pos = 0x1f
	// Bit mask of ULA field.
	SDMMC2_SDMMC_IDMALAR_ULA_Msk = 0x80000000
	// Bit ULA.
	SDMMC2_SDMMC_IDMALAR_ULA = 0x80000000

	// SDMMC_IDMABAR: SDMMC IDMA linked list memory base register
	// Position of IDMABA field.
	SDMMC2_SDMMC_IDMABAR_IDMABA_Pos = 0x2
	// Bit mask of IDMABA field.
	SDMMC2_SDMMC_IDMABAR_IDMABA_Msk = 0xfffffffc

	// SDMMC_FIFOR0: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR0_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR0_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR1: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR1_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR1_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR2: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR2_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR2_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR3: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR3_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR3_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR4: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR4_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR4_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR5: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR5_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR5_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR6: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR6_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR6_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR7: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR7_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR7_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR8: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR8_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR8_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR9: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR9_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR9_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR10: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR10_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR10_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR11: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR11_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR11_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR12: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR12_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR12_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR13: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR13_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR13_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR14: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR14_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR14_FIFODATA_Msk = 0xffffffff

	// SDMMC_FIFOR15: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC2_SDMMC_FIFOR15_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC2_SDMMC_FIFOR15_FIFODATA_Msk = 0xffffffff

	// SDMMC_VERR: SDMMC version register
	// Position of MINREV field.
	SDMMC2_SDMMC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	SDMMC2_SDMMC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	SDMMC2_SDMMC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	SDMMC2_SDMMC_VERR_MAJREV_Msk = 0xf0

	// SDMMC_IPIDR: SDMMC identification register
	// Position of IP_ID field.
	SDMMC2_SDMMC_IPIDR_IP_ID_Pos = 0x0
	// Bit mask of IP_ID field.
	SDMMC2_SDMMC_IPIDR_IP_ID_Msk = 0xffffffff

	// SDMMC_SIDR: SDMMC size ID register
	// Position of SID field.
	SDMMC2_SDMMC_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	SDMMC2_SDMMC_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for SPDIFRX: SPDIFRX
const (
	// SPDIFRX_CR: Control register
	// Position of SPDIFRXEN field.
	SPDIFRX_SPDIFRX_CR_SPDIFRXEN_Pos = 0x0
	// Bit mask of SPDIFRXEN field.
	SPDIFRX_SPDIFRX_CR_SPDIFRXEN_Msk = 0x3
	// Position of RXDMAEN field.
	SPDIFRX_SPDIFRX_CR_RXDMAEN_Pos = 0x2
	// Bit mask of RXDMAEN field.
	SPDIFRX_SPDIFRX_CR_RXDMAEN_Msk = 0x4
	// Bit RXDMAEN.
	SPDIFRX_SPDIFRX_CR_RXDMAEN = 0x4
	// Position of RXSTEO field.
	SPDIFRX_SPDIFRX_CR_RXSTEO_Pos = 0x3
	// Bit mask of RXSTEO field.
	SPDIFRX_SPDIFRX_CR_RXSTEO_Msk = 0x8
	// Bit RXSTEO.
	SPDIFRX_SPDIFRX_CR_RXSTEO = 0x8
	// Position of DRFMT field.
	SPDIFRX_SPDIFRX_CR_DRFMT_Pos = 0x4
	// Bit mask of DRFMT field.
	SPDIFRX_SPDIFRX_CR_DRFMT_Msk = 0x30
	// Position of PMSK field.
	SPDIFRX_SPDIFRX_CR_PMSK_Pos = 0x6
	// Bit mask of PMSK field.
	SPDIFRX_SPDIFRX_CR_PMSK_Msk = 0x40
	// Bit PMSK.
	SPDIFRX_SPDIFRX_CR_PMSK = 0x40
	// Position of VMSK field.
	SPDIFRX_SPDIFRX_CR_VMSK_Pos = 0x7
	// Bit mask of VMSK field.
	SPDIFRX_SPDIFRX_CR_VMSK_Msk = 0x80
	// Bit VMSK.
	SPDIFRX_SPDIFRX_CR_VMSK = 0x80
	// Position of CUMSK field.
	SPDIFRX_SPDIFRX_CR_CUMSK_Pos = 0x8
	// Bit mask of CUMSK field.
	SPDIFRX_SPDIFRX_CR_CUMSK_Msk = 0x100
	// Bit CUMSK.
	SPDIFRX_SPDIFRX_CR_CUMSK = 0x100
	// Position of PTMSK field.
	SPDIFRX_SPDIFRX_CR_PTMSK_Pos = 0x9
	// Bit mask of PTMSK field.
	SPDIFRX_SPDIFRX_CR_PTMSK_Msk = 0x200
	// Bit PTMSK.
	SPDIFRX_SPDIFRX_CR_PTMSK = 0x200
	// Position of CBDMAEN field.
	SPDIFRX_SPDIFRX_CR_CBDMAEN_Pos = 0xa
	// Bit mask of CBDMAEN field.
	SPDIFRX_SPDIFRX_CR_CBDMAEN_Msk = 0x400
	// Bit CBDMAEN.
	SPDIFRX_SPDIFRX_CR_CBDMAEN = 0x400
	// Position of CHSEL field.
	SPDIFRX_SPDIFRX_CR_CHSEL_Pos = 0xb
	// Bit mask of CHSEL field.
	SPDIFRX_SPDIFRX_CR_CHSEL_Msk = 0x800
	// Bit CHSEL.
	SPDIFRX_SPDIFRX_CR_CHSEL = 0x800
	// Position of NBTR field.
	SPDIFRX_SPDIFRX_CR_NBTR_Pos = 0xc
	// Bit mask of NBTR field.
	SPDIFRX_SPDIFRX_CR_NBTR_Msk = 0x3000
	// Position of WFA field.
	SPDIFRX_SPDIFRX_CR_WFA_Pos = 0xe
	// Bit mask of WFA field.
	SPDIFRX_SPDIFRX_CR_WFA_Msk = 0x4000
	// Bit WFA.
	SPDIFRX_SPDIFRX_CR_WFA = 0x4000
	// Position of INSEL field.
	SPDIFRX_SPDIFRX_CR_INSEL_Pos = 0x10
	// Bit mask of INSEL field.
	SPDIFRX_SPDIFRX_CR_INSEL_Msk = 0x70000
	// Position of CKSEN field.
	SPDIFRX_SPDIFRX_CR_CKSEN_Pos = 0x14
	// Bit mask of CKSEN field.
	SPDIFRX_SPDIFRX_CR_CKSEN_Msk = 0x100000
	// Bit CKSEN.
	SPDIFRX_SPDIFRX_CR_CKSEN = 0x100000
	// Position of CKSBKPEN field.
	SPDIFRX_SPDIFRX_CR_CKSBKPEN_Pos = 0x15
	// Bit mask of CKSBKPEN field.
	SPDIFRX_SPDIFRX_CR_CKSBKPEN_Msk = 0x200000
	// Bit CKSBKPEN.
	SPDIFRX_SPDIFRX_CR_CKSBKPEN = 0x200000

	// SPDIFRX_IMR: Interrupt mask register
	// Position of RXNEIE field.
	SPDIFRX_SPDIFRX_IMR_RXNEIE_Pos = 0x0
	// Bit mask of RXNEIE field.
	SPDIFRX_SPDIFRX_IMR_RXNEIE_Msk = 0x1
	// Bit RXNEIE.
	SPDIFRX_SPDIFRX_IMR_RXNEIE = 0x1
	// Position of CSRNEIE field.
	SPDIFRX_SPDIFRX_IMR_CSRNEIE_Pos = 0x1
	// Bit mask of CSRNEIE field.
	SPDIFRX_SPDIFRX_IMR_CSRNEIE_Msk = 0x2
	// Bit CSRNEIE.
	SPDIFRX_SPDIFRX_IMR_CSRNEIE = 0x2
	// Position of PERRIE field.
	SPDIFRX_SPDIFRX_IMR_PERRIE_Pos = 0x2
	// Bit mask of PERRIE field.
	SPDIFRX_SPDIFRX_IMR_PERRIE_Msk = 0x4
	// Bit PERRIE.
	SPDIFRX_SPDIFRX_IMR_PERRIE = 0x4
	// Position of OVRIE field.
	SPDIFRX_SPDIFRX_IMR_OVRIE_Pos = 0x3
	// Bit mask of OVRIE field.
	SPDIFRX_SPDIFRX_IMR_OVRIE_Msk = 0x8
	// Bit OVRIE.
	SPDIFRX_SPDIFRX_IMR_OVRIE = 0x8
	// Position of SBLKIE field.
	SPDIFRX_SPDIFRX_IMR_SBLKIE_Pos = 0x4
	// Bit mask of SBLKIE field.
	SPDIFRX_SPDIFRX_IMR_SBLKIE_Msk = 0x10
	// Bit SBLKIE.
	SPDIFRX_SPDIFRX_IMR_SBLKIE = 0x10
	// Position of SYNCDIE field.
	SPDIFRX_SPDIFRX_IMR_SYNCDIE_Pos = 0x5
	// Bit mask of SYNCDIE field.
	SPDIFRX_SPDIFRX_IMR_SYNCDIE_Msk = 0x20
	// Bit SYNCDIE.
	SPDIFRX_SPDIFRX_IMR_SYNCDIE = 0x20
	// Position of IFEIE field.
	SPDIFRX_SPDIFRX_IMR_IFEIE_Pos = 0x6
	// Bit mask of IFEIE field.
	SPDIFRX_SPDIFRX_IMR_IFEIE_Msk = 0x40
	// Bit IFEIE.
	SPDIFRX_SPDIFRX_IMR_IFEIE = 0x40

	// SPDIFRX_SR: Status register
	// Position of RXNE field.
	SPDIFRX_SPDIFRX_SR_RXNE_Pos = 0x0
	// Bit mask of RXNE field.
	SPDIFRX_SPDIFRX_SR_RXNE_Msk = 0x1
	// Bit RXNE.
	SPDIFRX_SPDIFRX_SR_RXNE = 0x1
	// Position of CSRNE field.
	SPDIFRX_SPDIFRX_SR_CSRNE_Pos = 0x1
	// Bit mask of CSRNE field.
	SPDIFRX_SPDIFRX_SR_CSRNE_Msk = 0x2
	// Bit CSRNE.
	SPDIFRX_SPDIFRX_SR_CSRNE = 0x2
	// Position of PERR field.
	SPDIFRX_SPDIFRX_SR_PERR_Pos = 0x2
	// Bit mask of PERR field.
	SPDIFRX_SPDIFRX_SR_PERR_Msk = 0x4
	// Bit PERR.
	SPDIFRX_SPDIFRX_SR_PERR = 0x4
	// Position of OVR field.
	SPDIFRX_SPDIFRX_SR_OVR_Pos = 0x3
	// Bit mask of OVR field.
	SPDIFRX_SPDIFRX_SR_OVR_Msk = 0x8
	// Bit OVR.
	SPDIFRX_SPDIFRX_SR_OVR = 0x8
	// Position of SBD field.
	SPDIFRX_SPDIFRX_SR_SBD_Pos = 0x4
	// Bit mask of SBD field.
	SPDIFRX_SPDIFRX_SR_SBD_Msk = 0x10
	// Bit SBD.
	SPDIFRX_SPDIFRX_SR_SBD = 0x10
	// Position of SYNCD field.
	SPDIFRX_SPDIFRX_SR_SYNCD_Pos = 0x5
	// Bit mask of SYNCD field.
	SPDIFRX_SPDIFRX_SR_SYNCD_Msk = 0x20
	// Bit SYNCD.
	SPDIFRX_SPDIFRX_SR_SYNCD = 0x20
	// Position of FERR field.
	SPDIFRX_SPDIFRX_SR_FERR_Pos = 0x6
	// Bit mask of FERR field.
	SPDIFRX_SPDIFRX_SR_FERR_Msk = 0x40
	// Bit FERR.
	SPDIFRX_SPDIFRX_SR_FERR = 0x40
	// Position of SERR field.
	SPDIFRX_SPDIFRX_SR_SERR_Pos = 0x7
	// Bit mask of SERR field.
	SPDIFRX_SPDIFRX_SR_SERR_Msk = 0x80
	// Bit SERR.
	SPDIFRX_SPDIFRX_SR_SERR = 0x80
	// Position of TERR field.
	SPDIFRX_SPDIFRX_SR_TERR_Pos = 0x8
	// Bit mask of TERR field.
	SPDIFRX_SPDIFRX_SR_TERR_Msk = 0x100
	// Bit TERR.
	SPDIFRX_SPDIFRX_SR_TERR = 0x100
	// Position of WIDTH5 field.
	SPDIFRX_SPDIFRX_SR_WIDTH5_Pos = 0x10
	// Bit mask of WIDTH5 field.
	SPDIFRX_SPDIFRX_SR_WIDTH5_Msk = 0x7fff0000

	// SPDIFRX_IFCR: Interrupt flag clear register
	// Position of PERRCF field.
	SPDIFRX_SPDIFRX_IFCR_PERRCF_Pos = 0x2
	// Bit mask of PERRCF field.
	SPDIFRX_SPDIFRX_IFCR_PERRCF_Msk = 0x4
	// Bit PERRCF.
	SPDIFRX_SPDIFRX_IFCR_PERRCF = 0x4
	// Position of OVRCF field.
	SPDIFRX_SPDIFRX_IFCR_OVRCF_Pos = 0x3
	// Bit mask of OVRCF field.
	SPDIFRX_SPDIFRX_IFCR_OVRCF_Msk = 0x8
	// Bit OVRCF.
	SPDIFRX_SPDIFRX_IFCR_OVRCF = 0x8
	// Position of SBDCF field.
	SPDIFRX_SPDIFRX_IFCR_SBDCF_Pos = 0x4
	// Bit mask of SBDCF field.
	SPDIFRX_SPDIFRX_IFCR_SBDCF_Msk = 0x10
	// Bit SBDCF.
	SPDIFRX_SPDIFRX_IFCR_SBDCF = 0x10
	// Position of SYNCDCF field.
	SPDIFRX_SPDIFRX_IFCR_SYNCDCF_Pos = 0x5
	// Bit mask of SYNCDCF field.
	SPDIFRX_SPDIFRX_IFCR_SYNCDCF_Msk = 0x20
	// Bit SYNCDCF.
	SPDIFRX_SPDIFRX_IFCR_SYNCDCF = 0x20

	// SPDIFRX_FMT0_DR: This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00:
	// Position of DR field.
	SPDIFRX_SPDIFRX_FMT0_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	SPDIFRX_SPDIFRX_FMT0_DR_DR_Msk = 0xffffff
	// Position of PE field.
	SPDIFRX_SPDIFRX_FMT0_DR_PE_Pos = 0x18
	// Bit mask of PE field.
	SPDIFRX_SPDIFRX_FMT0_DR_PE_Msk = 0x1000000
	// Bit PE.
	SPDIFRX_SPDIFRX_FMT0_DR_PE = 0x1000000
	// Position of V field.
	SPDIFRX_SPDIFRX_FMT0_DR_V_Pos = 0x19
	// Bit mask of V field.
	SPDIFRX_SPDIFRX_FMT0_DR_V_Msk = 0x2000000
	// Bit V.
	SPDIFRX_SPDIFRX_FMT0_DR_V = 0x2000000
	// Position of U field.
	SPDIFRX_SPDIFRX_FMT0_DR_U_Pos = 0x1a
	// Bit mask of U field.
	SPDIFRX_SPDIFRX_FMT0_DR_U_Msk = 0x4000000
	// Bit U.
	SPDIFRX_SPDIFRX_FMT0_DR_U = 0x4000000
	// Position of C field.
	SPDIFRX_SPDIFRX_FMT0_DR_C_Pos = 0x1b
	// Bit mask of C field.
	SPDIFRX_SPDIFRX_FMT0_DR_C_Msk = 0x8000000
	// Bit C.
	SPDIFRX_SPDIFRX_FMT0_DR_C = 0x8000000
	// Position of PT field.
	SPDIFRX_SPDIFRX_FMT0_DR_PT_Pos = 0x1c
	// Bit mask of PT field.
	SPDIFRX_SPDIFRX_FMT0_DR_PT_Msk = 0x30000000

	// SPDIFRX_CSR: Channel status register
	// Position of USR field.
	SPDIFRX_SPDIFRX_CSR_USR_Pos = 0x0
	// Bit mask of USR field.
	SPDIFRX_SPDIFRX_CSR_USR_Msk = 0xffff
	// Position of CS field.
	SPDIFRX_SPDIFRX_CSR_CS_Pos = 0x10
	// Bit mask of CS field.
	SPDIFRX_SPDIFRX_CSR_CS_Msk = 0xff0000
	// Position of SOB field.
	SPDIFRX_SPDIFRX_CSR_SOB_Pos = 0x18
	// Bit mask of SOB field.
	SPDIFRX_SPDIFRX_CSR_SOB_Msk = 0x1000000
	// Bit SOB.
	SPDIFRX_SPDIFRX_CSR_SOB = 0x1000000

	// SPDIFRX_DIR: Debug information register
	// Position of THI field.
	SPDIFRX_SPDIFRX_DIR_THI_Pos = 0x0
	// Bit mask of THI field.
	SPDIFRX_SPDIFRX_DIR_THI_Msk = 0x1fff
	// Position of TLO field.
	SPDIFRX_SPDIFRX_DIR_TLO_Pos = 0x10
	// Bit mask of TLO field.
	SPDIFRX_SPDIFRX_DIR_TLO_Msk = 0x1fff0000

	// SPDIFRX_VERR: SPDIFRX version register
	// Position of MINREV field.
	SPDIFRX_SPDIFRX_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	SPDIFRX_SPDIFRX_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	SPDIFRX_SPDIFRX_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	SPDIFRX_SPDIFRX_VERR_MAJREV_Msk = 0xf0

	// SPDIFRX_IPIDR: SPDIFRX identification register
	// Position of ID field.
	SPDIFRX_SPDIFRX_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	SPDIFRX_SPDIFRX_IPIDR_ID_Msk = 0xffffffff

	// SPDIFRX_SIDR: SPDIFRX size identification register
	// Position of SID field.
	SPDIFRX_SPDIFRX_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	SPDIFRX_SPDIFRX_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for SPI1: SPI1
const (
	// SPI2S_CR1: SPI/I2S control register 1
	// Position of SPE field.
	SPI1_SPI2S_CR1_SPE_Pos = 0x0
	// Bit mask of SPE field.
	SPI1_SPI2S_CR1_SPE_Msk = 0x1
	// Bit SPE.
	SPI1_SPI2S_CR1_SPE = 0x1
	// Position of MASRX field.
	SPI1_SPI2S_CR1_MASRX_Pos = 0x8
	// Bit mask of MASRX field.
	SPI1_SPI2S_CR1_MASRX_Msk = 0x100
	// Bit MASRX.
	SPI1_SPI2S_CR1_MASRX = 0x100
	// Position of CSTART field.
	SPI1_SPI2S_CR1_CSTART_Pos = 0x9
	// Bit mask of CSTART field.
	SPI1_SPI2S_CR1_CSTART_Msk = 0x200
	// Bit CSTART.
	SPI1_SPI2S_CR1_CSTART = 0x200
	// Position of CSUSP field.
	SPI1_SPI2S_CR1_CSUSP_Pos = 0xa
	// Bit mask of CSUSP field.
	SPI1_SPI2S_CR1_CSUSP_Msk = 0x400
	// Bit CSUSP.
	SPI1_SPI2S_CR1_CSUSP = 0x400
	// Position of HDDIR field.
	SPI1_SPI2S_CR1_HDDIR_Pos = 0xb
	// Bit mask of HDDIR field.
	SPI1_SPI2S_CR1_HDDIR_Msk = 0x800
	// Bit HDDIR.
	SPI1_SPI2S_CR1_HDDIR = 0x800
	// Position of SSI field.
	SPI1_SPI2S_CR1_SSI_Pos = 0xc
	// Bit mask of SSI field.
	SPI1_SPI2S_CR1_SSI_Msk = 0x1000
	// Bit SSI.
	SPI1_SPI2S_CR1_SSI = 0x1000
	// Position of CRC33_17 field.
	SPI1_SPI2S_CR1_CRC33_17_Pos = 0xd
	// Bit mask of CRC33_17 field.
	SPI1_SPI2S_CR1_CRC33_17_Msk = 0x2000
	// Bit CRC33_17.
	SPI1_SPI2S_CR1_CRC33_17 = 0x2000
	// Position of RCRCINI field.
	SPI1_SPI2S_CR1_RCRCINI_Pos = 0xe
	// Bit mask of RCRCINI field.
	SPI1_SPI2S_CR1_RCRCINI_Msk = 0x4000
	// Bit RCRCINI.
	SPI1_SPI2S_CR1_RCRCINI = 0x4000
	// Position of TCRCINI field.
	SPI1_SPI2S_CR1_TCRCINI_Pos = 0xf
	// Bit mask of TCRCINI field.
	SPI1_SPI2S_CR1_TCRCINI_Msk = 0x8000
	// Bit TCRCINI.
	SPI1_SPI2S_CR1_TCRCINI = 0x8000
	// Position of IOLOCK field.
	SPI1_SPI2S_CR1_IOLOCK_Pos = 0x10
	// Bit mask of IOLOCK field.
	SPI1_SPI2S_CR1_IOLOCK_Msk = 0x10000
	// Bit IOLOCK.
	SPI1_SPI2S_CR1_IOLOCK = 0x10000

	// SPI_CR2: SPI control register 2
	// Position of TSIZE field.
	SPI1_SPI_CR2_TSIZE_Pos = 0x0
	// Bit mask of TSIZE field.
	SPI1_SPI_CR2_TSIZE_Msk = 0xffff
	// Position of TSER field.
	SPI1_SPI_CR2_TSER_Pos = 0x10
	// Bit mask of TSER field.
	SPI1_SPI_CR2_TSER_Msk = 0xffff0000

	// SPI_CFG1: Content of this register is write protected when SPI is enabled
	// Position of DSIZE field.
	SPI1_SPI_CFG1_DSIZE_Pos = 0x0
	// Bit mask of DSIZE field.
	SPI1_SPI_CFG1_DSIZE_Msk = 0x1f
	// Position of FTHLV field.
	SPI1_SPI_CFG1_FTHLV_Pos = 0x5
	// Bit mask of FTHLV field.
	SPI1_SPI_CFG1_FTHLV_Msk = 0x1e0
	// Position of UDRCFG field.
	SPI1_SPI_CFG1_UDRCFG_Pos = 0x9
	// Bit mask of UDRCFG field.
	SPI1_SPI_CFG1_UDRCFG_Msk = 0x600
	// Position of UDRDET field.
	SPI1_SPI_CFG1_UDRDET_Pos = 0xb
	// Bit mask of UDRDET field.
	SPI1_SPI_CFG1_UDRDET_Msk = 0x1800
	// Position of RXDMAEN field.
	SPI1_SPI_CFG1_RXDMAEN_Pos = 0xe
	// Bit mask of RXDMAEN field.
	SPI1_SPI_CFG1_RXDMAEN_Msk = 0x4000
	// Bit RXDMAEN.
	SPI1_SPI_CFG1_RXDMAEN = 0x4000
	// Position of TXDMAEN field.
	SPI1_SPI_CFG1_TXDMAEN_Pos = 0xf
	// Bit mask of TXDMAEN field.
	SPI1_SPI_CFG1_TXDMAEN_Msk = 0x8000
	// Bit TXDMAEN.
	SPI1_SPI_CFG1_TXDMAEN = 0x8000
	// Position of CRCSIZE field.
	SPI1_SPI_CFG1_CRCSIZE_Pos = 0x10
	// Bit mask of CRCSIZE field.
	SPI1_SPI_CFG1_CRCSIZE_Msk = 0x1f0000
	// Position of CRCEN field.
	SPI1_SPI_CFG1_CRCEN_Pos = 0x16
	// Bit mask of CRCEN field.
	SPI1_SPI_CFG1_CRCEN_Msk = 0x400000
	// Bit CRCEN.
	SPI1_SPI_CFG1_CRCEN = 0x400000
	// Position of MBR field.
	SPI1_SPI_CFG1_MBR_Pos = 0x1c
	// Bit mask of MBR field.
	SPI1_SPI_CFG1_MBR_Msk = 0x70000000

	// SPI_CFG2: The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.
	// Position of MSSI field.
	SPI1_SPI_CFG2_MSSI_Pos = 0x0
	// Bit mask of MSSI field.
	SPI1_SPI_CFG2_MSSI_Msk = 0xf
	// Position of MIDI field.
	SPI1_SPI_CFG2_MIDI_Pos = 0x4
	// Bit mask of MIDI field.
	SPI1_SPI_CFG2_MIDI_Msk = 0xf0
	// Position of IOSWP field.
	SPI1_SPI_CFG2_IOSWP_Pos = 0xf
	// Bit mask of IOSWP field.
	SPI1_SPI_CFG2_IOSWP_Msk = 0x8000
	// Bit IOSWP.
	SPI1_SPI_CFG2_IOSWP = 0x8000
	// Position of COMM field.
	SPI1_SPI_CFG2_COMM_Pos = 0x11
	// Bit mask of COMM field.
	SPI1_SPI_CFG2_COMM_Msk = 0x60000
	// Position of SP field.
	SPI1_SPI_CFG2_SP_Pos = 0x13
	// Bit mask of SP field.
	SPI1_SPI_CFG2_SP_Msk = 0x380000
	// Position of MASTER field.
	SPI1_SPI_CFG2_MASTER_Pos = 0x16
	// Bit mask of MASTER field.
	SPI1_SPI_CFG2_MASTER_Msk = 0x400000
	// Bit MASTER.
	SPI1_SPI_CFG2_MASTER = 0x400000
	// Position of LSBFRST field.
	SPI1_SPI_CFG2_LSBFRST_Pos = 0x17
	// Bit mask of LSBFRST field.
	SPI1_SPI_CFG2_LSBFRST_Msk = 0x800000
	// Bit LSBFRST.
	SPI1_SPI_CFG2_LSBFRST = 0x800000
	// Position of CPHA field.
	SPI1_SPI_CFG2_CPHA_Pos = 0x18
	// Bit mask of CPHA field.
	SPI1_SPI_CFG2_CPHA_Msk = 0x1000000
	// Bit CPHA.
	SPI1_SPI_CFG2_CPHA = 0x1000000
	// Position of CPOL field.
	SPI1_SPI_CFG2_CPOL_Pos = 0x19
	// Bit mask of CPOL field.
	SPI1_SPI_CFG2_CPOL_Msk = 0x2000000
	// Bit CPOL.
	SPI1_SPI_CFG2_CPOL = 0x2000000
	// Position of SSM field.
	SPI1_SPI_CFG2_SSM_Pos = 0x1a
	// Bit mask of SSM field.
	SPI1_SPI_CFG2_SSM_Msk = 0x4000000
	// Bit SSM.
	SPI1_SPI_CFG2_SSM = 0x4000000
	// Position of SSIOP field.
	SPI1_SPI_CFG2_SSIOP_Pos = 0x1c
	// Bit mask of SSIOP field.
	SPI1_SPI_CFG2_SSIOP_Msk = 0x10000000
	// Bit SSIOP.
	SPI1_SPI_CFG2_SSIOP = 0x10000000
	// Position of SSOE field.
	SPI1_SPI_CFG2_SSOE_Pos = 0x1d
	// Bit mask of SSOE field.
	SPI1_SPI_CFG2_SSOE_Msk = 0x20000000
	// Bit SSOE.
	SPI1_SPI_CFG2_SSOE = 0x20000000
	// Position of SSOM field.
	SPI1_SPI_CFG2_SSOM_Pos = 0x1e
	// Bit mask of SSOM field.
	SPI1_SPI_CFG2_SSOM_Msk = 0x40000000
	// Bit SSOM.
	SPI1_SPI_CFG2_SSOM = 0x40000000
	// Position of AFCNTR field.
	SPI1_SPI_CFG2_AFCNTR_Pos = 0x1f
	// Bit mask of AFCNTR field.
	SPI1_SPI_CFG2_AFCNTR_Msk = 0x80000000
	// Bit AFCNTR.
	SPI1_SPI_CFG2_AFCNTR = 0x80000000

	// SPI2S_IER: SPI/I2S interrupt enable register
	// Position of RXPIE field.
	SPI1_SPI2S_IER_RXPIE_Pos = 0x0
	// Bit mask of RXPIE field.
	SPI1_SPI2S_IER_RXPIE_Msk = 0x1
	// Bit RXPIE.
	SPI1_SPI2S_IER_RXPIE = 0x1
	// Position of TXPIE field.
	SPI1_SPI2S_IER_TXPIE_Pos = 0x1
	// Bit mask of TXPIE field.
	SPI1_SPI2S_IER_TXPIE_Msk = 0x2
	// Bit TXPIE.
	SPI1_SPI2S_IER_TXPIE = 0x2
	// Position of DXPIE field.
	SPI1_SPI2S_IER_DXPIE_Pos = 0x2
	// Bit mask of DXPIE field.
	SPI1_SPI2S_IER_DXPIE_Msk = 0x4
	// Bit DXPIE.
	SPI1_SPI2S_IER_DXPIE = 0x4
	// Position of EOTIE field.
	SPI1_SPI2S_IER_EOTIE_Pos = 0x3
	// Bit mask of EOTIE field.
	SPI1_SPI2S_IER_EOTIE_Msk = 0x8
	// Bit EOTIE.
	SPI1_SPI2S_IER_EOTIE = 0x8
	// Position of TXTFIE field.
	SPI1_SPI2S_IER_TXTFIE_Pos = 0x4
	// Bit mask of TXTFIE field.
	SPI1_SPI2S_IER_TXTFIE_Msk = 0x10
	// Bit TXTFIE.
	SPI1_SPI2S_IER_TXTFIE = 0x10
	// Position of UDRIE field.
	SPI1_SPI2S_IER_UDRIE_Pos = 0x5
	// Bit mask of UDRIE field.
	SPI1_SPI2S_IER_UDRIE_Msk = 0x20
	// Bit UDRIE.
	SPI1_SPI2S_IER_UDRIE = 0x20
	// Position of OVRIE field.
	SPI1_SPI2S_IER_OVRIE_Pos = 0x6
	// Bit mask of OVRIE field.
	SPI1_SPI2S_IER_OVRIE_Msk = 0x40
	// Bit OVRIE.
	SPI1_SPI2S_IER_OVRIE = 0x40
	// Position of CRCEIE field.
	SPI1_SPI2S_IER_CRCEIE_Pos = 0x7
	// Bit mask of CRCEIE field.
	SPI1_SPI2S_IER_CRCEIE_Msk = 0x80
	// Bit CRCEIE.
	SPI1_SPI2S_IER_CRCEIE = 0x80
	// Position of TIFREIE field.
	SPI1_SPI2S_IER_TIFREIE_Pos = 0x8
	// Bit mask of TIFREIE field.
	SPI1_SPI2S_IER_TIFREIE_Msk = 0x100
	// Bit TIFREIE.
	SPI1_SPI2S_IER_TIFREIE = 0x100
	// Position of MODFIE field.
	SPI1_SPI2S_IER_MODFIE_Pos = 0x9
	// Bit mask of MODFIE field.
	SPI1_SPI2S_IER_MODFIE_Msk = 0x200
	// Bit MODFIE.
	SPI1_SPI2S_IER_MODFIE = 0x200
	// Position of TSERFIE field.
	SPI1_SPI2S_IER_TSERFIE_Pos = 0xa
	// Bit mask of TSERFIE field.
	SPI1_SPI2S_IER_TSERFIE_Msk = 0x400
	// Bit TSERFIE.
	SPI1_SPI2S_IER_TSERFIE = 0x400

	// SPI2S_SR: SPI/I2S status register
	// Position of RXP field.
	SPI1_SPI2S_SR_RXP_Pos = 0x0
	// Bit mask of RXP field.
	SPI1_SPI2S_SR_RXP_Msk = 0x1
	// Bit RXP.
	SPI1_SPI2S_SR_RXP = 0x1
	// Position of TXP field.
	SPI1_SPI2S_SR_TXP_Pos = 0x1
	// Bit mask of TXP field.
	SPI1_SPI2S_SR_TXP_Msk = 0x2
	// Bit TXP.
	SPI1_SPI2S_SR_TXP = 0x2
	// Position of DXP field.
	SPI1_SPI2S_SR_DXP_Pos = 0x2
	// Bit mask of DXP field.
	SPI1_SPI2S_SR_DXP_Msk = 0x4
	// Bit DXP.
	SPI1_SPI2S_SR_DXP = 0x4
	// Position of EOT field.
	SPI1_SPI2S_SR_EOT_Pos = 0x3
	// Bit mask of EOT field.
	SPI1_SPI2S_SR_EOT_Msk = 0x8
	// Bit EOT.
	SPI1_SPI2S_SR_EOT = 0x8
	// Position of TXTF field.
	SPI1_SPI2S_SR_TXTF_Pos = 0x4
	// Bit mask of TXTF field.
	SPI1_SPI2S_SR_TXTF_Msk = 0x10
	// Bit TXTF.
	SPI1_SPI2S_SR_TXTF = 0x10
	// Position of UDR field.
	SPI1_SPI2S_SR_UDR_Pos = 0x5
	// Bit mask of UDR field.
	SPI1_SPI2S_SR_UDR_Msk = 0x20
	// Bit UDR.
	SPI1_SPI2S_SR_UDR = 0x20
	// Position of OVR field.
	SPI1_SPI2S_SR_OVR_Pos = 0x6
	// Bit mask of OVR field.
	SPI1_SPI2S_SR_OVR_Msk = 0x40
	// Bit OVR.
	SPI1_SPI2S_SR_OVR = 0x40
	// Position of CRCE field.
	SPI1_SPI2S_SR_CRCE_Pos = 0x7
	// Bit mask of CRCE field.
	SPI1_SPI2S_SR_CRCE_Msk = 0x80
	// Bit CRCE.
	SPI1_SPI2S_SR_CRCE = 0x80
	// Position of TIFRE field.
	SPI1_SPI2S_SR_TIFRE_Pos = 0x8
	// Bit mask of TIFRE field.
	SPI1_SPI2S_SR_TIFRE_Msk = 0x100
	// Bit TIFRE.
	SPI1_SPI2S_SR_TIFRE = 0x100
	// Position of MODF field.
	SPI1_SPI2S_SR_MODF_Pos = 0x9
	// Bit mask of MODF field.
	SPI1_SPI2S_SR_MODF_Msk = 0x200
	// Bit MODF.
	SPI1_SPI2S_SR_MODF = 0x200
	// Position of TSERF field.
	SPI1_SPI2S_SR_TSERF_Pos = 0xa
	// Bit mask of TSERF field.
	SPI1_SPI2S_SR_TSERF_Msk = 0x400
	// Bit TSERF.
	SPI1_SPI2S_SR_TSERF = 0x400
	// Position of SUSP field.
	SPI1_SPI2S_SR_SUSP_Pos = 0xb
	// Bit mask of SUSP field.
	SPI1_SPI2S_SR_SUSP_Msk = 0x800
	// Bit SUSP.
	SPI1_SPI2S_SR_SUSP = 0x800
	// Position of TXC field.
	SPI1_SPI2S_SR_TXC_Pos = 0xc
	// Bit mask of TXC field.
	SPI1_SPI2S_SR_TXC_Msk = 0x1000
	// Bit TXC.
	SPI1_SPI2S_SR_TXC = 0x1000
	// Position of RXPLVL field.
	SPI1_SPI2S_SR_RXPLVL_Pos = 0xd
	// Bit mask of RXPLVL field.
	SPI1_SPI2S_SR_RXPLVL_Msk = 0x6000
	// Position of RXWNE field.
	SPI1_SPI2S_SR_RXWNE_Pos = 0xf
	// Bit mask of RXWNE field.
	SPI1_SPI2S_SR_RXWNE_Msk = 0x8000
	// Bit RXWNE.
	SPI1_SPI2S_SR_RXWNE = 0x8000
	// Position of CTSIZE field.
	SPI1_SPI2S_SR_CTSIZE_Pos = 0x10
	// Bit mask of CTSIZE field.
	SPI1_SPI2S_SR_CTSIZE_Msk = 0xffff0000

	// SPI2S_IFCR: SPI/I2S interrupt/status flags clear register
	// Position of EOTC field.
	SPI1_SPI2S_IFCR_EOTC_Pos = 0x3
	// Bit mask of EOTC field.
	SPI1_SPI2S_IFCR_EOTC_Msk = 0x8
	// Bit EOTC.
	SPI1_SPI2S_IFCR_EOTC = 0x8
	// Position of TXTFC field.
	SPI1_SPI2S_IFCR_TXTFC_Pos = 0x4
	// Bit mask of TXTFC field.
	SPI1_SPI2S_IFCR_TXTFC_Msk = 0x10
	// Bit TXTFC.
	SPI1_SPI2S_IFCR_TXTFC = 0x10
	// Position of UDRC field.
	SPI1_SPI2S_IFCR_UDRC_Pos = 0x5
	// Bit mask of UDRC field.
	SPI1_SPI2S_IFCR_UDRC_Msk = 0x20
	// Bit UDRC.
	SPI1_SPI2S_IFCR_UDRC = 0x20
	// Position of OVRC field.
	SPI1_SPI2S_IFCR_OVRC_Pos = 0x6
	// Bit mask of OVRC field.
	SPI1_SPI2S_IFCR_OVRC_Msk = 0x40
	// Bit OVRC.
	SPI1_SPI2S_IFCR_OVRC = 0x40
	// Position of CRCEC field.
	SPI1_SPI2S_IFCR_CRCEC_Pos = 0x7
	// Bit mask of CRCEC field.
	SPI1_SPI2S_IFCR_CRCEC_Msk = 0x80
	// Bit CRCEC.
	SPI1_SPI2S_IFCR_CRCEC = 0x80
	// Position of TIFREC field.
	SPI1_SPI2S_IFCR_TIFREC_Pos = 0x8
	// Bit mask of TIFREC field.
	SPI1_SPI2S_IFCR_TIFREC_Msk = 0x100
	// Bit TIFREC.
	SPI1_SPI2S_IFCR_TIFREC = 0x100
	// Position of MODFC field.
	SPI1_SPI2S_IFCR_MODFC_Pos = 0x9
	// Bit mask of MODFC field.
	SPI1_SPI2S_IFCR_MODFC_Msk = 0x200
	// Bit MODFC.
	SPI1_SPI2S_IFCR_MODFC = 0x200
	// Position of TSERFC field.
	SPI1_SPI2S_IFCR_TSERFC_Pos = 0xa
	// Bit mask of TSERFC field.
	SPI1_SPI2S_IFCR_TSERFC_Msk = 0x400
	// Bit TSERFC.
	SPI1_SPI2S_IFCR_TSERFC = 0x400
	// Position of SUSPC field.
	SPI1_SPI2S_IFCR_SUSPC_Pos = 0xb
	// Bit mask of SUSPC field.
	SPI1_SPI2S_IFCR_SUSPC_Msk = 0x800
	// Bit SUSPC.
	SPI1_SPI2S_IFCR_SUSPC = 0x800

	// SPI2S_TXDR: SPI/I2S transmit data register
	// Position of TXDR field.
	SPI1_SPI2S_TXDR_TXDR_Pos = 0x0
	// Bit mask of TXDR field.
	SPI1_SPI2S_TXDR_TXDR_Msk = 0xffffffff

	// SPI2S_RXDR: SPI/I2S receive data register
	// Position of RXDR field.
	SPI1_SPI2S_RXDR_RXDR_Pos = 0x0
	// Bit mask of RXDR field.
	SPI1_SPI2S_RXDR_RXDR_Msk = 0xffffffff

	// SPI_CRCPOLY: SPI polynomial register
	// Position of CRCPOLY field.
	SPI1_SPI_CRCPOLY_CRCPOLY_Pos = 0x0
	// Bit mask of CRCPOLY field.
	SPI1_SPI_CRCPOLY_CRCPOLY_Msk = 0xffffffff

	// SPI_TXCRC: SPI transmitter CRC register
	// Position of TXCRC field.
	SPI1_SPI_TXCRC_TXCRC_Pos = 0x0
	// Bit mask of TXCRC field.
	SPI1_SPI_TXCRC_TXCRC_Msk = 0xffffffff

	// SPI_RXCRC: SPI receiver CRC register
	// Position of RXCRC field.
	SPI1_SPI_RXCRC_RXCRC_Pos = 0x0
	// Bit mask of RXCRC field.
	SPI1_SPI_RXCRC_RXCRC_Msk = 0xffffffff

	// SPI_UDRDR: SPI underrun data register
	// Position of UDRDR field.
	SPI1_SPI_UDRDR_UDRDR_Pos = 0x0
	// Bit mask of UDRDR field.
	SPI1_SPI_UDRDR_UDRDR_Msk = 0xffffffff

	// SPI_I2SCFGR: All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.
	// Position of I2SMOD field.
	SPI1_SPI_I2SCFGR_I2SMOD_Pos = 0x0
	// Bit mask of I2SMOD field.
	SPI1_SPI_I2SCFGR_I2SMOD_Msk = 0x1
	// Bit I2SMOD.
	SPI1_SPI_I2SCFGR_I2SMOD = 0x1
	// Position of I2SCFG field.
	SPI1_SPI_I2SCFGR_I2SCFG_Pos = 0x1
	// Bit mask of I2SCFG field.
	SPI1_SPI_I2SCFGR_I2SCFG_Msk = 0xe
	// Position of I2SSTD field.
	SPI1_SPI_I2SCFGR_I2SSTD_Pos = 0x4
	// Bit mask of I2SSTD field.
	SPI1_SPI_I2SCFGR_I2SSTD_Msk = 0x30
	// Position of PCMSYNC field.
	SPI1_SPI_I2SCFGR_PCMSYNC_Pos = 0x7
	// Bit mask of PCMSYNC field.
	SPI1_SPI_I2SCFGR_PCMSYNC_Msk = 0x80
	// Bit PCMSYNC.
	SPI1_SPI_I2SCFGR_PCMSYNC = 0x80
	// Position of DATLEN field.
	SPI1_SPI_I2SCFGR_DATLEN_Pos = 0x8
	// Bit mask of DATLEN field.
	SPI1_SPI_I2SCFGR_DATLEN_Msk = 0x300
	// Position of CHLEN field.
	SPI1_SPI_I2SCFGR_CHLEN_Pos = 0xa
	// Bit mask of CHLEN field.
	SPI1_SPI_I2SCFGR_CHLEN_Msk = 0x400
	// Bit CHLEN.
	SPI1_SPI_I2SCFGR_CHLEN = 0x400
	// Position of CKPOL field.
	SPI1_SPI_I2SCFGR_CKPOL_Pos = 0xb
	// Bit mask of CKPOL field.
	SPI1_SPI_I2SCFGR_CKPOL_Msk = 0x800
	// Bit CKPOL.
	SPI1_SPI_I2SCFGR_CKPOL = 0x800
	// Position of FIXCH field.
	SPI1_SPI_I2SCFGR_FIXCH_Pos = 0xc
	// Bit mask of FIXCH field.
	SPI1_SPI_I2SCFGR_FIXCH_Msk = 0x1000
	// Bit FIXCH.
	SPI1_SPI_I2SCFGR_FIXCH = 0x1000
	// Position of WSINV field.
	SPI1_SPI_I2SCFGR_WSINV_Pos = 0xd
	// Bit mask of WSINV field.
	SPI1_SPI_I2SCFGR_WSINV_Msk = 0x2000
	// Bit WSINV.
	SPI1_SPI_I2SCFGR_WSINV = 0x2000
	// Position of DATFMT field.
	SPI1_SPI_I2SCFGR_DATFMT_Pos = 0xe
	// Bit mask of DATFMT field.
	SPI1_SPI_I2SCFGR_DATFMT_Msk = 0x4000
	// Bit DATFMT.
	SPI1_SPI_I2SCFGR_DATFMT = 0x4000
	// Position of I2SDIV field.
	SPI1_SPI_I2SCFGR_I2SDIV_Pos = 0x10
	// Bit mask of I2SDIV field.
	SPI1_SPI_I2SCFGR_I2SDIV_Msk = 0xff0000
	// Position of ODD field.
	SPI1_SPI_I2SCFGR_ODD_Pos = 0x18
	// Bit mask of ODD field.
	SPI1_SPI_I2SCFGR_ODD_Msk = 0x1000000
	// Bit ODD.
	SPI1_SPI_I2SCFGR_ODD = 0x1000000
	// Position of MCKOE field.
	SPI1_SPI_I2SCFGR_MCKOE_Pos = 0x19
	// Bit mask of MCKOE field.
	SPI1_SPI_I2SCFGR_MCKOE_Msk = 0x2000000
	// Bit MCKOE.
	SPI1_SPI_I2SCFGR_MCKOE = 0x2000000

	// SPI_I2S_HWCFGR: SPI/I2S hardware configuration register
	// Position of TXFCFG field.
	SPI1_SPI_I2S_HWCFGR_TXFCFG_Pos = 0x0
	// Bit mask of TXFCFG field.
	SPI1_SPI_I2S_HWCFGR_TXFCFG_Msk = 0xf
	// Position of RXFCFG field.
	SPI1_SPI_I2S_HWCFGR_RXFCFG_Pos = 0x4
	// Bit mask of RXFCFG field.
	SPI1_SPI_I2S_HWCFGR_RXFCFG_Msk = 0xf0
	// Position of CRCCFG field.
	SPI1_SPI_I2S_HWCFGR_CRCCFG_Pos = 0x8
	// Bit mask of CRCCFG field.
	SPI1_SPI_I2S_HWCFGR_CRCCFG_Msk = 0xf00
	// Position of I2SCFG field.
	SPI1_SPI_I2S_HWCFGR_I2SCFG_Pos = 0xc
	// Bit mask of I2SCFG field.
	SPI1_SPI_I2S_HWCFGR_I2SCFG_Msk = 0xf000
	// Position of DSCFG field.
	SPI1_SPI_I2S_HWCFGR_DSCFG_Pos = 0x10
	// Bit mask of DSCFG field.
	SPI1_SPI_I2S_HWCFGR_DSCFG_Msk = 0xf0000

	// SPI_VERR: SPI/I2S version register
	// Position of MINREV field.
	SPI1_SPI_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	SPI1_SPI_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	SPI1_SPI_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	SPI1_SPI_VERR_MAJREV_Msk = 0xf0

	// SPI_IPIDR: SPI/I2S identification register
	// Position of ID field.
	SPI1_SPI_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	SPI1_SPI_IPIDR_ID_Msk = 0xffffffff

	// SPI_SIDR: SPI/I2S size identification register
	// Position of SID field.
	SPI1_SPI_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	SPI1_SPI_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for STGENC: STGENC
const (
	// STGENC_CNTCR: STGENC control register
	// Position of EN field.
	STGENC_STGENC_CNTCR_EN_Pos = 0x0
	// Bit mask of EN field.
	STGENC_STGENC_CNTCR_EN_Msk = 0x1
	// Bit EN.
	STGENC_STGENC_CNTCR_EN = 0x1
	// Position of HLTDBG field.
	STGENC_STGENC_CNTCR_HLTDBG_Pos = 0x1
	// Bit mask of HLTDBG field.
	STGENC_STGENC_CNTCR_HLTDBG_Msk = 0x2
	// Bit HLTDBG.
	STGENC_STGENC_CNTCR_HLTDBG = 0x2

	// STGENC_CNTSR: STGENC status register
	// Position of EN field.
	STGENC_STGENC_CNTSR_EN_Pos = 0x0
	// Bit mask of EN field.
	STGENC_STGENC_CNTSR_EN_Msk = 0x1
	// Bit EN.
	STGENC_STGENC_CNTSR_EN = 0x1
	// Position of HLTDBG field.
	STGENC_STGENC_CNTSR_HLTDBG_Pos = 0x1
	// Bit mask of HLTDBG field.
	STGENC_STGENC_CNTSR_HLTDBG_Msk = 0x2
	// Bit HLTDBG.
	STGENC_STGENC_CNTSR_HLTDBG = 0x2

	// STGENC_CNTCVL: the control interface must clear the STGENC_CNTCR.EN bit before writing to this register.
	// Position of CNTCVL_L_32 field.
	STGENC_STGENC_CNTCVL_CNTCVL_L_32_Pos = 0x0
	// Bit mask of CNTCVL_L_32 field.
	STGENC_STGENC_CNTCVL_CNTCVL_L_32_Msk = 0xffffffff

	// STGENC_CNTCVU: the control interface must clear the STGENC_CNTCR.EN bit before writing to this register.
	// Position of CNTCVU_U_32 field.
	STGENC_STGENC_CNTCVU_CNTCVU_U_32_Pos = 0x0
	// Bit mask of CNTCVU_U_32 field.
	STGENC_STGENC_CNTCVU_CNTCVU_U_32_Msk = 0xffffffff

	// STGENC_CNTFID0: the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.
	// Position of FREQ field.
	STGENC_STGENC_CNTFID0_FREQ_Pos = 0x0
	// Bit mask of FREQ field.
	STGENC_STGENC_CNTFID0_FREQ_Msk = 0xffffffff

	// STGENC_PIDR4: STGENC peripheral ID4 register
	// Position of DES_2 field.
	STGENC_STGENC_PIDR4_DES_2_Pos = 0x0
	// Bit mask of DES_2 field.
	STGENC_STGENC_PIDR4_DES_2_Msk = 0xf
	// Position of SIZE field.
	STGENC_STGENC_PIDR4_SIZE_Pos = 0x4
	// Bit mask of SIZE field.
	STGENC_STGENC_PIDR4_SIZE_Msk = 0xf0

	// STGENC_PIDR5: STGENC peripheral ID5 register
	// Position of PIDR5 field.
	STGENC_STGENC_PIDR5_PIDR5_Pos = 0x0
	// Bit mask of PIDR5 field.
	STGENC_STGENC_PIDR5_PIDR5_Msk = 0xffffffff

	// STGENC_PIDR6: STGENC peripheral ID6 register
	// Position of PIDR6 field.
	STGENC_STGENC_PIDR6_PIDR6_Pos = 0x0
	// Bit mask of PIDR6 field.
	STGENC_STGENC_PIDR6_PIDR6_Msk = 0xffffffff

	// STGENC_PIDR7: STGENC peripheral ID7 register
	// Position of PIDR7 field.
	STGENC_STGENC_PIDR7_PIDR7_Pos = 0x0
	// Bit mask of PIDR7 field.
	STGENC_STGENC_PIDR7_PIDR7_Msk = 0xffffffff

	// STGENC_PIDR0: STGENC peripheral ID0 register
	// Position of PART_0 field.
	STGENC_STGENC_PIDR0_PART_0_Pos = 0x0
	// Bit mask of PART_0 field.
	STGENC_STGENC_PIDR0_PART_0_Msk = 0xff

	// STGENC_PIDR1: STGENC peripheral ID1 register
	// Position of PART_1 field.
	STGENC_STGENC_PIDR1_PART_1_Pos = 0x0
	// Bit mask of PART_1 field.
	STGENC_STGENC_PIDR1_PART_1_Msk = 0xf
	// Position of DES_0 field.
	STGENC_STGENC_PIDR1_DES_0_Pos = 0x4
	// Bit mask of DES_0 field.
	STGENC_STGENC_PIDR1_DES_0_Msk = 0xf0

	// STGENC_PIDR2: STGENC peripheral ID2 register
	// Position of DES_1 field.
	STGENC_STGENC_PIDR2_DES_1_Pos = 0x0
	// Bit mask of DES_1 field.
	STGENC_STGENC_PIDR2_DES_1_Msk = 0x7
	// Position of JEDEC field.
	STGENC_STGENC_PIDR2_JEDEC_Pos = 0x3
	// Bit mask of JEDEC field.
	STGENC_STGENC_PIDR2_JEDEC_Msk = 0x8
	// Bit JEDEC.
	STGENC_STGENC_PIDR2_JEDEC = 0x8
	// Position of REVISION field.
	STGENC_STGENC_PIDR2_REVISION_Pos = 0x4
	// Bit mask of REVISION field.
	STGENC_STGENC_PIDR2_REVISION_Msk = 0xf0

	// STGENC_PIDR3: STGENC peripheral ID3 register
	// Position of CMOD field.
	STGENC_STGENC_PIDR3_CMOD_Pos = 0x0
	// Bit mask of CMOD field.
	STGENC_STGENC_PIDR3_CMOD_Msk = 0xf
	// Position of REVAND field.
	STGENC_STGENC_PIDR3_REVAND_Pos = 0x4
	// Bit mask of REVAND field.
	STGENC_STGENC_PIDR3_REVAND_Msk = 0xf0

	// STGENC_CIDR0: STGENC component ID0 register
	// Position of PRMBL_0 field.
	STGENC_STGENC_CIDR0_PRMBL_0_Pos = 0x0
	// Bit mask of PRMBL_0 field.
	STGENC_STGENC_CIDR0_PRMBL_0_Msk = 0xff

	// STGENC_CIDR1: STGENC component ID1 register
	// Position of PRMBL_1 field.
	STGENC_STGENC_CIDR1_PRMBL_1_Pos = 0x0
	// Bit mask of PRMBL_1 field.
	STGENC_STGENC_CIDR1_PRMBL_1_Msk = 0xf
	// Position of CLASS field.
	STGENC_STGENC_CIDR1_CLASS_Pos = 0x4
	// Bit mask of CLASS field.
	STGENC_STGENC_CIDR1_CLASS_Msk = 0xf0

	// STGENC_CIDR2: STGENC component ID2 register
	// Position of PRMBL_2 field.
	STGENC_STGENC_CIDR2_PRMBL_2_Pos = 0x0
	// Bit mask of PRMBL_2 field.
	STGENC_STGENC_CIDR2_PRMBL_2_Msk = 0xff

	// STGENC_CIDR3: STGENC component ID3 register
	// Position of PRMBL_3 field.
	STGENC_STGENC_CIDR3_PRMBL_3_Pos = 0x0
	// Bit mask of PRMBL_3 field.
	STGENC_STGENC_CIDR3_PRMBL_3_Msk = 0xff
)

// Bitfields for STGENR: STGENR
const (
	// STGENR_CNTCVL: the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.
	// Position of CNTCVL_L_32 field.
	STGENR_STGENR_CNTCVL_CNTCVL_L_32_Pos = 0x0
	// Bit mask of CNTCVL_L_32 field.
	STGENR_STGENR_CNTCVL_CNTCVL_L_32_Msk = 0xffffffff

	// STGENR_CNTCVU: the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.
	// Position of CNTCVU_U_32 field.
	STGENR_STGENR_CNTCVU_CNTCVU_U_32_Pos = 0x0
	// Bit mask of CNTCVU_U_32 field.
	STGENR_STGENR_CNTCVU_CNTCVU_U_32_Msk = 0xffffffff

	// STGENR_PIDR4: STGENR peripheral ID4 register
	// Position of DES_2 field.
	STGENR_STGENR_PIDR4_DES_2_Pos = 0x0
	// Bit mask of DES_2 field.
	STGENR_STGENR_PIDR4_DES_2_Msk = 0xf
	// Position of SIZE field.
	STGENR_STGENR_PIDR4_SIZE_Pos = 0x4
	// Bit mask of SIZE field.
	STGENR_STGENR_PIDR4_SIZE_Msk = 0xf0

	// STGENR_PIDR5: STGENR peripheral ID5 register
	// Position of PIDR5 field.
	STGENR_STGENR_PIDR5_PIDR5_Pos = 0x0
	// Bit mask of PIDR5 field.
	STGENR_STGENR_PIDR5_PIDR5_Msk = 0xffffffff

	// STGENR_PIDR6: STGENR peripheral ID6 register
	// Position of PIDR6 field.
	STGENR_STGENR_PIDR6_PIDR6_Pos = 0x0
	// Bit mask of PIDR6 field.
	STGENR_STGENR_PIDR6_PIDR6_Msk = 0xffffffff

	// STGENR_PIDR7: STGENR peripheral ID7 register
	// Position of PIDR7 field.
	STGENR_STGENR_PIDR7_PIDR7_Pos = 0x0
	// Bit mask of PIDR7 field.
	STGENR_STGENR_PIDR7_PIDR7_Msk = 0xffffffff

	// STGENR_PIDR0: STGENR peripheral ID0 register
	// Position of PART_0 field.
	STGENR_STGENR_PIDR0_PART_0_Pos = 0x0
	// Bit mask of PART_0 field.
	STGENR_STGENR_PIDR0_PART_0_Msk = 0xff

	// STGENR_PIDR1: STGENR peripheral ID1 register
	// Position of PART_1 field.
	STGENR_STGENR_PIDR1_PART_1_Pos = 0x0
	// Bit mask of PART_1 field.
	STGENR_STGENR_PIDR1_PART_1_Msk = 0xf
	// Position of DES_0 field.
	STGENR_STGENR_PIDR1_DES_0_Pos = 0x4
	// Bit mask of DES_0 field.
	STGENR_STGENR_PIDR1_DES_0_Msk = 0xf0

	// STGENR_PIDR2: STGENR peripheral ID2 register
	// Position of DES_1 field.
	STGENR_STGENR_PIDR2_DES_1_Pos = 0x0
	// Bit mask of DES_1 field.
	STGENR_STGENR_PIDR2_DES_1_Msk = 0x7
	// Position of JEDEC field.
	STGENR_STGENR_PIDR2_JEDEC_Pos = 0x3
	// Bit mask of JEDEC field.
	STGENR_STGENR_PIDR2_JEDEC_Msk = 0x8
	// Bit JEDEC.
	STGENR_STGENR_PIDR2_JEDEC = 0x8
	// Position of REVISION field.
	STGENR_STGENR_PIDR2_REVISION_Pos = 0x4
	// Bit mask of REVISION field.
	STGENR_STGENR_PIDR2_REVISION_Msk = 0xf0

	// STGENR_PIDR3: STGENR peripheral ID3 register
	// Position of CMOD field.
	STGENR_STGENR_PIDR3_CMOD_Pos = 0x0
	// Bit mask of CMOD field.
	STGENR_STGENR_PIDR3_CMOD_Msk = 0xf
	// Position of REVAND field.
	STGENR_STGENR_PIDR3_REVAND_Pos = 0x4
	// Bit mask of REVAND field.
	STGENR_STGENR_PIDR3_REVAND_Msk = 0xf0

	// STGENR_CIDR0: STGENR component ID0 register
	// Position of PRMBL_0 field.
	STGENR_STGENR_CIDR0_PRMBL_0_Pos = 0x0
	// Bit mask of PRMBL_0 field.
	STGENR_STGENR_CIDR0_PRMBL_0_Msk = 0xff

	// STGENR_CIDR1: STGENR component ID1 register
	// Position of PRMBL_1 field.
	STGENR_STGENR_CIDR1_PRMBL_1_Pos = 0x0
	// Bit mask of PRMBL_1 field.
	STGENR_STGENR_CIDR1_PRMBL_1_Msk = 0xf
	// Position of CLASS field.
	STGENR_STGENR_CIDR1_CLASS_Pos = 0x4
	// Bit mask of CLASS field.
	STGENR_STGENR_CIDR1_CLASS_Msk = 0xf0

	// STGENR_CIDR2: STGENR component ID2 register
	// Position of PRMBL_2 field.
	STGENR_STGENR_CIDR2_PRMBL_2_Pos = 0x0
	// Bit mask of PRMBL_2 field.
	STGENR_STGENR_CIDR2_PRMBL_2_Msk = 0xff

	// STGENR_CIDR3: STGENR component ID3 register
	// Position of PRMBL_3 field.
	STGENR_STGENR_CIDR3_PRMBL_3_Pos = 0x0
	// Bit mask of PRMBL_3 field.
	STGENR_STGENR_CIDR3_PRMBL_3_Msk = 0xff
)

// Bitfields for SYSCFG: SYSCFG
const (
	// SYSCFG_BOOTR: This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. )
	// Position of BOOT0 field.
	SYSCFG_SYSCFG_BOOTR_BOOT0_Pos = 0x0
	// Bit mask of BOOT0 field.
	SYSCFG_SYSCFG_BOOTR_BOOT0_Msk = 0x1
	// Bit BOOT0.
	SYSCFG_SYSCFG_BOOTR_BOOT0 = 0x1
	// Position of BOOT1 field.
	SYSCFG_SYSCFG_BOOTR_BOOT1_Pos = 0x1
	// Bit mask of BOOT1 field.
	SYSCFG_SYSCFG_BOOTR_BOOT1_Msk = 0x2
	// Bit BOOT1.
	SYSCFG_SYSCFG_BOOTR_BOOT1 = 0x2
	// Position of BOOT2 field.
	SYSCFG_SYSCFG_BOOTR_BOOT2_Pos = 0x2
	// Bit mask of BOOT2 field.
	SYSCFG_SYSCFG_BOOTR_BOOT2_Msk = 0x4
	// Bit BOOT2.
	SYSCFG_SYSCFG_BOOTR_BOOT2 = 0x4
	// Position of BOOT0_PD field.
	SYSCFG_SYSCFG_BOOTR_BOOT0_PD_Pos = 0x4
	// Bit mask of BOOT0_PD field.
	SYSCFG_SYSCFG_BOOTR_BOOT0_PD_Msk = 0x10
	// Bit BOOT0_PD.
	SYSCFG_SYSCFG_BOOTR_BOOT0_PD = 0x10
	// Position of BOOT1_PD field.
	SYSCFG_SYSCFG_BOOTR_BOOT1_PD_Pos = 0x5
	// Bit mask of BOOT1_PD field.
	SYSCFG_SYSCFG_BOOTR_BOOT1_PD_Msk = 0x20
	// Bit BOOT1_PD.
	SYSCFG_SYSCFG_BOOTR_BOOT1_PD = 0x20
	// Position of BOOT2_PD field.
	SYSCFG_SYSCFG_BOOTR_BOOT2_PD_Pos = 0x6
	// Bit mask of BOOT2_PD field.
	SYSCFG_SYSCFG_BOOTR_BOOT2_PD_Msk = 0x40
	// Bit BOOT2_PD.
	SYSCFG_SYSCFG_BOOTR_BOOT2_PD = 0x40

	// SYSCFG_PMCSETR: SYSCFG peripheral mode configuration set register
	// Position of I2C1_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C1_FMP_Pos = 0x0
	// Bit mask of I2C1_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C1_FMP_Msk = 0x1
	// Bit I2C1_FMP.
	SYSCFG_SYSCFG_PMCSETR_I2C1_FMP = 0x1
	// Position of I2C2_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C2_FMP_Pos = 0x1
	// Bit mask of I2C2_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C2_FMP_Msk = 0x2
	// Bit I2C2_FMP.
	SYSCFG_SYSCFG_PMCSETR_I2C2_FMP = 0x2
	// Position of I2C3_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C3_FMP_Pos = 0x2
	// Bit mask of I2C3_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C3_FMP_Msk = 0x4
	// Bit I2C3_FMP.
	SYSCFG_SYSCFG_PMCSETR_I2C3_FMP = 0x4
	// Position of I2C4_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C4_FMP_Pos = 0x3
	// Bit mask of I2C4_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C4_FMP_Msk = 0x8
	// Bit I2C4_FMP.
	SYSCFG_SYSCFG_PMCSETR_I2C4_FMP = 0x8
	// Position of I2C5_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C5_FMP_Pos = 0x4
	// Bit mask of I2C5_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C5_FMP_Msk = 0x10
	// Bit I2C5_FMP.
	SYSCFG_SYSCFG_PMCSETR_I2C5_FMP = 0x10
	// Position of I2C6_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C6_FMP_Pos = 0x5
	// Bit mask of I2C6_FMP field.
	SYSCFG_SYSCFG_PMCSETR_I2C6_FMP_Msk = 0x20
	// Bit I2C6_FMP.
	SYSCFG_SYSCFG_PMCSETR_I2C6_FMP = 0x20
	// Position of EN_BOOSTER field.
	SYSCFG_SYSCFG_PMCSETR_EN_BOOSTER_Pos = 0x8
	// Bit mask of EN_BOOSTER field.
	SYSCFG_SYSCFG_PMCSETR_EN_BOOSTER_Msk = 0x100
	// Bit EN_BOOSTER.
	SYSCFG_SYSCFG_PMCSETR_EN_BOOSTER = 0x100
	// Position of ANASWVDD field.
	SYSCFG_SYSCFG_PMCSETR_ANASWVDD_Pos = 0x9
	// Bit mask of ANASWVDD field.
	SYSCFG_SYSCFG_PMCSETR_ANASWVDD_Msk = 0x200
	// Bit ANASWVDD.
	SYSCFG_SYSCFG_PMCSETR_ANASWVDD = 0x200
	// Position of ETH_CLK_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ETH_CLK_SEL_Pos = 0x10
	// Bit mask of ETH_CLK_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ETH_CLK_SEL_Msk = 0x10000
	// Bit ETH_CLK_SEL.
	SYSCFG_SYSCFG_PMCSETR_ETH_CLK_SEL = 0x10000
	// Position of ETH_REF_CLK_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos = 0x11
	// Bit mask of ETH_REF_CLK_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk = 0x20000
	// Bit ETH_REF_CLK_SEL.
	SYSCFG_SYSCFG_PMCSETR_ETH_REF_CLK_SEL = 0x20000
	// Position of ETH_SELMII field.
	SYSCFG_SYSCFG_PMCSETR_ETH_SELMII_Pos = 0x14
	// Bit mask of ETH_SELMII field.
	SYSCFG_SYSCFG_PMCSETR_ETH_SELMII_Msk = 0x100000
	// Bit ETH_SELMII.
	SYSCFG_SYSCFG_PMCSETR_ETH_SELMII = 0x100000
	// Position of ETH_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ETH_SEL_Pos = 0x15
	// Bit mask of ETH_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ETH_SEL_Msk = 0xe00000
	// Position of ANA0_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ANA0_SEL_Pos = 0x18
	// Bit mask of ANA0_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ANA0_SEL_Msk = 0x1000000
	// Bit ANA0_SEL.
	SYSCFG_SYSCFG_PMCSETR_ANA0_SEL = 0x1000000
	// Position of ANA1_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ANA1_SEL_Pos = 0x19
	// Bit mask of ANA1_SEL field.
	SYSCFG_SYSCFG_PMCSETR_ANA1_SEL_Msk = 0x2000000
	// Bit ANA1_SEL.
	SYSCFG_SYSCFG_PMCSETR_ANA1_SEL = 0x2000000

	// SYSCFG_IOCTRLSETR: SYSCFG IO control register
	// Position of HSLVEN_TRACE field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos = 0x0
	// Bit mask of HSLVEN_TRACE field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk = 0x1
	// Bit HSLVEN_TRACE.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_TRACE = 0x1
	// Position of HSLVEN_QUADSPI field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos = 0x1
	// Bit mask of HSLVEN_QUADSPI field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk = 0x2
	// Bit HSLVEN_QUADSPI.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI = 0x2
	// Position of HSLVEN_ETH field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos = 0x2
	// Bit mask of HSLVEN_ETH field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk = 0x4
	// Bit HSLVEN_ETH.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_ETH = 0x4
	// Position of HSLVEN_SDMMC field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos = 0x3
	// Bit mask of HSLVEN_SDMMC field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk = 0x8
	// Bit HSLVEN_SDMMC.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_SDMMC = 0x8
	// Position of HSLVEN_SPI field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos = 0x4
	// Bit mask of HSLVEN_SPI field.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk = 0x10
	// Bit HSLVEN_SPI.
	SYSCFG_SYSCFG_IOCTRLSETR_HSLVEN_SPI = 0x10

	// SYSCFG_ICNR: SYSCFG interconnect control register
	// Position of AXI_M0 field.
	SYSCFG_SYSCFG_ICNR_AXI_M0_Pos = 0x0
	// Bit mask of AXI_M0 field.
	SYSCFG_SYSCFG_ICNR_AXI_M0_Msk = 0x1
	// Bit AXI_M0.
	SYSCFG_SYSCFG_ICNR_AXI_M0 = 0x1
	// Position of AXI_M1 field.
	SYSCFG_SYSCFG_ICNR_AXI_M1_Pos = 0x1
	// Bit mask of AXI_M1 field.
	SYSCFG_SYSCFG_ICNR_AXI_M1_Msk = 0x2
	// Bit AXI_M1.
	SYSCFG_SYSCFG_ICNR_AXI_M1 = 0x2
	// Position of AXI_M2 field.
	SYSCFG_SYSCFG_ICNR_AXI_M2_Pos = 0x2
	// Bit mask of AXI_M2 field.
	SYSCFG_SYSCFG_ICNR_AXI_M2_Msk = 0x4
	// Bit AXI_M2.
	SYSCFG_SYSCFG_ICNR_AXI_M2 = 0x4
	// Position of AXI_M3 field.
	SYSCFG_SYSCFG_ICNR_AXI_M3_Pos = 0x3
	// Bit mask of AXI_M3 field.
	SYSCFG_SYSCFG_ICNR_AXI_M3_Msk = 0x8
	// Bit AXI_M3.
	SYSCFG_SYSCFG_ICNR_AXI_M3 = 0x8
	// Position of AXI_M5 field.
	SYSCFG_SYSCFG_ICNR_AXI_M5_Pos = 0x5
	// Bit mask of AXI_M5 field.
	SYSCFG_SYSCFG_ICNR_AXI_M5_Msk = 0x20
	// Bit AXI_M5.
	SYSCFG_SYSCFG_ICNR_AXI_M5 = 0x20
	// Position of AXI_M6 field.
	SYSCFG_SYSCFG_ICNR_AXI_M6_Pos = 0x6
	// Bit mask of AXI_M6 field.
	SYSCFG_SYSCFG_ICNR_AXI_M6_Msk = 0x40
	// Bit AXI_M6.
	SYSCFG_SYSCFG_ICNR_AXI_M6 = 0x40
	// Position of AXI_M7 field.
	SYSCFG_SYSCFG_ICNR_AXI_M7_Pos = 0x7
	// Bit mask of AXI_M7 field.
	SYSCFG_SYSCFG_ICNR_AXI_M7_Msk = 0x80
	// Bit AXI_M7.
	SYSCFG_SYSCFG_ICNR_AXI_M7 = 0x80
	// Position of AXI_M8 field.
	SYSCFG_SYSCFG_ICNR_AXI_M8_Pos = 0x8
	// Bit mask of AXI_M8 field.
	SYSCFG_SYSCFG_ICNR_AXI_M8_Msk = 0x100
	// Bit AXI_M8.
	SYSCFG_SYSCFG_ICNR_AXI_M8 = 0x100
	// Position of AXI_M9 field.
	SYSCFG_SYSCFG_ICNR_AXI_M9_Pos = 0x9
	// Bit mask of AXI_M9 field.
	SYSCFG_SYSCFG_ICNR_AXI_M9_Msk = 0x200
	// Bit AXI_M9.
	SYSCFG_SYSCFG_ICNR_AXI_M9 = 0x200
	// Position of AXI_M10 field.
	SYSCFG_SYSCFG_ICNR_AXI_M10_Pos = 0xa
	// Bit mask of AXI_M10 field.
	SYSCFG_SYSCFG_ICNR_AXI_M10_Msk = 0x400
	// Bit AXI_M10.
	SYSCFG_SYSCFG_ICNR_AXI_M10 = 0x400

	// SYSCFG_CMPCR: SYSCFG compensation cell control register
	// Position of SW_CTRL field.
	SYSCFG_SYSCFG_CMPCR_SW_CTRL_Pos = 0x1
	// Bit mask of SW_CTRL field.
	SYSCFG_SYSCFG_CMPCR_SW_CTRL_Msk = 0x2
	// Bit SW_CTRL.
	SYSCFG_SYSCFG_CMPCR_SW_CTRL = 0x2
	// Position of READY field.
	SYSCFG_SYSCFG_CMPCR_READY_Pos = 0x8
	// Bit mask of READY field.
	SYSCFG_SYSCFG_CMPCR_READY_Msk = 0x100
	// Bit READY.
	SYSCFG_SYSCFG_CMPCR_READY = 0x100
	// Position of RANSRC field.
	SYSCFG_SYSCFG_CMPCR_RANSRC_Pos = 0x10
	// Bit mask of RANSRC field.
	SYSCFG_SYSCFG_CMPCR_RANSRC_Msk = 0xf0000
	// Position of RAPSRC field.
	SYSCFG_SYSCFG_CMPCR_RAPSRC_Pos = 0x14
	// Bit mask of RAPSRC field.
	SYSCFG_SYSCFG_CMPCR_RAPSRC_Msk = 0xf00000
	// Position of ANSRC field.
	SYSCFG_SYSCFG_CMPCR_ANSRC_Pos = 0x18
	// Bit mask of ANSRC field.
	SYSCFG_SYSCFG_CMPCR_ANSRC_Msk = 0xf000000
	// Position of APSRC field.
	SYSCFG_SYSCFG_CMPCR_APSRC_Pos = 0x1c
	// Bit mask of APSRC field.
	SYSCFG_SYSCFG_CMPCR_APSRC_Msk = 0xf0000000

	// SYSCFG_CMPENSETR: SYSCFG compensation cell enable set register
	// Position of MPU_EN field.
	SYSCFG_SYSCFG_CMPENSETR_MPU_EN_Pos = 0x0
	// Bit mask of MPU_EN field.
	SYSCFG_SYSCFG_CMPENSETR_MPU_EN_Msk = 0x1
	// Bit MPU_EN.
	SYSCFG_SYSCFG_CMPENSETR_MPU_EN = 0x1
	// Position of MCU_EN field.
	SYSCFG_SYSCFG_CMPENSETR_MCU_EN_Pos = 0x1
	// Bit mask of MCU_EN field.
	SYSCFG_SYSCFG_CMPENSETR_MCU_EN_Msk = 0x2
	// Bit MCU_EN.
	SYSCFG_SYSCFG_CMPENSETR_MCU_EN = 0x2

	// SYSCFG_CMPENCLRR: SYSCFG compensation cell enable set register
	// Position of MPU_EN field.
	SYSCFG_SYSCFG_CMPENCLRR_MPU_EN_Pos = 0x0
	// Bit mask of MPU_EN field.
	SYSCFG_SYSCFG_CMPENCLRR_MPU_EN_Msk = 0x1
	// Bit MPU_EN.
	SYSCFG_SYSCFG_CMPENCLRR_MPU_EN = 0x1
	// Position of MCU_EN field.
	SYSCFG_SYSCFG_CMPENCLRR_MCU_EN_Pos = 0x1
	// Bit mask of MCU_EN field.
	SYSCFG_SYSCFG_CMPENCLRR_MCU_EN_Msk = 0x2
	// Bit MCU_EN.
	SYSCFG_SYSCFG_CMPENCLRR_MCU_EN = 0x2

	// SYSCFG_CBR: SYSCFG control timer break register
	// Position of CLL field.
	SYSCFG_SYSCFG_CBR_CLL_Pos = 0x0
	// Bit mask of CLL field.
	SYSCFG_SYSCFG_CBR_CLL_Msk = 0x1
	// Bit CLL.
	SYSCFG_SYSCFG_CBR_CLL = 0x1
	// Position of PVDL field.
	SYSCFG_SYSCFG_CBR_PVDL_Pos = 0x2
	// Bit mask of PVDL field.
	SYSCFG_SYSCFG_CBR_PVDL_Msk = 0x4
	// Bit PVDL.
	SYSCFG_SYSCFG_CBR_PVDL = 0x4

	// SYSCFG_PMCCLRR: SYSCFG peripheral mode configuration clear register
	// Position of I2C1_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C1_FMP_Pos = 0x0
	// Bit mask of I2C1_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C1_FMP_Msk = 0x1
	// Bit I2C1_FMP.
	SYSCFG_SYSCFG_PMCCLRR_I2C1_FMP = 0x1
	// Position of I2C2_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C2_FMP_Pos = 0x1
	// Bit mask of I2C2_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C2_FMP_Msk = 0x2
	// Bit I2C2_FMP.
	SYSCFG_SYSCFG_PMCCLRR_I2C2_FMP = 0x2
	// Position of I2C3_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C3_FMP_Pos = 0x2
	// Bit mask of I2C3_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C3_FMP_Msk = 0x4
	// Bit I2C3_FMP.
	SYSCFG_SYSCFG_PMCCLRR_I2C3_FMP = 0x4
	// Position of I2C4_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C4_FMP_Pos = 0x3
	// Bit mask of I2C4_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C4_FMP_Msk = 0x8
	// Bit I2C4_FMP.
	SYSCFG_SYSCFG_PMCCLRR_I2C4_FMP = 0x8
	// Position of I2C5_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C5_FMP_Pos = 0x4
	// Bit mask of I2C5_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C5_FMP_Msk = 0x10
	// Bit I2C5_FMP.
	SYSCFG_SYSCFG_PMCCLRR_I2C5_FMP = 0x10
	// Position of I2C6_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C6_FMP_Pos = 0x5
	// Bit mask of I2C6_FMP field.
	SYSCFG_SYSCFG_PMCCLRR_I2C6_FMP_Msk = 0x20
	// Bit I2C6_FMP.
	SYSCFG_SYSCFG_PMCCLRR_I2C6_FMP = 0x20
	// Position of EN_BOOSTER field.
	SYSCFG_SYSCFG_PMCCLRR_EN_BOOSTER_Pos = 0x8
	// Bit mask of EN_BOOSTER field.
	SYSCFG_SYSCFG_PMCCLRR_EN_BOOSTER_Msk = 0x100
	// Bit EN_BOOSTER.
	SYSCFG_SYSCFG_PMCCLRR_EN_BOOSTER = 0x100
	// Position of ANASWVDD field.
	SYSCFG_SYSCFG_PMCCLRR_ANASWVDD_Pos = 0x9
	// Bit mask of ANASWVDD field.
	SYSCFG_SYSCFG_PMCCLRR_ANASWVDD_Msk = 0x200
	// Bit ANASWVDD.
	SYSCFG_SYSCFG_PMCCLRR_ANASWVDD = 0x200
	// Position of ETH_CLK_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_CLK_SEL_Pos = 0x10
	// Bit mask of ETH_CLK_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_CLK_SEL_Msk = 0x10000
	// Bit ETH_CLK_SEL.
	SYSCFG_SYSCFG_PMCCLRR_ETH_CLK_SEL = 0x10000
	// Position of ETH_REF_CLK_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos = 0x11
	// Bit mask of ETH_REF_CLK_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk = 0x20000
	// Bit ETH_REF_CLK_SEL.
	SYSCFG_SYSCFG_PMCCLRR_ETH_REF_CLK_SEL = 0x20000
	// Position of ETH_SELMII field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_SELMII_Pos = 0x14
	// Bit mask of ETH_SELMII field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_SELMII_Msk = 0x100000
	// Bit ETH_SELMII.
	SYSCFG_SYSCFG_PMCCLRR_ETH_SELMII = 0x100000
	// Position of ETH_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_SEL_Pos = 0x15
	// Bit mask of ETH_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ETH_SEL_Msk = 0xe00000
	// Position of ANA0_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ANA0_SEL_Pos = 0x18
	// Bit mask of ANA0_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ANA0_SEL_Msk = 0x1000000
	// Bit ANA0_SEL.
	SYSCFG_SYSCFG_PMCCLRR_ANA0_SEL = 0x1000000
	// Position of ANA1_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ANA1_SEL_Pos = 0x19
	// Bit mask of ANA1_SEL field.
	SYSCFG_SYSCFG_PMCCLRR_ANA1_SEL_Msk = 0x2000000
	// Bit ANA1_SEL.
	SYSCFG_SYSCFG_PMCCLRR_ANA1_SEL = 0x2000000

	// SYSCFG_IOCTRLCLRR: SYSCFG IO control register
	// Position of HSLVEN_TRACE field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos = 0x0
	// Bit mask of HSLVEN_TRACE field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk = 0x1
	// Bit HSLVEN_TRACE.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_TRACE = 0x1
	// Position of HSLVEN_QUADSPI field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos = 0x1
	// Bit mask of HSLVEN_QUADSPI field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk = 0x2
	// Bit HSLVEN_QUADSPI.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI = 0x2
	// Position of HSLVEN_ETH field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos = 0x2
	// Bit mask of HSLVEN_ETH field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk = 0x4
	// Bit HSLVEN_ETH.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_ETH = 0x4
	// Position of HSLVEN_SDMMC field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos = 0x3
	// Bit mask of HSLVEN_SDMMC field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk = 0x8
	// Bit HSLVEN_SDMMC.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC = 0x8
	// Position of HSLVEN_SPI field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos = 0x4
	// Bit mask of HSLVEN_SPI field.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk = 0x10
	// Bit HSLVEN_SPI.
	SYSCFG_SYSCFG_IOCTRLCLRR_HSLVEN_SPI = 0x10

	// SYSCFG_VERR: SYSCFG version register
	// Position of MINREV field.
	SYSCFG_SYSCFG_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	SYSCFG_SYSCFG_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	SYSCFG_SYSCFG_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	SYSCFG_SYSCFG_VERR_MAJREV_Msk = 0xf0

	// SYSCFG_IPIDR: SYSCFG identification register
	// Position of ID field.
	SYSCFG_SYSCFG_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	SYSCFG_SYSCFG_IPIDR_ID_Msk = 0xffffffff

	// SYSCFG_SIDR: SYSCFG size identification register
	// Position of SID field.
	SYSCFG_SYSCFG_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	SYSCFG_SYSCFG_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for TAMP: TAMP
const (
	// TAMP_CR1: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of TAMP1E field.
	TAMP_TAMP_CR1_TAMP1E_Pos = 0x0
	// Bit mask of TAMP1E field.
	TAMP_TAMP_CR1_TAMP1E_Msk = 0x1
	// Bit TAMP1E.
	TAMP_TAMP_CR1_TAMP1E = 0x1
	// Position of TAMP2E field.
	TAMP_TAMP_CR1_TAMP2E_Pos = 0x1
	// Bit mask of TAMP2E field.
	TAMP_TAMP_CR1_TAMP2E_Msk = 0x2
	// Bit TAMP2E.
	TAMP_TAMP_CR1_TAMP2E = 0x2
	// Position of TAMP3E field.
	TAMP_TAMP_CR1_TAMP3E_Pos = 0x2
	// Bit mask of TAMP3E field.
	TAMP_TAMP_CR1_TAMP3E_Msk = 0x4
	// Bit TAMP3E.
	TAMP_TAMP_CR1_TAMP3E = 0x4
	// Position of ITAMP1E field.
	TAMP_TAMP_CR1_ITAMP1E_Pos = 0x10
	// Bit mask of ITAMP1E field.
	TAMP_TAMP_CR1_ITAMP1E_Msk = 0x10000
	// Bit ITAMP1E.
	TAMP_TAMP_CR1_ITAMP1E = 0x10000
	// Position of ITAMP2E field.
	TAMP_TAMP_CR1_ITAMP2E_Pos = 0x11
	// Bit mask of ITAMP2E field.
	TAMP_TAMP_CR1_ITAMP2E_Msk = 0x20000
	// Bit ITAMP2E.
	TAMP_TAMP_CR1_ITAMP2E = 0x20000
	// Position of ITAMP3E field.
	TAMP_TAMP_CR1_ITAMP3E_Pos = 0x12
	// Bit mask of ITAMP3E field.
	TAMP_TAMP_CR1_ITAMP3E_Msk = 0x40000
	// Bit ITAMP3E.
	TAMP_TAMP_CR1_ITAMP3E = 0x40000
	// Position of ITAMP4E field.
	TAMP_TAMP_CR1_ITAMP4E_Pos = 0x13
	// Bit mask of ITAMP4E field.
	TAMP_TAMP_CR1_ITAMP4E_Msk = 0x80000
	// Bit ITAMP4E.
	TAMP_TAMP_CR1_ITAMP4E = 0x80000
	// Position of ITAMP5E field.
	TAMP_TAMP_CR1_ITAMP5E_Pos = 0x14
	// Bit mask of ITAMP5E field.
	TAMP_TAMP_CR1_ITAMP5E_Msk = 0x100000
	// Bit ITAMP5E.
	TAMP_TAMP_CR1_ITAMP5E = 0x100000
	// Position of ITAMP8E field.
	TAMP_TAMP_CR1_ITAMP8E_Pos = 0x17
	// Bit mask of ITAMP8E field.
	TAMP_TAMP_CR1_ITAMP8E_Msk = 0x800000
	// Bit ITAMP8E.
	TAMP_TAMP_CR1_ITAMP8E = 0x800000

	// TAMP_CR2: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of TAMP1NOER field.
	TAMP_TAMP_CR2_TAMP1NOER_Pos = 0x0
	// Bit mask of TAMP1NOER field.
	TAMP_TAMP_CR2_TAMP1NOER_Msk = 0x1
	// Bit TAMP1NOER.
	TAMP_TAMP_CR2_TAMP1NOER = 0x1
	// Position of TAMP2NOER field.
	TAMP_TAMP_CR2_TAMP2NOER_Pos = 0x1
	// Bit mask of TAMP2NOER field.
	TAMP_TAMP_CR2_TAMP2NOER_Msk = 0x2
	// Bit TAMP2NOER.
	TAMP_TAMP_CR2_TAMP2NOER = 0x2
	// Position of TAMP3NOER field.
	TAMP_TAMP_CR2_TAMP3NOER_Pos = 0x2
	// Bit mask of TAMP3NOER field.
	TAMP_TAMP_CR2_TAMP3NOER_Msk = 0x4
	// Bit TAMP3NOER.
	TAMP_TAMP_CR2_TAMP3NOER = 0x4
	// Position of TAMP1MSK field.
	TAMP_TAMP_CR2_TAMP1MSK_Pos = 0x10
	// Bit mask of TAMP1MSK field.
	TAMP_TAMP_CR2_TAMP1MSK_Msk = 0x10000
	// Bit TAMP1MSK.
	TAMP_TAMP_CR2_TAMP1MSK = 0x10000
	// Position of TAMP2MSK field.
	TAMP_TAMP_CR2_TAMP2MSK_Pos = 0x11
	// Bit mask of TAMP2MSK field.
	TAMP_TAMP_CR2_TAMP2MSK_Msk = 0x20000
	// Bit TAMP2MSK.
	TAMP_TAMP_CR2_TAMP2MSK = 0x20000
	// Position of TAMP3MSK field.
	TAMP_TAMP_CR2_TAMP3MSK_Pos = 0x12
	// Bit mask of TAMP3MSK field.
	TAMP_TAMP_CR2_TAMP3MSK_Msk = 0x40000
	// Bit TAMP3MSK.
	TAMP_TAMP_CR2_TAMP3MSK = 0x40000
	// Position of TAMP1TRG field.
	TAMP_TAMP_CR2_TAMP1TRG_Pos = 0x18
	// Bit mask of TAMP1TRG field.
	TAMP_TAMP_CR2_TAMP1TRG_Msk = 0x1000000
	// Bit TAMP1TRG.
	TAMP_TAMP_CR2_TAMP1TRG = 0x1000000
	// Position of TAMP2TRG field.
	TAMP_TAMP_CR2_TAMP2TRG_Pos = 0x19
	// Bit mask of TAMP2TRG field.
	TAMP_TAMP_CR2_TAMP2TRG_Msk = 0x2000000
	// Bit TAMP2TRG.
	TAMP_TAMP_CR2_TAMP2TRG = 0x2000000
	// Position of TAMP3TRG field.
	TAMP_TAMP_CR2_TAMP3TRG_Pos = 0x1a
	// Bit mask of TAMP3TRG field.
	TAMP_TAMP_CR2_TAMP3TRG_Msk = 0x4000000
	// Bit TAMP3TRG.
	TAMP_TAMP_CR2_TAMP3TRG = 0x4000000

	// TAMP_FLTCR: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of TAMPFREQ field.
	TAMP_TAMP_FLTCR_TAMPFREQ_Pos = 0x0
	// Bit mask of TAMPFREQ field.
	TAMP_TAMP_FLTCR_TAMPFREQ_Msk = 0x7
	// Position of TAMPFLT field.
	TAMP_TAMP_FLTCR_TAMPFLT_Pos = 0x3
	// Bit mask of TAMPFLT field.
	TAMP_TAMP_FLTCR_TAMPFLT_Msk = 0x18
	// Position of TAMPPRCH field.
	TAMP_TAMP_FLTCR_TAMPPRCH_Pos = 0x5
	// Bit mask of TAMPPRCH field.
	TAMP_TAMP_FLTCR_TAMPPRCH_Msk = 0x60
	// Position of TAMPPUDIS field.
	TAMP_TAMP_FLTCR_TAMPPUDIS_Pos = 0x7
	// Bit mask of TAMPPUDIS field.
	TAMP_TAMP_FLTCR_TAMPPUDIS_Msk = 0x80
	// Bit TAMPPUDIS.
	TAMP_TAMP_FLTCR_TAMPPUDIS = 0x80

	// TAMP_ATCR1: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of TAMP1AM field.
	TAMP_TAMP_ATCR1_TAMP1AM_Pos = 0x0
	// Bit mask of TAMP1AM field.
	TAMP_TAMP_ATCR1_TAMP1AM_Msk = 0x1
	// Bit TAMP1AM.
	TAMP_TAMP_ATCR1_TAMP1AM = 0x1
	// Position of TAMP2AM field.
	TAMP_TAMP_ATCR1_TAMP2AM_Pos = 0x1
	// Bit mask of TAMP2AM field.
	TAMP_TAMP_ATCR1_TAMP2AM_Msk = 0x2
	// Bit TAMP2AM.
	TAMP_TAMP_ATCR1_TAMP2AM = 0x2
	// Position of TAMP3AM field.
	TAMP_TAMP_ATCR1_TAMP3AM_Pos = 0x2
	// Bit mask of TAMP3AM field.
	TAMP_TAMP_ATCR1_TAMP3AM_Msk = 0x4
	// Bit TAMP3AM.
	TAMP_TAMP_ATCR1_TAMP3AM = 0x4
	// Position of ATOSEL1 field.
	TAMP_TAMP_ATCR1_ATOSEL1_Pos = 0x8
	// Bit mask of ATOSEL1 field.
	TAMP_TAMP_ATCR1_ATOSEL1_Msk = 0x300
	// Position of ATOSEL2 field.
	TAMP_TAMP_ATCR1_ATOSEL2_Pos = 0xa
	// Bit mask of ATOSEL2 field.
	TAMP_TAMP_ATCR1_ATOSEL2_Msk = 0xc00
	// Position of ATOSEL3 field.
	TAMP_TAMP_ATCR1_ATOSEL3_Pos = 0xc
	// Bit mask of ATOSEL3 field.
	TAMP_TAMP_ATCR1_ATOSEL3_Msk = 0x3000
	// Position of ATCKSEL field.
	TAMP_TAMP_ATCR1_ATCKSEL_Pos = 0x10
	// Bit mask of ATCKSEL field.
	TAMP_TAMP_ATCR1_ATCKSEL_Msk = 0x70000
	// Position of ATPER field.
	TAMP_TAMP_ATCR1_ATPER_Pos = 0x18
	// Bit mask of ATPER field.
	TAMP_TAMP_ATCR1_ATPER_Msk = 0x7000000
	// Position of ATOSHARE field.
	TAMP_TAMP_ATCR1_ATOSHARE_Pos = 0x1e
	// Bit mask of ATOSHARE field.
	TAMP_TAMP_ATCR1_ATOSHARE_Msk = 0x40000000
	// Bit ATOSHARE.
	TAMP_TAMP_ATCR1_ATOSHARE = 0x40000000
	// Position of FLTEN field.
	TAMP_TAMP_ATCR1_FLTEN_Pos = 0x1f
	// Bit mask of FLTEN field.
	TAMP_TAMP_ATCR1_FLTEN_Msk = 0x80000000
	// Bit FLTEN.
	TAMP_TAMP_ATCR1_FLTEN = 0x80000000

	// TAMP_ATSEEDR: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of SEED field.
	TAMP_TAMP_ATSEEDR_SEED_Pos = 0x0
	// Bit mask of SEED field.
	TAMP_TAMP_ATSEEDR_SEED_Msk = 0xffffffff

	// TAMP_ATOR: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of PRNG field.
	TAMP_TAMP_ATOR_PRNG_Pos = 0x0
	// Bit mask of PRNG field.
	TAMP_TAMP_ATOR_PRNG_Msk = 0xff
	// Position of SEEDF field.
	TAMP_TAMP_ATOR_SEEDF_Pos = 0xe
	// Bit mask of SEEDF field.
	TAMP_TAMP_ATOR_SEEDF_Msk = 0x4000
	// Bit SEEDF.
	TAMP_TAMP_ATOR_SEEDF = 0x4000
	// Position of INITS field.
	TAMP_TAMP_ATOR_INITS_Pos = 0xf
	// Bit mask of INITS field.
	TAMP_TAMP_ATOR_INITS_Msk = 0x8000
	// Bit INITS.
	TAMP_TAMP_ATOR_INITS = 0x8000

	// TAMP_SMCR: This register can be written only when the APB access is secure.
	// Position of BKPRWDPROT field.
	TAMP_TAMP_SMCR_BKPRWDPROT_Pos = 0x0
	// Bit mask of BKPRWDPROT field.
	TAMP_TAMP_SMCR_BKPRWDPROT_Msk = 0xff
	// Position of BKPWDPROT field.
	TAMP_TAMP_SMCR_BKPWDPROT_Pos = 0x10
	// Bit mask of BKPWDPROT field.
	TAMP_TAMP_SMCR_BKPWDPROT_Msk = 0xff0000
	// Position of TAMPDPROT field.
	TAMP_TAMP_SMCR_TAMPDPROT_Pos = 0x1f
	// Bit mask of TAMPDPROT field.
	TAMP_TAMP_SMCR_TAMPDPROT_Msk = 0x80000000
	// Bit TAMPDPROT.
	TAMP_TAMP_SMCR_TAMPDPROT = 0x80000000

	// TAMP_IER: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of TAMP1IE field.
	TAMP_TAMP_IER_TAMP1IE_Pos = 0x0
	// Bit mask of TAMP1IE field.
	TAMP_TAMP_IER_TAMP1IE_Msk = 0x1
	// Bit TAMP1IE.
	TAMP_TAMP_IER_TAMP1IE = 0x1
	// Position of TAMP2IE field.
	TAMP_TAMP_IER_TAMP2IE_Pos = 0x1
	// Bit mask of TAMP2IE field.
	TAMP_TAMP_IER_TAMP2IE_Msk = 0x2
	// Bit TAMP2IE.
	TAMP_TAMP_IER_TAMP2IE = 0x2
	// Position of TAMP3IE field.
	TAMP_TAMP_IER_TAMP3IE_Pos = 0x2
	// Bit mask of TAMP3IE field.
	TAMP_TAMP_IER_TAMP3IE_Msk = 0x4
	// Bit TAMP3IE.
	TAMP_TAMP_IER_TAMP3IE = 0x4
	// Position of ITAMP1IE field.
	TAMP_TAMP_IER_ITAMP1IE_Pos = 0x10
	// Bit mask of ITAMP1IE field.
	TAMP_TAMP_IER_ITAMP1IE_Msk = 0x10000
	// Bit ITAMP1IE.
	TAMP_TAMP_IER_ITAMP1IE = 0x10000
	// Position of ITAMP2IE field.
	TAMP_TAMP_IER_ITAMP2IE_Pos = 0x11
	// Bit mask of ITAMP2IE field.
	TAMP_TAMP_IER_ITAMP2IE_Msk = 0x20000
	// Bit ITAMP2IE.
	TAMP_TAMP_IER_ITAMP2IE = 0x20000
	// Position of ITAMP3IE field.
	TAMP_TAMP_IER_ITAMP3IE_Pos = 0x12
	// Bit mask of ITAMP3IE field.
	TAMP_TAMP_IER_ITAMP3IE_Msk = 0x40000
	// Bit ITAMP3IE.
	TAMP_TAMP_IER_ITAMP3IE = 0x40000
	// Position of ITAMP4IE field.
	TAMP_TAMP_IER_ITAMP4IE_Pos = 0x13
	// Bit mask of ITAMP4IE field.
	TAMP_TAMP_IER_ITAMP4IE_Msk = 0x80000
	// Bit ITAMP4IE.
	TAMP_TAMP_IER_ITAMP4IE = 0x80000
	// Position of ITAMP5IE field.
	TAMP_TAMP_IER_ITAMP5IE_Pos = 0x14
	// Bit mask of ITAMP5IE field.
	TAMP_TAMP_IER_ITAMP5IE_Msk = 0x100000
	// Bit ITAMP5IE.
	TAMP_TAMP_IER_ITAMP5IE = 0x100000
	// Position of ITAMP8IE field.
	TAMP_TAMP_IER_ITAMP8IE_Pos = 0x17
	// Bit mask of ITAMP8IE field.
	TAMP_TAMP_IER_ITAMP8IE_Msk = 0x800000
	// Bit ITAMP8IE.
	TAMP_TAMP_IER_ITAMP8IE = 0x800000

	// TAMP_SR: This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.
	// Position of TAMP1F field.
	TAMP_TAMP_SR_TAMP1F_Pos = 0x0
	// Bit mask of TAMP1F field.
	TAMP_TAMP_SR_TAMP1F_Msk = 0x1
	// Bit TAMP1F.
	TAMP_TAMP_SR_TAMP1F = 0x1
	// Position of TAMP2F field.
	TAMP_TAMP_SR_TAMP2F_Pos = 0x1
	// Bit mask of TAMP2F field.
	TAMP_TAMP_SR_TAMP2F_Msk = 0x2
	// Bit TAMP2F.
	TAMP_TAMP_SR_TAMP2F = 0x2
	// Position of TAMP3F field.
	TAMP_TAMP_SR_TAMP3F_Pos = 0x2
	// Bit mask of TAMP3F field.
	TAMP_TAMP_SR_TAMP3F_Msk = 0x4
	// Bit TAMP3F.
	TAMP_TAMP_SR_TAMP3F = 0x4
	// Position of ITAMP1F field.
	TAMP_TAMP_SR_ITAMP1F_Pos = 0x10
	// Bit mask of ITAMP1F field.
	TAMP_TAMP_SR_ITAMP1F_Msk = 0x10000
	// Bit ITAMP1F.
	TAMP_TAMP_SR_ITAMP1F = 0x10000
	// Position of ITAMP2F field.
	TAMP_TAMP_SR_ITAMP2F_Pos = 0x11
	// Bit mask of ITAMP2F field.
	TAMP_TAMP_SR_ITAMP2F_Msk = 0x20000
	// Bit ITAMP2F.
	TAMP_TAMP_SR_ITAMP2F = 0x20000
	// Position of ITAMP3F field.
	TAMP_TAMP_SR_ITAMP3F_Pos = 0x12
	// Bit mask of ITAMP3F field.
	TAMP_TAMP_SR_ITAMP3F_Msk = 0x40000
	// Bit ITAMP3F.
	TAMP_TAMP_SR_ITAMP3F = 0x40000
	// Position of ITAMP4F field.
	TAMP_TAMP_SR_ITAMP4F_Pos = 0x13
	// Bit mask of ITAMP4F field.
	TAMP_TAMP_SR_ITAMP4F_Msk = 0x80000
	// Bit ITAMP4F.
	TAMP_TAMP_SR_ITAMP4F = 0x80000
	// Position of ITAMP5F field.
	TAMP_TAMP_SR_ITAMP5F_Pos = 0x14
	// Bit mask of ITAMP5F field.
	TAMP_TAMP_SR_ITAMP5F_Msk = 0x100000
	// Bit ITAMP5F.
	TAMP_TAMP_SR_ITAMP5F = 0x100000
	// Position of ITAMP8F field.
	TAMP_TAMP_SR_ITAMP8F_Pos = 0x17
	// Bit mask of ITAMP8F field.
	TAMP_TAMP_SR_ITAMP8F_Msk = 0x800000
	// Bit ITAMP8F.
	TAMP_TAMP_SR_ITAMP8F = 0x800000

	// TAMP_MISR: TAMP non-secure masked interrupt status register
	// Position of TAMP1MF field.
	TAMP_TAMP_MISR_TAMP1MF_Pos = 0x0
	// Bit mask of TAMP1MF field.
	TAMP_TAMP_MISR_TAMP1MF_Msk = 0x1
	// Bit TAMP1MF.
	TAMP_TAMP_MISR_TAMP1MF = 0x1
	// Position of TAMP2MF field.
	TAMP_TAMP_MISR_TAMP2MF_Pos = 0x1
	// Bit mask of TAMP2MF field.
	TAMP_TAMP_MISR_TAMP2MF_Msk = 0x2
	// Bit TAMP2MF.
	TAMP_TAMP_MISR_TAMP2MF = 0x2
	// Position of TAMP3MF field.
	TAMP_TAMP_MISR_TAMP3MF_Pos = 0x2
	// Bit mask of TAMP3MF field.
	TAMP_TAMP_MISR_TAMP3MF_Msk = 0x4
	// Bit TAMP3MF.
	TAMP_TAMP_MISR_TAMP3MF = 0x4
	// Position of ITAMP1MF field.
	TAMP_TAMP_MISR_ITAMP1MF_Pos = 0x10
	// Bit mask of ITAMP1MF field.
	TAMP_TAMP_MISR_ITAMP1MF_Msk = 0x10000
	// Bit ITAMP1MF.
	TAMP_TAMP_MISR_ITAMP1MF = 0x10000
	// Position of ITAMP2MF field.
	TAMP_TAMP_MISR_ITAMP2MF_Pos = 0x11
	// Bit mask of ITAMP2MF field.
	TAMP_TAMP_MISR_ITAMP2MF_Msk = 0x20000
	// Bit ITAMP2MF.
	TAMP_TAMP_MISR_ITAMP2MF = 0x20000
	// Position of ITAMP3MF field.
	TAMP_TAMP_MISR_ITAMP3MF_Pos = 0x12
	// Bit mask of ITAMP3MF field.
	TAMP_TAMP_MISR_ITAMP3MF_Msk = 0x40000
	// Bit ITAMP3MF.
	TAMP_TAMP_MISR_ITAMP3MF = 0x40000
	// Position of ITAMP4MF field.
	TAMP_TAMP_MISR_ITAMP4MF_Pos = 0x13
	// Bit mask of ITAMP4MF field.
	TAMP_TAMP_MISR_ITAMP4MF_Msk = 0x80000
	// Bit ITAMP4MF.
	TAMP_TAMP_MISR_ITAMP4MF = 0x80000
	// Position of ITAMP5MF field.
	TAMP_TAMP_MISR_ITAMP5MF_Pos = 0x14
	// Bit mask of ITAMP5MF field.
	TAMP_TAMP_MISR_ITAMP5MF_Msk = 0x100000
	// Bit ITAMP5MF.
	TAMP_TAMP_MISR_ITAMP5MF = 0x100000
	// Position of ITAMP8MF field.
	TAMP_TAMP_MISR_ITAMP8MF_Pos = 0x17
	// Bit mask of ITAMP8MF field.
	TAMP_TAMP_MISR_ITAMP8MF_Msk = 0x800000
	// Bit ITAMP8MF.
	TAMP_TAMP_MISR_ITAMP8MF = 0x800000

	// TAMP_SMISR: TAMP secure masked interrupt status register
	// Position of TAMP1MF field.
	TAMP_TAMP_SMISR_TAMP1MF_Pos = 0x0
	// Bit mask of TAMP1MF field.
	TAMP_TAMP_SMISR_TAMP1MF_Msk = 0x1
	// Bit TAMP1MF.
	TAMP_TAMP_SMISR_TAMP1MF = 0x1
	// Position of TAMP2MF field.
	TAMP_TAMP_SMISR_TAMP2MF_Pos = 0x1
	// Bit mask of TAMP2MF field.
	TAMP_TAMP_SMISR_TAMP2MF_Msk = 0x2
	// Bit TAMP2MF.
	TAMP_TAMP_SMISR_TAMP2MF = 0x2
	// Position of TAMP3MF field.
	TAMP_TAMP_SMISR_TAMP3MF_Pos = 0x2
	// Bit mask of TAMP3MF field.
	TAMP_TAMP_SMISR_TAMP3MF_Msk = 0x4
	// Bit TAMP3MF.
	TAMP_TAMP_SMISR_TAMP3MF = 0x4
	// Position of ITAMP1MF field.
	TAMP_TAMP_SMISR_ITAMP1MF_Pos = 0x10
	// Bit mask of ITAMP1MF field.
	TAMP_TAMP_SMISR_ITAMP1MF_Msk = 0x10000
	// Bit ITAMP1MF.
	TAMP_TAMP_SMISR_ITAMP1MF = 0x10000
	// Position of ITAMP2MF field.
	TAMP_TAMP_SMISR_ITAMP2MF_Pos = 0x11
	// Bit mask of ITAMP2MF field.
	TAMP_TAMP_SMISR_ITAMP2MF_Msk = 0x20000
	// Bit ITAMP2MF.
	TAMP_TAMP_SMISR_ITAMP2MF = 0x20000
	// Position of ITAMP3MF field.
	TAMP_TAMP_SMISR_ITAMP3MF_Pos = 0x12
	// Bit mask of ITAMP3MF field.
	TAMP_TAMP_SMISR_ITAMP3MF_Msk = 0x40000
	// Bit ITAMP3MF.
	TAMP_TAMP_SMISR_ITAMP3MF = 0x40000
	// Position of ITAMP4MF field.
	TAMP_TAMP_SMISR_ITAMP4MF_Pos = 0x13
	// Bit mask of ITAMP4MF field.
	TAMP_TAMP_SMISR_ITAMP4MF_Msk = 0x80000
	// Bit ITAMP4MF.
	TAMP_TAMP_SMISR_ITAMP4MF = 0x80000
	// Position of ITAMP5MF field.
	TAMP_TAMP_SMISR_ITAMP5MF_Pos = 0x14
	// Bit mask of ITAMP5MF field.
	TAMP_TAMP_SMISR_ITAMP5MF_Msk = 0x100000
	// Bit ITAMP5MF.
	TAMP_TAMP_SMISR_ITAMP5MF = 0x100000
	// Position of ITAMP8MF field.
	TAMP_TAMP_SMISR_ITAMP8MF_Pos = 0x17
	// Bit mask of ITAMP8MF field.
	TAMP_TAMP_SMISR_ITAMP8MF_Msk = 0x800000
	// Bit ITAMP8MF.
	TAMP_TAMP_SMISR_ITAMP8MF = 0x800000

	// TAMP_SCR: TAMP status clear register
	// Position of CTAMP1F field.
	TAMP_TAMP_SCR_CTAMP1F_Pos = 0x0
	// Bit mask of CTAMP1F field.
	TAMP_TAMP_SCR_CTAMP1F_Msk = 0x1
	// Bit CTAMP1F.
	TAMP_TAMP_SCR_CTAMP1F = 0x1
	// Position of CTAMP2F field.
	TAMP_TAMP_SCR_CTAMP2F_Pos = 0x1
	// Bit mask of CTAMP2F field.
	TAMP_TAMP_SCR_CTAMP2F_Msk = 0x2
	// Bit CTAMP2F.
	TAMP_TAMP_SCR_CTAMP2F = 0x2
	// Position of CTAMP3F field.
	TAMP_TAMP_SCR_CTAMP3F_Pos = 0x2
	// Bit mask of CTAMP3F field.
	TAMP_TAMP_SCR_CTAMP3F_Msk = 0x4
	// Bit CTAMP3F.
	TAMP_TAMP_SCR_CTAMP3F = 0x4
	// Position of CITAMP1F field.
	TAMP_TAMP_SCR_CITAMP1F_Pos = 0x10
	// Bit mask of CITAMP1F field.
	TAMP_TAMP_SCR_CITAMP1F_Msk = 0x10000
	// Bit CITAMP1F.
	TAMP_TAMP_SCR_CITAMP1F = 0x10000
	// Position of CITAMP2F field.
	TAMP_TAMP_SCR_CITAMP2F_Pos = 0x11
	// Bit mask of CITAMP2F field.
	TAMP_TAMP_SCR_CITAMP2F_Msk = 0x20000
	// Bit CITAMP2F.
	TAMP_TAMP_SCR_CITAMP2F = 0x20000
	// Position of CITAMP3F field.
	TAMP_TAMP_SCR_CITAMP3F_Pos = 0x12
	// Bit mask of CITAMP3F field.
	TAMP_TAMP_SCR_CITAMP3F_Msk = 0x40000
	// Bit CITAMP3F.
	TAMP_TAMP_SCR_CITAMP3F = 0x40000
	// Position of CITAMP4F field.
	TAMP_TAMP_SCR_CITAMP4F_Pos = 0x13
	// Bit mask of CITAMP4F field.
	TAMP_TAMP_SCR_CITAMP4F_Msk = 0x80000
	// Bit CITAMP4F.
	TAMP_TAMP_SCR_CITAMP4F = 0x80000
	// Position of CITAMP5F field.
	TAMP_TAMP_SCR_CITAMP5F_Pos = 0x14
	// Bit mask of CITAMP5F field.
	TAMP_TAMP_SCR_CITAMP5F_Msk = 0x100000
	// Bit CITAMP5F.
	TAMP_TAMP_SCR_CITAMP5F = 0x100000
	// Position of CITAMP8F field.
	TAMP_TAMP_SCR_CITAMP8F_Pos = 0x17
	// Bit mask of CITAMP8F field.
	TAMP_TAMP_SCR_CITAMP8F_Msk = 0x800000
	// Bit CITAMP8F.
	TAMP_TAMP_SCR_CITAMP8F = 0x800000

	// TAMP_COUNTR: TAMP monotonic counter register
	// Position of COUNT field.
	TAMP_TAMP_COUNTR_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	TAMP_TAMP_COUNTR_COUNT_Msk = 0xffffffff

	// TAMP_CFGR: TAMP configuration register
	// Position of OUT3_RMP field.
	TAMP_TAMP_CFGR_OUT3_RMP_Pos = 0x0
	// Bit mask of OUT3_RMP field.
	TAMP_TAMP_CFGR_OUT3_RMP_Msk = 0x1
	// Bit OUT3_RMP.
	TAMP_TAMP_CFGR_OUT3_RMP = 0x1

	// TAMP_BKP0R: TAMP backup 0 register
	// Position of BKP field.
	TAMP_TAMP_BKP0R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP0R_BKP_Msk = 0xffffffff

	// TAMP_BKP1R: TAMP backup 1 register
	// Position of BKP field.
	TAMP_TAMP_BKP1R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP1R_BKP_Msk = 0xffffffff

	// TAMP_BKP2R: TAMP backup 2 register
	// Position of BKP field.
	TAMP_TAMP_BKP2R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP2R_BKP_Msk = 0xffffffff

	// TAMP_BKP3R: TAMP backup 3 register
	// Position of BKP field.
	TAMP_TAMP_BKP3R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP3R_BKP_Msk = 0xffffffff

	// TAMP_BKP4R: TAMP backup 4 register
	// Position of BKP field.
	TAMP_TAMP_BKP4R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP4R_BKP_Msk = 0xffffffff

	// TAMP_BKP5R: TAMP backup 5 register
	// Position of BKP field.
	TAMP_TAMP_BKP5R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP5R_BKP_Msk = 0xffffffff

	// TAMP_BKP6R: TAMP backup 6 register
	// Position of BKP field.
	TAMP_TAMP_BKP6R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP6R_BKP_Msk = 0xffffffff

	// TAMP_BKP7R: TAMP backup 7 register
	// Position of BKP field.
	TAMP_TAMP_BKP7R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP7R_BKP_Msk = 0xffffffff

	// TAMP_BKP8R: TAMP backup 8 register
	// Position of BKP field.
	TAMP_TAMP_BKP8R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP8R_BKP_Msk = 0xffffffff

	// TAMP_BKP9R: TAMP backup 9 register
	// Position of BKP field.
	TAMP_TAMP_BKP9R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP9R_BKP_Msk = 0xffffffff

	// TAMP_BKP10R: TAMP backup 10 register
	// Position of BKP field.
	TAMP_TAMP_BKP10R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP10R_BKP_Msk = 0xffffffff

	// TAMP_BKP11R: TAMP backup 11 register
	// Position of BKP field.
	TAMP_TAMP_BKP11R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP11R_BKP_Msk = 0xffffffff

	// TAMP_BKP12R: TAMP backup 12 register
	// Position of BKP field.
	TAMP_TAMP_BKP12R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP12R_BKP_Msk = 0xffffffff

	// TAMP_BKP13R: TAMP backup 13 register
	// Position of BKP field.
	TAMP_TAMP_BKP13R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP13R_BKP_Msk = 0xffffffff

	// TAMP_BKP14R: TAMP backup 14 register
	// Position of BKP field.
	TAMP_TAMP_BKP14R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP14R_BKP_Msk = 0xffffffff

	// TAMP_BKP15R: TAMP backup 15 register
	// Position of BKP field.
	TAMP_TAMP_BKP15R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP15R_BKP_Msk = 0xffffffff

	// TAMP_BKP16R: TAMP backup 16 register
	// Position of BKP field.
	TAMP_TAMP_BKP16R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP16R_BKP_Msk = 0xffffffff

	// TAMP_BKP17R: TAMP backup 17 register
	// Position of BKP field.
	TAMP_TAMP_BKP17R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP17R_BKP_Msk = 0xffffffff

	// TAMP_BKP18R: TAMP backup 18 register
	// Position of BKP field.
	TAMP_TAMP_BKP18R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP18R_BKP_Msk = 0xffffffff

	// TAMP_BKP19R: TAMP backup 19 register
	// Position of BKP field.
	TAMP_TAMP_BKP19R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP19R_BKP_Msk = 0xffffffff

	// TAMP_BKP20R: TAMP backup 20 register
	// Position of BKP field.
	TAMP_TAMP_BKP20R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP20R_BKP_Msk = 0xffffffff

	// TAMP_BKP21R: TAMP backup 21 register
	// Position of BKP field.
	TAMP_TAMP_BKP21R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP21R_BKP_Msk = 0xffffffff

	// TAMP_BKP22R: TAMP backup 22 register
	// Position of BKP field.
	TAMP_TAMP_BKP22R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP22R_BKP_Msk = 0xffffffff

	// TAMP_BKP23R: TAMP backup 23 register
	// Position of BKP field.
	TAMP_TAMP_BKP23R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP23R_BKP_Msk = 0xffffffff

	// TAMP_BKP24R: TAMP backup 24 register
	// Position of BKP field.
	TAMP_TAMP_BKP24R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP24R_BKP_Msk = 0xffffffff

	// TAMP_BKP25R: TAMP backup 25 register
	// Position of BKP field.
	TAMP_TAMP_BKP25R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP25R_BKP_Msk = 0xffffffff

	// TAMP_BKP26R: TAMP backup 26 register
	// Position of BKP field.
	TAMP_TAMP_BKP26R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP26R_BKP_Msk = 0xffffffff

	// TAMP_BKP27R: TAMP backup 27 register
	// Position of BKP field.
	TAMP_TAMP_BKP27R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP27R_BKP_Msk = 0xffffffff

	// TAMP_BKP28R: TAMP backup 28 register
	// Position of BKP field.
	TAMP_TAMP_BKP28R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP28R_BKP_Msk = 0xffffffff

	// TAMP_BKP29R: TAMP backup 29 register
	// Position of BKP field.
	TAMP_TAMP_BKP29R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP29R_BKP_Msk = 0xffffffff

	// TAMP_BKP30R: TAMP backup 30 register
	// Position of BKP field.
	TAMP_TAMP_BKP30R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP30R_BKP_Msk = 0xffffffff

	// TAMP_BKP31R: TAMP backup 31 register
	// Position of BKP field.
	TAMP_TAMP_BKP31R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_TAMP_BKP31R_BKP_Msk = 0xffffffff

	// TAMP_HWCFGR2: TAMP hardware configuration register 2
	// Position of OPTIONREG_OUT field.
	TAMP_TAMP_HWCFGR2_OPTIONREG_OUT_Pos = 0x0
	// Bit mask of OPTIONREG_OUT field.
	TAMP_TAMP_HWCFGR2_OPTIONREG_OUT_Msk = 0xff
	// Position of TRUST_ZONE field.
	TAMP_TAMP_HWCFGR2_TRUST_ZONE_Pos = 0x8
	// Bit mask of TRUST_ZONE field.
	TAMP_TAMP_HWCFGR2_TRUST_ZONE_Msk = 0xf00

	// TAMP_HWCFGR1: TAMP hardware configuration register 1
	// Position of BACKUP_REGS field.
	TAMP_TAMP_HWCFGR1_BACKUP_REGS_Pos = 0x0
	// Bit mask of BACKUP_REGS field.
	TAMP_TAMP_HWCFGR1_BACKUP_REGS_Msk = 0xff
	// Position of TAMPER field.
	TAMP_TAMP_HWCFGR1_TAMPER_Pos = 0x8
	// Bit mask of TAMPER field.
	TAMP_TAMP_HWCFGR1_TAMPER_Msk = 0xf00
	// Position of ACTIVE_TAMPER field.
	TAMP_TAMP_HWCFGR1_ACTIVE_TAMPER_Pos = 0xc
	// Bit mask of ACTIVE_TAMPER field.
	TAMP_TAMP_HWCFGR1_ACTIVE_TAMPER_Msk = 0xf000
	// Position of INT_TAMPER field.
	TAMP_TAMP_HWCFGR1_INT_TAMPER_Pos = 0x10
	// Bit mask of INT_TAMPER field.
	TAMP_TAMP_HWCFGR1_INT_TAMPER_Msk = 0xffff0000

	// TAMP_VERR: TAMP version register
	// Position of MINREV field.
	TAMP_TAMP_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	TAMP_TAMP_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	TAMP_TAMP_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	TAMP_TAMP_VERR_MAJREV_Msk = 0xf0

	// TAMP_IPIDR: TAMP identification register
	// Position of ID field.
	TAMP_TAMP_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	TAMP_TAMP_IPIDR_ID_Msk = 0xffffffff

	// TAMP_SIDR: TAMP size identification register
	// Position of SID field.
	TAMP_TAMP_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	TAMP_TAMP_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for TIM1: TIM1
const (
	// TIM1_CR1: TIM1 control register 1
	// Position of CEN field.
	TIM1_TIM1_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM1_TIM1_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM1_TIM1_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM1_TIM1_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM1_TIM1_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM1_TIM1_CR1_UDIS = 0x2
	// Position of URS field.
	TIM1_TIM1_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM1_TIM1_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM1_TIM1_CR1_URS = 0x4
	// Position of OPM field.
	TIM1_TIM1_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM1_TIM1_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM1_TIM1_CR1_OPM = 0x8
	// Position of DIR field.
	TIM1_TIM1_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM1_TIM1_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM1_TIM1_CR1_DIR = 0x10
	// Position of CMS field.
	TIM1_TIM1_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM1_TIM1_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM1_TIM1_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM1_TIM1_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM1_TIM1_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM1_TIM1_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM1_TIM1_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM1_TIM1_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM1_TIM1_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM1_TIM1_CR1_UIFREMAP = 0x800

	// TIM1_CR2: TIM1 control register 2
	// Position of CCPC field.
	TIM1_TIM1_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM1_TIM1_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM1_TIM1_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM1_TIM1_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM1_TIM1_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM1_TIM1_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM1_TIM1_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM1_TIM1_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM1_TIM1_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM1_TIM1_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM1_TIM1_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM1_TIM1_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM1_TIM1_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM1_TIM1_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM1_TIM1_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM1_TIM1_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM1_TIM1_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM1_TIM1_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM1_TIM1_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM1_TIM1_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM1_TIM1_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM1_TIM1_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM1_TIM1_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM1_TIM1_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM1_TIM1_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM1_TIM1_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM1_TIM1_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM1_TIM1_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM1_TIM1_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM1_TIM1_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM1_TIM1_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM1_TIM1_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM1_TIM1_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM1_TIM1_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM1_TIM1_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM1_TIM1_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM1_TIM1_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM1_TIM1_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM1_TIM1_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM1_TIM1_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM1_TIM1_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM1_TIM1_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM1_TIM1_CR2_MMS2_Msk = 0xf00000

	// TIM1_SMCR: TIM1 slave mode control register
	// Position of SMS field.
	TIM1_TIM1_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM1_TIM1_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM1_TIM1_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM1_TIM1_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM1_TIM1_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM1_TIM1_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM1_TIM1_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM1_TIM1_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM1_TIM1_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM1_TIM1_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM1_TIM1_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM1_TIM1_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM1_TIM1_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM1_TIM1_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM1_TIM1_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM1_TIM1_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM1_TIM1_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM1_TIM1_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM1_TIM1_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM1_TIM1_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM1_TIM1_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM1_TIM1_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM1_TIM1_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM1_TIM1_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM1_TIM1_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM1_TIM1_SMCR_TS4 = 0x200000

	// TIM1_DIER: TIM1 DMA/interrupt enable register
	// Position of UIE field.
	TIM1_TIM1_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM1_TIM1_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM1_TIM1_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM1_TIM1_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM1_TIM1_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM1_TIM1_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM1_TIM1_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM1_TIM1_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM1_TIM1_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM1_TIM1_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM1_TIM1_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM1_TIM1_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM1_TIM1_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM1_TIM1_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM1_TIM1_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM1_TIM1_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM1_TIM1_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM1_TIM1_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM1_TIM1_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM1_TIM1_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM1_TIM1_DIER_TIE = 0x40
	// Position of BIE field.
	TIM1_TIM1_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM1_TIM1_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM1_TIM1_DIER_BIE = 0x80
	// Position of UDE field.
	TIM1_TIM1_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM1_TIM1_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM1_TIM1_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM1_TIM1_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM1_TIM1_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM1_TIM1_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM1_TIM1_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM1_TIM1_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM1_TIM1_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM1_TIM1_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM1_TIM1_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM1_TIM1_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM1_TIM1_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM1_TIM1_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM1_TIM1_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM1_TIM1_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM1_TIM1_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM1_TIM1_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM1_TIM1_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM1_TIM1_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM1_TIM1_DIER_TDE = 0x4000

	// TIM1_SR: TIM1 status register
	// Position of UIF field.
	TIM1_TIM1_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM1_TIM1_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM1_TIM1_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM1_TIM1_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM1_TIM1_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM1_TIM1_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM1_TIM1_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM1_TIM1_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM1_TIM1_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM1_TIM1_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM1_TIM1_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM1_TIM1_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM1_TIM1_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM1_TIM1_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM1_TIM1_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM1_TIM1_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM1_TIM1_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM1_TIM1_SR_COMIF = 0x20
	// Position of TIF field.
	TIM1_TIM1_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM1_TIM1_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM1_TIM1_SR_TIF = 0x40
	// Position of BIF field.
	TIM1_TIM1_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM1_TIM1_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM1_TIM1_SR_BIF = 0x80
	// Position of B2IF field.
	TIM1_TIM1_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM1_TIM1_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM1_TIM1_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM1_TIM1_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM1_TIM1_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM1_TIM1_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM1_TIM1_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM1_TIM1_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM1_TIM1_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM1_TIM1_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM1_TIM1_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM1_TIM1_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM1_TIM1_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM1_TIM1_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM1_TIM1_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM1_TIM1_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM1_TIM1_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM1_TIM1_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM1_TIM1_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM1_TIM1_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM1_TIM1_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM1_TIM1_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM1_TIM1_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM1_TIM1_SR_CC6IF = 0x20000

	// TIM1_EGR: TIM1 event generation register
	// Position of UG field.
	TIM1_TIM1_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM1_TIM1_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM1_TIM1_EGR_UG = 0x1
	// Position of CC1G field.
	TIM1_TIM1_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM1_TIM1_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM1_TIM1_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM1_TIM1_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM1_TIM1_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM1_TIM1_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM1_TIM1_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM1_TIM1_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM1_TIM1_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM1_TIM1_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM1_TIM1_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM1_TIM1_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM1_TIM1_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM1_TIM1_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM1_TIM1_EGR_COMG = 0x20
	// Position of TG field.
	TIM1_TIM1_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM1_TIM1_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM1_TIM1_EGR_TG = 0x40
	// Position of BG field.
	TIM1_TIM1_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM1_TIM1_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM1_TIM1_EGR_BG = 0x80
	// Position of B2G field.
	TIM1_TIM1_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM1_TIM1_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM1_TIM1_EGR_B2G = 0x100

	// TIM1_CCMR1ALTERNATE1: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM1_TIM1_CCMR1ALTERNATE1_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM1_TIM1_CCMR1ALTERNATE1_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM1_TIM1_CCMR1ALTERNATE1_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM1_TIM1_CCMR1ALTERNATE1_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM1_TIM1_CCMR1ALTERNATE1_IC2F_Msk = 0xf000

	// TIM1_CCMR2ALTERNATE17: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM1_TIM1_CCMR2ALTERNATE17_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM1_TIM1_CCMR2ALTERNATE17_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM1_TIM1_CCMR2ALTERNATE17_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM1_TIM1_CCMR2ALTERNATE17_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM1_TIM1_CCMR2ALTERNATE17_IC4F_Msk = 0xf000

	// TIM1_CCER: TIM1 capture/compare enable register
	// Position of CC1E field.
	TIM1_TIM1_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM1_TIM1_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM1_TIM1_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM1_TIM1_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM1_TIM1_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM1_TIM1_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM1_TIM1_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM1_TIM1_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM1_TIM1_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM1_TIM1_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM1_TIM1_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM1_TIM1_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM1_TIM1_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM1_TIM1_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM1_TIM1_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM1_TIM1_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM1_TIM1_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM1_TIM1_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM1_TIM1_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM1_TIM1_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM1_TIM1_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM1_TIM1_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM1_TIM1_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM1_TIM1_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM1_TIM1_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM1_TIM1_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM1_TIM1_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM1_TIM1_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM1_TIM1_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM1_TIM1_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM1_TIM1_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM1_TIM1_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM1_TIM1_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM1_TIM1_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM1_TIM1_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM1_TIM1_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM1_TIM1_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM1_TIM1_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM1_TIM1_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM1_TIM1_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM1_TIM1_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM1_TIM1_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM1_TIM1_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM1_TIM1_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM1_TIM1_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM1_TIM1_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM1_TIM1_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM1_TIM1_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM1_TIM1_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM1_TIM1_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM1_TIM1_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM1_TIM1_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM1_TIM1_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM1_TIM1_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM1_TIM1_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM1_TIM1_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM1_TIM1_CCER_CC6P = 0x200000

	// TIM1_CNT: TIM1 counter
	// Position of CNT field.
	TIM1_TIM1_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM1_TIM1_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM1_TIM1_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM1_TIM1_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM1_TIM1_CNT_UIFCPY = 0x80000000

	// TIM1_PSC: TIM1 prescaler
	// Position of PSC field.
	TIM1_TIM1_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM1_TIM1_PSC_PSC_Msk = 0xffff

	// TIM1_ARR: TIM1 auto-reload register
	// Position of ARR field.
	TIM1_TIM1_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM1_TIM1_ARR_ARR_Msk = 0xffff

	// TIM1_RCR: TIM1 repetition counter register
	// Position of REP field.
	TIM1_TIM1_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM1_TIM1_RCR_REP_Msk = 0xffff

	// TIM1_CCR1: TIM1 capture/compare register 1
	// Position of CCR1 field.
	TIM1_TIM1_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM1_TIM1_CCR1_CCR1_Msk = 0xffff

	// TIM1_CCR2: TIM1 capture/compare register 2
	// Position of CCR2 field.
	TIM1_TIM1_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM1_TIM1_CCR2_CCR2_Msk = 0xffff

	// TIM1_CCR3: TIM1 capture/compare register 3
	// Position of CCR3 field.
	TIM1_TIM1_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM1_TIM1_CCR3_CCR3_Msk = 0xffff

	// TIM1_CCR4: TIM1 capture/compare register 4
	// Position of CCR4 field.
	TIM1_TIM1_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM1_TIM1_CCR4_CCR4_Msk = 0xffff

	// TIM1_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM1_TIM1_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM1_TIM1_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM1_TIM1_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM1_TIM1_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM1_TIM1_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM1_TIM1_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM1_TIM1_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM1_TIM1_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM1_TIM1_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM1_TIM1_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM1_TIM1_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM1_TIM1_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM1_TIM1_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM1_TIM1_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM1_TIM1_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM1_TIM1_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM1_TIM1_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM1_TIM1_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM1_TIM1_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM1_TIM1_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM1_TIM1_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM1_TIM1_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM1_TIM1_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM1_TIM1_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM1_TIM1_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM1_TIM1_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM1_TIM1_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM1_TIM1_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM1_TIM1_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM1_TIM1_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM1_TIM1_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM1_TIM1_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM1_TIM1_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM1_TIM1_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM1_TIM1_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM1_TIM1_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM1_TIM1_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM1_TIM1_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM1_TIM1_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM1_TIM1_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM1_TIM1_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM1_TIM1_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM1_TIM1_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM1_TIM1_BDTR_BK2BID = 0x20000000

	// TIM1_DCR: TIM1 DMA control register
	// Position of DBA field.
	TIM1_TIM1_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM1_TIM1_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM1_TIM1_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM1_TIM1_DCR_DBL_Msk = 0x1f00

	// TIM1_DMAR: TIM1 DMA address for full transfer
	// Position of DMAB field.
	TIM1_TIM1_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM1_TIM1_DMAR_DMAB_Msk = 0xffffffff

	// TIM1_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM1_TIM1_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM1_TIM1_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM1_TIM1_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM1_TIM1_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM1_TIM1_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM1_TIM1_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM1_TIM1_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM1_TIM1_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM1_TIM1_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM1_TIM1_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM1_TIM1_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM1_TIM1_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM1_TIM1_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM1_TIM1_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM1_TIM1_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM1_TIM1_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM1_TIM1_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM1_TIM1_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM1_TIM1_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM1_TIM1_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM1_TIM1_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM1_TIM1_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM1_TIM1_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM1_TIM1_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM1_TIM1_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM1_TIM1_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM1_TIM1_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM1_TIM1_CCMR3_OC6M3 = 0x1000000

	// TIM1_CCR5: TIM1 capture/compare register 5
	// Position of CCR5 field.
	TIM1_TIM1_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM1_TIM1_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM1_TIM1_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM1_TIM1_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM1_TIM1_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM1_TIM1_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM1_TIM1_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM1_TIM1_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM1_TIM1_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM1_TIM1_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM1_TIM1_CCR5_GC5C3 = 0x80000000

	// TIM1_CCR6: TIM1 capture/compare register 6
	// Position of CCR6 field.
	TIM1_TIM1_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM1_TIM1_CCR6_CCR6_Msk = 0xffff

	// TIM1_AF1: TIM1 alternate function option register 1
	// Position of BKINE field.
	TIM1_TIM1_AF1_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIM1_TIM1_AF1_BKINE_Msk = 0x1
	// Bit BKINE.
	TIM1_TIM1_AF1_BKINE = 0x1
	// Position of BKDF1BK0E field.
	TIM1_TIM1_AF1_BKDF1BK0E_Pos = 0x8
	// Bit mask of BKDF1BK0E field.
	TIM1_TIM1_AF1_BKDF1BK0E_Msk = 0x100
	// Bit BKDF1BK0E.
	TIM1_TIM1_AF1_BKDF1BK0E = 0x100
	// Position of BKINP field.
	TIM1_TIM1_AF1_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIM1_TIM1_AF1_BKINP_Msk = 0x200
	// Bit BKINP.
	TIM1_TIM1_AF1_BKINP = 0x200
	// Position of ETRSEL field.
	TIM1_TIM1_AF1_ETRSEL_Pos = 0xe
	// Bit mask of ETRSEL field.
	TIM1_TIM1_AF1_ETRSEL_Msk = 0x3c000

	// TIM1_AF2: TIM1 Alternate function register 2
	// Position of BK2INE field.
	TIM1_TIM1_AF2_BK2INE_Pos = 0x0
	// Bit mask of BK2INE field.
	TIM1_TIM1_AF2_BK2INE_Msk = 0x1
	// Bit BK2INE.
	TIM1_TIM1_AF2_BK2INE = 0x1
	// Position of BK2DF1BK1E field.
	TIM1_TIM1_AF2_BK2DF1BK1E_Pos = 0x8
	// Bit mask of BK2DF1BK1E field.
	TIM1_TIM1_AF2_BK2DF1BK1E_Msk = 0x100
	// Bit BK2DF1BK1E.
	TIM1_TIM1_AF2_BK2DF1BK1E = 0x100
	// Position of BK2INP field.
	TIM1_TIM1_AF2_BK2INP_Pos = 0x9
	// Bit mask of BK2INP field.
	TIM1_TIM1_AF2_BK2INP_Msk = 0x200
	// Bit BK2INP.
	TIM1_TIM1_AF2_BK2INP = 0x200

	// TIM1_TISEL: TIM1 timer input selection register
	// Position of TI1SEL field.
	TIM1_TIM1_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM1_TIM1_TISEL_TI1SEL_Msk = 0xf
	// Position of TI2SEL field.
	TIM1_TIM1_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIM1_TIM1_TISEL_TI2SEL_Msk = 0xf00
	// Position of TI3SEL field.
	TIM1_TIM1_TISEL_TI3SEL_Pos = 0x10
	// Bit mask of TI3SEL field.
	TIM1_TIM1_TISEL_TI3SEL_Msk = 0xf0000
	// Position of TI4SEL field.
	TIM1_TIM1_TISEL_TI4SEL_Pos = 0x18
	// Bit mask of TI4SEL field.
	TIM1_TIM1_TISEL_TI4SEL_Msk = 0xf000000
)

// Bitfields for TIM2: TIM2
const (
	// TIM2_CR1: TIM2 control register 1
	// Position of CEN field.
	TIM2_TIM2_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM2_TIM2_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM2_TIM2_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM2_TIM2_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM2_TIM2_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM2_TIM2_CR1_UDIS = 0x2
	// Position of URS field.
	TIM2_TIM2_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM2_TIM2_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM2_TIM2_CR1_URS = 0x4
	// Position of OPM field.
	TIM2_TIM2_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM2_TIM2_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM2_TIM2_CR1_OPM = 0x8
	// Position of DIR field.
	TIM2_TIM2_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM2_TIM2_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM2_TIM2_CR1_DIR = 0x10
	// Position of CMS field.
	TIM2_TIM2_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM2_TIM2_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM2_TIM2_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM2_TIM2_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM2_TIM2_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM2_TIM2_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM2_TIM2_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM2_TIM2_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM2_TIM2_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM2_TIM2_CR1_UIFREMAP = 0x800

	// TIM2_CR2: TIM2 control register 2
	// Position of CCPC field.
	TIM2_TIM2_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM2_TIM2_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM2_TIM2_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM2_TIM2_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM2_TIM2_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM2_TIM2_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM2_TIM2_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM2_TIM2_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM2_TIM2_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM2_TIM2_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM2_TIM2_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM2_TIM2_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM2_TIM2_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM2_TIM2_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM2_TIM2_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM2_TIM2_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM2_TIM2_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM2_TIM2_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM2_TIM2_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM2_TIM2_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM2_TIM2_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM2_TIM2_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM2_TIM2_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM2_TIM2_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM2_TIM2_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM2_TIM2_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM2_TIM2_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM2_TIM2_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM2_TIM2_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM2_TIM2_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM2_TIM2_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM2_TIM2_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM2_TIM2_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM2_TIM2_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM2_TIM2_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM2_TIM2_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM2_TIM2_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM2_TIM2_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM2_TIM2_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM2_TIM2_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM2_TIM2_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM2_TIM2_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM2_TIM2_CR2_MMS2_Msk = 0xf00000

	// TIM2_SMCR: TIM2 slave mode control register
	// Position of SMS field.
	TIM2_TIM2_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM2_TIM2_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM2_TIM2_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM2_TIM2_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM2_TIM2_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM2_TIM2_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM2_TIM2_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM2_TIM2_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM2_TIM2_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM2_TIM2_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM2_TIM2_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM2_TIM2_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM2_TIM2_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM2_TIM2_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM2_TIM2_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM2_TIM2_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM2_TIM2_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM2_TIM2_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM2_TIM2_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM2_TIM2_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM2_TIM2_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM2_TIM2_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM2_TIM2_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM2_TIM2_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM2_TIM2_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM2_TIM2_SMCR_TS4 = 0x200000

	// TIM2_DIER: TIM2 DMA/interrupt enable register
	// Position of UIE field.
	TIM2_TIM2_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM2_TIM2_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM2_TIM2_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM2_TIM2_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM2_TIM2_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM2_TIM2_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM2_TIM2_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM2_TIM2_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM2_TIM2_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM2_TIM2_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM2_TIM2_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM2_TIM2_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM2_TIM2_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM2_TIM2_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM2_TIM2_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM2_TIM2_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM2_TIM2_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM2_TIM2_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM2_TIM2_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM2_TIM2_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM2_TIM2_DIER_TIE = 0x40
	// Position of BIE field.
	TIM2_TIM2_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM2_TIM2_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM2_TIM2_DIER_BIE = 0x80
	// Position of UDE field.
	TIM2_TIM2_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM2_TIM2_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM2_TIM2_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM2_TIM2_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM2_TIM2_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM2_TIM2_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM2_TIM2_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM2_TIM2_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM2_TIM2_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM2_TIM2_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM2_TIM2_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM2_TIM2_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM2_TIM2_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM2_TIM2_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM2_TIM2_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM2_TIM2_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM2_TIM2_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM2_TIM2_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM2_TIM2_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM2_TIM2_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM2_TIM2_DIER_TDE = 0x4000

	// TIM2_SR: TIM2 status register
	// Position of UIF field.
	TIM2_TIM2_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM2_TIM2_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM2_TIM2_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM2_TIM2_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM2_TIM2_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM2_TIM2_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM2_TIM2_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM2_TIM2_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM2_TIM2_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM2_TIM2_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM2_TIM2_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM2_TIM2_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM2_TIM2_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM2_TIM2_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM2_TIM2_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM2_TIM2_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM2_TIM2_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM2_TIM2_SR_COMIF = 0x20
	// Position of TIF field.
	TIM2_TIM2_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM2_TIM2_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM2_TIM2_SR_TIF = 0x40
	// Position of BIF field.
	TIM2_TIM2_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM2_TIM2_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM2_TIM2_SR_BIF = 0x80
	// Position of B2IF field.
	TIM2_TIM2_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM2_TIM2_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM2_TIM2_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM2_TIM2_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM2_TIM2_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM2_TIM2_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM2_TIM2_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM2_TIM2_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM2_TIM2_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM2_TIM2_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM2_TIM2_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM2_TIM2_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM2_TIM2_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM2_TIM2_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM2_TIM2_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM2_TIM2_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM2_TIM2_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM2_TIM2_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM2_TIM2_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM2_TIM2_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM2_TIM2_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM2_TIM2_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM2_TIM2_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM2_TIM2_SR_CC6IF = 0x20000

	// TIM2_EGR: TIM2 event generation register
	// Position of UG field.
	TIM2_TIM2_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM2_TIM2_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM2_TIM2_EGR_UG = 0x1
	// Position of CC1G field.
	TIM2_TIM2_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM2_TIM2_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM2_TIM2_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM2_TIM2_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM2_TIM2_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM2_TIM2_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM2_TIM2_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM2_TIM2_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM2_TIM2_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM2_TIM2_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM2_TIM2_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM2_TIM2_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM2_TIM2_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM2_TIM2_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM2_TIM2_EGR_COMG = 0x20
	// Position of TG field.
	TIM2_TIM2_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM2_TIM2_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM2_TIM2_EGR_TG = 0x40
	// Position of BG field.
	TIM2_TIM2_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM2_TIM2_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM2_TIM2_EGR_BG = 0x80
	// Position of B2G field.
	TIM2_TIM2_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM2_TIM2_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM2_TIM2_EGR_B2G = 0x100

	// TIM2_CCMR1ALTERNATE2: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM2_TIM2_CCMR1ALTERNATE2_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM2_TIM2_CCMR1ALTERNATE2_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM2_TIM2_CCMR1ALTERNATE2_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM2_TIM2_CCMR1ALTERNATE2_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM2_TIM2_CCMR1ALTERNATE2_IC2F_Msk = 0xf000

	// TIM2_CCMR2ALTERNATE18: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM2_TIM2_CCMR2ALTERNATE18_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM2_TIM2_CCMR2ALTERNATE18_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM2_TIM2_CCMR2ALTERNATE18_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM2_TIM2_CCMR2ALTERNATE18_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM2_TIM2_CCMR2ALTERNATE18_IC4F_Msk = 0xf000

	// TIM2_CCER: TIM2 capture/compare enable register
	// Position of CC1E field.
	TIM2_TIM2_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM2_TIM2_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM2_TIM2_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM2_TIM2_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM2_TIM2_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM2_TIM2_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM2_TIM2_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM2_TIM2_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM2_TIM2_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM2_TIM2_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM2_TIM2_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM2_TIM2_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM2_TIM2_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM2_TIM2_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM2_TIM2_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM2_TIM2_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM2_TIM2_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM2_TIM2_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM2_TIM2_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM2_TIM2_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM2_TIM2_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM2_TIM2_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM2_TIM2_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM2_TIM2_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM2_TIM2_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM2_TIM2_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM2_TIM2_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM2_TIM2_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM2_TIM2_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM2_TIM2_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM2_TIM2_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM2_TIM2_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM2_TIM2_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM2_TIM2_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM2_TIM2_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM2_TIM2_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM2_TIM2_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM2_TIM2_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM2_TIM2_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM2_TIM2_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM2_TIM2_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM2_TIM2_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM2_TIM2_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM2_TIM2_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM2_TIM2_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM2_TIM2_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM2_TIM2_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM2_TIM2_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM2_TIM2_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM2_TIM2_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM2_TIM2_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM2_TIM2_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM2_TIM2_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM2_TIM2_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM2_TIM2_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM2_TIM2_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM2_TIM2_CCER_CC6P = 0x200000

	// TIM2_CNT: TIM2 counter
	// Position of CNT field.
	TIM2_TIM2_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM2_TIM2_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM2_TIM2_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM2_TIM2_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM2_TIM2_CNT_UIFCPY = 0x80000000

	// TIM2_PSC: TIM2 prescaler
	// Position of PSC field.
	TIM2_TIM2_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM2_TIM2_PSC_PSC_Msk = 0xffff

	// TIM2_ARR: TIM2 auto-reload register
	// Position of ARR field.
	TIM2_TIM2_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM2_TIM2_ARR_ARR_Msk = 0xffff

	// TIM2_RCR: TIM2 repetition counter register
	// Position of REP field.
	TIM2_TIM2_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM2_TIM2_RCR_REP_Msk = 0xffff

	// TIM2_CCR1: TIM2 capture/compare register 1
	// Position of CCR1 field.
	TIM2_TIM2_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM2_TIM2_CCR1_CCR1_Msk = 0xffff

	// TIM2_CCR2: TIM2 capture/compare register 2
	// Position of CCR2 field.
	TIM2_TIM2_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM2_TIM2_CCR2_CCR2_Msk = 0xffff

	// TIM2_CCR3: TIM2 capture/compare register 3
	// Position of CCR3 field.
	TIM2_TIM2_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM2_TIM2_CCR3_CCR3_Msk = 0xffff

	// TIM2_CCR4: TIM2 capture/compare register 4
	// Position of CCR4 field.
	TIM2_TIM2_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM2_TIM2_CCR4_CCR4_Msk = 0xffff

	// TIM2_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM2_TIM2_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM2_TIM2_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM2_TIM2_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM2_TIM2_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM2_TIM2_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM2_TIM2_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM2_TIM2_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM2_TIM2_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM2_TIM2_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM2_TIM2_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM2_TIM2_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM2_TIM2_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM2_TIM2_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM2_TIM2_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM2_TIM2_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM2_TIM2_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM2_TIM2_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM2_TIM2_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM2_TIM2_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM2_TIM2_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM2_TIM2_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM2_TIM2_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM2_TIM2_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM2_TIM2_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM2_TIM2_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM2_TIM2_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM2_TIM2_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM2_TIM2_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM2_TIM2_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM2_TIM2_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM2_TIM2_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM2_TIM2_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM2_TIM2_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM2_TIM2_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM2_TIM2_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM2_TIM2_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM2_TIM2_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM2_TIM2_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM2_TIM2_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM2_TIM2_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM2_TIM2_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM2_TIM2_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM2_TIM2_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM2_TIM2_BDTR_BK2BID = 0x20000000

	// TIM2_DCR: TIM2 DMA control register
	// Position of DBA field.
	TIM2_TIM2_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM2_TIM2_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM2_TIM2_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM2_TIM2_DCR_DBL_Msk = 0x1f00

	// TIM2_DMAR: TIM2 DMA address for full transfer
	// Position of DMAB field.
	TIM2_TIM2_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM2_TIM2_DMAR_DMAB_Msk = 0xffffffff

	// TIM2_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM2_TIM2_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM2_TIM2_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM2_TIM2_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM2_TIM2_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM2_TIM2_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM2_TIM2_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM2_TIM2_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM2_TIM2_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM2_TIM2_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM2_TIM2_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM2_TIM2_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM2_TIM2_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM2_TIM2_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM2_TIM2_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM2_TIM2_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM2_TIM2_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM2_TIM2_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM2_TIM2_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM2_TIM2_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM2_TIM2_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM2_TIM2_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM2_TIM2_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM2_TIM2_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM2_TIM2_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM2_TIM2_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM2_TIM2_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM2_TIM2_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM2_TIM2_CCMR3_OC6M3 = 0x1000000

	// TIM2_CCR5: TIM2 capture/compare register 5
	// Position of CCR5 field.
	TIM2_TIM2_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM2_TIM2_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM2_TIM2_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM2_TIM2_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM2_TIM2_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM2_TIM2_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM2_TIM2_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM2_TIM2_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM2_TIM2_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM2_TIM2_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM2_TIM2_CCR5_GC5C3 = 0x80000000

	// TIM2_CCR6: TIM2 capture/compare register 6
	// Position of CCR6 field.
	TIM2_TIM2_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM2_TIM2_CCR6_CCR6_Msk = 0xffff
)

// Bitfields for TIM3: TIM3
const (
	// TIM3_CR1: TIM3 control register 1
	// Position of CEN field.
	TIM3_TIM3_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM3_TIM3_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM3_TIM3_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM3_TIM3_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM3_TIM3_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM3_TIM3_CR1_UDIS = 0x2
	// Position of URS field.
	TIM3_TIM3_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM3_TIM3_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM3_TIM3_CR1_URS = 0x4
	// Position of OPM field.
	TIM3_TIM3_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM3_TIM3_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM3_TIM3_CR1_OPM = 0x8
	// Position of DIR field.
	TIM3_TIM3_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM3_TIM3_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM3_TIM3_CR1_DIR = 0x10
	// Position of CMS field.
	TIM3_TIM3_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM3_TIM3_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM3_TIM3_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM3_TIM3_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM3_TIM3_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM3_TIM3_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM3_TIM3_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM3_TIM3_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM3_TIM3_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM3_TIM3_CR1_UIFREMAP = 0x800

	// TIM3_CR2: TIM3 control register 2
	// Position of CCPC field.
	TIM3_TIM3_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM3_TIM3_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM3_TIM3_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM3_TIM3_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM3_TIM3_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM3_TIM3_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM3_TIM3_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM3_TIM3_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM3_TIM3_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM3_TIM3_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM3_TIM3_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM3_TIM3_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM3_TIM3_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM3_TIM3_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM3_TIM3_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM3_TIM3_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM3_TIM3_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM3_TIM3_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM3_TIM3_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM3_TIM3_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM3_TIM3_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM3_TIM3_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM3_TIM3_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM3_TIM3_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM3_TIM3_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM3_TIM3_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM3_TIM3_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM3_TIM3_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM3_TIM3_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM3_TIM3_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM3_TIM3_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM3_TIM3_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM3_TIM3_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM3_TIM3_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM3_TIM3_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM3_TIM3_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM3_TIM3_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM3_TIM3_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM3_TIM3_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM3_TIM3_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM3_TIM3_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM3_TIM3_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM3_TIM3_CR2_MMS2_Msk = 0xf00000

	// TIM3_SMCR: TIM3 slave mode control register
	// Position of SMS field.
	TIM3_TIM3_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM3_TIM3_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM3_TIM3_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM3_TIM3_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM3_TIM3_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM3_TIM3_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM3_TIM3_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM3_TIM3_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM3_TIM3_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM3_TIM3_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM3_TIM3_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM3_TIM3_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM3_TIM3_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM3_TIM3_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM3_TIM3_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM3_TIM3_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM3_TIM3_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM3_TIM3_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM3_TIM3_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM3_TIM3_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM3_TIM3_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM3_TIM3_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM3_TIM3_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM3_TIM3_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM3_TIM3_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM3_TIM3_SMCR_TS4 = 0x200000

	// TIM3_DIER: TIM3 DMA/interrupt enable register
	// Position of UIE field.
	TIM3_TIM3_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM3_TIM3_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM3_TIM3_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM3_TIM3_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM3_TIM3_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM3_TIM3_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM3_TIM3_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM3_TIM3_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM3_TIM3_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM3_TIM3_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM3_TIM3_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM3_TIM3_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM3_TIM3_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM3_TIM3_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM3_TIM3_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM3_TIM3_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM3_TIM3_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM3_TIM3_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM3_TIM3_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM3_TIM3_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM3_TIM3_DIER_TIE = 0x40
	// Position of BIE field.
	TIM3_TIM3_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM3_TIM3_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM3_TIM3_DIER_BIE = 0x80
	// Position of UDE field.
	TIM3_TIM3_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM3_TIM3_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM3_TIM3_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM3_TIM3_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM3_TIM3_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM3_TIM3_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM3_TIM3_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM3_TIM3_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM3_TIM3_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM3_TIM3_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM3_TIM3_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM3_TIM3_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM3_TIM3_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM3_TIM3_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM3_TIM3_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM3_TIM3_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM3_TIM3_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM3_TIM3_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM3_TIM3_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM3_TIM3_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM3_TIM3_DIER_TDE = 0x4000

	// TIM3_SR: TIM3 status register
	// Position of UIF field.
	TIM3_TIM3_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM3_TIM3_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM3_TIM3_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM3_TIM3_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM3_TIM3_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM3_TIM3_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM3_TIM3_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM3_TIM3_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM3_TIM3_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM3_TIM3_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM3_TIM3_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM3_TIM3_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM3_TIM3_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM3_TIM3_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM3_TIM3_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM3_TIM3_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM3_TIM3_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM3_TIM3_SR_COMIF = 0x20
	// Position of TIF field.
	TIM3_TIM3_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM3_TIM3_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM3_TIM3_SR_TIF = 0x40
	// Position of BIF field.
	TIM3_TIM3_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM3_TIM3_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM3_TIM3_SR_BIF = 0x80
	// Position of B2IF field.
	TIM3_TIM3_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM3_TIM3_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM3_TIM3_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM3_TIM3_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM3_TIM3_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM3_TIM3_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM3_TIM3_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM3_TIM3_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM3_TIM3_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM3_TIM3_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM3_TIM3_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM3_TIM3_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM3_TIM3_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM3_TIM3_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM3_TIM3_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM3_TIM3_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM3_TIM3_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM3_TIM3_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM3_TIM3_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM3_TIM3_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM3_TIM3_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM3_TIM3_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM3_TIM3_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM3_TIM3_SR_CC6IF = 0x20000

	// TIM3_EGR: TIM3 event generation register
	// Position of UG field.
	TIM3_TIM3_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM3_TIM3_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM3_TIM3_EGR_UG = 0x1
	// Position of CC1G field.
	TIM3_TIM3_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM3_TIM3_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM3_TIM3_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM3_TIM3_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM3_TIM3_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM3_TIM3_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM3_TIM3_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM3_TIM3_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM3_TIM3_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM3_TIM3_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM3_TIM3_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM3_TIM3_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM3_TIM3_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM3_TIM3_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM3_TIM3_EGR_COMG = 0x20
	// Position of TG field.
	TIM3_TIM3_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM3_TIM3_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM3_TIM3_EGR_TG = 0x40
	// Position of BG field.
	TIM3_TIM3_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM3_TIM3_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM3_TIM3_EGR_BG = 0x80
	// Position of B2G field.
	TIM3_TIM3_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM3_TIM3_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM3_TIM3_EGR_B2G = 0x100

	// TIM3_CCMR1ALTERNATE3: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM3_TIM3_CCMR1ALTERNATE3_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM3_TIM3_CCMR1ALTERNATE3_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM3_TIM3_CCMR1ALTERNATE3_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM3_TIM3_CCMR1ALTERNATE3_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM3_TIM3_CCMR1ALTERNATE3_IC2F_Msk = 0xf000

	// TIM3_CCMR2ALTERNATE19: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM3_TIM3_CCMR2ALTERNATE19_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM3_TIM3_CCMR2ALTERNATE19_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM3_TIM3_CCMR2ALTERNATE19_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM3_TIM3_CCMR2ALTERNATE19_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM3_TIM3_CCMR2ALTERNATE19_IC4F_Msk = 0xf000

	// TIM3_CCER: TIM3 capture/compare enable register
	// Position of CC1E field.
	TIM3_TIM3_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM3_TIM3_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM3_TIM3_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM3_TIM3_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM3_TIM3_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM3_TIM3_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM3_TIM3_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM3_TIM3_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM3_TIM3_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM3_TIM3_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM3_TIM3_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM3_TIM3_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM3_TIM3_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM3_TIM3_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM3_TIM3_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM3_TIM3_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM3_TIM3_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM3_TIM3_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM3_TIM3_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM3_TIM3_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM3_TIM3_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM3_TIM3_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM3_TIM3_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM3_TIM3_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM3_TIM3_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM3_TIM3_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM3_TIM3_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM3_TIM3_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM3_TIM3_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM3_TIM3_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM3_TIM3_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM3_TIM3_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM3_TIM3_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM3_TIM3_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM3_TIM3_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM3_TIM3_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM3_TIM3_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM3_TIM3_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM3_TIM3_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM3_TIM3_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM3_TIM3_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM3_TIM3_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM3_TIM3_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM3_TIM3_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM3_TIM3_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM3_TIM3_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM3_TIM3_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM3_TIM3_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM3_TIM3_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM3_TIM3_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM3_TIM3_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM3_TIM3_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM3_TIM3_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM3_TIM3_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM3_TIM3_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM3_TIM3_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM3_TIM3_CCER_CC6P = 0x200000

	// TIM3_CNT: TIM3 counter
	// Position of CNT field.
	TIM3_TIM3_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM3_TIM3_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM3_TIM3_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM3_TIM3_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM3_TIM3_CNT_UIFCPY = 0x80000000

	// TIM3_PSC: TIM3 prescaler
	// Position of PSC field.
	TIM3_TIM3_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM3_TIM3_PSC_PSC_Msk = 0xffff

	// TIM3_ARR: TIM3 auto-reload register
	// Position of ARR field.
	TIM3_TIM3_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM3_TIM3_ARR_ARR_Msk = 0xffff

	// TIM3_RCR: TIM3 repetition counter register
	// Position of REP field.
	TIM3_TIM3_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM3_TIM3_RCR_REP_Msk = 0xffff

	// TIM3_CCR1: TIM3 capture/compare register 1
	// Position of CCR1 field.
	TIM3_TIM3_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM3_TIM3_CCR1_CCR1_Msk = 0xffff

	// TIM3_CCR2: TIM3 capture/compare register 2
	// Position of CCR2 field.
	TIM3_TIM3_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM3_TIM3_CCR2_CCR2_Msk = 0xffff

	// TIM3_CCR3: TIM3 capture/compare register 3
	// Position of CCR3 field.
	TIM3_TIM3_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM3_TIM3_CCR3_CCR3_Msk = 0xffff

	// TIM3_CCR4: TIM3 capture/compare register 4
	// Position of CCR4 field.
	TIM3_TIM3_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM3_TIM3_CCR4_CCR4_Msk = 0xffff

	// TIM3_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM3_TIM3_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM3_TIM3_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM3_TIM3_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM3_TIM3_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM3_TIM3_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM3_TIM3_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM3_TIM3_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM3_TIM3_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM3_TIM3_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM3_TIM3_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM3_TIM3_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM3_TIM3_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM3_TIM3_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM3_TIM3_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM3_TIM3_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM3_TIM3_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM3_TIM3_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM3_TIM3_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM3_TIM3_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM3_TIM3_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM3_TIM3_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM3_TIM3_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM3_TIM3_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM3_TIM3_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM3_TIM3_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM3_TIM3_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM3_TIM3_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM3_TIM3_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM3_TIM3_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM3_TIM3_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM3_TIM3_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM3_TIM3_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM3_TIM3_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM3_TIM3_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM3_TIM3_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM3_TIM3_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM3_TIM3_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM3_TIM3_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM3_TIM3_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM3_TIM3_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM3_TIM3_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM3_TIM3_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM3_TIM3_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM3_TIM3_BDTR_BK2BID = 0x20000000

	// TIM3_DCR: TIM3 DMA control register
	// Position of DBA field.
	TIM3_TIM3_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM3_TIM3_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM3_TIM3_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM3_TIM3_DCR_DBL_Msk = 0x1f00

	// TIM3_DMAR: TIM3 DMA address for full transfer
	// Position of DMAB field.
	TIM3_TIM3_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM3_TIM3_DMAR_DMAB_Msk = 0xffffffff

	// TIM3_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM3_TIM3_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM3_TIM3_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM3_TIM3_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM3_TIM3_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM3_TIM3_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM3_TIM3_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM3_TIM3_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM3_TIM3_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM3_TIM3_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM3_TIM3_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM3_TIM3_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM3_TIM3_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM3_TIM3_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM3_TIM3_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM3_TIM3_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM3_TIM3_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM3_TIM3_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM3_TIM3_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM3_TIM3_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM3_TIM3_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM3_TIM3_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM3_TIM3_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM3_TIM3_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM3_TIM3_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM3_TIM3_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM3_TIM3_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM3_TIM3_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM3_TIM3_CCMR3_OC6M3 = 0x1000000

	// TIM3_CCR5: TIM3 capture/compare register 5
	// Position of CCR5 field.
	TIM3_TIM3_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM3_TIM3_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM3_TIM3_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM3_TIM3_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM3_TIM3_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM3_TIM3_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM3_TIM3_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM3_TIM3_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM3_TIM3_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM3_TIM3_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM3_TIM3_CCR5_GC5C3 = 0x80000000

	// TIM3_CCR6: TIM3 capture/compare register 6
	// Position of CCR6 field.
	TIM3_TIM3_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM3_TIM3_CCR6_CCR6_Msk = 0xffff
)

// Bitfields for TIM4: TIM4
const (
	// TIM4_CR1: TIM4 control register 1
	// Position of CEN field.
	TIM4_TIM4_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM4_TIM4_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM4_TIM4_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM4_TIM4_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM4_TIM4_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM4_TIM4_CR1_UDIS = 0x2
	// Position of URS field.
	TIM4_TIM4_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM4_TIM4_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM4_TIM4_CR1_URS = 0x4
	// Position of OPM field.
	TIM4_TIM4_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM4_TIM4_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM4_TIM4_CR1_OPM = 0x8
	// Position of DIR field.
	TIM4_TIM4_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM4_TIM4_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM4_TIM4_CR1_DIR = 0x10
	// Position of CMS field.
	TIM4_TIM4_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM4_TIM4_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM4_TIM4_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM4_TIM4_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM4_TIM4_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM4_TIM4_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM4_TIM4_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM4_TIM4_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM4_TIM4_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM4_TIM4_CR1_UIFREMAP = 0x800

	// TIM4_CR2: TIM4 control register 2
	// Position of CCPC field.
	TIM4_TIM4_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM4_TIM4_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM4_TIM4_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM4_TIM4_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM4_TIM4_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM4_TIM4_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM4_TIM4_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM4_TIM4_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM4_TIM4_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM4_TIM4_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM4_TIM4_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM4_TIM4_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM4_TIM4_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM4_TIM4_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM4_TIM4_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM4_TIM4_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM4_TIM4_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM4_TIM4_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM4_TIM4_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM4_TIM4_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM4_TIM4_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM4_TIM4_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM4_TIM4_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM4_TIM4_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM4_TIM4_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM4_TIM4_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM4_TIM4_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM4_TIM4_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM4_TIM4_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM4_TIM4_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM4_TIM4_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM4_TIM4_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM4_TIM4_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM4_TIM4_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM4_TIM4_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM4_TIM4_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM4_TIM4_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM4_TIM4_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM4_TIM4_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM4_TIM4_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM4_TIM4_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM4_TIM4_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM4_TIM4_CR2_MMS2_Msk = 0xf00000

	// TIM4_SMCR: TIM4 slave mode control register
	// Position of SMS field.
	TIM4_TIM4_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM4_TIM4_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM4_TIM4_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM4_TIM4_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM4_TIM4_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM4_TIM4_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM4_TIM4_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM4_TIM4_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM4_TIM4_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM4_TIM4_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM4_TIM4_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM4_TIM4_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM4_TIM4_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM4_TIM4_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM4_TIM4_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM4_TIM4_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM4_TIM4_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM4_TIM4_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM4_TIM4_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM4_TIM4_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM4_TIM4_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM4_TIM4_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM4_TIM4_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM4_TIM4_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM4_TIM4_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM4_TIM4_SMCR_TS4 = 0x200000

	// TIM4_DIER: TIM4 DMA/interrupt enable register
	// Position of UIE field.
	TIM4_TIM4_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM4_TIM4_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM4_TIM4_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM4_TIM4_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM4_TIM4_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM4_TIM4_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM4_TIM4_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM4_TIM4_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM4_TIM4_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM4_TIM4_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM4_TIM4_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM4_TIM4_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM4_TIM4_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM4_TIM4_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM4_TIM4_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM4_TIM4_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM4_TIM4_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM4_TIM4_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM4_TIM4_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM4_TIM4_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM4_TIM4_DIER_TIE = 0x40
	// Position of BIE field.
	TIM4_TIM4_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM4_TIM4_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM4_TIM4_DIER_BIE = 0x80
	// Position of UDE field.
	TIM4_TIM4_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM4_TIM4_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM4_TIM4_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM4_TIM4_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM4_TIM4_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM4_TIM4_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM4_TIM4_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM4_TIM4_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM4_TIM4_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM4_TIM4_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM4_TIM4_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM4_TIM4_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM4_TIM4_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM4_TIM4_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM4_TIM4_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM4_TIM4_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM4_TIM4_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM4_TIM4_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM4_TIM4_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM4_TIM4_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM4_TIM4_DIER_TDE = 0x4000

	// TIM4_SR: TIM4 status register
	// Position of UIF field.
	TIM4_TIM4_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM4_TIM4_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM4_TIM4_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM4_TIM4_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM4_TIM4_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM4_TIM4_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM4_TIM4_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM4_TIM4_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM4_TIM4_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM4_TIM4_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM4_TIM4_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM4_TIM4_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM4_TIM4_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM4_TIM4_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM4_TIM4_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM4_TIM4_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM4_TIM4_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM4_TIM4_SR_COMIF = 0x20
	// Position of TIF field.
	TIM4_TIM4_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM4_TIM4_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM4_TIM4_SR_TIF = 0x40
	// Position of BIF field.
	TIM4_TIM4_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM4_TIM4_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM4_TIM4_SR_BIF = 0x80
	// Position of B2IF field.
	TIM4_TIM4_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM4_TIM4_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM4_TIM4_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM4_TIM4_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM4_TIM4_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM4_TIM4_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM4_TIM4_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM4_TIM4_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM4_TIM4_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM4_TIM4_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM4_TIM4_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM4_TIM4_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM4_TIM4_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM4_TIM4_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM4_TIM4_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM4_TIM4_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM4_TIM4_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM4_TIM4_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM4_TIM4_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM4_TIM4_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM4_TIM4_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM4_TIM4_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM4_TIM4_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM4_TIM4_SR_CC6IF = 0x20000

	// TIM4_EGR: TIM4 event generation register
	// Position of UG field.
	TIM4_TIM4_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM4_TIM4_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM4_TIM4_EGR_UG = 0x1
	// Position of CC1G field.
	TIM4_TIM4_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM4_TIM4_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM4_TIM4_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM4_TIM4_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM4_TIM4_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM4_TIM4_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM4_TIM4_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM4_TIM4_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM4_TIM4_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM4_TIM4_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM4_TIM4_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM4_TIM4_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM4_TIM4_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM4_TIM4_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM4_TIM4_EGR_COMG = 0x20
	// Position of TG field.
	TIM4_TIM4_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM4_TIM4_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM4_TIM4_EGR_TG = 0x40
	// Position of BG field.
	TIM4_TIM4_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM4_TIM4_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM4_TIM4_EGR_BG = 0x80
	// Position of B2G field.
	TIM4_TIM4_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM4_TIM4_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM4_TIM4_EGR_B2G = 0x100

	// TIM4_CCMR1ALTERNATE4: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM4_TIM4_CCMR1ALTERNATE4_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM4_TIM4_CCMR1ALTERNATE4_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM4_TIM4_CCMR1ALTERNATE4_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM4_TIM4_CCMR1ALTERNATE4_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM4_TIM4_CCMR1ALTERNATE4_IC2F_Msk = 0xf000

	// TIM4_CCMR2ALTERNATE20: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM4_TIM4_CCMR2ALTERNATE20_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM4_TIM4_CCMR2ALTERNATE20_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM4_TIM4_CCMR2ALTERNATE20_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM4_TIM4_CCMR2ALTERNATE20_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM4_TIM4_CCMR2ALTERNATE20_IC4F_Msk = 0xf000

	// TIM4_CCER: TIM4 capture/compare enable register
	// Position of CC1E field.
	TIM4_TIM4_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM4_TIM4_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM4_TIM4_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM4_TIM4_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM4_TIM4_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM4_TIM4_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM4_TIM4_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM4_TIM4_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM4_TIM4_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM4_TIM4_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM4_TIM4_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM4_TIM4_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM4_TIM4_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM4_TIM4_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM4_TIM4_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM4_TIM4_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM4_TIM4_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM4_TIM4_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM4_TIM4_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM4_TIM4_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM4_TIM4_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM4_TIM4_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM4_TIM4_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM4_TIM4_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM4_TIM4_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM4_TIM4_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM4_TIM4_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM4_TIM4_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM4_TIM4_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM4_TIM4_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM4_TIM4_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM4_TIM4_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM4_TIM4_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM4_TIM4_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM4_TIM4_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM4_TIM4_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM4_TIM4_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM4_TIM4_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM4_TIM4_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM4_TIM4_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM4_TIM4_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM4_TIM4_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM4_TIM4_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM4_TIM4_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM4_TIM4_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM4_TIM4_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM4_TIM4_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM4_TIM4_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM4_TIM4_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM4_TIM4_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM4_TIM4_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM4_TIM4_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM4_TIM4_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM4_TIM4_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM4_TIM4_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM4_TIM4_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM4_TIM4_CCER_CC6P = 0x200000

	// TIM4_CNT: TIM4 counter
	// Position of CNT field.
	TIM4_TIM4_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM4_TIM4_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM4_TIM4_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM4_TIM4_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM4_TIM4_CNT_UIFCPY = 0x80000000

	// TIM4_PSC: TIM4 prescaler
	// Position of PSC field.
	TIM4_TIM4_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM4_TIM4_PSC_PSC_Msk = 0xffff

	// TIM4_ARR: TIM4 auto-reload register
	// Position of ARR field.
	TIM4_TIM4_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM4_TIM4_ARR_ARR_Msk = 0xffff

	// TIM4_RCR: TIM4 repetition counter register
	// Position of REP field.
	TIM4_TIM4_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM4_TIM4_RCR_REP_Msk = 0xffff

	// TIM4_CCR1: TIM4 capture/compare register 1
	// Position of CCR1 field.
	TIM4_TIM4_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM4_TIM4_CCR1_CCR1_Msk = 0xffff

	// TIM4_CCR2: TIM4 capture/compare register 2
	// Position of CCR2 field.
	TIM4_TIM4_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM4_TIM4_CCR2_CCR2_Msk = 0xffff

	// TIM4_CCR3: TIM4 capture/compare register 3
	// Position of CCR3 field.
	TIM4_TIM4_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM4_TIM4_CCR3_CCR3_Msk = 0xffff

	// TIM4_CCR4: TIM4 capture/compare register 4
	// Position of CCR4 field.
	TIM4_TIM4_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM4_TIM4_CCR4_CCR4_Msk = 0xffff

	// TIM4_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM4_TIM4_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM4_TIM4_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM4_TIM4_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM4_TIM4_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM4_TIM4_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM4_TIM4_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM4_TIM4_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM4_TIM4_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM4_TIM4_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM4_TIM4_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM4_TIM4_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM4_TIM4_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM4_TIM4_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM4_TIM4_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM4_TIM4_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM4_TIM4_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM4_TIM4_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM4_TIM4_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM4_TIM4_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM4_TIM4_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM4_TIM4_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM4_TIM4_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM4_TIM4_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM4_TIM4_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM4_TIM4_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM4_TIM4_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM4_TIM4_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM4_TIM4_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM4_TIM4_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM4_TIM4_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM4_TIM4_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM4_TIM4_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM4_TIM4_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM4_TIM4_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM4_TIM4_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM4_TIM4_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM4_TIM4_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM4_TIM4_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM4_TIM4_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM4_TIM4_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM4_TIM4_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM4_TIM4_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM4_TIM4_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM4_TIM4_BDTR_BK2BID = 0x20000000

	// TIM4_DCR: TIM4 DMA control register
	// Position of DBA field.
	TIM4_TIM4_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM4_TIM4_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM4_TIM4_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM4_TIM4_DCR_DBL_Msk = 0x1f00

	// TIM4_DMAR: TIM4 DMA address for full transfer
	// Position of DMAB field.
	TIM4_TIM4_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM4_TIM4_DMAR_DMAB_Msk = 0xffffffff

	// TIM4_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM4_TIM4_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM4_TIM4_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM4_TIM4_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM4_TIM4_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM4_TIM4_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM4_TIM4_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM4_TIM4_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM4_TIM4_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM4_TIM4_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM4_TIM4_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM4_TIM4_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM4_TIM4_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM4_TIM4_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM4_TIM4_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM4_TIM4_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM4_TIM4_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM4_TIM4_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM4_TIM4_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM4_TIM4_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM4_TIM4_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM4_TIM4_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM4_TIM4_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM4_TIM4_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM4_TIM4_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM4_TIM4_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM4_TIM4_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM4_TIM4_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM4_TIM4_CCMR3_OC6M3 = 0x1000000

	// TIM4_CCR5: TIM4 capture/compare register 5
	// Position of CCR5 field.
	TIM4_TIM4_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM4_TIM4_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM4_TIM4_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM4_TIM4_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM4_TIM4_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM4_TIM4_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM4_TIM4_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM4_TIM4_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM4_TIM4_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM4_TIM4_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM4_TIM4_CCR5_GC5C3 = 0x80000000

	// TIM4_CCR6: TIM4 capture/compare register 6
	// Position of CCR6 field.
	TIM4_TIM4_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM4_TIM4_CCR6_CCR6_Msk = 0xffff
)

// Bitfields for TIM5: TIM5
const (
	// TIM5_CR1: TIM5 control register 1
	// Position of CEN field.
	TIM5_TIM5_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM5_TIM5_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM5_TIM5_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM5_TIM5_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM5_TIM5_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM5_TIM5_CR1_UDIS = 0x2
	// Position of URS field.
	TIM5_TIM5_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM5_TIM5_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM5_TIM5_CR1_URS = 0x4
	// Position of OPM field.
	TIM5_TIM5_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM5_TIM5_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM5_TIM5_CR1_OPM = 0x8
	// Position of DIR field.
	TIM5_TIM5_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM5_TIM5_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM5_TIM5_CR1_DIR = 0x10
	// Position of CMS field.
	TIM5_TIM5_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM5_TIM5_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM5_TIM5_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM5_TIM5_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM5_TIM5_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM5_TIM5_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM5_TIM5_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM5_TIM5_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM5_TIM5_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM5_TIM5_CR1_UIFREMAP = 0x800

	// TIM5_CR2: TIM5 control register 2
	// Position of CCPC field.
	TIM5_TIM5_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM5_TIM5_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM5_TIM5_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM5_TIM5_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM5_TIM5_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM5_TIM5_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM5_TIM5_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM5_TIM5_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM5_TIM5_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM5_TIM5_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM5_TIM5_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM5_TIM5_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM5_TIM5_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM5_TIM5_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM5_TIM5_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM5_TIM5_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM5_TIM5_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM5_TIM5_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM5_TIM5_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM5_TIM5_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM5_TIM5_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM5_TIM5_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM5_TIM5_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM5_TIM5_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM5_TIM5_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM5_TIM5_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM5_TIM5_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM5_TIM5_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM5_TIM5_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM5_TIM5_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM5_TIM5_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM5_TIM5_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM5_TIM5_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM5_TIM5_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM5_TIM5_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM5_TIM5_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM5_TIM5_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM5_TIM5_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM5_TIM5_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM5_TIM5_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM5_TIM5_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM5_TIM5_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM5_TIM5_CR2_MMS2_Msk = 0xf00000

	// TIM5_SMCR: TIM5 slave mode control register
	// Position of SMS field.
	TIM5_TIM5_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM5_TIM5_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM5_TIM5_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM5_TIM5_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM5_TIM5_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM5_TIM5_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM5_TIM5_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM5_TIM5_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM5_TIM5_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM5_TIM5_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM5_TIM5_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM5_TIM5_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM5_TIM5_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM5_TIM5_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM5_TIM5_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM5_TIM5_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM5_TIM5_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM5_TIM5_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM5_TIM5_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM5_TIM5_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM5_TIM5_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM5_TIM5_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM5_TIM5_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM5_TIM5_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM5_TIM5_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM5_TIM5_SMCR_TS4 = 0x200000

	// TIM5_DIER: TIM5 DMA/interrupt enable register
	// Position of UIE field.
	TIM5_TIM5_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM5_TIM5_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM5_TIM5_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM5_TIM5_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM5_TIM5_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM5_TIM5_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM5_TIM5_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM5_TIM5_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM5_TIM5_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM5_TIM5_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM5_TIM5_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM5_TIM5_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM5_TIM5_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM5_TIM5_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM5_TIM5_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM5_TIM5_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM5_TIM5_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM5_TIM5_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM5_TIM5_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM5_TIM5_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM5_TIM5_DIER_TIE = 0x40
	// Position of BIE field.
	TIM5_TIM5_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM5_TIM5_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM5_TIM5_DIER_BIE = 0x80
	// Position of UDE field.
	TIM5_TIM5_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM5_TIM5_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM5_TIM5_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM5_TIM5_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM5_TIM5_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM5_TIM5_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM5_TIM5_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM5_TIM5_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM5_TIM5_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM5_TIM5_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM5_TIM5_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM5_TIM5_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM5_TIM5_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM5_TIM5_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM5_TIM5_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM5_TIM5_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM5_TIM5_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM5_TIM5_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM5_TIM5_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM5_TIM5_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM5_TIM5_DIER_TDE = 0x4000

	// TIM5_SR: TIM5 status register
	// Position of UIF field.
	TIM5_TIM5_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM5_TIM5_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM5_TIM5_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM5_TIM5_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM5_TIM5_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM5_TIM5_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM5_TIM5_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM5_TIM5_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM5_TIM5_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM5_TIM5_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM5_TIM5_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM5_TIM5_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM5_TIM5_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM5_TIM5_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM5_TIM5_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM5_TIM5_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM5_TIM5_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM5_TIM5_SR_COMIF = 0x20
	// Position of TIF field.
	TIM5_TIM5_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM5_TIM5_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM5_TIM5_SR_TIF = 0x40
	// Position of BIF field.
	TIM5_TIM5_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM5_TIM5_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM5_TIM5_SR_BIF = 0x80
	// Position of B2IF field.
	TIM5_TIM5_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM5_TIM5_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM5_TIM5_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM5_TIM5_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM5_TIM5_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM5_TIM5_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM5_TIM5_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM5_TIM5_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM5_TIM5_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM5_TIM5_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM5_TIM5_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM5_TIM5_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM5_TIM5_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM5_TIM5_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM5_TIM5_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM5_TIM5_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM5_TIM5_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM5_TIM5_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM5_TIM5_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM5_TIM5_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM5_TIM5_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM5_TIM5_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM5_TIM5_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM5_TIM5_SR_CC6IF = 0x20000

	// TIM5_EGR: TIM5 event generation register
	// Position of UG field.
	TIM5_TIM5_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM5_TIM5_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM5_TIM5_EGR_UG = 0x1
	// Position of CC1G field.
	TIM5_TIM5_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM5_TIM5_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM5_TIM5_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM5_TIM5_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM5_TIM5_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM5_TIM5_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM5_TIM5_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM5_TIM5_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM5_TIM5_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM5_TIM5_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM5_TIM5_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM5_TIM5_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM5_TIM5_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM5_TIM5_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM5_TIM5_EGR_COMG = 0x20
	// Position of TG field.
	TIM5_TIM5_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM5_TIM5_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM5_TIM5_EGR_TG = 0x40
	// Position of BG field.
	TIM5_TIM5_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM5_TIM5_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM5_TIM5_EGR_BG = 0x80
	// Position of B2G field.
	TIM5_TIM5_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM5_TIM5_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM5_TIM5_EGR_B2G = 0x100

	// TIM5_CCMR1ALTERNATE5: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM5_TIM5_CCMR1ALTERNATE5_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM5_TIM5_CCMR1ALTERNATE5_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM5_TIM5_CCMR1ALTERNATE5_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM5_TIM5_CCMR1ALTERNATE5_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM5_TIM5_CCMR1ALTERNATE5_IC2F_Msk = 0xf000

	// TIM5_CCMR2ALTERNATE21: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM5_TIM5_CCMR2ALTERNATE21_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM5_TIM5_CCMR2ALTERNATE21_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM5_TIM5_CCMR2ALTERNATE21_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM5_TIM5_CCMR2ALTERNATE21_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM5_TIM5_CCMR2ALTERNATE21_IC4F_Msk = 0xf000

	// TIM5_CCER: TIM5 capture/compare enable register
	// Position of CC1E field.
	TIM5_TIM5_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM5_TIM5_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM5_TIM5_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM5_TIM5_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM5_TIM5_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM5_TIM5_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM5_TIM5_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM5_TIM5_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM5_TIM5_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM5_TIM5_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM5_TIM5_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM5_TIM5_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM5_TIM5_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM5_TIM5_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM5_TIM5_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM5_TIM5_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM5_TIM5_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM5_TIM5_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM5_TIM5_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM5_TIM5_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM5_TIM5_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM5_TIM5_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM5_TIM5_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM5_TIM5_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM5_TIM5_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM5_TIM5_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM5_TIM5_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM5_TIM5_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM5_TIM5_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM5_TIM5_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM5_TIM5_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM5_TIM5_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM5_TIM5_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM5_TIM5_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM5_TIM5_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM5_TIM5_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM5_TIM5_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM5_TIM5_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM5_TIM5_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM5_TIM5_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM5_TIM5_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM5_TIM5_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM5_TIM5_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM5_TIM5_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM5_TIM5_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM5_TIM5_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM5_TIM5_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM5_TIM5_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM5_TIM5_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM5_TIM5_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM5_TIM5_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM5_TIM5_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM5_TIM5_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM5_TIM5_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM5_TIM5_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM5_TIM5_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM5_TIM5_CCER_CC6P = 0x200000

	// TIM5_CNT: TIM5 counter
	// Position of CNT field.
	TIM5_TIM5_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM5_TIM5_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM5_TIM5_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM5_TIM5_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM5_TIM5_CNT_UIFCPY = 0x80000000

	// TIM5_PSC: TIM5 prescaler
	// Position of PSC field.
	TIM5_TIM5_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM5_TIM5_PSC_PSC_Msk = 0xffff

	// TIM5_ARR: TIM5 auto-reload register
	// Position of ARR field.
	TIM5_TIM5_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM5_TIM5_ARR_ARR_Msk = 0xffff

	// TIM5_RCR: TIM5 repetition counter register
	// Position of REP field.
	TIM5_TIM5_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM5_TIM5_RCR_REP_Msk = 0xffff

	// TIM5_CCR1: TIM5 capture/compare register 1
	// Position of CCR1 field.
	TIM5_TIM5_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM5_TIM5_CCR1_CCR1_Msk = 0xffff

	// TIM5_CCR2: TIM5 capture/compare register 2
	// Position of CCR2 field.
	TIM5_TIM5_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM5_TIM5_CCR2_CCR2_Msk = 0xffff

	// TIM5_CCR3: TIM5 capture/compare register 3
	// Position of CCR3 field.
	TIM5_TIM5_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM5_TIM5_CCR3_CCR3_Msk = 0xffff

	// TIM5_CCR4: TIM5 capture/compare register 4
	// Position of CCR4 field.
	TIM5_TIM5_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM5_TIM5_CCR4_CCR4_Msk = 0xffff

	// TIM5_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM5_TIM5_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM5_TIM5_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM5_TIM5_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM5_TIM5_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM5_TIM5_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM5_TIM5_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM5_TIM5_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM5_TIM5_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM5_TIM5_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM5_TIM5_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM5_TIM5_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM5_TIM5_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM5_TIM5_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM5_TIM5_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM5_TIM5_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM5_TIM5_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM5_TIM5_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM5_TIM5_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM5_TIM5_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM5_TIM5_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM5_TIM5_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM5_TIM5_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM5_TIM5_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM5_TIM5_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM5_TIM5_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM5_TIM5_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM5_TIM5_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM5_TIM5_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM5_TIM5_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM5_TIM5_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM5_TIM5_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM5_TIM5_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM5_TIM5_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM5_TIM5_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM5_TIM5_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM5_TIM5_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM5_TIM5_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM5_TIM5_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM5_TIM5_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM5_TIM5_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM5_TIM5_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM5_TIM5_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM5_TIM5_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM5_TIM5_BDTR_BK2BID = 0x20000000

	// TIM5_DCR: TIM5 DMA control register
	// Position of DBA field.
	TIM5_TIM5_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM5_TIM5_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM5_TIM5_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM5_TIM5_DCR_DBL_Msk = 0x1f00

	// TIM5_DMAR: TIM5 DMA address for full transfer
	// Position of DMAB field.
	TIM5_TIM5_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM5_TIM5_DMAR_DMAB_Msk = 0xffffffff

	// TIM5_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM5_TIM5_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM5_TIM5_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM5_TIM5_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM5_TIM5_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM5_TIM5_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM5_TIM5_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM5_TIM5_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM5_TIM5_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM5_TIM5_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM5_TIM5_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM5_TIM5_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM5_TIM5_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM5_TIM5_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM5_TIM5_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM5_TIM5_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM5_TIM5_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM5_TIM5_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM5_TIM5_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM5_TIM5_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM5_TIM5_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM5_TIM5_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM5_TIM5_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM5_TIM5_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM5_TIM5_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM5_TIM5_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM5_TIM5_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM5_TIM5_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM5_TIM5_CCMR3_OC6M3 = 0x1000000

	// TIM5_CCR5: TIM5 capture/compare register 5
	// Position of CCR5 field.
	TIM5_TIM5_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM5_TIM5_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM5_TIM5_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM5_TIM5_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM5_TIM5_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM5_TIM5_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM5_TIM5_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM5_TIM5_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM5_TIM5_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM5_TIM5_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM5_TIM5_CCR5_GC5C3 = 0x80000000

	// TIM5_CCR6: TIM5 capture/compare register 6
	// Position of CCR6 field.
	TIM5_TIM5_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM5_TIM5_CCR6_CCR6_Msk = 0xffff
)

// Bitfields for TIM6: TIM6
const (
	// TIM6_CR1: TIM6 control register 1
	// Position of CEN field.
	TIM6_TIM6_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM6_TIM6_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM6_TIM6_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM6_TIM6_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM6_TIM6_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM6_TIM6_CR1_UDIS = 0x2
	// Position of URS field.
	TIM6_TIM6_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM6_TIM6_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM6_TIM6_CR1_URS = 0x4
	// Position of OPM field.
	TIM6_TIM6_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM6_TIM6_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM6_TIM6_CR1_OPM = 0x8
	// Position of DIR field.
	TIM6_TIM6_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM6_TIM6_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM6_TIM6_CR1_DIR = 0x10
	// Position of CMS field.
	TIM6_TIM6_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM6_TIM6_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM6_TIM6_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM6_TIM6_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM6_TIM6_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM6_TIM6_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM6_TIM6_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM6_TIM6_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM6_TIM6_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM6_TIM6_CR1_UIFREMAP = 0x800

	// TIM6_CR2: TIM6 control register 2
	// Position of CCPC field.
	TIM6_TIM6_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM6_TIM6_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM6_TIM6_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM6_TIM6_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM6_TIM6_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM6_TIM6_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM6_TIM6_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM6_TIM6_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM6_TIM6_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM6_TIM6_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM6_TIM6_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM6_TIM6_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM6_TIM6_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM6_TIM6_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM6_TIM6_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM6_TIM6_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM6_TIM6_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM6_TIM6_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM6_TIM6_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM6_TIM6_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM6_TIM6_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM6_TIM6_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM6_TIM6_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM6_TIM6_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM6_TIM6_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM6_TIM6_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM6_TIM6_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM6_TIM6_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM6_TIM6_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM6_TIM6_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM6_TIM6_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM6_TIM6_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM6_TIM6_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM6_TIM6_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM6_TIM6_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM6_TIM6_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM6_TIM6_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM6_TIM6_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM6_TIM6_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM6_TIM6_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM6_TIM6_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM6_TIM6_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM6_TIM6_CR2_MMS2_Msk = 0xf00000

	// TIM6_SMCR: TIM6 slave mode control register
	// Position of SMS field.
	TIM6_TIM6_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM6_TIM6_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM6_TIM6_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM6_TIM6_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM6_TIM6_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM6_TIM6_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM6_TIM6_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM6_TIM6_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM6_TIM6_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM6_TIM6_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM6_TIM6_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM6_TIM6_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM6_TIM6_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM6_TIM6_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM6_TIM6_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM6_TIM6_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM6_TIM6_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM6_TIM6_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM6_TIM6_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM6_TIM6_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM6_TIM6_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM6_TIM6_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM6_TIM6_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM6_TIM6_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM6_TIM6_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM6_TIM6_SMCR_TS4 = 0x200000

	// TIM6_DIER: TIM6 DMA/interrupt enable register
	// Position of UIE field.
	TIM6_TIM6_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM6_TIM6_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM6_TIM6_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM6_TIM6_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM6_TIM6_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM6_TIM6_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM6_TIM6_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM6_TIM6_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM6_TIM6_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM6_TIM6_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM6_TIM6_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM6_TIM6_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM6_TIM6_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM6_TIM6_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM6_TIM6_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM6_TIM6_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM6_TIM6_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM6_TIM6_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM6_TIM6_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM6_TIM6_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM6_TIM6_DIER_TIE = 0x40
	// Position of BIE field.
	TIM6_TIM6_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM6_TIM6_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM6_TIM6_DIER_BIE = 0x80
	// Position of UDE field.
	TIM6_TIM6_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM6_TIM6_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM6_TIM6_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM6_TIM6_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM6_TIM6_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM6_TIM6_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM6_TIM6_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM6_TIM6_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM6_TIM6_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM6_TIM6_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM6_TIM6_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM6_TIM6_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM6_TIM6_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM6_TIM6_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM6_TIM6_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM6_TIM6_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM6_TIM6_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM6_TIM6_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM6_TIM6_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM6_TIM6_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM6_TIM6_DIER_TDE = 0x4000

	// TIM6_SR: TIM6 status register
	// Position of UIF field.
	TIM6_TIM6_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM6_TIM6_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM6_TIM6_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM6_TIM6_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM6_TIM6_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM6_TIM6_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM6_TIM6_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM6_TIM6_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM6_TIM6_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM6_TIM6_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM6_TIM6_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM6_TIM6_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM6_TIM6_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM6_TIM6_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM6_TIM6_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM6_TIM6_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM6_TIM6_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM6_TIM6_SR_COMIF = 0x20
	// Position of TIF field.
	TIM6_TIM6_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM6_TIM6_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM6_TIM6_SR_TIF = 0x40
	// Position of BIF field.
	TIM6_TIM6_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM6_TIM6_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM6_TIM6_SR_BIF = 0x80
	// Position of B2IF field.
	TIM6_TIM6_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM6_TIM6_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM6_TIM6_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM6_TIM6_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM6_TIM6_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM6_TIM6_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM6_TIM6_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM6_TIM6_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM6_TIM6_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM6_TIM6_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM6_TIM6_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM6_TIM6_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM6_TIM6_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM6_TIM6_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM6_TIM6_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM6_TIM6_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM6_TIM6_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM6_TIM6_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM6_TIM6_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM6_TIM6_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM6_TIM6_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM6_TIM6_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM6_TIM6_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM6_TIM6_SR_CC6IF = 0x20000

	// TIM6_EGR: TIM6 event generation register
	// Position of UG field.
	TIM6_TIM6_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM6_TIM6_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM6_TIM6_EGR_UG = 0x1
	// Position of CC1G field.
	TIM6_TIM6_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM6_TIM6_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM6_TIM6_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM6_TIM6_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM6_TIM6_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM6_TIM6_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM6_TIM6_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM6_TIM6_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM6_TIM6_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM6_TIM6_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM6_TIM6_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM6_TIM6_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM6_TIM6_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM6_TIM6_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM6_TIM6_EGR_COMG = 0x20
	// Position of TG field.
	TIM6_TIM6_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM6_TIM6_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM6_TIM6_EGR_TG = 0x40
	// Position of BG field.
	TIM6_TIM6_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM6_TIM6_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM6_TIM6_EGR_BG = 0x80
	// Position of B2G field.
	TIM6_TIM6_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM6_TIM6_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM6_TIM6_EGR_B2G = 0x100

	// TIM6_CCMR1ALTERNATE6: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM6_TIM6_CCMR1ALTERNATE6_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM6_TIM6_CCMR1ALTERNATE6_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM6_TIM6_CCMR1ALTERNATE6_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM6_TIM6_CCMR1ALTERNATE6_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM6_TIM6_CCMR1ALTERNATE6_IC2F_Msk = 0xf000

	// TIM6_CCMR2ALTERNATE22: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM6_TIM6_CCMR2ALTERNATE22_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM6_TIM6_CCMR2ALTERNATE22_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM6_TIM6_CCMR2ALTERNATE22_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM6_TIM6_CCMR2ALTERNATE22_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM6_TIM6_CCMR2ALTERNATE22_IC4F_Msk = 0xf000

	// TIM6_CCER: TIM6 capture/compare enable register
	// Position of CC1E field.
	TIM6_TIM6_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM6_TIM6_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM6_TIM6_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM6_TIM6_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM6_TIM6_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM6_TIM6_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM6_TIM6_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM6_TIM6_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM6_TIM6_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM6_TIM6_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM6_TIM6_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM6_TIM6_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM6_TIM6_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM6_TIM6_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM6_TIM6_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM6_TIM6_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM6_TIM6_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM6_TIM6_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM6_TIM6_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM6_TIM6_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM6_TIM6_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM6_TIM6_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM6_TIM6_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM6_TIM6_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM6_TIM6_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM6_TIM6_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM6_TIM6_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM6_TIM6_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM6_TIM6_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM6_TIM6_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM6_TIM6_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM6_TIM6_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM6_TIM6_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM6_TIM6_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM6_TIM6_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM6_TIM6_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM6_TIM6_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM6_TIM6_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM6_TIM6_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM6_TIM6_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM6_TIM6_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM6_TIM6_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM6_TIM6_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM6_TIM6_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM6_TIM6_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM6_TIM6_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM6_TIM6_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM6_TIM6_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM6_TIM6_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM6_TIM6_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM6_TIM6_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM6_TIM6_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM6_TIM6_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM6_TIM6_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM6_TIM6_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM6_TIM6_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM6_TIM6_CCER_CC6P = 0x200000

	// TIM6_CNT: TIM6 counter
	// Position of CNT field.
	TIM6_TIM6_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM6_TIM6_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM6_TIM6_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM6_TIM6_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM6_TIM6_CNT_UIFCPY = 0x80000000

	// TIM6_PSC: TIM6 prescaler
	// Position of PSC field.
	TIM6_TIM6_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM6_TIM6_PSC_PSC_Msk = 0xffff

	// TIM6_ARR: TIM6 auto-reload register
	// Position of ARR field.
	TIM6_TIM6_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM6_TIM6_ARR_ARR_Msk = 0xffff

	// TIM6_RCR: TIM6 repetition counter register
	// Position of REP field.
	TIM6_TIM6_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM6_TIM6_RCR_REP_Msk = 0xffff

	// TIM6_CCR1: TIM6 capture/compare register 1
	// Position of CCR1 field.
	TIM6_TIM6_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM6_TIM6_CCR1_CCR1_Msk = 0xffff

	// TIM6_CCR2: TIM6 capture/compare register 2
	// Position of CCR2 field.
	TIM6_TIM6_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM6_TIM6_CCR2_CCR2_Msk = 0xffff

	// TIM6_CCR3: TIM6 capture/compare register 3
	// Position of CCR3 field.
	TIM6_TIM6_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM6_TIM6_CCR3_CCR3_Msk = 0xffff

	// TIM6_CCR4: TIM6 capture/compare register 4
	// Position of CCR4 field.
	TIM6_TIM6_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM6_TIM6_CCR4_CCR4_Msk = 0xffff

	// TIM6_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM6_TIM6_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM6_TIM6_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM6_TIM6_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM6_TIM6_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM6_TIM6_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM6_TIM6_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM6_TIM6_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM6_TIM6_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM6_TIM6_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM6_TIM6_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM6_TIM6_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM6_TIM6_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM6_TIM6_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM6_TIM6_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM6_TIM6_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM6_TIM6_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM6_TIM6_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM6_TIM6_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM6_TIM6_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM6_TIM6_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM6_TIM6_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM6_TIM6_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM6_TIM6_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM6_TIM6_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM6_TIM6_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM6_TIM6_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM6_TIM6_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM6_TIM6_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM6_TIM6_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM6_TIM6_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM6_TIM6_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM6_TIM6_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM6_TIM6_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM6_TIM6_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM6_TIM6_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM6_TIM6_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM6_TIM6_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM6_TIM6_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM6_TIM6_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM6_TIM6_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM6_TIM6_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM6_TIM6_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM6_TIM6_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM6_TIM6_BDTR_BK2BID = 0x20000000

	// TIM6_DCR: TIM6 DMA control register
	// Position of DBA field.
	TIM6_TIM6_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM6_TIM6_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM6_TIM6_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM6_TIM6_DCR_DBL_Msk = 0x1f00

	// TIM6_DMAR: TIM6 DMA address for full transfer
	// Position of DMAB field.
	TIM6_TIM6_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM6_TIM6_DMAR_DMAB_Msk = 0xffffffff

	// TIM6_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM6_TIM6_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM6_TIM6_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM6_TIM6_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM6_TIM6_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM6_TIM6_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM6_TIM6_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM6_TIM6_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM6_TIM6_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM6_TIM6_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM6_TIM6_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM6_TIM6_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM6_TIM6_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM6_TIM6_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM6_TIM6_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM6_TIM6_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM6_TIM6_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM6_TIM6_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM6_TIM6_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM6_TIM6_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM6_TIM6_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM6_TIM6_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM6_TIM6_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM6_TIM6_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM6_TIM6_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM6_TIM6_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM6_TIM6_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM6_TIM6_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM6_TIM6_CCMR3_OC6M3 = 0x1000000

	// TIM6_CCR5: TIM6 capture/compare register 5
	// Position of CCR5 field.
	TIM6_TIM6_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM6_TIM6_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM6_TIM6_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM6_TIM6_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM6_TIM6_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM6_TIM6_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM6_TIM6_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM6_TIM6_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM6_TIM6_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM6_TIM6_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM6_TIM6_CCR5_GC5C3 = 0x80000000

	// TIM6_CCR6: TIM6 capture/compare register 6
	// Position of CCR6 field.
	TIM6_TIM6_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM6_TIM6_CCR6_CCR6_Msk = 0xffff
)

// Bitfields for TIM7: TIM7
const (
	// TIM7_CR1: TIM7 control register 1
	// Position of CEN field.
	TIM7_TIM7_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM7_TIM7_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM7_TIM7_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM7_TIM7_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM7_TIM7_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM7_TIM7_CR1_UDIS = 0x2
	// Position of URS field.
	TIM7_TIM7_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM7_TIM7_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM7_TIM7_CR1_URS = 0x4
	// Position of OPM field.
	TIM7_TIM7_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM7_TIM7_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM7_TIM7_CR1_OPM = 0x8
	// Position of DIR field.
	TIM7_TIM7_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM7_TIM7_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM7_TIM7_CR1_DIR = 0x10
	// Position of CMS field.
	TIM7_TIM7_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM7_TIM7_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM7_TIM7_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM7_TIM7_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM7_TIM7_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM7_TIM7_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM7_TIM7_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM7_TIM7_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM7_TIM7_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM7_TIM7_CR1_UIFREMAP = 0x800

	// TIM7_CR2: TIM7 control register 2
	// Position of CCPC field.
	TIM7_TIM7_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM7_TIM7_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM7_TIM7_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM7_TIM7_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM7_TIM7_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM7_TIM7_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM7_TIM7_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM7_TIM7_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM7_TIM7_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM7_TIM7_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM7_TIM7_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM7_TIM7_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM7_TIM7_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM7_TIM7_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM7_TIM7_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM7_TIM7_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM7_TIM7_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM7_TIM7_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM7_TIM7_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM7_TIM7_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM7_TIM7_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM7_TIM7_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM7_TIM7_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM7_TIM7_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM7_TIM7_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM7_TIM7_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM7_TIM7_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM7_TIM7_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM7_TIM7_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM7_TIM7_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM7_TIM7_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM7_TIM7_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM7_TIM7_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM7_TIM7_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM7_TIM7_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM7_TIM7_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM7_TIM7_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM7_TIM7_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM7_TIM7_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM7_TIM7_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM7_TIM7_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM7_TIM7_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM7_TIM7_CR2_MMS2_Msk = 0xf00000

	// TIM7_SMCR: TIM7 slave mode control register
	// Position of SMS field.
	TIM7_TIM7_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM7_TIM7_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM7_TIM7_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM7_TIM7_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM7_TIM7_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM7_TIM7_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM7_TIM7_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM7_TIM7_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM7_TIM7_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM7_TIM7_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM7_TIM7_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM7_TIM7_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM7_TIM7_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM7_TIM7_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM7_TIM7_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM7_TIM7_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM7_TIM7_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM7_TIM7_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM7_TIM7_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM7_TIM7_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM7_TIM7_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM7_TIM7_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM7_TIM7_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM7_TIM7_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM7_TIM7_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM7_TIM7_SMCR_TS4 = 0x200000

	// TIM7_DIER: TIM7 DMA/interrupt enable register
	// Position of UIE field.
	TIM7_TIM7_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM7_TIM7_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM7_TIM7_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM7_TIM7_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM7_TIM7_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM7_TIM7_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM7_TIM7_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM7_TIM7_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM7_TIM7_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM7_TIM7_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM7_TIM7_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM7_TIM7_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM7_TIM7_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM7_TIM7_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM7_TIM7_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM7_TIM7_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM7_TIM7_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM7_TIM7_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM7_TIM7_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM7_TIM7_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM7_TIM7_DIER_TIE = 0x40
	// Position of BIE field.
	TIM7_TIM7_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM7_TIM7_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM7_TIM7_DIER_BIE = 0x80
	// Position of UDE field.
	TIM7_TIM7_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM7_TIM7_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM7_TIM7_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM7_TIM7_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM7_TIM7_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM7_TIM7_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM7_TIM7_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM7_TIM7_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM7_TIM7_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM7_TIM7_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM7_TIM7_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM7_TIM7_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM7_TIM7_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM7_TIM7_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM7_TIM7_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM7_TIM7_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM7_TIM7_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM7_TIM7_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM7_TIM7_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM7_TIM7_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM7_TIM7_DIER_TDE = 0x4000

	// TIM7_SR: TIM7 status register
	// Position of UIF field.
	TIM7_TIM7_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM7_TIM7_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM7_TIM7_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM7_TIM7_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM7_TIM7_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM7_TIM7_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM7_TIM7_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM7_TIM7_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM7_TIM7_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM7_TIM7_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM7_TIM7_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM7_TIM7_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM7_TIM7_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM7_TIM7_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM7_TIM7_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM7_TIM7_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM7_TIM7_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM7_TIM7_SR_COMIF = 0x20
	// Position of TIF field.
	TIM7_TIM7_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM7_TIM7_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM7_TIM7_SR_TIF = 0x40
	// Position of BIF field.
	TIM7_TIM7_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM7_TIM7_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM7_TIM7_SR_BIF = 0x80
	// Position of B2IF field.
	TIM7_TIM7_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM7_TIM7_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM7_TIM7_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM7_TIM7_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM7_TIM7_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM7_TIM7_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM7_TIM7_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM7_TIM7_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM7_TIM7_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM7_TIM7_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM7_TIM7_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM7_TIM7_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM7_TIM7_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM7_TIM7_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM7_TIM7_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM7_TIM7_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM7_TIM7_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM7_TIM7_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM7_TIM7_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM7_TIM7_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM7_TIM7_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM7_TIM7_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM7_TIM7_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM7_TIM7_SR_CC6IF = 0x20000

	// TIM7_EGR: TIM7 event generation register
	// Position of UG field.
	TIM7_TIM7_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM7_TIM7_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM7_TIM7_EGR_UG = 0x1
	// Position of CC1G field.
	TIM7_TIM7_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM7_TIM7_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM7_TIM7_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM7_TIM7_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM7_TIM7_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM7_TIM7_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM7_TIM7_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM7_TIM7_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM7_TIM7_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM7_TIM7_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM7_TIM7_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM7_TIM7_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM7_TIM7_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM7_TIM7_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM7_TIM7_EGR_COMG = 0x20
	// Position of TG field.
	TIM7_TIM7_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM7_TIM7_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM7_TIM7_EGR_TG = 0x40
	// Position of BG field.
	TIM7_TIM7_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM7_TIM7_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM7_TIM7_EGR_BG = 0x80
	// Position of B2G field.
	TIM7_TIM7_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM7_TIM7_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM7_TIM7_EGR_B2G = 0x100

	// TIM7_CCMR1ALTERNATE7: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM7_TIM7_CCMR1ALTERNATE7_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM7_TIM7_CCMR1ALTERNATE7_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM7_TIM7_CCMR1ALTERNATE7_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM7_TIM7_CCMR1ALTERNATE7_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM7_TIM7_CCMR1ALTERNATE7_IC2F_Msk = 0xf000

	// TIM7_CCMR2ALTERNATE23: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM7_TIM7_CCMR2ALTERNATE23_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM7_TIM7_CCMR2ALTERNATE23_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM7_TIM7_CCMR2ALTERNATE23_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM7_TIM7_CCMR2ALTERNATE23_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM7_TIM7_CCMR2ALTERNATE23_IC4F_Msk = 0xf000

	// TIM7_CCER: TIM7 capture/compare enable register
	// Position of CC1E field.
	TIM7_TIM7_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM7_TIM7_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM7_TIM7_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM7_TIM7_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM7_TIM7_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM7_TIM7_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM7_TIM7_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM7_TIM7_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM7_TIM7_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM7_TIM7_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM7_TIM7_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM7_TIM7_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM7_TIM7_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM7_TIM7_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM7_TIM7_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM7_TIM7_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM7_TIM7_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM7_TIM7_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM7_TIM7_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM7_TIM7_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM7_TIM7_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM7_TIM7_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM7_TIM7_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM7_TIM7_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM7_TIM7_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM7_TIM7_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM7_TIM7_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM7_TIM7_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM7_TIM7_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM7_TIM7_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM7_TIM7_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM7_TIM7_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM7_TIM7_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM7_TIM7_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM7_TIM7_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM7_TIM7_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM7_TIM7_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM7_TIM7_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM7_TIM7_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM7_TIM7_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM7_TIM7_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM7_TIM7_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM7_TIM7_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM7_TIM7_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM7_TIM7_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM7_TIM7_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM7_TIM7_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM7_TIM7_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM7_TIM7_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM7_TIM7_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM7_TIM7_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM7_TIM7_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM7_TIM7_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM7_TIM7_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM7_TIM7_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM7_TIM7_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM7_TIM7_CCER_CC6P = 0x200000

	// TIM7_CNT: TIM7 counter
	// Position of CNT field.
	TIM7_TIM7_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM7_TIM7_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM7_TIM7_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM7_TIM7_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM7_TIM7_CNT_UIFCPY = 0x80000000

	// TIM7_PSC: TIM7 prescaler
	// Position of PSC field.
	TIM7_TIM7_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM7_TIM7_PSC_PSC_Msk = 0xffff

	// TIM7_ARR: TIM7 auto-reload register
	// Position of ARR field.
	TIM7_TIM7_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM7_TIM7_ARR_ARR_Msk = 0xffff

	// TIM7_RCR: TIM7 repetition counter register
	// Position of REP field.
	TIM7_TIM7_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM7_TIM7_RCR_REP_Msk = 0xffff

	// TIM7_CCR1: TIM7 capture/compare register 1
	// Position of CCR1 field.
	TIM7_TIM7_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM7_TIM7_CCR1_CCR1_Msk = 0xffff

	// TIM7_CCR2: TIM7 capture/compare register 2
	// Position of CCR2 field.
	TIM7_TIM7_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM7_TIM7_CCR2_CCR2_Msk = 0xffff

	// TIM7_CCR3: TIM7 capture/compare register 3
	// Position of CCR3 field.
	TIM7_TIM7_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM7_TIM7_CCR3_CCR3_Msk = 0xffff

	// TIM7_CCR4: TIM7 capture/compare register 4
	// Position of CCR4 field.
	TIM7_TIM7_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM7_TIM7_CCR4_CCR4_Msk = 0xffff

	// TIM7_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM7_TIM7_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM7_TIM7_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM7_TIM7_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM7_TIM7_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM7_TIM7_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM7_TIM7_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM7_TIM7_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM7_TIM7_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM7_TIM7_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM7_TIM7_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM7_TIM7_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM7_TIM7_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM7_TIM7_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM7_TIM7_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM7_TIM7_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM7_TIM7_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM7_TIM7_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM7_TIM7_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM7_TIM7_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM7_TIM7_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM7_TIM7_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM7_TIM7_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM7_TIM7_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM7_TIM7_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM7_TIM7_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM7_TIM7_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM7_TIM7_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM7_TIM7_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM7_TIM7_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM7_TIM7_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM7_TIM7_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM7_TIM7_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM7_TIM7_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM7_TIM7_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM7_TIM7_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM7_TIM7_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM7_TIM7_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM7_TIM7_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM7_TIM7_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM7_TIM7_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM7_TIM7_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM7_TIM7_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM7_TIM7_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM7_TIM7_BDTR_BK2BID = 0x20000000

	// TIM7_DCR: TIM7 DMA control register
	// Position of DBA field.
	TIM7_TIM7_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM7_TIM7_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM7_TIM7_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM7_TIM7_DCR_DBL_Msk = 0x1f00

	// TIM7_DMAR: TIM7 DMA address for full transfer
	// Position of DMAB field.
	TIM7_TIM7_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM7_TIM7_DMAR_DMAB_Msk = 0xffffffff

	// TIM7_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM7_TIM7_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM7_TIM7_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM7_TIM7_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM7_TIM7_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM7_TIM7_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM7_TIM7_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM7_TIM7_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM7_TIM7_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM7_TIM7_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM7_TIM7_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM7_TIM7_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM7_TIM7_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM7_TIM7_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM7_TIM7_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM7_TIM7_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM7_TIM7_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM7_TIM7_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM7_TIM7_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM7_TIM7_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM7_TIM7_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM7_TIM7_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM7_TIM7_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM7_TIM7_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM7_TIM7_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM7_TIM7_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM7_TIM7_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM7_TIM7_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM7_TIM7_CCMR3_OC6M3 = 0x1000000

	// TIM7_CCR5: TIM7 capture/compare register 5
	// Position of CCR5 field.
	TIM7_TIM7_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM7_TIM7_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM7_TIM7_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM7_TIM7_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM7_TIM7_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM7_TIM7_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM7_TIM7_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM7_TIM7_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM7_TIM7_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM7_TIM7_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM7_TIM7_CCR5_GC5C3 = 0x80000000

	// TIM7_CCR6: TIM7 capture/compare register 6
	// Position of CCR6 field.
	TIM7_TIM7_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM7_TIM7_CCR6_CCR6_Msk = 0xffff
)

// Bitfields for TIM8: TIM8
const (
	// TIM8_CR1: TIM8 control register 1
	// Position of CEN field.
	TIM8_TIM8_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM8_TIM8_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM8_TIM8_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM8_TIM8_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM8_TIM8_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM8_TIM8_CR1_UDIS = 0x2
	// Position of URS field.
	TIM8_TIM8_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM8_TIM8_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM8_TIM8_CR1_URS = 0x4
	// Position of OPM field.
	TIM8_TIM8_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM8_TIM8_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM8_TIM8_CR1_OPM = 0x8
	// Position of DIR field.
	TIM8_TIM8_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM8_TIM8_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM8_TIM8_CR1_DIR = 0x10
	// Position of CMS field.
	TIM8_TIM8_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM8_TIM8_CR1_CMS_Msk = 0x60
	// Position of ARPE field.
	TIM8_TIM8_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM8_TIM8_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM8_TIM8_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM8_TIM8_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM8_TIM8_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM8_TIM8_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM8_TIM8_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM8_TIM8_CR1_UIFREMAP = 0x800

	// TIM8_CR2: TIM8 control register 2
	// Position of CCPC field.
	TIM8_TIM8_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM8_TIM8_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM8_TIM8_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIM8_TIM8_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM8_TIM8_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM8_TIM8_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIM8_TIM8_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM8_TIM8_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM8_TIM8_CR2_CCDS = 0x8
	// Position of MMS field.
	TIM8_TIM8_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM8_TIM8_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM8_TIM8_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM8_TIM8_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM8_TIM8_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIM8_TIM8_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM8_TIM8_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM8_TIM8_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIM8_TIM8_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM8_TIM8_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM8_TIM8_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIM8_TIM8_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM8_TIM8_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM8_TIM8_CR2_OIS2 = 0x400
	// Position of OIS2N field.
	TIM8_TIM8_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM8_TIM8_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM8_TIM8_CR2_OIS2N = 0x800
	// Position of OIS3 field.
	TIM8_TIM8_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM8_TIM8_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM8_TIM8_CR2_OIS3 = 0x1000
	// Position of OIS3N field.
	TIM8_TIM8_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM8_TIM8_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM8_TIM8_CR2_OIS3N = 0x2000
	// Position of OIS4 field.
	TIM8_TIM8_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM8_TIM8_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM8_TIM8_CR2_OIS4 = 0x4000
	// Position of OIS5 field.
	TIM8_TIM8_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM8_TIM8_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM8_TIM8_CR2_OIS5 = 0x10000
	// Position of OIS6 field.
	TIM8_TIM8_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM8_TIM8_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM8_TIM8_CR2_OIS6 = 0x40000
	// Position of MMS2 field.
	TIM8_TIM8_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM8_TIM8_CR2_MMS2_Msk = 0xf00000

	// TIM8_SMCR: TIM8 slave mode control register
	// Position of SMS field.
	TIM8_TIM8_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM8_TIM8_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM8_TIM8_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM8_TIM8_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM8_TIM8_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM8_TIM8_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM8_TIM8_SMCR_MSM = 0x80
	// Position of ETF field.
	TIM8_TIM8_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM8_TIM8_SMCR_ETF_Msk = 0xf00
	// Position of ETPS field.
	TIM8_TIM8_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM8_TIM8_SMCR_ETPS_Msk = 0x3000
	// Position of ECE field.
	TIM8_TIM8_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM8_TIM8_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM8_TIM8_SMCR_ECE = 0x4000
	// Position of ETP field.
	TIM8_TIM8_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM8_TIM8_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM8_TIM8_SMCR_ETP = 0x8000
	// Position of SMS3 field.
	TIM8_TIM8_SMCR_SMS3_Pos = 0x10
	// Bit mask of SMS3 field.
	TIM8_TIM8_SMCR_SMS3_Msk = 0x10000
	// Bit SMS3.
	TIM8_TIM8_SMCR_SMS3 = 0x10000
	// Position of TS3 field.
	TIM8_TIM8_SMCR_TS3_Pos = 0x14
	// Bit mask of TS3 field.
	TIM8_TIM8_SMCR_TS3_Msk = 0x100000
	// Bit TS3.
	TIM8_TIM8_SMCR_TS3 = 0x100000
	// Position of TS4 field.
	TIM8_TIM8_SMCR_TS4_Pos = 0x15
	// Bit mask of TS4 field.
	TIM8_TIM8_SMCR_TS4_Msk = 0x200000
	// Bit TS4.
	TIM8_TIM8_SMCR_TS4 = 0x200000

	// TIM8_DIER: TIM8 DMA/interrupt enable register
	// Position of UIE field.
	TIM8_TIM8_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM8_TIM8_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM8_TIM8_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM8_TIM8_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM8_TIM8_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM8_TIM8_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM8_TIM8_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM8_TIM8_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM8_TIM8_DIER_CC2IE = 0x4
	// Position of CC3IE field.
	TIM8_TIM8_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM8_TIM8_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM8_TIM8_DIER_CC3IE = 0x8
	// Position of CC4IE field.
	TIM8_TIM8_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM8_TIM8_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM8_TIM8_DIER_CC4IE = 0x10
	// Position of COMIE field.
	TIM8_TIM8_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM8_TIM8_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM8_TIM8_DIER_COMIE = 0x20
	// Position of TIE field.
	TIM8_TIM8_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM8_TIM8_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM8_TIM8_DIER_TIE = 0x40
	// Position of BIE field.
	TIM8_TIM8_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM8_TIM8_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM8_TIM8_DIER_BIE = 0x80
	// Position of UDE field.
	TIM8_TIM8_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM8_TIM8_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM8_TIM8_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIM8_TIM8_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM8_TIM8_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM8_TIM8_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIM8_TIM8_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM8_TIM8_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM8_TIM8_DIER_CC2DE = 0x400
	// Position of CC3DE field.
	TIM8_TIM8_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM8_TIM8_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM8_TIM8_DIER_CC3DE = 0x800
	// Position of CC4DE field.
	TIM8_TIM8_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM8_TIM8_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM8_TIM8_DIER_CC4DE = 0x1000
	// Position of COMDE field.
	TIM8_TIM8_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM8_TIM8_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM8_TIM8_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIM8_TIM8_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM8_TIM8_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM8_TIM8_DIER_TDE = 0x4000

	// TIM8_SR: TIM8 status register
	// Position of UIF field.
	TIM8_TIM8_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM8_TIM8_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM8_TIM8_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM8_TIM8_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM8_TIM8_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM8_TIM8_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM8_TIM8_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM8_TIM8_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM8_TIM8_SR_CC2IF = 0x4
	// Position of CC3IF field.
	TIM8_TIM8_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM8_TIM8_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM8_TIM8_SR_CC3IF = 0x8
	// Position of CC4IF field.
	TIM8_TIM8_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM8_TIM8_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM8_TIM8_SR_CC4IF = 0x10
	// Position of COMIF field.
	TIM8_TIM8_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM8_TIM8_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM8_TIM8_SR_COMIF = 0x20
	// Position of TIF field.
	TIM8_TIM8_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM8_TIM8_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM8_TIM8_SR_TIF = 0x40
	// Position of BIF field.
	TIM8_TIM8_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM8_TIM8_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM8_TIM8_SR_BIF = 0x80
	// Position of B2IF field.
	TIM8_TIM8_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM8_TIM8_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM8_TIM8_SR_B2IF = 0x100
	// Position of CC1OF field.
	TIM8_TIM8_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM8_TIM8_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM8_TIM8_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM8_TIM8_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM8_TIM8_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM8_TIM8_SR_CC2OF = 0x400
	// Position of CC3OF field.
	TIM8_TIM8_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM8_TIM8_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM8_TIM8_SR_CC3OF = 0x800
	// Position of CC4OF field.
	TIM8_TIM8_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM8_TIM8_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM8_TIM8_SR_CC4OF = 0x1000
	// Position of SBIF field.
	TIM8_TIM8_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM8_TIM8_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM8_TIM8_SR_SBIF = 0x2000
	// Position of CC5IF field.
	TIM8_TIM8_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM8_TIM8_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM8_TIM8_SR_CC5IF = 0x10000
	// Position of CC6IF field.
	TIM8_TIM8_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM8_TIM8_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM8_TIM8_SR_CC6IF = 0x20000

	// TIM8_EGR: TIM8 event generation register
	// Position of UG field.
	TIM8_TIM8_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM8_TIM8_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM8_TIM8_EGR_UG = 0x1
	// Position of CC1G field.
	TIM8_TIM8_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM8_TIM8_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM8_TIM8_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM8_TIM8_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM8_TIM8_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM8_TIM8_EGR_CC2G = 0x4
	// Position of CC3G field.
	TIM8_TIM8_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM8_TIM8_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM8_TIM8_EGR_CC3G = 0x8
	// Position of CC4G field.
	TIM8_TIM8_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM8_TIM8_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM8_TIM8_EGR_CC4G = 0x10
	// Position of COMG field.
	TIM8_TIM8_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM8_TIM8_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM8_TIM8_EGR_COMG = 0x20
	// Position of TG field.
	TIM8_TIM8_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM8_TIM8_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM8_TIM8_EGR_TG = 0x40
	// Position of BG field.
	TIM8_TIM8_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM8_TIM8_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM8_TIM8_EGR_BG = 0x80
	// Position of B2G field.
	TIM8_TIM8_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM8_TIM8_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM8_TIM8_EGR_B2G = 0x100

	// TIM8_CCMR1ALTERNATE8: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC1S field.
	TIM8_TIM8_CCMR1ALTERNATE8_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM8_TIM8_CCMR1ALTERNATE8_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM8_TIM8_CCMR1ALTERNATE8_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM8_TIM8_CCMR1ALTERNATE8_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM8_TIM8_CCMR1ALTERNATE8_IC2F_Msk = 0xf000

	// TIM8_CCMR2ALTERNATE24: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
	// Position of CC3S field.
	TIM8_TIM8_CCMR2ALTERNATE24_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM8_TIM8_CCMR2ALTERNATE24_CC3S_Msk = 0x3
	// Position of IC3PSC field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC3PSC_Msk = 0xc
	// Position of IC3F field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC3F_Msk = 0xf0
	// Position of CC4S field.
	TIM8_TIM8_CCMR2ALTERNATE24_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM8_TIM8_CCMR2ALTERNATE24_CC4S_Msk = 0x300
	// Position of IC4PSC field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC4PSC_Msk = 0xc00
	// Position of IC4F field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM8_TIM8_CCMR2ALTERNATE24_IC4F_Msk = 0xf000

	// TIM8_CCER: TIM8 capture/compare enable register
	// Position of CC1E field.
	TIM8_TIM8_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM8_TIM8_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM8_TIM8_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM8_TIM8_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM8_TIM8_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM8_TIM8_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM8_TIM8_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM8_TIM8_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM8_TIM8_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM8_TIM8_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM8_TIM8_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM8_TIM8_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM8_TIM8_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM8_TIM8_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM8_TIM8_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM8_TIM8_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM8_TIM8_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM8_TIM8_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM8_TIM8_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM8_TIM8_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM8_TIM8_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM8_TIM8_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM8_TIM8_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM8_TIM8_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM8_TIM8_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM8_TIM8_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM8_TIM8_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM8_TIM8_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM8_TIM8_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM8_TIM8_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM8_TIM8_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM8_TIM8_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM8_TIM8_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM8_TIM8_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM8_TIM8_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM8_TIM8_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM8_TIM8_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM8_TIM8_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM8_TIM8_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM8_TIM8_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM8_TIM8_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM8_TIM8_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM8_TIM8_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM8_TIM8_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM8_TIM8_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM8_TIM8_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM8_TIM8_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM8_TIM8_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM8_TIM8_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM8_TIM8_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM8_TIM8_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM8_TIM8_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM8_TIM8_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM8_TIM8_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM8_TIM8_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM8_TIM8_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM8_TIM8_CCER_CC6P = 0x200000

	// TIM8_CNT: TIM8 counter
	// Position of CNT field.
	TIM8_TIM8_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM8_TIM8_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM8_TIM8_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM8_TIM8_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM8_TIM8_CNT_UIFCPY = 0x80000000

	// TIM8_PSC: TIM8 prescaler
	// Position of PSC field.
	TIM8_TIM8_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM8_TIM8_PSC_PSC_Msk = 0xffff

	// TIM8_ARR: TIM8 auto-reload register
	// Position of ARR field.
	TIM8_TIM8_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM8_TIM8_ARR_ARR_Msk = 0xffff

	// TIM8_RCR: TIM8 repetition counter register
	// Position of REP field.
	TIM8_TIM8_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM8_TIM8_RCR_REP_Msk = 0xffff

	// TIM8_CCR1: TIM8 capture/compare register 1
	// Position of CCR1 field.
	TIM8_TIM8_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM8_TIM8_CCR1_CCR1_Msk = 0xffff

	// TIM8_CCR2: TIM8 capture/compare register 2
	// Position of CCR2 field.
	TIM8_TIM8_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM8_TIM8_CCR2_CCR2_Msk = 0xffff

	// TIM8_CCR3: TIM8 capture/compare register 3
	// Position of CCR3 field.
	TIM8_TIM8_CCR3_CCR3_Pos = 0x0
	// Bit mask of CCR3 field.
	TIM8_TIM8_CCR3_CCR3_Msk = 0xffff

	// TIM8_CCR4: TIM8 capture/compare register 4
	// Position of CCR4 field.
	TIM8_TIM8_CCR4_CCR4_Pos = 0x0
	// Bit mask of CCR4 field.
	TIM8_TIM8_CCR4_CCR4_Msk = 0xffff

	// TIM8_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIM8_TIM8_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM8_TIM8_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM8_TIM8_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM8_TIM8_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM8_TIM8_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM8_TIM8_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM8_TIM8_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIM8_TIM8_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM8_TIM8_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM8_TIM8_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIM8_TIM8_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM8_TIM8_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM8_TIM8_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM8_TIM8_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM8_TIM8_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM8_TIM8_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM8_TIM8_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM8_TIM8_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM8_TIM8_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM8_TIM8_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM8_TIM8_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM8_TIM8_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIM8_TIM8_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM8_TIM8_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM8_TIM8_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM8_TIM8_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM8_TIM8_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM8_TIM8_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM8_TIM8_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM8_TIM8_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM8_TIM8_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM8_TIM8_BDTR_BK2P = 0x2000000
	// Position of BKDSRM field.
	TIM8_TIM8_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM8_TIM8_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM8_TIM8_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM8_TIM8_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM8_TIM8_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM8_TIM8_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM8_TIM8_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM8_TIM8_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM8_TIM8_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM8_TIM8_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM8_TIM8_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM8_TIM8_BDTR_BK2BID = 0x20000000

	// TIM8_DCR: TIM8 DMA control register
	// Position of DBA field.
	TIM8_TIM8_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM8_TIM8_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM8_TIM8_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM8_TIM8_DCR_DBL_Msk = 0x1f00

	// TIM8_DMAR: TIM8 DMA address for full transfer
	// Position of DMAB field.
	TIM8_TIM8_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM8_TIM8_DMAR_DMAB_Msk = 0xffffffff

	// TIM8_CCMR3: The channels 5 and 6 can only be configured in output. Output compare mode:
	// Position of OC5FE field.
	TIM8_TIM8_CCMR3_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM8_TIM8_CCMR3_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM8_TIM8_CCMR3_OC5FE = 0x4
	// Position of OC5PE field.
	TIM8_TIM8_CCMR3_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM8_TIM8_CCMR3_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM8_TIM8_CCMR3_OC5PE = 0x8
	// Position of OC5M field.
	TIM8_TIM8_CCMR3_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM8_TIM8_CCMR3_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM8_TIM8_CCMR3_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM8_TIM8_CCMR3_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM8_TIM8_CCMR3_OC5CE = 0x80
	// Position of OC6FE field.
	TIM8_TIM8_CCMR3_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM8_TIM8_CCMR3_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM8_TIM8_CCMR3_OC6FE = 0x400
	// Position of OC6PE field.
	TIM8_TIM8_CCMR3_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM8_TIM8_CCMR3_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM8_TIM8_CCMR3_OC6PE = 0x800
	// Position of OC6M field.
	TIM8_TIM8_CCMR3_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM8_TIM8_CCMR3_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM8_TIM8_CCMR3_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM8_TIM8_CCMR3_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM8_TIM8_CCMR3_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM8_TIM8_CCMR3_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM8_TIM8_CCMR3_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM8_TIM8_CCMR3_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM8_TIM8_CCMR3_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM8_TIM8_CCMR3_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM8_TIM8_CCMR3_OC6M3 = 0x1000000

	// TIM8_CCR5: TIM8 capture/compare register 5
	// Position of CCR5 field.
	TIM8_TIM8_CCR5_CCR5_Pos = 0x0
	// Bit mask of CCR5 field.
	TIM8_TIM8_CCR5_CCR5_Msk = 0xffff
	// Position of GC5C1 field.
	TIM8_TIM8_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM8_TIM8_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM8_TIM8_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM8_TIM8_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM8_TIM8_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM8_TIM8_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM8_TIM8_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM8_TIM8_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM8_TIM8_CCR5_GC5C3 = 0x80000000

	// TIM8_CCR6: TIM8 capture/compare register 6
	// Position of CCR6 field.
	TIM8_TIM8_CCR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM8_TIM8_CCR6_CCR6_Msk = 0xffff

	// TIM8_AF1: TIM8 Alternate function option register 1
	// Position of BKINE field.
	TIM8_TIM8_AF1_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIM8_TIM8_AF1_BKINE_Msk = 0x1
	// Bit BKINE.
	TIM8_TIM8_AF1_BKINE = 0x1
	// Position of BKDF1BK2E field.
	TIM8_TIM8_AF1_BKDF1BK2E_Pos = 0x8
	// Bit mask of BKDF1BK2E field.
	TIM8_TIM8_AF1_BKDF1BK2E_Msk = 0x100
	// Bit BKDF1BK2E.
	TIM8_TIM8_AF1_BKDF1BK2E = 0x100
	// Position of BKINP field.
	TIM8_TIM8_AF1_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIM8_TIM8_AF1_BKINP_Msk = 0x200
	// Bit BKINP.
	TIM8_TIM8_AF1_BKINP = 0x200
	// Position of ETRSEL field.
	TIM8_TIM8_AF1_ETRSEL_Pos = 0xe
	// Bit mask of ETRSEL field.
	TIM8_TIM8_AF1_ETRSEL_Msk = 0x3c000

	// TIM8_AF2: TIM8 Alternate function option register 2
	// Position of BK2INE field.
	TIM8_TIM8_AF2_BK2INE_Pos = 0x0
	// Bit mask of BK2INE field.
	TIM8_TIM8_AF2_BK2INE_Msk = 0x1
	// Bit BK2INE.
	TIM8_TIM8_AF2_BK2INE = 0x1
	// Position of BK2DF1BK3E field.
	TIM8_TIM8_AF2_BK2DF1BK3E_Pos = 0x8
	// Bit mask of BK2DF1BK3E field.
	TIM8_TIM8_AF2_BK2DF1BK3E_Msk = 0x100
	// Bit BK2DF1BK3E.
	TIM8_TIM8_AF2_BK2DF1BK3E = 0x100
	// Position of BK2INP field.
	TIM8_TIM8_AF2_BK2INP_Pos = 0x9
	// Bit mask of BK2INP field.
	TIM8_TIM8_AF2_BK2INP_Msk = 0x200
	// Bit BK2INP.
	TIM8_TIM8_AF2_BK2INP = 0x200

	// TIM8_TISEL: TIM8 timer input selection register
	// Position of TI1SEL field.
	TIM8_TIM8_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM8_TIM8_TISEL_TI1SEL_Msk = 0xf
	// Position of TI2SEL field.
	TIM8_TIM8_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIM8_TIM8_TISEL_TI2SEL_Msk = 0xf00
	// Position of TI3SEL field.
	TIM8_TIM8_TISEL_TI3SEL_Pos = 0x10
	// Bit mask of TI3SEL field.
	TIM8_TIM8_TISEL_TI3SEL_Msk = 0xf0000
	// Position of TI4SEL field.
	TIM8_TIM8_TISEL_TI4SEL_Pos = 0x18
	// Bit mask of TI4SEL field.
	TIM8_TIM8_TISEL_TI4SEL_Msk = 0xf000000
)

// Bitfields for TIM12: TIM12
const (
	// TIM12_CR1: TIM12 control register 1
	// Position of CEN field.
	TIM12_TIM12_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM12_TIM12_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM12_TIM12_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM12_TIM12_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM12_TIM12_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM12_TIM12_CR1_UDIS = 0x2
	// Position of URS field.
	TIM12_TIM12_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM12_TIM12_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM12_TIM12_CR1_URS = 0x4
	// Position of OPM field.
	TIM12_TIM12_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM12_TIM12_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM12_TIM12_CR1_OPM = 0x8
	// Position of ARPE field.
	TIM12_TIM12_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM12_TIM12_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM12_TIM12_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM12_TIM12_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM12_TIM12_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM12_TIM12_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM12_TIM12_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM12_TIM12_CR1_UIFREMAP = 0x800

	// TIM12_CR2: TIM12 control register 2
	// Position of MMS field.
	TIM12_TIM12_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM12_TIM12_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM12_TIM12_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM12_TIM12_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM12_TIM12_CR2_TI1S = 0x80

	// TIM12_SMCR: TIM12 slave mode control register
	// Position of SMS field.
	TIM12_TIM12_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM12_TIM12_SMCR_SMS_Msk = 0x7
	// Position of TS field.
	TIM12_TIM12_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM12_TIM12_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM12_TIM12_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM12_TIM12_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM12_TIM12_SMCR_MSM = 0x80
	// Position of SMS_3 field.
	TIM12_TIM12_SMCR_SMS_3_Pos = 0x10
	// Bit mask of SMS_3 field.
	TIM12_TIM12_SMCR_SMS_3_Msk = 0x10000
	// Bit SMS_3.
	TIM12_TIM12_SMCR_SMS_3 = 0x10000
	// Position of TS_3 field.
	TIM12_TIM12_SMCR_TS_3_Pos = 0x14
	// Bit mask of TS_3 field.
	TIM12_TIM12_SMCR_TS_3_Msk = 0x100000
	// Bit TS_3.
	TIM12_TIM12_SMCR_TS_3 = 0x100000
	// Position of TS_4 field.
	TIM12_TIM12_SMCR_TS_4_Pos = 0x15
	// Bit mask of TS_4 field.
	TIM12_TIM12_SMCR_TS_4_Msk = 0x200000
	// Bit TS_4.
	TIM12_TIM12_SMCR_TS_4 = 0x200000

	// TIM12_DIER: TIM12 interrupt enable register
	// Position of UIE field.
	TIM12_TIM12_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM12_TIM12_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM12_TIM12_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM12_TIM12_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM12_TIM12_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM12_TIM12_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIM12_TIM12_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM12_TIM12_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM12_TIM12_DIER_CC2IE = 0x4
	// Position of TIE field.
	TIM12_TIM12_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM12_TIM12_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM12_TIM12_DIER_TIE = 0x40

	// TIM12_SR: TIM12 status register
	// Position of UIF field.
	TIM12_TIM12_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM12_TIM12_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM12_TIM12_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM12_TIM12_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM12_TIM12_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM12_TIM12_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIM12_TIM12_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM12_TIM12_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM12_TIM12_SR_CC2IF = 0x4
	// Position of TIF field.
	TIM12_TIM12_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM12_TIM12_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM12_TIM12_SR_TIF = 0x40
	// Position of CC1OF field.
	TIM12_TIM12_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM12_TIM12_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM12_TIM12_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIM12_TIM12_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM12_TIM12_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM12_TIM12_SR_CC2OF = 0x400

	// TIM12_EGR: TIM12 event generation register
	// Position of UG field.
	TIM12_TIM12_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM12_TIM12_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM12_TIM12_EGR_UG = 0x1
	// Position of CC1G field.
	TIM12_TIM12_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM12_TIM12_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM12_TIM12_EGR_CC1G = 0x2
	// Position of CC2G field.
	TIM12_TIM12_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM12_TIM12_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM12_TIM12_EGR_CC2G = 0x4
	// Position of TG field.
	TIM12_TIM12_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM12_TIM12_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM12_TIM12_EGR_TG = 0x40

	// TIM12_CCMR1_input: TIM12 capture/compare mode register 1
	// Position of CC1S field.
	TIM12_TIM12_CCMR1_input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM12_TIM12_CCMR1_input_CC1S_Msk = 0x3
	// Position of IC1PSC field.
	TIM12_TIM12_CCMR1_input_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM12_TIM12_CCMR1_input_IC1PSC_Msk = 0xc
	// Position of IC1F field.
	TIM12_TIM12_CCMR1_input_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM12_TIM12_CCMR1_input_IC1F_Msk = 0xf0
	// Position of CC2S field.
	TIM12_TIM12_CCMR1_input_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM12_TIM12_CCMR1_input_CC2S_Msk = 0x300
	// Position of IC2PSC field.
	TIM12_TIM12_CCMR1_input_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM12_TIM12_CCMR1_input_IC2PSC_Msk = 0xc00
	// Position of IC2F field.
	TIM12_TIM12_CCMR1_input_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM12_TIM12_CCMR1_input_IC2F_Msk = 0xf000

	// TIM12_CCMR1_output: TIM12 capture/compare mode register 1
	// Position of CC1S field.
	TIM12_TIM12_CCMR1_output_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM12_TIM12_CCMR1_output_CC1S_Msk = 0x3
	// Position of OC1FE field.
	TIM12_TIM12_CCMR1_output_OC1FE_Pos = 0x2
	// Bit mask of OC1FE field.
	TIM12_TIM12_CCMR1_output_OC1FE_Msk = 0x4
	// Bit OC1FE.
	TIM12_TIM12_CCMR1_output_OC1FE = 0x4
	// Position of OC1PE field.
	TIM12_TIM12_CCMR1_output_OC1PE_Pos = 0x3
	// Bit mask of OC1PE field.
	TIM12_TIM12_CCMR1_output_OC1PE_Msk = 0x8
	// Bit OC1PE.
	TIM12_TIM12_CCMR1_output_OC1PE = 0x8
	// Position of OC1M field.
	TIM12_TIM12_CCMR1_output_OC1M_Pos = 0x4
	// Bit mask of OC1M field.
	TIM12_TIM12_CCMR1_output_OC1M_Msk = 0x70
	// Position of CC2S field.
	TIM12_TIM12_CCMR1_output_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM12_TIM12_CCMR1_output_CC2S_Msk = 0x300
	// Position of OC2FE field.
	TIM12_TIM12_CCMR1_output_OC2FE_Pos = 0xa
	// Bit mask of OC2FE field.
	TIM12_TIM12_CCMR1_output_OC2FE_Msk = 0x400
	// Bit OC2FE.
	TIM12_TIM12_CCMR1_output_OC2FE = 0x400
	// Position of OC2PE field.
	TIM12_TIM12_CCMR1_output_OC2PE_Pos = 0xb
	// Bit mask of OC2PE field.
	TIM12_TIM12_CCMR1_output_OC2PE_Msk = 0x800
	// Bit OC2PE.
	TIM12_TIM12_CCMR1_output_OC2PE = 0x800
	// Position of OC2M field.
	TIM12_TIM12_CCMR1_output_OC2M_Pos = 0xc
	// Bit mask of OC2M field.
	TIM12_TIM12_CCMR1_output_OC2M_Msk = 0x7000
	// Position of OC1M_3 field.
	TIM12_TIM12_CCMR1_output_OC1M_3_Pos = 0x10
	// Bit mask of OC1M_3 field.
	TIM12_TIM12_CCMR1_output_OC1M_3_Msk = 0x10000
	// Bit OC1M_3.
	TIM12_TIM12_CCMR1_output_OC1M_3 = 0x10000
	// Position of OC2M_3 field.
	TIM12_TIM12_CCMR1_output_OC2M_3_Pos = 0x18
	// Bit mask of OC2M_3 field.
	TIM12_TIM12_CCMR1_output_OC2M_3_Msk = 0x1000000
	// Bit OC2M_3.
	TIM12_TIM12_CCMR1_output_OC2M_3 = 0x1000000

	// TIM12_CCER: TIM12 capture/compare enable register
	// Position of CC1E field.
	TIM12_TIM12_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM12_TIM12_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM12_TIM12_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM12_TIM12_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM12_TIM12_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM12_TIM12_CCER_CC1P = 0x2
	// Position of CC1NP field.
	TIM12_TIM12_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM12_TIM12_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM12_TIM12_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM12_TIM12_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM12_TIM12_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM12_TIM12_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM12_TIM12_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM12_TIM12_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM12_TIM12_CCER_CC2P = 0x20
	// Position of CC2NP field.
	TIM12_TIM12_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM12_TIM12_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM12_TIM12_CCER_CC2NP = 0x80

	// TIM12_CNT: TIM12 counter
	// Position of CNT field.
	TIM12_TIM12_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM12_TIM12_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM12_TIM12_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM12_TIM12_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM12_TIM12_CNT_UIFCPY = 0x80000000

	// TIM12_PSC: TIM12 prescaler
	// Position of PSC field.
	TIM12_TIM12_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM12_TIM12_PSC_PSC_Msk = 0xffff

	// TIM12_ARR: TIM12 auto-reload register
	// Position of ARR field.
	TIM12_TIM12_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM12_TIM12_ARR_ARR_Msk = 0xffff

	// TIM12_CCR1: TIM12 capture/compare register 1
	// Position of CCR1 field.
	TIM12_TIM12_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM12_TIM12_CCR1_CCR1_Msk = 0xffff

	// TIM12_CCR2: TIM12 capture/compare register 2
	// Position of CCR2 field.
	TIM12_TIM12_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIM12_TIM12_CCR2_CCR2_Msk = 0xffff

	// TIM12_TISEL: TIM12 timer input selection register
	// Position of TI1SEL field.
	TIM12_TIM12_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM12_TIM12_TISEL_TI1SEL_Msk = 0xf
	// Position of TI2SEL field.
	TIM12_TIM12_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIM12_TIM12_TISEL_TI2SEL_Msk = 0xf00
)

// Bitfields for TIM13: TIM13
const (
	// TIM13_CR1: TIM13 control register 1
	// Position of CEN field.
	TIM13_TIM13_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM13_TIM13_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM13_TIM13_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM13_TIM13_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM13_TIM13_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM13_TIM13_CR1_UDIS = 0x2
	// Position of URS field.
	TIM13_TIM13_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM13_TIM13_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM13_TIM13_CR1_URS = 0x4
	// Position of OPM field.
	TIM13_TIM13_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM13_TIM13_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM13_TIM13_CR1_OPM = 0x8
	// Position of ARPE field.
	TIM13_TIM13_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM13_TIM13_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM13_TIM13_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM13_TIM13_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM13_TIM13_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM13_TIM13_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM13_TIM13_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM13_TIM13_CR1_UIFREMAP = 0x800

	// TIM13_DIER: TIM13 Interrupt enable register
	// Position of UIE field.
	TIM13_TIM13_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM13_TIM13_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM13_TIM13_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM13_TIM13_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM13_TIM13_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM13_TIM13_DIER_CC1IE = 0x2

	// TIM13_SR: TIM13 status register
	// Position of UIF field.
	TIM13_TIM13_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM13_TIM13_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM13_TIM13_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM13_TIM13_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM13_TIM13_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM13_TIM13_SR_CC1IF = 0x2
	// Position of CC1OF field.
	TIM13_TIM13_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM13_TIM13_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM13_TIM13_SR_CC1OF = 0x200

	// TIM13_EGR: TIM13 event generation register
	// Position of UG field.
	TIM13_TIM13_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM13_TIM13_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM13_TIM13_EGR_UG = 0x1
	// Position of CC1G field.
	TIM13_TIM13_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM13_TIM13_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM13_TIM13_EGR_CC1G = 0x2

	// TIM13_CCMR1: The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
	// Position of CC1S field.
	TIM13_TIM13_CCMR1_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM13_TIM13_CCMR1_CC1S_Msk = 0x3
	// Position of OC1FE field.
	TIM13_TIM13_CCMR1_OC1FE_Pos = 0x2
	// Bit mask of OC1FE field.
	TIM13_TIM13_CCMR1_OC1FE_Msk = 0x4
	// Bit OC1FE.
	TIM13_TIM13_CCMR1_OC1FE = 0x4
	// Position of OC1PE field.
	TIM13_TIM13_CCMR1_OC1PE_Pos = 0x3
	// Bit mask of OC1PE field.
	TIM13_TIM13_CCMR1_OC1PE_Msk = 0x8
	// Bit OC1PE.
	TIM13_TIM13_CCMR1_OC1PE = 0x8
	// Position of OC1M field.
	TIM13_TIM13_CCMR1_OC1M_Pos = 0x4
	// Bit mask of OC1M field.
	TIM13_TIM13_CCMR1_OC1M_Msk = 0x70
	// Position of OC1M3 field.
	TIM13_TIM13_CCMR1_OC1M3_Pos = 0x10
	// Bit mask of OC1M3 field.
	TIM13_TIM13_CCMR1_OC1M3_Msk = 0x10000
	// Bit OC1M3.
	TIM13_TIM13_CCMR1_OC1M3 = 0x10000

	// TIM13_CCER: TIM13 capture/compare enable register
	// Position of CC1E field.
	TIM13_TIM13_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM13_TIM13_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM13_TIM13_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM13_TIM13_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM13_TIM13_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM13_TIM13_CCER_CC1P = 0x2
	// Position of CC1NP field.
	TIM13_TIM13_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM13_TIM13_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM13_TIM13_CCER_CC1NP = 0x8

	// TIM13_CNT: TIM13 counter
	// Position of CNT field.
	TIM13_TIM13_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM13_TIM13_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM13_TIM13_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM13_TIM13_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM13_TIM13_CNT_UIFCPY = 0x80000000

	// TIM13_PSC: TIM13 prescaler
	// Position of PSC field.
	TIM13_TIM13_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM13_TIM13_PSC_PSC_Msk = 0xffff

	// TIM13_ARR: TIM13 auto-reload register
	// Position of ARR field.
	TIM13_TIM13_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM13_TIM13_ARR_ARR_Msk = 0xffff

	// TIM13_CCR1: TIM13 capture/compare register 1
	// Position of CCR1 field.
	TIM13_TIM13_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM13_TIM13_CCR1_CCR1_Msk = 0xffff

	// TIM13_TISEL: TIM13 timer input selection register
	// Position of TI1SEL field.
	TIM13_TIM13_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM13_TIM13_TISEL_TI1SEL_Msk = 0xf
)

// Bitfields for TIM14: TIM14
const (
	// TIM14_CR1: TIM14 control register 1
	// Position of CEN field.
	TIM14_TIM14_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM14_TIM14_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM14_TIM14_CR1_CEN = 0x1
	// Position of UDIS field.
	TIM14_TIM14_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM14_TIM14_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM14_TIM14_CR1_UDIS = 0x2
	// Position of URS field.
	TIM14_TIM14_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM14_TIM14_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM14_TIM14_CR1_URS = 0x4
	// Position of OPM field.
	TIM14_TIM14_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM14_TIM14_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM14_TIM14_CR1_OPM = 0x8
	// Position of ARPE field.
	TIM14_TIM14_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM14_TIM14_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM14_TIM14_CR1_ARPE = 0x80
	// Position of CKD field.
	TIM14_TIM14_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM14_TIM14_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIM14_TIM14_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM14_TIM14_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM14_TIM14_CR1_UIFREMAP = 0x800

	// TIM14_DIER: TIM14 Interrupt enable register
	// Position of UIE field.
	TIM14_TIM14_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM14_TIM14_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM14_TIM14_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIM14_TIM14_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM14_TIM14_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM14_TIM14_DIER_CC1IE = 0x2

	// TIM14_SR: TIM14 status register
	// Position of UIF field.
	TIM14_TIM14_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM14_TIM14_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM14_TIM14_SR_UIF = 0x1
	// Position of CC1IF field.
	TIM14_TIM14_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM14_TIM14_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM14_TIM14_SR_CC1IF = 0x2
	// Position of CC1OF field.
	TIM14_TIM14_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM14_TIM14_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM14_TIM14_SR_CC1OF = 0x200

	// TIM14_EGR: TIM14 event generation register
	// Position of UG field.
	TIM14_TIM14_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM14_TIM14_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM14_TIM14_EGR_UG = 0x1
	// Position of CC1G field.
	TIM14_TIM14_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM14_TIM14_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM14_TIM14_EGR_CC1G = 0x2

	// TIM14_CCMR1: The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
	// Position of CC1S field.
	TIM14_TIM14_CCMR1_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM14_TIM14_CCMR1_CC1S_Msk = 0x3
	// Position of OC1FE field.
	TIM14_TIM14_CCMR1_OC1FE_Pos = 0x2
	// Bit mask of OC1FE field.
	TIM14_TIM14_CCMR1_OC1FE_Msk = 0x4
	// Bit OC1FE.
	TIM14_TIM14_CCMR1_OC1FE = 0x4
	// Position of OC1PE field.
	TIM14_TIM14_CCMR1_OC1PE_Pos = 0x3
	// Bit mask of OC1PE field.
	TIM14_TIM14_CCMR1_OC1PE_Msk = 0x8
	// Bit OC1PE.
	TIM14_TIM14_CCMR1_OC1PE = 0x8
	// Position of OC1M field.
	TIM14_TIM14_CCMR1_OC1M_Pos = 0x4
	// Bit mask of OC1M field.
	TIM14_TIM14_CCMR1_OC1M_Msk = 0x70
	// Position of OC1M3 field.
	TIM14_TIM14_CCMR1_OC1M3_Pos = 0x10
	// Bit mask of OC1M3 field.
	TIM14_TIM14_CCMR1_OC1M3_Msk = 0x10000
	// Bit OC1M3.
	TIM14_TIM14_CCMR1_OC1M3 = 0x10000

	// TIM14_CCER: TIM14 capture/compare enable register
	// Position of CC1E field.
	TIM14_TIM14_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM14_TIM14_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM14_TIM14_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM14_TIM14_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM14_TIM14_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM14_TIM14_CCER_CC1P = 0x2
	// Position of CC1NP field.
	TIM14_TIM14_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM14_TIM14_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM14_TIM14_CCER_CC1NP = 0x8

	// TIM14_CNT: TIM14 counter
	// Position of CNT field.
	TIM14_TIM14_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM14_TIM14_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM14_TIM14_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM14_TIM14_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM14_TIM14_CNT_UIFCPY = 0x80000000

	// TIM14_PSC: TIM14 prescaler
	// Position of PSC field.
	TIM14_TIM14_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM14_TIM14_PSC_PSC_Msk = 0xffff

	// TIM14_ARR: TIM14 auto-reload register
	// Position of ARR field.
	TIM14_TIM14_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM14_TIM14_ARR_ARR_Msk = 0xffff

	// TIM14_CCR1: TIM14 capture/compare register 1
	// Position of CCR1 field.
	TIM14_TIM14_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIM14_TIM14_CCR1_CCR1_Msk = 0xffff

	// TIM14_TISEL: TIM14 timer input selection register
	// Position of TI1SEL field.
	TIM14_TIM14_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM14_TIM14_TISEL_TI1SEL_Msk = 0xf
)

// Bitfields for TIM15: TIM15
const (
	// TIM15_CR1: TIM15 control register 1
	// Position of CEN field.
	TIMER_TIM15_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIMER_TIM15_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIMER_TIM15_CR1_CEN = 0x1
	// Position of UDIS field.
	TIMER_TIM15_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIMER_TIM15_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIMER_TIM15_CR1_UDIS = 0x2
	// Position of URS field.
	TIMER_TIM15_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIMER_TIM15_CR1_URS_Msk = 0x4
	// Bit URS.
	TIMER_TIM15_CR1_URS = 0x4
	// Position of OPM field.
	TIMER_TIM15_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIMER_TIM15_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIMER_TIM15_CR1_OPM = 0x8
	// Position of ARPE field.
	TIMER_TIM15_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIMER_TIM15_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIMER_TIM15_CR1_ARPE = 0x80
	// Position of CKD field.
	TIMER_TIM15_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIMER_TIM15_CR1_CKD_Msk = 0x300
	// Position of UIFREMAP field.
	TIMER_TIM15_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIMER_TIM15_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIMER_TIM15_CR1_UIFREMAP = 0x800

	// TIM15_CR2: TIM15 control register 2
	// Position of CCPC field.
	TIMER_TIM15_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIMER_TIM15_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIMER_TIM15_CR2_CCPC = 0x1
	// Position of CCUS field.
	TIMER_TIM15_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIMER_TIM15_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIMER_TIM15_CR2_CCUS = 0x4
	// Position of CCDS field.
	TIMER_TIM15_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIMER_TIM15_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIMER_TIM15_CR2_CCDS = 0x8
	// Position of MMS field.
	TIMER_TIM15_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIMER_TIM15_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIMER_TIM15_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIMER_TIM15_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIMER_TIM15_CR2_TI1S = 0x80
	// Position of OIS1 field.
	TIMER_TIM15_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIMER_TIM15_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIMER_TIM15_CR2_OIS1 = 0x100
	// Position of OIS1N field.
	TIMER_TIM15_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIMER_TIM15_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIMER_TIM15_CR2_OIS1N = 0x200
	// Position of OIS2 field.
	TIMER_TIM15_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIMER_TIM15_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIMER_TIM15_CR2_OIS2 = 0x400

	// TIMx_SMCR: slave mode control register
	// Position of TS_4_3 field.
	TIMER_TIMx_SMCR_TS_4_3_Pos = 0x14
	// Bit mask of TS_4_3 field.
	TIMER_TIMx_SMCR_TS_4_3_Msk = 0x300000
	// Position of SMS_3 field.
	TIMER_TIMx_SMCR_SMS_3_Pos = 0x10
	// Bit mask of SMS_3 field.
	TIMER_TIMx_SMCR_SMS_3_Msk = 0x10000
	// Bit SMS_3.
	TIMER_TIMx_SMCR_SMS_3 = 0x10000
	// Position of MSM field.
	TIMER_TIMx_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIMER_TIMx_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIMER_TIMx_SMCR_MSM = 0x80
	// Position of TS field.
	TIMER_TIMx_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIMER_TIMx_SMCR_TS_Msk = 0x70
	// Position of SMS field.
	TIMER_TIMx_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIMER_TIMx_SMCR_SMS_Msk = 0x7

	// TIM15_DIER: TIM15 DMA/interrupt enable register
	// Position of UIE field.
	TIMER_TIM15_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIMER_TIM15_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIMER_TIM15_DIER_UIE = 0x1
	// Position of CC1IE field.
	TIMER_TIM15_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIMER_TIM15_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIMER_TIM15_DIER_CC1IE = 0x2
	// Position of CC2IE field.
	TIMER_TIM15_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIMER_TIM15_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIMER_TIM15_DIER_CC2IE = 0x4
	// Position of COMIE field.
	TIMER_TIM15_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIMER_TIM15_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIMER_TIM15_DIER_COMIE = 0x20
	// Position of TIE field.
	TIMER_TIM15_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIMER_TIM15_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIMER_TIM15_DIER_TIE = 0x40
	// Position of BIE field.
	TIMER_TIM15_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIMER_TIM15_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIMER_TIM15_DIER_BIE = 0x80
	// Position of UDE field.
	TIMER_TIM15_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIMER_TIM15_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIMER_TIM15_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIMER_TIM15_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIMER_TIM15_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIMER_TIM15_DIER_CC1DE = 0x200
	// Position of CC2DE field.
	TIMER_TIM15_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIMER_TIM15_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIMER_TIM15_DIER_CC2DE = 0x400
	// Position of COMDE field.
	TIMER_TIM15_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIMER_TIM15_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIMER_TIM15_DIER_COMDE = 0x2000
	// Position of TDE field.
	TIMER_TIM15_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIMER_TIM15_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIMER_TIM15_DIER_TDE = 0x4000

	// TIM15_SR: TIM15 status register
	// Position of UIF field.
	TIMER_TIM15_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIMER_TIM15_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIMER_TIM15_SR_UIF = 0x1
	// Position of CC1IF field.
	TIMER_TIM15_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIMER_TIM15_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIMER_TIM15_SR_CC1IF = 0x2
	// Position of CC2IF field.
	TIMER_TIM15_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIMER_TIM15_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIMER_TIM15_SR_CC2IF = 0x4
	// Position of COMIF field.
	TIMER_TIM15_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIMER_TIM15_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIMER_TIM15_SR_COMIF = 0x20
	// Position of TIF field.
	TIMER_TIM15_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIMER_TIM15_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIMER_TIM15_SR_TIF = 0x40
	// Position of BIF field.
	TIMER_TIM15_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIMER_TIM15_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIMER_TIM15_SR_BIF = 0x80
	// Position of CC1OF field.
	TIMER_TIM15_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIMER_TIM15_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIMER_TIM15_SR_CC1OF = 0x200
	// Position of CC2OF field.
	TIMER_TIM15_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIMER_TIM15_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIMER_TIM15_SR_CC2OF = 0x400

	// TIMx_EGR: event generation register
	// Position of BG field.
	TIMER_TIMx_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIMER_TIMx_EGR_BG_Msk = 0x80
	// Bit BG.
	TIMER_TIMx_EGR_BG = 0x80
	// Position of TG field.
	TIMER_TIMx_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIMER_TIMx_EGR_TG_Msk = 0x40
	// Bit TG.
	TIMER_TIMx_EGR_TG = 0x40
	// Position of COMG field.
	TIMER_TIMx_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIMER_TIMx_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIMER_TIMx_EGR_COMG = 0x20
	// Position of CC2G field.
	TIMER_TIMx_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIMER_TIMx_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIMER_TIMx_EGR_CC2G = 0x4
	// Position of CC1G field.
	TIMER_TIMx_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIMER_TIMx_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIMER_TIMx_EGR_CC1G = 0x2
	// Position of UG field.
	TIMER_TIMx_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIMER_TIMx_EGR_UG_Msk = 0x1
	// Bit UG.
	TIMER_TIMx_EGR_UG = 0x1

	// TIMx_CCMR1_Output: capture/compare mode register 1 (output mode)
	// Position of OC2M_3 field.
	TIMER_TIMx_CCMR1_Output_OC2M_3_Pos = 0x18
	// Bit mask of OC2M_3 field.
	TIMER_TIMx_CCMR1_Output_OC2M_3_Msk = 0x1000000
	// Bit OC2M_3.
	TIMER_TIMx_CCMR1_Output_OC2M_3 = 0x1000000
	// Position of OC1M_3 field.
	TIMER_TIMx_CCMR1_Output_OC1M_3_Pos = 0x10
	// Bit mask of OC1M_3 field.
	TIMER_TIMx_CCMR1_Output_OC1M_3_Msk = 0x10000
	// Bit OC1M_3.
	TIMER_TIMx_CCMR1_Output_OC1M_3 = 0x10000
	// Position of OC2CE field.
	TIMER_TIMx_CCMR1_Output_OC2CE_Pos = 0xf
	// Bit mask of OC2CE field.
	TIMER_TIMx_CCMR1_Output_OC2CE_Msk = 0x8000
	// Bit OC2CE.
	TIMER_TIMx_CCMR1_Output_OC2CE = 0x8000
	// Position of OC2M field.
	TIMER_TIMx_CCMR1_Output_OC2M_Pos = 0xc
	// Bit mask of OC2M field.
	TIMER_TIMx_CCMR1_Output_OC2M_Msk = 0x7000
	// Position of OC2PE field.
	TIMER_TIMx_CCMR1_Output_OC2PE_Pos = 0xb
	// Bit mask of OC2PE field.
	TIMER_TIMx_CCMR1_Output_OC2PE_Msk = 0x800
	// Bit OC2PE.
	TIMER_TIMx_CCMR1_Output_OC2PE = 0x800
	// Position of OC2FE field.
	TIMER_TIMx_CCMR1_Output_OC2FE_Pos = 0xa
	// Bit mask of OC2FE field.
	TIMER_TIMx_CCMR1_Output_OC2FE_Msk = 0x400
	// Bit OC2FE.
	TIMER_TIMx_CCMR1_Output_OC2FE = 0x400
	// Position of CC2S field.
	TIMER_TIMx_CCMR1_Output_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIMER_TIMx_CCMR1_Output_CC2S_Msk = 0x300
	// Position of OC1CE field.
	TIMER_TIMx_CCMR1_Output_OC1CE_Pos = 0x7
	// Bit mask of OC1CE field.
	TIMER_TIMx_CCMR1_Output_OC1CE_Msk = 0x80
	// Bit OC1CE.
	TIMER_TIMx_CCMR1_Output_OC1CE = 0x80
	// Position of OC1M field.
	TIMER_TIMx_CCMR1_Output_OC1M_Pos = 0x4
	// Bit mask of OC1M field.
	TIMER_TIMx_CCMR1_Output_OC1M_Msk = 0x70
	// Position of OC1PE field.
	TIMER_TIMx_CCMR1_Output_OC1PE_Pos = 0x3
	// Bit mask of OC1PE field.
	TIMER_TIMx_CCMR1_Output_OC1PE_Msk = 0x8
	// Bit OC1PE.
	TIMER_TIMx_CCMR1_Output_OC1PE = 0x8
	// Position of OC1FE field.
	TIMER_TIMx_CCMR1_Output_OC1FE_Pos = 0x2
	// Bit mask of OC1FE field.
	TIMER_TIMx_CCMR1_Output_OC1FE_Msk = 0x4
	// Bit OC1FE.
	TIMER_TIMx_CCMR1_Output_OC1FE = 0x4
	// Position of CC1S field.
	TIMER_TIMx_CCMR1_Output_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIMER_TIMx_CCMR1_Output_CC1S_Msk = 0x3

	// TIMx_CCMR1_Input: capture/compare mode register 1 (input mode)
	// Position of IC2F field.
	TIMER_TIMx_CCMR1_Input_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIMER_TIMx_CCMR1_Input_IC2F_Msk = 0xf000
	// Position of IC2PSC field.
	TIMER_TIMx_CCMR1_Input_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIMER_TIMx_CCMR1_Input_IC2PSC_Msk = 0xc00
	// Position of CC2S field.
	TIMER_TIMx_CCMR1_Input_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIMER_TIMx_CCMR1_Input_CC2S_Msk = 0x300
	// Position of IC1F field.
	TIMER_TIMx_CCMR1_Input_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIMER_TIMx_CCMR1_Input_IC1F_Msk = 0xf0
	// Position of IC1PSC field.
	TIMER_TIMx_CCMR1_Input_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIMER_TIMx_CCMR1_Input_IC1PSC_Msk = 0xc
	// Position of CC1S field.
	TIMER_TIMx_CCMR1_Input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIMER_TIMx_CCMR1_Input_CC1S_Msk = 0x3

	// TIM15_CCER: TIM15 capture/compare enable register
	// Position of CC1E field.
	TIMER_TIM15_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIMER_TIM15_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIMER_TIM15_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIMER_TIM15_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIMER_TIM15_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIMER_TIM15_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIMER_TIM15_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIMER_TIM15_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIMER_TIM15_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIMER_TIM15_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIMER_TIM15_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIMER_TIM15_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIMER_TIM15_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIMER_TIM15_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIMER_TIM15_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIMER_TIM15_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIMER_TIM15_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIMER_TIM15_CCER_CC2P = 0x20
	// Position of CC2NP field.
	TIMER_TIM15_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIMER_TIM15_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIMER_TIM15_CCER_CC2NP = 0x80

	// TIM15_CNT: TIM15 counter
	// Position of CNT field.
	TIMER_TIM15_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIMER_TIM15_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIMER_TIM15_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIMER_TIM15_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIMER_TIM15_CNT_UIFCPY = 0x80000000

	// TIM15_PSC: TIM15 prescaler
	// Position of PSC field.
	TIMER_TIM15_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIMER_TIM15_PSC_PSC_Msk = 0xffff

	// TIM15_ARR: TIM15 auto-reload register
	// Position of ARR field.
	TIMER_TIM15_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIMER_TIM15_ARR_ARR_Msk = 0xffff

	// TIM15_RCR: TIM15 repetition counter register
	// Position of REP field.
	TIMER_TIM15_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIMER_TIM15_RCR_REP_Msk = 0xff

	// TIM15_CCR1: TIM15 capture/compare register 1
	// Position of CCR1 field.
	TIMER_TIM15_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	TIMER_TIM15_CCR1_CCR1_Msk = 0xffff

	// TIM15_CCR2: TIM15 capture/compare register 2
	// Position of CCR2 field.
	TIMER_TIM15_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	TIMER_TIM15_CCR2_CCR2_Msk = 0xffff

	// TIMx_BDTR: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
	// Position of DTG field.
	TIMER_TIMx_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIMER_TIMx_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIMER_TIMx_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIMER_TIMx_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIMER_TIMx_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIMER_TIMx_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIMER_TIMx_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIMER_TIMx_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIMER_TIMx_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIMER_TIMx_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIMER_TIMx_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIMER_TIMx_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIMER_TIMx_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIMER_TIMx_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIMER_TIMx_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIMER_TIMx_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIMER_TIMx_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIMER_TIMx_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIMER_TIMx_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIMER_TIMx_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIMER_TIMx_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIMER_TIMx_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIMER_TIMx_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIMER_TIMx_BDTR_BKF_Msk = 0xf0000
	// Position of BKDSRM field.
	TIMER_TIMx_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIMER_TIMx_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIMER_TIMx_BDTR_BKDSRM = 0x4000000
	// Position of BKBID field.
	TIMER_TIMx_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIMER_TIMx_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIMER_TIMx_BDTR_BKBID = 0x10000000

	// TIM15_DCR: TIM15 DMA control register
	// Position of DBA field.
	TIMER_TIM15_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIMER_TIM15_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIMER_TIM15_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIMER_TIM15_DCR_DBL_Msk = 0x1f00

	// TIM15_DMAR: TIM15 DMA address for full transfer
	// Position of DMAB field.
	TIMER_TIM15_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIMER_TIM15_DMAR_DMAB_Msk = 0xffff

	// TIM15_AF1: TIM15 alternate register 1
	// Position of BKINE field.
	TIMER_TIM15_AF1_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIMER_TIM15_AF1_BKINE_Msk = 0x1
	// Bit BKINE.
	TIMER_TIM15_AF1_BKINE = 0x1
	// Position of BKDF1BK0E field.
	TIMER_TIM15_AF1_BKDF1BK0E_Pos = 0x8
	// Bit mask of BKDF1BK0E field.
	TIMER_TIM15_AF1_BKDF1BK0E_Msk = 0x100
	// Bit BKDF1BK0E.
	TIMER_TIM15_AF1_BKDF1BK0E = 0x100
	// Position of BKINP field.
	TIMER_TIM15_AF1_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIMER_TIM15_AF1_BKINP_Msk = 0x200
	// Bit BKINP.
	TIMER_TIM15_AF1_BKINP = 0x200

	// TIM15_TISEL: TIM15 input selection register
	// Position of TI1SEL field.
	TIMER_TIM15_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIMER_TIM15_TISEL_TI1SEL_Msk = 0xf
	// Position of TI2SEL field.
	TIMER_TIM15_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIMER_TIM15_TISEL_TI2SEL_Msk = 0xf00
)

// Bitfields for TZC: TZC
const (
	// TZC_BUILD_CONFIG: Provides information about TZC configuration.
	// Position of NO_OF_REGIONS field.
	TZC_TZC_BUILD_CONFIG_NO_OF_REGIONS_Pos = 0x0
	// Bit mask of NO_OF_REGIONS field.
	TZC_TZC_BUILD_CONFIG_NO_OF_REGIONS_Msk = 0x1f
	// Position of ADDRESS_WIDTH field.
	TZC_TZC_BUILD_CONFIG_ADDRESS_WIDTH_Pos = 0x8
	// Bit mask of ADDRESS_WIDTH field.
	TZC_TZC_BUILD_CONFIG_ADDRESS_WIDTH_Msk = 0x3f00
	// Position of NO_OF_FILTERS field.
	TZC_TZC_BUILD_CONFIG_NO_OF_FILTERS_Pos = 0x18
	// Bit mask of NO_OF_FILTERS field.
	TZC_TZC_BUILD_CONFIG_NO_OF_FILTERS_Msk = 0x3000000

	// TZC_ACTION: Controls interrupt and bus error response behavior when regions permission failures occur.
	// Position of REACTION_VALUE field.
	TZC_TZC_ACTION_REACTION_VALUE_Pos = 0x0
	// Bit mask of REACTION_VALUE field.
	TZC_TZC_ACTION_REACTION_VALUE_Msk = 0x3

	// TZC_GATE_KEEPER: Provides control and status for the gate keeper in each filter unit implemented.
	// Position of OPENREQ field.
	TZC_TZC_GATE_KEEPER_OPENREQ_Pos = 0x0
	// Bit mask of OPENREQ field.
	TZC_TZC_GATE_KEEPER_OPENREQ_Msk = 0x3
	// Position of OPENSTAT field.
	TZC_TZC_GATE_KEEPER_OPENSTAT_Pos = 0x10
	// Bit mask of OPENSTAT field.
	TZC_TZC_GATE_KEEPER_OPENSTAT_Msk = 0x30000

	// TZC_SPECULATION_CTRL: Controls read and write access speculation.
	// Position of READSPEC_DISABLE field.
	TZC_TZC_SPECULATION_CTRL_READSPEC_DISABLE_Pos = 0x0
	// Bit mask of READSPEC_DISABLE field.
	TZC_TZC_SPECULATION_CTRL_READSPEC_DISABLE_Msk = 0x1
	// Bit READSPEC_DISABLE.
	TZC_TZC_SPECULATION_CTRL_READSPEC_DISABLE = 0x1
	// Position of WRITESPEC_DISABLE field.
	TZC_TZC_SPECULATION_CTRL_WRITESPEC_DISABLE_Pos = 0x1
	// Bit mask of WRITESPEC_DISABLE field.
	TZC_TZC_SPECULATION_CTRL_WRITESPEC_DISABLE_Msk = 0x2
	// Bit WRITESPEC_DISABLE.
	TZC_TZC_SPECULATION_CTRL_WRITESPEC_DISABLE = 0x2

	// TZC_INT_STATUS: Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors.
	// Position of STATUS field.
	TZC_TZC_INT_STATUS_STATUS_Pos = 0x0
	// Bit mask of STATUS field.
	TZC_TZC_INT_STATUS_STATUS_Msk = 0x3
	// Position of OVERRUN field.
	TZC_TZC_INT_STATUS_OVERRUN_Pos = 0x8
	// Bit mask of OVERRUN field.
	TZC_TZC_INT_STATUS_OVERRUN_Msk = 0x300
	// Position of OVERLAP field.
	TZC_TZC_INT_STATUS_OVERLAP_Pos = 0x10
	// Bit mask of OVERLAP field.
	TZC_TZC_INT_STATUS_OVERLAP_Msk = 0x30000

	// TZC_INT_CLEAR: Interrupt clear for each filter.
	// Position of CLEAR field.
	TZC_TZC_INT_CLEAR_CLEAR_Pos = 0x0
	// Bit mask of CLEAR field.
	TZC_TZC_INT_CLEAR_CLEAR_Msk = 0x3

	// TZC_FAIL_ADDRESS_LOW0: Address low bits of the first failed access in the associated filter (0 to 1).
	// Position of ADDR_STATUS_LOW field.
	TZC_TZC_FAIL_ADDRESS_LOW0_ADDR_STATUS_LOW_Pos = 0x0
	// Bit mask of ADDR_STATUS_LOW field.
	TZC_TZC_FAIL_ADDRESS_LOW0_ADDR_STATUS_LOW_Msk = 0xffffffff

	// TZC_FAIL_CONTROL0: Status information about the first access that failed a region permission check in the associated filter (0 to 1).
	// Position of PRIVILEGE field.
	TZC_TZC_FAIL_CONTROL0_PRIVILEGE_Pos = 0x14
	// Bit mask of PRIVILEGE field.
	TZC_TZC_FAIL_CONTROL0_PRIVILEGE_Msk = 0x100000
	// Bit PRIVILEGE.
	TZC_TZC_FAIL_CONTROL0_PRIVILEGE = 0x100000
	// Position of NON_SECURE field.
	TZC_TZC_FAIL_CONTROL0_NON_SECURE_Pos = 0x15
	// Bit mask of NON_SECURE field.
	TZC_TZC_FAIL_CONTROL0_NON_SECURE_Msk = 0x200000
	// Bit NON_SECURE.
	TZC_TZC_FAIL_CONTROL0_NON_SECURE = 0x200000
	// Position of DIRECTION field.
	TZC_TZC_FAIL_CONTROL0_DIRECTION_Pos = 0x18
	// Bit mask of DIRECTION field.
	TZC_TZC_FAIL_CONTROL0_DIRECTION_Msk = 0x1000000
	// Bit DIRECTION.
	TZC_TZC_FAIL_CONTROL0_DIRECTION = 0x1000000

	// TZC_FAIL_ID0: Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD).
	// Position of ID field.
	TZC_TZC_FAIL_ID0_ID_Pos = 0x0
	// Bit mask of ID field.
	TZC_TZC_FAIL_ID0_ID_Msk = 0x7ff

	// TZC_FAIL_ADDRESS_LOW1: Address low bits of the first failed access in the associated filter (0 to 1).
	// Position of ADDR_STATUS_LOW field.
	TZC_TZC_FAIL_ADDRESS_LOW1_ADDR_STATUS_LOW_Pos = 0x0
	// Bit mask of ADDR_STATUS_LOW field.
	TZC_TZC_FAIL_ADDRESS_LOW1_ADDR_STATUS_LOW_Msk = 0xffffffff

	// TZC_FAIL_CONTROL1: Status information about the first access that failed a region permission check in the associated filter (0 to 1).
	// Position of PRIVILEGE field.
	TZC_TZC_FAIL_CONTROL1_PRIVILEGE_Pos = 0x14
	// Bit mask of PRIVILEGE field.
	TZC_TZC_FAIL_CONTROL1_PRIVILEGE_Msk = 0x100000
	// Bit PRIVILEGE.
	TZC_TZC_FAIL_CONTROL1_PRIVILEGE = 0x100000
	// Position of NON_SECURE field.
	TZC_TZC_FAIL_CONTROL1_NON_SECURE_Pos = 0x15
	// Bit mask of NON_SECURE field.
	TZC_TZC_FAIL_CONTROL1_NON_SECURE_Msk = 0x200000
	// Bit NON_SECURE.
	TZC_TZC_FAIL_CONTROL1_NON_SECURE = 0x200000
	// Position of DIRECTION field.
	TZC_TZC_FAIL_CONTROL1_DIRECTION_Pos = 0x18
	// Bit mask of DIRECTION field.
	TZC_TZC_FAIL_CONTROL1_DIRECTION_Msk = 0x1000000
	// Bit DIRECTION.
	TZC_TZC_FAIL_CONTROL1_DIRECTION = 0x1000000

	// TZC_FAIL_ID1: Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD).
	// Position of ID field.
	TZC_TZC_FAIL_ID1_ID_Pos = 0x0
	// Bit mask of ID field.
	TZC_TZC_FAIL_ID1_ID_Msk = 0x7ff

	// TZC_REGION_TOP_LOW0: Top address bits [31:12] for region 0.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW0_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW0_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE0: Region 0 attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE0_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE0_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE0_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE0_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE0_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE0_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE0_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE0_S_WR_EN = 0x80000000

	// TZC_REGION_ID_ACCESS0: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS0_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS0_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS0_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS0_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_BASE_LOW1: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW1_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW1_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_TOP_LOW1: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW1_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW1_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE1: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE1_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE1_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE1_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE1_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE1_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE1_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE1_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE1_S_WR_EN = 0x80000000

	// TZC_REGION_ID_ACCESS1: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS1_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS1_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS1_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS1_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_BASE_LOW2: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW2_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW2_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_TOP_LOW2: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW2_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW2_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE2: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE2_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE2_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE2_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE2_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE2_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE2_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE2_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE2_S_WR_EN = 0x80000000

	// TZC_REGION_ID_ACCESS2: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS2_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS2_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS2_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS2_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_BASE_LOW3: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW3_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW3_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_TOP_LOW3: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW3_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW3_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE3: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE3_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE3_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE3_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE3_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE3_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE3_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE3_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE3_S_WR_EN = 0x80000000

	// TZC_REGION_ID_ACCESS3: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS3_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS3_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS3_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS3_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_BASE_LOW4: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW4_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW4_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_TOP_LOW4: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW4_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW4_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE4: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE4_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE4_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE4_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE4_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE4_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE4_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE4_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE4_S_WR_EN = 0x80000000

	// TZC_REGION_ID_ACCESS4: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS4_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS4_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS4_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS4_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_BASE_LOW5: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW5_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW5_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_TOP_LOW5: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW5_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW5_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE5: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE5_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE5_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE5_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE5_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE5_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE5_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE5_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE5_S_WR_EN = 0x80000000

	// TZC_REGION_ID_ACCESS5: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS5_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS5_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS5_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS5_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_BASE_LOW6: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW6_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW6_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_TOP_LOW6: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW6_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW6_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE6: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE6_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE6_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE6_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE6_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE6_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE6_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE6_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE6_S_WR_EN = 0x80000000

	// TZC_REGION_ID_ACCESS6: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS6_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS6_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS6_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS6_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_TOP_LOW7: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW7_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW7_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE7: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE7_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE7_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE7_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE7_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE7_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE7_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE7_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE7_S_WR_EN = 0x80000000

	// TZC_REGION_BASE_LOW8: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW8_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW8_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ATTRIBUTE8: Region x attributes.
	// Position of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE8_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TZC_TZC_REGION_ATTRIBUTE8_FILTER_EN_Msk = 0x3
	// Position of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE8_S_RD_EN_Pos = 0x1e
	// Bit mask of S_RD_EN field.
	TZC_TZC_REGION_ATTRIBUTE8_S_RD_EN_Msk = 0x40000000
	// Bit S_RD_EN.
	TZC_TZC_REGION_ATTRIBUTE8_S_RD_EN = 0x40000000
	// Position of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE8_S_WR_EN_Pos = 0x1f
	// Bit mask of S_WR_EN field.
	TZC_TZC_REGION_ATTRIBUTE8_S_WR_EN_Msk = 0x80000000
	// Bit S_WR_EN.
	TZC_TZC_REGION_ATTRIBUTE8_S_WR_EN = 0x80000000

	// TZC_REGION_BASE_LOW7: Base address low for regions 1 to 8.
	// Position of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW7_BASE_ADDRESS_LOW_Pos = 0xc
	// Bit mask of BASE_ADDRESS_LOW field.
	TZC_TZC_REGION_BASE_LOW7_BASE_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ID_ACCESS7: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS7_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS7_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS7_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS7_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_REGION_TOP_LOW8: Top address bits [31:12] for region x.
	// Position of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW8_TOP_ADDRESS_LOW_Pos = 0xc
	// Bit mask of TOP_ADDRESS_LOW field.
	TZC_TZC_REGION_TOP_LOW8_TOP_ADDRESS_LOW_Msk = 0xfffff000

	// TZC_REGION_ID_ACCESS8: Region non-secure access based on NSAID.
	// Position of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS8_NSAID_RD_EN_Pos = 0x0
	// Bit mask of NSAID_RD_EN field.
	TZC_TZC_REGION_ID_ACCESS8_NSAID_RD_EN_Msk = 0xffff
	// Position of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS8_NSAID_WR_EN_Pos = 0x10
	// Bit mask of NSAID_WR_EN field.
	TZC_TZC_REGION_ID_ACCESS8_NSAID_WR_EN_Msk = 0xffff0000

	// TZC_PID4: Peripheral ID 4.
	// Position of PER_ID_4 field.
	TZC_TZC_PID4_PER_ID_4_Pos = 0x0
	// Bit mask of PER_ID_4 field.
	TZC_TZC_PID4_PER_ID_4_Msk = 0xff

	// TZC_PID5: Peripheral ID 5.
	// Position of PER_ID_5 field.
	TZC_TZC_PID5_PER_ID_5_Pos = 0x0
	// Bit mask of PER_ID_5 field.
	TZC_TZC_PID5_PER_ID_5_Msk = 0xff

	// TZC_PID6: Peripheral ID 6.
	// Position of PER_ID_6 field.
	TZC_TZC_PID6_PER_ID_6_Pos = 0x0
	// Bit mask of PER_ID_6 field.
	TZC_TZC_PID6_PER_ID_6_Msk = 0xff

	// TZC_PID7: Peripheral ID 7.
	// Position of PER_ID_7 field.
	TZC_TZC_PID7_PER_ID_7_Pos = 0x0
	// Bit mask of PER_ID_7 field.
	TZC_TZC_PID7_PER_ID_7_Msk = 0xff

	// TZC_PID0: Peripheral ID 0.
	// Position of PER_ID_0 field.
	TZC_TZC_PID0_PER_ID_0_Pos = 0x0
	// Bit mask of PER_ID_0 field.
	TZC_TZC_PID0_PER_ID_0_Msk = 0xff

	// TZC_PID1: Peripheral ID 1.
	// Position of PER_ID_1 field.
	TZC_TZC_PID1_PER_ID_1_Pos = 0x0
	// Bit mask of PER_ID_1 field.
	TZC_TZC_PID1_PER_ID_1_Msk = 0xff

	// TZC_PID2: Peripheral ID 2.
	// Position of PER_ID_2 field.
	TZC_TZC_PID2_PER_ID_2_Pos = 0x0
	// Bit mask of PER_ID_2 field.
	TZC_TZC_PID2_PER_ID_2_Msk = 0xff

	// TZC_PID3: Peripheral ID 3.
	// Position of PER_ID_3 field.
	TZC_TZC_PID3_PER_ID_3_Pos = 0x0
	// Bit mask of PER_ID_3 field.
	TZC_TZC_PID3_PER_ID_3_Msk = 0xff

	// TZC_CID0: Component ID 0.
	// Position of COMP_ID_0 field.
	TZC_TZC_CID0_COMP_ID_0_Pos = 0x0
	// Bit mask of COMP_ID_0 field.
	TZC_TZC_CID0_COMP_ID_0_Msk = 0xff

	// TZC_CID1: Component ID 1.
	// Position of COMP_ID_1 field.
	TZC_TZC_CID1_COMP_ID_1_Pos = 0x0
	// Bit mask of COMP_ID_1 field.
	TZC_TZC_CID1_COMP_ID_1_Msk = 0xff

	// TZC_CID2: Component ID 2.
	// Position of COMP_ID_2 field.
	TZC_TZC_CID2_COMP_ID_2_Pos = 0x0
	// Bit mask of COMP_ID_2 field.
	TZC_TZC_CID2_COMP_ID_2_Msk = 0xff

	// TZC_CID3: Component ID 3.
	// Position of COMP_ID_3 field.
	TZC_TZC_CID3_COMP_ID_3_Pos = 0x0
	// Bit mask of COMP_ID_3 field.
	TZC_TZC_CID3_COMP_ID_3_Msk = 0xff
)

// Bitfields for USART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	// Position of RXFFIE field.
	USART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	USART_CR1_RXFFIE = 0x80000000
	// Position of TXFEIE field.
	USART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	USART_CR1_TXFEIE = 0x40000000
	// Position of FIFOEN field.
	USART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	USART_CR1_FIFOEN = 0x20000000
	// Position of M1 field.
	USART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	USART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	USART_CR1_M1 = 0x10000000
	// Position of EOBIE field.
	USART_CR1_EOBIE_Pos = 0x1b
	// Bit mask of EOBIE field.
	USART_CR1_EOBIE_Msk = 0x8000000
	// Bit EOBIE.
	USART_CR1_EOBIE = 0x8000000
	// Position of RTOIE field.
	USART_CR1_RTOIE_Pos = 0x1a
	// Bit mask of RTOIE field.
	USART_CR1_RTOIE_Msk = 0x4000000
	// Bit RTOIE.
	USART_CR1_RTOIE = 0x4000000
	// Position of DEAT field.
	USART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	USART_CR1_DEAT_Msk = 0x3e00000
	// Position of DEDT field.
	USART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	USART_CR1_DEDT_Msk = 0x1f0000
	// Position of OVER8 field.
	USART_CR1_OVER8_Pos = 0xf
	// Bit mask of OVER8 field.
	USART_CR1_OVER8_Msk = 0x8000
	// Bit OVER8.
	USART_CR1_OVER8 = 0x8000
	// Position of CMIE field.
	USART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	USART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	USART_CR1_CMIE = 0x4000
	// Position of MME field.
	USART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	USART_CR1_MME_Msk = 0x2000
	// Bit MME.
	USART_CR1_MME = 0x2000
	// Position of M0 field.
	USART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	USART_CR1_M0_Msk = 0x1000
	// Bit M0.
	USART_CR1_M0 = 0x1000
	// Position of WAKE field.
	USART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	USART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	USART_CR1_WAKE = 0x800
	// Position of PCE field.
	USART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	USART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	USART_CR1_PCE = 0x400
	// Position of PS field.
	USART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	USART_CR1_PS_Msk = 0x200
	// Bit PS.
	USART_CR1_PS = 0x200
	// Position of PEIE field.
	USART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	USART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	USART_CR1_PEIE = 0x100
	// Position of TXEIE field.
	USART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	USART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	USART_CR1_TXEIE = 0x80
	// Position of TCIE field.
	USART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	USART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	USART_CR1_TCIE = 0x40
	// Position of RXNEIE field.
	USART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	USART_CR1_RXNEIE = 0x20
	// Position of IDLEIE field.
	USART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	USART_CR1_IDLEIE = 0x10
	// Position of TE field.
	USART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	USART_CR1_TE_Msk = 0x8
	// Bit TE.
	USART_CR1_TE = 0x8
	// Position of RE field.
	USART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	USART_CR1_RE_Msk = 0x4
	// Bit RE.
	USART_CR1_RE = 0x4
	// Position of UESM field.
	USART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	USART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	USART_CR1_UESM = 0x2
	// Position of UE field.
	USART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	USART_CR1_UE_Msk = 0x1
	// Bit UE.
	USART_CR1_UE = 0x1

	// CR2: Control register 2
	// Position of ADD4_7 field.
	USART_CR2_ADD4_7_Pos = 0x1c
	// Bit mask of ADD4_7 field.
	USART_CR2_ADD4_7_Msk = 0xf0000000
	// Position of ADD0_3 field.
	USART_CR2_ADD0_3_Pos = 0x18
	// Bit mask of ADD0_3 field.
	USART_CR2_ADD0_3_Msk = 0xf000000
	// Position of RTOEN field.
	USART_CR2_RTOEN_Pos = 0x17
	// Bit mask of RTOEN field.
	USART_CR2_RTOEN_Msk = 0x800000
	// Bit RTOEN.
	USART_CR2_RTOEN = 0x800000
	// Position of ABRMOD field.
	USART_CR2_ABRMOD_Pos = 0x15
	// Bit mask of ABRMOD field.
	USART_CR2_ABRMOD_Msk = 0x600000
	// Position of ABREN field.
	USART_CR2_ABREN_Pos = 0x14
	// Bit mask of ABREN field.
	USART_CR2_ABREN_Msk = 0x100000
	// Bit ABREN.
	USART_CR2_ABREN = 0x100000
	// Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	USART_CR2_MSBFIRST = 0x80000
	// Position of TAINV field.
	USART_CR2_TAINV_Pos = 0x12
	// Bit mask of TAINV field.
	USART_CR2_TAINV_Msk = 0x40000
	// Bit TAINV.
	USART_CR2_TAINV = 0x40000
	// Position of TXINV field.
	USART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	USART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	USART_CR2_TXINV = 0x20000
	// Position of RXINV field.
	USART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	USART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	USART_CR2_RXINV = 0x10000
	// Position of SWAP field.
	USART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	USART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	USART_CR2_SWAP = 0x8000
	// Position of LINEN field.
	USART_CR2_LINEN_Pos = 0xe
	// Bit mask of LINEN field.
	USART_CR2_LINEN_Msk = 0x4000
	// Bit LINEN.
	USART_CR2_LINEN = 0x4000
	// Position of STOP field.
	USART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	USART_CR2_STOP_Msk = 0x3000
	// Position of CLKEN field.
	USART_CR2_CLKEN_Pos = 0xb
	// Bit mask of CLKEN field.
	USART_CR2_CLKEN_Msk = 0x800
	// Bit CLKEN.
	USART_CR2_CLKEN = 0x800
	// Position of CPOL field.
	USART_CR2_CPOL_Pos = 0xa
	// Bit mask of CPOL field.
	USART_CR2_CPOL_Msk = 0x400
	// Bit CPOL.
	USART_CR2_CPOL = 0x400
	// Position of CPHA field.
	USART_CR2_CPHA_Pos = 0x9
	// Bit mask of CPHA field.
	USART_CR2_CPHA_Msk = 0x200
	// Bit CPHA.
	USART_CR2_CPHA = 0x200
	// Position of LBCL field.
	USART_CR2_LBCL_Pos = 0x8
	// Bit mask of LBCL field.
	USART_CR2_LBCL_Msk = 0x100
	// Bit LBCL.
	USART_CR2_LBCL = 0x100
	// Position of LBDIE field.
	USART_CR2_LBDIE_Pos = 0x6
	// Bit mask of LBDIE field.
	USART_CR2_LBDIE_Msk = 0x40
	// Bit LBDIE.
	USART_CR2_LBDIE = 0x40
	// Position of LBDL field.
	USART_CR2_LBDL_Pos = 0x5
	// Bit mask of LBDL field.
	USART_CR2_LBDL_Msk = 0x20
	// Bit LBDL.
	USART_CR2_LBDL = 0x20
	// Position of ADDM7 field.
	USART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	USART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	USART_CR2_ADDM7 = 0x10
	// Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Pos = 0x3
	// Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk = 0x8
	// Bit DIS_NSS.
	USART_CR2_DIS_NSS = 0x8
	// Position of SLVEN field.
	USART_CR2_SLVEN_Pos = 0x0
	// Bit mask of SLVEN field.
	USART_CR2_SLVEN_Msk = 0x1
	// Bit SLVEN.
	USART_CR2_SLVEN = 0x1

	// CR3: Control register 3
	// Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000
	// Position of RXFTIE field.
	USART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	USART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	USART_CR3_RXFTIE = 0x10000000
	// Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000
	// Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Pos = 0x18
	// Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000
	// Bit TCBGTIE.
	USART_CR3_TCBGTIE = 0x1000000
	// Position of TXFTIE field.
	USART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	USART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	USART_CR3_TXFTIE = 0x800000
	// Position of WUFIE field.
	USART_CR3_WUFIE_Pos = 0x16
	// Bit mask of WUFIE field.
	USART_CR3_WUFIE_Msk = 0x400000
	// Bit WUFIE.
	USART_CR3_WUFIE = 0x400000
	// Position of WUS field.
	USART_CR3_WUS_Pos = 0x14
	// Bit mask of WUS field.
	USART_CR3_WUS_Msk = 0x300000
	// Position of SCARCNT field.
	USART_CR3_SCARCNT_Pos = 0x11
	// Bit mask of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000
	// Position of DEP field.
	USART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	USART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	USART_CR3_DEP = 0x8000
	// Position of DEM field.
	USART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	USART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	USART_CR3_DEM = 0x4000
	// Position of DDRE field.
	USART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	USART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	USART_CR3_DDRE = 0x2000
	// Position of OVRDIS field.
	USART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	USART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	USART_CR3_OVRDIS = 0x1000
	// Position of ONEBIT field.
	USART_CR3_ONEBIT_Pos = 0xb
	// Bit mask of ONEBIT field.
	USART_CR3_ONEBIT_Msk = 0x800
	// Bit ONEBIT.
	USART_CR3_ONEBIT = 0x800
	// Position of CTSIE field.
	USART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	USART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	USART_CR3_CTSIE = 0x400
	// Position of CTSE field.
	USART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	USART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	USART_CR3_CTSE = 0x200
	// Position of RTSE field.
	USART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	USART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	USART_CR3_RTSE = 0x100
	// Position of DMAT field.
	USART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	USART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	USART_CR3_DMAT = 0x80
	// Position of DMAR field.
	USART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	USART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	USART_CR3_DMAR = 0x40
	// Position of SCEN field.
	USART_CR3_SCEN_Pos = 0x5
	// Bit mask of SCEN field.
	USART_CR3_SCEN_Msk = 0x20
	// Bit SCEN.
	USART_CR3_SCEN = 0x20
	// Position of NACK field.
	USART_CR3_NACK_Pos = 0x4
	// Bit mask of NACK field.
	USART_CR3_NACK_Msk = 0x10
	// Bit NACK.
	USART_CR3_NACK = 0x10
	// Position of HDSEL field.
	USART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	USART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	USART_CR3_HDSEL = 0x8
	// Position of IRLP field.
	USART_CR3_IRLP_Pos = 0x2
	// Bit mask of IRLP field.
	USART_CR3_IRLP_Msk = 0x4
	// Bit IRLP.
	USART_CR3_IRLP = 0x4
	// Position of IREN field.
	USART_CR3_IREN_Pos = 0x1
	// Bit mask of IREN field.
	USART_CR3_IREN_Msk = 0x2
	// Bit IREN.
	USART_CR3_IREN = 0x2
	// Position of EIE field.
	USART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	USART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	USART_CR3_EIE = 0x1

	// BRR: Baud rate register
	// Position of BRR_4_15 field.
	USART_BRR_BRR_4_15_Pos = 0x4
	// Bit mask of BRR_4_15 field.
	USART_BRR_BRR_4_15_Msk = 0xfff0
	// Position of BRR_0_3 field.
	USART_BRR_BRR_0_3_Pos = 0x0
	// Bit mask of BRR_0_3 field.
	USART_BRR_BRR_0_3_Msk = 0xf

	// GTPR: Guard time and prescaler register
	// Position of GT field.
	USART_GTPR_GT_Pos = 0x8
	// Bit mask of GT field.
	USART_GTPR_GT_Msk = 0xff00
	// Position of PSC field.
	USART_GTPR_PSC_Pos = 0x0
	// Bit mask of PSC field.
	USART_GTPR_PSC_Msk = 0xff

	// RTOR: Receiver timeout register
	// Position of BLEN field.
	USART_RTOR_BLEN_Pos = 0x18
	// Bit mask of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000
	// Position of RTO field.
	USART_RTOR_RTO_Pos = 0x0
	// Bit mask of RTO field.
	USART_RTOR_RTO_Msk = 0xffffff

	// RQR: Request register
	// Position of TXFRQ field.
	USART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	USART_RQR_TXFRQ = 0x10
	// Position of RXFRQ field.
	USART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	USART_RQR_RXFRQ = 0x8
	// Position of MMRQ field.
	USART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	USART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	USART_RQR_MMRQ = 0x4
	// Position of SBKRQ field.
	USART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	USART_RQR_SBKRQ = 0x2
	// Position of ABRRQ field.
	USART_RQR_ABRRQ_Pos = 0x0
	// Bit mask of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1
	// Bit ABRRQ.
	USART_RQR_ABRRQ = 0x1

	// ISR: Interrupt & status register
	// Position of TXFT field.
	USART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	USART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	USART_ISR_TXFT = 0x8000000
	// Position of RXFT field.
	USART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	USART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	USART_ISR_RXFT = 0x4000000
	// Position of TCBGT field.
	USART_ISR_TCBGT_Pos = 0x19
	// Bit mask of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000
	// Bit TCBGT.
	USART_ISR_TCBGT = 0x2000000
	// Position of RXFF field.
	USART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	USART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	USART_ISR_RXFF = 0x1000000
	// Position of TXFE field.
	USART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	USART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	USART_ISR_TXFE = 0x800000
	// Position of REACK field.
	USART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	USART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	USART_ISR_REACK = 0x400000
	// Position of TEACK field.
	USART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	USART_ISR_TEACK = 0x200000
	// Position of WUF field.
	USART_ISR_WUF_Pos = 0x14
	// Bit mask of WUF field.
	USART_ISR_WUF_Msk = 0x100000
	// Bit WUF.
	USART_ISR_WUF = 0x100000
	// Position of RWU field.
	USART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	USART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	USART_ISR_RWU = 0x80000
	// Position of SBKF field.
	USART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	USART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	USART_ISR_SBKF = 0x40000
	// Position of CMF field.
	USART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	USART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	USART_ISR_CMF = 0x20000
	// Position of BUSY field.
	USART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	USART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	USART_ISR_BUSY = 0x10000
	// Position of ABRF field.
	USART_ISR_ABRF_Pos = 0xf
	// Bit mask of ABRF field.
	USART_ISR_ABRF_Msk = 0x8000
	// Bit ABRF.
	USART_ISR_ABRF = 0x8000
	// Position of ABRE field.
	USART_ISR_ABRE_Pos = 0xe
	// Bit mask of ABRE field.
	USART_ISR_ABRE_Msk = 0x4000
	// Bit ABRE.
	USART_ISR_ABRE = 0x4000
	// Position of UDR field.
	USART_ISR_UDR_Pos = 0xd
	// Bit mask of UDR field.
	USART_ISR_UDR_Msk = 0x2000
	// Bit UDR.
	USART_ISR_UDR = 0x2000
	// Position of EOBF field.
	USART_ISR_EOBF_Pos = 0xc
	// Bit mask of EOBF field.
	USART_ISR_EOBF_Msk = 0x1000
	// Bit EOBF.
	USART_ISR_EOBF = 0x1000
	// Position of RTOF field.
	USART_ISR_RTOF_Pos = 0xb
	// Bit mask of RTOF field.
	USART_ISR_RTOF_Msk = 0x800
	// Bit RTOF.
	USART_ISR_RTOF = 0x800
	// Position of CTS field.
	USART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	USART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	USART_ISR_CTS = 0x400
	// Position of CTSIF field.
	USART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	USART_ISR_CTSIF = 0x200
	// Position of LBDF field.
	USART_ISR_LBDF_Pos = 0x8
	// Bit mask of LBDF field.
	USART_ISR_LBDF_Msk = 0x100
	// Bit LBDF.
	USART_ISR_LBDF = 0x100
	// Position of TXE field.
	USART_ISR_TXE_Pos = 0x7
	// Bit mask of TXE field.
	USART_ISR_TXE_Msk = 0x80
	// Bit TXE.
	USART_ISR_TXE = 0x80
	// Position of TC field.
	USART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	USART_ISR_TC_Msk = 0x40
	// Bit TC.
	USART_ISR_TC = 0x40
	// Position of RXNE field.
	USART_ISR_RXNE_Pos = 0x5
	// Bit mask of RXNE field.
	USART_ISR_RXNE_Msk = 0x20
	// Bit RXNE.
	USART_ISR_RXNE = 0x20
	// Position of IDLE field.
	USART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	USART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	USART_ISR_IDLE = 0x10
	// Position of ORE field.
	USART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	USART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	USART_ISR_ORE = 0x8
	// Position of NF field.
	USART_ISR_NF_Pos = 0x2
	// Bit mask of NF field.
	USART_ISR_NF_Msk = 0x4
	// Bit NF.
	USART_ISR_NF = 0x4
	// Position of FE field.
	USART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	USART_ISR_FE_Msk = 0x2
	// Bit FE.
	USART_ISR_FE = 0x2
	// Position of PE field.
	USART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	USART_ISR_PE_Msk = 0x1
	// Bit PE.
	USART_ISR_PE = 0x1

	// ICR: Interrupt flag clear register
	// Position of WUCF field.
	USART_ICR_WUCF_Pos = 0x14
	// Bit mask of WUCF field.
	USART_ICR_WUCF_Msk = 0x100000
	// Bit WUCF.
	USART_ICR_WUCF = 0x100000
	// Position of CMCF field.
	USART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	USART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	USART_ICR_CMCF = 0x20000
	// Position of UDRCF field.
	USART_ICR_UDRCF_Pos = 0xd
	// Bit mask of UDRCF field.
	USART_ICR_UDRCF_Msk = 0x2000
	// Bit UDRCF.
	USART_ICR_UDRCF = 0x2000
	// Position of EOBCF field.
	USART_ICR_EOBCF_Pos = 0xc
	// Bit mask of EOBCF field.
	USART_ICR_EOBCF_Msk = 0x1000
	// Bit EOBCF.
	USART_ICR_EOBCF = 0x1000
	// Position of RTOCF field.
	USART_ICR_RTOCF_Pos = 0xb
	// Bit mask of RTOCF field.
	USART_ICR_RTOCF_Msk = 0x800
	// Bit RTOCF.
	USART_ICR_RTOCF = 0x800
	// Position of CTSCF field.
	USART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	USART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	USART_ICR_CTSCF = 0x200
	// Position of LBDCF field.
	USART_ICR_LBDCF_Pos = 0x8
	// Bit mask of LBDCF field.
	USART_ICR_LBDCF_Msk = 0x100
	// Bit LBDCF.
	USART_ICR_LBDCF = 0x100
	// Position of TCBGTCF field.
	USART_ICR_TCBGTCF_Pos = 0x7
	// Bit mask of TCBGTCF field.
	USART_ICR_TCBGTCF_Msk = 0x80
	// Bit TCBGTCF.
	USART_ICR_TCBGTCF = 0x80
	// Position of TCCF field.
	USART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	USART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	USART_ICR_TCCF = 0x40
	// Position of TXFECF field.
	USART_ICR_TXFECF_Pos = 0x5
	// Bit mask of TXFECF field.
	USART_ICR_TXFECF_Msk = 0x20
	// Bit TXFECF.
	USART_ICR_TXFECF = 0x20
	// Position of IDLECF field.
	USART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	USART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	USART_ICR_IDLECF = 0x10
	// Position of ORECF field.
	USART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	USART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	USART_ICR_ORECF = 0x8
	// Position of NCF field.
	USART_ICR_NCF_Pos = 0x2
	// Bit mask of NCF field.
	USART_ICR_NCF_Msk = 0x4
	// Bit NCF.
	USART_ICR_NCF = 0x4
	// Position of FECF field.
	USART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	USART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	USART_ICR_FECF = 0x2
	// Position of PECF field.
	USART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	USART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	USART_ICR_PECF = 0x1

	// RDR: Receive data register
	// Position of RDR field.
	USART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	USART_RDR_RDR_Msk = 0x1ff

	// TDR: Transmit data register
	// Position of TDR field.
	USART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	USART_TDR_TDR_Msk = 0x1ff

	// PRESC: Prescaler register
	// Position of PRESCALER field.
	USART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf

	// HWCFGR2: USART Hardware Configuration register 2
	// Position of CFG1 field.
	USART_HWCFGR2_CFG1_Pos = 0x0
	// Bit mask of CFG1 field.
	USART_HWCFGR2_CFG1_Msk = 0xf
	// Position of CFG2 field.
	USART_HWCFGR2_CFG2_Pos = 0x4
	// Bit mask of CFG2 field.
	USART_HWCFGR2_CFG2_Msk = 0xf0

	// HWCFGR1: USART Hardware Configuration register 1
	// Position of CFG1 field.
	USART_HWCFGR1_CFG1_Pos = 0x0
	// Bit mask of CFG1 field.
	USART_HWCFGR1_CFG1_Msk = 0xf
	// Position of CFG2 field.
	USART_HWCFGR1_CFG2_Pos = 0x4
	// Bit mask of CFG2 field.
	USART_HWCFGR1_CFG2_Msk = 0xf0
	// Position of CFG3 field.
	USART_HWCFGR1_CFG3_Pos = 0x8
	// Bit mask of CFG3 field.
	USART_HWCFGR1_CFG3_Msk = 0xf00
	// Position of CFG4 field.
	USART_HWCFGR1_CFG4_Pos = 0xc
	// Bit mask of CFG4 field.
	USART_HWCFGR1_CFG4_Msk = 0xf000
	// Position of CFG5 field.
	USART_HWCFGR1_CFG5_Pos = 0x10
	// Bit mask of CFG5 field.
	USART_HWCFGR1_CFG5_Msk = 0xf0000
	// Position of CFG6 field.
	USART_HWCFGR1_CFG6_Pos = 0x14
	// Bit mask of CFG6 field.
	USART_HWCFGR1_CFG6_Msk = 0xf00000
	// Position of CFG7 field.
	USART_HWCFGR1_CFG7_Pos = 0x18
	// Bit mask of CFG7 field.
	USART_HWCFGR1_CFG7_Msk = 0xf000000
	// Position of CFG8 field.
	USART_HWCFGR1_CFG8_Pos = 0x1c
	// Bit mask of CFG8 field.
	USART_HWCFGR1_CFG8_Msk = 0xf0000000

	// VERR: EXTI IP Version register
	// Position of MINREV field.
	USART_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	USART_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	USART_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	USART_VERR_MAJREV_Msk = 0xf0

	// IPIDR: EXTI Identification register
	// Position of IPID field.
	USART_IPIDR_IPID_Pos = 0x0
	// Bit mask of IPID field.
	USART_IPIDR_IPID_Msk = 0xffffffff

	// SIDR: EXTI Size ID register
	// Position of SID field.
	USART_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	USART_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for USBPHYC: USBPHYC
const (
	// USBPHYC_PLL: This register is used to control the PLL of the HS PHY.
	// Position of PLLNDIV field.
	USBPHYC_USBPHYC_PLL_PLLNDIV_Pos = 0x0
	// Bit mask of PLLNDIV field.
	USBPHYC_USBPHYC_PLL_PLLNDIV_Msk = 0x7f
	// Position of PLLODF field.
	USBPHYC_USBPHYC_PLL_PLLODF_Pos = 0x7
	// Bit mask of PLLODF field.
	USBPHYC_USBPHYC_PLL_PLLODF_Msk = 0x380
	// Position of PLLFRACIN field.
	USBPHYC_USBPHYC_PLL_PLLFRACIN_Pos = 0xa
	// Bit mask of PLLFRACIN field.
	USBPHYC_USBPHYC_PLL_PLLFRACIN_Msk = 0x3fffc00
	// Position of PLLEN field.
	USBPHYC_USBPHYC_PLL_PLLEN_Pos = 0x1a
	// Bit mask of PLLEN field.
	USBPHYC_USBPHYC_PLL_PLLEN_Msk = 0x4000000
	// Bit PLLEN.
	USBPHYC_USBPHYC_PLL_PLLEN = 0x4000000
	// Position of PLLSTRB field.
	USBPHYC_USBPHYC_PLL_PLLSTRB_Pos = 0x1b
	// Bit mask of PLLSTRB field.
	USBPHYC_USBPHYC_PLL_PLLSTRB_Msk = 0x8000000
	// Bit PLLSTRB.
	USBPHYC_USBPHYC_PLL_PLLSTRB = 0x8000000
	// Position of PLLSTRBYP field.
	USBPHYC_USBPHYC_PLL_PLLSTRBYP_Pos = 0x1c
	// Bit mask of PLLSTRBYP field.
	USBPHYC_USBPHYC_PLL_PLLSTRBYP_Msk = 0x10000000
	// Bit PLLSTRBYP.
	USBPHYC_USBPHYC_PLL_PLLSTRBYP = 0x10000000
	// Position of PLLFRACCTL field.
	USBPHYC_USBPHYC_PLL_PLLFRACCTL_Pos = 0x1d
	// Bit mask of PLLFRACCTL field.
	USBPHYC_USBPHYC_PLL_PLLFRACCTL_Msk = 0x20000000
	// Bit PLLFRACCTL.
	USBPHYC_USBPHYC_PLL_PLLFRACCTL = 0x20000000
	// Position of PLLDITHEN0 field.
	USBPHYC_USBPHYC_PLL_PLLDITHEN0_Pos = 0x1e
	// Bit mask of PLLDITHEN0 field.
	USBPHYC_USBPHYC_PLL_PLLDITHEN0_Msk = 0x40000000
	// Bit PLLDITHEN0.
	USBPHYC_USBPHYC_PLL_PLLDITHEN0 = 0x40000000
	// Position of PLLDITHEN1 field.
	USBPHYC_USBPHYC_PLL_PLLDITHEN1_Pos = 0x1f
	// Bit mask of PLLDITHEN1 field.
	USBPHYC_USBPHYC_PLL_PLLDITHEN1_Msk = 0x80000000
	// Bit PLLDITHEN1.
	USBPHYC_USBPHYC_PLL_PLLDITHEN1 = 0x80000000

	// USBPHYC_MISC: This register is used to control the switch between controllers for the HS PHY.
	// Position of SWITHOST field.
	USBPHYC_USBPHYC_MISC_SWITHOST_Pos = 0x0
	// Bit mask of SWITHOST field.
	USBPHYC_USBPHYC_MISC_SWITHOST_Msk = 0x1
	// Bit SWITHOST.
	USBPHYC_USBPHYC_MISC_SWITHOST = 0x1
	// Position of PPCKDIS field.
	USBPHYC_USBPHYC_MISC_PPCKDIS_Pos = 0x1
	// Bit mask of PPCKDIS field.
	USBPHYC_USBPHYC_MISC_PPCKDIS_Msk = 0x6

	// USBPHYC_TUNE1: This register is used to control the tune interface of the HS PHY, port #x.
	// Position of INCURREN field.
	USBPHYC_USBPHYC_TUNE1_INCURREN_Pos = 0x0
	// Bit mask of INCURREN field.
	USBPHYC_USBPHYC_TUNE1_INCURREN_Msk = 0x1
	// Bit INCURREN.
	USBPHYC_USBPHYC_TUNE1_INCURREN = 0x1
	// Position of INCURRINT field.
	USBPHYC_USBPHYC_TUNE1_INCURRINT_Pos = 0x1
	// Bit mask of INCURRINT field.
	USBPHYC_USBPHYC_TUNE1_INCURRINT_Msk = 0x2
	// Bit INCURRINT.
	USBPHYC_USBPHYC_TUNE1_INCURRINT = 0x2
	// Position of LFSCAPEN field.
	USBPHYC_USBPHYC_TUNE1_LFSCAPEN_Pos = 0x2
	// Bit mask of LFSCAPEN field.
	USBPHYC_USBPHYC_TUNE1_LFSCAPEN_Msk = 0x4
	// Bit LFSCAPEN.
	USBPHYC_USBPHYC_TUNE1_LFSCAPEN = 0x4
	// Position of HSDRVSLEW field.
	USBPHYC_USBPHYC_TUNE1_HSDRVSLEW_Pos = 0x3
	// Bit mask of HSDRVSLEW field.
	USBPHYC_USBPHYC_TUNE1_HSDRVSLEW_Msk = 0x8
	// Bit HSDRVSLEW.
	USBPHYC_USBPHYC_TUNE1_HSDRVSLEW = 0x8
	// Position of HSDRVDCCUR field.
	USBPHYC_USBPHYC_TUNE1_HSDRVDCCUR_Pos = 0x4
	// Bit mask of HSDRVDCCUR field.
	USBPHYC_USBPHYC_TUNE1_HSDRVDCCUR_Msk = 0x10
	// Bit HSDRVDCCUR.
	USBPHYC_USBPHYC_TUNE1_HSDRVDCCUR = 0x10
	// Position of HSDRVDCLEV field.
	USBPHYC_USBPHYC_TUNE1_HSDRVDCLEV_Pos = 0x5
	// Bit mask of HSDRVDCLEV field.
	USBPHYC_USBPHYC_TUNE1_HSDRVDCLEV_Msk = 0x20
	// Bit HSDRVDCLEV.
	USBPHYC_USBPHYC_TUNE1_HSDRVDCLEV = 0x20
	// Position of HSDRVCURINCR field.
	USBPHYC_USBPHYC_TUNE1_HSDRVCURINCR_Pos = 0x6
	// Bit mask of HSDRVCURINCR field.
	USBPHYC_USBPHYC_TUNE1_HSDRVCURINCR_Msk = 0x40
	// Bit HSDRVCURINCR.
	USBPHYC_USBPHYC_TUNE1_HSDRVCURINCR = 0x40
	// Position of FSDRVRFADJ field.
	USBPHYC_USBPHYC_TUNE1_FSDRVRFADJ_Pos = 0x7
	// Bit mask of FSDRVRFADJ field.
	USBPHYC_USBPHYC_TUNE1_FSDRVRFADJ_Msk = 0x80
	// Bit FSDRVRFADJ.
	USBPHYC_USBPHYC_TUNE1_FSDRVRFADJ = 0x80
	// Position of HSDRVRFRED field.
	USBPHYC_USBPHYC_TUNE1_HSDRVRFRED_Pos = 0x8
	// Bit mask of HSDRVRFRED field.
	USBPHYC_USBPHYC_TUNE1_HSDRVRFRED_Msk = 0x100
	// Bit HSDRVRFRED.
	USBPHYC_USBPHYC_TUNE1_HSDRVRFRED = 0x100
	// Position of HSDRVCHKITRM field.
	USBPHYC_USBPHYC_TUNE1_HSDRVCHKITRM_Pos = 0x9
	// Bit mask of HSDRVCHKITRM field.
	USBPHYC_USBPHYC_TUNE1_HSDRVCHKITRM_Msk = 0x1e00
	// Position of HSDRVCHKZTRM field.
	USBPHYC_USBPHYC_TUNE1_HSDRVCHKZTRM_Pos = 0xd
	// Bit mask of HSDRVCHKZTRM field.
	USBPHYC_USBPHYC_TUNE1_HSDRVCHKZTRM_Msk = 0x6000
	// Position of OTPCOMP field.
	USBPHYC_USBPHYC_TUNE1_OTPCOMP_Pos = 0xf
	// Bit mask of OTPCOMP field.
	USBPHYC_USBPHYC_TUNE1_OTPCOMP_Msk = 0xf8000
	// Position of SQLCHCTL field.
	USBPHYC_USBPHYC_TUNE1_SQLCHCTL_Pos = 0x14
	// Bit mask of SQLCHCTL field.
	USBPHYC_USBPHYC_TUNE1_SQLCHCTL_Msk = 0x300000
	// Position of HDRXGNEQEN field.
	USBPHYC_USBPHYC_TUNE1_HDRXGNEQEN_Pos = 0x16
	// Bit mask of HDRXGNEQEN field.
	USBPHYC_USBPHYC_TUNE1_HDRXGNEQEN_Msk = 0x400000
	// Bit HDRXGNEQEN.
	USBPHYC_USBPHYC_TUNE1_HDRXGNEQEN = 0x400000
	// Position of HSRXOFF field.
	USBPHYC_USBPHYC_TUNE1_HSRXOFF_Pos = 0x17
	// Bit mask of HSRXOFF field.
	USBPHYC_USBPHYC_TUNE1_HSRXOFF_Msk = 0x1800000
	// Position of HSFALLPREEM field.
	USBPHYC_USBPHYC_TUNE1_HSFALLPREEM_Pos = 0x19
	// Bit mask of HSFALLPREEM field.
	USBPHYC_USBPHYC_TUNE1_HSFALLPREEM_Msk = 0x2000000
	// Bit HSFALLPREEM.
	USBPHYC_USBPHYC_TUNE1_HSFALLPREEM = 0x2000000
	// Position of SHTCCTCTLPROT field.
	USBPHYC_USBPHYC_TUNE1_SHTCCTCTLPROT_Pos = 0x1a
	// Bit mask of SHTCCTCTLPROT field.
	USBPHYC_USBPHYC_TUNE1_SHTCCTCTLPROT_Msk = 0x4000000
	// Bit SHTCCTCTLPROT.
	USBPHYC_USBPHYC_TUNE1_SHTCCTCTLPROT = 0x4000000
	// Position of STAGSEL field.
	USBPHYC_USBPHYC_TUNE1_STAGSEL_Pos = 0x1b
	// Bit mask of STAGSEL field.
	USBPHYC_USBPHYC_TUNE1_STAGSEL_Msk = 0x8000000
	// Bit STAGSEL.
	USBPHYC_USBPHYC_TUNE1_STAGSEL = 0x8000000

	// USBPHYC_TUNE2: This register is used to control the tune interface of the HS PHY, port #x.
	// Position of INCURREN field.
	USBPHYC_USBPHYC_TUNE2_INCURREN_Pos = 0x0
	// Bit mask of INCURREN field.
	USBPHYC_USBPHYC_TUNE2_INCURREN_Msk = 0x1
	// Bit INCURREN.
	USBPHYC_USBPHYC_TUNE2_INCURREN = 0x1
	// Position of INCURRINT field.
	USBPHYC_USBPHYC_TUNE2_INCURRINT_Pos = 0x1
	// Bit mask of INCURRINT field.
	USBPHYC_USBPHYC_TUNE2_INCURRINT_Msk = 0x2
	// Bit INCURRINT.
	USBPHYC_USBPHYC_TUNE2_INCURRINT = 0x2
	// Position of LFSCAPEN field.
	USBPHYC_USBPHYC_TUNE2_LFSCAPEN_Pos = 0x2
	// Bit mask of LFSCAPEN field.
	USBPHYC_USBPHYC_TUNE2_LFSCAPEN_Msk = 0x4
	// Bit LFSCAPEN.
	USBPHYC_USBPHYC_TUNE2_LFSCAPEN = 0x4
	// Position of HSDRVSLEW field.
	USBPHYC_USBPHYC_TUNE2_HSDRVSLEW_Pos = 0x3
	// Bit mask of HSDRVSLEW field.
	USBPHYC_USBPHYC_TUNE2_HSDRVSLEW_Msk = 0x8
	// Bit HSDRVSLEW.
	USBPHYC_USBPHYC_TUNE2_HSDRVSLEW = 0x8
	// Position of HSDRVDCCUR field.
	USBPHYC_USBPHYC_TUNE2_HSDRVDCCUR_Pos = 0x4
	// Bit mask of HSDRVDCCUR field.
	USBPHYC_USBPHYC_TUNE2_HSDRVDCCUR_Msk = 0x10
	// Bit HSDRVDCCUR.
	USBPHYC_USBPHYC_TUNE2_HSDRVDCCUR = 0x10
	// Position of HSDRVDCLEV field.
	USBPHYC_USBPHYC_TUNE2_HSDRVDCLEV_Pos = 0x5
	// Bit mask of HSDRVDCLEV field.
	USBPHYC_USBPHYC_TUNE2_HSDRVDCLEV_Msk = 0x20
	// Bit HSDRVDCLEV.
	USBPHYC_USBPHYC_TUNE2_HSDRVDCLEV = 0x20
	// Position of HSDRVCURINCR field.
	USBPHYC_USBPHYC_TUNE2_HSDRVCURINCR_Pos = 0x6
	// Bit mask of HSDRVCURINCR field.
	USBPHYC_USBPHYC_TUNE2_HSDRVCURINCR_Msk = 0x40
	// Bit HSDRVCURINCR.
	USBPHYC_USBPHYC_TUNE2_HSDRVCURINCR = 0x40
	// Position of FSDRVRFADJ field.
	USBPHYC_USBPHYC_TUNE2_FSDRVRFADJ_Pos = 0x7
	// Bit mask of FSDRVRFADJ field.
	USBPHYC_USBPHYC_TUNE2_FSDRVRFADJ_Msk = 0x80
	// Bit FSDRVRFADJ.
	USBPHYC_USBPHYC_TUNE2_FSDRVRFADJ = 0x80
	// Position of HSDRVRFRED field.
	USBPHYC_USBPHYC_TUNE2_HSDRVRFRED_Pos = 0x8
	// Bit mask of HSDRVRFRED field.
	USBPHYC_USBPHYC_TUNE2_HSDRVRFRED_Msk = 0x100
	// Bit HSDRVRFRED.
	USBPHYC_USBPHYC_TUNE2_HSDRVRFRED = 0x100
	// Position of HSDRVCHKITRM field.
	USBPHYC_USBPHYC_TUNE2_HSDRVCHKITRM_Pos = 0x9
	// Bit mask of HSDRVCHKITRM field.
	USBPHYC_USBPHYC_TUNE2_HSDRVCHKITRM_Msk = 0x1e00
	// Position of HSDRVCHKZTRM field.
	USBPHYC_USBPHYC_TUNE2_HSDRVCHKZTRM_Pos = 0xd
	// Bit mask of HSDRVCHKZTRM field.
	USBPHYC_USBPHYC_TUNE2_HSDRVCHKZTRM_Msk = 0x6000
	// Position of OTPCOMP field.
	USBPHYC_USBPHYC_TUNE2_OTPCOMP_Pos = 0xf
	// Bit mask of OTPCOMP field.
	USBPHYC_USBPHYC_TUNE2_OTPCOMP_Msk = 0xf8000
	// Position of SQLCHCTL field.
	USBPHYC_USBPHYC_TUNE2_SQLCHCTL_Pos = 0x14
	// Bit mask of SQLCHCTL field.
	USBPHYC_USBPHYC_TUNE2_SQLCHCTL_Msk = 0x300000
	// Position of HDRXGNEQEN field.
	USBPHYC_USBPHYC_TUNE2_HDRXGNEQEN_Pos = 0x16
	// Bit mask of HDRXGNEQEN field.
	USBPHYC_USBPHYC_TUNE2_HDRXGNEQEN_Msk = 0x400000
	// Bit HDRXGNEQEN.
	USBPHYC_USBPHYC_TUNE2_HDRXGNEQEN = 0x400000
	// Position of HSRXOFF field.
	USBPHYC_USBPHYC_TUNE2_HSRXOFF_Pos = 0x17
	// Bit mask of HSRXOFF field.
	USBPHYC_USBPHYC_TUNE2_HSRXOFF_Msk = 0x1800000
	// Position of HSFALLPREEM field.
	USBPHYC_USBPHYC_TUNE2_HSFALLPREEM_Pos = 0x19
	// Bit mask of HSFALLPREEM field.
	USBPHYC_USBPHYC_TUNE2_HSFALLPREEM_Msk = 0x2000000
	// Bit HSFALLPREEM.
	USBPHYC_USBPHYC_TUNE2_HSFALLPREEM = 0x2000000
	// Position of SHTCCTCTLPROT field.
	USBPHYC_USBPHYC_TUNE2_SHTCCTCTLPROT_Pos = 0x1a
	// Bit mask of SHTCCTCTLPROT field.
	USBPHYC_USBPHYC_TUNE2_SHTCCTCTLPROT_Msk = 0x4000000
	// Bit SHTCCTCTLPROT.
	USBPHYC_USBPHYC_TUNE2_SHTCCTCTLPROT = 0x4000000
	// Position of STAGSEL field.
	USBPHYC_USBPHYC_TUNE2_STAGSEL_Pos = 0x1b
	// Bit mask of STAGSEL field.
	USBPHYC_USBPHYC_TUNE2_STAGSEL_Msk = 0x8000000
	// Bit STAGSEL.
	USBPHYC_USBPHYC_TUNE2_STAGSEL = 0x8000000

	// USBPHYC_VERR: This register defines the version of this IP.
	// Position of MINREV field.
	USBPHYC_USBPHYC_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	USBPHYC_USBPHYC_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	USBPHYC_USBPHYC_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	USBPHYC_USBPHYC_VERR_MAJREV_Msk = 0xf0
)

// Bitfields for VREFBUF: VREFBUF
const (
	// VREFBUF_CSR: VREFBUF control and status register
	// Position of ENVR field.
	VREFBUF_VREFBUF_CSR_ENVR_Pos = 0x0
	// Bit mask of ENVR field.
	VREFBUF_VREFBUF_CSR_ENVR_Msk = 0x1
	// Bit ENVR.
	VREFBUF_VREFBUF_CSR_ENVR = 0x1
	// Position of HIZ field.
	VREFBUF_VREFBUF_CSR_HIZ_Pos = 0x1
	// Bit mask of HIZ field.
	VREFBUF_VREFBUF_CSR_HIZ_Msk = 0x2
	// Bit HIZ.
	VREFBUF_VREFBUF_CSR_HIZ = 0x2
	// Position of VRR field.
	VREFBUF_VREFBUF_CSR_VRR_Pos = 0x3
	// Bit mask of VRR field.
	VREFBUF_VREFBUF_CSR_VRR_Msk = 0x8
	// Bit VRR.
	VREFBUF_VREFBUF_CSR_VRR = 0x8
	// Position of VRS field.
	VREFBUF_VREFBUF_CSR_VRS_Pos = 0x4
	// Bit mask of VRS field.
	VREFBUF_VREFBUF_CSR_VRS_Msk = 0x70

	// VREFBUF_CCR: VREFBUF calibration control register
	// Position of TRIM field.
	VREFBUF_VREFBUF_CCR_TRIM_Pos = 0x0
	// Bit mask of TRIM field.
	VREFBUF_VREFBUF_CCR_TRIM_Msk = 0x3f
)

// Bitfields for WWDG1: WWDG1
const (
	// WWDG_CR: Control register
	// Position of T field.
	WWDG1_WWDG_CR_T_Pos = 0x0
	// Bit mask of T field.
	WWDG1_WWDG_CR_T_Msk = 0x7f
	// Position of WDGA field.
	WWDG1_WWDG_CR_WDGA_Pos = 0x7
	// Bit mask of WDGA field.
	WWDG1_WWDG_CR_WDGA_Msk = 0x80
	// Bit WDGA.
	WWDG1_WWDG_CR_WDGA = 0x80

	// WWDG_CFR: Configuration register
	// Position of W field.
	WWDG1_WWDG_CFR_W_Pos = 0x0
	// Bit mask of W field.
	WWDG1_WWDG_CFR_W_Msk = 0x7f
	// Position of EWI field.
	WWDG1_WWDG_CFR_EWI_Pos = 0x9
	// Bit mask of EWI field.
	WWDG1_WWDG_CFR_EWI_Msk = 0x200
	// Bit EWI.
	WWDG1_WWDG_CFR_EWI = 0x200
	// Position of WDGTB field.
	WWDG1_WWDG_CFR_WDGTB_Pos = 0xb
	// Bit mask of WDGTB field.
	WWDG1_WWDG_CFR_WDGTB_Msk = 0x3800

	// WWDG_SR: Status register
	// Position of EWIF field.
	WWDG1_WWDG_SR_EWIF_Pos = 0x0
	// Bit mask of EWIF field.
	WWDG1_WWDG_SR_EWIF_Msk = 0x1
	// Bit EWIF.
	WWDG1_WWDG_SR_EWIF = 0x1

	// WWDG_HWCFGR: WWDG hardware configuration register
	// Position of PREDIV field.
	WWDG1_WWDG_HWCFGR_PREDIV_Pos = 0x0
	// Bit mask of PREDIV field.
	WWDG1_WWDG_HWCFGR_PREDIV_Msk = 0xffff

	// WWDG_VERR: WWDG version register
	// Position of MINREV field.
	WWDG1_WWDG_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	WWDG1_WWDG_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	WWDG1_WWDG_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	WWDG1_WWDG_VERR_MAJREV_Msk = 0xf0

	// WWDG_IPIDR: WWDG ID register
	// Position of ID field.
	WWDG1_WWDG_IPIDR_ID_Pos = 0x0
	// Bit mask of ID field.
	WWDG1_WWDG_IPIDR_ID_Msk = 0xffffffff

	// WWDG_SIDR: WWDG size ID register
	// Position of SID field.
	WWDG1_WWDG_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	WWDG1_WWDG_SIDR_SID_Msk = 0xffffffff
)
