// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from ATSAME54P19A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel

// +build sam,atsame54p19a

// Microchip ATSAME54P19A Microcontroller
//

package sam

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "ATSAME54P19A"
	CPU          = "CM4"
	FPUPresent   = true
	NVICPrioBits = 3
)

// Interrupt numbers.
const (
	// Power Manager
	IRQ_PM = 0

	// Main Clock
	IRQ_MCLK = 1

	// Oscillators Control
	IRQ_OSCCTRL_XOSC0 = 2

	// Oscillators Control
	IRQ_OSCCTRL_XOSC1 = 3

	// Oscillators Control
	IRQ_OSCCTRL_DFLL = 4

	// Oscillators Control
	IRQ_OSCCTRL_DPLL0 = 5

	// Oscillators Control
	IRQ_OSCCTRL_DPLL1 = 6

	// 32kHz Oscillators Control
	IRQ_OSC32KCTRL = 7

	// Supply Controller
	IRQ_SUPC_OTHER = 8

	// Supply Controller
	IRQ_SUPC_BODDET = 9

	// Watchdog Timer
	IRQ_WDT = 10

	// Real-Time Counter
	IRQ_RTC = 11

	// External Interrupt Controller
	IRQ_EIC_EXTINT_0 = 12

	// External Interrupt Controller
	IRQ_EIC_EXTINT_1 = 13

	// External Interrupt Controller
	IRQ_EIC_EXTINT_2 = 14

	// External Interrupt Controller
	IRQ_EIC_EXTINT_3 = 15

	// External Interrupt Controller
	IRQ_EIC_EXTINT_4 = 16

	// External Interrupt Controller
	IRQ_EIC_EXTINT_5 = 17

	// External Interrupt Controller
	IRQ_EIC_EXTINT_6 = 18

	// External Interrupt Controller
	IRQ_EIC_EXTINT_7 = 19

	// External Interrupt Controller
	IRQ_EIC_EXTINT_8 = 20

	// External Interrupt Controller
	IRQ_EIC_EXTINT_9 = 21

	// External Interrupt Controller
	IRQ_EIC_EXTINT_10 = 22

	// External Interrupt Controller
	IRQ_EIC_EXTINT_11 = 23

	// External Interrupt Controller
	IRQ_EIC_EXTINT_12 = 24

	// External Interrupt Controller
	IRQ_EIC_EXTINT_13 = 25

	// External Interrupt Controller
	IRQ_EIC_EXTINT_14 = 26

	// External Interrupt Controller
	IRQ_EIC_EXTINT_15 = 27

	// Frequency Meter
	IRQ_FREQM = 28

	// Non-Volatile Memory Controller
	IRQ_NVMCTRL_0 = 29

	// Non-Volatile Memory Controller
	IRQ_NVMCTRL_1 = 30

	// Direct Memory Access Controller
	IRQ_DMAC_0 = 31

	// Direct Memory Access Controller
	IRQ_DMAC_1 = 32

	// Direct Memory Access Controller
	IRQ_DMAC_2 = 33

	// Direct Memory Access Controller
	IRQ_DMAC_3 = 34

	// Direct Memory Access Controller
	IRQ_DMAC_OTHER = 35

	// Event System Interface
	IRQ_EVSYS_0 = 36

	// Event System Interface
	IRQ_EVSYS_1 = 37

	// Event System Interface
	IRQ_EVSYS_2 = 38

	// Event System Interface
	IRQ_EVSYS_3 = 39

	// Event System Interface
	IRQ_EVSYS_OTHER = 40

	// Peripheral Access Controller
	IRQ_PAC = 41

	// RAM ECC
	IRQ_RAMECC = 45

	// Serial Communication Interface
	IRQ_SERCOM0_0 = 46

	// Serial Communication Interface
	IRQ_SERCOM0_1 = 47

	// Serial Communication Interface
	IRQ_SERCOM0_2 = 48

	// Serial Communication Interface
	IRQ_SERCOM0_OTHER = 49

	IRQ_SERCOM1_0 = 50

	IRQ_SERCOM1_1 = 51

	IRQ_SERCOM1_2 = 52

	IRQ_SERCOM1_OTHER = 53

	IRQ_SERCOM2_0 = 54

	IRQ_SERCOM2_1 = 55

	IRQ_SERCOM2_2 = 56

	IRQ_SERCOM2_OTHER = 57

	IRQ_SERCOM3_0 = 58

	IRQ_SERCOM3_1 = 59

	IRQ_SERCOM3_2 = 60

	IRQ_SERCOM3_OTHER = 61

	IRQ_SERCOM4_0 = 62

	IRQ_SERCOM4_1 = 63

	IRQ_SERCOM4_2 = 64

	IRQ_SERCOM4_OTHER = 65

	IRQ_SERCOM5_0 = 66

	IRQ_SERCOM5_1 = 67

	IRQ_SERCOM5_2 = 68

	IRQ_SERCOM5_OTHER = 69

	IRQ_SERCOM6_0 = 70

	IRQ_SERCOM6_1 = 71

	IRQ_SERCOM6_2 = 72

	IRQ_SERCOM6_OTHER = 73

	IRQ_SERCOM7_0 = 74

	IRQ_SERCOM7_1 = 75

	IRQ_SERCOM7_2 = 76

	IRQ_SERCOM7_OTHER = 77

	// Control Area Network
	IRQ_CAN0 = 78

	IRQ_CAN1 = 79

	// Universal Serial Bus
	IRQ_USB_OTHER = 80

	// Universal Serial Bus
	IRQ_USB_SOF_HSOF = 81

	// Universal Serial Bus
	IRQ_USB_TRCPT0 = 82

	// Universal Serial Bus
	IRQ_USB_TRCPT1 = 83

	// Ethernet MAC
	IRQ_GMAC = 84

	// Timer Counter Control
	IRQ_TCC0_OTHER = 85

	// Timer Counter Control
	IRQ_TCC0_MC0 = 86

	// Timer Counter Control
	IRQ_TCC0_MC1 = 87

	// Timer Counter Control
	IRQ_TCC0_MC2 = 88

	// Timer Counter Control
	IRQ_TCC0_MC3 = 89

	// Timer Counter Control
	IRQ_TCC0_MC4 = 90

	// Timer Counter Control
	IRQ_TCC0_MC5 = 91

	IRQ_TCC1_OTHER = 92

	IRQ_TCC1_MC0 = 93

	IRQ_TCC1_MC1 = 94

	IRQ_TCC1_MC2 = 95

	IRQ_TCC1_MC3 = 96

	IRQ_TCC2_OTHER = 97

	IRQ_TCC2_MC0 = 98

	IRQ_TCC2_MC1 = 99

	IRQ_TCC2_MC2 = 100

	IRQ_TCC3_OTHER = 101

	IRQ_TCC3_MC0 = 102

	IRQ_TCC3_MC1 = 103

	IRQ_TCC4_OTHER = 104

	IRQ_TCC4_MC0 = 105

	IRQ_TCC4_MC1 = 106

	// Basic Timer Counter
	IRQ_TC0 = 107

	IRQ_TC1 = 108

	IRQ_TC2 = 109

	IRQ_TC3 = 110

	IRQ_TC4 = 111

	IRQ_TC5 = 112

	IRQ_TC6 = 113

	IRQ_TC7 = 114

	// Quadrature Decodeur
	IRQ_PDEC_OTHER = 115

	// Quadrature Decodeur
	IRQ_PDEC_MC0 = 116

	// Quadrature Decodeur
	IRQ_PDEC_MC1 = 117

	// Analog Digital Converter
	IRQ_ADC0_OTHER = 118

	// Analog Digital Converter
	IRQ_ADC0_RESRDY = 119

	IRQ_ADC1_OTHER = 120

	IRQ_ADC1_RESRDY = 121

	// Analog Comparators
	IRQ_AC = 122

	// Digital-to-Analog Converter
	IRQ_DAC_OTHER = 123

	// Digital-to-Analog Converter
	IRQ_DAC_EMPTY_0 = 124

	// Digital-to-Analog Converter
	IRQ_DAC_EMPTY_1 = 125

	// Digital-to-Analog Converter
	IRQ_DAC_RESRDY_0 = 126

	// Digital-to-Analog Converter
	IRQ_DAC_RESRDY_1 = 127

	// Inter-IC Sound Interface
	IRQ_I2S = 128

	// Parallel Capture Controller
	IRQ_PCC = 129

	// Advanced Encryption Standard
	IRQ_AES = 130

	// True Random Generator
	IRQ_TRNG = 131

	// Integrity Check Monitor
	IRQ_ICM = 132

	// Quad SPI interface
	IRQ_QSPI = 134

	// SD/MMC Host Controller
	IRQ_SDHC0 = 135

	IRQ_SDHC1 = 136

	// Highest interrupt number on this device.
	IRQ_max = 136
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_PM, "PM_IRQHandler")
	_ = interrupt.Register(IRQ_MCLK, "MCLK_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_XOSC0, "OSCCTRL_XOSC0_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_XOSC1, "OSCCTRL_XOSC1_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_DFLL, "OSCCTRL_DFLL_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_DPLL0, "OSCCTRL_DPLL0_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_DPLL1, "OSCCTRL_DPLL1_IRQHandler")
	_ = interrupt.Register(IRQ_OSC32KCTRL, "OSC32KCTRL_IRQHandler")
	_ = interrupt.Register(IRQ_SUPC_OTHER, "SUPC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SUPC_BODDET, "SUPC_BODDET_IRQHandler")
	_ = interrupt.Register(IRQ_WDT, "WDT_IRQHandler")
	_ = interrupt.Register(IRQ_RTC, "RTC_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_0, "EIC_EXTINT_0_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_1, "EIC_EXTINT_1_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_2, "EIC_EXTINT_2_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_3, "EIC_EXTINT_3_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_4, "EIC_EXTINT_4_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_5, "EIC_EXTINT_5_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_6, "EIC_EXTINT_6_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_7, "EIC_EXTINT_7_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_8, "EIC_EXTINT_8_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_9, "EIC_EXTINT_9_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_10, "EIC_EXTINT_10_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_11, "EIC_EXTINT_11_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_12, "EIC_EXTINT_12_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_13, "EIC_EXTINT_13_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_14, "EIC_EXTINT_14_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_15, "EIC_EXTINT_15_IRQHandler")
	_ = interrupt.Register(IRQ_FREQM, "FREQM_IRQHandler")
	_ = interrupt.Register(IRQ_NVMCTRL_0, "NVMCTRL_0_IRQHandler")
	_ = interrupt.Register(IRQ_NVMCTRL_1, "NVMCTRL_1_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_0, "DMAC_0_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_1, "DMAC_1_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_2, "DMAC_2_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_3, "DMAC_3_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_OTHER, "DMAC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_0, "EVSYS_0_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_1, "EVSYS_1_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_2, "EVSYS_2_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_3, "EVSYS_3_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_OTHER, "EVSYS_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_PAC, "PAC_IRQHandler")
	_ = interrupt.Register(IRQ_RAMECC, "RAMECC_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_0, "SERCOM0_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_1, "SERCOM0_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_2, "SERCOM0_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_OTHER, "SERCOM0_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_0, "SERCOM1_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_1, "SERCOM1_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_2, "SERCOM1_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_OTHER, "SERCOM1_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_0, "SERCOM2_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_1, "SERCOM2_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_2, "SERCOM2_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_OTHER, "SERCOM2_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_0, "SERCOM3_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_1, "SERCOM3_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_2, "SERCOM3_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_OTHER, "SERCOM3_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_0, "SERCOM4_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_1, "SERCOM4_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_2, "SERCOM4_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_OTHER, "SERCOM4_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_0, "SERCOM5_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_1, "SERCOM5_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_2, "SERCOM5_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_OTHER, "SERCOM5_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_0, "SERCOM6_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_1, "SERCOM6_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_2, "SERCOM6_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_OTHER, "SERCOM6_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_0, "SERCOM7_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_1, "SERCOM7_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_2, "SERCOM7_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_OTHER, "SERCOM7_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_CAN0, "CAN0_IRQHandler")
	_ = interrupt.Register(IRQ_CAN1, "CAN1_IRQHandler")
	_ = interrupt.Register(IRQ_USB_OTHER, "USB_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_USB_SOF_HSOF, "USB_SOF_HSOF_IRQHandler")
	_ = interrupt.Register(IRQ_USB_TRCPT0, "USB_TRCPT0_IRQHandler")
	_ = interrupt.Register(IRQ_USB_TRCPT1, "USB_TRCPT1_IRQHandler")
	_ = interrupt.Register(IRQ_GMAC, "GMAC_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_OTHER, "TCC0_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC0, "TCC0_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC1, "TCC0_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC2, "TCC0_MC2_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC3, "TCC0_MC3_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC4, "TCC0_MC4_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC5, "TCC0_MC5_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_OTHER, "TCC1_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC0, "TCC1_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC1, "TCC1_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC2, "TCC1_MC2_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC3, "TCC1_MC3_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_OTHER, "TCC2_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_MC0, "TCC2_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_MC1, "TCC2_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_MC2, "TCC2_MC2_IRQHandler")
	_ = interrupt.Register(IRQ_TCC3_OTHER, "TCC3_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC3_MC0, "TCC3_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC3_MC1, "TCC3_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC4_OTHER, "TCC4_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC4_MC0, "TCC4_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC4_MC1, "TCC4_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TC0, "TC0_IRQHandler")
	_ = interrupt.Register(IRQ_TC1, "TC1_IRQHandler")
	_ = interrupt.Register(IRQ_TC2, "TC2_IRQHandler")
	_ = interrupt.Register(IRQ_TC3, "TC3_IRQHandler")
	_ = interrupt.Register(IRQ_TC4, "TC4_IRQHandler")
	_ = interrupt.Register(IRQ_TC5, "TC5_IRQHandler")
	_ = interrupt.Register(IRQ_TC6, "TC6_IRQHandler")
	_ = interrupt.Register(IRQ_TC7, "TC7_IRQHandler")
	_ = interrupt.Register(IRQ_PDEC_OTHER, "PDEC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_PDEC_MC0, "PDEC_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_PDEC_MC1, "PDEC_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_ADC0_OTHER, "ADC0_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_ADC0_RESRDY, "ADC0_RESRDY_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1_OTHER, "ADC1_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1_RESRDY, "ADC1_RESRDY_IRQHandler")
	_ = interrupt.Register(IRQ_AC, "AC_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_OTHER, "DAC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_EMPTY_0, "DAC_EMPTY_0_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_EMPTY_1, "DAC_EMPTY_1_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_RESRDY_0, "DAC_RESRDY_0_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_RESRDY_1, "DAC_RESRDY_1_IRQHandler")
	_ = interrupt.Register(IRQ_I2S, "I2S_IRQHandler")
	_ = interrupt.Register(IRQ_PCC, "PCC_IRQHandler")
	_ = interrupt.Register(IRQ_AES, "AES_IRQHandler")
	_ = interrupt.Register(IRQ_TRNG, "TRNG_IRQHandler")
	_ = interrupt.Register(IRQ_ICM, "ICM_IRQHandler")
	_ = interrupt.Register(IRQ_QSPI, "QSPI_IRQHandler")
	_ = interrupt.Register(IRQ_SDHC0, "SDHC0_IRQHandler")
	_ = interrupt.Register(IRQ_SDHC1, "SDHC1_IRQHandler")
)

// Peripherals.
var (
	// Analog Comparators
	AC = (*AC_Type)(unsafe.Pointer(uintptr(0x42002000)))

	// Analog Digital Converter
	ADC0 = (*ADC_Type)(unsafe.Pointer(uintptr(0x43001c00)))

	// Advanced Encryption Standard
	AES = (*AES_Type)(unsafe.Pointer(uintptr(0x42002400)))

	// Control Area Network
	CAN0 = (*CAN_Type)(unsafe.Pointer(uintptr(0x42000000)))

	// Configurable Custom Logic
	CCL = (*CCL_Type)(unsafe.Pointer(uintptr(0x42003800)))

	// Cortex M Cache Controller
	CMCC = (*CMCC_Type)(unsafe.Pointer(uintptr(0x41006000)))

	// Digital-to-Analog Converter
	DAC = (*DAC_Type)(unsafe.Pointer(uintptr(0x43002400)))

	// Direct Memory Access Controller
	DMAC = (*DMAC_Type)(unsafe.Pointer(uintptr(0x4100a000)))

	// Device Service Unit
	DSU = (*DSU_Type)(unsafe.Pointer(uintptr(0x41002000)))

	// External Interrupt Controller
	EIC = (*EIC_Type)(unsafe.Pointer(uintptr(0x40002800)))

	// Event System Interface
	EVSYS = (*EVSYS_Type)(unsafe.Pointer(uintptr(0x4100e000)))

	// Frequency Meter
	FREQM = (*FREQM_Type)(unsafe.Pointer(uintptr(0x40002c00)))

	// Generic Clock Generator
	GCLK = (*GCLK_Type)(unsafe.Pointer(uintptr(0x40001c00)))

	// Ethernet MAC
	GMAC = (*GMAC_Type)(unsafe.Pointer(uintptr(0x42000800)))

	// HSB Matrix
	HMATRIX = (*HMATRIXB_Type)(unsafe.Pointer(uintptr(0x4100c000)))

	// Integrity Check Monitor
	ICM = (*ICM_Type)(unsafe.Pointer(uintptr(0x42002c00)))

	// Inter-IC Sound Interface
	I2S = (*I2S_Type)(unsafe.Pointer(uintptr(0x43002800)))

	// Main Clock
	MCLK = (*MCLK_Type)(unsafe.Pointer(uintptr(0x40000800)))

	// Non-Volatile Memory Controller
	NVMCTRL = (*NVMCTRL_Type)(unsafe.Pointer(uintptr(0x41004000)))

	// Oscillators Control
	OSCCTRL = (*OSCCTRL_Type)(unsafe.Pointer(uintptr(0x40001000)))

	// 32kHz Oscillators Control
	OSC32KCTRL = (*OSC32KCTRL_Type)(unsafe.Pointer(uintptr(0x40001400)))

	// Peripheral Access Controller
	PAC = (*PAC_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// Parallel Capture Controller
	PCC = (*PCC_Type)(unsafe.Pointer(uintptr(0x43002c00)))

	// Quadrature Decodeur
	PDEC = (*PDEC_Type)(unsafe.Pointer(uintptr(0x42001c00)))

	// Power Manager
	PM = (*PM_Type)(unsafe.Pointer(uintptr(0x40000400)))

	// Port Module
	PORT = (*PORT_Type)(unsafe.Pointer(uintptr(0x41008000)))

	// Quad SPI interface
	QSPI = (*QSPI_Type)(unsafe.Pointer(uintptr(0x42003400)))

	// RAM ECC
	RAMECC = (*RAMECC_Type)(unsafe.Pointer(uintptr(0x41020000)))

	// Reset Controller
	RSTC = (*RSTC_Type)(unsafe.Pointer(uintptr(0x40000c00)))

	// Real-Time Counter
	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x40002400)))

	// Real-Time Counter - MODE0
	RTC_MODE0 = (*RTC_MODE0_Type)(unsafe.Pointer(uintptr(0x40002400)))

	// Real-Time Counter - MODE1
	RTC_MODE1 = (*RTC_MODE1_Type)(unsafe.Pointer(uintptr(0x40002400)))

	// Real-Time Counter - MODE2
	RTC_MODE2 = (*RTC_MODE2_Type)(unsafe.Pointer(uintptr(0x40002400)))

	// SD/MMC Host Controller
	SDHC0 = (*SDHC_Type)(unsafe.Pointer(uintptr(0x45000000)))

	// Serial Communication Interface
	SERCOM0 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Serial Communication Interface - I2CM
	SERCOM0_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Serial Communication Interface - I2CS
	SERCOM0_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Serial Communication Interface - SPIS
	SERCOM0_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Serial Communication Interface - SPIM
	SERCOM0_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Serial Communication Interface - USART_EXT
	SERCOM0_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Serial Communication Interface - USART_INT
	SERCOM0_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Supply Controller
	SUPC = (*SUPC_Type)(unsafe.Pointer(uintptr(0x40001800)))

	// Basic Timer Counter
	TC0 = (*TC_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// Basic Timer Counter - COUNT8
	TC0_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// Basic Timer Counter - COUNT16
	TC0_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// Basic Timer Counter - COUNT32
	TC0_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// Timer Counter Control
	TCC0 = (*TCC_Type)(unsafe.Pointer(uintptr(0x41016000)))

	// True Random Generator
	TRNG = (*TRNG_Type)(unsafe.Pointer(uintptr(0x42002800)))

	// Universal Serial Bus
	USB = (*USB_Type)(unsafe.Pointer(uintptr(0x41000000)))

	// Universal Serial Bus - DEVICE
	USB_DEVICE = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x41000000)))

	// Universal Serial Bus - HOST
	USB_HOST = (*USB_HOST_Type)(unsafe.Pointer(uintptr(0x41000000)))

	// Watchdog Timer
	WDT = (*WDT_Type)(unsafe.Pointer(uintptr(0x40002000)))

	// Core Debug Register
	CoreDebug = (*CoreDebug_Type)(unsafe.Pointer(uintptr(0xe000edf0)))

	// Data Watchpoint and Trace Register
	DWT = (*DWT_Type)(unsafe.Pointer(uintptr(0xe0001000)))

	// Embedded Trace Macrocell
	ETM = (*ETM_Type)(unsafe.Pointer(uintptr(0xe0041000)))

	// Floating Point Unit
	FPU = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ef30)))

	// Instrumentation Trace Macrocell
	ITM = (*ITM_Type)(unsafe.Pointer(uintptr(0xe0000000)))

	// Memory Protection Unit
	MPU = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90)))

	// Nested Vectored Interrupt Controller
	NVIC = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000e100)))

	// System timer
	SysTick = (*SysTick_Type)(unsafe.Pointer(uintptr(0xe000e010)))

	// System Control Registers
	SystemControl = (*SystemControl_Type)(unsafe.Pointer(uintptr(0xe000e000)))

	// Trace Port Interface Register
	TPI = (*TPI_Type)(unsafe.Pointer(uintptr(0xe0040000)))

	// Analog Digital Converter
	ADC1 = (*ADC_Type)(unsafe.Pointer(uintptr(0x43002000)))

	// Control Area Network
	CAN1 = (*CAN_Type)(unsafe.Pointer(uintptr(0x42000400)))

	// SD/MMC Host Controller
	SDHC1 = (*SDHC_Type)(unsafe.Pointer(uintptr(0x46000000)))

	// Serial Communication Interface
	SERCOM1 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Serial Communication Interface - I2CM
	SERCOM1_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Serial Communication Interface - I2CS
	SERCOM1_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Serial Communication Interface - SPIS
	SERCOM1_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Serial Communication Interface - SPIM
	SERCOM1_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Serial Communication Interface - USART_EXT
	SERCOM1_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Serial Communication Interface - USART_INT
	SERCOM1_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Serial Communication Interface
	SERCOM2 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x41012000)))

	// Serial Communication Interface - I2CM
	SERCOM2_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x41012000)))

	// Serial Communication Interface - I2CS
	SERCOM2_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x41012000)))

	// Serial Communication Interface - SPIS
	SERCOM2_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x41012000)))

	// Serial Communication Interface - SPIM
	SERCOM2_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x41012000)))

	// Serial Communication Interface - USART_EXT
	SERCOM2_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x41012000)))

	// Serial Communication Interface - USART_INT
	SERCOM2_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x41012000)))

	// Serial Communication Interface
	SERCOM3 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x41014000)))

	// Serial Communication Interface - I2CM
	SERCOM3_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x41014000)))

	// Serial Communication Interface - I2CS
	SERCOM3_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x41014000)))

	// Serial Communication Interface - SPIS
	SERCOM3_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x41014000)))

	// Serial Communication Interface - SPIM
	SERCOM3_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x41014000)))

	// Serial Communication Interface - USART_EXT
	SERCOM3_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x41014000)))

	// Serial Communication Interface - USART_INT
	SERCOM3_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x41014000)))

	// Serial Communication Interface
	SERCOM4 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000000)))

	// Serial Communication Interface - I2CM
	SERCOM4_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000000)))

	// Serial Communication Interface - I2CS
	SERCOM4_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000000)))

	// Serial Communication Interface - SPIS
	SERCOM4_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000000)))

	// Serial Communication Interface - SPIM
	SERCOM4_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000000)))

	// Serial Communication Interface - USART_EXT
	SERCOM4_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000000)))

	// Serial Communication Interface - USART_INT
	SERCOM4_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000000)))

	// Serial Communication Interface
	SERCOM5 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000400)))

	// Serial Communication Interface - I2CM
	SERCOM5_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000400)))

	// Serial Communication Interface - I2CS
	SERCOM5_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000400)))

	// Serial Communication Interface - SPIS
	SERCOM5_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000400)))

	// Serial Communication Interface - SPIM
	SERCOM5_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000400)))

	// Serial Communication Interface - USART_EXT
	SERCOM5_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000400)))

	// Serial Communication Interface - USART_INT
	SERCOM5_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000400)))

	// Serial Communication Interface
	SERCOM6 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000800)))

	// Serial Communication Interface - I2CM
	SERCOM6_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000800)))

	// Serial Communication Interface - I2CS
	SERCOM6_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000800)))

	// Serial Communication Interface - SPIS
	SERCOM6_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000800)))

	// Serial Communication Interface - SPIM
	SERCOM6_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000800)))

	// Serial Communication Interface - USART_EXT
	SERCOM6_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000800)))

	// Serial Communication Interface - USART_INT
	SERCOM6_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000800)))

	// Serial Communication Interface
	SERCOM7 = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000c00)))

	// Serial Communication Interface - I2CM
	SERCOM7_I2CM = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000c00)))

	// Serial Communication Interface - I2CS
	SERCOM7_I2CS = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000c00)))

	// Serial Communication Interface - SPIS
	SERCOM7_SPIS = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000c00)))

	// Serial Communication Interface - SPIM
	SERCOM7_SPIM = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000c00)))

	// Serial Communication Interface - USART_EXT
	SERCOM7_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000c00)))

	// Serial Communication Interface - USART_INT
	SERCOM7_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000c00)))

	// Basic Timer Counter
	TC1 = (*TC_Type)(unsafe.Pointer(uintptr(0x40003c00)))

	// Basic Timer Counter - COUNT8
	TC1_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x40003c00)))

	// Basic Timer Counter - COUNT16
	TC1_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x40003c00)))

	// Basic Timer Counter - COUNT32
	TC1_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x40003c00)))

	// Basic Timer Counter
	TC2 = (*TC_Type)(unsafe.Pointer(uintptr(0x4101a000)))

	// Basic Timer Counter - COUNT8
	TC2_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x4101a000)))

	// Basic Timer Counter - COUNT16
	TC2_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x4101a000)))

	// Basic Timer Counter - COUNT32
	TC2_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x4101a000)))

	// Basic Timer Counter
	TC3 = (*TC_Type)(unsafe.Pointer(uintptr(0x4101c000)))

	// Basic Timer Counter - COUNT8
	TC3_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x4101c000)))

	// Basic Timer Counter - COUNT16
	TC3_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x4101c000)))

	// Basic Timer Counter - COUNT32
	TC3_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x4101c000)))

	// Basic Timer Counter
	TC4 = (*TC_Type)(unsafe.Pointer(uintptr(0x42001400)))

	// Basic Timer Counter - COUNT8
	TC4_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x42001400)))

	// Basic Timer Counter - COUNT16
	TC4_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x42001400)))

	// Basic Timer Counter - COUNT32
	TC4_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x42001400)))

	// Basic Timer Counter
	TC5 = (*TC_Type)(unsafe.Pointer(uintptr(0x42001800)))

	// Basic Timer Counter - COUNT8
	TC5_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x42001800)))

	// Basic Timer Counter - COUNT16
	TC5_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x42001800)))

	// Basic Timer Counter - COUNT32
	TC5_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x42001800)))

	// Basic Timer Counter
	TC6 = (*TC_Type)(unsafe.Pointer(uintptr(0x43001400)))

	// Basic Timer Counter - COUNT8
	TC6_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x43001400)))

	// Basic Timer Counter - COUNT16
	TC6_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x43001400)))

	// Basic Timer Counter - COUNT32
	TC6_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x43001400)))

	// Basic Timer Counter
	TC7 = (*TC_Type)(unsafe.Pointer(uintptr(0x43001800)))

	// Basic Timer Counter - COUNT8
	TC7_COUNT8 = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x43001800)))

	// Basic Timer Counter - COUNT16
	TC7_COUNT16 = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x43001800)))

	// Basic Timer Counter - COUNT32
	TC7_COUNT32 = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x43001800)))

	// Timer Counter Control
	TCC1 = (*TCC_Type)(unsafe.Pointer(uintptr(0x41018000)))

	// Timer Counter Control
	TCC2 = (*TCC_Type)(unsafe.Pointer(uintptr(0x42000c00)))

	// Timer Counter Control
	TCC3 = (*TCC_Type)(unsafe.Pointer(uintptr(0x42001000)))

	// Timer Counter Control
	TCC4 = (*TCC_Type)(unsafe.Pointer(uintptr(0x43001000)))
)

// Analog Comparators
type AC_Type struct {
	CTRLA    volatile.Register8  // 0x0
	CTRLB    volatile.Register8  // 0x1
	EVCTRL   volatile.Register16 // 0x2
	INTENCLR volatile.Register8  // 0x4
	INTENSET volatile.Register8  // 0x5
	INTFLAG  volatile.Register8  // 0x6
	STATUSA  volatile.Register8  // 0x7
	STATUSB  volatile.Register8  // 0x8
	DBGCTRL  volatile.Register8  // 0x9
	WINCTRL  volatile.Register8  // 0xA
	_        byte
	SCALER   [2]volatile.Register8 // 0xC
	_        [2]byte
	COMPCTRL [2]volatile.Register32 // 0x10
	_        [8]byte
	SYNCBUSY volatile.Register32 // 0x20
	CALIB    volatile.Register16 // 0x24
}

// Analog Digital Converter
type ADC_Type struct {
	CTRLA      volatile.Register16 // 0x0
	EVCTRL     volatile.Register8  // 0x2
	DBGCTRL    volatile.Register8  // 0x3
	INPUTCTRL  volatile.Register16 // 0x4
	CTRLB      volatile.Register16 // 0x6
	REFCTRL    volatile.Register8  // 0x8
	_          byte
	AVGCTRL    volatile.Register8  // 0xA
	SAMPCTRL   volatile.Register8  // 0xB
	WINLT      volatile.Register16 // 0xC
	WINUT      volatile.Register16 // 0xE
	GAINCORR   volatile.Register16 // 0x10
	OFFSETCORR volatile.Register16 // 0x12
	SWTRIG     volatile.Register8  // 0x14
	_          [23]byte
	INTENCLR   volatile.Register8  // 0x2C
	INTENSET   volatile.Register8  // 0x2D
	INTFLAG    volatile.Register8  // 0x2E
	STATUS     volatile.Register8  // 0x2F
	SYNCBUSY   volatile.Register32 // 0x30
	DSEQDATA   volatile.Register32 // 0x34
	DSEQCTRL   volatile.Register32 // 0x38
	DSEQSTAT   volatile.Register32 // 0x3C
	RESULT     volatile.Register16 // 0x40
	_          [2]byte
	RESS       volatile.Register16 // 0x44
	_          [2]byte
	CALIB      volatile.Register16 // 0x48
}

// Advanced Encryption Standard
type AES_Type struct {
	CTRLA      volatile.Register32 // 0x0
	CTRLB      volatile.Register8  // 0x4
	INTENCLR   volatile.Register8  // 0x5
	INTENSET   volatile.Register8  // 0x6
	INTFLAG    volatile.Register8  // 0x7
	DATABUFPTR volatile.Register8  // 0x8
	DBGCTRL    volatile.Register8  // 0x9
	_          [2]byte
	KEYWORD    [8]volatile.Register32 // 0xC
	_          [12]byte
	INDATA     volatile.Register32    // 0x38
	INTVECTV   [4]volatile.Register32 // 0x3C
	_          [16]byte
	HASHKEY    [4]volatile.Register32 // 0x5C
	GHASH      [4]volatile.Register32 // 0x6C
	_          [4]byte
	CIPLEN     volatile.Register32 // 0x80
	RANDSEED   volatile.Register32 // 0x84
}

// Control Area Network
type CAN_Type struct {
	CREL   volatile.Register32 // 0x0
	ENDN   volatile.Register32 // 0x4
	MRCFG  volatile.Register32 // 0x8
	DBTP   volatile.Register32 // 0xC
	TEST   volatile.Register32 // 0x10
	RWD    volatile.Register32 // 0x14
	CCCR   volatile.Register32 // 0x18
	NBTP   volatile.Register32 // 0x1C
	TSCC   volatile.Register32 // 0x20
	TSCV   volatile.Register32 // 0x24
	TOCC   volatile.Register32 // 0x28
	TOCV   volatile.Register32 // 0x2C
	_      [16]byte
	ECR    volatile.Register32 // 0x40
	PSR    volatile.Register32 // 0x44
	TDCR   volatile.Register32 // 0x48
	_      [4]byte
	IR     volatile.Register32 // 0x50
	IE     volatile.Register32 // 0x54
	ILS    volatile.Register32 // 0x58
	ILE    volatile.Register32 // 0x5C
	_      [32]byte
	GFC    volatile.Register32 // 0x80
	SIDFC  volatile.Register32 // 0x84
	XIDFC  volatile.Register32 // 0x88
	_      [4]byte
	XIDAM  volatile.Register32 // 0x90
	HPMS   volatile.Register32 // 0x94
	NDAT1  volatile.Register32 // 0x98
	NDAT2  volatile.Register32 // 0x9C
	RXF0C  volatile.Register32 // 0xA0
	RXF0S  volatile.Register32 // 0xA4
	RXF0A  volatile.Register32 // 0xA8
	RXBC   volatile.Register32 // 0xAC
	RXF1C  volatile.Register32 // 0xB0
	RXF1S  volatile.Register32 // 0xB4
	RXF1A  volatile.Register32 // 0xB8
	RXESC  volatile.Register32 // 0xBC
	TXBC   volatile.Register32 // 0xC0
	TXFQS  volatile.Register32 // 0xC4
	TXESC  volatile.Register32 // 0xC8
	TXBRP  volatile.Register32 // 0xCC
	TXBAR  volatile.Register32 // 0xD0
	TXBCR  volatile.Register32 // 0xD4
	TXBTO  volatile.Register32 // 0xD8
	TXBCF  volatile.Register32 // 0xDC
	TXBTIE volatile.Register32 // 0xE0
	TXBCIE volatile.Register32 // 0xE4
	_      [8]byte
	TXEFC  volatile.Register32 // 0xF0
	TXEFS  volatile.Register32 // 0xF4
	TXEFA  volatile.Register32 // 0xF8
}

// Configurable Custom Logic
type CCL_Type struct {
	CTRL    volatile.Register8 // 0x0
	_       [3]byte
	SEQCTRL [2]volatile.Register8 // 0x4
	_       [2]byte
	LUTCTRL [4]volatile.Register32 // 0x8
}

// Cortex M Cache Controller
type CMCC_Type struct {
	TYPE   volatile.Register32 // 0x0
	CFG    volatile.Register32 // 0x4
	CTRL   volatile.Register32 // 0x8
	SR     volatile.Register32 // 0xC
	LCKWAY volatile.Register32 // 0x10
	_      [12]byte
	MAINT0 volatile.Register32 // 0x20
	MAINT1 volatile.Register32 // 0x24
	MCFG   volatile.Register32 // 0x28
	MEN    volatile.Register32 // 0x2C
	MCTRL  volatile.Register32 // 0x30
	MSR    volatile.Register32 // 0x34
}

// Digital-to-Analog Converter
type DAC_Type struct {
	CTRLA    volatile.Register8 // 0x0
	CTRLB    volatile.Register8 // 0x1
	EVCTRL   volatile.Register8 // 0x2
	_        byte
	INTENCLR volatile.Register8     // 0x4
	INTENSET volatile.Register8     // 0x5
	INTFLAG  volatile.Register8     // 0x6
	STATUS   volatile.Register8     // 0x7
	SYNCBUSY volatile.Register32    // 0x8
	DACCTRL  [2]volatile.Register16 // 0xC
	DATA     [2]volatile.Register16 // 0x10
	DATABUF  [2]volatile.Register16 // 0x14
	DBGCTRL  volatile.Register8     // 0x18
	_        [3]byte
	RESULT   [2]volatile.Register16 // 0x1C
}

// Direct Memory Access Controller
type DMAC_Type struct {
	CTRL       volatile.Register16 // 0x0
	CRCCTRL    volatile.Register16 // 0x2
	CRCDATAIN  volatile.Register32 // 0x4
	CRCCHKSUM  volatile.Register32 // 0x8
	CRCSTATUS  volatile.Register8  // 0xC
	DBGCTRL    volatile.Register8  // 0xD
	_          [2]byte
	SWTRIGCTRL volatile.Register32 // 0x10
	PRICTRL0   volatile.Register32 // 0x14
	_          [8]byte
	INTPEND    volatile.Register16 // 0x20
	_          [2]byte
	INTSTATUS  volatile.Register32 // 0x24
	BUSYCH     volatile.Register32 // 0x28
	PENDCH     volatile.Register32 // 0x2C
	ACTIVE     volatile.Register32 // 0x30
	BASEADDR   volatile.Register32 // 0x34
	WRBADDR    volatile.Register32 // 0x38
	_          [4]byte
	CHANNEL    [32]struct {
		CHCTRLA    volatile.Register32
		CHCTRLB    volatile.Register8
		CHPRILVL   volatile.Register8
		CHEVCTRL   volatile.Register8
		_          [5]byte
		CHINTENCLR volatile.Register8
		CHINTENSET volatile.Register8
		CHINTFLAG  volatile.Register8
		CHSTATUS   volatile.Register8
	} // 0x40
}

// Device Service Unit
type DSU_Type struct {
	CTRL    volatile.Register8 // 0x0
	STATUSA volatile.Register8 // 0x1
	STATUSB volatile.Register8 // 0x2
	_       byte
	ADDR    volatile.Register32    // 0x4
	LENGTH  volatile.Register32    // 0x8
	DATA    volatile.Register32    // 0xC
	DCC     [2]volatile.Register32 // 0x10
	DID     volatile.Register32    // 0x18
	CFG     volatile.Register32    // 0x1C
	_       [208]byte
	DCFG    [2]volatile.Register32 // 0xF0
	_       [3848]byte
	ENTRY0  volatile.Register32 // 0x1000
	ENTRY1  volatile.Register32 // 0x1004
	END     volatile.Register32 // 0x1008
	_       [4032]byte
	MEMTYPE volatile.Register32 // 0x1FCC
	PID4    volatile.Register32 // 0x1FD0
	PID5    volatile.Register32 // 0x1FD4
	PID6    volatile.Register32 // 0x1FD8
	PID7    volatile.Register32 // 0x1FDC
	PID0    volatile.Register32 // 0x1FE0
	PID1    volatile.Register32 // 0x1FE4
	PID2    volatile.Register32 // 0x1FE8
	PID3    volatile.Register32 // 0x1FEC
	CID0    volatile.Register32 // 0x1FF0
	CID1    volatile.Register32 // 0x1FF4
	CID2    volatile.Register32 // 0x1FF8
	CID3    volatile.Register32 // 0x1FFC
}

// External Interrupt Controller
type EIC_Type struct {
	CTRLA      volatile.Register8     // 0x0
	NMICTRL    volatile.Register8     // 0x1
	NMIFLAG    volatile.Register16    // 0x2
	SYNCBUSY   volatile.Register32    // 0x4
	EVCTRL     volatile.Register32    // 0x8
	INTENCLR   volatile.Register32    // 0xC
	INTENSET   volatile.Register32    // 0x10
	INTFLAG    volatile.Register32    // 0x14
	ASYNCH     volatile.Register32    // 0x18
	CONFIG     [2]volatile.Register32 // 0x1C
	_          [12]byte
	DEBOUNCEN  volatile.Register32 // 0x30
	DPRESCALER volatile.Register32 // 0x34
	PINSTATE   volatile.Register32 // 0x38
}

// Event System Interface
type EVSYS_Type struct {
	CTRLA     volatile.Register8 // 0x0
	_         [3]byte
	SWEVT     volatile.Register32 // 0x4
	PRICTRL   volatile.Register8  // 0x8
	_         [7]byte
	INTPEND   volatile.Register16 // 0x10
	_         [2]byte
	INTSTATUS volatile.Register32 // 0x14
	BUSYCH    volatile.Register32 // 0x18
	READYUSR  volatile.Register32 // 0x1C
	CHANNEL   [32]struct {
		CHANNEL    volatile.Register32
		CHINTENCLR volatile.Register8
		CHINTENSET volatile.Register8
		CHINTFLAG  volatile.Register8
		CHSTATUS   volatile.Register8
	} // 0x20
	USER [67]volatile.Register32 // 0x120
}

// Frequency Meter
type FREQM_Type struct {
	CTRLA    volatile.Register8  // 0x0
	CTRLB    volatile.Register8  // 0x1
	CFGA     volatile.Register16 // 0x2
	_        [4]byte
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	SYNCBUSY volatile.Register32 // 0xC
	VALUE    volatile.Register32 // 0x10
}

// Generic Clock Generator
type GCLK_Type struct {
	CTRLA    volatile.Register8 // 0x0
	_        [3]byte
	SYNCBUSY volatile.Register32 // 0x4
	_        [24]byte
	GENCTRL  [12]volatile.Register32 // 0x20
	_        [48]byte
	PCHCTRL  [48]volatile.Register32 // 0x80
}

// Ethernet MAC
type GMAC_Type struct {
	NCR   volatile.Register32 // 0x0
	NCFGR volatile.Register32 // 0x4
	NSR   volatile.Register32 // 0x8
	UR    volatile.Register32 // 0xC
	DCFGR volatile.Register32 // 0x10
	TSR   volatile.Register32 // 0x14
	RBQB  volatile.Register32 // 0x18
	TBQB  volatile.Register32 // 0x1C
	RSR   volatile.Register32 // 0x20
	ISR   volatile.Register32 // 0x24
	IER   volatile.Register32 // 0x28
	IDR   volatile.Register32 // 0x2C
	IMR   volatile.Register32 // 0x30
	MAN   volatile.Register32 // 0x34
	RPQ   volatile.Register32 // 0x38
	TPQ   volatile.Register32 // 0x3C
	TPSF  volatile.Register32 // 0x40
	RPSF  volatile.Register32 // 0x44
	RJFML volatile.Register32 // 0x48
	_     [52]byte
	HRB   volatile.Register32 // 0x80
	HRT   volatile.Register32 // 0x84
	SA    [4]struct {
		SAB volatile.Register32
		SAT volatile.Register32
	} // 0x88
	TIDM      [4]volatile.Register32 // 0xA8
	WOL       volatile.Register32    // 0xB8
	IPGS      volatile.Register32    // 0xBC
	SVLAN     volatile.Register32    // 0xC0
	TPFCP     volatile.Register32    // 0xC4
	SAMB1     volatile.Register32    // 0xC8
	SAMT1     volatile.Register32    // 0xCC
	_         [12]byte
	NSC       volatile.Register32 // 0xDC
	SCL       volatile.Register32 // 0xE0
	SCH       volatile.Register32 // 0xE4
	EFTSH     volatile.Register32 // 0xE8
	EFRSH     volatile.Register32 // 0xEC
	PEFTSH    volatile.Register32 // 0xF0
	PEFRSH    volatile.Register32 // 0xF4
	_         [8]byte
	OTLO      volatile.Register32 // 0x100
	OTHI      volatile.Register32 // 0x104
	FT        volatile.Register32 // 0x108
	BCFT      volatile.Register32 // 0x10C
	MFT       volatile.Register32 // 0x110
	PFT       volatile.Register32 // 0x114
	BFT64     volatile.Register32 // 0x118
	TBFT127   volatile.Register32 // 0x11C
	TBFT255   volatile.Register32 // 0x120
	TBFT511   volatile.Register32 // 0x124
	TBFT1023  volatile.Register32 // 0x128
	TBFT1518  volatile.Register32 // 0x12C
	GTBFT1518 volatile.Register32 // 0x130
	TUR       volatile.Register32 // 0x134
	SCF       volatile.Register32 // 0x138
	MCF       volatile.Register32 // 0x13C
	EC        volatile.Register32 // 0x140
	LC        volatile.Register32 // 0x144
	DTF       volatile.Register32 // 0x148
	CSE       volatile.Register32 // 0x14C
	ORLO      volatile.Register32 // 0x150
	ORHI      volatile.Register32 // 0x154
	FR        volatile.Register32 // 0x158
	BCFR      volatile.Register32 // 0x15C
	MFR       volatile.Register32 // 0x160
	PFR       volatile.Register32 // 0x164
	BFR64     volatile.Register32 // 0x168
	TBFR127   volatile.Register32 // 0x16C
	TBFR255   volatile.Register32 // 0x170
	TBFR511   volatile.Register32 // 0x174
	TBFR1023  volatile.Register32 // 0x178
	TBFR1518  volatile.Register32 // 0x17C
	TMXBFR    volatile.Register32 // 0x180
	UFR       volatile.Register32 // 0x184
	OFR       volatile.Register32 // 0x188
	JR        volatile.Register32 // 0x18C
	FCSE      volatile.Register32 // 0x190
	LFFE      volatile.Register32 // 0x194
	RSE       volatile.Register32 // 0x198
	AE        volatile.Register32 // 0x19C
	RRE       volatile.Register32 // 0x1A0
	ROE       volatile.Register32 // 0x1A4
	IHCE      volatile.Register32 // 0x1A8
	TCE       volatile.Register32 // 0x1AC
	UCE       volatile.Register32 // 0x1B0
	_         [8]byte
	TISUBN    volatile.Register32 // 0x1BC
	TSH       volatile.Register32 // 0x1C0
	_         [4]byte
	TSSSL     volatile.Register32 // 0x1C8
	TSSN      volatile.Register32 // 0x1CC
	TSL       volatile.Register32 // 0x1D0
	TN        volatile.Register32 // 0x1D4
	TA        volatile.Register32 // 0x1D8
	TI        volatile.Register32 // 0x1DC
	EFTSL     volatile.Register32 // 0x1E0
	EFTN      volatile.Register32 // 0x1E4
	EFRSL     volatile.Register32 // 0x1E8
	EFRN      volatile.Register32 // 0x1EC
	PEFTSL    volatile.Register32 // 0x1F0
	PEFTN     volatile.Register32 // 0x1F4
	PEFRSL    volatile.Register32 // 0x1F8
	PEFRN     volatile.Register32 // 0x1FC
	_         [112]byte
	RLPITR    volatile.Register32 // 0x270
	RLPITI    volatile.Register32 // 0x274
	TLPITR    volatile.Register32 // 0x278
	TLPITI    volatile.Register32 // 0x27C
}

// HSB Matrix
type HMATRIXB_Type struct {
	_   [128]byte
	PRS [16]struct {
		PRAS volatile.Register32
		PRBS volatile.Register32
	} // 0x80
}

// Integrity Check Monitor
type ICM_Type struct {
	CFG    volatile.Register32 // 0x0
	CTRL   volatile.Register32 // 0x4
	SR     volatile.Register32 // 0x8
	_      [4]byte
	IER    volatile.Register32 // 0x10
	IDR    volatile.Register32 // 0x14
	IMR    volatile.Register32 // 0x18
	ISR    volatile.Register32 // 0x1C
	UASR   volatile.Register32 // 0x20
	_      [12]byte
	DSCR   volatile.Register32    // 0x30
	HASH   volatile.Register32    // 0x34
	UIHVAL [8]volatile.Register32 // 0x38
}

// Inter-IC Sound Interface
type I2S_Type struct {
	CTRLA    volatile.Register8 // 0x0
	_        [3]byte
	CLKCTRL  [2]volatile.Register32 // 0x4
	INTENCLR volatile.Register16    // 0xC
	_        [2]byte
	INTENSET volatile.Register16 // 0x10
	_        [2]byte
	INTFLAG  volatile.Register16 // 0x14
	_        [2]byte
	SYNCBUSY volatile.Register16 // 0x18
	_        [6]byte
	TXCTRL   volatile.Register32 // 0x20
	RXCTRL   volatile.Register32 // 0x24
	_        [8]byte
	TXDATA   volatile.Register32 // 0x30
	RXDATA   volatile.Register32 // 0x34
}

// Main Clock
type MCLK_Type struct {
	_        byte
	INTENCLR volatile.Register8 // 0x1
	INTENSET volatile.Register8 // 0x2
	INTFLAG  volatile.Register8 // 0x3
	HSDIV    volatile.Register8 // 0x4
	CPUDIV   volatile.Register8 // 0x5
	_        [10]byte
	AHBMASK  volatile.Register32 // 0x10
	APBAMASK volatile.Register32 // 0x14
	APBBMASK volatile.Register32 // 0x18
	APBCMASK volatile.Register32 // 0x1C
	APBDMASK volatile.Register32 // 0x20
}

// Non-Volatile Memory Controller
type NVMCTRL_Type struct {
	CTRLA    volatile.Register16 // 0x0
	_        [2]byte
	CTRLB    volatile.Register16 // 0x4
	_        [2]byte
	PARAM    volatile.Register32    // 0x8
	INTENCLR volatile.Register16    // 0xC
	INTENSET volatile.Register16    // 0xE
	INTFLAG  volatile.Register16    // 0x10
	STATUS   volatile.Register16    // 0x12
	ADDR     volatile.Register32    // 0x14
	RUNLOCK  volatile.Register32    // 0x18
	PBLDATA  [2]volatile.Register32 // 0x1C
	ECCERR   volatile.Register32    // 0x24
	DBGCTRL  volatile.Register8     // 0x28
	_        byte
	SEECFG   volatile.Register8 // 0x2A
	_        byte
	SEESTAT  volatile.Register32 // 0x2C
}

// Oscillators Control
type OSCCTRL_Type struct {
	EVCTRL    volatile.Register8 // 0x0
	_         [3]byte
	INTENCLR  volatile.Register32    // 0x4
	INTENSET  volatile.Register32    // 0x8
	INTFLAG   volatile.Register32    // 0xC
	STATUS    volatile.Register32    // 0x10
	XOSCCTRL  [2]volatile.Register32 // 0x14
	DFLLCTRLA volatile.Register8     // 0x1C
	_         [3]byte
	DFLLCTRLB volatile.Register8 // 0x20
	_         [3]byte
	DFLLVAL   volatile.Register32 // 0x24
	DFLLMUL   volatile.Register32 // 0x28
	DFLLSYNC  volatile.Register8  // 0x2C
	_         [3]byte
	DPLL      [2]struct {
		DPLLCTRLA    volatile.Register8
		_            [3]byte
		DPLLRATIO    volatile.Register32
		DPLLCTRLB    volatile.Register32
		DPLLSYNCBUSY volatile.Register32
		DPLLSTATUS   volatile.Register32
	} // 0x30
}

// 32kHz Oscillators Control
type OSC32KCTRL_Type struct {
	INTENCLR  volatile.Register32 // 0x0
	INTENSET  volatile.Register32 // 0x4
	INTFLAG   volatile.Register32 // 0x8
	STATUS    volatile.Register32 // 0xC
	RTCCTRL   volatile.Register8  // 0x10
	_         [3]byte
	XOSC32K   volatile.Register16 // 0x14
	CFDCTRL   volatile.Register8  // 0x16
	EVCTRL    volatile.Register8  // 0x17
	_         [4]byte
	OSCULP32K volatile.Register32 // 0x1C
}

// Peripheral Access Controller
type PAC_Type struct {
	WRCTRL     volatile.Register32 // 0x0
	EVCTRL     volatile.Register8  // 0x4
	_          [3]byte
	INTENCLR   volatile.Register8 // 0x8
	INTENSET   volatile.Register8 // 0x9
	_          [6]byte
	INTFLAGAHB volatile.Register32 // 0x10
	INTFLAGA   volatile.Register32 // 0x14
	INTFLAGB   volatile.Register32 // 0x18
	INTFLAGC   volatile.Register32 // 0x1C
	INTFLAGD   volatile.Register32 // 0x20
	_          [16]byte
	STATUSA    volatile.Register32 // 0x34
	STATUSB    volatile.Register32 // 0x38
	STATUSC    volatile.Register32 // 0x3C
	STATUSD    volatile.Register32 // 0x40
}

// Parallel Capture Controller
type PCC_Type struct {
	MR   volatile.Register32 // 0x0
	IER  volatile.Register32 // 0x4
	IDR  volatile.Register32 // 0x8
	IMR  volatile.Register32 // 0xC
	ISR  volatile.Register32 // 0x10
	RHR  volatile.Register32 // 0x14
	_    [200]byte
	WPMR volatile.Register32 // 0xE0
	WPSR volatile.Register32 // 0xE4
}

// Quadrature Decodeur
type PDEC_Type struct {
	CTRLA     volatile.Register32 // 0x0
	CTRLBCLR  volatile.Register8  // 0x4
	CTRLBSET  volatile.Register8  // 0x5
	EVCTRL    volatile.Register16 // 0x6
	INTENCLR  volatile.Register8  // 0x8
	INTENSET  volatile.Register8  // 0x9
	INTFLAG   volatile.Register8  // 0xA
	_         byte
	STATUS    volatile.Register16 // 0xC
	_         byte
	DBGCTRL   volatile.Register8  // 0xF
	SYNCBUSY  volatile.Register32 // 0x10
	PRESC     volatile.Register8  // 0x14
	FILTER    volatile.Register8  // 0x15
	_         [2]byte
	PRESCBUF  volatile.Register8 // 0x18
	FILTERBUF volatile.Register8 // 0x19
	_         [2]byte
	COUNT     volatile.Register32    // 0x1C
	CC        [2]volatile.Register32 // 0x20
	_         [8]byte
	CCBUF     [2]volatile.Register32 // 0x30
}

// Power Manager
type PM_Type struct {
	CTRLA    volatile.Register8 // 0x0
	SLEEPCFG volatile.Register8 // 0x1
	_        [2]byte
	INTENCLR volatile.Register8 // 0x4
	INTENSET volatile.Register8 // 0x5
	INTFLAG  volatile.Register8 // 0x6
	_        byte
	STDBYCFG volatile.Register8 // 0x8
	HIBCFG   volatile.Register8 // 0x9
	BKUPCFG  volatile.Register8 // 0xA
	_        [7]byte
	PWSAKDLY volatile.Register8 // 0x12
}

// Port Module
type PORT_Type struct {
	GROUP [4]struct {
		DIR      volatile.Register32
		DIRCLR   volatile.Register32
		DIRSET   volatile.Register32
		DIRTGL   volatile.Register32
		OUT      volatile.Register32
		OUTCLR   volatile.Register32
		OUTSET   volatile.Register32
		OUTTGL   volatile.Register32
		IN       volatile.Register32
		CTRL     volatile.Register32
		WRCONFIG volatile.Register32
		EVCTRL   volatile.Register32
		PMUX     [16]volatile.Register8
		PINCFG   [32]volatile.Register8
		_        [32]byte
	} // 0x0
}

// Quad SPI interface
type QSPI_Type struct {
	CTRLA      volatile.Register32 // 0x0
	CTRLB      volatile.Register32 // 0x4
	BAUD       volatile.Register32 // 0x8
	RXDATA     volatile.Register32 // 0xC
	TXDATA     volatile.Register32 // 0x10
	INTENCLR   volatile.Register32 // 0x14
	INTENSET   volatile.Register32 // 0x18
	INTFLAG    volatile.Register32 // 0x1C
	STATUS     volatile.Register32 // 0x20
	_          [12]byte
	INSTRADDR  volatile.Register32 // 0x30
	INSTRCTRL  volatile.Register32 // 0x34
	INSTRFRAME volatile.Register32 // 0x38
	_          [4]byte
	SCRAMBCTRL volatile.Register32 // 0x40
	SCRAMBKEY  volatile.Register32 // 0x44
}

// RAM ECC
type RAMECC_Type struct {
	INTENCLR volatile.Register8  // 0x0
	INTENSET volatile.Register8  // 0x1
	INTFLAG  volatile.Register8  // 0x2
	STATUS   volatile.Register8  // 0x3
	ERRADDR  volatile.Register32 // 0x4
	_        [7]byte
	DBGCTRL  volatile.Register8 // 0xF
}

// Reset Controller
type RSTC_Type struct {
	RCAUSE   volatile.Register8 // 0x0
	_        byte
	BKUPEXIT volatile.Register8 // 0x2
}

// Real-Time Counter
type RTC_Type struct {
}

// Real-Time Counter - MODE0
type RTC_MODE0_Type struct {
	CTRLA     volatile.Register16 // 0x0
	CTRLB     volatile.Register16 // 0x2
	EVCTRL    volatile.Register32 // 0x4
	INTENCLR  volatile.Register16 // 0x8
	INTENSET  volatile.Register16 // 0xA
	INTFLAG   volatile.Register16 // 0xC
	DBGCTRL   volatile.Register8  // 0xE
	_         byte
	SYNCBUSY  volatile.Register32 // 0x10
	FREQCORR  volatile.Register8  // 0x14
	_         [3]byte
	COUNT     volatile.Register32 // 0x18
	_         [4]byte
	COMP      [2]volatile.Register32 // 0x20
	_         [24]byte
	GP        [4]volatile.Register32 // 0x40
	_         [16]byte
	TAMPCTRL  volatile.Register32 // 0x60
	TIMESTAMP volatile.Register32 // 0x64
	TAMPID    volatile.Register32 // 0x68
	_         [20]byte
	BKUP      [8]volatile.Register32 // 0x80
}

// Real-Time Counter - MODE1
type RTC_MODE1_Type struct {
	CTRLA     volatile.Register16 // 0x0
	CTRLB     volatile.Register16 // 0x2
	EVCTRL    volatile.Register32 // 0x4
	INTENCLR  volatile.Register16 // 0x8
	INTENSET  volatile.Register16 // 0xA
	INTFLAG   volatile.Register16 // 0xC
	DBGCTRL   volatile.Register8  // 0xE
	_         byte
	SYNCBUSY  volatile.Register32 // 0x10
	FREQCORR  volatile.Register8  // 0x14
	_         [3]byte
	COUNT     volatile.Register16 // 0x18
	_         [2]byte
	PER       volatile.Register16 // 0x1C
	_         [2]byte
	COMP      [4]volatile.Register16 // 0x20
	_         [24]byte
	GP        [4]volatile.Register32 // 0x40
	_         [16]byte
	TAMPCTRL  volatile.Register32 // 0x60
	TIMESTAMP volatile.Register32 // 0x64
	TAMPID    volatile.Register32 // 0x68
	_         [20]byte
	BKUP      [8]volatile.Register32 // 0x80
}

// Real-Time Counter - MODE2
type RTC_MODE2_Type struct {
	CTRLA     volatile.Register16 // 0x0
	CTRLB     volatile.Register16 // 0x2
	EVCTRL    volatile.Register32 // 0x4
	INTENCLR  volatile.Register16 // 0x8
	INTENSET  volatile.Register16 // 0xA
	INTFLAG   volatile.Register16 // 0xC
	DBGCTRL   volatile.Register8  // 0xE
	_         byte
	SYNCBUSY  volatile.Register32 // 0x10
	FREQCORR  volatile.Register8  // 0x14
	_         [3]byte
	CLOCK     volatile.Register32 // 0x18
	_         [4]byte
	ALARM0    volatile.Register32 // 0x20
	MASK0     volatile.Register8  // 0x24
	_         [3]byte
	ALARM1    volatile.Register32 // 0x28
	MASK1     volatile.Register8  // 0x2C
	_         [19]byte
	GP        [4]volatile.Register32 // 0x40
	_         [16]byte
	TAMPCTRL  volatile.Register32 // 0x60
	TIMESTAMP volatile.Register32 // 0x64
	TAMPID    volatile.Register32 // 0x68
	_         [20]byte
	BKUP      [8]volatile.Register32 // 0x80
}

// SD/MMC Host Controller
type SDHC_Type struct {
	SSAR    volatile.Register32    // 0x0
	BSR     volatile.Register16    // 0x4
	BCR     volatile.Register16    // 0x6
	ARG1R   volatile.Register32    // 0x8
	TMR     volatile.Register16    // 0xC
	CR      volatile.Register16    // 0xE
	RR      [4]volatile.Register32 // 0x10
	BDPR    volatile.Register32    // 0x20
	PSR     volatile.Register32    // 0x24
	HC1R    volatile.Register8     // 0x28
	PCR     volatile.Register8     // 0x29
	BGCR    volatile.Register8     // 0x2A
	WCR     volatile.Register8     // 0x2B
	CCR     volatile.Register16    // 0x2C
	TCR     volatile.Register8     // 0x2E
	SRR     volatile.Register8     // 0x2F
	NISTR   volatile.Register16    // 0x30
	EISTR   volatile.Register16    // 0x32
	NISTER  volatile.Register16    // 0x34
	EISTER  volatile.Register16    // 0x36
	NISIER  volatile.Register16    // 0x38
	EISIER  volatile.Register16    // 0x3A
	ACESR   volatile.Register16    // 0x3C
	HC2R    volatile.Register16    // 0x3E
	CA0R    volatile.Register32    // 0x40
	CA1R    volatile.Register32    // 0x44
	MCCAR   volatile.Register32    // 0x48
	_       [4]byte
	FERACES volatile.Register16 // 0x50
	FEREIS  volatile.Register16 // 0x52
	AESR    volatile.Register8  // 0x54
	_       [3]byte
	ASAR    [1]volatile.Register32 // 0x58
	_       [4]byte
	PVR     [8]volatile.Register16 // 0x60
	_       [140]byte
	SISR    volatile.Register16 // 0xFC
	HCVR    volatile.Register16 // 0xFE
	_       [260]byte
	MC1R    volatile.Register8 // 0x204
	MC2R    volatile.Register8 // 0x205
	_       [2]byte
	ACR     volatile.Register32 // 0x208
	CC2R    volatile.Register32 // 0x20C
	_       [32]byte
	CACR    volatile.Register32 // 0x230
	DBGR    volatile.Register8  // 0x234
}

// Serial Communication Interface
type SERCOM_Type struct {
}

// Serial Communication Interface - I2CM
type SERCOM_I2CM_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register32 // 0xC
	_        [4]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [4]byte
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register8  // 0x28
	_        [7]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - I2CS
type SERCOM_I2CS_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	_        [8]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [2]byte
	LENGTH   volatile.Register16 // 0x22
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register32 // 0x28
}

// Serial Communication Interface - SPIS
type SERCOM_SPIS_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register8  // 0xC
	_        [7]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [2]byte
	LENGTH   volatile.Register16 // 0x22
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - SPIM
type SERCOM_SPIM_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register8  // 0xC
	_        [7]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [2]byte
	LENGTH   volatile.Register16 // 0x22
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - USART_EXT
type SERCOM_USART_EXT_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register16 // 0xC
	RXPL     volatile.Register8  // 0xE
	_        [5]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	RXERRCNT volatile.Register8  // 0x20
	_        byte
	LENGTH   volatile.Register16 // 0x22
	_        [4]byte
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - USART_INT
type SERCOM_USART_INT_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register16 // 0xC
	RXPL     volatile.Register8  // 0xE
	_        [5]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	RXERRCNT volatile.Register8  // 0x20
	_        byte
	LENGTH   volatile.Register16 // 0x22
	_        [4]byte
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Supply Controller
type SUPC_Type struct {
	INTENCLR volatile.Register32 // 0x0
	INTENSET volatile.Register32 // 0x4
	INTFLAG  volatile.Register32 // 0x8
	STATUS   volatile.Register32 // 0xC
	BOD33    volatile.Register32 // 0x10
	_        [4]byte
	VREG     volatile.Register32 // 0x18
	VREF     volatile.Register32 // 0x1C
	BBPS     volatile.Register32 // 0x20
	BKOUT    volatile.Register32 // 0x24
	BKIN     volatile.Register32 // 0x28
}

// Basic Timer Counter
type TC_Type struct {
}

// Basic Timer Counter - COUNT8
type TC_COUNT8_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	EVCTRL   volatile.Register16 // 0x6
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	WAVE     volatile.Register8  // 0xC
	DRVCTRL  volatile.Register8  // 0xD
	_        byte
	DBGCTRL  volatile.Register8  // 0xF
	SYNCBUSY volatile.Register32 // 0x10
	COUNT    volatile.Register8  // 0x14
	_        [6]byte
	PER      volatile.Register8    // 0x1B
	CC       [2]volatile.Register8 // 0x1C
	_        [17]byte
	PERBUF   volatile.Register8    // 0x2F
	CCBUF    [2]volatile.Register8 // 0x30
}

// Basic Timer Counter - COUNT16
type TC_COUNT16_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	EVCTRL   volatile.Register16 // 0x6
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	WAVE     volatile.Register8  // 0xC
	DRVCTRL  volatile.Register8  // 0xD
	_        byte
	DBGCTRL  volatile.Register8  // 0xF
	SYNCBUSY volatile.Register32 // 0x10
	COUNT    volatile.Register16 // 0x14
	_        [6]byte
	CC       [2]volatile.Register16 // 0x1C
	_        [16]byte
	CCBUF    [2]volatile.Register16 // 0x30
}

// Basic Timer Counter - COUNT32
type TC_COUNT32_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	EVCTRL   volatile.Register16 // 0x6
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	WAVE     volatile.Register8  // 0xC
	DRVCTRL  volatile.Register8  // 0xD
	_        byte
	DBGCTRL  volatile.Register8  // 0xF
	SYNCBUSY volatile.Register32 // 0x10
	COUNT    volatile.Register32 // 0x14
	_        [4]byte
	CC       [2]volatile.Register32 // 0x1C
	_        [12]byte
	CCBUF    [2]volatile.Register32 // 0x30
}

// Timer Counter Control
type TCC_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	_        [2]byte
	SYNCBUSY volatile.Register32 // 0x8
	FCTRLA   volatile.Register32 // 0xC
	FCTRLB   volatile.Register32 // 0x10
	WEXCTRL  volatile.Register32 // 0x14
	DRVCTRL  volatile.Register32 // 0x18
	_        [2]byte
	DBGCTRL  volatile.Register8 // 0x1E
	_        byte
	EVCTRL   volatile.Register32 // 0x20
	INTENCLR volatile.Register32 // 0x24
	INTENSET volatile.Register32 // 0x28
	INTFLAG  volatile.Register32 // 0x2C
	STATUS   volatile.Register32 // 0x30
	COUNT    volatile.Register32 // 0x34
	PATT     volatile.Register16 // 0x38
	_        [2]byte
	WAVE     volatile.Register32    // 0x3C
	PER      volatile.Register32    // 0x40
	CC       [6]volatile.Register32 // 0x44
	_        [8]byte
	PATTBUF  volatile.Register16 // 0x64
	_        [6]byte
	PERBUF   volatile.Register32    // 0x6C
	CCBUF    [6]volatile.Register32 // 0x70
}

// True Random Generator
type TRNG_Type struct {
	CTRLA    volatile.Register8 // 0x0
	_        [3]byte
	EVCTRL   volatile.Register8 // 0x4
	_        [3]byte
	INTENCLR volatile.Register8 // 0x8
	INTENSET volatile.Register8 // 0x9
	INTFLAG  volatile.Register8 // 0xA
	_        [21]byte
	DATA     volatile.Register32 // 0x20
}

// Universal Serial Bus
type USB_Type struct {
}

// Universal Serial Bus - DEVICE
type USB_DEVICE_Type struct {
	CTRLA           volatile.Register8 // 0x0
	_               byte
	SYNCBUSY        volatile.Register8 // 0x2
	QOSCTRL         volatile.Register8 // 0x3
	_               [4]byte
	CTRLB           volatile.Register16 // 0x8
	DADD            volatile.Register8  // 0xA
	_               byte
	STATUS          volatile.Register8 // 0xC
	FSMSTATUS       volatile.Register8 // 0xD
	_               [2]byte
	FNUM            volatile.Register16 // 0x10
	_               [2]byte
	INTENCLR        volatile.Register16 // 0x14
	_               [2]byte
	INTENSET        volatile.Register16 // 0x18
	_               [2]byte
	INTFLAG         volatile.Register16 // 0x1C
	_               [2]byte
	EPINTSMRY       volatile.Register16 // 0x20
	_               [2]byte
	DESCADD         volatile.Register32 // 0x24
	PADCAL          volatile.Register16 // 0x28
	_               [214]byte
	DEVICE_ENDPOINT [8]struct {
		EPCFG       volatile.Register8
		_           [3]byte
		EPSTATUSCLR volatile.Register8
		EPSTATUSSET volatile.Register8
		EPSTATUS    volatile.Register8
		EPINTFLAG   volatile.Register8
		EPINTENCLR  volatile.Register8
		EPINTENSET  volatile.Register8
		_           [22]byte
	} // 0x100
}

// Universal Serial Bus - HOST
type USB_HOST_Type struct {
	CTRLA     volatile.Register8 // 0x0
	_         byte
	SYNCBUSY  volatile.Register8 // 0x2
	QOSCTRL   volatile.Register8 // 0x3
	_         [4]byte
	CTRLB     volatile.Register16 // 0x8
	HSOFC     volatile.Register8  // 0xA
	_         byte
	STATUS    volatile.Register8 // 0xC
	FSMSTATUS volatile.Register8 // 0xD
	_         [2]byte
	FNUM      volatile.Register16 // 0x10
	FLENHIGH  volatile.Register8  // 0x12
	_         byte
	INTENCLR  volatile.Register16 // 0x14
	_         [2]byte
	INTENSET  volatile.Register16 // 0x18
	_         [2]byte
	INTFLAG   volatile.Register16 // 0x1C
	_         [2]byte
	PINTSMRY  volatile.Register16 // 0x20
	_         [2]byte
	DESCADD   volatile.Register32 // 0x24
	PADCAL    volatile.Register16 // 0x28
	_         [214]byte
	HOST_PIPE [8]struct {
		PCFG       volatile.Register8
		_          [2]byte
		BINTERVAL  volatile.Register8
		PSTATUSCLR volatile.Register8
		PSTATUSSET volatile.Register8
		PSTATUS    volatile.Register8
		PINTFLAG   volatile.Register8
		PINTENCLR  volatile.Register8
		PINTENSET  volatile.Register8
		_          [22]byte
	} // 0x100
}

// Watchdog Timer
type WDT_Type struct {
	CTRLA    volatile.Register8 // 0x0
	CONFIG   volatile.Register8 // 0x1
	EWCTRL   volatile.Register8 // 0x2
	_        byte
	INTENCLR volatile.Register8 // 0x4
	INTENSET volatile.Register8 // 0x5
	INTFLAG  volatile.Register8 // 0x6
	_        byte
	SYNCBUSY volatile.Register32 // 0x8
	CLEAR    volatile.Register8  // 0xC
}

// Core Debug Register
type CoreDebug_Type struct {
	DHCSR volatile.Register32 // 0x0
	DCRSR volatile.Register32 // 0x4
	DCRDR volatile.Register32 // 0x8
	DEMCR volatile.Register32 // 0xC
}

// Data Watchpoint and Trace Register
type DWT_Type struct {
	CTRL      volatile.Register32 // 0x0
	CYCCNT    volatile.Register32 // 0x4
	CPICNT    volatile.Register32 // 0x8
	EXCCNT    volatile.Register32 // 0xC
	SLEEPCNT  volatile.Register32 // 0x10
	LSUCNT    volatile.Register32 // 0x14
	FOLDCNT   volatile.Register32 // 0x18
	PCSR      volatile.Register32 // 0x1C
	COMP0     volatile.Register32 // 0x20
	MASK0     volatile.Register32 // 0x24
	FUNCTION0 volatile.Register32 // 0x28
	_         [4]byte
	COMP1     volatile.Register32 // 0x30
	MASK1     volatile.Register32 // 0x34
	FUNCTION1 volatile.Register32 // 0x38
	_         [4]byte
	COMP2     volatile.Register32 // 0x40
	MASK2     volatile.Register32 // 0x44
	FUNCTION2 volatile.Register32 // 0x48
	_         [4]byte
	COMP3     volatile.Register32 // 0x50
	MASK3     volatile.Register32 // 0x54
	FUNCTION3 volatile.Register32 // 0x58
}

// Embedded Trace Macrocell
type ETM_Type struct {
	CR         volatile.Register32 // 0x0
	CCR        volatile.Register32 // 0x4
	TRIGGER    volatile.Register32 // 0x8
	_          [4]byte
	SR         volatile.Register32 // 0x10
	SCR        volatile.Register32 // 0x14
	_          [8]byte
	TEEVR      volatile.Register32 // 0x20
	TECR1      volatile.Register32 // 0x24
	FFLR       volatile.Register32 // 0x28
	_          [276]byte
	CNTRLDVR1  volatile.Register32 // 0x140
	_          [156]byte
	SYNCFR     volatile.Register32 // 0x1E0
	IDR        volatile.Register32 // 0x1E4
	CCER       volatile.Register32 // 0x1E8
	_          [4]byte
	TESSEICR   volatile.Register32 // 0x1F0
	_          [4]byte
	TSEVT      volatile.Register32 // 0x1F8
	_          [4]byte
	TRACEIDR   volatile.Register32 // 0x200
	_          [4]byte
	IDR2       volatile.Register32 // 0x208
	_          [264]byte
	PDSR       volatile.Register32 // 0x314
	_          [3016]byte
	ITMISCIN   volatile.Register32 // 0xEE0
	_          [4]byte
	ITTRIGOUT  volatile.Register32 // 0xEE8
	_          [4]byte
	ITATBCTR2  volatile.Register32 // 0xEF0
	_          [4]byte
	ITATBCTR0  volatile.Register32 // 0xEF8
	_          [4]byte
	ITCTRL     volatile.Register32 // 0xF00
	_          [156]byte
	CLAIMSET   volatile.Register32 // 0xFA0
	CLAIMCLR   volatile.Register32 // 0xFA4
	_          [8]byte
	LAR        volatile.Register32 // 0xFB0
	LSR        volatile.Register32 // 0xFB4
	AUTHSTATUS volatile.Register32 // 0xFB8
	_          [16]byte
	DEVTYPE    volatile.Register32 // 0xFCC
	PIDR4      volatile.Register32 // 0xFD0
	PIDR5      volatile.Register32 // 0xFD4
	PIDR6      volatile.Register32 // 0xFD8
	PIDR7      volatile.Register32 // 0xFDC
	PIDR0      volatile.Register32 // 0xFE0
	PIDR1      volatile.Register32 // 0xFE4
	PIDR2      volatile.Register32 // 0xFE8
	PIDR3      volatile.Register32 // 0xFEC
	CIDR0      volatile.Register32 // 0xFF0
	CIDR1      volatile.Register32 // 0xFF4
	CIDR2      volatile.Register32 // 0xFF8
	CIDR3      volatile.Register32 // 0xFFC
}

// Floating Point Unit
type FPU_Type struct {
	_      [4]byte
	FPCCR  volatile.Register32 // 0x4
	FPCAR  volatile.Register32 // 0x8
	FPDSCR volatile.Register32 // 0xC
	MVFR0  volatile.Register32 // 0x10
	MVFR1  volatile.Register32 // 0x14
}

// Instrumentation Trace Macrocell
type ITM_Type struct {
	PORT_WORD_MODE [32]volatile.Register32 // 0x0
	_              [3456]byte
	TER            volatile.Register32 // 0xE00
	_              [60]byte
	TPR            volatile.Register32 // 0xE40
	_              [60]byte
	TCR            volatile.Register32 // 0xE80
	_              [116]byte
	IWR            volatile.Register32 // 0xEF8
	IRR            volatile.Register32 // 0xEFC
}

// Memory Protection Unit
type MPU_Type struct {
	TYPE    volatile.Register32 // 0x0
	CTRL    volatile.Register32 // 0x4
	RNR     volatile.Register32 // 0x8
	RBAR    volatile.Register32 // 0xC
	RASR    volatile.Register32 // 0x10
	RBAR_A1 volatile.Register32 // 0x14
	RASR_A1 volatile.Register32 // 0x18
	RBAR_A2 volatile.Register32 // 0x1C
	RASR_A2 volatile.Register32 // 0x20
	RBAR_A3 volatile.Register32 // 0x24
	RASR_A3 volatile.Register32 // 0x28
}

// Nested Vectored Interrupt Controller
type NVIC_Type struct {
	ISER [5]volatile.Register32 // 0x0
	_    [108]byte
	ICER [5]volatile.Register32 // 0x80
	_    [108]byte
	ISPR [5]volatile.Register32 // 0x100
	_    [108]byte
	ICPR [5]volatile.Register32 // 0x180
	_    [108]byte
	IABR [5]volatile.Register32 // 0x200
	_    [236]byte
	IP   [35]volatile.Register8 // 0x300
	_    [2781]byte
	STIR volatile.Register32 // 0xE00
}

// System timer
type SysTick_Type struct {
	CSR   volatile.Register32 // 0x0
	RVR   volatile.Register32 // 0x4
	CVR   volatile.Register32 // 0x8
	CALIB volatile.Register32 // 0xC
}

// System Control Registers
type SystemControl_Type struct {
	_     [4]byte
	ICTR  volatile.Register32 // 0x4
	ACTLR volatile.Register32 // 0x8
	_     [3316]byte
	CPUID volatile.Register32    // 0xD00
	ICSR  volatile.Register32    // 0xD04
	VTOR  volatile.Register32    // 0xD08
	AIRCR volatile.Register32    // 0xD0C
	SCR   volatile.Register32    // 0xD10
	CCR   volatile.Register32    // 0xD14
	SHPR1 volatile.Register32    // 0xD18
	SHPR2 volatile.Register32    // 0xD1C
	SHPR3 volatile.Register32    // 0xD20
	SHCSR volatile.Register32    // 0xD24
	CFSR  volatile.Register32    // 0xD28
	HFSR  volatile.Register32    // 0xD2C
	DFSR  volatile.Register32    // 0xD30
	MMFAR volatile.Register32    // 0xD34
	BFAR  volatile.Register32    // 0xD38
	AFSR  volatile.Register32    // 0xD3C
	PFR   [2]volatile.Register32 // 0xD40
	DFR   volatile.Register32    // 0xD48
	ADR   volatile.Register32    // 0xD4C
	MMFR  [4]volatile.Register32 // 0xD50
	ISAR  [5]volatile.Register32 // 0xD60
	_     [20]byte
	CPACR volatile.Register32 // 0xD88
}

// Trace Port Interface Register
type TPI_Type struct {
	SSPSR     volatile.Register32 // 0x0
	CSPSR     volatile.Register32 // 0x4
	_         [8]byte
	ACPR      volatile.Register32 // 0x10
	_         [220]byte
	SPPR      volatile.Register32 // 0xF0
	_         [524]byte
	FFSR      volatile.Register32 // 0x300
	FFCR      volatile.Register32 // 0x304
	FSCR      volatile.Register32 // 0x308
	_         [3036]byte
	TRIGGER   volatile.Register32 // 0xEE8
	FIFO0     volatile.Register32 // 0xEEC
	ITATBCTR2 volatile.Register32 // 0xEF0
	_         [4]byte
	ITATBCTR0 volatile.Register32 // 0xEF8
	FIFO1     volatile.Register32 // 0xEFC
	ITCTRL    volatile.Register32 // 0xF00
	_         [156]byte
	CLAIMSET  volatile.Register32 // 0xFA0
	CLAIMCLR  volatile.Register32 // 0xFA4
	_         [32]byte
	DEVID     volatile.Register32 // 0xFC8
	DEVTYPE   volatile.Register32 // 0xFCC
}

// Bitfields for AC: Analog Comparators
const (
	// CTRLA: Control A
	// Position of SWRST field.
	AC_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	AC_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	AC_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	AC_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	AC_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	AC_CTRLA_ENABLE = 0x2

	// CTRLB: Control B
	// Position of START0 field.
	AC_CTRLB_START0_Pos = 0x0
	// Bit mask of START0 field.
	AC_CTRLB_START0_Msk = 0x1
	// Bit START0.
	AC_CTRLB_START0 = 0x1
	// Position of START1 field.
	AC_CTRLB_START1_Pos = 0x1
	// Bit mask of START1 field.
	AC_CTRLB_START1_Msk = 0x2
	// Bit START1.
	AC_CTRLB_START1 = 0x2

	// EVCTRL: Event Control
	// Position of COMPEO0 field.
	AC_EVCTRL_COMPEO0_Pos = 0x0
	// Bit mask of COMPEO0 field.
	AC_EVCTRL_COMPEO0_Msk = 0x1
	// Bit COMPEO0.
	AC_EVCTRL_COMPEO0 = 0x1
	// Position of COMPEO1 field.
	AC_EVCTRL_COMPEO1_Pos = 0x1
	// Bit mask of COMPEO1 field.
	AC_EVCTRL_COMPEO1_Msk = 0x2
	// Bit COMPEO1.
	AC_EVCTRL_COMPEO1 = 0x2
	// Position of WINEO0 field.
	AC_EVCTRL_WINEO0_Pos = 0x4
	// Bit mask of WINEO0 field.
	AC_EVCTRL_WINEO0_Msk = 0x10
	// Bit WINEO0.
	AC_EVCTRL_WINEO0 = 0x10
	// Position of COMPEI0 field.
	AC_EVCTRL_COMPEI0_Pos = 0x8
	// Bit mask of COMPEI0 field.
	AC_EVCTRL_COMPEI0_Msk = 0x100
	// Bit COMPEI0.
	AC_EVCTRL_COMPEI0 = 0x100
	// Position of COMPEI1 field.
	AC_EVCTRL_COMPEI1_Pos = 0x9
	// Bit mask of COMPEI1 field.
	AC_EVCTRL_COMPEI1_Msk = 0x200
	// Bit COMPEI1.
	AC_EVCTRL_COMPEI1 = 0x200
	// Position of INVEI0 field.
	AC_EVCTRL_INVEI0_Pos = 0xc
	// Bit mask of INVEI0 field.
	AC_EVCTRL_INVEI0_Msk = 0x1000
	// Bit INVEI0.
	AC_EVCTRL_INVEI0 = 0x1000
	// Position of INVEI1 field.
	AC_EVCTRL_INVEI1_Pos = 0xd
	// Bit mask of INVEI1 field.
	AC_EVCTRL_INVEI1_Msk = 0x2000
	// Bit INVEI1.
	AC_EVCTRL_INVEI1 = 0x2000

	// INTENCLR: Interrupt Enable Clear
	// Position of COMP0 field.
	AC_INTENCLR_COMP0_Pos = 0x0
	// Bit mask of COMP0 field.
	AC_INTENCLR_COMP0_Msk = 0x1
	// Bit COMP0.
	AC_INTENCLR_COMP0 = 0x1
	// Position of COMP1 field.
	AC_INTENCLR_COMP1_Pos = 0x1
	// Bit mask of COMP1 field.
	AC_INTENCLR_COMP1_Msk = 0x2
	// Bit COMP1.
	AC_INTENCLR_COMP1 = 0x2
	// Position of WIN0 field.
	AC_INTENCLR_WIN0_Pos = 0x4
	// Bit mask of WIN0 field.
	AC_INTENCLR_WIN0_Msk = 0x10
	// Bit WIN0.
	AC_INTENCLR_WIN0 = 0x10

	// INTENSET: Interrupt Enable Set
	// Position of COMP0 field.
	AC_INTENSET_COMP0_Pos = 0x0
	// Bit mask of COMP0 field.
	AC_INTENSET_COMP0_Msk = 0x1
	// Bit COMP0.
	AC_INTENSET_COMP0 = 0x1
	// Position of COMP1 field.
	AC_INTENSET_COMP1_Pos = 0x1
	// Bit mask of COMP1 field.
	AC_INTENSET_COMP1_Msk = 0x2
	// Bit COMP1.
	AC_INTENSET_COMP1 = 0x2
	// Position of WIN0 field.
	AC_INTENSET_WIN0_Pos = 0x4
	// Bit mask of WIN0 field.
	AC_INTENSET_WIN0_Msk = 0x10
	// Bit WIN0.
	AC_INTENSET_WIN0 = 0x10

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of COMP0 field.
	AC_INTFLAG_COMP0_Pos = 0x0
	// Bit mask of COMP0 field.
	AC_INTFLAG_COMP0_Msk = 0x1
	// Bit COMP0.
	AC_INTFLAG_COMP0 = 0x1
	// Position of COMP1 field.
	AC_INTFLAG_COMP1_Pos = 0x1
	// Bit mask of COMP1 field.
	AC_INTFLAG_COMP1_Msk = 0x2
	// Bit COMP1.
	AC_INTFLAG_COMP1 = 0x2
	// Position of WIN0 field.
	AC_INTFLAG_WIN0_Pos = 0x4
	// Bit mask of WIN0 field.
	AC_INTFLAG_WIN0_Msk = 0x10
	// Bit WIN0.
	AC_INTFLAG_WIN0 = 0x10

	// STATUSA: Status A
	// Position of STATE0 field.
	AC_STATUSA_STATE0_Pos = 0x0
	// Bit mask of STATE0 field.
	AC_STATUSA_STATE0_Msk = 0x1
	// Bit STATE0.
	AC_STATUSA_STATE0 = 0x1
	// Position of STATE1 field.
	AC_STATUSA_STATE1_Pos = 0x1
	// Bit mask of STATE1 field.
	AC_STATUSA_STATE1_Msk = 0x2
	// Bit STATE1.
	AC_STATUSA_STATE1 = 0x2
	// Position of WSTATE0 field.
	AC_STATUSA_WSTATE0_Pos = 0x4
	// Bit mask of WSTATE0 field.
	AC_STATUSA_WSTATE0_Msk = 0x30
	// Signal is above window
	AC_STATUSA_WSTATE0_ABOVE = 0x0
	// Signal is inside window
	AC_STATUSA_WSTATE0_INSIDE = 0x1
	// Signal is below window
	AC_STATUSA_WSTATE0_BELOW = 0x2

	// STATUSB: Status B
	// Position of READY0 field.
	AC_STATUSB_READY0_Pos = 0x0
	// Bit mask of READY0 field.
	AC_STATUSB_READY0_Msk = 0x1
	// Bit READY0.
	AC_STATUSB_READY0 = 0x1
	// Position of READY1 field.
	AC_STATUSB_READY1_Pos = 0x1
	// Bit mask of READY1 field.
	AC_STATUSB_READY1_Msk = 0x2
	// Bit READY1.
	AC_STATUSB_READY1 = 0x2

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	AC_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	AC_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	AC_DBGCTRL_DBGRUN = 0x1

	// WINCTRL: Window Control
	// Position of WEN0 field.
	AC_WINCTRL_WEN0_Pos = 0x0
	// Bit mask of WEN0 field.
	AC_WINCTRL_WEN0_Msk = 0x1
	// Bit WEN0.
	AC_WINCTRL_WEN0 = 0x1
	// Position of WINTSEL0 field.
	AC_WINCTRL_WINTSEL0_Pos = 0x1
	// Bit mask of WINTSEL0 field.
	AC_WINCTRL_WINTSEL0_Msk = 0x6
	// Interrupt on signal above window
	AC_WINCTRL_WINTSEL0_ABOVE = 0x0
	// Interrupt on signal inside window
	AC_WINCTRL_WINTSEL0_INSIDE = 0x1
	// Interrupt on signal below window
	AC_WINCTRL_WINTSEL0_BELOW = 0x2
	// Interrupt on signal outside window
	AC_WINCTRL_WINTSEL0_OUTSIDE = 0x3

	// SCALER: Scaler n
	// Position of VALUE field.
	AC_SCALER_VALUE_Pos = 0x0
	// Bit mask of VALUE field.
	AC_SCALER_VALUE_Msk = 0x3f

	// COMPCTRL: Comparator Control n
	// Position of ENABLE field.
	AC_COMPCTRL_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	AC_COMPCTRL_ENABLE_Msk = 0x2
	// Bit ENABLE.
	AC_COMPCTRL_ENABLE = 0x2
	// Position of SINGLE field.
	AC_COMPCTRL_SINGLE_Pos = 0x2
	// Bit mask of SINGLE field.
	AC_COMPCTRL_SINGLE_Msk = 0x4
	// Bit SINGLE.
	AC_COMPCTRL_SINGLE = 0x4
	// Position of INTSEL field.
	AC_COMPCTRL_INTSEL_Pos = 0x3
	// Bit mask of INTSEL field.
	AC_COMPCTRL_INTSEL_Msk = 0x18
	// Interrupt on comparator output toggle
	AC_COMPCTRL_INTSEL_TOGGLE = 0x0
	// Interrupt on comparator output rising
	AC_COMPCTRL_INTSEL_RISING = 0x1
	// Interrupt on comparator output falling
	AC_COMPCTRL_INTSEL_FALLING = 0x2
	// Interrupt on end of comparison (single-shot mode only)
	AC_COMPCTRL_INTSEL_EOC = 0x3
	// Position of RUNSTDBY field.
	AC_COMPCTRL_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	AC_COMPCTRL_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	AC_COMPCTRL_RUNSTDBY = 0x40
	// Position of MUXNEG field.
	AC_COMPCTRL_MUXNEG_Pos = 0x8
	// Bit mask of MUXNEG field.
	AC_COMPCTRL_MUXNEG_Msk = 0x700
	// I/O pin 0
	AC_COMPCTRL_MUXNEG_PIN0 = 0x0
	// I/O pin 1
	AC_COMPCTRL_MUXNEG_PIN1 = 0x1
	// I/O pin 2
	AC_COMPCTRL_MUXNEG_PIN2 = 0x2
	// I/O pin 3
	AC_COMPCTRL_MUXNEG_PIN3 = 0x3
	// Ground
	AC_COMPCTRL_MUXNEG_GND = 0x4
	// VDD scaler
	AC_COMPCTRL_MUXNEG_VSCALE = 0x5
	// Internal bandgap voltage
	AC_COMPCTRL_MUXNEG_BANDGAP = 0x6
	// DAC output
	AC_COMPCTRL_MUXNEG_DAC = 0x7
	// Position of MUXPOS field.
	AC_COMPCTRL_MUXPOS_Pos = 0xc
	// Bit mask of MUXPOS field.
	AC_COMPCTRL_MUXPOS_Msk = 0x7000
	// I/O pin 0
	AC_COMPCTRL_MUXPOS_PIN0 = 0x0
	// I/O pin 1
	AC_COMPCTRL_MUXPOS_PIN1 = 0x1
	// I/O pin 2
	AC_COMPCTRL_MUXPOS_PIN2 = 0x2
	// I/O pin 3
	AC_COMPCTRL_MUXPOS_PIN3 = 0x3
	// VDD Scaler
	AC_COMPCTRL_MUXPOS_VSCALE = 0x4
	// Position of SWAP field.
	AC_COMPCTRL_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	AC_COMPCTRL_SWAP_Msk = 0x8000
	// Bit SWAP.
	AC_COMPCTRL_SWAP = 0x8000
	// Position of SPEED field.
	AC_COMPCTRL_SPEED_Pos = 0x10
	// Bit mask of SPEED field.
	AC_COMPCTRL_SPEED_Msk = 0x30000
	// High speed
	AC_COMPCTRL_SPEED_HIGH = 0x3
	// Position of HYSTEN field.
	AC_COMPCTRL_HYSTEN_Pos = 0x13
	// Bit mask of HYSTEN field.
	AC_COMPCTRL_HYSTEN_Msk = 0x80000
	// Bit HYSTEN.
	AC_COMPCTRL_HYSTEN = 0x80000
	// Position of HYST field.
	AC_COMPCTRL_HYST_Pos = 0x14
	// Bit mask of HYST field.
	AC_COMPCTRL_HYST_Msk = 0x300000
	// 50mV
	AC_COMPCTRL_HYST_HYST50 = 0x0
	// 100mV
	AC_COMPCTRL_HYST_HYST100 = 0x1
	// 150mV
	AC_COMPCTRL_HYST_HYST150 = 0x2
	// Position of FLEN field.
	AC_COMPCTRL_FLEN_Pos = 0x18
	// Bit mask of FLEN field.
	AC_COMPCTRL_FLEN_Msk = 0x7000000
	// No filtering
	AC_COMPCTRL_FLEN_OFF = 0x0
	// 3-bit majority function (2 of 3)
	AC_COMPCTRL_FLEN_MAJ3 = 0x1
	// 5-bit majority function (3 of 5)
	AC_COMPCTRL_FLEN_MAJ5 = 0x2
	// Position of OUT field.
	AC_COMPCTRL_OUT_Pos = 0x1c
	// Bit mask of OUT field.
	AC_COMPCTRL_OUT_Msk = 0x30000000
	// The output of COMPn is not routed to the COMPn I/O port
	AC_COMPCTRL_OUT_OFF = 0x0
	// The asynchronous output of COMPn is routed to the COMPn I/O port
	AC_COMPCTRL_OUT_ASYNC = 0x1
	// The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
	AC_COMPCTRL_OUT_SYNC = 0x2

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	AC_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	AC_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	AC_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	AC_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	AC_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	AC_SYNCBUSY_ENABLE = 0x2
	// Position of WINCTRL field.
	AC_SYNCBUSY_WINCTRL_Pos = 0x2
	// Bit mask of WINCTRL field.
	AC_SYNCBUSY_WINCTRL_Msk = 0x4
	// Bit WINCTRL.
	AC_SYNCBUSY_WINCTRL = 0x4
	// Position of COMPCTRL0 field.
	AC_SYNCBUSY_COMPCTRL0_Pos = 0x3
	// Bit mask of COMPCTRL0 field.
	AC_SYNCBUSY_COMPCTRL0_Msk = 0x8
	// Bit COMPCTRL0.
	AC_SYNCBUSY_COMPCTRL0 = 0x8
	// Position of COMPCTRL1 field.
	AC_SYNCBUSY_COMPCTRL1_Pos = 0x4
	// Bit mask of COMPCTRL1 field.
	AC_SYNCBUSY_COMPCTRL1_Msk = 0x10
	// Bit COMPCTRL1.
	AC_SYNCBUSY_COMPCTRL1 = 0x10

	// CALIB: Calibration
	// Position of BIAS0 field.
	AC_CALIB_BIAS0_Pos = 0x0
	// Bit mask of BIAS0 field.
	AC_CALIB_BIAS0_Msk = 0x3
)

// Bitfields for ADC0: Analog Digital Converter
const (
	// CTRLA: Control A
	// Position of SWRST field.
	ADC_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	ADC_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	ADC_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	ADC_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	ADC_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	ADC_CTRLA_ENABLE = 0x2
	// Position of DUALSEL field.
	ADC_CTRLA_DUALSEL_Pos = 0x3
	// Bit mask of DUALSEL field.
	ADC_CTRLA_DUALSEL_Msk = 0x18
	// Start event or software trigger will start a conversion on both ADCs
	ADC_CTRLA_DUALSEL_BOTH = 0x0
	// START event or software trigger will alternatingly start a conversion on ADC0 and ADC1
	ADC_CTRLA_DUALSEL_INTERLEAVE = 0x1
	// Position of SLAVEEN field.
	ADC_CTRLA_SLAVEEN_Pos = 0x5
	// Bit mask of SLAVEEN field.
	ADC_CTRLA_SLAVEEN_Msk = 0x20
	// Bit SLAVEEN.
	ADC_CTRLA_SLAVEEN = 0x20
	// Position of RUNSTDBY field.
	ADC_CTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	ADC_CTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	ADC_CTRLA_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	ADC_CTRLA_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	ADC_CTRLA_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	ADC_CTRLA_ONDEMAND = 0x80
	// Position of PRESCALER field.
	ADC_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	ADC_CTRLA_PRESCALER_Msk = 0x700
	// Peripheral clock divided by 2
	ADC_CTRLA_PRESCALER_DIV2 = 0x0
	// Peripheral clock divided by 4
	ADC_CTRLA_PRESCALER_DIV4 = 0x1
	// Peripheral clock divided by 8
	ADC_CTRLA_PRESCALER_DIV8 = 0x2
	// Peripheral clock divided by 16
	ADC_CTRLA_PRESCALER_DIV16 = 0x3
	// Peripheral clock divided by 32
	ADC_CTRLA_PRESCALER_DIV32 = 0x4
	// Peripheral clock divided by 64
	ADC_CTRLA_PRESCALER_DIV64 = 0x5
	// Peripheral clock divided by 128
	ADC_CTRLA_PRESCALER_DIV128 = 0x6
	// Peripheral clock divided by 256
	ADC_CTRLA_PRESCALER_DIV256 = 0x7
	// Position of R2R field.
	ADC_CTRLA_R2R_Pos = 0xf
	// Bit mask of R2R field.
	ADC_CTRLA_R2R_Msk = 0x8000
	// Bit R2R.
	ADC_CTRLA_R2R = 0x8000

	// EVCTRL: Event Control
	// Position of FLUSHEI field.
	ADC_EVCTRL_FLUSHEI_Pos = 0x0
	// Bit mask of FLUSHEI field.
	ADC_EVCTRL_FLUSHEI_Msk = 0x1
	// Bit FLUSHEI.
	ADC_EVCTRL_FLUSHEI = 0x1
	// Position of STARTEI field.
	ADC_EVCTRL_STARTEI_Pos = 0x1
	// Bit mask of STARTEI field.
	ADC_EVCTRL_STARTEI_Msk = 0x2
	// Bit STARTEI.
	ADC_EVCTRL_STARTEI = 0x2
	// Position of FLUSHINV field.
	ADC_EVCTRL_FLUSHINV_Pos = 0x2
	// Bit mask of FLUSHINV field.
	ADC_EVCTRL_FLUSHINV_Msk = 0x4
	// Bit FLUSHINV.
	ADC_EVCTRL_FLUSHINV = 0x4
	// Position of STARTINV field.
	ADC_EVCTRL_STARTINV_Pos = 0x3
	// Bit mask of STARTINV field.
	ADC_EVCTRL_STARTINV_Msk = 0x8
	// Bit STARTINV.
	ADC_EVCTRL_STARTINV = 0x8
	// Position of RESRDYEO field.
	ADC_EVCTRL_RESRDYEO_Pos = 0x4
	// Bit mask of RESRDYEO field.
	ADC_EVCTRL_RESRDYEO_Msk = 0x10
	// Bit RESRDYEO.
	ADC_EVCTRL_RESRDYEO = 0x10
	// Position of WINMONEO field.
	ADC_EVCTRL_WINMONEO_Pos = 0x5
	// Bit mask of WINMONEO field.
	ADC_EVCTRL_WINMONEO_Msk = 0x20
	// Bit WINMONEO.
	ADC_EVCTRL_WINMONEO = 0x20

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	ADC_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	ADC_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	ADC_DBGCTRL_DBGRUN = 0x1

	// INPUTCTRL: Input Control
	// Position of MUXPOS field.
	ADC_INPUTCTRL_MUXPOS_Pos = 0x0
	// Bit mask of MUXPOS field.
	ADC_INPUTCTRL_MUXPOS_Msk = 0x1f
	// ADC AIN0 Pin
	ADC_INPUTCTRL_MUXPOS_AIN0 = 0x0
	// ADC AIN1 Pin
	ADC_INPUTCTRL_MUXPOS_AIN1 = 0x1
	// ADC AIN2 Pin
	ADC_INPUTCTRL_MUXPOS_AIN2 = 0x2
	// ADC AIN3 Pin
	ADC_INPUTCTRL_MUXPOS_AIN3 = 0x3
	// ADC AIN4 Pin
	ADC_INPUTCTRL_MUXPOS_AIN4 = 0x4
	// ADC AIN5 Pin
	ADC_INPUTCTRL_MUXPOS_AIN5 = 0x5
	// ADC AIN6 Pin
	ADC_INPUTCTRL_MUXPOS_AIN6 = 0x6
	// ADC AIN7 Pin
	ADC_INPUTCTRL_MUXPOS_AIN7 = 0x7
	// ADC AIN8 Pin
	ADC_INPUTCTRL_MUXPOS_AIN8 = 0x8
	// ADC AIN9 Pin
	ADC_INPUTCTRL_MUXPOS_AIN9 = 0x9
	// ADC AIN10 Pin
	ADC_INPUTCTRL_MUXPOS_AIN10 = 0xa
	// ADC AIN11 Pin
	ADC_INPUTCTRL_MUXPOS_AIN11 = 0xb
	// ADC AIN12 Pin
	ADC_INPUTCTRL_MUXPOS_AIN12 = 0xc
	// ADC AIN13 Pin
	ADC_INPUTCTRL_MUXPOS_AIN13 = 0xd
	// ADC AIN14 Pin
	ADC_INPUTCTRL_MUXPOS_AIN14 = 0xe
	// ADC AIN15 Pin
	ADC_INPUTCTRL_MUXPOS_AIN15 = 0xf
	// ADC AIN16 Pin
	ADC_INPUTCTRL_MUXPOS_AIN16 = 0x10
	// ADC AIN17 Pin
	ADC_INPUTCTRL_MUXPOS_AIN17 = 0x11
	// ADC AIN18 Pin
	ADC_INPUTCTRL_MUXPOS_AIN18 = 0x12
	// ADC AIN19 Pin
	ADC_INPUTCTRL_MUXPOS_AIN19 = 0x13
	// ADC AIN20 Pin
	ADC_INPUTCTRL_MUXPOS_AIN20 = 0x14
	// ADC AIN21 Pin
	ADC_INPUTCTRL_MUXPOS_AIN21 = 0x15
	// ADC AIN22 Pin
	ADC_INPUTCTRL_MUXPOS_AIN22 = 0x16
	// ADC AIN23 Pin
	ADC_INPUTCTRL_MUXPOS_AIN23 = 0x17
	// 1/4 Scaled Core Supply
	ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC = 0x18
	// 1/4 Scaled VBAT Supply
	ADC_INPUTCTRL_MUXPOS_SCALEDVBAT = 0x19
	// 1/4 Scaled I/O Supply
	ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC = 0x1a
	// Bandgap Voltage
	ADC_INPUTCTRL_MUXPOS_BANDGAP = 0x1b
	// Temperature Sensor
	ADC_INPUTCTRL_MUXPOS_PTAT = 0x1c
	// Temperature Sensor
	ADC_INPUTCTRL_MUXPOS_CTAT = 0x1d
	// DAC Output
	ADC_INPUTCTRL_MUXPOS_DAC = 0x1e
	// PTC output (only on ADC0)
	ADC_INPUTCTRL_MUXPOS_PTC = 0x1f
	// Position of DIFFMODE field.
	ADC_INPUTCTRL_DIFFMODE_Pos = 0x7
	// Bit mask of DIFFMODE field.
	ADC_INPUTCTRL_DIFFMODE_Msk = 0x80
	// Bit DIFFMODE.
	ADC_INPUTCTRL_DIFFMODE = 0x80
	// Position of MUXNEG field.
	ADC_INPUTCTRL_MUXNEG_Pos = 0x8
	// Bit mask of MUXNEG field.
	ADC_INPUTCTRL_MUXNEG_Msk = 0x1f00
	// ADC AIN0 Pin
	ADC_INPUTCTRL_MUXNEG_AIN0 = 0x0
	// ADC AIN1 Pin
	ADC_INPUTCTRL_MUXNEG_AIN1 = 0x1
	// ADC AIN2 Pin
	ADC_INPUTCTRL_MUXNEG_AIN2 = 0x2
	// ADC AIN3 Pin
	ADC_INPUTCTRL_MUXNEG_AIN3 = 0x3
	// ADC AIN4 Pin
	ADC_INPUTCTRL_MUXNEG_AIN4 = 0x4
	// ADC AIN5 Pin
	ADC_INPUTCTRL_MUXNEG_AIN5 = 0x5
	// ADC AIN6 Pin
	ADC_INPUTCTRL_MUXNEG_AIN6 = 0x6
	// ADC AIN7 Pin
	ADC_INPUTCTRL_MUXNEG_AIN7 = 0x7
	// Internal Ground
	ADC_INPUTCTRL_MUXNEG_GND = 0x18
	// Position of DSEQSTOP field.
	ADC_INPUTCTRL_DSEQSTOP_Pos = 0xf
	// Bit mask of DSEQSTOP field.
	ADC_INPUTCTRL_DSEQSTOP_Msk = 0x8000
	// Bit DSEQSTOP.
	ADC_INPUTCTRL_DSEQSTOP = 0x8000

	// CTRLB: Control B
	// Position of LEFTADJ field.
	ADC_CTRLB_LEFTADJ_Pos = 0x0
	// Bit mask of LEFTADJ field.
	ADC_CTRLB_LEFTADJ_Msk = 0x1
	// Bit LEFTADJ.
	ADC_CTRLB_LEFTADJ = 0x1
	// Position of FREERUN field.
	ADC_CTRLB_FREERUN_Pos = 0x1
	// Bit mask of FREERUN field.
	ADC_CTRLB_FREERUN_Msk = 0x2
	// Bit FREERUN.
	ADC_CTRLB_FREERUN = 0x2
	// Position of CORREN field.
	ADC_CTRLB_CORREN_Pos = 0x2
	// Bit mask of CORREN field.
	ADC_CTRLB_CORREN_Msk = 0x4
	// Bit CORREN.
	ADC_CTRLB_CORREN = 0x4
	// Position of RESSEL field.
	ADC_CTRLB_RESSEL_Pos = 0x3
	// Bit mask of RESSEL field.
	ADC_CTRLB_RESSEL_Msk = 0x18
	// 12-bit result
	ADC_CTRLB_RESSEL_12BIT = 0x0
	// For averaging mode output
	ADC_CTRLB_RESSEL_16BIT = 0x1
	// 10-bit result
	ADC_CTRLB_RESSEL_10BIT = 0x2
	// 8-bit result
	ADC_CTRLB_RESSEL_8BIT = 0x3
	// Position of WINMODE field.
	ADC_CTRLB_WINMODE_Pos = 0x8
	// Bit mask of WINMODE field.
	ADC_CTRLB_WINMODE_Msk = 0x700
	// No window mode (default)
	ADC_CTRLB_WINMODE_DISABLE = 0x0
	// RESULT > WINLT
	ADC_CTRLB_WINMODE_MODE1 = 0x1
	// RESULT < WINUT
	ADC_CTRLB_WINMODE_MODE2 = 0x2
	// WINLT < RESULT < WINUT
	ADC_CTRLB_WINMODE_MODE3 = 0x3
	// !(WINLT < RESULT < WINUT)
	ADC_CTRLB_WINMODE_MODE4 = 0x4
	// Position of WINSS field.
	ADC_CTRLB_WINSS_Pos = 0xb
	// Bit mask of WINSS field.
	ADC_CTRLB_WINSS_Msk = 0x800
	// Bit WINSS.
	ADC_CTRLB_WINSS = 0x800

	// REFCTRL: Reference Control
	// Position of REFSEL field.
	ADC_REFCTRL_REFSEL_Pos = 0x0
	// Bit mask of REFSEL field.
	ADC_REFCTRL_REFSEL_Msk = 0xf
	// Internal Bandgap Reference
	ADC_REFCTRL_REFSEL_INTREF = 0x0
	// 1/2 VDDANA
	ADC_REFCTRL_REFSEL_INTVCC0 = 0x2
	// VDDANA
	ADC_REFCTRL_REFSEL_INTVCC1 = 0x3
	// External Reference
	ADC_REFCTRL_REFSEL_AREFA = 0x4
	// External Reference
	ADC_REFCTRL_REFSEL_AREFB = 0x5
	// External Reference (only on ADC1)
	ADC_REFCTRL_REFSEL_AREFC = 0x6
	// Position of REFCOMP field.
	ADC_REFCTRL_REFCOMP_Pos = 0x7
	// Bit mask of REFCOMP field.
	ADC_REFCTRL_REFCOMP_Msk = 0x80
	// Bit REFCOMP.
	ADC_REFCTRL_REFCOMP = 0x80

	// AVGCTRL: Average Control
	// Position of SAMPLENUM field.
	ADC_AVGCTRL_SAMPLENUM_Pos = 0x0
	// Bit mask of SAMPLENUM field.
	ADC_AVGCTRL_SAMPLENUM_Msk = 0xf
	// 1 sample
	ADC_AVGCTRL_SAMPLENUM_1 = 0x0
	// 2 samples
	ADC_AVGCTRL_SAMPLENUM_2 = 0x1
	// 4 samples
	ADC_AVGCTRL_SAMPLENUM_4 = 0x2
	// 8 samples
	ADC_AVGCTRL_SAMPLENUM_8 = 0x3
	// 16 samples
	ADC_AVGCTRL_SAMPLENUM_16 = 0x4
	// 32 samples
	ADC_AVGCTRL_SAMPLENUM_32 = 0x5
	// 64 samples
	ADC_AVGCTRL_SAMPLENUM_64 = 0x6
	// 128 samples
	ADC_AVGCTRL_SAMPLENUM_128 = 0x7
	// 256 samples
	ADC_AVGCTRL_SAMPLENUM_256 = 0x8
	// 512 samples
	ADC_AVGCTRL_SAMPLENUM_512 = 0x9
	// 1024 samples
	ADC_AVGCTRL_SAMPLENUM_1024 = 0xa
	// Position of ADJRES field.
	ADC_AVGCTRL_ADJRES_Pos = 0x4
	// Bit mask of ADJRES field.
	ADC_AVGCTRL_ADJRES_Msk = 0x70

	// SAMPCTRL: Sample Time Control
	// Position of SAMPLEN field.
	ADC_SAMPCTRL_SAMPLEN_Pos = 0x0
	// Bit mask of SAMPLEN field.
	ADC_SAMPCTRL_SAMPLEN_Msk = 0x3f
	// Position of OFFCOMP field.
	ADC_SAMPCTRL_OFFCOMP_Pos = 0x7
	// Bit mask of OFFCOMP field.
	ADC_SAMPCTRL_OFFCOMP_Msk = 0x80
	// Bit OFFCOMP.
	ADC_SAMPCTRL_OFFCOMP = 0x80

	// WINLT: Window Monitor Lower Threshold
	// Position of WINLT field.
	ADC_WINLT_WINLT_Pos = 0x0
	// Bit mask of WINLT field.
	ADC_WINLT_WINLT_Msk = 0xffff

	// WINUT: Window Monitor Upper Threshold
	// Position of WINUT field.
	ADC_WINUT_WINUT_Pos = 0x0
	// Bit mask of WINUT field.
	ADC_WINUT_WINUT_Msk = 0xffff

	// GAINCORR: Gain Correction
	// Position of GAINCORR field.
	ADC_GAINCORR_GAINCORR_Pos = 0x0
	// Bit mask of GAINCORR field.
	ADC_GAINCORR_GAINCORR_Msk = 0xfff

	// OFFSETCORR: Offset Correction
	// Position of OFFSETCORR field.
	ADC_OFFSETCORR_OFFSETCORR_Pos = 0x0
	// Bit mask of OFFSETCORR field.
	ADC_OFFSETCORR_OFFSETCORR_Msk = 0xfff

	// SWTRIG: Software Trigger
	// Position of FLUSH field.
	ADC_SWTRIG_FLUSH_Pos = 0x0
	// Bit mask of FLUSH field.
	ADC_SWTRIG_FLUSH_Msk = 0x1
	// Bit FLUSH.
	ADC_SWTRIG_FLUSH = 0x1
	// Position of START field.
	ADC_SWTRIG_START_Pos = 0x1
	// Bit mask of START field.
	ADC_SWTRIG_START_Msk = 0x2
	// Bit START.
	ADC_SWTRIG_START = 0x2

	// INTENCLR: Interrupt Enable Clear
	// Position of RESRDY field.
	ADC_INTENCLR_RESRDY_Pos = 0x0
	// Bit mask of RESRDY field.
	ADC_INTENCLR_RESRDY_Msk = 0x1
	// Bit RESRDY.
	ADC_INTENCLR_RESRDY = 0x1
	// Position of OVERRUN field.
	ADC_INTENCLR_OVERRUN_Pos = 0x1
	// Bit mask of OVERRUN field.
	ADC_INTENCLR_OVERRUN_Msk = 0x2
	// Bit OVERRUN.
	ADC_INTENCLR_OVERRUN = 0x2
	// Position of WINMON field.
	ADC_INTENCLR_WINMON_Pos = 0x2
	// Bit mask of WINMON field.
	ADC_INTENCLR_WINMON_Msk = 0x4
	// Bit WINMON.
	ADC_INTENCLR_WINMON = 0x4

	// INTENSET: Interrupt Enable Set
	// Position of RESRDY field.
	ADC_INTENSET_RESRDY_Pos = 0x0
	// Bit mask of RESRDY field.
	ADC_INTENSET_RESRDY_Msk = 0x1
	// Bit RESRDY.
	ADC_INTENSET_RESRDY = 0x1
	// Position of OVERRUN field.
	ADC_INTENSET_OVERRUN_Pos = 0x1
	// Bit mask of OVERRUN field.
	ADC_INTENSET_OVERRUN_Msk = 0x2
	// Bit OVERRUN.
	ADC_INTENSET_OVERRUN = 0x2
	// Position of WINMON field.
	ADC_INTENSET_WINMON_Pos = 0x2
	// Bit mask of WINMON field.
	ADC_INTENSET_WINMON_Msk = 0x4
	// Bit WINMON.
	ADC_INTENSET_WINMON = 0x4

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of RESRDY field.
	ADC_INTFLAG_RESRDY_Pos = 0x0
	// Bit mask of RESRDY field.
	ADC_INTFLAG_RESRDY_Msk = 0x1
	// Bit RESRDY.
	ADC_INTFLAG_RESRDY = 0x1
	// Position of OVERRUN field.
	ADC_INTFLAG_OVERRUN_Pos = 0x1
	// Bit mask of OVERRUN field.
	ADC_INTFLAG_OVERRUN_Msk = 0x2
	// Bit OVERRUN.
	ADC_INTFLAG_OVERRUN = 0x2
	// Position of WINMON field.
	ADC_INTFLAG_WINMON_Pos = 0x2
	// Bit mask of WINMON field.
	ADC_INTFLAG_WINMON_Msk = 0x4
	// Bit WINMON.
	ADC_INTFLAG_WINMON = 0x4

	// STATUS: Status
	// Position of ADCBUSY field.
	ADC_STATUS_ADCBUSY_Pos = 0x0
	// Bit mask of ADCBUSY field.
	ADC_STATUS_ADCBUSY_Msk = 0x1
	// Bit ADCBUSY.
	ADC_STATUS_ADCBUSY = 0x1
	// Position of WCC field.
	ADC_STATUS_WCC_Pos = 0x2
	// Bit mask of WCC field.
	ADC_STATUS_WCC_Msk = 0xfc

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	ADC_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	ADC_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	ADC_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	ADC_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	ADC_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	ADC_SYNCBUSY_ENABLE = 0x2
	// Position of INPUTCTRL field.
	ADC_SYNCBUSY_INPUTCTRL_Pos = 0x2
	// Bit mask of INPUTCTRL field.
	ADC_SYNCBUSY_INPUTCTRL_Msk = 0x4
	// Bit INPUTCTRL.
	ADC_SYNCBUSY_INPUTCTRL = 0x4
	// Position of CTRLB field.
	ADC_SYNCBUSY_CTRLB_Pos = 0x3
	// Bit mask of CTRLB field.
	ADC_SYNCBUSY_CTRLB_Msk = 0x8
	// Bit CTRLB.
	ADC_SYNCBUSY_CTRLB = 0x8
	// Position of REFCTRL field.
	ADC_SYNCBUSY_REFCTRL_Pos = 0x4
	// Bit mask of REFCTRL field.
	ADC_SYNCBUSY_REFCTRL_Msk = 0x10
	// Bit REFCTRL.
	ADC_SYNCBUSY_REFCTRL = 0x10
	// Position of AVGCTRL field.
	ADC_SYNCBUSY_AVGCTRL_Pos = 0x5
	// Bit mask of AVGCTRL field.
	ADC_SYNCBUSY_AVGCTRL_Msk = 0x20
	// Bit AVGCTRL.
	ADC_SYNCBUSY_AVGCTRL = 0x20
	// Position of SAMPCTRL field.
	ADC_SYNCBUSY_SAMPCTRL_Pos = 0x6
	// Bit mask of SAMPCTRL field.
	ADC_SYNCBUSY_SAMPCTRL_Msk = 0x40
	// Bit SAMPCTRL.
	ADC_SYNCBUSY_SAMPCTRL = 0x40
	// Position of WINLT field.
	ADC_SYNCBUSY_WINLT_Pos = 0x7
	// Bit mask of WINLT field.
	ADC_SYNCBUSY_WINLT_Msk = 0x80
	// Bit WINLT.
	ADC_SYNCBUSY_WINLT = 0x80
	// Position of WINUT field.
	ADC_SYNCBUSY_WINUT_Pos = 0x8
	// Bit mask of WINUT field.
	ADC_SYNCBUSY_WINUT_Msk = 0x100
	// Bit WINUT.
	ADC_SYNCBUSY_WINUT = 0x100
	// Position of GAINCORR field.
	ADC_SYNCBUSY_GAINCORR_Pos = 0x9
	// Bit mask of GAINCORR field.
	ADC_SYNCBUSY_GAINCORR_Msk = 0x200
	// Bit GAINCORR.
	ADC_SYNCBUSY_GAINCORR = 0x200
	// Position of OFFSETCORR field.
	ADC_SYNCBUSY_OFFSETCORR_Pos = 0xa
	// Bit mask of OFFSETCORR field.
	ADC_SYNCBUSY_OFFSETCORR_Msk = 0x400
	// Bit OFFSETCORR.
	ADC_SYNCBUSY_OFFSETCORR = 0x400
	// Position of SWTRIG field.
	ADC_SYNCBUSY_SWTRIG_Pos = 0xb
	// Bit mask of SWTRIG field.
	ADC_SYNCBUSY_SWTRIG_Msk = 0x800
	// Bit SWTRIG.
	ADC_SYNCBUSY_SWTRIG = 0x800

	// DSEQDATA: DMA Sequencial Data
	// Position of DATA field.
	ADC_DSEQDATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	ADC_DSEQDATA_DATA_Msk = 0xffffffff

	// DSEQCTRL: DMA Sequential Control
	// Position of INPUTCTRL field.
	ADC_DSEQCTRL_INPUTCTRL_Pos = 0x0
	// Bit mask of INPUTCTRL field.
	ADC_DSEQCTRL_INPUTCTRL_Msk = 0x1
	// Bit INPUTCTRL.
	ADC_DSEQCTRL_INPUTCTRL = 0x1
	// Position of CTRLB field.
	ADC_DSEQCTRL_CTRLB_Pos = 0x1
	// Bit mask of CTRLB field.
	ADC_DSEQCTRL_CTRLB_Msk = 0x2
	// Bit CTRLB.
	ADC_DSEQCTRL_CTRLB = 0x2
	// Position of REFCTRL field.
	ADC_DSEQCTRL_REFCTRL_Pos = 0x2
	// Bit mask of REFCTRL field.
	ADC_DSEQCTRL_REFCTRL_Msk = 0x4
	// Bit REFCTRL.
	ADC_DSEQCTRL_REFCTRL = 0x4
	// Position of AVGCTRL field.
	ADC_DSEQCTRL_AVGCTRL_Pos = 0x3
	// Bit mask of AVGCTRL field.
	ADC_DSEQCTRL_AVGCTRL_Msk = 0x8
	// Bit AVGCTRL.
	ADC_DSEQCTRL_AVGCTRL = 0x8
	// Position of SAMPCTRL field.
	ADC_DSEQCTRL_SAMPCTRL_Pos = 0x4
	// Bit mask of SAMPCTRL field.
	ADC_DSEQCTRL_SAMPCTRL_Msk = 0x10
	// Bit SAMPCTRL.
	ADC_DSEQCTRL_SAMPCTRL = 0x10
	// Position of WINLT field.
	ADC_DSEQCTRL_WINLT_Pos = 0x5
	// Bit mask of WINLT field.
	ADC_DSEQCTRL_WINLT_Msk = 0x20
	// Bit WINLT.
	ADC_DSEQCTRL_WINLT = 0x20
	// Position of WINUT field.
	ADC_DSEQCTRL_WINUT_Pos = 0x6
	// Bit mask of WINUT field.
	ADC_DSEQCTRL_WINUT_Msk = 0x40
	// Bit WINUT.
	ADC_DSEQCTRL_WINUT = 0x40
	// Position of GAINCORR field.
	ADC_DSEQCTRL_GAINCORR_Pos = 0x7
	// Bit mask of GAINCORR field.
	ADC_DSEQCTRL_GAINCORR_Msk = 0x80
	// Bit GAINCORR.
	ADC_DSEQCTRL_GAINCORR = 0x80
	// Position of OFFSETCORR field.
	ADC_DSEQCTRL_OFFSETCORR_Pos = 0x8
	// Bit mask of OFFSETCORR field.
	ADC_DSEQCTRL_OFFSETCORR_Msk = 0x100
	// Bit OFFSETCORR.
	ADC_DSEQCTRL_OFFSETCORR = 0x100
	// Position of AUTOSTART field.
	ADC_DSEQCTRL_AUTOSTART_Pos = 0x1f
	// Bit mask of AUTOSTART field.
	ADC_DSEQCTRL_AUTOSTART_Msk = 0x80000000
	// Bit AUTOSTART.
	ADC_DSEQCTRL_AUTOSTART = 0x80000000

	// DSEQSTAT: DMA Sequencial Status
	// Position of INPUTCTRL field.
	ADC_DSEQSTAT_INPUTCTRL_Pos = 0x0
	// Bit mask of INPUTCTRL field.
	ADC_DSEQSTAT_INPUTCTRL_Msk = 0x1
	// Bit INPUTCTRL.
	ADC_DSEQSTAT_INPUTCTRL = 0x1
	// Position of CTRLB field.
	ADC_DSEQSTAT_CTRLB_Pos = 0x1
	// Bit mask of CTRLB field.
	ADC_DSEQSTAT_CTRLB_Msk = 0x2
	// Bit CTRLB.
	ADC_DSEQSTAT_CTRLB = 0x2
	// Position of REFCTRL field.
	ADC_DSEQSTAT_REFCTRL_Pos = 0x2
	// Bit mask of REFCTRL field.
	ADC_DSEQSTAT_REFCTRL_Msk = 0x4
	// Bit REFCTRL.
	ADC_DSEQSTAT_REFCTRL = 0x4
	// Position of AVGCTRL field.
	ADC_DSEQSTAT_AVGCTRL_Pos = 0x3
	// Bit mask of AVGCTRL field.
	ADC_DSEQSTAT_AVGCTRL_Msk = 0x8
	// Bit AVGCTRL.
	ADC_DSEQSTAT_AVGCTRL = 0x8
	// Position of SAMPCTRL field.
	ADC_DSEQSTAT_SAMPCTRL_Pos = 0x4
	// Bit mask of SAMPCTRL field.
	ADC_DSEQSTAT_SAMPCTRL_Msk = 0x10
	// Bit SAMPCTRL.
	ADC_DSEQSTAT_SAMPCTRL = 0x10
	// Position of WINLT field.
	ADC_DSEQSTAT_WINLT_Pos = 0x5
	// Bit mask of WINLT field.
	ADC_DSEQSTAT_WINLT_Msk = 0x20
	// Bit WINLT.
	ADC_DSEQSTAT_WINLT = 0x20
	// Position of WINUT field.
	ADC_DSEQSTAT_WINUT_Pos = 0x6
	// Bit mask of WINUT field.
	ADC_DSEQSTAT_WINUT_Msk = 0x40
	// Bit WINUT.
	ADC_DSEQSTAT_WINUT = 0x40
	// Position of GAINCORR field.
	ADC_DSEQSTAT_GAINCORR_Pos = 0x7
	// Bit mask of GAINCORR field.
	ADC_DSEQSTAT_GAINCORR_Msk = 0x80
	// Bit GAINCORR.
	ADC_DSEQSTAT_GAINCORR = 0x80
	// Position of OFFSETCORR field.
	ADC_DSEQSTAT_OFFSETCORR_Pos = 0x8
	// Bit mask of OFFSETCORR field.
	ADC_DSEQSTAT_OFFSETCORR_Msk = 0x100
	// Bit OFFSETCORR.
	ADC_DSEQSTAT_OFFSETCORR = 0x100
	// Position of BUSY field.
	ADC_DSEQSTAT_BUSY_Pos = 0x1f
	// Bit mask of BUSY field.
	ADC_DSEQSTAT_BUSY_Msk = 0x80000000
	// Bit BUSY.
	ADC_DSEQSTAT_BUSY = 0x80000000

	// RESULT: Result Conversion Value
	// Position of RESULT field.
	ADC_RESULT_RESULT_Pos = 0x0
	// Bit mask of RESULT field.
	ADC_RESULT_RESULT_Msk = 0xffff

	// RESS: Last Sample Result
	// Position of RESS field.
	ADC_RESS_RESS_Pos = 0x0
	// Bit mask of RESS field.
	ADC_RESS_RESS_Msk = 0xffff

	// CALIB: Calibration
	// Position of BIASCOMP field.
	ADC_CALIB_BIASCOMP_Pos = 0x0
	// Bit mask of BIASCOMP field.
	ADC_CALIB_BIASCOMP_Msk = 0x7
	// Position of BIASR2R field.
	ADC_CALIB_BIASR2R_Pos = 0x4
	// Bit mask of BIASR2R field.
	ADC_CALIB_BIASR2R_Msk = 0x70
	// Position of BIASREFBUF field.
	ADC_CALIB_BIASREFBUF_Pos = 0x8
	// Bit mask of BIASREFBUF field.
	ADC_CALIB_BIASREFBUF_Msk = 0x700
)

// Bitfields for AES: Advanced Encryption Standard
const (
	// CTRLA: Control A
	// Position of SWRST field.
	AES_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	AES_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	AES_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	AES_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	AES_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	AES_CTRLA_ENABLE = 0x2
	// Position of AESMODE field.
	AES_CTRLA_AESMODE_Pos = 0x2
	// Bit mask of AESMODE field.
	AES_CTRLA_AESMODE_Msk = 0x1c
	// Electronic code book mode
	AES_CTRLA_AESMODE_ECB = 0x0
	// Cipher block chaining mode
	AES_CTRLA_AESMODE_CBC = 0x1
	// Output feedback mode
	AES_CTRLA_AESMODE_OFB = 0x2
	// Cipher feedback mode
	AES_CTRLA_AESMODE_CFB = 0x3
	// Counter mode
	AES_CTRLA_AESMODE_COUNTER = 0x4
	// CCM mode
	AES_CTRLA_AESMODE_CCM = 0x5
	// Galois counter mode
	AES_CTRLA_AESMODE_GCM = 0x6
	// Position of CFBS field.
	AES_CTRLA_CFBS_Pos = 0x5
	// Bit mask of CFBS field.
	AES_CTRLA_CFBS_Msk = 0xe0
	// 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_128BIT = 0x0
	// 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_64BIT = 0x1
	// 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_32BIT = 0x2
	// 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_16BIT = 0x3
	// 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_8BIT = 0x4
	// Position of KEYSIZE field.
	AES_CTRLA_KEYSIZE_Pos = 0x8
	// Bit mask of KEYSIZE field.
	AES_CTRLA_KEYSIZE_Msk = 0x300
	// 128-bit Key for Encryption / Decryption
	AES_CTRLA_KEYSIZE_128BIT = 0x0
	// 192-bit Key for Encryption / Decryption
	AES_CTRLA_KEYSIZE_192BIT = 0x1
	// 256-bit Key for Encryption / Decryption
	AES_CTRLA_KEYSIZE_256BIT = 0x2
	// Position of CIPHER field.
	AES_CTRLA_CIPHER_Pos = 0xa
	// Bit mask of CIPHER field.
	AES_CTRLA_CIPHER_Msk = 0x400
	// Bit CIPHER.
	AES_CTRLA_CIPHER = 0x400
	// Decryption
	AES_CTRLA_CIPHER_DEC = 0x0
	// Encryption
	AES_CTRLA_CIPHER_ENC = 0x1
	// Position of STARTMODE field.
	AES_CTRLA_STARTMODE_Pos = 0xb
	// Bit mask of STARTMODE field.
	AES_CTRLA_STARTMODE_Msk = 0x800
	// Bit STARTMODE.
	AES_CTRLA_STARTMODE = 0x800
	// Start Encryption / Decryption in Manual mode
	AES_CTRLA_STARTMODE_MANUAL = 0x0
	// Start Encryption / Decryption in Auto mode
	AES_CTRLA_STARTMODE_AUTO = 0x1
	// Position of LOD field.
	AES_CTRLA_LOD_Pos = 0xc
	// Bit mask of LOD field.
	AES_CTRLA_LOD_Msk = 0x1000
	// Bit LOD.
	AES_CTRLA_LOD = 0x1000
	// No effect
	AES_CTRLA_LOD_NONE = 0x0
	// Start encryption in Last Output Data mode
	AES_CTRLA_LOD_LAST = 0x1
	// Position of KEYGEN field.
	AES_CTRLA_KEYGEN_Pos = 0xd
	// Bit mask of KEYGEN field.
	AES_CTRLA_KEYGEN_Msk = 0x2000
	// Bit KEYGEN.
	AES_CTRLA_KEYGEN = 0x2000
	// No effect
	AES_CTRLA_KEYGEN_NONE = 0x0
	// Start Computation of the last NK words of the expanded key
	AES_CTRLA_KEYGEN_LAST = 0x1
	// Position of XORKEY field.
	AES_CTRLA_XORKEY_Pos = 0xe
	// Bit mask of XORKEY field.
	AES_CTRLA_XORKEY_Msk = 0x4000
	// Bit XORKEY.
	AES_CTRLA_XORKEY = 0x4000
	// No effect
	AES_CTRLA_XORKEY_NONE = 0x0
	// The user keyword gets XORed with the previous keyword register content.
	AES_CTRLA_XORKEY_XOR = 0x1
	// Position of CTYPE field.
	AES_CTRLA_CTYPE_Pos = 0x10
	// Bit mask of CTYPE field.
	AES_CTRLA_CTYPE_Msk = 0xf0000

	// CTRLB: Control B
	// Position of START field.
	AES_CTRLB_START_Pos = 0x0
	// Bit mask of START field.
	AES_CTRLB_START_Msk = 0x1
	// Bit START.
	AES_CTRLB_START = 0x1
	// Position of NEWMSG field.
	AES_CTRLB_NEWMSG_Pos = 0x1
	// Bit mask of NEWMSG field.
	AES_CTRLB_NEWMSG_Msk = 0x2
	// Bit NEWMSG.
	AES_CTRLB_NEWMSG = 0x2
	// Position of EOM field.
	AES_CTRLB_EOM_Pos = 0x2
	// Bit mask of EOM field.
	AES_CTRLB_EOM_Msk = 0x4
	// Bit EOM.
	AES_CTRLB_EOM = 0x4
	// Position of GFMUL field.
	AES_CTRLB_GFMUL_Pos = 0x3
	// Bit mask of GFMUL field.
	AES_CTRLB_GFMUL_Msk = 0x8
	// Bit GFMUL.
	AES_CTRLB_GFMUL = 0x8

	// INTENCLR: Interrupt Enable Clear
	// Position of ENCCMP field.
	AES_INTENCLR_ENCCMP_Pos = 0x0
	// Bit mask of ENCCMP field.
	AES_INTENCLR_ENCCMP_Msk = 0x1
	// Bit ENCCMP.
	AES_INTENCLR_ENCCMP = 0x1
	// Position of GFMCMP field.
	AES_INTENCLR_GFMCMP_Pos = 0x1
	// Bit mask of GFMCMP field.
	AES_INTENCLR_GFMCMP_Msk = 0x2
	// Bit GFMCMP.
	AES_INTENCLR_GFMCMP = 0x2

	// INTENSET: Interrupt Enable Set
	// Position of ENCCMP field.
	AES_INTENSET_ENCCMP_Pos = 0x0
	// Bit mask of ENCCMP field.
	AES_INTENSET_ENCCMP_Msk = 0x1
	// Bit ENCCMP.
	AES_INTENSET_ENCCMP = 0x1
	// Position of GFMCMP field.
	AES_INTENSET_GFMCMP_Pos = 0x1
	// Bit mask of GFMCMP field.
	AES_INTENSET_GFMCMP_Msk = 0x2
	// Bit GFMCMP.
	AES_INTENSET_GFMCMP = 0x2

	// INTFLAG: Interrupt Flag Status
	// Position of ENCCMP field.
	AES_INTFLAG_ENCCMP_Pos = 0x0
	// Bit mask of ENCCMP field.
	AES_INTFLAG_ENCCMP_Msk = 0x1
	// Bit ENCCMP.
	AES_INTFLAG_ENCCMP = 0x1
	// Position of GFMCMP field.
	AES_INTFLAG_GFMCMP_Pos = 0x1
	// Bit mask of GFMCMP field.
	AES_INTFLAG_GFMCMP_Msk = 0x2
	// Bit GFMCMP.
	AES_INTFLAG_GFMCMP = 0x2

	// DATABUFPTR: Data buffer pointer
	// Position of INDATAPTR field.
	AES_DATABUFPTR_INDATAPTR_Pos = 0x0
	// Bit mask of INDATAPTR field.
	AES_DATABUFPTR_INDATAPTR_Msk = 0x3

	// DBGCTRL: Debug control
	// Position of DBGRUN field.
	AES_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	AES_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	AES_DBGCTRL_DBGRUN = 0x1
)

// Bitfields for CAN0: Control Area Network
const (
	// CREL: Core Release
	// Position of SUBSTEP field.
	CAN_CREL_SUBSTEP_Pos = 0x14
	// Bit mask of SUBSTEP field.
	CAN_CREL_SUBSTEP_Msk = 0xf00000
	// Position of STEP field.
	CAN_CREL_STEP_Pos = 0x18
	// Bit mask of STEP field.
	CAN_CREL_STEP_Msk = 0xf000000
	// Position of REL field.
	CAN_CREL_REL_Pos = 0x1c
	// Bit mask of REL field.
	CAN_CREL_REL_Msk = 0xf0000000

	// ENDN: Endian
	// Position of ETV field.
	CAN_ENDN_ETV_Pos = 0x0
	// Bit mask of ETV field.
	CAN_ENDN_ETV_Msk = 0xffffffff

	// MRCFG: Message RAM Configuration
	// Position of QOS field.
	CAN_MRCFG_QOS_Pos = 0x0
	// Bit mask of QOS field.
	CAN_MRCFG_QOS_Msk = 0x3
	// Background (no sensitive operation)
	CAN_MRCFG_QOS_DISABLE = 0x0
	// Sensitive Bandwidth
	CAN_MRCFG_QOS_LOW = 0x1
	// Sensitive Latency
	CAN_MRCFG_QOS_MEDIUM = 0x2
	// Critical Latency
	CAN_MRCFG_QOS_HIGH = 0x3

	// DBTP: Fast Bit Timing and Prescaler
	// Position of DSJW field.
	CAN_DBTP_DSJW_Pos = 0x0
	// Bit mask of DSJW field.
	CAN_DBTP_DSJW_Msk = 0xf
	// Position of DTSEG2 field.
	CAN_DBTP_DTSEG2_Pos = 0x4
	// Bit mask of DTSEG2 field.
	CAN_DBTP_DTSEG2_Msk = 0xf0
	// Position of DTSEG1 field.
	CAN_DBTP_DTSEG1_Pos = 0x8
	// Bit mask of DTSEG1 field.
	CAN_DBTP_DTSEG1_Msk = 0x1f00
	// Position of DBRP field.
	CAN_DBTP_DBRP_Pos = 0x10
	// Bit mask of DBRP field.
	CAN_DBTP_DBRP_Msk = 0x1f0000
	// Position of TDC field.
	CAN_DBTP_TDC_Pos = 0x17
	// Bit mask of TDC field.
	CAN_DBTP_TDC_Msk = 0x800000
	// Bit TDC.
	CAN_DBTP_TDC = 0x800000

	// TEST: Test
	// Position of LBCK field.
	CAN_TEST_LBCK_Pos = 0x4
	// Bit mask of LBCK field.
	CAN_TEST_LBCK_Msk = 0x10
	// Bit LBCK.
	CAN_TEST_LBCK = 0x10
	// Position of TX field.
	CAN_TEST_TX_Pos = 0x5
	// Bit mask of TX field.
	CAN_TEST_TX_Msk = 0x60
	// TX controlled by CAN core
	CAN_TEST_TX_CORE = 0x0
	// TX monitoring sample point
	CAN_TEST_TX_SAMPLE = 0x1
	// Dominant (0) level at pin CAN_TX
	CAN_TEST_TX_DOMINANT = 0x2
	// Recessive (1) level at pin CAN_TX
	CAN_TEST_TX_RECESSIVE = 0x3
	// Position of RX field.
	CAN_TEST_RX_Pos = 0x7
	// Bit mask of RX field.
	CAN_TEST_RX_Msk = 0x80
	// Bit RX.
	CAN_TEST_RX = 0x80

	// RWD: RAM Watchdog
	// Position of WDC field.
	CAN_RWD_WDC_Pos = 0x0
	// Bit mask of WDC field.
	CAN_RWD_WDC_Msk = 0xff
	// Position of WDV field.
	CAN_RWD_WDV_Pos = 0x8
	// Bit mask of WDV field.
	CAN_RWD_WDV_Msk = 0xff00

	// CCCR: CC Control
	// Position of INIT field.
	CAN_CCCR_INIT_Pos = 0x0
	// Bit mask of INIT field.
	CAN_CCCR_INIT_Msk = 0x1
	// Bit INIT.
	CAN_CCCR_INIT = 0x1
	// Position of CCE field.
	CAN_CCCR_CCE_Pos = 0x1
	// Bit mask of CCE field.
	CAN_CCCR_CCE_Msk = 0x2
	// Bit CCE.
	CAN_CCCR_CCE = 0x2
	// Position of ASM field.
	CAN_CCCR_ASM_Pos = 0x2
	// Bit mask of ASM field.
	CAN_CCCR_ASM_Msk = 0x4
	// Bit ASM.
	CAN_CCCR_ASM = 0x4
	// Position of CSA field.
	CAN_CCCR_CSA_Pos = 0x3
	// Bit mask of CSA field.
	CAN_CCCR_CSA_Msk = 0x8
	// Bit CSA.
	CAN_CCCR_CSA = 0x8
	// Position of CSR field.
	CAN_CCCR_CSR_Pos = 0x4
	// Bit mask of CSR field.
	CAN_CCCR_CSR_Msk = 0x10
	// Bit CSR.
	CAN_CCCR_CSR = 0x10
	// Position of MON field.
	CAN_CCCR_MON_Pos = 0x5
	// Bit mask of MON field.
	CAN_CCCR_MON_Msk = 0x20
	// Bit MON.
	CAN_CCCR_MON = 0x20
	// Position of DAR field.
	CAN_CCCR_DAR_Pos = 0x6
	// Bit mask of DAR field.
	CAN_CCCR_DAR_Msk = 0x40
	// Bit DAR.
	CAN_CCCR_DAR = 0x40
	// Position of TEST field.
	CAN_CCCR_TEST_Pos = 0x7
	// Bit mask of TEST field.
	CAN_CCCR_TEST_Msk = 0x80
	// Bit TEST.
	CAN_CCCR_TEST = 0x80
	// Position of FDOE field.
	CAN_CCCR_FDOE_Pos = 0x8
	// Bit mask of FDOE field.
	CAN_CCCR_FDOE_Msk = 0x100
	// Bit FDOE.
	CAN_CCCR_FDOE = 0x100
	// Position of BRSE field.
	CAN_CCCR_BRSE_Pos = 0x9
	// Bit mask of BRSE field.
	CAN_CCCR_BRSE_Msk = 0x200
	// Bit BRSE.
	CAN_CCCR_BRSE = 0x200
	// Position of PXHD field.
	CAN_CCCR_PXHD_Pos = 0xc
	// Bit mask of PXHD field.
	CAN_CCCR_PXHD_Msk = 0x1000
	// Bit PXHD.
	CAN_CCCR_PXHD = 0x1000
	// Position of EFBI field.
	CAN_CCCR_EFBI_Pos = 0xd
	// Bit mask of EFBI field.
	CAN_CCCR_EFBI_Msk = 0x2000
	// Bit EFBI.
	CAN_CCCR_EFBI = 0x2000
	// Position of TXP field.
	CAN_CCCR_TXP_Pos = 0xe
	// Bit mask of TXP field.
	CAN_CCCR_TXP_Msk = 0x4000
	// Bit TXP.
	CAN_CCCR_TXP = 0x4000
	// Position of NISO field.
	CAN_CCCR_NISO_Pos = 0xf
	// Bit mask of NISO field.
	CAN_CCCR_NISO_Msk = 0x8000
	// Bit NISO.
	CAN_CCCR_NISO = 0x8000

	// NBTP: Nominal Bit Timing and Prescaler
	// Position of NTSEG2 field.
	CAN_NBTP_NTSEG2_Pos = 0x0
	// Bit mask of NTSEG2 field.
	CAN_NBTP_NTSEG2_Msk = 0x7f
	// Position of NTSEG1 field.
	CAN_NBTP_NTSEG1_Pos = 0x8
	// Bit mask of NTSEG1 field.
	CAN_NBTP_NTSEG1_Msk = 0xff00
	// Position of NBRP field.
	CAN_NBTP_NBRP_Pos = 0x10
	// Bit mask of NBRP field.
	CAN_NBTP_NBRP_Msk = 0x1ff0000
	// Position of NSJW field.
	CAN_NBTP_NSJW_Pos = 0x19
	// Bit mask of NSJW field.
	CAN_NBTP_NSJW_Msk = 0xfe000000

	// TSCC: Timestamp Counter Configuration
	// Position of TSS field.
	CAN_TSCC_TSS_Pos = 0x0
	// Bit mask of TSS field.
	CAN_TSCC_TSS_Msk = 0x3
	// Timestamp counter value always 0x0000
	CAN_TSCC_TSS_ZERO = 0x0
	// Timestamp counter value incremented by TCP
	CAN_TSCC_TSS_INC = 0x1
	// External timestamp counter value used
	CAN_TSCC_TSS_EXT = 0x2
	// Position of TCP field.
	CAN_TSCC_TCP_Pos = 0x10
	// Bit mask of TCP field.
	CAN_TSCC_TCP_Msk = 0xf0000

	// TSCV: Timestamp Counter Value
	// Position of TSC field.
	CAN_TSCV_TSC_Pos = 0x0
	// Bit mask of TSC field.
	CAN_TSCV_TSC_Msk = 0xffff

	// TOCC: Timeout Counter Configuration
	// Position of ETOC field.
	CAN_TOCC_ETOC_Pos = 0x0
	// Bit mask of ETOC field.
	CAN_TOCC_ETOC_Msk = 0x1
	// Bit ETOC.
	CAN_TOCC_ETOC = 0x1
	// Position of TOS field.
	CAN_TOCC_TOS_Pos = 0x1
	// Bit mask of TOS field.
	CAN_TOCC_TOS_Msk = 0x6
	// Continuout operation
	CAN_TOCC_TOS_CONT = 0x0
	// Timeout controlled by TX Event FIFO
	CAN_TOCC_TOS_TXEF = 0x1
	// Timeout controlled by Rx FIFO 0
	CAN_TOCC_TOS_RXF0 = 0x2
	// Timeout controlled by Rx FIFO 1
	CAN_TOCC_TOS_RXF1 = 0x3
	// Position of TOP field.
	CAN_TOCC_TOP_Pos = 0x10
	// Bit mask of TOP field.
	CAN_TOCC_TOP_Msk = 0xffff0000

	// TOCV: Timeout Counter Value
	// Position of TOC field.
	CAN_TOCV_TOC_Pos = 0x0
	// Bit mask of TOC field.
	CAN_TOCV_TOC_Msk = 0xffff

	// ECR: Error Counter
	// Position of TEC field.
	CAN_ECR_TEC_Pos = 0x0
	// Bit mask of TEC field.
	CAN_ECR_TEC_Msk = 0xff
	// Position of REC field.
	CAN_ECR_REC_Pos = 0x8
	// Bit mask of REC field.
	CAN_ECR_REC_Msk = 0x7f00
	// Position of RP field.
	CAN_ECR_RP_Pos = 0xf
	// Bit mask of RP field.
	CAN_ECR_RP_Msk = 0x8000
	// Bit RP.
	CAN_ECR_RP = 0x8000
	// Position of CEL field.
	CAN_ECR_CEL_Pos = 0x10
	// Bit mask of CEL field.
	CAN_ECR_CEL_Msk = 0xff0000

	// PSR: Protocol Status
	// Position of LEC field.
	CAN_PSR_LEC_Pos = 0x0
	// Bit mask of LEC field.
	CAN_PSR_LEC_Msk = 0x7
	// No Error
	CAN_PSR_LEC_NONE = 0x0
	// Stuff Error
	CAN_PSR_LEC_STUFF = 0x1
	// Form Error
	CAN_PSR_LEC_FORM = 0x2
	// Ack Error
	CAN_PSR_LEC_ACK = 0x3
	// Bit1 Error
	CAN_PSR_LEC_BIT1 = 0x4
	// Bit0 Error
	CAN_PSR_LEC_BIT0 = 0x5
	// CRC Error
	CAN_PSR_LEC_CRC = 0x6
	// No Change
	CAN_PSR_LEC_NC = 0x7
	// Position of ACT field.
	CAN_PSR_ACT_Pos = 0x3
	// Bit mask of ACT field.
	CAN_PSR_ACT_Msk = 0x18
	// Node is synchronizing on CAN communication
	CAN_PSR_ACT_SYNC = 0x0
	// Node is neither receiver nor transmitter
	CAN_PSR_ACT_IDLE = 0x1
	// Node is operating as receiver
	CAN_PSR_ACT_RX = 0x2
	// Node is operating as transmitter
	CAN_PSR_ACT_TX = 0x3
	// Position of EP field.
	CAN_PSR_EP_Pos = 0x5
	// Bit mask of EP field.
	CAN_PSR_EP_Msk = 0x20
	// Bit EP.
	CAN_PSR_EP = 0x20
	// Position of EW field.
	CAN_PSR_EW_Pos = 0x6
	// Bit mask of EW field.
	CAN_PSR_EW_Msk = 0x40
	// Bit EW.
	CAN_PSR_EW = 0x40
	// Position of BO field.
	CAN_PSR_BO_Pos = 0x7
	// Bit mask of BO field.
	CAN_PSR_BO_Msk = 0x80
	// Bit BO.
	CAN_PSR_BO = 0x80
	// Position of DLEC field.
	CAN_PSR_DLEC_Pos = 0x8
	// Bit mask of DLEC field.
	CAN_PSR_DLEC_Msk = 0x700
	// No Error
	CAN_PSR_DLEC_NONE = 0x0
	// Stuff Error
	CAN_PSR_DLEC_STUFF = 0x1
	// Form Error
	CAN_PSR_DLEC_FORM = 0x2
	// Ack Error
	CAN_PSR_DLEC_ACK = 0x3
	// Bit1 Error
	CAN_PSR_DLEC_BIT1 = 0x4
	// Bit0 Error
	CAN_PSR_DLEC_BIT0 = 0x5
	// CRC Error
	CAN_PSR_DLEC_CRC = 0x6
	// No Change
	CAN_PSR_DLEC_NC = 0x7
	// Position of RESI field.
	CAN_PSR_RESI_Pos = 0xb
	// Bit mask of RESI field.
	CAN_PSR_RESI_Msk = 0x800
	// Bit RESI.
	CAN_PSR_RESI = 0x800
	// Position of RBRS field.
	CAN_PSR_RBRS_Pos = 0xc
	// Bit mask of RBRS field.
	CAN_PSR_RBRS_Msk = 0x1000
	// Bit RBRS.
	CAN_PSR_RBRS = 0x1000
	// Position of RFDF field.
	CAN_PSR_RFDF_Pos = 0xd
	// Bit mask of RFDF field.
	CAN_PSR_RFDF_Msk = 0x2000
	// Bit RFDF.
	CAN_PSR_RFDF = 0x2000
	// Position of PXE field.
	CAN_PSR_PXE_Pos = 0xe
	// Bit mask of PXE field.
	CAN_PSR_PXE_Msk = 0x4000
	// Bit PXE.
	CAN_PSR_PXE = 0x4000
	// Position of TDCV field.
	CAN_PSR_TDCV_Pos = 0x10
	// Bit mask of TDCV field.
	CAN_PSR_TDCV_Msk = 0x7f0000

	// TDCR: Extended ID Filter Configuration
	// Position of TDCF field.
	CAN_TDCR_TDCF_Pos = 0x0
	// Bit mask of TDCF field.
	CAN_TDCR_TDCF_Msk = 0x7f
	// Position of TDCO field.
	CAN_TDCR_TDCO_Pos = 0x8
	// Bit mask of TDCO field.
	CAN_TDCR_TDCO_Msk = 0x7f00

	// IR: Interrupt
	// Position of RF0N field.
	CAN_IR_RF0N_Pos = 0x0
	// Bit mask of RF0N field.
	CAN_IR_RF0N_Msk = 0x1
	// Bit RF0N.
	CAN_IR_RF0N = 0x1
	// Position of RF0W field.
	CAN_IR_RF0W_Pos = 0x1
	// Bit mask of RF0W field.
	CAN_IR_RF0W_Msk = 0x2
	// Bit RF0W.
	CAN_IR_RF0W = 0x2
	// Position of RF0F field.
	CAN_IR_RF0F_Pos = 0x2
	// Bit mask of RF0F field.
	CAN_IR_RF0F_Msk = 0x4
	// Bit RF0F.
	CAN_IR_RF0F = 0x4
	// Position of RF0L field.
	CAN_IR_RF0L_Pos = 0x3
	// Bit mask of RF0L field.
	CAN_IR_RF0L_Msk = 0x8
	// Bit RF0L.
	CAN_IR_RF0L = 0x8
	// Position of RF1N field.
	CAN_IR_RF1N_Pos = 0x4
	// Bit mask of RF1N field.
	CAN_IR_RF1N_Msk = 0x10
	// Bit RF1N.
	CAN_IR_RF1N = 0x10
	// Position of RF1W field.
	CAN_IR_RF1W_Pos = 0x5
	// Bit mask of RF1W field.
	CAN_IR_RF1W_Msk = 0x20
	// Bit RF1W.
	CAN_IR_RF1W = 0x20
	// Position of RF1F field.
	CAN_IR_RF1F_Pos = 0x6
	// Bit mask of RF1F field.
	CAN_IR_RF1F_Msk = 0x40
	// Bit RF1F.
	CAN_IR_RF1F = 0x40
	// Position of RF1L field.
	CAN_IR_RF1L_Pos = 0x7
	// Bit mask of RF1L field.
	CAN_IR_RF1L_Msk = 0x80
	// Bit RF1L.
	CAN_IR_RF1L = 0x80
	// Position of HPM field.
	CAN_IR_HPM_Pos = 0x8
	// Bit mask of HPM field.
	CAN_IR_HPM_Msk = 0x100
	// Bit HPM.
	CAN_IR_HPM = 0x100
	// Position of TC field.
	CAN_IR_TC_Pos = 0x9
	// Bit mask of TC field.
	CAN_IR_TC_Msk = 0x200
	// Bit TC.
	CAN_IR_TC = 0x200
	// Position of TCF field.
	CAN_IR_TCF_Pos = 0xa
	// Bit mask of TCF field.
	CAN_IR_TCF_Msk = 0x400
	// Bit TCF.
	CAN_IR_TCF = 0x400
	// Position of TFE field.
	CAN_IR_TFE_Pos = 0xb
	// Bit mask of TFE field.
	CAN_IR_TFE_Msk = 0x800
	// Bit TFE.
	CAN_IR_TFE = 0x800
	// Position of TEFN field.
	CAN_IR_TEFN_Pos = 0xc
	// Bit mask of TEFN field.
	CAN_IR_TEFN_Msk = 0x1000
	// Bit TEFN.
	CAN_IR_TEFN = 0x1000
	// Position of TEFW field.
	CAN_IR_TEFW_Pos = 0xd
	// Bit mask of TEFW field.
	CAN_IR_TEFW_Msk = 0x2000
	// Bit TEFW.
	CAN_IR_TEFW = 0x2000
	// Position of TEFF field.
	CAN_IR_TEFF_Pos = 0xe
	// Bit mask of TEFF field.
	CAN_IR_TEFF_Msk = 0x4000
	// Bit TEFF.
	CAN_IR_TEFF = 0x4000
	// Position of TEFL field.
	CAN_IR_TEFL_Pos = 0xf
	// Bit mask of TEFL field.
	CAN_IR_TEFL_Msk = 0x8000
	// Bit TEFL.
	CAN_IR_TEFL = 0x8000
	// Position of TSW field.
	CAN_IR_TSW_Pos = 0x10
	// Bit mask of TSW field.
	CAN_IR_TSW_Msk = 0x10000
	// Bit TSW.
	CAN_IR_TSW = 0x10000
	// Position of MRAF field.
	CAN_IR_MRAF_Pos = 0x11
	// Bit mask of MRAF field.
	CAN_IR_MRAF_Msk = 0x20000
	// Bit MRAF.
	CAN_IR_MRAF = 0x20000
	// Position of TOO field.
	CAN_IR_TOO_Pos = 0x12
	// Bit mask of TOO field.
	CAN_IR_TOO_Msk = 0x40000
	// Bit TOO.
	CAN_IR_TOO = 0x40000
	// Position of DRX field.
	CAN_IR_DRX_Pos = 0x13
	// Bit mask of DRX field.
	CAN_IR_DRX_Msk = 0x80000
	// Bit DRX.
	CAN_IR_DRX = 0x80000
	// Position of BEC field.
	CAN_IR_BEC_Pos = 0x14
	// Bit mask of BEC field.
	CAN_IR_BEC_Msk = 0x100000
	// Bit BEC.
	CAN_IR_BEC = 0x100000
	// Position of BEU field.
	CAN_IR_BEU_Pos = 0x15
	// Bit mask of BEU field.
	CAN_IR_BEU_Msk = 0x200000
	// Bit BEU.
	CAN_IR_BEU = 0x200000
	// Position of ELO field.
	CAN_IR_ELO_Pos = 0x16
	// Bit mask of ELO field.
	CAN_IR_ELO_Msk = 0x400000
	// Bit ELO.
	CAN_IR_ELO = 0x400000
	// Position of EP field.
	CAN_IR_EP_Pos = 0x17
	// Bit mask of EP field.
	CAN_IR_EP_Msk = 0x800000
	// Bit EP.
	CAN_IR_EP = 0x800000
	// Position of EW field.
	CAN_IR_EW_Pos = 0x18
	// Bit mask of EW field.
	CAN_IR_EW_Msk = 0x1000000
	// Bit EW.
	CAN_IR_EW = 0x1000000
	// Position of BO field.
	CAN_IR_BO_Pos = 0x19
	// Bit mask of BO field.
	CAN_IR_BO_Msk = 0x2000000
	// Bit BO.
	CAN_IR_BO = 0x2000000
	// Position of WDI field.
	CAN_IR_WDI_Pos = 0x1a
	// Bit mask of WDI field.
	CAN_IR_WDI_Msk = 0x4000000
	// Bit WDI.
	CAN_IR_WDI = 0x4000000
	// Position of PEA field.
	CAN_IR_PEA_Pos = 0x1b
	// Bit mask of PEA field.
	CAN_IR_PEA_Msk = 0x8000000
	// Bit PEA.
	CAN_IR_PEA = 0x8000000
	// Position of PED field.
	CAN_IR_PED_Pos = 0x1c
	// Bit mask of PED field.
	CAN_IR_PED_Msk = 0x10000000
	// Bit PED.
	CAN_IR_PED = 0x10000000
	// Position of ARA field.
	CAN_IR_ARA_Pos = 0x1d
	// Bit mask of ARA field.
	CAN_IR_ARA_Msk = 0x20000000
	// Bit ARA.
	CAN_IR_ARA = 0x20000000

	// IE: Interrupt Enable
	// Position of RF0NE field.
	CAN_IE_RF0NE_Pos = 0x0
	// Bit mask of RF0NE field.
	CAN_IE_RF0NE_Msk = 0x1
	// Bit RF0NE.
	CAN_IE_RF0NE = 0x1
	// Position of RF0WE field.
	CAN_IE_RF0WE_Pos = 0x1
	// Bit mask of RF0WE field.
	CAN_IE_RF0WE_Msk = 0x2
	// Bit RF0WE.
	CAN_IE_RF0WE = 0x2
	// Position of RF0FE field.
	CAN_IE_RF0FE_Pos = 0x2
	// Bit mask of RF0FE field.
	CAN_IE_RF0FE_Msk = 0x4
	// Bit RF0FE.
	CAN_IE_RF0FE = 0x4
	// Position of RF0LE field.
	CAN_IE_RF0LE_Pos = 0x3
	// Bit mask of RF0LE field.
	CAN_IE_RF0LE_Msk = 0x8
	// Bit RF0LE.
	CAN_IE_RF0LE = 0x8
	// Position of RF1NE field.
	CAN_IE_RF1NE_Pos = 0x4
	// Bit mask of RF1NE field.
	CAN_IE_RF1NE_Msk = 0x10
	// Bit RF1NE.
	CAN_IE_RF1NE = 0x10
	// Position of RF1WE field.
	CAN_IE_RF1WE_Pos = 0x5
	// Bit mask of RF1WE field.
	CAN_IE_RF1WE_Msk = 0x20
	// Bit RF1WE.
	CAN_IE_RF1WE = 0x20
	// Position of RF1FE field.
	CAN_IE_RF1FE_Pos = 0x6
	// Bit mask of RF1FE field.
	CAN_IE_RF1FE_Msk = 0x40
	// Bit RF1FE.
	CAN_IE_RF1FE = 0x40
	// Position of RF1LE field.
	CAN_IE_RF1LE_Pos = 0x7
	// Bit mask of RF1LE field.
	CAN_IE_RF1LE_Msk = 0x80
	// Bit RF1LE.
	CAN_IE_RF1LE = 0x80
	// Position of HPME field.
	CAN_IE_HPME_Pos = 0x8
	// Bit mask of HPME field.
	CAN_IE_HPME_Msk = 0x100
	// Bit HPME.
	CAN_IE_HPME = 0x100
	// Position of TCE field.
	CAN_IE_TCE_Pos = 0x9
	// Bit mask of TCE field.
	CAN_IE_TCE_Msk = 0x200
	// Bit TCE.
	CAN_IE_TCE = 0x200
	// Position of TCFE field.
	CAN_IE_TCFE_Pos = 0xa
	// Bit mask of TCFE field.
	CAN_IE_TCFE_Msk = 0x400
	// Bit TCFE.
	CAN_IE_TCFE = 0x400
	// Position of TFEE field.
	CAN_IE_TFEE_Pos = 0xb
	// Bit mask of TFEE field.
	CAN_IE_TFEE_Msk = 0x800
	// Bit TFEE.
	CAN_IE_TFEE = 0x800
	// Position of TEFNE field.
	CAN_IE_TEFNE_Pos = 0xc
	// Bit mask of TEFNE field.
	CAN_IE_TEFNE_Msk = 0x1000
	// Bit TEFNE.
	CAN_IE_TEFNE = 0x1000
	// Position of TEFWE field.
	CAN_IE_TEFWE_Pos = 0xd
	// Bit mask of TEFWE field.
	CAN_IE_TEFWE_Msk = 0x2000
	// Bit TEFWE.
	CAN_IE_TEFWE = 0x2000
	// Position of TEFFE field.
	CAN_IE_TEFFE_Pos = 0xe
	// Bit mask of TEFFE field.
	CAN_IE_TEFFE_Msk = 0x4000
	// Bit TEFFE.
	CAN_IE_TEFFE = 0x4000
	// Position of TEFLE field.
	CAN_IE_TEFLE_Pos = 0xf
	// Bit mask of TEFLE field.
	CAN_IE_TEFLE_Msk = 0x8000
	// Bit TEFLE.
	CAN_IE_TEFLE = 0x8000
	// Position of TSWE field.
	CAN_IE_TSWE_Pos = 0x10
	// Bit mask of TSWE field.
	CAN_IE_TSWE_Msk = 0x10000
	// Bit TSWE.
	CAN_IE_TSWE = 0x10000
	// Position of MRAFE field.
	CAN_IE_MRAFE_Pos = 0x11
	// Bit mask of MRAFE field.
	CAN_IE_MRAFE_Msk = 0x20000
	// Bit MRAFE.
	CAN_IE_MRAFE = 0x20000
	// Position of TOOE field.
	CAN_IE_TOOE_Pos = 0x12
	// Bit mask of TOOE field.
	CAN_IE_TOOE_Msk = 0x40000
	// Bit TOOE.
	CAN_IE_TOOE = 0x40000
	// Position of DRXE field.
	CAN_IE_DRXE_Pos = 0x13
	// Bit mask of DRXE field.
	CAN_IE_DRXE_Msk = 0x80000
	// Bit DRXE.
	CAN_IE_DRXE = 0x80000
	// Position of BECE field.
	CAN_IE_BECE_Pos = 0x14
	// Bit mask of BECE field.
	CAN_IE_BECE_Msk = 0x100000
	// Bit BECE.
	CAN_IE_BECE = 0x100000
	// Position of BEUE field.
	CAN_IE_BEUE_Pos = 0x15
	// Bit mask of BEUE field.
	CAN_IE_BEUE_Msk = 0x200000
	// Bit BEUE.
	CAN_IE_BEUE = 0x200000
	// Position of ELOE field.
	CAN_IE_ELOE_Pos = 0x16
	// Bit mask of ELOE field.
	CAN_IE_ELOE_Msk = 0x400000
	// Bit ELOE.
	CAN_IE_ELOE = 0x400000
	// Position of EPE field.
	CAN_IE_EPE_Pos = 0x17
	// Bit mask of EPE field.
	CAN_IE_EPE_Msk = 0x800000
	// Bit EPE.
	CAN_IE_EPE = 0x800000
	// Position of EWE field.
	CAN_IE_EWE_Pos = 0x18
	// Bit mask of EWE field.
	CAN_IE_EWE_Msk = 0x1000000
	// Bit EWE.
	CAN_IE_EWE = 0x1000000
	// Position of BOE field.
	CAN_IE_BOE_Pos = 0x19
	// Bit mask of BOE field.
	CAN_IE_BOE_Msk = 0x2000000
	// Bit BOE.
	CAN_IE_BOE = 0x2000000
	// Position of WDIE field.
	CAN_IE_WDIE_Pos = 0x1a
	// Bit mask of WDIE field.
	CAN_IE_WDIE_Msk = 0x4000000
	// Bit WDIE.
	CAN_IE_WDIE = 0x4000000
	// Position of PEAE field.
	CAN_IE_PEAE_Pos = 0x1b
	// Bit mask of PEAE field.
	CAN_IE_PEAE_Msk = 0x8000000
	// Bit PEAE.
	CAN_IE_PEAE = 0x8000000
	// Position of PEDE field.
	CAN_IE_PEDE_Pos = 0x1c
	// Bit mask of PEDE field.
	CAN_IE_PEDE_Msk = 0x10000000
	// Bit PEDE.
	CAN_IE_PEDE = 0x10000000
	// Position of ARAE field.
	CAN_IE_ARAE_Pos = 0x1d
	// Bit mask of ARAE field.
	CAN_IE_ARAE_Msk = 0x20000000
	// Bit ARAE.
	CAN_IE_ARAE = 0x20000000

	// ILS: Interrupt Line Select
	// Position of RF0NL field.
	CAN_ILS_RF0NL_Pos = 0x0
	// Bit mask of RF0NL field.
	CAN_ILS_RF0NL_Msk = 0x1
	// Bit RF0NL.
	CAN_ILS_RF0NL = 0x1
	// Position of RF0WL field.
	CAN_ILS_RF0WL_Pos = 0x1
	// Bit mask of RF0WL field.
	CAN_ILS_RF0WL_Msk = 0x2
	// Bit RF0WL.
	CAN_ILS_RF0WL = 0x2
	// Position of RF0FL field.
	CAN_ILS_RF0FL_Pos = 0x2
	// Bit mask of RF0FL field.
	CAN_ILS_RF0FL_Msk = 0x4
	// Bit RF0FL.
	CAN_ILS_RF0FL = 0x4
	// Position of RF0LL field.
	CAN_ILS_RF0LL_Pos = 0x3
	// Bit mask of RF0LL field.
	CAN_ILS_RF0LL_Msk = 0x8
	// Bit RF0LL.
	CAN_ILS_RF0LL = 0x8
	// Position of RF1NL field.
	CAN_ILS_RF1NL_Pos = 0x4
	// Bit mask of RF1NL field.
	CAN_ILS_RF1NL_Msk = 0x10
	// Bit RF1NL.
	CAN_ILS_RF1NL = 0x10
	// Position of RF1WL field.
	CAN_ILS_RF1WL_Pos = 0x5
	// Bit mask of RF1WL field.
	CAN_ILS_RF1WL_Msk = 0x20
	// Bit RF1WL.
	CAN_ILS_RF1WL = 0x20
	// Position of RF1FL field.
	CAN_ILS_RF1FL_Pos = 0x6
	// Bit mask of RF1FL field.
	CAN_ILS_RF1FL_Msk = 0x40
	// Bit RF1FL.
	CAN_ILS_RF1FL = 0x40
	// Position of RF1LL field.
	CAN_ILS_RF1LL_Pos = 0x7
	// Bit mask of RF1LL field.
	CAN_ILS_RF1LL_Msk = 0x80
	// Bit RF1LL.
	CAN_ILS_RF1LL = 0x80
	// Position of HPML field.
	CAN_ILS_HPML_Pos = 0x8
	// Bit mask of HPML field.
	CAN_ILS_HPML_Msk = 0x100
	// Bit HPML.
	CAN_ILS_HPML = 0x100
	// Position of TCL field.
	CAN_ILS_TCL_Pos = 0x9
	// Bit mask of TCL field.
	CAN_ILS_TCL_Msk = 0x200
	// Bit TCL.
	CAN_ILS_TCL = 0x200
	// Position of TCFL field.
	CAN_ILS_TCFL_Pos = 0xa
	// Bit mask of TCFL field.
	CAN_ILS_TCFL_Msk = 0x400
	// Bit TCFL.
	CAN_ILS_TCFL = 0x400
	// Position of TFEL field.
	CAN_ILS_TFEL_Pos = 0xb
	// Bit mask of TFEL field.
	CAN_ILS_TFEL_Msk = 0x800
	// Bit TFEL.
	CAN_ILS_TFEL = 0x800
	// Position of TEFNL field.
	CAN_ILS_TEFNL_Pos = 0xc
	// Bit mask of TEFNL field.
	CAN_ILS_TEFNL_Msk = 0x1000
	// Bit TEFNL.
	CAN_ILS_TEFNL = 0x1000
	// Position of TEFWL field.
	CAN_ILS_TEFWL_Pos = 0xd
	// Bit mask of TEFWL field.
	CAN_ILS_TEFWL_Msk = 0x2000
	// Bit TEFWL.
	CAN_ILS_TEFWL = 0x2000
	// Position of TEFFL field.
	CAN_ILS_TEFFL_Pos = 0xe
	// Bit mask of TEFFL field.
	CAN_ILS_TEFFL_Msk = 0x4000
	// Bit TEFFL.
	CAN_ILS_TEFFL = 0x4000
	// Position of TEFLL field.
	CAN_ILS_TEFLL_Pos = 0xf
	// Bit mask of TEFLL field.
	CAN_ILS_TEFLL_Msk = 0x8000
	// Bit TEFLL.
	CAN_ILS_TEFLL = 0x8000
	// Position of TSWL field.
	CAN_ILS_TSWL_Pos = 0x10
	// Bit mask of TSWL field.
	CAN_ILS_TSWL_Msk = 0x10000
	// Bit TSWL.
	CAN_ILS_TSWL = 0x10000
	// Position of MRAFL field.
	CAN_ILS_MRAFL_Pos = 0x11
	// Bit mask of MRAFL field.
	CAN_ILS_MRAFL_Msk = 0x20000
	// Bit MRAFL.
	CAN_ILS_MRAFL = 0x20000
	// Position of TOOL field.
	CAN_ILS_TOOL_Pos = 0x12
	// Bit mask of TOOL field.
	CAN_ILS_TOOL_Msk = 0x40000
	// Bit TOOL.
	CAN_ILS_TOOL = 0x40000
	// Position of DRXL field.
	CAN_ILS_DRXL_Pos = 0x13
	// Bit mask of DRXL field.
	CAN_ILS_DRXL_Msk = 0x80000
	// Bit DRXL.
	CAN_ILS_DRXL = 0x80000
	// Position of BECL field.
	CAN_ILS_BECL_Pos = 0x14
	// Bit mask of BECL field.
	CAN_ILS_BECL_Msk = 0x100000
	// Bit BECL.
	CAN_ILS_BECL = 0x100000
	// Position of BEUL field.
	CAN_ILS_BEUL_Pos = 0x15
	// Bit mask of BEUL field.
	CAN_ILS_BEUL_Msk = 0x200000
	// Bit BEUL.
	CAN_ILS_BEUL = 0x200000
	// Position of ELOL field.
	CAN_ILS_ELOL_Pos = 0x16
	// Bit mask of ELOL field.
	CAN_ILS_ELOL_Msk = 0x400000
	// Bit ELOL.
	CAN_ILS_ELOL = 0x400000
	// Position of EPL field.
	CAN_ILS_EPL_Pos = 0x17
	// Bit mask of EPL field.
	CAN_ILS_EPL_Msk = 0x800000
	// Bit EPL.
	CAN_ILS_EPL = 0x800000
	// Position of EWL field.
	CAN_ILS_EWL_Pos = 0x18
	// Bit mask of EWL field.
	CAN_ILS_EWL_Msk = 0x1000000
	// Bit EWL.
	CAN_ILS_EWL = 0x1000000
	// Position of BOL field.
	CAN_ILS_BOL_Pos = 0x19
	// Bit mask of BOL field.
	CAN_ILS_BOL_Msk = 0x2000000
	// Bit BOL.
	CAN_ILS_BOL = 0x2000000
	// Position of WDIL field.
	CAN_ILS_WDIL_Pos = 0x1a
	// Bit mask of WDIL field.
	CAN_ILS_WDIL_Msk = 0x4000000
	// Bit WDIL.
	CAN_ILS_WDIL = 0x4000000
	// Position of PEAL field.
	CAN_ILS_PEAL_Pos = 0x1b
	// Bit mask of PEAL field.
	CAN_ILS_PEAL_Msk = 0x8000000
	// Bit PEAL.
	CAN_ILS_PEAL = 0x8000000
	// Position of PEDL field.
	CAN_ILS_PEDL_Pos = 0x1c
	// Bit mask of PEDL field.
	CAN_ILS_PEDL_Msk = 0x10000000
	// Bit PEDL.
	CAN_ILS_PEDL = 0x10000000
	// Position of ARAL field.
	CAN_ILS_ARAL_Pos = 0x1d
	// Bit mask of ARAL field.
	CAN_ILS_ARAL_Msk = 0x20000000
	// Bit ARAL.
	CAN_ILS_ARAL = 0x20000000

	// ILE: Interrupt Line Enable
	// Position of EINT0 field.
	CAN_ILE_EINT0_Pos = 0x0
	// Bit mask of EINT0 field.
	CAN_ILE_EINT0_Msk = 0x1
	// Bit EINT0.
	CAN_ILE_EINT0 = 0x1
	// Position of EINT1 field.
	CAN_ILE_EINT1_Pos = 0x1
	// Bit mask of EINT1 field.
	CAN_ILE_EINT1_Msk = 0x2
	// Bit EINT1.
	CAN_ILE_EINT1 = 0x2

	// GFC: Global Filter Configuration
	// Position of RRFE field.
	CAN_GFC_RRFE_Pos = 0x0
	// Bit mask of RRFE field.
	CAN_GFC_RRFE_Msk = 0x1
	// Bit RRFE.
	CAN_GFC_RRFE = 0x1
	// Position of RRFS field.
	CAN_GFC_RRFS_Pos = 0x1
	// Bit mask of RRFS field.
	CAN_GFC_RRFS_Msk = 0x2
	// Bit RRFS.
	CAN_GFC_RRFS = 0x2
	// Position of ANFE field.
	CAN_GFC_ANFE_Pos = 0x2
	// Bit mask of ANFE field.
	CAN_GFC_ANFE_Msk = 0xc
	// Accept in Rx FIFO 0
	CAN_GFC_ANFE_RXF0 = 0x0
	// Accept in Rx FIFO 1
	CAN_GFC_ANFE_RXF1 = 0x1
	// Reject
	CAN_GFC_ANFE_REJECT = 0x2
	// Position of ANFS field.
	CAN_GFC_ANFS_Pos = 0x4
	// Bit mask of ANFS field.
	CAN_GFC_ANFS_Msk = 0x30
	// Accept in Rx FIFO 0
	CAN_GFC_ANFS_RXF0 = 0x0
	// Accept in Rx FIFO 1
	CAN_GFC_ANFS_RXF1 = 0x1
	// Reject
	CAN_GFC_ANFS_REJECT = 0x2

	// SIDFC: Standard ID Filter Configuration
	// Position of FLSSA field.
	CAN_SIDFC_FLSSA_Pos = 0x0
	// Bit mask of FLSSA field.
	CAN_SIDFC_FLSSA_Msk = 0xffff
	// Position of LSS field.
	CAN_SIDFC_LSS_Pos = 0x10
	// Bit mask of LSS field.
	CAN_SIDFC_LSS_Msk = 0xff0000

	// XIDFC: Extended ID Filter Configuration
	// Position of FLESA field.
	CAN_XIDFC_FLESA_Pos = 0x0
	// Bit mask of FLESA field.
	CAN_XIDFC_FLESA_Msk = 0xffff
	// Position of LSE field.
	CAN_XIDFC_LSE_Pos = 0x10
	// Bit mask of LSE field.
	CAN_XIDFC_LSE_Msk = 0x7f0000

	// XIDAM: Extended ID AND Mask
	// Position of EIDM field.
	CAN_XIDAM_EIDM_Pos = 0x0
	// Bit mask of EIDM field.
	CAN_XIDAM_EIDM_Msk = 0x1fffffff

	// HPMS: High Priority Message Status
	// Position of BIDX field.
	CAN_HPMS_BIDX_Pos = 0x0
	// Bit mask of BIDX field.
	CAN_HPMS_BIDX_Msk = 0x3f
	// Position of MSI field.
	CAN_HPMS_MSI_Pos = 0x6
	// Bit mask of MSI field.
	CAN_HPMS_MSI_Msk = 0xc0
	// No FIFO selected
	CAN_HPMS_MSI_NONE = 0x0
	// FIFO message lost
	CAN_HPMS_MSI_LOST = 0x1
	// Message stored in FIFO 0
	CAN_HPMS_MSI_FIFO0 = 0x2
	// Message stored in FIFO 1
	CAN_HPMS_MSI_FIFO1 = 0x3
	// Position of FIDX field.
	CAN_HPMS_FIDX_Pos = 0x8
	// Bit mask of FIDX field.
	CAN_HPMS_FIDX_Msk = 0x7f00
	// Position of FLST field.
	CAN_HPMS_FLST_Pos = 0xf
	// Bit mask of FLST field.
	CAN_HPMS_FLST_Msk = 0x8000
	// Bit FLST.
	CAN_HPMS_FLST = 0x8000

	// NDAT1: New Data 1
	// Position of ND0 field.
	CAN_NDAT1_ND0_Pos = 0x0
	// Bit mask of ND0 field.
	CAN_NDAT1_ND0_Msk = 0x1
	// Bit ND0.
	CAN_NDAT1_ND0 = 0x1
	// Position of ND1 field.
	CAN_NDAT1_ND1_Pos = 0x1
	// Bit mask of ND1 field.
	CAN_NDAT1_ND1_Msk = 0x2
	// Bit ND1.
	CAN_NDAT1_ND1 = 0x2
	// Position of ND2 field.
	CAN_NDAT1_ND2_Pos = 0x2
	// Bit mask of ND2 field.
	CAN_NDAT1_ND2_Msk = 0x4
	// Bit ND2.
	CAN_NDAT1_ND2 = 0x4
	// Position of ND3 field.
	CAN_NDAT1_ND3_Pos = 0x3
	// Bit mask of ND3 field.
	CAN_NDAT1_ND3_Msk = 0x8
	// Bit ND3.
	CAN_NDAT1_ND3 = 0x8
	// Position of ND4 field.
	CAN_NDAT1_ND4_Pos = 0x4
	// Bit mask of ND4 field.
	CAN_NDAT1_ND4_Msk = 0x10
	// Bit ND4.
	CAN_NDAT1_ND4 = 0x10
	// Position of ND5 field.
	CAN_NDAT1_ND5_Pos = 0x5
	// Bit mask of ND5 field.
	CAN_NDAT1_ND5_Msk = 0x20
	// Bit ND5.
	CAN_NDAT1_ND5 = 0x20
	// Position of ND6 field.
	CAN_NDAT1_ND6_Pos = 0x6
	// Bit mask of ND6 field.
	CAN_NDAT1_ND6_Msk = 0x40
	// Bit ND6.
	CAN_NDAT1_ND6 = 0x40
	// Position of ND7 field.
	CAN_NDAT1_ND7_Pos = 0x7
	// Bit mask of ND7 field.
	CAN_NDAT1_ND7_Msk = 0x80
	// Bit ND7.
	CAN_NDAT1_ND7 = 0x80
	// Position of ND8 field.
	CAN_NDAT1_ND8_Pos = 0x8
	// Bit mask of ND8 field.
	CAN_NDAT1_ND8_Msk = 0x100
	// Bit ND8.
	CAN_NDAT1_ND8 = 0x100
	// Position of ND9 field.
	CAN_NDAT1_ND9_Pos = 0x9
	// Bit mask of ND9 field.
	CAN_NDAT1_ND9_Msk = 0x200
	// Bit ND9.
	CAN_NDAT1_ND9 = 0x200
	// Position of ND10 field.
	CAN_NDAT1_ND10_Pos = 0xa
	// Bit mask of ND10 field.
	CAN_NDAT1_ND10_Msk = 0x400
	// Bit ND10.
	CAN_NDAT1_ND10 = 0x400
	// Position of ND11 field.
	CAN_NDAT1_ND11_Pos = 0xb
	// Bit mask of ND11 field.
	CAN_NDAT1_ND11_Msk = 0x800
	// Bit ND11.
	CAN_NDAT1_ND11 = 0x800
	// Position of ND12 field.
	CAN_NDAT1_ND12_Pos = 0xc
	// Bit mask of ND12 field.
	CAN_NDAT1_ND12_Msk = 0x1000
	// Bit ND12.
	CAN_NDAT1_ND12 = 0x1000
	// Position of ND13 field.
	CAN_NDAT1_ND13_Pos = 0xd
	// Bit mask of ND13 field.
	CAN_NDAT1_ND13_Msk = 0x2000
	// Bit ND13.
	CAN_NDAT1_ND13 = 0x2000
	// Position of ND14 field.
	CAN_NDAT1_ND14_Pos = 0xe
	// Bit mask of ND14 field.
	CAN_NDAT1_ND14_Msk = 0x4000
	// Bit ND14.
	CAN_NDAT1_ND14 = 0x4000
	// Position of ND15 field.
	CAN_NDAT1_ND15_Pos = 0xf
	// Bit mask of ND15 field.
	CAN_NDAT1_ND15_Msk = 0x8000
	// Bit ND15.
	CAN_NDAT1_ND15 = 0x8000
	// Position of ND16 field.
	CAN_NDAT1_ND16_Pos = 0x10
	// Bit mask of ND16 field.
	CAN_NDAT1_ND16_Msk = 0x10000
	// Bit ND16.
	CAN_NDAT1_ND16 = 0x10000
	// Position of ND17 field.
	CAN_NDAT1_ND17_Pos = 0x11
	// Bit mask of ND17 field.
	CAN_NDAT1_ND17_Msk = 0x20000
	// Bit ND17.
	CAN_NDAT1_ND17 = 0x20000
	// Position of ND18 field.
	CAN_NDAT1_ND18_Pos = 0x12
	// Bit mask of ND18 field.
	CAN_NDAT1_ND18_Msk = 0x40000
	// Bit ND18.
	CAN_NDAT1_ND18 = 0x40000
	// Position of ND19 field.
	CAN_NDAT1_ND19_Pos = 0x13
	// Bit mask of ND19 field.
	CAN_NDAT1_ND19_Msk = 0x80000
	// Bit ND19.
	CAN_NDAT1_ND19 = 0x80000
	// Position of ND20 field.
	CAN_NDAT1_ND20_Pos = 0x14
	// Bit mask of ND20 field.
	CAN_NDAT1_ND20_Msk = 0x100000
	// Bit ND20.
	CAN_NDAT1_ND20 = 0x100000
	// Position of ND21 field.
	CAN_NDAT1_ND21_Pos = 0x15
	// Bit mask of ND21 field.
	CAN_NDAT1_ND21_Msk = 0x200000
	// Bit ND21.
	CAN_NDAT1_ND21 = 0x200000
	// Position of ND22 field.
	CAN_NDAT1_ND22_Pos = 0x16
	// Bit mask of ND22 field.
	CAN_NDAT1_ND22_Msk = 0x400000
	// Bit ND22.
	CAN_NDAT1_ND22 = 0x400000
	// Position of ND23 field.
	CAN_NDAT1_ND23_Pos = 0x17
	// Bit mask of ND23 field.
	CAN_NDAT1_ND23_Msk = 0x800000
	// Bit ND23.
	CAN_NDAT1_ND23 = 0x800000
	// Position of ND24 field.
	CAN_NDAT1_ND24_Pos = 0x18
	// Bit mask of ND24 field.
	CAN_NDAT1_ND24_Msk = 0x1000000
	// Bit ND24.
	CAN_NDAT1_ND24 = 0x1000000
	// Position of ND25 field.
	CAN_NDAT1_ND25_Pos = 0x19
	// Bit mask of ND25 field.
	CAN_NDAT1_ND25_Msk = 0x2000000
	// Bit ND25.
	CAN_NDAT1_ND25 = 0x2000000
	// Position of ND26 field.
	CAN_NDAT1_ND26_Pos = 0x1a
	// Bit mask of ND26 field.
	CAN_NDAT1_ND26_Msk = 0x4000000
	// Bit ND26.
	CAN_NDAT1_ND26 = 0x4000000
	// Position of ND27 field.
	CAN_NDAT1_ND27_Pos = 0x1b
	// Bit mask of ND27 field.
	CAN_NDAT1_ND27_Msk = 0x8000000
	// Bit ND27.
	CAN_NDAT1_ND27 = 0x8000000
	// Position of ND28 field.
	CAN_NDAT1_ND28_Pos = 0x1c
	// Bit mask of ND28 field.
	CAN_NDAT1_ND28_Msk = 0x10000000
	// Bit ND28.
	CAN_NDAT1_ND28 = 0x10000000
	// Position of ND29 field.
	CAN_NDAT1_ND29_Pos = 0x1d
	// Bit mask of ND29 field.
	CAN_NDAT1_ND29_Msk = 0x20000000
	// Bit ND29.
	CAN_NDAT1_ND29 = 0x20000000
	// Position of ND30 field.
	CAN_NDAT1_ND30_Pos = 0x1e
	// Bit mask of ND30 field.
	CAN_NDAT1_ND30_Msk = 0x40000000
	// Bit ND30.
	CAN_NDAT1_ND30 = 0x40000000
	// Position of ND31 field.
	CAN_NDAT1_ND31_Pos = 0x1f
	// Bit mask of ND31 field.
	CAN_NDAT1_ND31_Msk = 0x80000000
	// Bit ND31.
	CAN_NDAT1_ND31 = 0x80000000

	// NDAT2: New Data 2
	// Position of ND32 field.
	CAN_NDAT2_ND32_Pos = 0x0
	// Bit mask of ND32 field.
	CAN_NDAT2_ND32_Msk = 0x1
	// Bit ND32.
	CAN_NDAT2_ND32 = 0x1
	// Position of ND33 field.
	CAN_NDAT2_ND33_Pos = 0x1
	// Bit mask of ND33 field.
	CAN_NDAT2_ND33_Msk = 0x2
	// Bit ND33.
	CAN_NDAT2_ND33 = 0x2
	// Position of ND34 field.
	CAN_NDAT2_ND34_Pos = 0x2
	// Bit mask of ND34 field.
	CAN_NDAT2_ND34_Msk = 0x4
	// Bit ND34.
	CAN_NDAT2_ND34 = 0x4
	// Position of ND35 field.
	CAN_NDAT2_ND35_Pos = 0x3
	// Bit mask of ND35 field.
	CAN_NDAT2_ND35_Msk = 0x8
	// Bit ND35.
	CAN_NDAT2_ND35 = 0x8
	// Position of ND36 field.
	CAN_NDAT2_ND36_Pos = 0x4
	// Bit mask of ND36 field.
	CAN_NDAT2_ND36_Msk = 0x10
	// Bit ND36.
	CAN_NDAT2_ND36 = 0x10
	// Position of ND37 field.
	CAN_NDAT2_ND37_Pos = 0x5
	// Bit mask of ND37 field.
	CAN_NDAT2_ND37_Msk = 0x20
	// Bit ND37.
	CAN_NDAT2_ND37 = 0x20
	// Position of ND38 field.
	CAN_NDAT2_ND38_Pos = 0x6
	// Bit mask of ND38 field.
	CAN_NDAT2_ND38_Msk = 0x40
	// Bit ND38.
	CAN_NDAT2_ND38 = 0x40
	// Position of ND39 field.
	CAN_NDAT2_ND39_Pos = 0x7
	// Bit mask of ND39 field.
	CAN_NDAT2_ND39_Msk = 0x80
	// Bit ND39.
	CAN_NDAT2_ND39 = 0x80
	// Position of ND40 field.
	CAN_NDAT2_ND40_Pos = 0x8
	// Bit mask of ND40 field.
	CAN_NDAT2_ND40_Msk = 0x100
	// Bit ND40.
	CAN_NDAT2_ND40 = 0x100
	// Position of ND41 field.
	CAN_NDAT2_ND41_Pos = 0x9
	// Bit mask of ND41 field.
	CAN_NDAT2_ND41_Msk = 0x200
	// Bit ND41.
	CAN_NDAT2_ND41 = 0x200
	// Position of ND42 field.
	CAN_NDAT2_ND42_Pos = 0xa
	// Bit mask of ND42 field.
	CAN_NDAT2_ND42_Msk = 0x400
	// Bit ND42.
	CAN_NDAT2_ND42 = 0x400
	// Position of ND43 field.
	CAN_NDAT2_ND43_Pos = 0xb
	// Bit mask of ND43 field.
	CAN_NDAT2_ND43_Msk = 0x800
	// Bit ND43.
	CAN_NDAT2_ND43 = 0x800
	// Position of ND44 field.
	CAN_NDAT2_ND44_Pos = 0xc
	// Bit mask of ND44 field.
	CAN_NDAT2_ND44_Msk = 0x1000
	// Bit ND44.
	CAN_NDAT2_ND44 = 0x1000
	// Position of ND45 field.
	CAN_NDAT2_ND45_Pos = 0xd
	// Bit mask of ND45 field.
	CAN_NDAT2_ND45_Msk = 0x2000
	// Bit ND45.
	CAN_NDAT2_ND45 = 0x2000
	// Position of ND46 field.
	CAN_NDAT2_ND46_Pos = 0xe
	// Bit mask of ND46 field.
	CAN_NDAT2_ND46_Msk = 0x4000
	// Bit ND46.
	CAN_NDAT2_ND46 = 0x4000
	// Position of ND47 field.
	CAN_NDAT2_ND47_Pos = 0xf
	// Bit mask of ND47 field.
	CAN_NDAT2_ND47_Msk = 0x8000
	// Bit ND47.
	CAN_NDAT2_ND47 = 0x8000
	// Position of ND48 field.
	CAN_NDAT2_ND48_Pos = 0x10
	// Bit mask of ND48 field.
	CAN_NDAT2_ND48_Msk = 0x10000
	// Bit ND48.
	CAN_NDAT2_ND48 = 0x10000
	// Position of ND49 field.
	CAN_NDAT2_ND49_Pos = 0x11
	// Bit mask of ND49 field.
	CAN_NDAT2_ND49_Msk = 0x20000
	// Bit ND49.
	CAN_NDAT2_ND49 = 0x20000
	// Position of ND50 field.
	CAN_NDAT2_ND50_Pos = 0x12
	// Bit mask of ND50 field.
	CAN_NDAT2_ND50_Msk = 0x40000
	// Bit ND50.
	CAN_NDAT2_ND50 = 0x40000
	// Position of ND51 field.
	CAN_NDAT2_ND51_Pos = 0x13
	// Bit mask of ND51 field.
	CAN_NDAT2_ND51_Msk = 0x80000
	// Bit ND51.
	CAN_NDAT2_ND51 = 0x80000
	// Position of ND52 field.
	CAN_NDAT2_ND52_Pos = 0x14
	// Bit mask of ND52 field.
	CAN_NDAT2_ND52_Msk = 0x100000
	// Bit ND52.
	CAN_NDAT2_ND52 = 0x100000
	// Position of ND53 field.
	CAN_NDAT2_ND53_Pos = 0x15
	// Bit mask of ND53 field.
	CAN_NDAT2_ND53_Msk = 0x200000
	// Bit ND53.
	CAN_NDAT2_ND53 = 0x200000
	// Position of ND54 field.
	CAN_NDAT2_ND54_Pos = 0x16
	// Bit mask of ND54 field.
	CAN_NDAT2_ND54_Msk = 0x400000
	// Bit ND54.
	CAN_NDAT2_ND54 = 0x400000
	// Position of ND55 field.
	CAN_NDAT2_ND55_Pos = 0x17
	// Bit mask of ND55 field.
	CAN_NDAT2_ND55_Msk = 0x800000
	// Bit ND55.
	CAN_NDAT2_ND55 = 0x800000
	// Position of ND56 field.
	CAN_NDAT2_ND56_Pos = 0x18
	// Bit mask of ND56 field.
	CAN_NDAT2_ND56_Msk = 0x1000000
	// Bit ND56.
	CAN_NDAT2_ND56 = 0x1000000
	// Position of ND57 field.
	CAN_NDAT2_ND57_Pos = 0x19
	// Bit mask of ND57 field.
	CAN_NDAT2_ND57_Msk = 0x2000000
	// Bit ND57.
	CAN_NDAT2_ND57 = 0x2000000
	// Position of ND58 field.
	CAN_NDAT2_ND58_Pos = 0x1a
	// Bit mask of ND58 field.
	CAN_NDAT2_ND58_Msk = 0x4000000
	// Bit ND58.
	CAN_NDAT2_ND58 = 0x4000000
	// Position of ND59 field.
	CAN_NDAT2_ND59_Pos = 0x1b
	// Bit mask of ND59 field.
	CAN_NDAT2_ND59_Msk = 0x8000000
	// Bit ND59.
	CAN_NDAT2_ND59 = 0x8000000
	// Position of ND60 field.
	CAN_NDAT2_ND60_Pos = 0x1c
	// Bit mask of ND60 field.
	CAN_NDAT2_ND60_Msk = 0x10000000
	// Bit ND60.
	CAN_NDAT2_ND60 = 0x10000000
	// Position of ND61 field.
	CAN_NDAT2_ND61_Pos = 0x1d
	// Bit mask of ND61 field.
	CAN_NDAT2_ND61_Msk = 0x20000000
	// Bit ND61.
	CAN_NDAT2_ND61 = 0x20000000
	// Position of ND62 field.
	CAN_NDAT2_ND62_Pos = 0x1e
	// Bit mask of ND62 field.
	CAN_NDAT2_ND62_Msk = 0x40000000
	// Bit ND62.
	CAN_NDAT2_ND62 = 0x40000000
	// Position of ND63 field.
	CAN_NDAT2_ND63_Pos = 0x1f
	// Bit mask of ND63 field.
	CAN_NDAT2_ND63_Msk = 0x80000000
	// Bit ND63.
	CAN_NDAT2_ND63 = 0x80000000

	// RXF0C: Rx FIFO 0 Configuration
	// Position of F0SA field.
	CAN_RXF0C_F0SA_Pos = 0x0
	// Bit mask of F0SA field.
	CAN_RXF0C_F0SA_Msk = 0xffff
	// Position of F0S field.
	CAN_RXF0C_F0S_Pos = 0x10
	// Bit mask of F0S field.
	CAN_RXF0C_F0S_Msk = 0x7f0000
	// Position of F0WM field.
	CAN_RXF0C_F0WM_Pos = 0x18
	// Bit mask of F0WM field.
	CAN_RXF0C_F0WM_Msk = 0x7f000000
	// Position of F0OM field.
	CAN_RXF0C_F0OM_Pos = 0x1f
	// Bit mask of F0OM field.
	CAN_RXF0C_F0OM_Msk = 0x80000000
	// Bit F0OM.
	CAN_RXF0C_F0OM = 0x80000000

	// RXF0S: Rx FIFO 0 Status
	// Position of F0FL field.
	CAN_RXF0S_F0FL_Pos = 0x0
	// Bit mask of F0FL field.
	CAN_RXF0S_F0FL_Msk = 0x7f
	// Position of F0GI field.
	CAN_RXF0S_F0GI_Pos = 0x8
	// Bit mask of F0GI field.
	CAN_RXF0S_F0GI_Msk = 0x3f00
	// Position of F0PI field.
	CAN_RXF0S_F0PI_Pos = 0x10
	// Bit mask of F0PI field.
	CAN_RXF0S_F0PI_Msk = 0x3f0000
	// Position of F0F field.
	CAN_RXF0S_F0F_Pos = 0x18
	// Bit mask of F0F field.
	CAN_RXF0S_F0F_Msk = 0x1000000
	// Bit F0F.
	CAN_RXF0S_F0F = 0x1000000
	// Position of RF0L field.
	CAN_RXF0S_RF0L_Pos = 0x19
	// Bit mask of RF0L field.
	CAN_RXF0S_RF0L_Msk = 0x2000000
	// Bit RF0L.
	CAN_RXF0S_RF0L = 0x2000000

	// RXF0A: Rx FIFO 0 Acknowledge
	// Position of F0AI field.
	CAN_RXF0A_F0AI_Pos = 0x0
	// Bit mask of F0AI field.
	CAN_RXF0A_F0AI_Msk = 0x3f

	// RXBC: Rx Buffer Configuration
	// Position of RBSA field.
	CAN_RXBC_RBSA_Pos = 0x0
	// Bit mask of RBSA field.
	CAN_RXBC_RBSA_Msk = 0xffff

	// RXF1C: Rx FIFO 1 Configuration
	// Position of F1SA field.
	CAN_RXF1C_F1SA_Pos = 0x0
	// Bit mask of F1SA field.
	CAN_RXF1C_F1SA_Msk = 0xffff
	// Position of F1S field.
	CAN_RXF1C_F1S_Pos = 0x10
	// Bit mask of F1S field.
	CAN_RXF1C_F1S_Msk = 0x7f0000
	// Position of F1WM field.
	CAN_RXF1C_F1WM_Pos = 0x18
	// Bit mask of F1WM field.
	CAN_RXF1C_F1WM_Msk = 0x7f000000
	// Position of F1OM field.
	CAN_RXF1C_F1OM_Pos = 0x1f
	// Bit mask of F1OM field.
	CAN_RXF1C_F1OM_Msk = 0x80000000
	// Bit F1OM.
	CAN_RXF1C_F1OM = 0x80000000

	// RXF1S: Rx FIFO 1 Status
	// Position of F1FL field.
	CAN_RXF1S_F1FL_Pos = 0x0
	// Bit mask of F1FL field.
	CAN_RXF1S_F1FL_Msk = 0x7f
	// Position of F1GI field.
	CAN_RXF1S_F1GI_Pos = 0x8
	// Bit mask of F1GI field.
	CAN_RXF1S_F1GI_Msk = 0x3f00
	// Position of F1PI field.
	CAN_RXF1S_F1PI_Pos = 0x10
	// Bit mask of F1PI field.
	CAN_RXF1S_F1PI_Msk = 0x3f0000
	// Position of F1F field.
	CAN_RXF1S_F1F_Pos = 0x18
	// Bit mask of F1F field.
	CAN_RXF1S_F1F_Msk = 0x1000000
	// Bit F1F.
	CAN_RXF1S_F1F = 0x1000000
	// Position of RF1L field.
	CAN_RXF1S_RF1L_Pos = 0x19
	// Bit mask of RF1L field.
	CAN_RXF1S_RF1L_Msk = 0x2000000
	// Bit RF1L.
	CAN_RXF1S_RF1L = 0x2000000
	// Position of DMS field.
	CAN_RXF1S_DMS_Pos = 0x1e
	// Bit mask of DMS field.
	CAN_RXF1S_DMS_Msk = 0xc0000000
	// Idle state
	CAN_RXF1S_DMS_IDLE = 0x0
	// Debug message A received
	CAN_RXF1S_DMS_DBGA = 0x1
	// Debug message A/B received
	CAN_RXF1S_DMS_DBGB = 0x2
	// Debug message A/B/C received, DMA request set
	CAN_RXF1S_DMS_DBGC = 0x3

	// RXF1A: Rx FIFO 1 Acknowledge
	// Position of F1AI field.
	CAN_RXF1A_F1AI_Pos = 0x0
	// Bit mask of F1AI field.
	CAN_RXF1A_F1AI_Msk = 0x3f

	// RXESC: Rx Buffer / FIFO Element Size Configuration
	// Position of F0DS field.
	CAN_RXESC_F0DS_Pos = 0x0
	// Bit mask of F0DS field.
	CAN_RXESC_F0DS_Msk = 0x7
	// 8 byte data field
	CAN_RXESC_F0DS_DATA8 = 0x0
	// 12 byte data field
	CAN_RXESC_F0DS_DATA12 = 0x1
	// 16 byte data field
	CAN_RXESC_F0DS_DATA16 = 0x2
	// 20 byte data field
	CAN_RXESC_F0DS_DATA20 = 0x3
	// 24 byte data field
	CAN_RXESC_F0DS_DATA24 = 0x4
	// 32 byte data field
	CAN_RXESC_F0DS_DATA32 = 0x5
	// 48 byte data field
	CAN_RXESC_F0DS_DATA48 = 0x6
	// 64 byte data field
	CAN_RXESC_F0DS_DATA64 = 0x7
	// Position of F1DS field.
	CAN_RXESC_F1DS_Pos = 0x4
	// Bit mask of F1DS field.
	CAN_RXESC_F1DS_Msk = 0x70
	// 8 byte data field
	CAN_RXESC_F1DS_DATA8 = 0x0
	// 12 byte data field
	CAN_RXESC_F1DS_DATA12 = 0x1
	// 16 byte data field
	CAN_RXESC_F1DS_DATA16 = 0x2
	// 20 byte data field
	CAN_RXESC_F1DS_DATA20 = 0x3
	// 24 byte data field
	CAN_RXESC_F1DS_DATA24 = 0x4
	// 32 byte data field
	CAN_RXESC_F1DS_DATA32 = 0x5
	// 48 byte data field
	CAN_RXESC_F1DS_DATA48 = 0x6
	// 64 byte data field
	CAN_RXESC_F1DS_DATA64 = 0x7
	// Position of RBDS field.
	CAN_RXESC_RBDS_Pos = 0x8
	// Bit mask of RBDS field.
	CAN_RXESC_RBDS_Msk = 0x700
	// 8 byte data field
	CAN_RXESC_RBDS_DATA8 = 0x0
	// 12 byte data field
	CAN_RXESC_RBDS_DATA12 = 0x1
	// 16 byte data field
	CAN_RXESC_RBDS_DATA16 = 0x2
	// 20 byte data field
	CAN_RXESC_RBDS_DATA20 = 0x3
	// 24 byte data field
	CAN_RXESC_RBDS_DATA24 = 0x4
	// 32 byte data field
	CAN_RXESC_RBDS_DATA32 = 0x5
	// 48 byte data field
	CAN_RXESC_RBDS_DATA48 = 0x6
	// 64 byte data field
	CAN_RXESC_RBDS_DATA64 = 0x7

	// TXBC: Tx Buffer Configuration
	// Position of TBSA field.
	CAN_TXBC_TBSA_Pos = 0x0
	// Bit mask of TBSA field.
	CAN_TXBC_TBSA_Msk = 0xffff
	// Position of NDTB field.
	CAN_TXBC_NDTB_Pos = 0x10
	// Bit mask of NDTB field.
	CAN_TXBC_NDTB_Msk = 0x3f0000
	// Position of TFQS field.
	CAN_TXBC_TFQS_Pos = 0x18
	// Bit mask of TFQS field.
	CAN_TXBC_TFQS_Msk = 0x3f000000
	// Position of TFQM field.
	CAN_TXBC_TFQM_Pos = 0x1e
	// Bit mask of TFQM field.
	CAN_TXBC_TFQM_Msk = 0x40000000
	// Bit TFQM.
	CAN_TXBC_TFQM = 0x40000000

	// TXFQS: Tx FIFO / Queue Status
	// Position of TFFL field.
	CAN_TXFQS_TFFL_Pos = 0x0
	// Bit mask of TFFL field.
	CAN_TXFQS_TFFL_Msk = 0x3f
	// Position of TFGI field.
	CAN_TXFQS_TFGI_Pos = 0x8
	// Bit mask of TFGI field.
	CAN_TXFQS_TFGI_Msk = 0x1f00
	// Position of TFQPI field.
	CAN_TXFQS_TFQPI_Pos = 0x10
	// Bit mask of TFQPI field.
	CAN_TXFQS_TFQPI_Msk = 0x1f0000
	// Position of TFQF field.
	CAN_TXFQS_TFQF_Pos = 0x15
	// Bit mask of TFQF field.
	CAN_TXFQS_TFQF_Msk = 0x200000
	// Bit TFQF.
	CAN_TXFQS_TFQF = 0x200000

	// TXESC: Tx Buffer Element Size Configuration
	// Position of TBDS field.
	CAN_TXESC_TBDS_Pos = 0x0
	// Bit mask of TBDS field.
	CAN_TXESC_TBDS_Msk = 0x7
	// 8 byte data field
	CAN_TXESC_TBDS_DATA8 = 0x0
	// 12 byte data field
	CAN_TXESC_TBDS_DATA12 = 0x1
	// 16 byte data field
	CAN_TXESC_TBDS_DATA16 = 0x2
	// 20 byte data field
	CAN_TXESC_TBDS_DATA20 = 0x3
	// 24 byte data field
	CAN_TXESC_TBDS_DATA24 = 0x4
	// 32 byte data field
	CAN_TXESC_TBDS_DATA32 = 0x5
	// 48 byte data field
	CAN_TXESC_TBDS_DATA48 = 0x6
	// 64 byte data field
	CAN_TXESC_TBDS_DATA64 = 0x7

	// TXBRP: Tx Buffer Request Pending
	// Position of TRP0 field.
	CAN_TXBRP_TRP0_Pos = 0x0
	// Bit mask of TRP0 field.
	CAN_TXBRP_TRP0_Msk = 0x1
	// Bit TRP0.
	CAN_TXBRP_TRP0 = 0x1
	// Position of TRP1 field.
	CAN_TXBRP_TRP1_Pos = 0x1
	// Bit mask of TRP1 field.
	CAN_TXBRP_TRP1_Msk = 0x2
	// Bit TRP1.
	CAN_TXBRP_TRP1 = 0x2
	// Position of TRP2 field.
	CAN_TXBRP_TRP2_Pos = 0x2
	// Bit mask of TRP2 field.
	CAN_TXBRP_TRP2_Msk = 0x4
	// Bit TRP2.
	CAN_TXBRP_TRP2 = 0x4
	// Position of TRP3 field.
	CAN_TXBRP_TRP3_Pos = 0x3
	// Bit mask of TRP3 field.
	CAN_TXBRP_TRP3_Msk = 0x8
	// Bit TRP3.
	CAN_TXBRP_TRP3 = 0x8
	// Position of TRP4 field.
	CAN_TXBRP_TRP4_Pos = 0x4
	// Bit mask of TRP4 field.
	CAN_TXBRP_TRP4_Msk = 0x10
	// Bit TRP4.
	CAN_TXBRP_TRP4 = 0x10
	// Position of TRP5 field.
	CAN_TXBRP_TRP5_Pos = 0x5
	// Bit mask of TRP5 field.
	CAN_TXBRP_TRP5_Msk = 0x20
	// Bit TRP5.
	CAN_TXBRP_TRP5 = 0x20
	// Position of TRP6 field.
	CAN_TXBRP_TRP6_Pos = 0x6
	// Bit mask of TRP6 field.
	CAN_TXBRP_TRP6_Msk = 0x40
	// Bit TRP6.
	CAN_TXBRP_TRP6 = 0x40
	// Position of TRP7 field.
	CAN_TXBRP_TRP7_Pos = 0x7
	// Bit mask of TRP7 field.
	CAN_TXBRP_TRP7_Msk = 0x80
	// Bit TRP7.
	CAN_TXBRP_TRP7 = 0x80
	// Position of TRP8 field.
	CAN_TXBRP_TRP8_Pos = 0x8
	// Bit mask of TRP8 field.
	CAN_TXBRP_TRP8_Msk = 0x100
	// Bit TRP8.
	CAN_TXBRP_TRP8 = 0x100
	// Position of TRP9 field.
	CAN_TXBRP_TRP9_Pos = 0x9
	// Bit mask of TRP9 field.
	CAN_TXBRP_TRP9_Msk = 0x200
	// Bit TRP9.
	CAN_TXBRP_TRP9 = 0x200
	// Position of TRP10 field.
	CAN_TXBRP_TRP10_Pos = 0xa
	// Bit mask of TRP10 field.
	CAN_TXBRP_TRP10_Msk = 0x400
	// Bit TRP10.
	CAN_TXBRP_TRP10 = 0x400
	// Position of TRP11 field.
	CAN_TXBRP_TRP11_Pos = 0xb
	// Bit mask of TRP11 field.
	CAN_TXBRP_TRP11_Msk = 0x800
	// Bit TRP11.
	CAN_TXBRP_TRP11 = 0x800
	// Position of TRP12 field.
	CAN_TXBRP_TRP12_Pos = 0xc
	// Bit mask of TRP12 field.
	CAN_TXBRP_TRP12_Msk = 0x1000
	// Bit TRP12.
	CAN_TXBRP_TRP12 = 0x1000
	// Position of TRP13 field.
	CAN_TXBRP_TRP13_Pos = 0xd
	// Bit mask of TRP13 field.
	CAN_TXBRP_TRP13_Msk = 0x2000
	// Bit TRP13.
	CAN_TXBRP_TRP13 = 0x2000
	// Position of TRP14 field.
	CAN_TXBRP_TRP14_Pos = 0xe
	// Bit mask of TRP14 field.
	CAN_TXBRP_TRP14_Msk = 0x4000
	// Bit TRP14.
	CAN_TXBRP_TRP14 = 0x4000
	// Position of TRP15 field.
	CAN_TXBRP_TRP15_Pos = 0xf
	// Bit mask of TRP15 field.
	CAN_TXBRP_TRP15_Msk = 0x8000
	// Bit TRP15.
	CAN_TXBRP_TRP15 = 0x8000
	// Position of TRP16 field.
	CAN_TXBRP_TRP16_Pos = 0x10
	// Bit mask of TRP16 field.
	CAN_TXBRP_TRP16_Msk = 0x10000
	// Bit TRP16.
	CAN_TXBRP_TRP16 = 0x10000
	// Position of TRP17 field.
	CAN_TXBRP_TRP17_Pos = 0x11
	// Bit mask of TRP17 field.
	CAN_TXBRP_TRP17_Msk = 0x20000
	// Bit TRP17.
	CAN_TXBRP_TRP17 = 0x20000
	// Position of TRP18 field.
	CAN_TXBRP_TRP18_Pos = 0x12
	// Bit mask of TRP18 field.
	CAN_TXBRP_TRP18_Msk = 0x40000
	// Bit TRP18.
	CAN_TXBRP_TRP18 = 0x40000
	// Position of TRP19 field.
	CAN_TXBRP_TRP19_Pos = 0x13
	// Bit mask of TRP19 field.
	CAN_TXBRP_TRP19_Msk = 0x80000
	// Bit TRP19.
	CAN_TXBRP_TRP19 = 0x80000
	// Position of TRP20 field.
	CAN_TXBRP_TRP20_Pos = 0x14
	// Bit mask of TRP20 field.
	CAN_TXBRP_TRP20_Msk = 0x100000
	// Bit TRP20.
	CAN_TXBRP_TRP20 = 0x100000
	// Position of TRP21 field.
	CAN_TXBRP_TRP21_Pos = 0x15
	// Bit mask of TRP21 field.
	CAN_TXBRP_TRP21_Msk = 0x200000
	// Bit TRP21.
	CAN_TXBRP_TRP21 = 0x200000
	// Position of TRP22 field.
	CAN_TXBRP_TRP22_Pos = 0x16
	// Bit mask of TRP22 field.
	CAN_TXBRP_TRP22_Msk = 0x400000
	// Bit TRP22.
	CAN_TXBRP_TRP22 = 0x400000
	// Position of TRP23 field.
	CAN_TXBRP_TRP23_Pos = 0x17
	// Bit mask of TRP23 field.
	CAN_TXBRP_TRP23_Msk = 0x800000
	// Bit TRP23.
	CAN_TXBRP_TRP23 = 0x800000
	// Position of TRP24 field.
	CAN_TXBRP_TRP24_Pos = 0x18
	// Bit mask of TRP24 field.
	CAN_TXBRP_TRP24_Msk = 0x1000000
	// Bit TRP24.
	CAN_TXBRP_TRP24 = 0x1000000
	// Position of TRP25 field.
	CAN_TXBRP_TRP25_Pos = 0x19
	// Bit mask of TRP25 field.
	CAN_TXBRP_TRP25_Msk = 0x2000000
	// Bit TRP25.
	CAN_TXBRP_TRP25 = 0x2000000
	// Position of TRP26 field.
	CAN_TXBRP_TRP26_Pos = 0x1a
	// Bit mask of TRP26 field.
	CAN_TXBRP_TRP26_Msk = 0x4000000
	// Bit TRP26.
	CAN_TXBRP_TRP26 = 0x4000000
	// Position of TRP27 field.
	CAN_TXBRP_TRP27_Pos = 0x1b
	// Bit mask of TRP27 field.
	CAN_TXBRP_TRP27_Msk = 0x8000000
	// Bit TRP27.
	CAN_TXBRP_TRP27 = 0x8000000
	// Position of TRP28 field.
	CAN_TXBRP_TRP28_Pos = 0x1c
	// Bit mask of TRP28 field.
	CAN_TXBRP_TRP28_Msk = 0x10000000
	// Bit TRP28.
	CAN_TXBRP_TRP28 = 0x10000000
	// Position of TRP29 field.
	CAN_TXBRP_TRP29_Pos = 0x1d
	// Bit mask of TRP29 field.
	CAN_TXBRP_TRP29_Msk = 0x20000000
	// Bit TRP29.
	CAN_TXBRP_TRP29 = 0x20000000
	// Position of TRP30 field.
	CAN_TXBRP_TRP30_Pos = 0x1e
	// Bit mask of TRP30 field.
	CAN_TXBRP_TRP30_Msk = 0x40000000
	// Bit TRP30.
	CAN_TXBRP_TRP30 = 0x40000000
	// Position of TRP31 field.
	CAN_TXBRP_TRP31_Pos = 0x1f
	// Bit mask of TRP31 field.
	CAN_TXBRP_TRP31_Msk = 0x80000000
	// Bit TRP31.
	CAN_TXBRP_TRP31 = 0x80000000

	// TXBAR: Tx Buffer Add Request
	// Position of AR0 field.
	CAN_TXBAR_AR0_Pos = 0x0
	// Bit mask of AR0 field.
	CAN_TXBAR_AR0_Msk = 0x1
	// Bit AR0.
	CAN_TXBAR_AR0 = 0x1
	// Position of AR1 field.
	CAN_TXBAR_AR1_Pos = 0x1
	// Bit mask of AR1 field.
	CAN_TXBAR_AR1_Msk = 0x2
	// Bit AR1.
	CAN_TXBAR_AR1 = 0x2
	// Position of AR2 field.
	CAN_TXBAR_AR2_Pos = 0x2
	// Bit mask of AR2 field.
	CAN_TXBAR_AR2_Msk = 0x4
	// Bit AR2.
	CAN_TXBAR_AR2 = 0x4
	// Position of AR3 field.
	CAN_TXBAR_AR3_Pos = 0x3
	// Bit mask of AR3 field.
	CAN_TXBAR_AR3_Msk = 0x8
	// Bit AR3.
	CAN_TXBAR_AR3 = 0x8
	// Position of AR4 field.
	CAN_TXBAR_AR4_Pos = 0x4
	// Bit mask of AR4 field.
	CAN_TXBAR_AR4_Msk = 0x10
	// Bit AR4.
	CAN_TXBAR_AR4 = 0x10
	// Position of AR5 field.
	CAN_TXBAR_AR5_Pos = 0x5
	// Bit mask of AR5 field.
	CAN_TXBAR_AR5_Msk = 0x20
	// Bit AR5.
	CAN_TXBAR_AR5 = 0x20
	// Position of AR6 field.
	CAN_TXBAR_AR6_Pos = 0x6
	// Bit mask of AR6 field.
	CAN_TXBAR_AR6_Msk = 0x40
	// Bit AR6.
	CAN_TXBAR_AR6 = 0x40
	// Position of AR7 field.
	CAN_TXBAR_AR7_Pos = 0x7
	// Bit mask of AR7 field.
	CAN_TXBAR_AR7_Msk = 0x80
	// Bit AR7.
	CAN_TXBAR_AR7 = 0x80
	// Position of AR8 field.
	CAN_TXBAR_AR8_Pos = 0x8
	// Bit mask of AR8 field.
	CAN_TXBAR_AR8_Msk = 0x100
	// Bit AR8.
	CAN_TXBAR_AR8 = 0x100
	// Position of AR9 field.
	CAN_TXBAR_AR9_Pos = 0x9
	// Bit mask of AR9 field.
	CAN_TXBAR_AR9_Msk = 0x200
	// Bit AR9.
	CAN_TXBAR_AR9 = 0x200
	// Position of AR10 field.
	CAN_TXBAR_AR10_Pos = 0xa
	// Bit mask of AR10 field.
	CAN_TXBAR_AR10_Msk = 0x400
	// Bit AR10.
	CAN_TXBAR_AR10 = 0x400
	// Position of AR11 field.
	CAN_TXBAR_AR11_Pos = 0xb
	// Bit mask of AR11 field.
	CAN_TXBAR_AR11_Msk = 0x800
	// Bit AR11.
	CAN_TXBAR_AR11 = 0x800
	// Position of AR12 field.
	CAN_TXBAR_AR12_Pos = 0xc
	// Bit mask of AR12 field.
	CAN_TXBAR_AR12_Msk = 0x1000
	// Bit AR12.
	CAN_TXBAR_AR12 = 0x1000
	// Position of AR13 field.
	CAN_TXBAR_AR13_Pos = 0xd
	// Bit mask of AR13 field.
	CAN_TXBAR_AR13_Msk = 0x2000
	// Bit AR13.
	CAN_TXBAR_AR13 = 0x2000
	// Position of AR14 field.
	CAN_TXBAR_AR14_Pos = 0xe
	// Bit mask of AR14 field.
	CAN_TXBAR_AR14_Msk = 0x4000
	// Bit AR14.
	CAN_TXBAR_AR14 = 0x4000
	// Position of AR15 field.
	CAN_TXBAR_AR15_Pos = 0xf
	// Bit mask of AR15 field.
	CAN_TXBAR_AR15_Msk = 0x8000
	// Bit AR15.
	CAN_TXBAR_AR15 = 0x8000
	// Position of AR16 field.
	CAN_TXBAR_AR16_Pos = 0x10
	// Bit mask of AR16 field.
	CAN_TXBAR_AR16_Msk = 0x10000
	// Bit AR16.
	CAN_TXBAR_AR16 = 0x10000
	// Position of AR17 field.
	CAN_TXBAR_AR17_Pos = 0x11
	// Bit mask of AR17 field.
	CAN_TXBAR_AR17_Msk = 0x20000
	// Bit AR17.
	CAN_TXBAR_AR17 = 0x20000
	// Position of AR18 field.
	CAN_TXBAR_AR18_Pos = 0x12
	// Bit mask of AR18 field.
	CAN_TXBAR_AR18_Msk = 0x40000
	// Bit AR18.
	CAN_TXBAR_AR18 = 0x40000
	// Position of AR19 field.
	CAN_TXBAR_AR19_Pos = 0x13
	// Bit mask of AR19 field.
	CAN_TXBAR_AR19_Msk = 0x80000
	// Bit AR19.
	CAN_TXBAR_AR19 = 0x80000
	// Position of AR20 field.
	CAN_TXBAR_AR20_Pos = 0x14
	// Bit mask of AR20 field.
	CAN_TXBAR_AR20_Msk = 0x100000
	// Bit AR20.
	CAN_TXBAR_AR20 = 0x100000
	// Position of AR21 field.
	CAN_TXBAR_AR21_Pos = 0x15
	// Bit mask of AR21 field.
	CAN_TXBAR_AR21_Msk = 0x200000
	// Bit AR21.
	CAN_TXBAR_AR21 = 0x200000
	// Position of AR22 field.
	CAN_TXBAR_AR22_Pos = 0x16
	// Bit mask of AR22 field.
	CAN_TXBAR_AR22_Msk = 0x400000
	// Bit AR22.
	CAN_TXBAR_AR22 = 0x400000
	// Position of AR23 field.
	CAN_TXBAR_AR23_Pos = 0x17
	// Bit mask of AR23 field.
	CAN_TXBAR_AR23_Msk = 0x800000
	// Bit AR23.
	CAN_TXBAR_AR23 = 0x800000
	// Position of AR24 field.
	CAN_TXBAR_AR24_Pos = 0x18
	// Bit mask of AR24 field.
	CAN_TXBAR_AR24_Msk = 0x1000000
	// Bit AR24.
	CAN_TXBAR_AR24 = 0x1000000
	// Position of AR25 field.
	CAN_TXBAR_AR25_Pos = 0x19
	// Bit mask of AR25 field.
	CAN_TXBAR_AR25_Msk = 0x2000000
	// Bit AR25.
	CAN_TXBAR_AR25 = 0x2000000
	// Position of AR26 field.
	CAN_TXBAR_AR26_Pos = 0x1a
	// Bit mask of AR26 field.
	CAN_TXBAR_AR26_Msk = 0x4000000
	// Bit AR26.
	CAN_TXBAR_AR26 = 0x4000000
	// Position of AR27 field.
	CAN_TXBAR_AR27_Pos = 0x1b
	// Bit mask of AR27 field.
	CAN_TXBAR_AR27_Msk = 0x8000000
	// Bit AR27.
	CAN_TXBAR_AR27 = 0x8000000
	// Position of AR28 field.
	CAN_TXBAR_AR28_Pos = 0x1c
	// Bit mask of AR28 field.
	CAN_TXBAR_AR28_Msk = 0x10000000
	// Bit AR28.
	CAN_TXBAR_AR28 = 0x10000000
	// Position of AR29 field.
	CAN_TXBAR_AR29_Pos = 0x1d
	// Bit mask of AR29 field.
	CAN_TXBAR_AR29_Msk = 0x20000000
	// Bit AR29.
	CAN_TXBAR_AR29 = 0x20000000
	// Position of AR30 field.
	CAN_TXBAR_AR30_Pos = 0x1e
	// Bit mask of AR30 field.
	CAN_TXBAR_AR30_Msk = 0x40000000
	// Bit AR30.
	CAN_TXBAR_AR30 = 0x40000000
	// Position of AR31 field.
	CAN_TXBAR_AR31_Pos = 0x1f
	// Bit mask of AR31 field.
	CAN_TXBAR_AR31_Msk = 0x80000000
	// Bit AR31.
	CAN_TXBAR_AR31 = 0x80000000

	// TXBCR: Tx Buffer Cancellation Request
	// Position of CR0 field.
	CAN_TXBCR_CR0_Pos = 0x0
	// Bit mask of CR0 field.
	CAN_TXBCR_CR0_Msk = 0x1
	// Bit CR0.
	CAN_TXBCR_CR0 = 0x1
	// Position of CR1 field.
	CAN_TXBCR_CR1_Pos = 0x1
	// Bit mask of CR1 field.
	CAN_TXBCR_CR1_Msk = 0x2
	// Bit CR1.
	CAN_TXBCR_CR1 = 0x2
	// Position of CR2 field.
	CAN_TXBCR_CR2_Pos = 0x2
	// Bit mask of CR2 field.
	CAN_TXBCR_CR2_Msk = 0x4
	// Bit CR2.
	CAN_TXBCR_CR2 = 0x4
	// Position of CR3 field.
	CAN_TXBCR_CR3_Pos = 0x3
	// Bit mask of CR3 field.
	CAN_TXBCR_CR3_Msk = 0x8
	// Bit CR3.
	CAN_TXBCR_CR3 = 0x8
	// Position of CR4 field.
	CAN_TXBCR_CR4_Pos = 0x4
	// Bit mask of CR4 field.
	CAN_TXBCR_CR4_Msk = 0x10
	// Bit CR4.
	CAN_TXBCR_CR4 = 0x10
	// Position of CR5 field.
	CAN_TXBCR_CR5_Pos = 0x5
	// Bit mask of CR5 field.
	CAN_TXBCR_CR5_Msk = 0x20
	// Bit CR5.
	CAN_TXBCR_CR5 = 0x20
	// Position of CR6 field.
	CAN_TXBCR_CR6_Pos = 0x6
	// Bit mask of CR6 field.
	CAN_TXBCR_CR6_Msk = 0x40
	// Bit CR6.
	CAN_TXBCR_CR6 = 0x40
	// Position of CR7 field.
	CAN_TXBCR_CR7_Pos = 0x7
	// Bit mask of CR7 field.
	CAN_TXBCR_CR7_Msk = 0x80
	// Bit CR7.
	CAN_TXBCR_CR7 = 0x80
	// Position of CR8 field.
	CAN_TXBCR_CR8_Pos = 0x8
	// Bit mask of CR8 field.
	CAN_TXBCR_CR8_Msk = 0x100
	// Bit CR8.
	CAN_TXBCR_CR8 = 0x100
	// Position of CR9 field.
	CAN_TXBCR_CR9_Pos = 0x9
	// Bit mask of CR9 field.
	CAN_TXBCR_CR9_Msk = 0x200
	// Bit CR9.
	CAN_TXBCR_CR9 = 0x200
	// Position of CR10 field.
	CAN_TXBCR_CR10_Pos = 0xa
	// Bit mask of CR10 field.
	CAN_TXBCR_CR10_Msk = 0x400
	// Bit CR10.
	CAN_TXBCR_CR10 = 0x400
	// Position of CR11 field.
	CAN_TXBCR_CR11_Pos = 0xb
	// Bit mask of CR11 field.
	CAN_TXBCR_CR11_Msk = 0x800
	// Bit CR11.
	CAN_TXBCR_CR11 = 0x800
	// Position of CR12 field.
	CAN_TXBCR_CR12_Pos = 0xc
	// Bit mask of CR12 field.
	CAN_TXBCR_CR12_Msk = 0x1000
	// Bit CR12.
	CAN_TXBCR_CR12 = 0x1000
	// Position of CR13 field.
	CAN_TXBCR_CR13_Pos = 0xd
	// Bit mask of CR13 field.
	CAN_TXBCR_CR13_Msk = 0x2000
	// Bit CR13.
	CAN_TXBCR_CR13 = 0x2000
	// Position of CR14 field.
	CAN_TXBCR_CR14_Pos = 0xe
	// Bit mask of CR14 field.
	CAN_TXBCR_CR14_Msk = 0x4000
	// Bit CR14.
	CAN_TXBCR_CR14 = 0x4000
	// Position of CR15 field.
	CAN_TXBCR_CR15_Pos = 0xf
	// Bit mask of CR15 field.
	CAN_TXBCR_CR15_Msk = 0x8000
	// Bit CR15.
	CAN_TXBCR_CR15 = 0x8000
	// Position of CR16 field.
	CAN_TXBCR_CR16_Pos = 0x10
	// Bit mask of CR16 field.
	CAN_TXBCR_CR16_Msk = 0x10000
	// Bit CR16.
	CAN_TXBCR_CR16 = 0x10000
	// Position of CR17 field.
	CAN_TXBCR_CR17_Pos = 0x11
	// Bit mask of CR17 field.
	CAN_TXBCR_CR17_Msk = 0x20000
	// Bit CR17.
	CAN_TXBCR_CR17 = 0x20000
	// Position of CR18 field.
	CAN_TXBCR_CR18_Pos = 0x12
	// Bit mask of CR18 field.
	CAN_TXBCR_CR18_Msk = 0x40000
	// Bit CR18.
	CAN_TXBCR_CR18 = 0x40000
	// Position of CR19 field.
	CAN_TXBCR_CR19_Pos = 0x13
	// Bit mask of CR19 field.
	CAN_TXBCR_CR19_Msk = 0x80000
	// Bit CR19.
	CAN_TXBCR_CR19 = 0x80000
	// Position of CR20 field.
	CAN_TXBCR_CR20_Pos = 0x14
	// Bit mask of CR20 field.
	CAN_TXBCR_CR20_Msk = 0x100000
	// Bit CR20.
	CAN_TXBCR_CR20 = 0x100000
	// Position of CR21 field.
	CAN_TXBCR_CR21_Pos = 0x15
	// Bit mask of CR21 field.
	CAN_TXBCR_CR21_Msk = 0x200000
	// Bit CR21.
	CAN_TXBCR_CR21 = 0x200000
	// Position of CR22 field.
	CAN_TXBCR_CR22_Pos = 0x16
	// Bit mask of CR22 field.
	CAN_TXBCR_CR22_Msk = 0x400000
	// Bit CR22.
	CAN_TXBCR_CR22 = 0x400000
	// Position of CR23 field.
	CAN_TXBCR_CR23_Pos = 0x17
	// Bit mask of CR23 field.
	CAN_TXBCR_CR23_Msk = 0x800000
	// Bit CR23.
	CAN_TXBCR_CR23 = 0x800000
	// Position of CR24 field.
	CAN_TXBCR_CR24_Pos = 0x18
	// Bit mask of CR24 field.
	CAN_TXBCR_CR24_Msk = 0x1000000
	// Bit CR24.
	CAN_TXBCR_CR24 = 0x1000000
	// Position of CR25 field.
	CAN_TXBCR_CR25_Pos = 0x19
	// Bit mask of CR25 field.
	CAN_TXBCR_CR25_Msk = 0x2000000
	// Bit CR25.
	CAN_TXBCR_CR25 = 0x2000000
	// Position of CR26 field.
	CAN_TXBCR_CR26_Pos = 0x1a
	// Bit mask of CR26 field.
	CAN_TXBCR_CR26_Msk = 0x4000000
	// Bit CR26.
	CAN_TXBCR_CR26 = 0x4000000
	// Position of CR27 field.
	CAN_TXBCR_CR27_Pos = 0x1b
	// Bit mask of CR27 field.
	CAN_TXBCR_CR27_Msk = 0x8000000
	// Bit CR27.
	CAN_TXBCR_CR27 = 0x8000000
	// Position of CR28 field.
	CAN_TXBCR_CR28_Pos = 0x1c
	// Bit mask of CR28 field.
	CAN_TXBCR_CR28_Msk = 0x10000000
	// Bit CR28.
	CAN_TXBCR_CR28 = 0x10000000
	// Position of CR29 field.
	CAN_TXBCR_CR29_Pos = 0x1d
	// Bit mask of CR29 field.
	CAN_TXBCR_CR29_Msk = 0x20000000
	// Bit CR29.
	CAN_TXBCR_CR29 = 0x20000000
	// Position of CR30 field.
	CAN_TXBCR_CR30_Pos = 0x1e
	// Bit mask of CR30 field.
	CAN_TXBCR_CR30_Msk = 0x40000000
	// Bit CR30.
	CAN_TXBCR_CR30 = 0x40000000
	// Position of CR31 field.
	CAN_TXBCR_CR31_Pos = 0x1f
	// Bit mask of CR31 field.
	CAN_TXBCR_CR31_Msk = 0x80000000
	// Bit CR31.
	CAN_TXBCR_CR31 = 0x80000000

	// TXBTO: Tx Buffer Transmission Occurred
	// Position of TO0 field.
	CAN_TXBTO_TO0_Pos = 0x0
	// Bit mask of TO0 field.
	CAN_TXBTO_TO0_Msk = 0x1
	// Bit TO0.
	CAN_TXBTO_TO0 = 0x1
	// Position of TO1 field.
	CAN_TXBTO_TO1_Pos = 0x1
	// Bit mask of TO1 field.
	CAN_TXBTO_TO1_Msk = 0x2
	// Bit TO1.
	CAN_TXBTO_TO1 = 0x2
	// Position of TO2 field.
	CAN_TXBTO_TO2_Pos = 0x2
	// Bit mask of TO2 field.
	CAN_TXBTO_TO2_Msk = 0x4
	// Bit TO2.
	CAN_TXBTO_TO2 = 0x4
	// Position of TO3 field.
	CAN_TXBTO_TO3_Pos = 0x3
	// Bit mask of TO3 field.
	CAN_TXBTO_TO3_Msk = 0x8
	// Bit TO3.
	CAN_TXBTO_TO3 = 0x8
	// Position of TO4 field.
	CAN_TXBTO_TO4_Pos = 0x4
	// Bit mask of TO4 field.
	CAN_TXBTO_TO4_Msk = 0x10
	// Bit TO4.
	CAN_TXBTO_TO4 = 0x10
	// Position of TO5 field.
	CAN_TXBTO_TO5_Pos = 0x5
	// Bit mask of TO5 field.
	CAN_TXBTO_TO5_Msk = 0x20
	// Bit TO5.
	CAN_TXBTO_TO5 = 0x20
	// Position of TO6 field.
	CAN_TXBTO_TO6_Pos = 0x6
	// Bit mask of TO6 field.
	CAN_TXBTO_TO6_Msk = 0x40
	// Bit TO6.
	CAN_TXBTO_TO6 = 0x40
	// Position of TO7 field.
	CAN_TXBTO_TO7_Pos = 0x7
	// Bit mask of TO7 field.
	CAN_TXBTO_TO7_Msk = 0x80
	// Bit TO7.
	CAN_TXBTO_TO7 = 0x80
	// Position of TO8 field.
	CAN_TXBTO_TO8_Pos = 0x8
	// Bit mask of TO8 field.
	CAN_TXBTO_TO8_Msk = 0x100
	// Bit TO8.
	CAN_TXBTO_TO8 = 0x100
	// Position of TO9 field.
	CAN_TXBTO_TO9_Pos = 0x9
	// Bit mask of TO9 field.
	CAN_TXBTO_TO9_Msk = 0x200
	// Bit TO9.
	CAN_TXBTO_TO9 = 0x200
	// Position of TO10 field.
	CAN_TXBTO_TO10_Pos = 0xa
	// Bit mask of TO10 field.
	CAN_TXBTO_TO10_Msk = 0x400
	// Bit TO10.
	CAN_TXBTO_TO10 = 0x400
	// Position of TO11 field.
	CAN_TXBTO_TO11_Pos = 0xb
	// Bit mask of TO11 field.
	CAN_TXBTO_TO11_Msk = 0x800
	// Bit TO11.
	CAN_TXBTO_TO11 = 0x800
	// Position of TO12 field.
	CAN_TXBTO_TO12_Pos = 0xc
	// Bit mask of TO12 field.
	CAN_TXBTO_TO12_Msk = 0x1000
	// Bit TO12.
	CAN_TXBTO_TO12 = 0x1000
	// Position of TO13 field.
	CAN_TXBTO_TO13_Pos = 0xd
	// Bit mask of TO13 field.
	CAN_TXBTO_TO13_Msk = 0x2000
	// Bit TO13.
	CAN_TXBTO_TO13 = 0x2000
	// Position of TO14 field.
	CAN_TXBTO_TO14_Pos = 0xe
	// Bit mask of TO14 field.
	CAN_TXBTO_TO14_Msk = 0x4000
	// Bit TO14.
	CAN_TXBTO_TO14 = 0x4000
	// Position of TO15 field.
	CAN_TXBTO_TO15_Pos = 0xf
	// Bit mask of TO15 field.
	CAN_TXBTO_TO15_Msk = 0x8000
	// Bit TO15.
	CAN_TXBTO_TO15 = 0x8000
	// Position of TO16 field.
	CAN_TXBTO_TO16_Pos = 0x10
	// Bit mask of TO16 field.
	CAN_TXBTO_TO16_Msk = 0x10000
	// Bit TO16.
	CAN_TXBTO_TO16 = 0x10000
	// Position of TO17 field.
	CAN_TXBTO_TO17_Pos = 0x11
	// Bit mask of TO17 field.
	CAN_TXBTO_TO17_Msk = 0x20000
	// Bit TO17.
	CAN_TXBTO_TO17 = 0x20000
	// Position of TO18 field.
	CAN_TXBTO_TO18_Pos = 0x12
	// Bit mask of TO18 field.
	CAN_TXBTO_TO18_Msk = 0x40000
	// Bit TO18.
	CAN_TXBTO_TO18 = 0x40000
	// Position of TO19 field.
	CAN_TXBTO_TO19_Pos = 0x13
	// Bit mask of TO19 field.
	CAN_TXBTO_TO19_Msk = 0x80000
	// Bit TO19.
	CAN_TXBTO_TO19 = 0x80000
	// Position of TO20 field.
	CAN_TXBTO_TO20_Pos = 0x14
	// Bit mask of TO20 field.
	CAN_TXBTO_TO20_Msk = 0x100000
	// Bit TO20.
	CAN_TXBTO_TO20 = 0x100000
	// Position of TO21 field.
	CAN_TXBTO_TO21_Pos = 0x15
	// Bit mask of TO21 field.
	CAN_TXBTO_TO21_Msk = 0x200000
	// Bit TO21.
	CAN_TXBTO_TO21 = 0x200000
	// Position of TO22 field.
	CAN_TXBTO_TO22_Pos = 0x16
	// Bit mask of TO22 field.
	CAN_TXBTO_TO22_Msk = 0x400000
	// Bit TO22.
	CAN_TXBTO_TO22 = 0x400000
	// Position of TO23 field.
	CAN_TXBTO_TO23_Pos = 0x17
	// Bit mask of TO23 field.
	CAN_TXBTO_TO23_Msk = 0x800000
	// Bit TO23.
	CAN_TXBTO_TO23 = 0x800000
	// Position of TO24 field.
	CAN_TXBTO_TO24_Pos = 0x18
	// Bit mask of TO24 field.
	CAN_TXBTO_TO24_Msk = 0x1000000
	// Bit TO24.
	CAN_TXBTO_TO24 = 0x1000000
	// Position of TO25 field.
	CAN_TXBTO_TO25_Pos = 0x19
	// Bit mask of TO25 field.
	CAN_TXBTO_TO25_Msk = 0x2000000
	// Bit TO25.
	CAN_TXBTO_TO25 = 0x2000000
	// Position of TO26 field.
	CAN_TXBTO_TO26_Pos = 0x1a
	// Bit mask of TO26 field.
	CAN_TXBTO_TO26_Msk = 0x4000000
	// Bit TO26.
	CAN_TXBTO_TO26 = 0x4000000
	// Position of TO27 field.
	CAN_TXBTO_TO27_Pos = 0x1b
	// Bit mask of TO27 field.
	CAN_TXBTO_TO27_Msk = 0x8000000
	// Bit TO27.
	CAN_TXBTO_TO27 = 0x8000000
	// Position of TO28 field.
	CAN_TXBTO_TO28_Pos = 0x1c
	// Bit mask of TO28 field.
	CAN_TXBTO_TO28_Msk = 0x10000000
	// Bit TO28.
	CAN_TXBTO_TO28 = 0x10000000
	// Position of TO29 field.
	CAN_TXBTO_TO29_Pos = 0x1d
	// Bit mask of TO29 field.
	CAN_TXBTO_TO29_Msk = 0x20000000
	// Bit TO29.
	CAN_TXBTO_TO29 = 0x20000000
	// Position of TO30 field.
	CAN_TXBTO_TO30_Pos = 0x1e
	// Bit mask of TO30 field.
	CAN_TXBTO_TO30_Msk = 0x40000000
	// Bit TO30.
	CAN_TXBTO_TO30 = 0x40000000
	// Position of TO31 field.
	CAN_TXBTO_TO31_Pos = 0x1f
	// Bit mask of TO31 field.
	CAN_TXBTO_TO31_Msk = 0x80000000
	// Bit TO31.
	CAN_TXBTO_TO31 = 0x80000000

	// TXBCF: Tx Buffer Cancellation Finished
	// Position of CF0 field.
	CAN_TXBCF_CF0_Pos = 0x0
	// Bit mask of CF0 field.
	CAN_TXBCF_CF0_Msk = 0x1
	// Bit CF0.
	CAN_TXBCF_CF0 = 0x1
	// Position of CF1 field.
	CAN_TXBCF_CF1_Pos = 0x1
	// Bit mask of CF1 field.
	CAN_TXBCF_CF1_Msk = 0x2
	// Bit CF1.
	CAN_TXBCF_CF1 = 0x2
	// Position of CF2 field.
	CAN_TXBCF_CF2_Pos = 0x2
	// Bit mask of CF2 field.
	CAN_TXBCF_CF2_Msk = 0x4
	// Bit CF2.
	CAN_TXBCF_CF2 = 0x4
	// Position of CF3 field.
	CAN_TXBCF_CF3_Pos = 0x3
	// Bit mask of CF3 field.
	CAN_TXBCF_CF3_Msk = 0x8
	// Bit CF3.
	CAN_TXBCF_CF3 = 0x8
	// Position of CF4 field.
	CAN_TXBCF_CF4_Pos = 0x4
	// Bit mask of CF4 field.
	CAN_TXBCF_CF4_Msk = 0x10
	// Bit CF4.
	CAN_TXBCF_CF4 = 0x10
	// Position of CF5 field.
	CAN_TXBCF_CF5_Pos = 0x5
	// Bit mask of CF5 field.
	CAN_TXBCF_CF5_Msk = 0x20
	// Bit CF5.
	CAN_TXBCF_CF5 = 0x20
	// Position of CF6 field.
	CAN_TXBCF_CF6_Pos = 0x6
	// Bit mask of CF6 field.
	CAN_TXBCF_CF6_Msk = 0x40
	// Bit CF6.
	CAN_TXBCF_CF6 = 0x40
	// Position of CF7 field.
	CAN_TXBCF_CF7_Pos = 0x7
	// Bit mask of CF7 field.
	CAN_TXBCF_CF7_Msk = 0x80
	// Bit CF7.
	CAN_TXBCF_CF7 = 0x80
	// Position of CF8 field.
	CAN_TXBCF_CF8_Pos = 0x8
	// Bit mask of CF8 field.
	CAN_TXBCF_CF8_Msk = 0x100
	// Bit CF8.
	CAN_TXBCF_CF8 = 0x100
	// Position of CF9 field.
	CAN_TXBCF_CF9_Pos = 0x9
	// Bit mask of CF9 field.
	CAN_TXBCF_CF9_Msk = 0x200
	// Bit CF9.
	CAN_TXBCF_CF9 = 0x200
	// Position of CF10 field.
	CAN_TXBCF_CF10_Pos = 0xa
	// Bit mask of CF10 field.
	CAN_TXBCF_CF10_Msk = 0x400
	// Bit CF10.
	CAN_TXBCF_CF10 = 0x400
	// Position of CF11 field.
	CAN_TXBCF_CF11_Pos = 0xb
	// Bit mask of CF11 field.
	CAN_TXBCF_CF11_Msk = 0x800
	// Bit CF11.
	CAN_TXBCF_CF11 = 0x800
	// Position of CF12 field.
	CAN_TXBCF_CF12_Pos = 0xc
	// Bit mask of CF12 field.
	CAN_TXBCF_CF12_Msk = 0x1000
	// Bit CF12.
	CAN_TXBCF_CF12 = 0x1000
	// Position of CF13 field.
	CAN_TXBCF_CF13_Pos = 0xd
	// Bit mask of CF13 field.
	CAN_TXBCF_CF13_Msk = 0x2000
	// Bit CF13.
	CAN_TXBCF_CF13 = 0x2000
	// Position of CF14 field.
	CAN_TXBCF_CF14_Pos = 0xe
	// Bit mask of CF14 field.
	CAN_TXBCF_CF14_Msk = 0x4000
	// Bit CF14.
	CAN_TXBCF_CF14 = 0x4000
	// Position of CF15 field.
	CAN_TXBCF_CF15_Pos = 0xf
	// Bit mask of CF15 field.
	CAN_TXBCF_CF15_Msk = 0x8000
	// Bit CF15.
	CAN_TXBCF_CF15 = 0x8000
	// Position of CF16 field.
	CAN_TXBCF_CF16_Pos = 0x10
	// Bit mask of CF16 field.
	CAN_TXBCF_CF16_Msk = 0x10000
	// Bit CF16.
	CAN_TXBCF_CF16 = 0x10000
	// Position of CF17 field.
	CAN_TXBCF_CF17_Pos = 0x11
	// Bit mask of CF17 field.
	CAN_TXBCF_CF17_Msk = 0x20000
	// Bit CF17.
	CAN_TXBCF_CF17 = 0x20000
	// Position of CF18 field.
	CAN_TXBCF_CF18_Pos = 0x12
	// Bit mask of CF18 field.
	CAN_TXBCF_CF18_Msk = 0x40000
	// Bit CF18.
	CAN_TXBCF_CF18 = 0x40000
	// Position of CF19 field.
	CAN_TXBCF_CF19_Pos = 0x13
	// Bit mask of CF19 field.
	CAN_TXBCF_CF19_Msk = 0x80000
	// Bit CF19.
	CAN_TXBCF_CF19 = 0x80000
	// Position of CF20 field.
	CAN_TXBCF_CF20_Pos = 0x14
	// Bit mask of CF20 field.
	CAN_TXBCF_CF20_Msk = 0x100000
	// Bit CF20.
	CAN_TXBCF_CF20 = 0x100000
	// Position of CF21 field.
	CAN_TXBCF_CF21_Pos = 0x15
	// Bit mask of CF21 field.
	CAN_TXBCF_CF21_Msk = 0x200000
	// Bit CF21.
	CAN_TXBCF_CF21 = 0x200000
	// Position of CF22 field.
	CAN_TXBCF_CF22_Pos = 0x16
	// Bit mask of CF22 field.
	CAN_TXBCF_CF22_Msk = 0x400000
	// Bit CF22.
	CAN_TXBCF_CF22 = 0x400000
	// Position of CF23 field.
	CAN_TXBCF_CF23_Pos = 0x17
	// Bit mask of CF23 field.
	CAN_TXBCF_CF23_Msk = 0x800000
	// Bit CF23.
	CAN_TXBCF_CF23 = 0x800000
	// Position of CF24 field.
	CAN_TXBCF_CF24_Pos = 0x18
	// Bit mask of CF24 field.
	CAN_TXBCF_CF24_Msk = 0x1000000
	// Bit CF24.
	CAN_TXBCF_CF24 = 0x1000000
	// Position of CF25 field.
	CAN_TXBCF_CF25_Pos = 0x19
	// Bit mask of CF25 field.
	CAN_TXBCF_CF25_Msk = 0x2000000
	// Bit CF25.
	CAN_TXBCF_CF25 = 0x2000000
	// Position of CF26 field.
	CAN_TXBCF_CF26_Pos = 0x1a
	// Bit mask of CF26 field.
	CAN_TXBCF_CF26_Msk = 0x4000000
	// Bit CF26.
	CAN_TXBCF_CF26 = 0x4000000
	// Position of CF27 field.
	CAN_TXBCF_CF27_Pos = 0x1b
	// Bit mask of CF27 field.
	CAN_TXBCF_CF27_Msk = 0x8000000
	// Bit CF27.
	CAN_TXBCF_CF27 = 0x8000000
	// Position of CF28 field.
	CAN_TXBCF_CF28_Pos = 0x1c
	// Bit mask of CF28 field.
	CAN_TXBCF_CF28_Msk = 0x10000000
	// Bit CF28.
	CAN_TXBCF_CF28 = 0x10000000
	// Position of CF29 field.
	CAN_TXBCF_CF29_Pos = 0x1d
	// Bit mask of CF29 field.
	CAN_TXBCF_CF29_Msk = 0x20000000
	// Bit CF29.
	CAN_TXBCF_CF29 = 0x20000000
	// Position of CF30 field.
	CAN_TXBCF_CF30_Pos = 0x1e
	// Bit mask of CF30 field.
	CAN_TXBCF_CF30_Msk = 0x40000000
	// Bit CF30.
	CAN_TXBCF_CF30 = 0x40000000
	// Position of CF31 field.
	CAN_TXBCF_CF31_Pos = 0x1f
	// Bit mask of CF31 field.
	CAN_TXBCF_CF31_Msk = 0x80000000
	// Bit CF31.
	CAN_TXBCF_CF31 = 0x80000000

	// TXBTIE: Tx Buffer Transmission Interrupt Enable
	// Position of TIE0 field.
	CAN_TXBTIE_TIE0_Pos = 0x0
	// Bit mask of TIE0 field.
	CAN_TXBTIE_TIE0_Msk = 0x1
	// Bit TIE0.
	CAN_TXBTIE_TIE0 = 0x1
	// Position of TIE1 field.
	CAN_TXBTIE_TIE1_Pos = 0x1
	// Bit mask of TIE1 field.
	CAN_TXBTIE_TIE1_Msk = 0x2
	// Bit TIE1.
	CAN_TXBTIE_TIE1 = 0x2
	// Position of TIE2 field.
	CAN_TXBTIE_TIE2_Pos = 0x2
	// Bit mask of TIE2 field.
	CAN_TXBTIE_TIE2_Msk = 0x4
	// Bit TIE2.
	CAN_TXBTIE_TIE2 = 0x4
	// Position of TIE3 field.
	CAN_TXBTIE_TIE3_Pos = 0x3
	// Bit mask of TIE3 field.
	CAN_TXBTIE_TIE3_Msk = 0x8
	// Bit TIE3.
	CAN_TXBTIE_TIE3 = 0x8
	// Position of TIE4 field.
	CAN_TXBTIE_TIE4_Pos = 0x4
	// Bit mask of TIE4 field.
	CAN_TXBTIE_TIE4_Msk = 0x10
	// Bit TIE4.
	CAN_TXBTIE_TIE4 = 0x10
	// Position of TIE5 field.
	CAN_TXBTIE_TIE5_Pos = 0x5
	// Bit mask of TIE5 field.
	CAN_TXBTIE_TIE5_Msk = 0x20
	// Bit TIE5.
	CAN_TXBTIE_TIE5 = 0x20
	// Position of TIE6 field.
	CAN_TXBTIE_TIE6_Pos = 0x6
	// Bit mask of TIE6 field.
	CAN_TXBTIE_TIE6_Msk = 0x40
	// Bit TIE6.
	CAN_TXBTIE_TIE6 = 0x40
	// Position of TIE7 field.
	CAN_TXBTIE_TIE7_Pos = 0x7
	// Bit mask of TIE7 field.
	CAN_TXBTIE_TIE7_Msk = 0x80
	// Bit TIE7.
	CAN_TXBTIE_TIE7 = 0x80
	// Position of TIE8 field.
	CAN_TXBTIE_TIE8_Pos = 0x8
	// Bit mask of TIE8 field.
	CAN_TXBTIE_TIE8_Msk = 0x100
	// Bit TIE8.
	CAN_TXBTIE_TIE8 = 0x100
	// Position of TIE9 field.
	CAN_TXBTIE_TIE9_Pos = 0x9
	// Bit mask of TIE9 field.
	CAN_TXBTIE_TIE9_Msk = 0x200
	// Bit TIE9.
	CAN_TXBTIE_TIE9 = 0x200
	// Position of TIE10 field.
	CAN_TXBTIE_TIE10_Pos = 0xa
	// Bit mask of TIE10 field.
	CAN_TXBTIE_TIE10_Msk = 0x400
	// Bit TIE10.
	CAN_TXBTIE_TIE10 = 0x400
	// Position of TIE11 field.
	CAN_TXBTIE_TIE11_Pos = 0xb
	// Bit mask of TIE11 field.
	CAN_TXBTIE_TIE11_Msk = 0x800
	// Bit TIE11.
	CAN_TXBTIE_TIE11 = 0x800
	// Position of TIE12 field.
	CAN_TXBTIE_TIE12_Pos = 0xc
	// Bit mask of TIE12 field.
	CAN_TXBTIE_TIE12_Msk = 0x1000
	// Bit TIE12.
	CAN_TXBTIE_TIE12 = 0x1000
	// Position of TIE13 field.
	CAN_TXBTIE_TIE13_Pos = 0xd
	// Bit mask of TIE13 field.
	CAN_TXBTIE_TIE13_Msk = 0x2000
	// Bit TIE13.
	CAN_TXBTIE_TIE13 = 0x2000
	// Position of TIE14 field.
	CAN_TXBTIE_TIE14_Pos = 0xe
	// Bit mask of TIE14 field.
	CAN_TXBTIE_TIE14_Msk = 0x4000
	// Bit TIE14.
	CAN_TXBTIE_TIE14 = 0x4000
	// Position of TIE15 field.
	CAN_TXBTIE_TIE15_Pos = 0xf
	// Bit mask of TIE15 field.
	CAN_TXBTIE_TIE15_Msk = 0x8000
	// Bit TIE15.
	CAN_TXBTIE_TIE15 = 0x8000
	// Position of TIE16 field.
	CAN_TXBTIE_TIE16_Pos = 0x10
	// Bit mask of TIE16 field.
	CAN_TXBTIE_TIE16_Msk = 0x10000
	// Bit TIE16.
	CAN_TXBTIE_TIE16 = 0x10000
	// Position of TIE17 field.
	CAN_TXBTIE_TIE17_Pos = 0x11
	// Bit mask of TIE17 field.
	CAN_TXBTIE_TIE17_Msk = 0x20000
	// Bit TIE17.
	CAN_TXBTIE_TIE17 = 0x20000
	// Position of TIE18 field.
	CAN_TXBTIE_TIE18_Pos = 0x12
	// Bit mask of TIE18 field.
	CAN_TXBTIE_TIE18_Msk = 0x40000
	// Bit TIE18.
	CAN_TXBTIE_TIE18 = 0x40000
	// Position of TIE19 field.
	CAN_TXBTIE_TIE19_Pos = 0x13
	// Bit mask of TIE19 field.
	CAN_TXBTIE_TIE19_Msk = 0x80000
	// Bit TIE19.
	CAN_TXBTIE_TIE19 = 0x80000
	// Position of TIE20 field.
	CAN_TXBTIE_TIE20_Pos = 0x14
	// Bit mask of TIE20 field.
	CAN_TXBTIE_TIE20_Msk = 0x100000
	// Bit TIE20.
	CAN_TXBTIE_TIE20 = 0x100000
	// Position of TIE21 field.
	CAN_TXBTIE_TIE21_Pos = 0x15
	// Bit mask of TIE21 field.
	CAN_TXBTIE_TIE21_Msk = 0x200000
	// Bit TIE21.
	CAN_TXBTIE_TIE21 = 0x200000
	// Position of TIE22 field.
	CAN_TXBTIE_TIE22_Pos = 0x16
	// Bit mask of TIE22 field.
	CAN_TXBTIE_TIE22_Msk = 0x400000
	// Bit TIE22.
	CAN_TXBTIE_TIE22 = 0x400000
	// Position of TIE23 field.
	CAN_TXBTIE_TIE23_Pos = 0x17
	// Bit mask of TIE23 field.
	CAN_TXBTIE_TIE23_Msk = 0x800000
	// Bit TIE23.
	CAN_TXBTIE_TIE23 = 0x800000
	// Position of TIE24 field.
	CAN_TXBTIE_TIE24_Pos = 0x18
	// Bit mask of TIE24 field.
	CAN_TXBTIE_TIE24_Msk = 0x1000000
	// Bit TIE24.
	CAN_TXBTIE_TIE24 = 0x1000000
	// Position of TIE25 field.
	CAN_TXBTIE_TIE25_Pos = 0x19
	// Bit mask of TIE25 field.
	CAN_TXBTIE_TIE25_Msk = 0x2000000
	// Bit TIE25.
	CAN_TXBTIE_TIE25 = 0x2000000
	// Position of TIE26 field.
	CAN_TXBTIE_TIE26_Pos = 0x1a
	// Bit mask of TIE26 field.
	CAN_TXBTIE_TIE26_Msk = 0x4000000
	// Bit TIE26.
	CAN_TXBTIE_TIE26 = 0x4000000
	// Position of TIE27 field.
	CAN_TXBTIE_TIE27_Pos = 0x1b
	// Bit mask of TIE27 field.
	CAN_TXBTIE_TIE27_Msk = 0x8000000
	// Bit TIE27.
	CAN_TXBTIE_TIE27 = 0x8000000
	// Position of TIE28 field.
	CAN_TXBTIE_TIE28_Pos = 0x1c
	// Bit mask of TIE28 field.
	CAN_TXBTIE_TIE28_Msk = 0x10000000
	// Bit TIE28.
	CAN_TXBTIE_TIE28 = 0x10000000
	// Position of TIE29 field.
	CAN_TXBTIE_TIE29_Pos = 0x1d
	// Bit mask of TIE29 field.
	CAN_TXBTIE_TIE29_Msk = 0x20000000
	// Bit TIE29.
	CAN_TXBTIE_TIE29 = 0x20000000
	// Position of TIE30 field.
	CAN_TXBTIE_TIE30_Pos = 0x1e
	// Bit mask of TIE30 field.
	CAN_TXBTIE_TIE30_Msk = 0x40000000
	// Bit TIE30.
	CAN_TXBTIE_TIE30 = 0x40000000
	// Position of TIE31 field.
	CAN_TXBTIE_TIE31_Pos = 0x1f
	// Bit mask of TIE31 field.
	CAN_TXBTIE_TIE31_Msk = 0x80000000
	// Bit TIE31.
	CAN_TXBTIE_TIE31 = 0x80000000

	// TXBCIE: Tx Buffer Cancellation Finished Interrupt Enable
	// Position of CFIE0 field.
	CAN_TXBCIE_CFIE0_Pos = 0x0
	// Bit mask of CFIE0 field.
	CAN_TXBCIE_CFIE0_Msk = 0x1
	// Bit CFIE0.
	CAN_TXBCIE_CFIE0 = 0x1
	// Position of CFIE1 field.
	CAN_TXBCIE_CFIE1_Pos = 0x1
	// Bit mask of CFIE1 field.
	CAN_TXBCIE_CFIE1_Msk = 0x2
	// Bit CFIE1.
	CAN_TXBCIE_CFIE1 = 0x2
	// Position of CFIE2 field.
	CAN_TXBCIE_CFIE2_Pos = 0x2
	// Bit mask of CFIE2 field.
	CAN_TXBCIE_CFIE2_Msk = 0x4
	// Bit CFIE2.
	CAN_TXBCIE_CFIE2 = 0x4
	// Position of CFIE3 field.
	CAN_TXBCIE_CFIE3_Pos = 0x3
	// Bit mask of CFIE3 field.
	CAN_TXBCIE_CFIE3_Msk = 0x8
	// Bit CFIE3.
	CAN_TXBCIE_CFIE3 = 0x8
	// Position of CFIE4 field.
	CAN_TXBCIE_CFIE4_Pos = 0x4
	// Bit mask of CFIE4 field.
	CAN_TXBCIE_CFIE4_Msk = 0x10
	// Bit CFIE4.
	CAN_TXBCIE_CFIE4 = 0x10
	// Position of CFIE5 field.
	CAN_TXBCIE_CFIE5_Pos = 0x5
	// Bit mask of CFIE5 field.
	CAN_TXBCIE_CFIE5_Msk = 0x20
	// Bit CFIE5.
	CAN_TXBCIE_CFIE5 = 0x20
	// Position of CFIE6 field.
	CAN_TXBCIE_CFIE6_Pos = 0x6
	// Bit mask of CFIE6 field.
	CAN_TXBCIE_CFIE6_Msk = 0x40
	// Bit CFIE6.
	CAN_TXBCIE_CFIE6 = 0x40
	// Position of CFIE7 field.
	CAN_TXBCIE_CFIE7_Pos = 0x7
	// Bit mask of CFIE7 field.
	CAN_TXBCIE_CFIE7_Msk = 0x80
	// Bit CFIE7.
	CAN_TXBCIE_CFIE7 = 0x80
	// Position of CFIE8 field.
	CAN_TXBCIE_CFIE8_Pos = 0x8
	// Bit mask of CFIE8 field.
	CAN_TXBCIE_CFIE8_Msk = 0x100
	// Bit CFIE8.
	CAN_TXBCIE_CFIE8 = 0x100
	// Position of CFIE9 field.
	CAN_TXBCIE_CFIE9_Pos = 0x9
	// Bit mask of CFIE9 field.
	CAN_TXBCIE_CFIE9_Msk = 0x200
	// Bit CFIE9.
	CAN_TXBCIE_CFIE9 = 0x200
	// Position of CFIE10 field.
	CAN_TXBCIE_CFIE10_Pos = 0xa
	// Bit mask of CFIE10 field.
	CAN_TXBCIE_CFIE10_Msk = 0x400
	// Bit CFIE10.
	CAN_TXBCIE_CFIE10 = 0x400
	// Position of CFIE11 field.
	CAN_TXBCIE_CFIE11_Pos = 0xb
	// Bit mask of CFIE11 field.
	CAN_TXBCIE_CFIE11_Msk = 0x800
	// Bit CFIE11.
	CAN_TXBCIE_CFIE11 = 0x800
	// Position of CFIE12 field.
	CAN_TXBCIE_CFIE12_Pos = 0xc
	// Bit mask of CFIE12 field.
	CAN_TXBCIE_CFIE12_Msk = 0x1000
	// Bit CFIE12.
	CAN_TXBCIE_CFIE12 = 0x1000
	// Position of CFIE13 field.
	CAN_TXBCIE_CFIE13_Pos = 0xd
	// Bit mask of CFIE13 field.
	CAN_TXBCIE_CFIE13_Msk = 0x2000
	// Bit CFIE13.
	CAN_TXBCIE_CFIE13 = 0x2000
	// Position of CFIE14 field.
	CAN_TXBCIE_CFIE14_Pos = 0xe
	// Bit mask of CFIE14 field.
	CAN_TXBCIE_CFIE14_Msk = 0x4000
	// Bit CFIE14.
	CAN_TXBCIE_CFIE14 = 0x4000
	// Position of CFIE15 field.
	CAN_TXBCIE_CFIE15_Pos = 0xf
	// Bit mask of CFIE15 field.
	CAN_TXBCIE_CFIE15_Msk = 0x8000
	// Bit CFIE15.
	CAN_TXBCIE_CFIE15 = 0x8000
	// Position of CFIE16 field.
	CAN_TXBCIE_CFIE16_Pos = 0x10
	// Bit mask of CFIE16 field.
	CAN_TXBCIE_CFIE16_Msk = 0x10000
	// Bit CFIE16.
	CAN_TXBCIE_CFIE16 = 0x10000
	// Position of CFIE17 field.
	CAN_TXBCIE_CFIE17_Pos = 0x11
	// Bit mask of CFIE17 field.
	CAN_TXBCIE_CFIE17_Msk = 0x20000
	// Bit CFIE17.
	CAN_TXBCIE_CFIE17 = 0x20000
	// Position of CFIE18 field.
	CAN_TXBCIE_CFIE18_Pos = 0x12
	// Bit mask of CFIE18 field.
	CAN_TXBCIE_CFIE18_Msk = 0x40000
	// Bit CFIE18.
	CAN_TXBCIE_CFIE18 = 0x40000
	// Position of CFIE19 field.
	CAN_TXBCIE_CFIE19_Pos = 0x13
	// Bit mask of CFIE19 field.
	CAN_TXBCIE_CFIE19_Msk = 0x80000
	// Bit CFIE19.
	CAN_TXBCIE_CFIE19 = 0x80000
	// Position of CFIE20 field.
	CAN_TXBCIE_CFIE20_Pos = 0x14
	// Bit mask of CFIE20 field.
	CAN_TXBCIE_CFIE20_Msk = 0x100000
	// Bit CFIE20.
	CAN_TXBCIE_CFIE20 = 0x100000
	// Position of CFIE21 field.
	CAN_TXBCIE_CFIE21_Pos = 0x15
	// Bit mask of CFIE21 field.
	CAN_TXBCIE_CFIE21_Msk = 0x200000
	// Bit CFIE21.
	CAN_TXBCIE_CFIE21 = 0x200000
	// Position of CFIE22 field.
	CAN_TXBCIE_CFIE22_Pos = 0x16
	// Bit mask of CFIE22 field.
	CAN_TXBCIE_CFIE22_Msk = 0x400000
	// Bit CFIE22.
	CAN_TXBCIE_CFIE22 = 0x400000
	// Position of CFIE23 field.
	CAN_TXBCIE_CFIE23_Pos = 0x17
	// Bit mask of CFIE23 field.
	CAN_TXBCIE_CFIE23_Msk = 0x800000
	// Bit CFIE23.
	CAN_TXBCIE_CFIE23 = 0x800000
	// Position of CFIE24 field.
	CAN_TXBCIE_CFIE24_Pos = 0x18
	// Bit mask of CFIE24 field.
	CAN_TXBCIE_CFIE24_Msk = 0x1000000
	// Bit CFIE24.
	CAN_TXBCIE_CFIE24 = 0x1000000
	// Position of CFIE25 field.
	CAN_TXBCIE_CFIE25_Pos = 0x19
	// Bit mask of CFIE25 field.
	CAN_TXBCIE_CFIE25_Msk = 0x2000000
	// Bit CFIE25.
	CAN_TXBCIE_CFIE25 = 0x2000000
	// Position of CFIE26 field.
	CAN_TXBCIE_CFIE26_Pos = 0x1a
	// Bit mask of CFIE26 field.
	CAN_TXBCIE_CFIE26_Msk = 0x4000000
	// Bit CFIE26.
	CAN_TXBCIE_CFIE26 = 0x4000000
	// Position of CFIE27 field.
	CAN_TXBCIE_CFIE27_Pos = 0x1b
	// Bit mask of CFIE27 field.
	CAN_TXBCIE_CFIE27_Msk = 0x8000000
	// Bit CFIE27.
	CAN_TXBCIE_CFIE27 = 0x8000000
	// Position of CFIE28 field.
	CAN_TXBCIE_CFIE28_Pos = 0x1c
	// Bit mask of CFIE28 field.
	CAN_TXBCIE_CFIE28_Msk = 0x10000000
	// Bit CFIE28.
	CAN_TXBCIE_CFIE28 = 0x10000000
	// Position of CFIE29 field.
	CAN_TXBCIE_CFIE29_Pos = 0x1d
	// Bit mask of CFIE29 field.
	CAN_TXBCIE_CFIE29_Msk = 0x20000000
	// Bit CFIE29.
	CAN_TXBCIE_CFIE29 = 0x20000000
	// Position of CFIE30 field.
	CAN_TXBCIE_CFIE30_Pos = 0x1e
	// Bit mask of CFIE30 field.
	CAN_TXBCIE_CFIE30_Msk = 0x40000000
	// Bit CFIE30.
	CAN_TXBCIE_CFIE30 = 0x40000000
	// Position of CFIE31 field.
	CAN_TXBCIE_CFIE31_Pos = 0x1f
	// Bit mask of CFIE31 field.
	CAN_TXBCIE_CFIE31_Msk = 0x80000000
	// Bit CFIE31.
	CAN_TXBCIE_CFIE31 = 0x80000000

	// TXEFC: Tx Event FIFO Configuration
	// Position of EFSA field.
	CAN_TXEFC_EFSA_Pos = 0x0
	// Bit mask of EFSA field.
	CAN_TXEFC_EFSA_Msk = 0xffff
	// Position of EFS field.
	CAN_TXEFC_EFS_Pos = 0x10
	// Bit mask of EFS field.
	CAN_TXEFC_EFS_Msk = 0x3f0000
	// Position of EFWM field.
	CAN_TXEFC_EFWM_Pos = 0x18
	// Bit mask of EFWM field.
	CAN_TXEFC_EFWM_Msk = 0x3f000000

	// TXEFS: Tx Event FIFO Status
	// Position of EFFL field.
	CAN_TXEFS_EFFL_Pos = 0x0
	// Bit mask of EFFL field.
	CAN_TXEFS_EFFL_Msk = 0x3f
	// Position of EFGI field.
	CAN_TXEFS_EFGI_Pos = 0x8
	// Bit mask of EFGI field.
	CAN_TXEFS_EFGI_Msk = 0x1f00
	// Position of EFPI field.
	CAN_TXEFS_EFPI_Pos = 0x10
	// Bit mask of EFPI field.
	CAN_TXEFS_EFPI_Msk = 0x1f0000
	// Position of EFF field.
	CAN_TXEFS_EFF_Pos = 0x18
	// Bit mask of EFF field.
	CAN_TXEFS_EFF_Msk = 0x1000000
	// Bit EFF.
	CAN_TXEFS_EFF = 0x1000000
	// Position of TEFL field.
	CAN_TXEFS_TEFL_Pos = 0x19
	// Bit mask of TEFL field.
	CAN_TXEFS_TEFL_Msk = 0x2000000
	// Bit TEFL.
	CAN_TXEFS_TEFL = 0x2000000

	// TXEFA: Tx Event FIFO Acknowledge
	// Position of EFAI field.
	CAN_TXEFA_EFAI_Pos = 0x0
	// Bit mask of EFAI field.
	CAN_TXEFA_EFAI_Msk = 0x1f
)

// Bitfields for CCL: Configurable Custom Logic
const (
	// CTRL: Control
	// Position of SWRST field.
	CCL_CTRL_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	CCL_CTRL_SWRST_Msk = 0x1
	// Bit SWRST.
	CCL_CTRL_SWRST = 0x1
	// Position of ENABLE field.
	CCL_CTRL_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	CCL_CTRL_ENABLE_Msk = 0x2
	// Bit ENABLE.
	CCL_CTRL_ENABLE = 0x2
	// Position of RUNSTDBY field.
	CCL_CTRL_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	CCL_CTRL_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	CCL_CTRL_RUNSTDBY = 0x40

	// SEQCTRL: SEQ Control x
	// Position of SEQSEL field.
	CCL_SEQCTRL_SEQSEL_Pos = 0x0
	// Bit mask of SEQSEL field.
	CCL_SEQCTRL_SEQSEL_Msk = 0xf
	// Sequential logic is disabled
	CCL_SEQCTRL_SEQSEL_DISABLE = 0x0
	// D flip flop
	CCL_SEQCTRL_SEQSEL_DFF = 0x1
	// JK flip flop
	CCL_SEQCTRL_SEQSEL_JK = 0x2
	// D latch
	CCL_SEQCTRL_SEQSEL_LATCH = 0x3
	// RS latch
	CCL_SEQCTRL_SEQSEL_RS = 0x4

	// LUTCTRL: LUT Control x
	// Position of ENABLE field.
	CCL_LUTCTRL_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	CCL_LUTCTRL_ENABLE_Msk = 0x2
	// Bit ENABLE.
	CCL_LUTCTRL_ENABLE = 0x2
	// Position of FILTSEL field.
	CCL_LUTCTRL_FILTSEL_Pos = 0x4
	// Bit mask of FILTSEL field.
	CCL_LUTCTRL_FILTSEL_Msk = 0x30
	// Filter disabled
	CCL_LUTCTRL_FILTSEL_DISABLE = 0x0
	// Synchronizer enabled
	CCL_LUTCTRL_FILTSEL_SYNCH = 0x1
	// Filter enabled
	CCL_LUTCTRL_FILTSEL_FILTER = 0x2
	// Position of EDGESEL field.
	CCL_LUTCTRL_EDGESEL_Pos = 0x7
	// Bit mask of EDGESEL field.
	CCL_LUTCTRL_EDGESEL_Msk = 0x80
	// Bit EDGESEL.
	CCL_LUTCTRL_EDGESEL = 0x80
	// Position of INSEL0 field.
	CCL_LUTCTRL_INSEL0_Pos = 0x8
	// Bit mask of INSEL0 field.
	CCL_LUTCTRL_INSEL0_Msk = 0xf00
	// Masked input
	CCL_LUTCTRL_INSEL0_MASK = 0x0
	// Feedback input source
	CCL_LUTCTRL_INSEL0_FEEDBACK = 0x1
	// Linked LUT input source
	CCL_LUTCTRL_INSEL0_LINK = 0x2
	// Event input source
	CCL_LUTCTRL_INSEL0_EVENT = 0x3
	// I/O pin input source
	CCL_LUTCTRL_INSEL0_IO = 0x4
	// AC input source
	CCL_LUTCTRL_INSEL0_AC = 0x5
	// TC input source
	CCL_LUTCTRL_INSEL0_TC = 0x6
	// Alternate TC input source
	CCL_LUTCTRL_INSEL0_ALTTC = 0x7
	// TCC input source
	CCL_LUTCTRL_INSEL0_TCC = 0x8
	// SERCOM input source
	CCL_LUTCTRL_INSEL0_SERCOM = 0x9
	// Position of INSEL1 field.
	CCL_LUTCTRL_INSEL1_Pos = 0xc
	// Bit mask of INSEL1 field.
	CCL_LUTCTRL_INSEL1_Msk = 0xf000
	// Masked input
	CCL_LUTCTRL_INSEL1_MASK = 0x0
	// Feedback input source
	CCL_LUTCTRL_INSEL1_FEEDBACK = 0x1
	// Linked LUT input source
	CCL_LUTCTRL_INSEL1_LINK = 0x2
	// Event input source
	CCL_LUTCTRL_INSEL1_EVENT = 0x3
	// I/O pin input source
	CCL_LUTCTRL_INSEL1_IO = 0x4
	// AC input source
	CCL_LUTCTRL_INSEL1_AC = 0x5
	// TC input source
	CCL_LUTCTRL_INSEL1_TC = 0x6
	// Alternate TC input source
	CCL_LUTCTRL_INSEL1_ALTTC = 0x7
	// TCC input source
	CCL_LUTCTRL_INSEL1_TCC = 0x8
	// SERCOM input source
	CCL_LUTCTRL_INSEL1_SERCOM = 0x9
	// Position of INSEL2 field.
	CCL_LUTCTRL_INSEL2_Pos = 0x10
	// Bit mask of INSEL2 field.
	CCL_LUTCTRL_INSEL2_Msk = 0xf0000
	// Masked input
	CCL_LUTCTRL_INSEL2_MASK = 0x0
	// Feedback input source
	CCL_LUTCTRL_INSEL2_FEEDBACK = 0x1
	// Linked LUT input source
	CCL_LUTCTRL_INSEL2_LINK = 0x2
	// Event input source
	CCL_LUTCTRL_INSEL2_EVENT = 0x3
	// I/O pin input source
	CCL_LUTCTRL_INSEL2_IO = 0x4
	// AC input source
	CCL_LUTCTRL_INSEL2_AC = 0x5
	// TC input source
	CCL_LUTCTRL_INSEL2_TC = 0x6
	// Alternate TC input source
	CCL_LUTCTRL_INSEL2_ALTTC = 0x7
	// TCC input source
	CCL_LUTCTRL_INSEL2_TCC = 0x8
	// SERCOM input source
	CCL_LUTCTRL_INSEL2_SERCOM = 0x9
	// Position of INVEI field.
	CCL_LUTCTRL_INVEI_Pos = 0x14
	// Bit mask of INVEI field.
	CCL_LUTCTRL_INVEI_Msk = 0x100000
	// Bit INVEI.
	CCL_LUTCTRL_INVEI = 0x100000
	// Position of LUTEI field.
	CCL_LUTCTRL_LUTEI_Pos = 0x15
	// Bit mask of LUTEI field.
	CCL_LUTCTRL_LUTEI_Msk = 0x200000
	// Bit LUTEI.
	CCL_LUTCTRL_LUTEI = 0x200000
	// Position of LUTEO field.
	CCL_LUTCTRL_LUTEO_Pos = 0x16
	// Bit mask of LUTEO field.
	CCL_LUTCTRL_LUTEO_Msk = 0x400000
	// Bit LUTEO.
	CCL_LUTCTRL_LUTEO = 0x400000
	// Position of TRUTH field.
	CCL_LUTCTRL_TRUTH_Pos = 0x18
	// Bit mask of TRUTH field.
	CCL_LUTCTRL_TRUTH_Msk = 0xff000000
)

// Bitfields for CMCC: Cortex M Cache Controller
const (
	// TYPE: Cache Type Register
	// Position of GCLK field.
	CMCC_TYPE_GCLK_Pos = 0x1
	// Bit mask of GCLK field.
	CMCC_TYPE_GCLK_Msk = 0x2
	// Bit GCLK.
	CMCC_TYPE_GCLK = 0x2
	// Position of RRP field.
	CMCC_TYPE_RRP_Pos = 0x4
	// Bit mask of RRP field.
	CMCC_TYPE_RRP_Msk = 0x10
	// Bit RRP.
	CMCC_TYPE_RRP = 0x10
	// Position of WAYNUM field.
	CMCC_TYPE_WAYNUM_Pos = 0x5
	// Bit mask of WAYNUM field.
	CMCC_TYPE_WAYNUM_Msk = 0x60
	// Direct Mapped Cache
	CMCC_TYPE_WAYNUM_DMAPPED = 0x0
	// 2-WAY set associative
	CMCC_TYPE_WAYNUM_ARCH2WAY = 0x1
	// 4-WAY set associative
	CMCC_TYPE_WAYNUM_ARCH4WAY = 0x2
	// Position of LCKDOWN field.
	CMCC_TYPE_LCKDOWN_Pos = 0x7
	// Bit mask of LCKDOWN field.
	CMCC_TYPE_LCKDOWN_Msk = 0x80
	// Bit LCKDOWN.
	CMCC_TYPE_LCKDOWN = 0x80
	// Position of CSIZE field.
	CMCC_TYPE_CSIZE_Pos = 0x8
	// Bit mask of CSIZE field.
	CMCC_TYPE_CSIZE_Msk = 0x700
	// Cache Size is 1 KB
	CMCC_TYPE_CSIZE_CSIZE_1KB = 0x0
	// Cache Size is 2 KB
	CMCC_TYPE_CSIZE_CSIZE_2KB = 0x1
	// Cache Size is 4 KB
	CMCC_TYPE_CSIZE_CSIZE_4KB = 0x2
	// Cache Size is 8 KB
	CMCC_TYPE_CSIZE_CSIZE_8KB = 0x3
	// Cache Size is 16 KB
	CMCC_TYPE_CSIZE_CSIZE_16KB = 0x4
	// Cache Size is 32 KB
	CMCC_TYPE_CSIZE_CSIZE_32KB = 0x5
	// Cache Size is 64 KB
	CMCC_TYPE_CSIZE_CSIZE_64KB = 0x6
	// Position of CLSIZE field.
	CMCC_TYPE_CLSIZE_Pos = 0xb
	// Bit mask of CLSIZE field.
	CMCC_TYPE_CLSIZE_Msk = 0x3800
	// Cache Line Size is 4 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_4B = 0x0
	// Cache Line Size is 8 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_8B = 0x1
	// Cache Line Size is 16 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_16B = 0x2
	// Cache Line Size is 32 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_32B = 0x3
	// Cache Line Size is 64 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_64B = 0x4
	// Cache Line Size is 128 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_128B = 0x5

	// CFG: Cache Configuration Register
	// Position of ICDIS field.
	CMCC_CFG_ICDIS_Pos = 0x1
	// Bit mask of ICDIS field.
	CMCC_CFG_ICDIS_Msk = 0x2
	// Bit ICDIS.
	CMCC_CFG_ICDIS = 0x2
	// Position of DCDIS field.
	CMCC_CFG_DCDIS_Pos = 0x2
	// Bit mask of DCDIS field.
	CMCC_CFG_DCDIS_Msk = 0x4
	// Bit DCDIS.
	CMCC_CFG_DCDIS = 0x4
	// Position of CSIZESW field.
	CMCC_CFG_CSIZESW_Pos = 0x4
	// Bit mask of CSIZESW field.
	CMCC_CFG_CSIZESW_Msk = 0x70
	// The Cache Size is configured to 1KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_1KB = 0x0
	// The Cache Size is configured to 2KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_2KB = 0x1
	// The Cache Size is configured to 4KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_4KB = 0x2
	// The Cache Size is configured to 8KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_8KB = 0x3
	// The Cache Size is configured to 16KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_16KB = 0x4
	// The Cache Size is configured to 32KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_32KB = 0x5
	// The Cache Size is configured to 64KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_64KB = 0x6

	// CTRL: Cache Control Register
	// Position of CEN field.
	CMCC_CTRL_CEN_Pos = 0x0
	// Bit mask of CEN field.
	CMCC_CTRL_CEN_Msk = 0x1
	// Bit CEN.
	CMCC_CTRL_CEN = 0x1

	// SR: Cache Status Register
	// Position of CSTS field.
	CMCC_SR_CSTS_Pos = 0x0
	// Bit mask of CSTS field.
	CMCC_SR_CSTS_Msk = 0x1
	// Bit CSTS.
	CMCC_SR_CSTS = 0x1

	// LCKWAY: Cache Lock per Way Register
	// Position of LCKWAY field.
	CMCC_LCKWAY_LCKWAY_Pos = 0x0
	// Bit mask of LCKWAY field.
	CMCC_LCKWAY_LCKWAY_Msk = 0xf

	// MAINT0: Cache Maintenance Register 0
	// Position of INVALL field.
	CMCC_MAINT0_INVALL_Pos = 0x0
	// Bit mask of INVALL field.
	CMCC_MAINT0_INVALL_Msk = 0x1
	// Bit INVALL.
	CMCC_MAINT0_INVALL = 0x1

	// MAINT1: Cache Maintenance Register 1
	// Position of INDEX field.
	CMCC_MAINT1_INDEX_Pos = 0x4
	// Bit mask of INDEX field.
	CMCC_MAINT1_INDEX_Msk = 0xff0
	// Position of WAY field.
	CMCC_MAINT1_WAY_Pos = 0x1c
	// Bit mask of WAY field.
	CMCC_MAINT1_WAY_Msk = 0xf0000000
	// Way 0 is selection for index invalidation
	CMCC_MAINT1_WAY_WAY0 = 0x0
	// Way 1 is selection for index invalidation
	CMCC_MAINT1_WAY_WAY1 = 0x1
	// Way 2 is selection for index invalidation
	CMCC_MAINT1_WAY_WAY2 = 0x2
	// Way 3 is selection for index invalidation
	CMCC_MAINT1_WAY_WAY3 = 0x3

	// MCFG: Cache Monitor Configuration Register
	// Position of MODE field.
	CMCC_MCFG_MODE_Pos = 0x0
	// Bit mask of MODE field.
	CMCC_MCFG_MODE_Msk = 0x3
	// Cycle counter
	CMCC_MCFG_MODE_CYCLE_COUNT = 0x0
	// Instruction hit counter
	CMCC_MCFG_MODE_IHIT_COUNT = 0x1
	// Data hit counter
	CMCC_MCFG_MODE_DHIT_COUNT = 0x2

	// MEN: Cache Monitor Enable Register
	// Position of MENABLE field.
	CMCC_MEN_MENABLE_Pos = 0x0
	// Bit mask of MENABLE field.
	CMCC_MEN_MENABLE_Msk = 0x1
	// Bit MENABLE.
	CMCC_MEN_MENABLE = 0x1

	// MCTRL: Cache Monitor Control Register
	// Position of SWRST field.
	CMCC_MCTRL_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	CMCC_MCTRL_SWRST_Msk = 0x1
	// Bit SWRST.
	CMCC_MCTRL_SWRST = 0x1

	// MSR: Cache Monitor Status Register
	// Position of EVENT_CNT field.
	CMCC_MSR_EVENT_CNT_Pos = 0x0
	// Bit mask of EVENT_CNT field.
	CMCC_MSR_EVENT_CNT_Msk = 0xffffffff
)

// Bitfields for DAC: Digital-to-Analog Converter
const (
	// CTRLA: Control A
	// Position of SWRST field.
	DAC_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	DAC_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	DAC_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	DAC_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	DAC_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	DAC_CTRLA_ENABLE = 0x2

	// CTRLB: Control B
	// Position of DIFF field.
	DAC_CTRLB_DIFF_Pos = 0x0
	// Bit mask of DIFF field.
	DAC_CTRLB_DIFF_Msk = 0x1
	// Bit DIFF.
	DAC_CTRLB_DIFF = 0x1
	// Position of REFSEL field.
	DAC_CTRLB_REFSEL_Pos = 0x1
	// Bit mask of REFSEL field.
	DAC_CTRLB_REFSEL_Msk = 0x6
	// External reference unbuffered
	DAC_CTRLB_REFSEL_VREFPU = 0x0
	// Analog supply
	DAC_CTRLB_REFSEL_VDDANA = 0x1
	// External reference buffered
	DAC_CTRLB_REFSEL_VREFPB = 0x2
	// Internal bandgap reference
	DAC_CTRLB_REFSEL_INTREF = 0x3

	// EVCTRL: Event Control
	// Position of STARTEI0 field.
	DAC_EVCTRL_STARTEI0_Pos = 0x0
	// Bit mask of STARTEI0 field.
	DAC_EVCTRL_STARTEI0_Msk = 0x1
	// Bit STARTEI0.
	DAC_EVCTRL_STARTEI0 = 0x1
	// Position of STARTEI1 field.
	DAC_EVCTRL_STARTEI1_Pos = 0x1
	// Bit mask of STARTEI1 field.
	DAC_EVCTRL_STARTEI1_Msk = 0x2
	// Bit STARTEI1.
	DAC_EVCTRL_STARTEI1 = 0x2
	// Position of EMPTYEO0 field.
	DAC_EVCTRL_EMPTYEO0_Pos = 0x2
	// Bit mask of EMPTYEO0 field.
	DAC_EVCTRL_EMPTYEO0_Msk = 0x4
	// Bit EMPTYEO0.
	DAC_EVCTRL_EMPTYEO0 = 0x4
	// Position of EMPTYEO1 field.
	DAC_EVCTRL_EMPTYEO1_Pos = 0x3
	// Bit mask of EMPTYEO1 field.
	DAC_EVCTRL_EMPTYEO1_Msk = 0x8
	// Bit EMPTYEO1.
	DAC_EVCTRL_EMPTYEO1 = 0x8
	// Position of INVEI0 field.
	DAC_EVCTRL_INVEI0_Pos = 0x4
	// Bit mask of INVEI0 field.
	DAC_EVCTRL_INVEI0_Msk = 0x10
	// Bit INVEI0.
	DAC_EVCTRL_INVEI0 = 0x10
	// Position of INVEI1 field.
	DAC_EVCTRL_INVEI1_Pos = 0x5
	// Bit mask of INVEI1 field.
	DAC_EVCTRL_INVEI1_Msk = 0x20
	// Bit INVEI1.
	DAC_EVCTRL_INVEI1 = 0x20
	// Position of RESRDYEO0 field.
	DAC_EVCTRL_RESRDYEO0_Pos = 0x6
	// Bit mask of RESRDYEO0 field.
	DAC_EVCTRL_RESRDYEO0_Msk = 0x40
	// Bit RESRDYEO0.
	DAC_EVCTRL_RESRDYEO0 = 0x40
	// Position of RESRDYEO1 field.
	DAC_EVCTRL_RESRDYEO1_Pos = 0x7
	// Bit mask of RESRDYEO1 field.
	DAC_EVCTRL_RESRDYEO1_Msk = 0x80
	// Bit RESRDYEO1.
	DAC_EVCTRL_RESRDYEO1 = 0x80

	// INTENCLR: Interrupt Enable Clear
	// Position of UNDERRUN0 field.
	DAC_INTENCLR_UNDERRUN0_Pos = 0x0
	// Bit mask of UNDERRUN0 field.
	DAC_INTENCLR_UNDERRUN0_Msk = 0x1
	// Bit UNDERRUN0.
	DAC_INTENCLR_UNDERRUN0 = 0x1
	// Position of UNDERRUN1 field.
	DAC_INTENCLR_UNDERRUN1_Pos = 0x1
	// Bit mask of UNDERRUN1 field.
	DAC_INTENCLR_UNDERRUN1_Msk = 0x2
	// Bit UNDERRUN1.
	DAC_INTENCLR_UNDERRUN1 = 0x2
	// Position of EMPTY0 field.
	DAC_INTENCLR_EMPTY0_Pos = 0x2
	// Bit mask of EMPTY0 field.
	DAC_INTENCLR_EMPTY0_Msk = 0x4
	// Bit EMPTY0.
	DAC_INTENCLR_EMPTY0 = 0x4
	// Position of EMPTY1 field.
	DAC_INTENCLR_EMPTY1_Pos = 0x3
	// Bit mask of EMPTY1 field.
	DAC_INTENCLR_EMPTY1_Msk = 0x8
	// Bit EMPTY1.
	DAC_INTENCLR_EMPTY1 = 0x8
	// Position of RESRDY0 field.
	DAC_INTENCLR_RESRDY0_Pos = 0x4
	// Bit mask of RESRDY0 field.
	DAC_INTENCLR_RESRDY0_Msk = 0x10
	// Bit RESRDY0.
	DAC_INTENCLR_RESRDY0 = 0x10
	// Position of RESRDY1 field.
	DAC_INTENCLR_RESRDY1_Pos = 0x5
	// Bit mask of RESRDY1 field.
	DAC_INTENCLR_RESRDY1_Msk = 0x20
	// Bit RESRDY1.
	DAC_INTENCLR_RESRDY1 = 0x20
	// Position of OVERRUN0 field.
	DAC_INTENCLR_OVERRUN0_Pos = 0x6
	// Bit mask of OVERRUN0 field.
	DAC_INTENCLR_OVERRUN0_Msk = 0x40
	// Bit OVERRUN0.
	DAC_INTENCLR_OVERRUN0 = 0x40
	// Position of OVERRUN1 field.
	DAC_INTENCLR_OVERRUN1_Pos = 0x7
	// Bit mask of OVERRUN1 field.
	DAC_INTENCLR_OVERRUN1_Msk = 0x80
	// Bit OVERRUN1.
	DAC_INTENCLR_OVERRUN1 = 0x80

	// INTENSET: Interrupt Enable Set
	// Position of UNDERRUN0 field.
	DAC_INTENSET_UNDERRUN0_Pos = 0x0
	// Bit mask of UNDERRUN0 field.
	DAC_INTENSET_UNDERRUN0_Msk = 0x1
	// Bit UNDERRUN0.
	DAC_INTENSET_UNDERRUN0 = 0x1
	// Position of UNDERRUN1 field.
	DAC_INTENSET_UNDERRUN1_Pos = 0x1
	// Bit mask of UNDERRUN1 field.
	DAC_INTENSET_UNDERRUN1_Msk = 0x2
	// Bit UNDERRUN1.
	DAC_INTENSET_UNDERRUN1 = 0x2
	// Position of EMPTY0 field.
	DAC_INTENSET_EMPTY0_Pos = 0x2
	// Bit mask of EMPTY0 field.
	DAC_INTENSET_EMPTY0_Msk = 0x4
	// Bit EMPTY0.
	DAC_INTENSET_EMPTY0 = 0x4
	// Position of EMPTY1 field.
	DAC_INTENSET_EMPTY1_Pos = 0x3
	// Bit mask of EMPTY1 field.
	DAC_INTENSET_EMPTY1_Msk = 0x8
	// Bit EMPTY1.
	DAC_INTENSET_EMPTY1 = 0x8
	// Position of RESRDY0 field.
	DAC_INTENSET_RESRDY0_Pos = 0x4
	// Bit mask of RESRDY0 field.
	DAC_INTENSET_RESRDY0_Msk = 0x10
	// Bit RESRDY0.
	DAC_INTENSET_RESRDY0 = 0x10
	// Position of RESRDY1 field.
	DAC_INTENSET_RESRDY1_Pos = 0x5
	// Bit mask of RESRDY1 field.
	DAC_INTENSET_RESRDY1_Msk = 0x20
	// Bit RESRDY1.
	DAC_INTENSET_RESRDY1 = 0x20
	// Position of OVERRUN0 field.
	DAC_INTENSET_OVERRUN0_Pos = 0x6
	// Bit mask of OVERRUN0 field.
	DAC_INTENSET_OVERRUN0_Msk = 0x40
	// Bit OVERRUN0.
	DAC_INTENSET_OVERRUN0 = 0x40
	// Position of OVERRUN1 field.
	DAC_INTENSET_OVERRUN1_Pos = 0x7
	// Bit mask of OVERRUN1 field.
	DAC_INTENSET_OVERRUN1_Msk = 0x80
	// Bit OVERRUN1.
	DAC_INTENSET_OVERRUN1 = 0x80

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of UNDERRUN0 field.
	DAC_INTFLAG_UNDERRUN0_Pos = 0x0
	// Bit mask of UNDERRUN0 field.
	DAC_INTFLAG_UNDERRUN0_Msk = 0x1
	// Bit UNDERRUN0.
	DAC_INTFLAG_UNDERRUN0 = 0x1
	// Position of UNDERRUN1 field.
	DAC_INTFLAG_UNDERRUN1_Pos = 0x1
	// Bit mask of UNDERRUN1 field.
	DAC_INTFLAG_UNDERRUN1_Msk = 0x2
	// Bit UNDERRUN1.
	DAC_INTFLAG_UNDERRUN1 = 0x2
	// Position of EMPTY0 field.
	DAC_INTFLAG_EMPTY0_Pos = 0x2
	// Bit mask of EMPTY0 field.
	DAC_INTFLAG_EMPTY0_Msk = 0x4
	// Bit EMPTY0.
	DAC_INTFLAG_EMPTY0 = 0x4
	// Position of EMPTY1 field.
	DAC_INTFLAG_EMPTY1_Pos = 0x3
	// Bit mask of EMPTY1 field.
	DAC_INTFLAG_EMPTY1_Msk = 0x8
	// Bit EMPTY1.
	DAC_INTFLAG_EMPTY1 = 0x8
	// Position of RESRDY0 field.
	DAC_INTFLAG_RESRDY0_Pos = 0x4
	// Bit mask of RESRDY0 field.
	DAC_INTFLAG_RESRDY0_Msk = 0x10
	// Bit RESRDY0.
	DAC_INTFLAG_RESRDY0 = 0x10
	// Position of RESRDY1 field.
	DAC_INTFLAG_RESRDY1_Pos = 0x5
	// Bit mask of RESRDY1 field.
	DAC_INTFLAG_RESRDY1_Msk = 0x20
	// Bit RESRDY1.
	DAC_INTFLAG_RESRDY1 = 0x20
	// Position of OVERRUN0 field.
	DAC_INTFLAG_OVERRUN0_Pos = 0x6
	// Bit mask of OVERRUN0 field.
	DAC_INTFLAG_OVERRUN0_Msk = 0x40
	// Bit OVERRUN0.
	DAC_INTFLAG_OVERRUN0 = 0x40
	// Position of OVERRUN1 field.
	DAC_INTFLAG_OVERRUN1_Pos = 0x7
	// Bit mask of OVERRUN1 field.
	DAC_INTFLAG_OVERRUN1_Msk = 0x80
	// Bit OVERRUN1.
	DAC_INTFLAG_OVERRUN1 = 0x80

	// STATUS: Status
	// Position of READY0 field.
	DAC_STATUS_READY0_Pos = 0x0
	// Bit mask of READY0 field.
	DAC_STATUS_READY0_Msk = 0x1
	// Bit READY0.
	DAC_STATUS_READY0 = 0x1
	// Position of READY1 field.
	DAC_STATUS_READY1_Pos = 0x1
	// Bit mask of READY1 field.
	DAC_STATUS_READY1_Msk = 0x2
	// Bit READY1.
	DAC_STATUS_READY1 = 0x2
	// Position of EOC0 field.
	DAC_STATUS_EOC0_Pos = 0x2
	// Bit mask of EOC0 field.
	DAC_STATUS_EOC0_Msk = 0x4
	// Bit EOC0.
	DAC_STATUS_EOC0 = 0x4
	// Position of EOC1 field.
	DAC_STATUS_EOC1_Pos = 0x3
	// Bit mask of EOC1 field.
	DAC_STATUS_EOC1_Msk = 0x8
	// Bit EOC1.
	DAC_STATUS_EOC1 = 0x8

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	DAC_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	DAC_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	DAC_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	DAC_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	DAC_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	DAC_SYNCBUSY_ENABLE = 0x2
	// Position of DATA0 field.
	DAC_SYNCBUSY_DATA0_Pos = 0x2
	// Bit mask of DATA0 field.
	DAC_SYNCBUSY_DATA0_Msk = 0x4
	// Bit DATA0.
	DAC_SYNCBUSY_DATA0 = 0x4
	// Position of DATA1 field.
	DAC_SYNCBUSY_DATA1_Pos = 0x3
	// Bit mask of DATA1 field.
	DAC_SYNCBUSY_DATA1_Msk = 0x8
	// Bit DATA1.
	DAC_SYNCBUSY_DATA1 = 0x8
	// Position of DATABUF0 field.
	DAC_SYNCBUSY_DATABUF0_Pos = 0x4
	// Bit mask of DATABUF0 field.
	DAC_SYNCBUSY_DATABUF0_Msk = 0x10
	// Bit DATABUF0.
	DAC_SYNCBUSY_DATABUF0 = 0x10
	// Position of DATABUF1 field.
	DAC_SYNCBUSY_DATABUF1_Pos = 0x5
	// Bit mask of DATABUF1 field.
	DAC_SYNCBUSY_DATABUF1_Msk = 0x20
	// Bit DATABUF1.
	DAC_SYNCBUSY_DATABUF1 = 0x20

	// DACCTRL: DAC n Control
	// Position of LEFTADJ field.
	DAC_DACCTRL_LEFTADJ_Pos = 0x0
	// Bit mask of LEFTADJ field.
	DAC_DACCTRL_LEFTADJ_Msk = 0x1
	// Bit LEFTADJ.
	DAC_DACCTRL_LEFTADJ = 0x1
	// Position of ENABLE field.
	DAC_DACCTRL_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	DAC_DACCTRL_ENABLE_Msk = 0x2
	// Bit ENABLE.
	DAC_DACCTRL_ENABLE = 0x2
	// Position of CCTRL field.
	DAC_DACCTRL_CCTRL_Pos = 0x2
	// Bit mask of CCTRL field.
	DAC_DACCTRL_CCTRL_Msk = 0xc
	// 100kSPS
	DAC_DACCTRL_CCTRL_CC100K = 0x0
	// 500kSPS
	DAC_DACCTRL_CCTRL_CC1M = 0x1
	// 1MSPS
	DAC_DACCTRL_CCTRL_CC12M = 0x2
	// Position of FEXT field.
	DAC_DACCTRL_FEXT_Pos = 0x5
	// Bit mask of FEXT field.
	DAC_DACCTRL_FEXT_Msk = 0x20
	// Bit FEXT.
	DAC_DACCTRL_FEXT = 0x20
	// Position of RUNSTDBY field.
	DAC_DACCTRL_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	DAC_DACCTRL_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	DAC_DACCTRL_RUNSTDBY = 0x40
	// Position of DITHER field.
	DAC_DACCTRL_DITHER_Pos = 0x7
	// Bit mask of DITHER field.
	DAC_DACCTRL_DITHER_Msk = 0x80
	// Bit DITHER.
	DAC_DACCTRL_DITHER = 0x80
	// Position of REFRESH field.
	DAC_DACCTRL_REFRESH_Pos = 0x8
	// Bit mask of REFRESH field.
	DAC_DACCTRL_REFRESH_Msk = 0xf00
	// Do not Refresh
	DAC_DACCTRL_REFRESH_REFRESH_0 = 0x0
	// Refresh every 30 us
	DAC_DACCTRL_REFRESH_REFRESH_1 = 0x1
	// Refresh every 60 us
	DAC_DACCTRL_REFRESH_REFRESH_2 = 0x2
	// Refresh every 90 us
	DAC_DACCTRL_REFRESH_REFRESH_3 = 0x3
	// Refresh every 120 us
	DAC_DACCTRL_REFRESH_REFRESH_4 = 0x4
	// Refresh every 150 us
	DAC_DACCTRL_REFRESH_REFRESH_5 = 0x5
	// Refresh every 180 us
	DAC_DACCTRL_REFRESH_REFRESH_6 = 0x6
	// Refresh every 210 us
	DAC_DACCTRL_REFRESH_REFRESH_7 = 0x7
	// Refresh every 240 us
	DAC_DACCTRL_REFRESH_REFRESH_8 = 0x8
	// Refresh every 270 us
	DAC_DACCTRL_REFRESH_REFRESH_9 = 0x9
	// Refresh every 300 us
	DAC_DACCTRL_REFRESH_REFRESH_10 = 0xa
	// Refresh every 330 us
	DAC_DACCTRL_REFRESH_REFRESH_11 = 0xb
	// Refresh every 360 us
	DAC_DACCTRL_REFRESH_REFRESH_12 = 0xc
	// Refresh every 390 us
	DAC_DACCTRL_REFRESH_REFRESH_13 = 0xd
	// Refresh every 420 us
	DAC_DACCTRL_REFRESH_REFRESH_14 = 0xe
	// Refresh every 450 us
	DAC_DACCTRL_REFRESH_REFRESH_15 = 0xf
	// Position of OSR field.
	DAC_DACCTRL_OSR_Pos = 0xd
	// Bit mask of OSR field.
	DAC_DACCTRL_OSR_Msk = 0xe000
	// No Over Sampling
	DAC_DACCTRL_OSR_OSR_1 = 0x0
	// 2x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_2 = 0x1
	// 4x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_4 = 0x2
	// 8x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_8 = 0x3
	// 16x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_16 = 0x4
	// 32x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_32 = 0x5

	// DATA: DAC n Data
	// Position of DATA field.
	DAC_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	DAC_DATA_DATA_Msk = 0xffff

	// DATABUF: DAC n Data Buffer
	// Position of DATABUF field.
	DAC_DATABUF_DATABUF_Pos = 0x0
	// Bit mask of DATABUF field.
	DAC_DATABUF_DATABUF_Msk = 0xffff

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	DAC_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	DAC_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	DAC_DBGCTRL_DBGRUN = 0x1

	// RESULT: Filter Result
	// Position of RESULT field.
	DAC_RESULT_RESULT_Pos = 0x0
	// Bit mask of RESULT field.
	DAC_RESULT_RESULT_Msk = 0xffff
)

// Bitfields for DMAC: Direct Memory Access Controller
const (
	// CTRL: Control
	// Position of SWRST field.
	DMAC_CTRL_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	DMAC_CTRL_SWRST_Msk = 0x1
	// Bit SWRST.
	DMAC_CTRL_SWRST = 0x1
	// Position of DMAENABLE field.
	DMAC_CTRL_DMAENABLE_Pos = 0x1
	// Bit mask of DMAENABLE field.
	DMAC_CTRL_DMAENABLE_Msk = 0x2
	// Bit DMAENABLE.
	DMAC_CTRL_DMAENABLE = 0x2
	// Position of LVLEN0 field.
	DMAC_CTRL_LVLEN0_Pos = 0x8
	// Bit mask of LVLEN0 field.
	DMAC_CTRL_LVLEN0_Msk = 0x100
	// Bit LVLEN0.
	DMAC_CTRL_LVLEN0 = 0x100
	// Position of LVLEN1 field.
	DMAC_CTRL_LVLEN1_Pos = 0x9
	// Bit mask of LVLEN1 field.
	DMAC_CTRL_LVLEN1_Msk = 0x200
	// Bit LVLEN1.
	DMAC_CTRL_LVLEN1 = 0x200
	// Position of LVLEN2 field.
	DMAC_CTRL_LVLEN2_Pos = 0xa
	// Bit mask of LVLEN2 field.
	DMAC_CTRL_LVLEN2_Msk = 0x400
	// Bit LVLEN2.
	DMAC_CTRL_LVLEN2 = 0x400
	// Position of LVLEN3 field.
	DMAC_CTRL_LVLEN3_Pos = 0xb
	// Bit mask of LVLEN3 field.
	DMAC_CTRL_LVLEN3_Msk = 0x800
	// Bit LVLEN3.
	DMAC_CTRL_LVLEN3 = 0x800

	// CRCCTRL: CRC Control
	// Position of CRCBEATSIZE field.
	DMAC_CRCCTRL_CRCBEATSIZE_Pos = 0x0
	// Bit mask of CRCBEATSIZE field.
	DMAC_CRCCTRL_CRCBEATSIZE_Msk = 0x3
	// 8-bit bus transfer
	DMAC_CRCCTRL_CRCBEATSIZE_BYTE = 0x0
	// 16-bit bus transfer
	DMAC_CRCCTRL_CRCBEATSIZE_HWORD = 0x1
	// 32-bit bus transfer
	DMAC_CRCCTRL_CRCBEATSIZE_WORD = 0x2
	// Position of CRCPOLY field.
	DMAC_CRCCTRL_CRCPOLY_Pos = 0x2
	// Bit mask of CRCPOLY field.
	DMAC_CRCCTRL_CRCPOLY_Msk = 0xc
	// CRC-16 (CRC-CCITT)
	DMAC_CRCCTRL_CRCPOLY_CRC16 = 0x0
	// CRC32 (IEEE 802.3)
	DMAC_CRCCTRL_CRCPOLY_CRC32 = 0x1
	// Position of CRCSRC field.
	DMAC_CRCCTRL_CRCSRC_Pos = 0x8
	// Bit mask of CRCSRC field.
	DMAC_CRCCTRL_CRCSRC_Msk = 0x3f00
	// CRC Disabled
	DMAC_CRCCTRL_CRCSRC_DISABLE = 0x0
	// I/O interface
	DMAC_CRCCTRL_CRCSRC_IO = 0x1
	// Position of CRCMODE field.
	DMAC_CRCCTRL_CRCMODE_Pos = 0xe
	// Bit mask of CRCMODE field.
	DMAC_CRCCTRL_CRCMODE_Msk = 0xc000
	// Default operating mode
	DMAC_CRCCTRL_CRCMODE_DEFAULT = 0x0
	// Memory CRC monitor operating mode
	DMAC_CRCCTRL_CRCMODE_CRCMON = 0x2
	// Memory CRC generation operating mode
	DMAC_CRCCTRL_CRCMODE_CRCGEN = 0x3

	// CRCDATAIN: CRC Data Input
	// Position of CRCDATAIN field.
	DMAC_CRCDATAIN_CRCDATAIN_Pos = 0x0
	// Bit mask of CRCDATAIN field.
	DMAC_CRCDATAIN_CRCDATAIN_Msk = 0xffffffff

	// CRCCHKSUM: CRC Checksum
	// Position of CRCCHKSUM field.
	DMAC_CRCCHKSUM_CRCCHKSUM_Pos = 0x0
	// Bit mask of CRCCHKSUM field.
	DMAC_CRCCHKSUM_CRCCHKSUM_Msk = 0xffffffff

	// CRCSTATUS: CRC Status
	// Position of CRCBUSY field.
	DMAC_CRCSTATUS_CRCBUSY_Pos = 0x0
	// Bit mask of CRCBUSY field.
	DMAC_CRCSTATUS_CRCBUSY_Msk = 0x1
	// Bit CRCBUSY.
	DMAC_CRCSTATUS_CRCBUSY = 0x1
	// Position of CRCZERO field.
	DMAC_CRCSTATUS_CRCZERO_Pos = 0x1
	// Bit mask of CRCZERO field.
	DMAC_CRCSTATUS_CRCZERO_Msk = 0x2
	// Bit CRCZERO.
	DMAC_CRCSTATUS_CRCZERO = 0x2
	// Position of CRCERR field.
	DMAC_CRCSTATUS_CRCERR_Pos = 0x2
	// Bit mask of CRCERR field.
	DMAC_CRCSTATUS_CRCERR_Msk = 0x4
	// Bit CRCERR.
	DMAC_CRCSTATUS_CRCERR = 0x4

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	DMAC_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	DMAC_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	DMAC_DBGCTRL_DBGRUN = 0x1

	// SWTRIGCTRL: Software Trigger Control
	// Position of SWTRIG0 field.
	DMAC_SWTRIGCTRL_SWTRIG0_Pos = 0x0
	// Bit mask of SWTRIG0 field.
	DMAC_SWTRIGCTRL_SWTRIG0_Msk = 0x1
	// Bit SWTRIG0.
	DMAC_SWTRIGCTRL_SWTRIG0 = 0x1
	// Position of SWTRIG1 field.
	DMAC_SWTRIGCTRL_SWTRIG1_Pos = 0x1
	// Bit mask of SWTRIG1 field.
	DMAC_SWTRIGCTRL_SWTRIG1_Msk = 0x2
	// Bit SWTRIG1.
	DMAC_SWTRIGCTRL_SWTRIG1 = 0x2
	// Position of SWTRIG2 field.
	DMAC_SWTRIGCTRL_SWTRIG2_Pos = 0x2
	// Bit mask of SWTRIG2 field.
	DMAC_SWTRIGCTRL_SWTRIG2_Msk = 0x4
	// Bit SWTRIG2.
	DMAC_SWTRIGCTRL_SWTRIG2 = 0x4
	// Position of SWTRIG3 field.
	DMAC_SWTRIGCTRL_SWTRIG3_Pos = 0x3
	// Bit mask of SWTRIG3 field.
	DMAC_SWTRIGCTRL_SWTRIG3_Msk = 0x8
	// Bit SWTRIG3.
	DMAC_SWTRIGCTRL_SWTRIG3 = 0x8
	// Position of SWTRIG4 field.
	DMAC_SWTRIGCTRL_SWTRIG4_Pos = 0x4
	// Bit mask of SWTRIG4 field.
	DMAC_SWTRIGCTRL_SWTRIG4_Msk = 0x10
	// Bit SWTRIG4.
	DMAC_SWTRIGCTRL_SWTRIG4 = 0x10
	// Position of SWTRIG5 field.
	DMAC_SWTRIGCTRL_SWTRIG5_Pos = 0x5
	// Bit mask of SWTRIG5 field.
	DMAC_SWTRIGCTRL_SWTRIG5_Msk = 0x20
	// Bit SWTRIG5.
	DMAC_SWTRIGCTRL_SWTRIG5 = 0x20
	// Position of SWTRIG6 field.
	DMAC_SWTRIGCTRL_SWTRIG6_Pos = 0x6
	// Bit mask of SWTRIG6 field.
	DMAC_SWTRIGCTRL_SWTRIG6_Msk = 0x40
	// Bit SWTRIG6.
	DMAC_SWTRIGCTRL_SWTRIG6 = 0x40
	// Position of SWTRIG7 field.
	DMAC_SWTRIGCTRL_SWTRIG7_Pos = 0x7
	// Bit mask of SWTRIG7 field.
	DMAC_SWTRIGCTRL_SWTRIG7_Msk = 0x80
	// Bit SWTRIG7.
	DMAC_SWTRIGCTRL_SWTRIG7 = 0x80
	// Position of SWTRIG8 field.
	DMAC_SWTRIGCTRL_SWTRIG8_Pos = 0x8
	// Bit mask of SWTRIG8 field.
	DMAC_SWTRIGCTRL_SWTRIG8_Msk = 0x100
	// Bit SWTRIG8.
	DMAC_SWTRIGCTRL_SWTRIG8 = 0x100
	// Position of SWTRIG9 field.
	DMAC_SWTRIGCTRL_SWTRIG9_Pos = 0x9
	// Bit mask of SWTRIG9 field.
	DMAC_SWTRIGCTRL_SWTRIG9_Msk = 0x200
	// Bit SWTRIG9.
	DMAC_SWTRIGCTRL_SWTRIG9 = 0x200
	// Position of SWTRIG10 field.
	DMAC_SWTRIGCTRL_SWTRIG10_Pos = 0xa
	// Bit mask of SWTRIG10 field.
	DMAC_SWTRIGCTRL_SWTRIG10_Msk = 0x400
	// Bit SWTRIG10.
	DMAC_SWTRIGCTRL_SWTRIG10 = 0x400
	// Position of SWTRIG11 field.
	DMAC_SWTRIGCTRL_SWTRIG11_Pos = 0xb
	// Bit mask of SWTRIG11 field.
	DMAC_SWTRIGCTRL_SWTRIG11_Msk = 0x800
	// Bit SWTRIG11.
	DMAC_SWTRIGCTRL_SWTRIG11 = 0x800
	// Position of SWTRIG12 field.
	DMAC_SWTRIGCTRL_SWTRIG12_Pos = 0xc
	// Bit mask of SWTRIG12 field.
	DMAC_SWTRIGCTRL_SWTRIG12_Msk = 0x1000
	// Bit SWTRIG12.
	DMAC_SWTRIGCTRL_SWTRIG12 = 0x1000
	// Position of SWTRIG13 field.
	DMAC_SWTRIGCTRL_SWTRIG13_Pos = 0xd
	// Bit mask of SWTRIG13 field.
	DMAC_SWTRIGCTRL_SWTRIG13_Msk = 0x2000
	// Bit SWTRIG13.
	DMAC_SWTRIGCTRL_SWTRIG13 = 0x2000
	// Position of SWTRIG14 field.
	DMAC_SWTRIGCTRL_SWTRIG14_Pos = 0xe
	// Bit mask of SWTRIG14 field.
	DMAC_SWTRIGCTRL_SWTRIG14_Msk = 0x4000
	// Bit SWTRIG14.
	DMAC_SWTRIGCTRL_SWTRIG14 = 0x4000
	// Position of SWTRIG15 field.
	DMAC_SWTRIGCTRL_SWTRIG15_Pos = 0xf
	// Bit mask of SWTRIG15 field.
	DMAC_SWTRIGCTRL_SWTRIG15_Msk = 0x8000
	// Bit SWTRIG15.
	DMAC_SWTRIGCTRL_SWTRIG15 = 0x8000
	// Position of SWTRIG16 field.
	DMAC_SWTRIGCTRL_SWTRIG16_Pos = 0x10
	// Bit mask of SWTRIG16 field.
	DMAC_SWTRIGCTRL_SWTRIG16_Msk = 0x10000
	// Bit SWTRIG16.
	DMAC_SWTRIGCTRL_SWTRIG16 = 0x10000
	// Position of SWTRIG17 field.
	DMAC_SWTRIGCTRL_SWTRIG17_Pos = 0x11
	// Bit mask of SWTRIG17 field.
	DMAC_SWTRIGCTRL_SWTRIG17_Msk = 0x20000
	// Bit SWTRIG17.
	DMAC_SWTRIGCTRL_SWTRIG17 = 0x20000
	// Position of SWTRIG18 field.
	DMAC_SWTRIGCTRL_SWTRIG18_Pos = 0x12
	// Bit mask of SWTRIG18 field.
	DMAC_SWTRIGCTRL_SWTRIG18_Msk = 0x40000
	// Bit SWTRIG18.
	DMAC_SWTRIGCTRL_SWTRIG18 = 0x40000
	// Position of SWTRIG19 field.
	DMAC_SWTRIGCTRL_SWTRIG19_Pos = 0x13
	// Bit mask of SWTRIG19 field.
	DMAC_SWTRIGCTRL_SWTRIG19_Msk = 0x80000
	// Bit SWTRIG19.
	DMAC_SWTRIGCTRL_SWTRIG19 = 0x80000
	// Position of SWTRIG20 field.
	DMAC_SWTRIGCTRL_SWTRIG20_Pos = 0x14
	// Bit mask of SWTRIG20 field.
	DMAC_SWTRIGCTRL_SWTRIG20_Msk = 0x100000
	// Bit SWTRIG20.
	DMAC_SWTRIGCTRL_SWTRIG20 = 0x100000
	// Position of SWTRIG21 field.
	DMAC_SWTRIGCTRL_SWTRIG21_Pos = 0x15
	// Bit mask of SWTRIG21 field.
	DMAC_SWTRIGCTRL_SWTRIG21_Msk = 0x200000
	// Bit SWTRIG21.
	DMAC_SWTRIGCTRL_SWTRIG21 = 0x200000
	// Position of SWTRIG22 field.
	DMAC_SWTRIGCTRL_SWTRIG22_Pos = 0x16
	// Bit mask of SWTRIG22 field.
	DMAC_SWTRIGCTRL_SWTRIG22_Msk = 0x400000
	// Bit SWTRIG22.
	DMAC_SWTRIGCTRL_SWTRIG22 = 0x400000
	// Position of SWTRIG23 field.
	DMAC_SWTRIGCTRL_SWTRIG23_Pos = 0x17
	// Bit mask of SWTRIG23 field.
	DMAC_SWTRIGCTRL_SWTRIG23_Msk = 0x800000
	// Bit SWTRIG23.
	DMAC_SWTRIGCTRL_SWTRIG23 = 0x800000
	// Position of SWTRIG24 field.
	DMAC_SWTRIGCTRL_SWTRIG24_Pos = 0x18
	// Bit mask of SWTRIG24 field.
	DMAC_SWTRIGCTRL_SWTRIG24_Msk = 0x1000000
	// Bit SWTRIG24.
	DMAC_SWTRIGCTRL_SWTRIG24 = 0x1000000
	// Position of SWTRIG25 field.
	DMAC_SWTRIGCTRL_SWTRIG25_Pos = 0x19
	// Bit mask of SWTRIG25 field.
	DMAC_SWTRIGCTRL_SWTRIG25_Msk = 0x2000000
	// Bit SWTRIG25.
	DMAC_SWTRIGCTRL_SWTRIG25 = 0x2000000
	// Position of SWTRIG26 field.
	DMAC_SWTRIGCTRL_SWTRIG26_Pos = 0x1a
	// Bit mask of SWTRIG26 field.
	DMAC_SWTRIGCTRL_SWTRIG26_Msk = 0x4000000
	// Bit SWTRIG26.
	DMAC_SWTRIGCTRL_SWTRIG26 = 0x4000000
	// Position of SWTRIG27 field.
	DMAC_SWTRIGCTRL_SWTRIG27_Pos = 0x1b
	// Bit mask of SWTRIG27 field.
	DMAC_SWTRIGCTRL_SWTRIG27_Msk = 0x8000000
	// Bit SWTRIG27.
	DMAC_SWTRIGCTRL_SWTRIG27 = 0x8000000
	// Position of SWTRIG28 field.
	DMAC_SWTRIGCTRL_SWTRIG28_Pos = 0x1c
	// Bit mask of SWTRIG28 field.
	DMAC_SWTRIGCTRL_SWTRIG28_Msk = 0x10000000
	// Bit SWTRIG28.
	DMAC_SWTRIGCTRL_SWTRIG28 = 0x10000000
	// Position of SWTRIG29 field.
	DMAC_SWTRIGCTRL_SWTRIG29_Pos = 0x1d
	// Bit mask of SWTRIG29 field.
	DMAC_SWTRIGCTRL_SWTRIG29_Msk = 0x20000000
	// Bit SWTRIG29.
	DMAC_SWTRIGCTRL_SWTRIG29 = 0x20000000
	// Position of SWTRIG30 field.
	DMAC_SWTRIGCTRL_SWTRIG30_Pos = 0x1e
	// Bit mask of SWTRIG30 field.
	DMAC_SWTRIGCTRL_SWTRIG30_Msk = 0x40000000
	// Bit SWTRIG30.
	DMAC_SWTRIGCTRL_SWTRIG30 = 0x40000000
	// Position of SWTRIG31 field.
	DMAC_SWTRIGCTRL_SWTRIG31_Pos = 0x1f
	// Bit mask of SWTRIG31 field.
	DMAC_SWTRIGCTRL_SWTRIG31_Msk = 0x80000000
	// Bit SWTRIG31.
	DMAC_SWTRIGCTRL_SWTRIG31 = 0x80000000

	// PRICTRL0: Priority Control 0
	// Position of LVLPRI0 field.
	DMAC_PRICTRL0_LVLPRI0_Pos = 0x0
	// Bit mask of LVLPRI0 field.
	DMAC_PRICTRL0_LVLPRI0_Msk = 0x1f
	// Position of QOS0 field.
	DMAC_PRICTRL0_QOS0_Pos = 0x5
	// Bit mask of QOS0 field.
	DMAC_PRICTRL0_QOS0_Msk = 0x60
	// Regular delivery
	DMAC_PRICTRL0_QOS0_REGULAR = 0x0
	// Bandwidth shortage
	DMAC_PRICTRL0_QOS0_SHORTAGE = 0x1
	// Latency sensitive
	DMAC_PRICTRL0_QOS0_SENSITIVE = 0x2
	// Latency critical
	DMAC_PRICTRL0_QOS0_CRITICAL = 0x3
	// Position of RRLVLEN0 field.
	DMAC_PRICTRL0_RRLVLEN0_Pos = 0x7
	// Bit mask of RRLVLEN0 field.
	DMAC_PRICTRL0_RRLVLEN0_Msk = 0x80
	// Bit RRLVLEN0.
	DMAC_PRICTRL0_RRLVLEN0 = 0x80
	// Position of LVLPRI1 field.
	DMAC_PRICTRL0_LVLPRI1_Pos = 0x8
	// Bit mask of LVLPRI1 field.
	DMAC_PRICTRL0_LVLPRI1_Msk = 0x1f00
	// Position of QOS1 field.
	DMAC_PRICTRL0_QOS1_Pos = 0xd
	// Bit mask of QOS1 field.
	DMAC_PRICTRL0_QOS1_Msk = 0x6000
	// Regular delivery
	DMAC_PRICTRL0_QOS1_REGULAR = 0x0
	// Bandwidth shortage
	DMAC_PRICTRL0_QOS1_SHORTAGE = 0x1
	// Latency sensitive
	DMAC_PRICTRL0_QOS1_SENSITIVE = 0x2
	// Latency critical
	DMAC_PRICTRL0_QOS1_CRITICAL = 0x3
	// Position of RRLVLEN1 field.
	DMAC_PRICTRL0_RRLVLEN1_Pos = 0xf
	// Bit mask of RRLVLEN1 field.
	DMAC_PRICTRL0_RRLVLEN1_Msk = 0x8000
	// Bit RRLVLEN1.
	DMAC_PRICTRL0_RRLVLEN1 = 0x8000
	// Position of LVLPRI2 field.
	DMAC_PRICTRL0_LVLPRI2_Pos = 0x10
	// Bit mask of LVLPRI2 field.
	DMAC_PRICTRL0_LVLPRI2_Msk = 0x1f0000
	// Position of QOS2 field.
	DMAC_PRICTRL0_QOS2_Pos = 0x15
	// Bit mask of QOS2 field.
	DMAC_PRICTRL0_QOS2_Msk = 0x600000
	// Regular delivery
	DMAC_PRICTRL0_QOS2_REGULAR = 0x0
	// Bandwidth shortage
	DMAC_PRICTRL0_QOS2_SHORTAGE = 0x1
	// Latency sensitive
	DMAC_PRICTRL0_QOS2_SENSITIVE = 0x2
	// Latency critical
	DMAC_PRICTRL0_QOS2_CRITICAL = 0x3
	// Position of RRLVLEN2 field.
	DMAC_PRICTRL0_RRLVLEN2_Pos = 0x17
	// Bit mask of RRLVLEN2 field.
	DMAC_PRICTRL0_RRLVLEN2_Msk = 0x800000
	// Bit RRLVLEN2.
	DMAC_PRICTRL0_RRLVLEN2 = 0x800000
	// Position of LVLPRI3 field.
	DMAC_PRICTRL0_LVLPRI3_Pos = 0x18
	// Bit mask of LVLPRI3 field.
	DMAC_PRICTRL0_LVLPRI3_Msk = 0x1f000000
	// Position of QOS3 field.
	DMAC_PRICTRL0_QOS3_Pos = 0x1d
	// Bit mask of QOS3 field.
	DMAC_PRICTRL0_QOS3_Msk = 0x60000000
	// Regular delivery
	DMAC_PRICTRL0_QOS3_REGULAR = 0x0
	// Bandwidth shortage
	DMAC_PRICTRL0_QOS3_SHORTAGE = 0x1
	// Latency sensitive
	DMAC_PRICTRL0_QOS3_SENSITIVE = 0x2
	// Latency critical
	DMAC_PRICTRL0_QOS3_CRITICAL = 0x3
	// Position of RRLVLEN3 field.
	DMAC_PRICTRL0_RRLVLEN3_Pos = 0x1f
	// Bit mask of RRLVLEN3 field.
	DMAC_PRICTRL0_RRLVLEN3_Msk = 0x80000000
	// Bit RRLVLEN3.
	DMAC_PRICTRL0_RRLVLEN3 = 0x80000000

	// INTPEND: Interrupt Pending
	// Position of ID field.
	DMAC_INTPEND_ID_Pos = 0x0
	// Bit mask of ID field.
	DMAC_INTPEND_ID_Msk = 0x1f
	// Position of TERR field.
	DMAC_INTPEND_TERR_Pos = 0x8
	// Bit mask of TERR field.
	DMAC_INTPEND_TERR_Msk = 0x100
	// Bit TERR.
	DMAC_INTPEND_TERR = 0x100
	// Position of TCMPL field.
	DMAC_INTPEND_TCMPL_Pos = 0x9
	// Bit mask of TCMPL field.
	DMAC_INTPEND_TCMPL_Msk = 0x200
	// Bit TCMPL.
	DMAC_INTPEND_TCMPL = 0x200
	// Position of SUSP field.
	DMAC_INTPEND_SUSP_Pos = 0xa
	// Bit mask of SUSP field.
	DMAC_INTPEND_SUSP_Msk = 0x400
	// Bit SUSP.
	DMAC_INTPEND_SUSP = 0x400
	// Position of CRCERR field.
	DMAC_INTPEND_CRCERR_Pos = 0xc
	// Bit mask of CRCERR field.
	DMAC_INTPEND_CRCERR_Msk = 0x1000
	// Bit CRCERR.
	DMAC_INTPEND_CRCERR = 0x1000
	// Position of FERR field.
	DMAC_INTPEND_FERR_Pos = 0xd
	// Bit mask of FERR field.
	DMAC_INTPEND_FERR_Msk = 0x2000
	// Bit FERR.
	DMAC_INTPEND_FERR = 0x2000
	// Position of BUSY field.
	DMAC_INTPEND_BUSY_Pos = 0xe
	// Bit mask of BUSY field.
	DMAC_INTPEND_BUSY_Msk = 0x4000
	// Bit BUSY.
	DMAC_INTPEND_BUSY = 0x4000
	// Position of PEND field.
	DMAC_INTPEND_PEND_Pos = 0xf
	// Bit mask of PEND field.
	DMAC_INTPEND_PEND_Msk = 0x8000
	// Bit PEND.
	DMAC_INTPEND_PEND = 0x8000

	// INTSTATUS: Interrupt Status
	// Position of CHINT0 field.
	DMAC_INTSTATUS_CHINT0_Pos = 0x0
	// Bit mask of CHINT0 field.
	DMAC_INTSTATUS_CHINT0_Msk = 0x1
	// Bit CHINT0.
	DMAC_INTSTATUS_CHINT0 = 0x1
	// Position of CHINT1 field.
	DMAC_INTSTATUS_CHINT1_Pos = 0x1
	// Bit mask of CHINT1 field.
	DMAC_INTSTATUS_CHINT1_Msk = 0x2
	// Bit CHINT1.
	DMAC_INTSTATUS_CHINT1 = 0x2
	// Position of CHINT2 field.
	DMAC_INTSTATUS_CHINT2_Pos = 0x2
	// Bit mask of CHINT2 field.
	DMAC_INTSTATUS_CHINT2_Msk = 0x4
	// Bit CHINT2.
	DMAC_INTSTATUS_CHINT2 = 0x4
	// Position of CHINT3 field.
	DMAC_INTSTATUS_CHINT3_Pos = 0x3
	// Bit mask of CHINT3 field.
	DMAC_INTSTATUS_CHINT3_Msk = 0x8
	// Bit CHINT3.
	DMAC_INTSTATUS_CHINT3 = 0x8
	// Position of CHINT4 field.
	DMAC_INTSTATUS_CHINT4_Pos = 0x4
	// Bit mask of CHINT4 field.
	DMAC_INTSTATUS_CHINT4_Msk = 0x10
	// Bit CHINT4.
	DMAC_INTSTATUS_CHINT4 = 0x10
	// Position of CHINT5 field.
	DMAC_INTSTATUS_CHINT5_Pos = 0x5
	// Bit mask of CHINT5 field.
	DMAC_INTSTATUS_CHINT5_Msk = 0x20
	// Bit CHINT5.
	DMAC_INTSTATUS_CHINT5 = 0x20
	// Position of CHINT6 field.
	DMAC_INTSTATUS_CHINT6_Pos = 0x6
	// Bit mask of CHINT6 field.
	DMAC_INTSTATUS_CHINT6_Msk = 0x40
	// Bit CHINT6.
	DMAC_INTSTATUS_CHINT6 = 0x40
	// Position of CHINT7 field.
	DMAC_INTSTATUS_CHINT7_Pos = 0x7
	// Bit mask of CHINT7 field.
	DMAC_INTSTATUS_CHINT7_Msk = 0x80
	// Bit CHINT7.
	DMAC_INTSTATUS_CHINT7 = 0x80
	// Position of CHINT8 field.
	DMAC_INTSTATUS_CHINT8_Pos = 0x8
	// Bit mask of CHINT8 field.
	DMAC_INTSTATUS_CHINT8_Msk = 0x100
	// Bit CHINT8.
	DMAC_INTSTATUS_CHINT8 = 0x100
	// Position of CHINT9 field.
	DMAC_INTSTATUS_CHINT9_Pos = 0x9
	// Bit mask of CHINT9 field.
	DMAC_INTSTATUS_CHINT9_Msk = 0x200
	// Bit CHINT9.
	DMAC_INTSTATUS_CHINT9 = 0x200
	// Position of CHINT10 field.
	DMAC_INTSTATUS_CHINT10_Pos = 0xa
	// Bit mask of CHINT10 field.
	DMAC_INTSTATUS_CHINT10_Msk = 0x400
	// Bit CHINT10.
	DMAC_INTSTATUS_CHINT10 = 0x400
	// Position of CHINT11 field.
	DMAC_INTSTATUS_CHINT11_Pos = 0xb
	// Bit mask of CHINT11 field.
	DMAC_INTSTATUS_CHINT11_Msk = 0x800
	// Bit CHINT11.
	DMAC_INTSTATUS_CHINT11 = 0x800
	// Position of CHINT12 field.
	DMAC_INTSTATUS_CHINT12_Pos = 0xc
	// Bit mask of CHINT12 field.
	DMAC_INTSTATUS_CHINT12_Msk = 0x1000
	// Bit CHINT12.
	DMAC_INTSTATUS_CHINT12 = 0x1000
	// Position of CHINT13 field.
	DMAC_INTSTATUS_CHINT13_Pos = 0xd
	// Bit mask of CHINT13 field.
	DMAC_INTSTATUS_CHINT13_Msk = 0x2000
	// Bit CHINT13.
	DMAC_INTSTATUS_CHINT13 = 0x2000
	// Position of CHINT14 field.
	DMAC_INTSTATUS_CHINT14_Pos = 0xe
	// Bit mask of CHINT14 field.
	DMAC_INTSTATUS_CHINT14_Msk = 0x4000
	// Bit CHINT14.
	DMAC_INTSTATUS_CHINT14 = 0x4000
	// Position of CHINT15 field.
	DMAC_INTSTATUS_CHINT15_Pos = 0xf
	// Bit mask of CHINT15 field.
	DMAC_INTSTATUS_CHINT15_Msk = 0x8000
	// Bit CHINT15.
	DMAC_INTSTATUS_CHINT15 = 0x8000
	// Position of CHINT16 field.
	DMAC_INTSTATUS_CHINT16_Pos = 0x10
	// Bit mask of CHINT16 field.
	DMAC_INTSTATUS_CHINT16_Msk = 0x10000
	// Bit CHINT16.
	DMAC_INTSTATUS_CHINT16 = 0x10000
	// Position of CHINT17 field.
	DMAC_INTSTATUS_CHINT17_Pos = 0x11
	// Bit mask of CHINT17 field.
	DMAC_INTSTATUS_CHINT17_Msk = 0x20000
	// Bit CHINT17.
	DMAC_INTSTATUS_CHINT17 = 0x20000
	// Position of CHINT18 field.
	DMAC_INTSTATUS_CHINT18_Pos = 0x12
	// Bit mask of CHINT18 field.
	DMAC_INTSTATUS_CHINT18_Msk = 0x40000
	// Bit CHINT18.
	DMAC_INTSTATUS_CHINT18 = 0x40000
	// Position of CHINT19 field.
	DMAC_INTSTATUS_CHINT19_Pos = 0x13
	// Bit mask of CHINT19 field.
	DMAC_INTSTATUS_CHINT19_Msk = 0x80000
	// Bit CHINT19.
	DMAC_INTSTATUS_CHINT19 = 0x80000
	// Position of CHINT20 field.
	DMAC_INTSTATUS_CHINT20_Pos = 0x14
	// Bit mask of CHINT20 field.
	DMAC_INTSTATUS_CHINT20_Msk = 0x100000
	// Bit CHINT20.
	DMAC_INTSTATUS_CHINT20 = 0x100000
	// Position of CHINT21 field.
	DMAC_INTSTATUS_CHINT21_Pos = 0x15
	// Bit mask of CHINT21 field.
	DMAC_INTSTATUS_CHINT21_Msk = 0x200000
	// Bit CHINT21.
	DMAC_INTSTATUS_CHINT21 = 0x200000
	// Position of CHINT22 field.
	DMAC_INTSTATUS_CHINT22_Pos = 0x16
	// Bit mask of CHINT22 field.
	DMAC_INTSTATUS_CHINT22_Msk = 0x400000
	// Bit CHINT22.
	DMAC_INTSTATUS_CHINT22 = 0x400000
	// Position of CHINT23 field.
	DMAC_INTSTATUS_CHINT23_Pos = 0x17
	// Bit mask of CHINT23 field.
	DMAC_INTSTATUS_CHINT23_Msk = 0x800000
	// Bit CHINT23.
	DMAC_INTSTATUS_CHINT23 = 0x800000
	// Position of CHINT24 field.
	DMAC_INTSTATUS_CHINT24_Pos = 0x18
	// Bit mask of CHINT24 field.
	DMAC_INTSTATUS_CHINT24_Msk = 0x1000000
	// Bit CHINT24.
	DMAC_INTSTATUS_CHINT24 = 0x1000000
	// Position of CHINT25 field.
	DMAC_INTSTATUS_CHINT25_Pos = 0x19
	// Bit mask of CHINT25 field.
	DMAC_INTSTATUS_CHINT25_Msk = 0x2000000
	// Bit CHINT25.
	DMAC_INTSTATUS_CHINT25 = 0x2000000
	// Position of CHINT26 field.
	DMAC_INTSTATUS_CHINT26_Pos = 0x1a
	// Bit mask of CHINT26 field.
	DMAC_INTSTATUS_CHINT26_Msk = 0x4000000
	// Bit CHINT26.
	DMAC_INTSTATUS_CHINT26 = 0x4000000
	// Position of CHINT27 field.
	DMAC_INTSTATUS_CHINT27_Pos = 0x1b
	// Bit mask of CHINT27 field.
	DMAC_INTSTATUS_CHINT27_Msk = 0x8000000
	// Bit CHINT27.
	DMAC_INTSTATUS_CHINT27 = 0x8000000
	// Position of CHINT28 field.
	DMAC_INTSTATUS_CHINT28_Pos = 0x1c
	// Bit mask of CHINT28 field.
	DMAC_INTSTATUS_CHINT28_Msk = 0x10000000
	// Bit CHINT28.
	DMAC_INTSTATUS_CHINT28 = 0x10000000
	// Position of CHINT29 field.
	DMAC_INTSTATUS_CHINT29_Pos = 0x1d
	// Bit mask of CHINT29 field.
	DMAC_INTSTATUS_CHINT29_Msk = 0x20000000
	// Bit CHINT29.
	DMAC_INTSTATUS_CHINT29 = 0x20000000
	// Position of CHINT30 field.
	DMAC_INTSTATUS_CHINT30_Pos = 0x1e
	// Bit mask of CHINT30 field.
	DMAC_INTSTATUS_CHINT30_Msk = 0x40000000
	// Bit CHINT30.
	DMAC_INTSTATUS_CHINT30 = 0x40000000
	// Position of CHINT31 field.
	DMAC_INTSTATUS_CHINT31_Pos = 0x1f
	// Bit mask of CHINT31 field.
	DMAC_INTSTATUS_CHINT31_Msk = 0x80000000
	// Bit CHINT31.
	DMAC_INTSTATUS_CHINT31 = 0x80000000

	// BUSYCH: Busy Channels
	// Position of BUSYCH0 field.
	DMAC_BUSYCH_BUSYCH0_Pos = 0x0
	// Bit mask of BUSYCH0 field.
	DMAC_BUSYCH_BUSYCH0_Msk = 0x1
	// Bit BUSYCH0.
	DMAC_BUSYCH_BUSYCH0 = 0x1
	// Position of BUSYCH1 field.
	DMAC_BUSYCH_BUSYCH1_Pos = 0x1
	// Bit mask of BUSYCH1 field.
	DMAC_BUSYCH_BUSYCH1_Msk = 0x2
	// Bit BUSYCH1.
	DMAC_BUSYCH_BUSYCH1 = 0x2
	// Position of BUSYCH2 field.
	DMAC_BUSYCH_BUSYCH2_Pos = 0x2
	// Bit mask of BUSYCH2 field.
	DMAC_BUSYCH_BUSYCH2_Msk = 0x4
	// Bit BUSYCH2.
	DMAC_BUSYCH_BUSYCH2 = 0x4
	// Position of BUSYCH3 field.
	DMAC_BUSYCH_BUSYCH3_Pos = 0x3
	// Bit mask of BUSYCH3 field.
	DMAC_BUSYCH_BUSYCH3_Msk = 0x8
	// Bit BUSYCH3.
	DMAC_BUSYCH_BUSYCH3 = 0x8
	// Position of BUSYCH4 field.
	DMAC_BUSYCH_BUSYCH4_Pos = 0x4
	// Bit mask of BUSYCH4 field.
	DMAC_BUSYCH_BUSYCH4_Msk = 0x10
	// Bit BUSYCH4.
	DMAC_BUSYCH_BUSYCH4 = 0x10
	// Position of BUSYCH5 field.
	DMAC_BUSYCH_BUSYCH5_Pos = 0x5
	// Bit mask of BUSYCH5 field.
	DMAC_BUSYCH_BUSYCH5_Msk = 0x20
	// Bit BUSYCH5.
	DMAC_BUSYCH_BUSYCH5 = 0x20
	// Position of BUSYCH6 field.
	DMAC_BUSYCH_BUSYCH6_Pos = 0x6
	// Bit mask of BUSYCH6 field.
	DMAC_BUSYCH_BUSYCH6_Msk = 0x40
	// Bit BUSYCH6.
	DMAC_BUSYCH_BUSYCH6 = 0x40
	// Position of BUSYCH7 field.
	DMAC_BUSYCH_BUSYCH7_Pos = 0x7
	// Bit mask of BUSYCH7 field.
	DMAC_BUSYCH_BUSYCH7_Msk = 0x80
	// Bit BUSYCH7.
	DMAC_BUSYCH_BUSYCH7 = 0x80
	// Position of BUSYCH8 field.
	DMAC_BUSYCH_BUSYCH8_Pos = 0x8
	// Bit mask of BUSYCH8 field.
	DMAC_BUSYCH_BUSYCH8_Msk = 0x100
	// Bit BUSYCH8.
	DMAC_BUSYCH_BUSYCH8 = 0x100
	// Position of BUSYCH9 field.
	DMAC_BUSYCH_BUSYCH9_Pos = 0x9
	// Bit mask of BUSYCH9 field.
	DMAC_BUSYCH_BUSYCH9_Msk = 0x200
	// Bit BUSYCH9.
	DMAC_BUSYCH_BUSYCH9 = 0x200
	// Position of BUSYCH10 field.
	DMAC_BUSYCH_BUSYCH10_Pos = 0xa
	// Bit mask of BUSYCH10 field.
	DMAC_BUSYCH_BUSYCH10_Msk = 0x400
	// Bit BUSYCH10.
	DMAC_BUSYCH_BUSYCH10 = 0x400
	// Position of BUSYCH11 field.
	DMAC_BUSYCH_BUSYCH11_Pos = 0xb
	// Bit mask of BUSYCH11 field.
	DMAC_BUSYCH_BUSYCH11_Msk = 0x800
	// Bit BUSYCH11.
	DMAC_BUSYCH_BUSYCH11 = 0x800
	// Position of BUSYCH12 field.
	DMAC_BUSYCH_BUSYCH12_Pos = 0xc
	// Bit mask of BUSYCH12 field.
	DMAC_BUSYCH_BUSYCH12_Msk = 0x1000
	// Bit BUSYCH12.
	DMAC_BUSYCH_BUSYCH12 = 0x1000
	// Position of BUSYCH13 field.
	DMAC_BUSYCH_BUSYCH13_Pos = 0xd
	// Bit mask of BUSYCH13 field.
	DMAC_BUSYCH_BUSYCH13_Msk = 0x2000
	// Bit BUSYCH13.
	DMAC_BUSYCH_BUSYCH13 = 0x2000
	// Position of BUSYCH14 field.
	DMAC_BUSYCH_BUSYCH14_Pos = 0xe
	// Bit mask of BUSYCH14 field.
	DMAC_BUSYCH_BUSYCH14_Msk = 0x4000
	// Bit BUSYCH14.
	DMAC_BUSYCH_BUSYCH14 = 0x4000
	// Position of BUSYCH15 field.
	DMAC_BUSYCH_BUSYCH15_Pos = 0xf
	// Bit mask of BUSYCH15 field.
	DMAC_BUSYCH_BUSYCH15_Msk = 0x8000
	// Bit BUSYCH15.
	DMAC_BUSYCH_BUSYCH15 = 0x8000
	// Position of BUSYCH16 field.
	DMAC_BUSYCH_BUSYCH16_Pos = 0x10
	// Bit mask of BUSYCH16 field.
	DMAC_BUSYCH_BUSYCH16_Msk = 0x10000
	// Bit BUSYCH16.
	DMAC_BUSYCH_BUSYCH16 = 0x10000
	// Position of BUSYCH17 field.
	DMAC_BUSYCH_BUSYCH17_Pos = 0x11
	// Bit mask of BUSYCH17 field.
	DMAC_BUSYCH_BUSYCH17_Msk = 0x20000
	// Bit BUSYCH17.
	DMAC_BUSYCH_BUSYCH17 = 0x20000
	// Position of BUSYCH18 field.
	DMAC_BUSYCH_BUSYCH18_Pos = 0x12
	// Bit mask of BUSYCH18 field.
	DMAC_BUSYCH_BUSYCH18_Msk = 0x40000
	// Bit BUSYCH18.
	DMAC_BUSYCH_BUSYCH18 = 0x40000
	// Position of BUSYCH19 field.
	DMAC_BUSYCH_BUSYCH19_Pos = 0x13
	// Bit mask of BUSYCH19 field.
	DMAC_BUSYCH_BUSYCH19_Msk = 0x80000
	// Bit BUSYCH19.
	DMAC_BUSYCH_BUSYCH19 = 0x80000
	// Position of BUSYCH20 field.
	DMAC_BUSYCH_BUSYCH20_Pos = 0x14
	// Bit mask of BUSYCH20 field.
	DMAC_BUSYCH_BUSYCH20_Msk = 0x100000
	// Bit BUSYCH20.
	DMAC_BUSYCH_BUSYCH20 = 0x100000
	// Position of BUSYCH21 field.
	DMAC_BUSYCH_BUSYCH21_Pos = 0x15
	// Bit mask of BUSYCH21 field.
	DMAC_BUSYCH_BUSYCH21_Msk = 0x200000
	// Bit BUSYCH21.
	DMAC_BUSYCH_BUSYCH21 = 0x200000
	// Position of BUSYCH22 field.
	DMAC_BUSYCH_BUSYCH22_Pos = 0x16
	// Bit mask of BUSYCH22 field.
	DMAC_BUSYCH_BUSYCH22_Msk = 0x400000
	// Bit BUSYCH22.
	DMAC_BUSYCH_BUSYCH22 = 0x400000
	// Position of BUSYCH23 field.
	DMAC_BUSYCH_BUSYCH23_Pos = 0x17
	// Bit mask of BUSYCH23 field.
	DMAC_BUSYCH_BUSYCH23_Msk = 0x800000
	// Bit BUSYCH23.
	DMAC_BUSYCH_BUSYCH23 = 0x800000
	// Position of BUSYCH24 field.
	DMAC_BUSYCH_BUSYCH24_Pos = 0x18
	// Bit mask of BUSYCH24 field.
	DMAC_BUSYCH_BUSYCH24_Msk = 0x1000000
	// Bit BUSYCH24.
	DMAC_BUSYCH_BUSYCH24 = 0x1000000
	// Position of BUSYCH25 field.
	DMAC_BUSYCH_BUSYCH25_Pos = 0x19
	// Bit mask of BUSYCH25 field.
	DMAC_BUSYCH_BUSYCH25_Msk = 0x2000000
	// Bit BUSYCH25.
	DMAC_BUSYCH_BUSYCH25 = 0x2000000
	// Position of BUSYCH26 field.
	DMAC_BUSYCH_BUSYCH26_Pos = 0x1a
	// Bit mask of BUSYCH26 field.
	DMAC_BUSYCH_BUSYCH26_Msk = 0x4000000
	// Bit BUSYCH26.
	DMAC_BUSYCH_BUSYCH26 = 0x4000000
	// Position of BUSYCH27 field.
	DMAC_BUSYCH_BUSYCH27_Pos = 0x1b
	// Bit mask of BUSYCH27 field.
	DMAC_BUSYCH_BUSYCH27_Msk = 0x8000000
	// Bit BUSYCH27.
	DMAC_BUSYCH_BUSYCH27 = 0x8000000
	// Position of BUSYCH28 field.
	DMAC_BUSYCH_BUSYCH28_Pos = 0x1c
	// Bit mask of BUSYCH28 field.
	DMAC_BUSYCH_BUSYCH28_Msk = 0x10000000
	// Bit BUSYCH28.
	DMAC_BUSYCH_BUSYCH28 = 0x10000000
	// Position of BUSYCH29 field.
	DMAC_BUSYCH_BUSYCH29_Pos = 0x1d
	// Bit mask of BUSYCH29 field.
	DMAC_BUSYCH_BUSYCH29_Msk = 0x20000000
	// Bit BUSYCH29.
	DMAC_BUSYCH_BUSYCH29 = 0x20000000
	// Position of BUSYCH30 field.
	DMAC_BUSYCH_BUSYCH30_Pos = 0x1e
	// Bit mask of BUSYCH30 field.
	DMAC_BUSYCH_BUSYCH30_Msk = 0x40000000
	// Bit BUSYCH30.
	DMAC_BUSYCH_BUSYCH30 = 0x40000000
	// Position of BUSYCH31 field.
	DMAC_BUSYCH_BUSYCH31_Pos = 0x1f
	// Bit mask of BUSYCH31 field.
	DMAC_BUSYCH_BUSYCH31_Msk = 0x80000000
	// Bit BUSYCH31.
	DMAC_BUSYCH_BUSYCH31 = 0x80000000

	// PENDCH: Pending Channels
	// Position of PENDCH0 field.
	DMAC_PENDCH_PENDCH0_Pos = 0x0
	// Bit mask of PENDCH0 field.
	DMAC_PENDCH_PENDCH0_Msk = 0x1
	// Bit PENDCH0.
	DMAC_PENDCH_PENDCH0 = 0x1
	// Position of PENDCH1 field.
	DMAC_PENDCH_PENDCH1_Pos = 0x1
	// Bit mask of PENDCH1 field.
	DMAC_PENDCH_PENDCH1_Msk = 0x2
	// Bit PENDCH1.
	DMAC_PENDCH_PENDCH1 = 0x2
	// Position of PENDCH2 field.
	DMAC_PENDCH_PENDCH2_Pos = 0x2
	// Bit mask of PENDCH2 field.
	DMAC_PENDCH_PENDCH2_Msk = 0x4
	// Bit PENDCH2.
	DMAC_PENDCH_PENDCH2 = 0x4
	// Position of PENDCH3 field.
	DMAC_PENDCH_PENDCH3_Pos = 0x3
	// Bit mask of PENDCH3 field.
	DMAC_PENDCH_PENDCH3_Msk = 0x8
	// Bit PENDCH3.
	DMAC_PENDCH_PENDCH3 = 0x8
	// Position of PENDCH4 field.
	DMAC_PENDCH_PENDCH4_Pos = 0x4
	// Bit mask of PENDCH4 field.
	DMAC_PENDCH_PENDCH4_Msk = 0x10
	// Bit PENDCH4.
	DMAC_PENDCH_PENDCH4 = 0x10
	// Position of PENDCH5 field.
	DMAC_PENDCH_PENDCH5_Pos = 0x5
	// Bit mask of PENDCH5 field.
	DMAC_PENDCH_PENDCH5_Msk = 0x20
	// Bit PENDCH5.
	DMAC_PENDCH_PENDCH5 = 0x20
	// Position of PENDCH6 field.
	DMAC_PENDCH_PENDCH6_Pos = 0x6
	// Bit mask of PENDCH6 field.
	DMAC_PENDCH_PENDCH6_Msk = 0x40
	// Bit PENDCH6.
	DMAC_PENDCH_PENDCH6 = 0x40
	// Position of PENDCH7 field.
	DMAC_PENDCH_PENDCH7_Pos = 0x7
	// Bit mask of PENDCH7 field.
	DMAC_PENDCH_PENDCH7_Msk = 0x80
	// Bit PENDCH7.
	DMAC_PENDCH_PENDCH7 = 0x80
	// Position of PENDCH8 field.
	DMAC_PENDCH_PENDCH8_Pos = 0x8
	// Bit mask of PENDCH8 field.
	DMAC_PENDCH_PENDCH8_Msk = 0x100
	// Bit PENDCH8.
	DMAC_PENDCH_PENDCH8 = 0x100
	// Position of PENDCH9 field.
	DMAC_PENDCH_PENDCH9_Pos = 0x9
	// Bit mask of PENDCH9 field.
	DMAC_PENDCH_PENDCH9_Msk = 0x200
	// Bit PENDCH9.
	DMAC_PENDCH_PENDCH9 = 0x200
	// Position of PENDCH10 field.
	DMAC_PENDCH_PENDCH10_Pos = 0xa
	// Bit mask of PENDCH10 field.
	DMAC_PENDCH_PENDCH10_Msk = 0x400
	// Bit PENDCH10.
	DMAC_PENDCH_PENDCH10 = 0x400
	// Position of PENDCH11 field.
	DMAC_PENDCH_PENDCH11_Pos = 0xb
	// Bit mask of PENDCH11 field.
	DMAC_PENDCH_PENDCH11_Msk = 0x800
	// Bit PENDCH11.
	DMAC_PENDCH_PENDCH11 = 0x800
	// Position of PENDCH12 field.
	DMAC_PENDCH_PENDCH12_Pos = 0xc
	// Bit mask of PENDCH12 field.
	DMAC_PENDCH_PENDCH12_Msk = 0x1000
	// Bit PENDCH12.
	DMAC_PENDCH_PENDCH12 = 0x1000
	// Position of PENDCH13 field.
	DMAC_PENDCH_PENDCH13_Pos = 0xd
	// Bit mask of PENDCH13 field.
	DMAC_PENDCH_PENDCH13_Msk = 0x2000
	// Bit PENDCH13.
	DMAC_PENDCH_PENDCH13 = 0x2000
	// Position of PENDCH14 field.
	DMAC_PENDCH_PENDCH14_Pos = 0xe
	// Bit mask of PENDCH14 field.
	DMAC_PENDCH_PENDCH14_Msk = 0x4000
	// Bit PENDCH14.
	DMAC_PENDCH_PENDCH14 = 0x4000
	// Position of PENDCH15 field.
	DMAC_PENDCH_PENDCH15_Pos = 0xf
	// Bit mask of PENDCH15 field.
	DMAC_PENDCH_PENDCH15_Msk = 0x8000
	// Bit PENDCH15.
	DMAC_PENDCH_PENDCH15 = 0x8000
	// Position of PENDCH16 field.
	DMAC_PENDCH_PENDCH16_Pos = 0x10
	// Bit mask of PENDCH16 field.
	DMAC_PENDCH_PENDCH16_Msk = 0x10000
	// Bit PENDCH16.
	DMAC_PENDCH_PENDCH16 = 0x10000
	// Position of PENDCH17 field.
	DMAC_PENDCH_PENDCH17_Pos = 0x11
	// Bit mask of PENDCH17 field.
	DMAC_PENDCH_PENDCH17_Msk = 0x20000
	// Bit PENDCH17.
	DMAC_PENDCH_PENDCH17 = 0x20000
	// Position of PENDCH18 field.
	DMAC_PENDCH_PENDCH18_Pos = 0x12
	// Bit mask of PENDCH18 field.
	DMAC_PENDCH_PENDCH18_Msk = 0x40000
	// Bit PENDCH18.
	DMAC_PENDCH_PENDCH18 = 0x40000
	// Position of PENDCH19 field.
	DMAC_PENDCH_PENDCH19_Pos = 0x13
	// Bit mask of PENDCH19 field.
	DMAC_PENDCH_PENDCH19_Msk = 0x80000
	// Bit PENDCH19.
	DMAC_PENDCH_PENDCH19 = 0x80000
	// Position of PENDCH20 field.
	DMAC_PENDCH_PENDCH20_Pos = 0x14
	// Bit mask of PENDCH20 field.
	DMAC_PENDCH_PENDCH20_Msk = 0x100000
	// Bit PENDCH20.
	DMAC_PENDCH_PENDCH20 = 0x100000
	// Position of PENDCH21 field.
	DMAC_PENDCH_PENDCH21_Pos = 0x15
	// Bit mask of PENDCH21 field.
	DMAC_PENDCH_PENDCH21_Msk = 0x200000
	// Bit PENDCH21.
	DMAC_PENDCH_PENDCH21 = 0x200000
	// Position of PENDCH22 field.
	DMAC_PENDCH_PENDCH22_Pos = 0x16
	// Bit mask of PENDCH22 field.
	DMAC_PENDCH_PENDCH22_Msk = 0x400000
	// Bit PENDCH22.
	DMAC_PENDCH_PENDCH22 = 0x400000
	// Position of PENDCH23 field.
	DMAC_PENDCH_PENDCH23_Pos = 0x17
	// Bit mask of PENDCH23 field.
	DMAC_PENDCH_PENDCH23_Msk = 0x800000
	// Bit PENDCH23.
	DMAC_PENDCH_PENDCH23 = 0x800000
	// Position of PENDCH24 field.
	DMAC_PENDCH_PENDCH24_Pos = 0x18
	// Bit mask of PENDCH24 field.
	DMAC_PENDCH_PENDCH24_Msk = 0x1000000
	// Bit PENDCH24.
	DMAC_PENDCH_PENDCH24 = 0x1000000
	// Position of PENDCH25 field.
	DMAC_PENDCH_PENDCH25_Pos = 0x19
	// Bit mask of PENDCH25 field.
	DMAC_PENDCH_PENDCH25_Msk = 0x2000000
	// Bit PENDCH25.
	DMAC_PENDCH_PENDCH25 = 0x2000000
	// Position of PENDCH26 field.
	DMAC_PENDCH_PENDCH26_Pos = 0x1a
	// Bit mask of PENDCH26 field.
	DMAC_PENDCH_PENDCH26_Msk = 0x4000000
	// Bit PENDCH26.
	DMAC_PENDCH_PENDCH26 = 0x4000000
	// Position of PENDCH27 field.
	DMAC_PENDCH_PENDCH27_Pos = 0x1b
	// Bit mask of PENDCH27 field.
	DMAC_PENDCH_PENDCH27_Msk = 0x8000000
	// Bit PENDCH27.
	DMAC_PENDCH_PENDCH27 = 0x8000000
	// Position of PENDCH28 field.
	DMAC_PENDCH_PENDCH28_Pos = 0x1c
	// Bit mask of PENDCH28 field.
	DMAC_PENDCH_PENDCH28_Msk = 0x10000000
	// Bit PENDCH28.
	DMAC_PENDCH_PENDCH28 = 0x10000000
	// Position of PENDCH29 field.
	DMAC_PENDCH_PENDCH29_Pos = 0x1d
	// Bit mask of PENDCH29 field.
	DMAC_PENDCH_PENDCH29_Msk = 0x20000000
	// Bit PENDCH29.
	DMAC_PENDCH_PENDCH29 = 0x20000000
	// Position of PENDCH30 field.
	DMAC_PENDCH_PENDCH30_Pos = 0x1e
	// Bit mask of PENDCH30 field.
	DMAC_PENDCH_PENDCH30_Msk = 0x40000000
	// Bit PENDCH30.
	DMAC_PENDCH_PENDCH30 = 0x40000000
	// Position of PENDCH31 field.
	DMAC_PENDCH_PENDCH31_Pos = 0x1f
	// Bit mask of PENDCH31 field.
	DMAC_PENDCH_PENDCH31_Msk = 0x80000000
	// Bit PENDCH31.
	DMAC_PENDCH_PENDCH31 = 0x80000000

	// ACTIVE: Active Channel and Levels
	// Position of LVLEX0 field.
	DMAC_ACTIVE_LVLEX0_Pos = 0x0
	// Bit mask of LVLEX0 field.
	DMAC_ACTIVE_LVLEX0_Msk = 0x1
	// Bit LVLEX0.
	DMAC_ACTIVE_LVLEX0 = 0x1
	// Position of LVLEX1 field.
	DMAC_ACTIVE_LVLEX1_Pos = 0x1
	// Bit mask of LVLEX1 field.
	DMAC_ACTIVE_LVLEX1_Msk = 0x2
	// Bit LVLEX1.
	DMAC_ACTIVE_LVLEX1 = 0x2
	// Position of LVLEX2 field.
	DMAC_ACTIVE_LVLEX2_Pos = 0x2
	// Bit mask of LVLEX2 field.
	DMAC_ACTIVE_LVLEX2_Msk = 0x4
	// Bit LVLEX2.
	DMAC_ACTIVE_LVLEX2 = 0x4
	// Position of LVLEX3 field.
	DMAC_ACTIVE_LVLEX3_Pos = 0x3
	// Bit mask of LVLEX3 field.
	DMAC_ACTIVE_LVLEX3_Msk = 0x8
	// Bit LVLEX3.
	DMAC_ACTIVE_LVLEX3 = 0x8
	// Position of ID field.
	DMAC_ACTIVE_ID_Pos = 0x8
	// Bit mask of ID field.
	DMAC_ACTIVE_ID_Msk = 0x1f00
	// Position of ABUSY field.
	DMAC_ACTIVE_ABUSY_Pos = 0xf
	// Bit mask of ABUSY field.
	DMAC_ACTIVE_ABUSY_Msk = 0x8000
	// Bit ABUSY.
	DMAC_ACTIVE_ABUSY = 0x8000
	// Position of BTCNT field.
	DMAC_ACTIVE_BTCNT_Pos = 0x10
	// Bit mask of BTCNT field.
	DMAC_ACTIVE_BTCNT_Msk = 0xffff0000

	// BASEADDR: Descriptor Memory Section Base Address
	// Position of BASEADDR field.
	DMAC_BASEADDR_BASEADDR_Pos = 0x0
	// Bit mask of BASEADDR field.
	DMAC_BASEADDR_BASEADDR_Msk = 0xffffffff

	// WRBADDR: Write-Back Memory Section Base Address
	// Position of WRBADDR field.
	DMAC_WRBADDR_WRBADDR_Pos = 0x0
	// Bit mask of WRBADDR field.
	DMAC_WRBADDR_WRBADDR_Msk = 0xffffffff

	// CHANNEL.CHCTRLA: Channel n Control A
	// Position of SWRST field.
	DMAC_CHANNEL_CHCTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	DMAC_CHANNEL_CHCTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	DMAC_CHANNEL_CHCTRLA_SWRST = 0x1
	// Position of ENABLE field.
	DMAC_CHANNEL_CHCTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	DMAC_CHANNEL_CHCTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	DMAC_CHANNEL_CHCTRLA_ENABLE = 0x2
	// Position of RUNSTDBY field.
	DMAC_CHANNEL_CHCTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	DMAC_CHANNEL_CHCTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	DMAC_CHANNEL_CHCTRLA_RUNSTDBY = 0x40
	// Position of TRIGSRC field.
	DMAC_CHANNEL_CHCTRLA_TRIGSRC_Pos = 0x8
	// Bit mask of TRIGSRC field.
	DMAC_CHANNEL_CHCTRLA_TRIGSRC_Msk = 0x7f00
	// Only software/event triggers
	DMAC_CHANNEL_CHCTRLA_TRIGSRC_DISABLE = 0x0
	// Position of TRIGACT field.
	DMAC_CHANNEL_CHCTRLA_TRIGACT_Pos = 0x14
	// Bit mask of TRIGACT field.
	DMAC_CHANNEL_CHCTRLA_TRIGACT_Msk = 0x300000
	// One trigger required for each block transfer
	DMAC_CHANNEL_CHCTRLA_TRIGACT_BLOCK = 0x0
	// One trigger required for each burst transfer
	DMAC_CHANNEL_CHCTRLA_TRIGACT_BURST = 0x2
	// One trigger required for each transaction
	DMAC_CHANNEL_CHCTRLA_TRIGACT_TRANSACTION = 0x3
	// Position of BURSTLEN field.
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_Pos = 0x18
	// Bit mask of BURSTLEN field.
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_Msk = 0xf000000
	// Single-beat burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_SINGLE = 0x0
	// 2-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_2BEAT = 0x1
	// 3-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_3BEAT = 0x2
	// 4-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_4BEAT = 0x3
	// 5-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_5BEAT = 0x4
	// 6-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_6BEAT = 0x5
	// 7-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_7BEAT = 0x6
	// 8-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_8BEAT = 0x7
	// 9-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_9BEAT = 0x8
	// 10-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_10BEAT = 0x9
	// 11-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_11BEAT = 0xa
	// 12-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_12BEAT = 0xb
	// 13-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_13BEAT = 0xc
	// 14-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_14BEAT = 0xd
	// 15-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_15BEAT = 0xe
	// 16-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_16BEAT = 0xf
	// Position of THRESHOLD field.
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_Pos = 0x1c
	// Bit mask of THRESHOLD field.
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_Msk = 0x30000000
	// Destination write starts after each beat source address read
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_1BEAT = 0x0
	// Destination write starts after 2-beats source address read
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_2BEATS = 0x1
	// Destination write starts after 4-beats source address read
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_4BEATS = 0x2
	// Destination write starts after 8-beats source address read
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_8BEATS = 0x3

	// CHANNEL.CHCTRLB: Channel n Control B
	// Position of CMD field.
	DMAC_CHANNEL_CHCTRLB_CMD_Pos = 0x0
	// Bit mask of CMD field.
	DMAC_CHANNEL_CHCTRLB_CMD_Msk = 0x3
	// No action
	DMAC_CHANNEL_CHCTRLB_CMD_NOACT = 0x0
	// Channel suspend operation
	DMAC_CHANNEL_CHCTRLB_CMD_SUSPEND = 0x1
	// Channel resume operation
	DMAC_CHANNEL_CHCTRLB_CMD_RESUME = 0x2

	// CHANNEL.CHPRILVL: Channel n Priority Level
	// Position of PRILVL field.
	DMAC_CHANNEL_CHPRILVL_PRILVL_Pos = 0x0
	// Bit mask of PRILVL field.
	DMAC_CHANNEL_CHPRILVL_PRILVL_Msk = 0x3
	// Channel Priority Level 0 (Lowest Level)
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL0 = 0x0
	// Channel Priority Level 1
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL1 = 0x1
	// Channel Priority Level 2
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL2 = 0x2
	// Channel Priority Level 3 (Highest Level)
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL3 = 0x3

	// CHANNEL.CHEVCTRL: Channel n Event Control
	// Position of EVACT field.
	DMAC_CHANNEL_CHEVCTRL_EVACT_Pos = 0x0
	// Bit mask of EVACT field.
	DMAC_CHANNEL_CHEVCTRL_EVACT_Msk = 0x7
	// No action
	DMAC_CHANNEL_CHEVCTRL_EVACT_NOACT = 0x0
	// Transfer and periodic transfer trigger
	DMAC_CHANNEL_CHEVCTRL_EVACT_TRIG = 0x1
	// Conditional transfer trigger
	DMAC_CHANNEL_CHEVCTRL_EVACT_CTRIG = 0x2
	// Conditional block transfer
	DMAC_CHANNEL_CHEVCTRL_EVACT_CBLOCK = 0x3
	// Channel suspend operation
	DMAC_CHANNEL_CHEVCTRL_EVACT_SUSPEND = 0x4
	// Channel resume operation
	DMAC_CHANNEL_CHEVCTRL_EVACT_RESUME = 0x5
	// Skip next block suspend action
	DMAC_CHANNEL_CHEVCTRL_EVACT_SSKIP = 0x6
	// Increase priority
	DMAC_CHANNEL_CHEVCTRL_EVACT_INCPRI = 0x7
	// Position of EVOMODE field.
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_Pos = 0x4
	// Bit mask of EVOMODE field.
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_Msk = 0x30
	// Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_DEFAULT = 0x0
	// Ongoing trigger action
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_TRIGACT = 0x1
	// Position of EVIE field.
	DMAC_CHANNEL_CHEVCTRL_EVIE_Pos = 0x6
	// Bit mask of EVIE field.
	DMAC_CHANNEL_CHEVCTRL_EVIE_Msk = 0x40
	// Bit EVIE.
	DMAC_CHANNEL_CHEVCTRL_EVIE = 0x40
	// Position of EVOE field.
	DMAC_CHANNEL_CHEVCTRL_EVOE_Pos = 0x7
	// Bit mask of EVOE field.
	DMAC_CHANNEL_CHEVCTRL_EVOE_Msk = 0x80
	// Bit EVOE.
	DMAC_CHANNEL_CHEVCTRL_EVOE = 0x80

	// CHANNEL.CHINTENCLR: Channel n Interrupt Enable Clear
	// Position of TERR field.
	DMAC_CHANNEL_CHINTENCLR_TERR_Pos = 0x0
	// Bit mask of TERR field.
	DMAC_CHANNEL_CHINTENCLR_TERR_Msk = 0x1
	// Bit TERR.
	DMAC_CHANNEL_CHINTENCLR_TERR = 0x1
	// Position of TCMPL field.
	DMAC_CHANNEL_CHINTENCLR_TCMPL_Pos = 0x1
	// Bit mask of TCMPL field.
	DMAC_CHANNEL_CHINTENCLR_TCMPL_Msk = 0x2
	// Bit TCMPL.
	DMAC_CHANNEL_CHINTENCLR_TCMPL = 0x2
	// Position of SUSP field.
	DMAC_CHANNEL_CHINTENCLR_SUSP_Pos = 0x2
	// Bit mask of SUSP field.
	DMAC_CHANNEL_CHINTENCLR_SUSP_Msk = 0x4
	// Bit SUSP.
	DMAC_CHANNEL_CHINTENCLR_SUSP = 0x4

	// CHANNEL.CHINTENSET: Channel n Interrupt Enable Set
	// Position of TERR field.
	DMAC_CHANNEL_CHINTENSET_TERR_Pos = 0x0
	// Bit mask of TERR field.
	DMAC_CHANNEL_CHINTENSET_TERR_Msk = 0x1
	// Bit TERR.
	DMAC_CHANNEL_CHINTENSET_TERR = 0x1
	// Position of TCMPL field.
	DMAC_CHANNEL_CHINTENSET_TCMPL_Pos = 0x1
	// Bit mask of TCMPL field.
	DMAC_CHANNEL_CHINTENSET_TCMPL_Msk = 0x2
	// Bit TCMPL.
	DMAC_CHANNEL_CHINTENSET_TCMPL = 0x2
	// Position of SUSP field.
	DMAC_CHANNEL_CHINTENSET_SUSP_Pos = 0x2
	// Bit mask of SUSP field.
	DMAC_CHANNEL_CHINTENSET_SUSP_Msk = 0x4
	// Bit SUSP.
	DMAC_CHANNEL_CHINTENSET_SUSP = 0x4

	// CHANNEL.CHINTFLAG: Channel n Interrupt Flag Status and Clear
	// Position of TERR field.
	DMAC_CHANNEL_CHINTFLAG_TERR_Pos = 0x0
	// Bit mask of TERR field.
	DMAC_CHANNEL_CHINTFLAG_TERR_Msk = 0x1
	// Bit TERR.
	DMAC_CHANNEL_CHINTFLAG_TERR = 0x1
	// Position of TCMPL field.
	DMAC_CHANNEL_CHINTFLAG_TCMPL_Pos = 0x1
	// Bit mask of TCMPL field.
	DMAC_CHANNEL_CHINTFLAG_TCMPL_Msk = 0x2
	// Bit TCMPL.
	DMAC_CHANNEL_CHINTFLAG_TCMPL = 0x2
	// Position of SUSP field.
	DMAC_CHANNEL_CHINTFLAG_SUSP_Pos = 0x2
	// Bit mask of SUSP field.
	DMAC_CHANNEL_CHINTFLAG_SUSP_Msk = 0x4
	// Bit SUSP.
	DMAC_CHANNEL_CHINTFLAG_SUSP = 0x4

	// CHANNEL.CHSTATUS: Channel n Status
	// Position of PEND field.
	DMAC_CHANNEL_CHSTATUS_PEND_Pos = 0x0
	// Bit mask of PEND field.
	DMAC_CHANNEL_CHSTATUS_PEND_Msk = 0x1
	// Bit PEND.
	DMAC_CHANNEL_CHSTATUS_PEND = 0x1
	// Position of BUSY field.
	DMAC_CHANNEL_CHSTATUS_BUSY_Pos = 0x1
	// Bit mask of BUSY field.
	DMAC_CHANNEL_CHSTATUS_BUSY_Msk = 0x2
	// Bit BUSY.
	DMAC_CHANNEL_CHSTATUS_BUSY = 0x2
	// Position of FERR field.
	DMAC_CHANNEL_CHSTATUS_FERR_Pos = 0x2
	// Bit mask of FERR field.
	DMAC_CHANNEL_CHSTATUS_FERR_Msk = 0x4
	// Bit FERR.
	DMAC_CHANNEL_CHSTATUS_FERR = 0x4
	// Position of CRCERR field.
	DMAC_CHANNEL_CHSTATUS_CRCERR_Pos = 0x3
	// Bit mask of CRCERR field.
	DMAC_CHANNEL_CHSTATUS_CRCERR_Msk = 0x8
	// Bit CRCERR.
	DMAC_CHANNEL_CHSTATUS_CRCERR = 0x8
)

// Bitfields for DSU: Device Service Unit
const (
	// CTRL: Control
	// Position of SWRST field.
	DSU_CTRL_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	DSU_CTRL_SWRST_Msk = 0x1
	// Bit SWRST.
	DSU_CTRL_SWRST = 0x1
	// Position of CRC field.
	DSU_CTRL_CRC_Pos = 0x2
	// Bit mask of CRC field.
	DSU_CTRL_CRC_Msk = 0x4
	// Bit CRC.
	DSU_CTRL_CRC = 0x4
	// Position of MBIST field.
	DSU_CTRL_MBIST_Pos = 0x3
	// Bit mask of MBIST field.
	DSU_CTRL_MBIST_Msk = 0x8
	// Bit MBIST.
	DSU_CTRL_MBIST = 0x8
	// Position of CE field.
	DSU_CTRL_CE_Pos = 0x4
	// Bit mask of CE field.
	DSU_CTRL_CE_Msk = 0x10
	// Bit CE.
	DSU_CTRL_CE = 0x10
	// Position of ARR field.
	DSU_CTRL_ARR_Pos = 0x6
	// Bit mask of ARR field.
	DSU_CTRL_ARR_Msk = 0x40
	// Bit ARR.
	DSU_CTRL_ARR = 0x40
	// Position of SMSA field.
	DSU_CTRL_SMSA_Pos = 0x7
	// Bit mask of SMSA field.
	DSU_CTRL_SMSA_Msk = 0x80
	// Bit SMSA.
	DSU_CTRL_SMSA = 0x80

	// STATUSA: Status A
	// Position of DONE field.
	DSU_STATUSA_DONE_Pos = 0x0
	// Bit mask of DONE field.
	DSU_STATUSA_DONE_Msk = 0x1
	// Bit DONE.
	DSU_STATUSA_DONE = 0x1
	// Position of CRSTEXT field.
	DSU_STATUSA_CRSTEXT_Pos = 0x1
	// Bit mask of CRSTEXT field.
	DSU_STATUSA_CRSTEXT_Msk = 0x2
	// Bit CRSTEXT.
	DSU_STATUSA_CRSTEXT = 0x2
	// Position of BERR field.
	DSU_STATUSA_BERR_Pos = 0x2
	// Bit mask of BERR field.
	DSU_STATUSA_BERR_Msk = 0x4
	// Bit BERR.
	DSU_STATUSA_BERR = 0x4
	// Position of FAIL field.
	DSU_STATUSA_FAIL_Pos = 0x3
	// Bit mask of FAIL field.
	DSU_STATUSA_FAIL_Msk = 0x8
	// Bit FAIL.
	DSU_STATUSA_FAIL = 0x8
	// Position of PERR field.
	DSU_STATUSA_PERR_Pos = 0x4
	// Bit mask of PERR field.
	DSU_STATUSA_PERR_Msk = 0x10
	// Bit PERR.
	DSU_STATUSA_PERR = 0x10

	// STATUSB: Status B
	// Position of PROT field.
	DSU_STATUSB_PROT_Pos = 0x0
	// Bit mask of PROT field.
	DSU_STATUSB_PROT_Msk = 0x1
	// Bit PROT.
	DSU_STATUSB_PROT = 0x1
	// Position of DBGPRES field.
	DSU_STATUSB_DBGPRES_Pos = 0x1
	// Bit mask of DBGPRES field.
	DSU_STATUSB_DBGPRES_Msk = 0x2
	// Bit DBGPRES.
	DSU_STATUSB_DBGPRES = 0x2
	// Position of DCCD0 field.
	DSU_STATUSB_DCCD0_Pos = 0x2
	// Bit mask of DCCD0 field.
	DSU_STATUSB_DCCD0_Msk = 0x4
	// Bit DCCD0.
	DSU_STATUSB_DCCD0 = 0x4
	// Position of DCCD1 field.
	DSU_STATUSB_DCCD1_Pos = 0x3
	// Bit mask of DCCD1 field.
	DSU_STATUSB_DCCD1_Msk = 0x8
	// Bit DCCD1.
	DSU_STATUSB_DCCD1 = 0x8
	// Position of HPE field.
	DSU_STATUSB_HPE_Pos = 0x4
	// Bit mask of HPE field.
	DSU_STATUSB_HPE_Msk = 0x10
	// Bit HPE.
	DSU_STATUSB_HPE = 0x10
	// Position of CELCK field.
	DSU_STATUSB_CELCK_Pos = 0x5
	// Bit mask of CELCK field.
	DSU_STATUSB_CELCK_Msk = 0x20
	// Bit CELCK.
	DSU_STATUSB_CELCK = 0x20
	// Position of TDCCD0 field.
	DSU_STATUSB_TDCCD0_Pos = 0x6
	// Bit mask of TDCCD0 field.
	DSU_STATUSB_TDCCD0_Msk = 0x40
	// Bit TDCCD0.
	DSU_STATUSB_TDCCD0 = 0x40
	// Position of TDCCD1 field.
	DSU_STATUSB_TDCCD1_Pos = 0x7
	// Bit mask of TDCCD1 field.
	DSU_STATUSB_TDCCD1_Msk = 0x80
	// Bit TDCCD1.
	DSU_STATUSB_TDCCD1 = 0x80

	// ADDR: Address
	// Position of AMOD field.
	DSU_ADDR_AMOD_Pos = 0x0
	// Bit mask of AMOD field.
	DSU_ADDR_AMOD_Msk = 0x3
	// Position of ADDR field.
	DSU_ADDR_ADDR_Pos = 0x2
	// Bit mask of ADDR field.
	DSU_ADDR_ADDR_Msk = 0xfffffffc

	// LENGTH: Length
	// Position of LENGTH field.
	DSU_LENGTH_LENGTH_Pos = 0x2
	// Bit mask of LENGTH field.
	DSU_LENGTH_LENGTH_Msk = 0xfffffffc

	// DATA: Data
	// Position of DATA field.
	DSU_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	DSU_DATA_DATA_Msk = 0xffffffff

	// DCC: Debug Communication Channel n
	// Position of DATA field.
	DSU_DCC_DATA_Pos = 0x0
	// Bit mask of DATA field.
	DSU_DCC_DATA_Msk = 0xffffffff

	// DID: Device Identification
	// Position of DEVSEL field.
	DSU_DID_DEVSEL_Pos = 0x0
	// Bit mask of DEVSEL field.
	DSU_DID_DEVSEL_Msk = 0xff
	// Position of REVISION field.
	DSU_DID_REVISION_Pos = 0x8
	// Bit mask of REVISION field.
	DSU_DID_REVISION_Msk = 0xf00
	// Position of DIE field.
	DSU_DID_DIE_Pos = 0xc
	// Bit mask of DIE field.
	DSU_DID_DIE_Msk = 0xf000
	// Position of SERIES field.
	DSU_DID_SERIES_Pos = 0x10
	// Bit mask of SERIES field.
	DSU_DID_SERIES_Msk = 0x3f0000
	// Cortex-M0+ processor, basic feature set
	DSU_DID_SERIES_0 = 0x0
	// Cortex-M0+ processor, USB
	DSU_DID_SERIES_1 = 0x1
	// Position of FAMILY field.
	DSU_DID_FAMILY_Pos = 0x17
	// Bit mask of FAMILY field.
	DSU_DID_FAMILY_Msk = 0xf800000
	// General purpose microcontroller
	DSU_DID_FAMILY_0 = 0x0
	// PicoPower
	DSU_DID_FAMILY_1 = 0x1
	// Position of PROCESSOR field.
	DSU_DID_PROCESSOR_Pos = 0x1c
	// Bit mask of PROCESSOR field.
	DSU_DID_PROCESSOR_Msk = 0xf0000000
	// Cortex-M0+
	DSU_DID_PROCESSOR_CM0P = 0x1
	// Cortex-M23
	DSU_DID_PROCESSOR_CM23 = 0x2
	// Cortex-M3
	DSU_DID_PROCESSOR_CM3 = 0x3
	// Cortex-M4
	DSU_DID_PROCESSOR_CM4 = 0x5
	// Cortex-M4 with FPU
	DSU_DID_PROCESSOR_CM4F = 0x6
	// Cortex-M33
	DSU_DID_PROCESSOR_CM33 = 0x7

	// CFG: Configuration
	// Position of LQOS field.
	DSU_CFG_LQOS_Pos = 0x0
	// Bit mask of LQOS field.
	DSU_CFG_LQOS_Msk = 0x3
	// Position of DCCDMALEVEL field.
	DSU_CFG_DCCDMALEVEL_Pos = 0x2
	// Bit mask of DCCDMALEVEL field.
	DSU_CFG_DCCDMALEVEL_Msk = 0xc
	// Trigger rises when DCC is empty
	DSU_CFG_DCCDMALEVEL_EMPTY = 0x0
	// Trigger rises when DCC is full
	DSU_CFG_DCCDMALEVEL_FULL = 0x1
	// Position of ETBRAMEN field.
	DSU_CFG_ETBRAMEN_Pos = 0x4
	// Bit mask of ETBRAMEN field.
	DSU_CFG_ETBRAMEN_Msk = 0x10
	// Bit ETBRAMEN.
	DSU_CFG_ETBRAMEN = 0x10

	// DCFG: Device Configuration
	// Position of DCFG field.
	DSU_DCFG_DCFG_Pos = 0x0
	// Bit mask of DCFG field.
	DSU_DCFG_DCFG_Msk = 0xffffffff

	// ENTRY0: CoreSight ROM Table Entry 0
	// Position of EPRES field.
	DSU_ENTRY0_EPRES_Pos = 0x0
	// Bit mask of EPRES field.
	DSU_ENTRY0_EPRES_Msk = 0x1
	// Bit EPRES.
	DSU_ENTRY0_EPRES = 0x1
	// Position of FMT field.
	DSU_ENTRY0_FMT_Pos = 0x1
	// Bit mask of FMT field.
	DSU_ENTRY0_FMT_Msk = 0x2
	// Bit FMT.
	DSU_ENTRY0_FMT = 0x2
	// Position of ADDOFF field.
	DSU_ENTRY0_ADDOFF_Pos = 0xc
	// Bit mask of ADDOFF field.
	DSU_ENTRY0_ADDOFF_Msk = 0xfffff000

	// END: CoreSight ROM Table End
	// Position of END field.
	DSU_END_END_Pos = 0x0
	// Bit mask of END field.
	DSU_END_END_Msk = 0xffffffff

	// MEMTYPE: CoreSight ROM Table Memory Type
	// Position of SMEMP field.
	DSU_MEMTYPE_SMEMP_Pos = 0x0
	// Bit mask of SMEMP field.
	DSU_MEMTYPE_SMEMP_Msk = 0x1
	// Bit SMEMP.
	DSU_MEMTYPE_SMEMP = 0x1

	// PID4: Peripheral Identification 4
	// Position of JEPCC field.
	DSU_PID4_JEPCC_Pos = 0x0
	// Bit mask of JEPCC field.
	DSU_PID4_JEPCC_Msk = 0xf
	// Position of FKBC field.
	DSU_PID4_FKBC_Pos = 0x4
	// Bit mask of FKBC field.
	DSU_PID4_FKBC_Msk = 0xf0

	// PID0: Peripheral Identification 0
	// Position of PARTNBL field.
	DSU_PID0_PARTNBL_Pos = 0x0
	// Bit mask of PARTNBL field.
	DSU_PID0_PARTNBL_Msk = 0xff

	// PID1: Peripheral Identification 1
	// Position of PARTNBH field.
	DSU_PID1_PARTNBH_Pos = 0x0
	// Bit mask of PARTNBH field.
	DSU_PID1_PARTNBH_Msk = 0xf
	// Position of JEPIDCL field.
	DSU_PID1_JEPIDCL_Pos = 0x4
	// Bit mask of JEPIDCL field.
	DSU_PID1_JEPIDCL_Msk = 0xf0

	// PID2: Peripheral Identification 2
	// Position of JEPIDCH field.
	DSU_PID2_JEPIDCH_Pos = 0x0
	// Bit mask of JEPIDCH field.
	DSU_PID2_JEPIDCH_Msk = 0x7
	// Position of JEPU field.
	DSU_PID2_JEPU_Pos = 0x3
	// Bit mask of JEPU field.
	DSU_PID2_JEPU_Msk = 0x8
	// Bit JEPU.
	DSU_PID2_JEPU = 0x8
	// Position of REVISION field.
	DSU_PID2_REVISION_Pos = 0x4
	// Bit mask of REVISION field.
	DSU_PID2_REVISION_Msk = 0xf0

	// PID3: Peripheral Identification 3
	// Position of CUSMOD field.
	DSU_PID3_CUSMOD_Pos = 0x0
	// Bit mask of CUSMOD field.
	DSU_PID3_CUSMOD_Msk = 0xf
	// Position of REVAND field.
	DSU_PID3_REVAND_Pos = 0x4
	// Bit mask of REVAND field.
	DSU_PID3_REVAND_Msk = 0xf0

	// CID0: Component Identification 0
	// Position of PREAMBLEB0 field.
	DSU_CID0_PREAMBLEB0_Pos = 0x0
	// Bit mask of PREAMBLEB0 field.
	DSU_CID0_PREAMBLEB0_Msk = 0xff

	// CID1: Component Identification 1
	// Position of PREAMBLE field.
	DSU_CID1_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	DSU_CID1_PREAMBLE_Msk = 0xf
	// Position of CCLASS field.
	DSU_CID1_CCLASS_Pos = 0x4
	// Bit mask of CCLASS field.
	DSU_CID1_CCLASS_Msk = 0xf0

	// CID2: Component Identification 2
	// Position of PREAMBLEB2 field.
	DSU_CID2_PREAMBLEB2_Pos = 0x0
	// Bit mask of PREAMBLEB2 field.
	DSU_CID2_PREAMBLEB2_Msk = 0xff

	// CID3: Component Identification 3
	// Position of PREAMBLEB3 field.
	DSU_CID3_PREAMBLEB3_Pos = 0x0
	// Bit mask of PREAMBLEB3 field.
	DSU_CID3_PREAMBLEB3_Msk = 0xff
)

// Bitfields for EIC: External Interrupt Controller
const (
	// CTRLA: Control A
	// Position of SWRST field.
	EIC_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	EIC_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	EIC_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	EIC_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	EIC_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	EIC_CTRLA_ENABLE = 0x2
	// Position of CKSEL field.
	EIC_CTRLA_CKSEL_Pos = 0x4
	// Bit mask of CKSEL field.
	EIC_CTRLA_CKSEL_Msk = 0x10
	// Bit CKSEL.
	EIC_CTRLA_CKSEL = 0x10
	// Clocked by GCLK
	EIC_CTRLA_CKSEL_CLK_GCLK = 0x0
	// Clocked by ULP32K
	EIC_CTRLA_CKSEL_CLK_ULP32K = 0x1

	// NMICTRL: Non-Maskable Interrupt Control
	// Position of NMISENSE field.
	EIC_NMICTRL_NMISENSE_Pos = 0x0
	// Bit mask of NMISENSE field.
	EIC_NMICTRL_NMISENSE_Msk = 0x7
	// No detection
	EIC_NMICTRL_NMISENSE_NONE = 0x0
	// Rising-edge detection
	EIC_NMICTRL_NMISENSE_RISE = 0x1
	// Falling-edge detection
	EIC_NMICTRL_NMISENSE_FALL = 0x2
	// Both-edges detection
	EIC_NMICTRL_NMISENSE_BOTH = 0x3
	// High-level detection
	EIC_NMICTRL_NMISENSE_HIGH = 0x4
	// Low-level detection
	EIC_NMICTRL_NMISENSE_LOW = 0x5
	// Position of NMIFILTEN field.
	EIC_NMICTRL_NMIFILTEN_Pos = 0x3
	// Bit mask of NMIFILTEN field.
	EIC_NMICTRL_NMIFILTEN_Msk = 0x8
	// Bit NMIFILTEN.
	EIC_NMICTRL_NMIFILTEN = 0x8
	// Position of NMIASYNCH field.
	EIC_NMICTRL_NMIASYNCH_Pos = 0x4
	// Bit mask of NMIASYNCH field.
	EIC_NMICTRL_NMIASYNCH_Msk = 0x10
	// Bit NMIASYNCH.
	EIC_NMICTRL_NMIASYNCH = 0x10
	// Edge detection is clock synchronously operated
	EIC_NMICTRL_NMIASYNCH_SYNC = 0x0
	// Edge detection is clock asynchronously operated
	EIC_NMICTRL_NMIASYNCH_ASYNC = 0x1

	// NMIFLAG: Non-Maskable Interrupt Flag Status and Clear
	// Position of NMI field.
	EIC_NMIFLAG_NMI_Pos = 0x0
	// Bit mask of NMI field.
	EIC_NMIFLAG_NMI_Msk = 0x1
	// Bit NMI.
	EIC_NMIFLAG_NMI = 0x1

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	EIC_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	EIC_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	EIC_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	EIC_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	EIC_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	EIC_SYNCBUSY_ENABLE = 0x2

	// EVCTRL: Event Control
	// Position of EXTINTEO field.
	EIC_EVCTRL_EXTINTEO_Pos = 0x0
	// Bit mask of EXTINTEO field.
	EIC_EVCTRL_EXTINTEO_Msk = 0xffff

	// INTENCLR: Interrupt Enable Clear
	// Position of EXTINT field.
	EIC_INTENCLR_EXTINT_Pos = 0x0
	// Bit mask of EXTINT field.
	EIC_INTENCLR_EXTINT_Msk = 0xffff

	// INTENSET: Interrupt Enable Set
	// Position of EXTINT field.
	EIC_INTENSET_EXTINT_Pos = 0x0
	// Bit mask of EXTINT field.
	EIC_INTENSET_EXTINT_Msk = 0xffff

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of EXTINT field.
	EIC_INTFLAG_EXTINT_Pos = 0x0
	// Bit mask of EXTINT field.
	EIC_INTFLAG_EXTINT_Msk = 0xffff

	// ASYNCH: External Interrupt Asynchronous Mode
	// Position of ASYNCH field.
	EIC_ASYNCH_ASYNCH_Pos = 0x0
	// Bit mask of ASYNCH field.
	EIC_ASYNCH_ASYNCH_Msk = 0xffff
	// Edge detection is clock synchronously operated
	EIC_ASYNCH_ASYNCH_SYNC = 0x0
	// Edge detection is clock asynchronously operated
	EIC_ASYNCH_ASYNCH_ASYNC = 0x1

	// CONFIG: External Interrupt Sense Configuration
	// Position of SENSE0 field.
	EIC_CONFIG_SENSE0_Pos = 0x0
	// Bit mask of SENSE0 field.
	EIC_CONFIG_SENSE0_Msk = 0x7
	// No detection
	EIC_CONFIG_SENSE0_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE0_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE0_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE0_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE0_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE0_LOW = 0x5
	// Position of FILTEN0 field.
	EIC_CONFIG_FILTEN0_Pos = 0x3
	// Bit mask of FILTEN0 field.
	EIC_CONFIG_FILTEN0_Msk = 0x8
	// Bit FILTEN0.
	EIC_CONFIG_FILTEN0 = 0x8
	// Position of SENSE1 field.
	EIC_CONFIG_SENSE1_Pos = 0x4
	// Bit mask of SENSE1 field.
	EIC_CONFIG_SENSE1_Msk = 0x70
	// No detection
	EIC_CONFIG_SENSE1_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE1_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE1_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE1_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE1_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE1_LOW = 0x5
	// Position of FILTEN1 field.
	EIC_CONFIG_FILTEN1_Pos = 0x7
	// Bit mask of FILTEN1 field.
	EIC_CONFIG_FILTEN1_Msk = 0x80
	// Bit FILTEN1.
	EIC_CONFIG_FILTEN1 = 0x80
	// Position of SENSE2 field.
	EIC_CONFIG_SENSE2_Pos = 0x8
	// Bit mask of SENSE2 field.
	EIC_CONFIG_SENSE2_Msk = 0x700
	// No detection
	EIC_CONFIG_SENSE2_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE2_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE2_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE2_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE2_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE2_LOW = 0x5
	// Position of FILTEN2 field.
	EIC_CONFIG_FILTEN2_Pos = 0xb
	// Bit mask of FILTEN2 field.
	EIC_CONFIG_FILTEN2_Msk = 0x800
	// Bit FILTEN2.
	EIC_CONFIG_FILTEN2 = 0x800
	// Position of SENSE3 field.
	EIC_CONFIG_SENSE3_Pos = 0xc
	// Bit mask of SENSE3 field.
	EIC_CONFIG_SENSE3_Msk = 0x7000
	// No detection
	EIC_CONFIG_SENSE3_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE3_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE3_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE3_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE3_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE3_LOW = 0x5
	// Position of FILTEN3 field.
	EIC_CONFIG_FILTEN3_Pos = 0xf
	// Bit mask of FILTEN3 field.
	EIC_CONFIG_FILTEN3_Msk = 0x8000
	// Bit FILTEN3.
	EIC_CONFIG_FILTEN3 = 0x8000
	// Position of SENSE4 field.
	EIC_CONFIG_SENSE4_Pos = 0x10
	// Bit mask of SENSE4 field.
	EIC_CONFIG_SENSE4_Msk = 0x70000
	// No detection
	EIC_CONFIG_SENSE4_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE4_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE4_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE4_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE4_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE4_LOW = 0x5
	// Position of FILTEN4 field.
	EIC_CONFIG_FILTEN4_Pos = 0x13
	// Bit mask of FILTEN4 field.
	EIC_CONFIG_FILTEN4_Msk = 0x80000
	// Bit FILTEN4.
	EIC_CONFIG_FILTEN4 = 0x80000
	// Position of SENSE5 field.
	EIC_CONFIG_SENSE5_Pos = 0x14
	// Bit mask of SENSE5 field.
	EIC_CONFIG_SENSE5_Msk = 0x700000
	// No detection
	EIC_CONFIG_SENSE5_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE5_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE5_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE5_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE5_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE5_LOW = 0x5
	// Position of FILTEN5 field.
	EIC_CONFIG_FILTEN5_Pos = 0x17
	// Bit mask of FILTEN5 field.
	EIC_CONFIG_FILTEN5_Msk = 0x800000
	// Bit FILTEN5.
	EIC_CONFIG_FILTEN5 = 0x800000
	// Position of SENSE6 field.
	EIC_CONFIG_SENSE6_Pos = 0x18
	// Bit mask of SENSE6 field.
	EIC_CONFIG_SENSE6_Msk = 0x7000000
	// No detection
	EIC_CONFIG_SENSE6_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE6_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE6_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE6_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE6_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE6_LOW = 0x5
	// Position of FILTEN6 field.
	EIC_CONFIG_FILTEN6_Pos = 0x1b
	// Bit mask of FILTEN6 field.
	EIC_CONFIG_FILTEN6_Msk = 0x8000000
	// Bit FILTEN6.
	EIC_CONFIG_FILTEN6 = 0x8000000
	// Position of SENSE7 field.
	EIC_CONFIG_SENSE7_Pos = 0x1c
	// Bit mask of SENSE7 field.
	EIC_CONFIG_SENSE7_Msk = 0x70000000
	// No detection
	EIC_CONFIG_SENSE7_NONE = 0x0
	// Rising edge detection
	EIC_CONFIG_SENSE7_RISE = 0x1
	// Falling edge detection
	EIC_CONFIG_SENSE7_FALL = 0x2
	// Both edges detection
	EIC_CONFIG_SENSE7_BOTH = 0x3
	// High level detection
	EIC_CONFIG_SENSE7_HIGH = 0x4
	// Low level detection
	EIC_CONFIG_SENSE7_LOW = 0x5
	// Position of FILTEN7 field.
	EIC_CONFIG_FILTEN7_Pos = 0x1f
	// Bit mask of FILTEN7 field.
	EIC_CONFIG_FILTEN7_Msk = 0x80000000
	// Bit FILTEN7.
	EIC_CONFIG_FILTEN7 = 0x80000000

	// DEBOUNCEN: Debouncer Enable
	// Position of DEBOUNCEN field.
	EIC_DEBOUNCEN_DEBOUNCEN_Pos = 0x0
	// Bit mask of DEBOUNCEN field.
	EIC_DEBOUNCEN_DEBOUNCEN_Msk = 0xffff

	// DPRESCALER: Debouncer Prescaler
	// Position of PRESCALER0 field.
	EIC_DPRESCALER_PRESCALER0_Pos = 0x0
	// Bit mask of PRESCALER0 field.
	EIC_DPRESCALER_PRESCALER0_Msk = 0x7
	// EIC clock divided by 2
	EIC_DPRESCALER_PRESCALER0_DIV2 = 0x0
	// EIC clock divided by 4
	EIC_DPRESCALER_PRESCALER0_DIV4 = 0x1
	// EIC clock divided by 8
	EIC_DPRESCALER_PRESCALER0_DIV8 = 0x2
	// EIC clock divided by 16
	EIC_DPRESCALER_PRESCALER0_DIV16 = 0x3
	// EIC clock divided by 32
	EIC_DPRESCALER_PRESCALER0_DIV32 = 0x4
	// EIC clock divided by 64
	EIC_DPRESCALER_PRESCALER0_DIV64 = 0x5
	// EIC clock divided by 128
	EIC_DPRESCALER_PRESCALER0_DIV128 = 0x6
	// EIC clock divided by 256
	EIC_DPRESCALER_PRESCALER0_DIV256 = 0x7
	// Position of STATES0 field.
	EIC_DPRESCALER_STATES0_Pos = 0x3
	// Bit mask of STATES0 field.
	EIC_DPRESCALER_STATES0_Msk = 0x8
	// Bit STATES0.
	EIC_DPRESCALER_STATES0 = 0x8
	// 3 low frequency samples
	EIC_DPRESCALER_STATES0_LFREQ3 = 0x0
	// 7 low frequency samples
	EIC_DPRESCALER_STATES0_LFREQ7 = 0x1
	// Position of PRESCALER1 field.
	EIC_DPRESCALER_PRESCALER1_Pos = 0x4
	// Bit mask of PRESCALER1 field.
	EIC_DPRESCALER_PRESCALER1_Msk = 0x70
	// EIC clock divided by 2
	EIC_DPRESCALER_PRESCALER1_DIV2 = 0x0
	// EIC clock divided by 4
	EIC_DPRESCALER_PRESCALER1_DIV4 = 0x1
	// EIC clock divided by 8
	EIC_DPRESCALER_PRESCALER1_DIV8 = 0x2
	// EIC clock divided by 16
	EIC_DPRESCALER_PRESCALER1_DIV16 = 0x3
	// EIC clock divided by 32
	EIC_DPRESCALER_PRESCALER1_DIV32 = 0x4
	// EIC clock divided by 64
	EIC_DPRESCALER_PRESCALER1_DIV64 = 0x5
	// EIC clock divided by 128
	EIC_DPRESCALER_PRESCALER1_DIV128 = 0x6
	// EIC clock divided by 256
	EIC_DPRESCALER_PRESCALER1_DIV256 = 0x7
	// Position of STATES1 field.
	EIC_DPRESCALER_STATES1_Pos = 0x7
	// Bit mask of STATES1 field.
	EIC_DPRESCALER_STATES1_Msk = 0x80
	// Bit STATES1.
	EIC_DPRESCALER_STATES1 = 0x80
	// 3 low frequency samples
	EIC_DPRESCALER_STATES1_LFREQ3 = 0x0
	// 7 low frequency samples
	EIC_DPRESCALER_STATES1_LFREQ7 = 0x1
	// Position of TICKON field.
	EIC_DPRESCALER_TICKON_Pos = 0x10
	// Bit mask of TICKON field.
	EIC_DPRESCALER_TICKON_Msk = 0x10000
	// Bit TICKON.
	EIC_DPRESCALER_TICKON = 0x10000
	// Clocked by GCLK
	EIC_DPRESCALER_TICKON_CLK_GCLK_EIC = 0x0
	// Clocked by Low Frequency Clock
	EIC_DPRESCALER_TICKON_CLK_LFREQ = 0x1

	// PINSTATE: Pin State
	// Position of PINSTATE field.
	EIC_PINSTATE_PINSTATE_Pos = 0x0
	// Bit mask of PINSTATE field.
	EIC_PINSTATE_PINSTATE_Msk = 0xffff
)

// Bitfields for EVSYS: Event System Interface
const (
	// CTRLA: Control
	// Position of SWRST field.
	EVSYS_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	EVSYS_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	EVSYS_CTRLA_SWRST = 0x1

	// SWEVT: Software Event
	// Position of CHANNEL0 field.
	EVSYS_SWEVT_CHANNEL0_Pos = 0x0
	// Bit mask of CHANNEL0 field.
	EVSYS_SWEVT_CHANNEL0_Msk = 0x1
	// Bit CHANNEL0.
	EVSYS_SWEVT_CHANNEL0 = 0x1
	// Position of CHANNEL1 field.
	EVSYS_SWEVT_CHANNEL1_Pos = 0x1
	// Bit mask of CHANNEL1 field.
	EVSYS_SWEVT_CHANNEL1_Msk = 0x2
	// Bit CHANNEL1.
	EVSYS_SWEVT_CHANNEL1 = 0x2
	// Position of CHANNEL2 field.
	EVSYS_SWEVT_CHANNEL2_Pos = 0x2
	// Bit mask of CHANNEL2 field.
	EVSYS_SWEVT_CHANNEL2_Msk = 0x4
	// Bit CHANNEL2.
	EVSYS_SWEVT_CHANNEL2 = 0x4
	// Position of CHANNEL3 field.
	EVSYS_SWEVT_CHANNEL3_Pos = 0x3
	// Bit mask of CHANNEL3 field.
	EVSYS_SWEVT_CHANNEL3_Msk = 0x8
	// Bit CHANNEL3.
	EVSYS_SWEVT_CHANNEL3 = 0x8
	// Position of CHANNEL4 field.
	EVSYS_SWEVT_CHANNEL4_Pos = 0x4
	// Bit mask of CHANNEL4 field.
	EVSYS_SWEVT_CHANNEL4_Msk = 0x10
	// Bit CHANNEL4.
	EVSYS_SWEVT_CHANNEL4 = 0x10
	// Position of CHANNEL5 field.
	EVSYS_SWEVT_CHANNEL5_Pos = 0x5
	// Bit mask of CHANNEL5 field.
	EVSYS_SWEVT_CHANNEL5_Msk = 0x20
	// Bit CHANNEL5.
	EVSYS_SWEVT_CHANNEL5 = 0x20
	// Position of CHANNEL6 field.
	EVSYS_SWEVT_CHANNEL6_Pos = 0x6
	// Bit mask of CHANNEL6 field.
	EVSYS_SWEVT_CHANNEL6_Msk = 0x40
	// Bit CHANNEL6.
	EVSYS_SWEVT_CHANNEL6 = 0x40
	// Position of CHANNEL7 field.
	EVSYS_SWEVT_CHANNEL7_Pos = 0x7
	// Bit mask of CHANNEL7 field.
	EVSYS_SWEVT_CHANNEL7_Msk = 0x80
	// Bit CHANNEL7.
	EVSYS_SWEVT_CHANNEL7 = 0x80
	// Position of CHANNEL8 field.
	EVSYS_SWEVT_CHANNEL8_Pos = 0x8
	// Bit mask of CHANNEL8 field.
	EVSYS_SWEVT_CHANNEL8_Msk = 0x100
	// Bit CHANNEL8.
	EVSYS_SWEVT_CHANNEL8 = 0x100
	// Position of CHANNEL9 field.
	EVSYS_SWEVT_CHANNEL9_Pos = 0x9
	// Bit mask of CHANNEL9 field.
	EVSYS_SWEVT_CHANNEL9_Msk = 0x200
	// Bit CHANNEL9.
	EVSYS_SWEVT_CHANNEL9 = 0x200
	// Position of CHANNEL10 field.
	EVSYS_SWEVT_CHANNEL10_Pos = 0xa
	// Bit mask of CHANNEL10 field.
	EVSYS_SWEVT_CHANNEL10_Msk = 0x400
	// Bit CHANNEL10.
	EVSYS_SWEVT_CHANNEL10 = 0x400
	// Position of CHANNEL11 field.
	EVSYS_SWEVT_CHANNEL11_Pos = 0xb
	// Bit mask of CHANNEL11 field.
	EVSYS_SWEVT_CHANNEL11_Msk = 0x800
	// Bit CHANNEL11.
	EVSYS_SWEVT_CHANNEL11 = 0x800
	// Position of CHANNEL12 field.
	EVSYS_SWEVT_CHANNEL12_Pos = 0xc
	// Bit mask of CHANNEL12 field.
	EVSYS_SWEVT_CHANNEL12_Msk = 0x1000
	// Bit CHANNEL12.
	EVSYS_SWEVT_CHANNEL12 = 0x1000
	// Position of CHANNEL13 field.
	EVSYS_SWEVT_CHANNEL13_Pos = 0xd
	// Bit mask of CHANNEL13 field.
	EVSYS_SWEVT_CHANNEL13_Msk = 0x2000
	// Bit CHANNEL13.
	EVSYS_SWEVT_CHANNEL13 = 0x2000
	// Position of CHANNEL14 field.
	EVSYS_SWEVT_CHANNEL14_Pos = 0xe
	// Bit mask of CHANNEL14 field.
	EVSYS_SWEVT_CHANNEL14_Msk = 0x4000
	// Bit CHANNEL14.
	EVSYS_SWEVT_CHANNEL14 = 0x4000
	// Position of CHANNEL15 field.
	EVSYS_SWEVT_CHANNEL15_Pos = 0xf
	// Bit mask of CHANNEL15 field.
	EVSYS_SWEVT_CHANNEL15_Msk = 0x8000
	// Bit CHANNEL15.
	EVSYS_SWEVT_CHANNEL15 = 0x8000
	// Position of CHANNEL16 field.
	EVSYS_SWEVT_CHANNEL16_Pos = 0x10
	// Bit mask of CHANNEL16 field.
	EVSYS_SWEVT_CHANNEL16_Msk = 0x10000
	// Bit CHANNEL16.
	EVSYS_SWEVT_CHANNEL16 = 0x10000
	// Position of CHANNEL17 field.
	EVSYS_SWEVT_CHANNEL17_Pos = 0x11
	// Bit mask of CHANNEL17 field.
	EVSYS_SWEVT_CHANNEL17_Msk = 0x20000
	// Bit CHANNEL17.
	EVSYS_SWEVT_CHANNEL17 = 0x20000
	// Position of CHANNEL18 field.
	EVSYS_SWEVT_CHANNEL18_Pos = 0x12
	// Bit mask of CHANNEL18 field.
	EVSYS_SWEVT_CHANNEL18_Msk = 0x40000
	// Bit CHANNEL18.
	EVSYS_SWEVT_CHANNEL18 = 0x40000
	// Position of CHANNEL19 field.
	EVSYS_SWEVT_CHANNEL19_Pos = 0x13
	// Bit mask of CHANNEL19 field.
	EVSYS_SWEVT_CHANNEL19_Msk = 0x80000
	// Bit CHANNEL19.
	EVSYS_SWEVT_CHANNEL19 = 0x80000
	// Position of CHANNEL20 field.
	EVSYS_SWEVT_CHANNEL20_Pos = 0x14
	// Bit mask of CHANNEL20 field.
	EVSYS_SWEVT_CHANNEL20_Msk = 0x100000
	// Bit CHANNEL20.
	EVSYS_SWEVT_CHANNEL20 = 0x100000
	// Position of CHANNEL21 field.
	EVSYS_SWEVT_CHANNEL21_Pos = 0x15
	// Bit mask of CHANNEL21 field.
	EVSYS_SWEVT_CHANNEL21_Msk = 0x200000
	// Bit CHANNEL21.
	EVSYS_SWEVT_CHANNEL21 = 0x200000
	// Position of CHANNEL22 field.
	EVSYS_SWEVT_CHANNEL22_Pos = 0x16
	// Bit mask of CHANNEL22 field.
	EVSYS_SWEVT_CHANNEL22_Msk = 0x400000
	// Bit CHANNEL22.
	EVSYS_SWEVT_CHANNEL22 = 0x400000
	// Position of CHANNEL23 field.
	EVSYS_SWEVT_CHANNEL23_Pos = 0x17
	// Bit mask of CHANNEL23 field.
	EVSYS_SWEVT_CHANNEL23_Msk = 0x800000
	// Bit CHANNEL23.
	EVSYS_SWEVT_CHANNEL23 = 0x800000
	// Position of CHANNEL24 field.
	EVSYS_SWEVT_CHANNEL24_Pos = 0x18
	// Bit mask of CHANNEL24 field.
	EVSYS_SWEVT_CHANNEL24_Msk = 0x1000000
	// Bit CHANNEL24.
	EVSYS_SWEVT_CHANNEL24 = 0x1000000
	// Position of CHANNEL25 field.
	EVSYS_SWEVT_CHANNEL25_Pos = 0x19
	// Bit mask of CHANNEL25 field.
	EVSYS_SWEVT_CHANNEL25_Msk = 0x2000000
	// Bit CHANNEL25.
	EVSYS_SWEVT_CHANNEL25 = 0x2000000
	// Position of CHANNEL26 field.
	EVSYS_SWEVT_CHANNEL26_Pos = 0x1a
	// Bit mask of CHANNEL26 field.
	EVSYS_SWEVT_CHANNEL26_Msk = 0x4000000
	// Bit CHANNEL26.
	EVSYS_SWEVT_CHANNEL26 = 0x4000000
	// Position of CHANNEL27 field.
	EVSYS_SWEVT_CHANNEL27_Pos = 0x1b
	// Bit mask of CHANNEL27 field.
	EVSYS_SWEVT_CHANNEL27_Msk = 0x8000000
	// Bit CHANNEL27.
	EVSYS_SWEVT_CHANNEL27 = 0x8000000
	// Position of CHANNEL28 field.
	EVSYS_SWEVT_CHANNEL28_Pos = 0x1c
	// Bit mask of CHANNEL28 field.
	EVSYS_SWEVT_CHANNEL28_Msk = 0x10000000
	// Bit CHANNEL28.
	EVSYS_SWEVT_CHANNEL28 = 0x10000000
	// Position of CHANNEL29 field.
	EVSYS_SWEVT_CHANNEL29_Pos = 0x1d
	// Bit mask of CHANNEL29 field.
	EVSYS_SWEVT_CHANNEL29_Msk = 0x20000000
	// Bit CHANNEL29.
	EVSYS_SWEVT_CHANNEL29 = 0x20000000
	// Position of CHANNEL30 field.
	EVSYS_SWEVT_CHANNEL30_Pos = 0x1e
	// Bit mask of CHANNEL30 field.
	EVSYS_SWEVT_CHANNEL30_Msk = 0x40000000
	// Bit CHANNEL30.
	EVSYS_SWEVT_CHANNEL30 = 0x40000000
	// Position of CHANNEL31 field.
	EVSYS_SWEVT_CHANNEL31_Pos = 0x1f
	// Bit mask of CHANNEL31 field.
	EVSYS_SWEVT_CHANNEL31_Msk = 0x80000000
	// Bit CHANNEL31.
	EVSYS_SWEVT_CHANNEL31 = 0x80000000

	// PRICTRL: Priority Control
	// Position of PRI field.
	EVSYS_PRICTRL_PRI_Pos = 0x0
	// Bit mask of PRI field.
	EVSYS_PRICTRL_PRI_Msk = 0xf
	// Position of RREN field.
	EVSYS_PRICTRL_RREN_Pos = 0x7
	// Bit mask of RREN field.
	EVSYS_PRICTRL_RREN_Msk = 0x80
	// Bit RREN.
	EVSYS_PRICTRL_RREN = 0x80

	// INTPEND: Channel Pending Interrupt
	// Position of ID field.
	EVSYS_INTPEND_ID_Pos = 0x0
	// Bit mask of ID field.
	EVSYS_INTPEND_ID_Msk = 0xf
	// Position of OVR field.
	EVSYS_INTPEND_OVR_Pos = 0x8
	// Bit mask of OVR field.
	EVSYS_INTPEND_OVR_Msk = 0x100
	// Bit OVR.
	EVSYS_INTPEND_OVR = 0x100
	// Position of EVD field.
	EVSYS_INTPEND_EVD_Pos = 0x9
	// Bit mask of EVD field.
	EVSYS_INTPEND_EVD_Msk = 0x200
	// Bit EVD.
	EVSYS_INTPEND_EVD = 0x200
	// Position of READY field.
	EVSYS_INTPEND_READY_Pos = 0xe
	// Bit mask of READY field.
	EVSYS_INTPEND_READY_Msk = 0x4000
	// Bit READY.
	EVSYS_INTPEND_READY = 0x4000
	// Position of BUSY field.
	EVSYS_INTPEND_BUSY_Pos = 0xf
	// Bit mask of BUSY field.
	EVSYS_INTPEND_BUSY_Msk = 0x8000
	// Bit BUSY.
	EVSYS_INTPEND_BUSY = 0x8000

	// INTSTATUS: Interrupt Status
	// Position of CHINT0 field.
	EVSYS_INTSTATUS_CHINT0_Pos = 0x0
	// Bit mask of CHINT0 field.
	EVSYS_INTSTATUS_CHINT0_Msk = 0x1
	// Bit CHINT0.
	EVSYS_INTSTATUS_CHINT0 = 0x1
	// Position of CHINT1 field.
	EVSYS_INTSTATUS_CHINT1_Pos = 0x1
	// Bit mask of CHINT1 field.
	EVSYS_INTSTATUS_CHINT1_Msk = 0x2
	// Bit CHINT1.
	EVSYS_INTSTATUS_CHINT1 = 0x2
	// Position of CHINT2 field.
	EVSYS_INTSTATUS_CHINT2_Pos = 0x2
	// Bit mask of CHINT2 field.
	EVSYS_INTSTATUS_CHINT2_Msk = 0x4
	// Bit CHINT2.
	EVSYS_INTSTATUS_CHINT2 = 0x4
	// Position of CHINT3 field.
	EVSYS_INTSTATUS_CHINT3_Pos = 0x3
	// Bit mask of CHINT3 field.
	EVSYS_INTSTATUS_CHINT3_Msk = 0x8
	// Bit CHINT3.
	EVSYS_INTSTATUS_CHINT3 = 0x8
	// Position of CHINT4 field.
	EVSYS_INTSTATUS_CHINT4_Pos = 0x4
	// Bit mask of CHINT4 field.
	EVSYS_INTSTATUS_CHINT4_Msk = 0x10
	// Bit CHINT4.
	EVSYS_INTSTATUS_CHINT4 = 0x10
	// Position of CHINT5 field.
	EVSYS_INTSTATUS_CHINT5_Pos = 0x5
	// Bit mask of CHINT5 field.
	EVSYS_INTSTATUS_CHINT5_Msk = 0x20
	// Bit CHINT5.
	EVSYS_INTSTATUS_CHINT5 = 0x20
	// Position of CHINT6 field.
	EVSYS_INTSTATUS_CHINT6_Pos = 0x6
	// Bit mask of CHINT6 field.
	EVSYS_INTSTATUS_CHINT6_Msk = 0x40
	// Bit CHINT6.
	EVSYS_INTSTATUS_CHINT6 = 0x40
	// Position of CHINT7 field.
	EVSYS_INTSTATUS_CHINT7_Pos = 0x7
	// Bit mask of CHINT7 field.
	EVSYS_INTSTATUS_CHINT7_Msk = 0x80
	// Bit CHINT7.
	EVSYS_INTSTATUS_CHINT7 = 0x80
	// Position of CHINT8 field.
	EVSYS_INTSTATUS_CHINT8_Pos = 0x8
	// Bit mask of CHINT8 field.
	EVSYS_INTSTATUS_CHINT8_Msk = 0x100
	// Bit CHINT8.
	EVSYS_INTSTATUS_CHINT8 = 0x100
	// Position of CHINT9 field.
	EVSYS_INTSTATUS_CHINT9_Pos = 0x9
	// Bit mask of CHINT9 field.
	EVSYS_INTSTATUS_CHINT9_Msk = 0x200
	// Bit CHINT9.
	EVSYS_INTSTATUS_CHINT9 = 0x200
	// Position of CHINT10 field.
	EVSYS_INTSTATUS_CHINT10_Pos = 0xa
	// Bit mask of CHINT10 field.
	EVSYS_INTSTATUS_CHINT10_Msk = 0x400
	// Bit CHINT10.
	EVSYS_INTSTATUS_CHINT10 = 0x400
	// Position of CHINT11 field.
	EVSYS_INTSTATUS_CHINT11_Pos = 0xb
	// Bit mask of CHINT11 field.
	EVSYS_INTSTATUS_CHINT11_Msk = 0x800
	// Bit CHINT11.
	EVSYS_INTSTATUS_CHINT11 = 0x800

	// BUSYCH: Busy Channels
	// Position of BUSYCH0 field.
	EVSYS_BUSYCH_BUSYCH0_Pos = 0x0
	// Bit mask of BUSYCH0 field.
	EVSYS_BUSYCH_BUSYCH0_Msk = 0x1
	// Bit BUSYCH0.
	EVSYS_BUSYCH_BUSYCH0 = 0x1
	// Position of BUSYCH1 field.
	EVSYS_BUSYCH_BUSYCH1_Pos = 0x1
	// Bit mask of BUSYCH1 field.
	EVSYS_BUSYCH_BUSYCH1_Msk = 0x2
	// Bit BUSYCH1.
	EVSYS_BUSYCH_BUSYCH1 = 0x2
	// Position of BUSYCH2 field.
	EVSYS_BUSYCH_BUSYCH2_Pos = 0x2
	// Bit mask of BUSYCH2 field.
	EVSYS_BUSYCH_BUSYCH2_Msk = 0x4
	// Bit BUSYCH2.
	EVSYS_BUSYCH_BUSYCH2 = 0x4
	// Position of BUSYCH3 field.
	EVSYS_BUSYCH_BUSYCH3_Pos = 0x3
	// Bit mask of BUSYCH3 field.
	EVSYS_BUSYCH_BUSYCH3_Msk = 0x8
	// Bit BUSYCH3.
	EVSYS_BUSYCH_BUSYCH3 = 0x8
	// Position of BUSYCH4 field.
	EVSYS_BUSYCH_BUSYCH4_Pos = 0x4
	// Bit mask of BUSYCH4 field.
	EVSYS_BUSYCH_BUSYCH4_Msk = 0x10
	// Bit BUSYCH4.
	EVSYS_BUSYCH_BUSYCH4 = 0x10
	// Position of BUSYCH5 field.
	EVSYS_BUSYCH_BUSYCH5_Pos = 0x5
	// Bit mask of BUSYCH5 field.
	EVSYS_BUSYCH_BUSYCH5_Msk = 0x20
	// Bit BUSYCH5.
	EVSYS_BUSYCH_BUSYCH5 = 0x20
	// Position of BUSYCH6 field.
	EVSYS_BUSYCH_BUSYCH6_Pos = 0x6
	// Bit mask of BUSYCH6 field.
	EVSYS_BUSYCH_BUSYCH6_Msk = 0x40
	// Bit BUSYCH6.
	EVSYS_BUSYCH_BUSYCH6 = 0x40
	// Position of BUSYCH7 field.
	EVSYS_BUSYCH_BUSYCH7_Pos = 0x7
	// Bit mask of BUSYCH7 field.
	EVSYS_BUSYCH_BUSYCH7_Msk = 0x80
	// Bit BUSYCH7.
	EVSYS_BUSYCH_BUSYCH7 = 0x80
	// Position of BUSYCH8 field.
	EVSYS_BUSYCH_BUSYCH8_Pos = 0x8
	// Bit mask of BUSYCH8 field.
	EVSYS_BUSYCH_BUSYCH8_Msk = 0x100
	// Bit BUSYCH8.
	EVSYS_BUSYCH_BUSYCH8 = 0x100
	// Position of BUSYCH9 field.
	EVSYS_BUSYCH_BUSYCH9_Pos = 0x9
	// Bit mask of BUSYCH9 field.
	EVSYS_BUSYCH_BUSYCH9_Msk = 0x200
	// Bit BUSYCH9.
	EVSYS_BUSYCH_BUSYCH9 = 0x200
	// Position of BUSYCH10 field.
	EVSYS_BUSYCH_BUSYCH10_Pos = 0xa
	// Bit mask of BUSYCH10 field.
	EVSYS_BUSYCH_BUSYCH10_Msk = 0x400
	// Bit BUSYCH10.
	EVSYS_BUSYCH_BUSYCH10 = 0x400
	// Position of BUSYCH11 field.
	EVSYS_BUSYCH_BUSYCH11_Pos = 0xb
	// Bit mask of BUSYCH11 field.
	EVSYS_BUSYCH_BUSYCH11_Msk = 0x800
	// Bit BUSYCH11.
	EVSYS_BUSYCH_BUSYCH11 = 0x800

	// READYUSR: Ready Users
	// Position of READYUSR0 field.
	EVSYS_READYUSR_READYUSR0_Pos = 0x0
	// Bit mask of READYUSR0 field.
	EVSYS_READYUSR_READYUSR0_Msk = 0x1
	// Bit READYUSR0.
	EVSYS_READYUSR_READYUSR0 = 0x1
	// Position of READYUSR1 field.
	EVSYS_READYUSR_READYUSR1_Pos = 0x1
	// Bit mask of READYUSR1 field.
	EVSYS_READYUSR_READYUSR1_Msk = 0x2
	// Bit READYUSR1.
	EVSYS_READYUSR_READYUSR1 = 0x2
	// Position of READYUSR2 field.
	EVSYS_READYUSR_READYUSR2_Pos = 0x2
	// Bit mask of READYUSR2 field.
	EVSYS_READYUSR_READYUSR2_Msk = 0x4
	// Bit READYUSR2.
	EVSYS_READYUSR_READYUSR2 = 0x4
	// Position of READYUSR3 field.
	EVSYS_READYUSR_READYUSR3_Pos = 0x3
	// Bit mask of READYUSR3 field.
	EVSYS_READYUSR_READYUSR3_Msk = 0x8
	// Bit READYUSR3.
	EVSYS_READYUSR_READYUSR3 = 0x8
	// Position of READYUSR4 field.
	EVSYS_READYUSR_READYUSR4_Pos = 0x4
	// Bit mask of READYUSR4 field.
	EVSYS_READYUSR_READYUSR4_Msk = 0x10
	// Bit READYUSR4.
	EVSYS_READYUSR_READYUSR4 = 0x10
	// Position of READYUSR5 field.
	EVSYS_READYUSR_READYUSR5_Pos = 0x5
	// Bit mask of READYUSR5 field.
	EVSYS_READYUSR_READYUSR5_Msk = 0x20
	// Bit READYUSR5.
	EVSYS_READYUSR_READYUSR5 = 0x20
	// Position of READYUSR6 field.
	EVSYS_READYUSR_READYUSR6_Pos = 0x6
	// Bit mask of READYUSR6 field.
	EVSYS_READYUSR_READYUSR6_Msk = 0x40
	// Bit READYUSR6.
	EVSYS_READYUSR_READYUSR6 = 0x40
	// Position of READYUSR7 field.
	EVSYS_READYUSR_READYUSR7_Pos = 0x7
	// Bit mask of READYUSR7 field.
	EVSYS_READYUSR_READYUSR7_Msk = 0x80
	// Bit READYUSR7.
	EVSYS_READYUSR_READYUSR7 = 0x80
	// Position of READYUSR8 field.
	EVSYS_READYUSR_READYUSR8_Pos = 0x8
	// Bit mask of READYUSR8 field.
	EVSYS_READYUSR_READYUSR8_Msk = 0x100
	// Bit READYUSR8.
	EVSYS_READYUSR_READYUSR8 = 0x100
	// Position of READYUSR9 field.
	EVSYS_READYUSR_READYUSR9_Pos = 0x9
	// Bit mask of READYUSR9 field.
	EVSYS_READYUSR_READYUSR9_Msk = 0x200
	// Bit READYUSR9.
	EVSYS_READYUSR_READYUSR9 = 0x200
	// Position of READYUSR10 field.
	EVSYS_READYUSR_READYUSR10_Pos = 0xa
	// Bit mask of READYUSR10 field.
	EVSYS_READYUSR_READYUSR10_Msk = 0x400
	// Bit READYUSR10.
	EVSYS_READYUSR_READYUSR10 = 0x400
	// Position of READYUSR11 field.
	EVSYS_READYUSR_READYUSR11_Pos = 0xb
	// Bit mask of READYUSR11 field.
	EVSYS_READYUSR_READYUSR11_Msk = 0x800
	// Bit READYUSR11.
	EVSYS_READYUSR_READYUSR11 = 0x800

	// CHANNEL.CHANNEL: Channel n Control
	// Position of EVGEN field.
	EVSYS_CHANNEL_CHANNEL_EVGEN_Pos = 0x0
	// Bit mask of EVGEN field.
	EVSYS_CHANNEL_CHANNEL_EVGEN_Msk = 0x7f
	// Position of PATH field.
	EVSYS_CHANNEL_CHANNEL_PATH_Pos = 0x8
	// Bit mask of PATH field.
	EVSYS_CHANNEL_CHANNEL_PATH_Msk = 0x300
	// Synchronous path
	EVSYS_CHANNEL_CHANNEL_PATH_SYNCHRONOUS = 0x0
	// Resynchronized path
	EVSYS_CHANNEL_CHANNEL_PATH_RESYNCHRONIZED = 0x1
	// Asynchronous path
	EVSYS_CHANNEL_CHANNEL_PATH_ASYNCHRONOUS = 0x2
	// Position of EDGSEL field.
	EVSYS_CHANNEL_CHANNEL_EDGSEL_Pos = 0xa
	// Bit mask of EDGSEL field.
	EVSYS_CHANNEL_CHANNEL_EDGSEL_Msk = 0xc00
	// No event output when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_NO_EVT_OUTPUT = 0x0
	// Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_RISING_EDGE = 0x1
	// Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_FALLING_EDGE = 0x2
	// Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_BOTH_EDGES = 0x3
	// Position of RUNSTDBY field.
	EVSYS_CHANNEL_CHANNEL_RUNSTDBY_Pos = 0xe
	// Bit mask of RUNSTDBY field.
	EVSYS_CHANNEL_CHANNEL_RUNSTDBY_Msk = 0x4000
	// Bit RUNSTDBY.
	EVSYS_CHANNEL_CHANNEL_RUNSTDBY = 0x4000
	// Position of ONDEMAND field.
	EVSYS_CHANNEL_CHANNEL_ONDEMAND_Pos = 0xf
	// Bit mask of ONDEMAND field.
	EVSYS_CHANNEL_CHANNEL_ONDEMAND_Msk = 0x8000
	// Bit ONDEMAND.
	EVSYS_CHANNEL_CHANNEL_ONDEMAND = 0x8000

	// CHANNEL.CHINTENCLR: Channel n Interrupt Enable Clear
	// Position of OVR field.
	EVSYS_CHANNEL_CHINTENCLR_OVR_Pos = 0x0
	// Bit mask of OVR field.
	EVSYS_CHANNEL_CHINTENCLR_OVR_Msk = 0x1
	// Bit OVR.
	EVSYS_CHANNEL_CHINTENCLR_OVR = 0x1
	// Position of EVD field.
	EVSYS_CHANNEL_CHINTENCLR_EVD_Pos = 0x1
	// Bit mask of EVD field.
	EVSYS_CHANNEL_CHINTENCLR_EVD_Msk = 0x2
	// Bit EVD.
	EVSYS_CHANNEL_CHINTENCLR_EVD = 0x2

	// CHANNEL.CHINTENSET: Channel n Interrupt Enable Set
	// Position of OVR field.
	EVSYS_CHANNEL_CHINTENSET_OVR_Pos = 0x0
	// Bit mask of OVR field.
	EVSYS_CHANNEL_CHINTENSET_OVR_Msk = 0x1
	// Bit OVR.
	EVSYS_CHANNEL_CHINTENSET_OVR = 0x1
	// Position of EVD field.
	EVSYS_CHANNEL_CHINTENSET_EVD_Pos = 0x1
	// Bit mask of EVD field.
	EVSYS_CHANNEL_CHINTENSET_EVD_Msk = 0x2
	// Bit EVD.
	EVSYS_CHANNEL_CHINTENSET_EVD = 0x2

	// CHANNEL.CHINTFLAG: Channel n Interrupt Flag Status and Clear
	// Position of OVR field.
	EVSYS_CHANNEL_CHINTFLAG_OVR_Pos = 0x0
	// Bit mask of OVR field.
	EVSYS_CHANNEL_CHINTFLAG_OVR_Msk = 0x1
	// Bit OVR.
	EVSYS_CHANNEL_CHINTFLAG_OVR = 0x1
	// Position of EVD field.
	EVSYS_CHANNEL_CHINTFLAG_EVD_Pos = 0x1
	// Bit mask of EVD field.
	EVSYS_CHANNEL_CHINTFLAG_EVD_Msk = 0x2
	// Bit EVD.
	EVSYS_CHANNEL_CHINTFLAG_EVD = 0x2

	// CHANNEL.CHSTATUS: Channel n Status
	// Position of RDYUSR field.
	EVSYS_CHANNEL_CHSTATUS_RDYUSR_Pos = 0x0
	// Bit mask of RDYUSR field.
	EVSYS_CHANNEL_CHSTATUS_RDYUSR_Msk = 0x1
	// Bit RDYUSR.
	EVSYS_CHANNEL_CHSTATUS_RDYUSR = 0x1
	// Position of BUSYCH field.
	EVSYS_CHANNEL_CHSTATUS_BUSYCH_Pos = 0x1
	// Bit mask of BUSYCH field.
	EVSYS_CHANNEL_CHSTATUS_BUSYCH_Msk = 0x2
	// Bit BUSYCH.
	EVSYS_CHANNEL_CHSTATUS_BUSYCH = 0x2

	// USER: User Multiplexer n
	// Position of CHANNEL field.
	EVSYS_USER_CHANNEL_Pos = 0x0
	// Bit mask of CHANNEL field.
	EVSYS_USER_CHANNEL_Msk = 0x3f
)

// Bitfields for FREQM: Frequency Meter
const (
	// CTRLA: Control A Register
	// Position of SWRST field.
	FREQM_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	FREQM_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	FREQM_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	FREQM_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	FREQM_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	FREQM_CTRLA_ENABLE = 0x2

	// CTRLB: Control B Register
	// Position of START field.
	FREQM_CTRLB_START_Pos = 0x0
	// Bit mask of START field.
	FREQM_CTRLB_START_Msk = 0x1
	// Bit START.
	FREQM_CTRLB_START = 0x1

	// CFGA: Config A register
	// Position of REFNUM field.
	FREQM_CFGA_REFNUM_Pos = 0x0
	// Bit mask of REFNUM field.
	FREQM_CFGA_REFNUM_Msk = 0xff

	// INTENCLR: Interrupt Enable Clear Register
	// Position of DONE field.
	FREQM_INTENCLR_DONE_Pos = 0x0
	// Bit mask of DONE field.
	FREQM_INTENCLR_DONE_Msk = 0x1
	// Bit DONE.
	FREQM_INTENCLR_DONE = 0x1

	// INTENSET: Interrupt Enable Set Register
	// Position of DONE field.
	FREQM_INTENSET_DONE_Pos = 0x0
	// Bit mask of DONE field.
	FREQM_INTENSET_DONE_Msk = 0x1
	// Bit DONE.
	FREQM_INTENSET_DONE = 0x1

	// INTFLAG: Interrupt Flag Register
	// Position of DONE field.
	FREQM_INTFLAG_DONE_Pos = 0x0
	// Bit mask of DONE field.
	FREQM_INTFLAG_DONE_Msk = 0x1
	// Bit DONE.
	FREQM_INTFLAG_DONE = 0x1

	// STATUS: Status Register
	// Position of BUSY field.
	FREQM_STATUS_BUSY_Pos = 0x0
	// Bit mask of BUSY field.
	FREQM_STATUS_BUSY_Msk = 0x1
	// Bit BUSY.
	FREQM_STATUS_BUSY = 0x1
	// Position of OVF field.
	FREQM_STATUS_OVF_Pos = 0x1
	// Bit mask of OVF field.
	FREQM_STATUS_OVF_Msk = 0x2
	// Bit OVF.
	FREQM_STATUS_OVF = 0x2

	// SYNCBUSY: Synchronization Busy Register
	// Position of SWRST field.
	FREQM_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	FREQM_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	FREQM_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	FREQM_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	FREQM_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	FREQM_SYNCBUSY_ENABLE = 0x2

	// VALUE: Count Value Register
	// Position of VALUE field.
	FREQM_VALUE_VALUE_Pos = 0x0
	// Bit mask of VALUE field.
	FREQM_VALUE_VALUE_Msk = 0xffffff
)

// Bitfields for GCLK: Generic Clock Generator
const (
	// CTRLA: Control
	// Position of SWRST field.
	GCLK_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	GCLK_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	GCLK_CTRLA_SWRST = 0x1

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	GCLK_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	GCLK_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	GCLK_SYNCBUSY_SWRST = 0x1
	// Position of GENCTRL field.
	GCLK_SYNCBUSY_GENCTRL_Pos = 0x2
	// Bit mask of GENCTRL field.
	GCLK_SYNCBUSY_GENCTRL_Msk = 0x3ffc
	// Generic clock generator 0
	GCLK_SYNCBUSY_GENCTRL_GCLK0 = 0x1
	// Generic clock generator 1
	GCLK_SYNCBUSY_GENCTRL_GCLK1 = 0x2
	// Generic clock generator 2
	GCLK_SYNCBUSY_GENCTRL_GCLK2 = 0x4
	// Generic clock generator 3
	GCLK_SYNCBUSY_GENCTRL_GCLK3 = 0x8
	// Generic clock generator 4
	GCLK_SYNCBUSY_GENCTRL_GCLK4 = 0x10
	// Generic clock generator 5
	GCLK_SYNCBUSY_GENCTRL_GCLK5 = 0x20
	// Generic clock generator 6
	GCLK_SYNCBUSY_GENCTRL_GCLK6 = 0x40
	// Generic clock generator 7
	GCLK_SYNCBUSY_GENCTRL_GCLK7 = 0x80
	// Generic clock generator 8
	GCLK_SYNCBUSY_GENCTRL_GCLK8 = 0x100
	// Generic clock generator 9
	GCLK_SYNCBUSY_GENCTRL_GCLK9 = 0x200
	// Generic clock generator 10
	GCLK_SYNCBUSY_GENCTRL_GCLK10 = 0x400
	// Generic clock generator 11
	GCLK_SYNCBUSY_GENCTRL_GCLK11 = 0x800

	// GENCTRL: Generic Clock Generator Control
	// Position of SRC field.
	GCLK_GENCTRL_SRC_Pos = 0x0
	// Bit mask of SRC field.
	GCLK_GENCTRL_SRC_Msk = 0xf
	// XOSC0 oscillator output
	GCLK_GENCTRL_SRC_XOSC0 = 0x0
	// XOSC1 oscillator output
	GCLK_GENCTRL_SRC_XOSC1 = 0x1
	// Generator input pad
	GCLK_GENCTRL_SRC_GCLKIN = 0x2
	// Generic clock generator 1 output
	GCLK_GENCTRL_SRC_GCLKGEN1 = 0x3
	// OSCULP32K oscillator output
	GCLK_GENCTRL_SRC_OSCULP32K = 0x4
	// XOSC32K oscillator output
	GCLK_GENCTRL_SRC_XOSC32K = 0x5
	// DFLL output
	GCLK_GENCTRL_SRC_DFLL = 0x6
	// DPLL0 output
	GCLK_GENCTRL_SRC_DPLL0 = 0x7
	// DPLL1 output
	GCLK_GENCTRL_SRC_DPLL1 = 0x8
	// Position of GENEN field.
	GCLK_GENCTRL_GENEN_Pos = 0x8
	// Bit mask of GENEN field.
	GCLK_GENCTRL_GENEN_Msk = 0x100
	// Bit GENEN.
	GCLK_GENCTRL_GENEN = 0x100
	// Position of IDC field.
	GCLK_GENCTRL_IDC_Pos = 0x9
	// Bit mask of IDC field.
	GCLK_GENCTRL_IDC_Msk = 0x200
	// Bit IDC.
	GCLK_GENCTRL_IDC = 0x200
	// Position of OOV field.
	GCLK_GENCTRL_OOV_Pos = 0xa
	// Bit mask of OOV field.
	GCLK_GENCTRL_OOV_Msk = 0x400
	// Bit OOV.
	GCLK_GENCTRL_OOV = 0x400
	// Position of OE field.
	GCLK_GENCTRL_OE_Pos = 0xb
	// Bit mask of OE field.
	GCLK_GENCTRL_OE_Msk = 0x800
	// Bit OE.
	GCLK_GENCTRL_OE = 0x800
	// Position of DIVSEL field.
	GCLK_GENCTRL_DIVSEL_Pos = 0xc
	// Bit mask of DIVSEL field.
	GCLK_GENCTRL_DIVSEL_Msk = 0x1000
	// Bit DIVSEL.
	GCLK_GENCTRL_DIVSEL = 0x1000
	// Divide input directly by divider factor
	GCLK_GENCTRL_DIVSEL_DIV1 = 0x0
	// Divide input by 2^(divider factor+ 1)
	GCLK_GENCTRL_DIVSEL_DIV2 = 0x1
	// Position of RUNSTDBY field.
	GCLK_GENCTRL_RUNSTDBY_Pos = 0xd
	// Bit mask of RUNSTDBY field.
	GCLK_GENCTRL_RUNSTDBY_Msk = 0x2000
	// Bit RUNSTDBY.
	GCLK_GENCTRL_RUNSTDBY = 0x2000
	// Position of DIV field.
	GCLK_GENCTRL_DIV_Pos = 0x10
	// Bit mask of DIV field.
	GCLK_GENCTRL_DIV_Msk = 0xffff0000

	// PCHCTRL: Peripheral Clock Control
	// Position of GEN field.
	GCLK_PCHCTRL_GEN_Pos = 0x0
	// Bit mask of GEN field.
	GCLK_PCHCTRL_GEN_Msk = 0xf
	// Generic clock generator 0
	GCLK_PCHCTRL_GEN_GCLK0 = 0x0
	// Generic clock generator 1
	GCLK_PCHCTRL_GEN_GCLK1 = 0x1
	// Generic clock generator 2
	GCLK_PCHCTRL_GEN_GCLK2 = 0x2
	// Generic clock generator 3
	GCLK_PCHCTRL_GEN_GCLK3 = 0x3
	// Generic clock generator 4
	GCLK_PCHCTRL_GEN_GCLK4 = 0x4
	// Generic clock generator 5
	GCLK_PCHCTRL_GEN_GCLK5 = 0x5
	// Generic clock generator 6
	GCLK_PCHCTRL_GEN_GCLK6 = 0x6
	// Generic clock generator 7
	GCLK_PCHCTRL_GEN_GCLK7 = 0x7
	// Generic clock generator 8
	GCLK_PCHCTRL_GEN_GCLK8 = 0x8
	// Generic clock generator 9
	GCLK_PCHCTRL_GEN_GCLK9 = 0x9
	// Generic clock generator 10
	GCLK_PCHCTRL_GEN_GCLK10 = 0xa
	// Generic clock generator 11
	GCLK_PCHCTRL_GEN_GCLK11 = 0xb
	// Position of CHEN field.
	GCLK_PCHCTRL_CHEN_Pos = 0x6
	// Bit mask of CHEN field.
	GCLK_PCHCTRL_CHEN_Msk = 0x40
	// Bit CHEN.
	GCLK_PCHCTRL_CHEN = 0x40
	// Position of WRTLOCK field.
	GCLK_PCHCTRL_WRTLOCK_Pos = 0x7
	// Bit mask of WRTLOCK field.
	GCLK_PCHCTRL_WRTLOCK_Msk = 0x80
	// Bit WRTLOCK.
	GCLK_PCHCTRL_WRTLOCK = 0x80
)

// Bitfields for GMAC: Ethernet MAC
const (
	// NCR: Network Control Register
	// Position of LBL field.
	GMAC_NCR_LBL_Pos = 0x1
	// Bit mask of LBL field.
	GMAC_NCR_LBL_Msk = 0x2
	// Bit LBL.
	GMAC_NCR_LBL = 0x2
	// Position of RXEN field.
	GMAC_NCR_RXEN_Pos = 0x2
	// Bit mask of RXEN field.
	GMAC_NCR_RXEN_Msk = 0x4
	// Bit RXEN.
	GMAC_NCR_RXEN = 0x4
	// Position of TXEN field.
	GMAC_NCR_TXEN_Pos = 0x3
	// Bit mask of TXEN field.
	GMAC_NCR_TXEN_Msk = 0x8
	// Bit TXEN.
	GMAC_NCR_TXEN = 0x8
	// Position of MPE field.
	GMAC_NCR_MPE_Pos = 0x4
	// Bit mask of MPE field.
	GMAC_NCR_MPE_Msk = 0x10
	// Bit MPE.
	GMAC_NCR_MPE = 0x10
	// Position of CLRSTAT field.
	GMAC_NCR_CLRSTAT_Pos = 0x5
	// Bit mask of CLRSTAT field.
	GMAC_NCR_CLRSTAT_Msk = 0x20
	// Bit CLRSTAT.
	GMAC_NCR_CLRSTAT = 0x20
	// Position of INCSTAT field.
	GMAC_NCR_INCSTAT_Pos = 0x6
	// Bit mask of INCSTAT field.
	GMAC_NCR_INCSTAT_Msk = 0x40
	// Bit INCSTAT.
	GMAC_NCR_INCSTAT = 0x40
	// Position of WESTAT field.
	GMAC_NCR_WESTAT_Pos = 0x7
	// Bit mask of WESTAT field.
	GMAC_NCR_WESTAT_Msk = 0x80
	// Bit WESTAT.
	GMAC_NCR_WESTAT = 0x80
	// Position of BP field.
	GMAC_NCR_BP_Pos = 0x8
	// Bit mask of BP field.
	GMAC_NCR_BP_Msk = 0x100
	// Bit BP.
	GMAC_NCR_BP = 0x100
	// Position of TSTART field.
	GMAC_NCR_TSTART_Pos = 0x9
	// Bit mask of TSTART field.
	GMAC_NCR_TSTART_Msk = 0x200
	// Bit TSTART.
	GMAC_NCR_TSTART = 0x200
	// Position of THALT field.
	GMAC_NCR_THALT_Pos = 0xa
	// Bit mask of THALT field.
	GMAC_NCR_THALT_Msk = 0x400
	// Bit THALT.
	GMAC_NCR_THALT = 0x400
	// Position of TXPF field.
	GMAC_NCR_TXPF_Pos = 0xb
	// Bit mask of TXPF field.
	GMAC_NCR_TXPF_Msk = 0x800
	// Bit TXPF.
	GMAC_NCR_TXPF = 0x800
	// Position of TXZQPF field.
	GMAC_NCR_TXZQPF_Pos = 0xc
	// Bit mask of TXZQPF field.
	GMAC_NCR_TXZQPF_Msk = 0x1000
	// Bit TXZQPF.
	GMAC_NCR_TXZQPF = 0x1000
	// Position of SRTSM field.
	GMAC_NCR_SRTSM_Pos = 0xf
	// Bit mask of SRTSM field.
	GMAC_NCR_SRTSM_Msk = 0x8000
	// Bit SRTSM.
	GMAC_NCR_SRTSM = 0x8000
	// Position of ENPBPR field.
	GMAC_NCR_ENPBPR_Pos = 0x10
	// Bit mask of ENPBPR field.
	GMAC_NCR_ENPBPR_Msk = 0x10000
	// Bit ENPBPR.
	GMAC_NCR_ENPBPR = 0x10000
	// Position of TXPBPF field.
	GMAC_NCR_TXPBPF_Pos = 0x11
	// Bit mask of TXPBPF field.
	GMAC_NCR_TXPBPF_Msk = 0x20000
	// Bit TXPBPF.
	GMAC_NCR_TXPBPF = 0x20000
	// Position of FNP field.
	GMAC_NCR_FNP_Pos = 0x12
	// Bit mask of FNP field.
	GMAC_NCR_FNP_Msk = 0x40000
	// Bit FNP.
	GMAC_NCR_FNP = 0x40000
	// Position of LPI field.
	GMAC_NCR_LPI_Pos = 0x13
	// Bit mask of LPI field.
	GMAC_NCR_LPI_Msk = 0x80000
	// Bit LPI.
	GMAC_NCR_LPI = 0x80000

	// NCFGR: Network Configuration Register
	// Position of SPD field.
	GMAC_NCFGR_SPD_Pos = 0x0
	// Bit mask of SPD field.
	GMAC_NCFGR_SPD_Msk = 0x1
	// Bit SPD.
	GMAC_NCFGR_SPD = 0x1
	// Position of FD field.
	GMAC_NCFGR_FD_Pos = 0x1
	// Bit mask of FD field.
	GMAC_NCFGR_FD_Msk = 0x2
	// Bit FD.
	GMAC_NCFGR_FD = 0x2
	// Position of DNVLAN field.
	GMAC_NCFGR_DNVLAN_Pos = 0x2
	// Bit mask of DNVLAN field.
	GMAC_NCFGR_DNVLAN_Msk = 0x4
	// Bit DNVLAN.
	GMAC_NCFGR_DNVLAN = 0x4
	// Position of JFRAME field.
	GMAC_NCFGR_JFRAME_Pos = 0x3
	// Bit mask of JFRAME field.
	GMAC_NCFGR_JFRAME_Msk = 0x8
	// Bit JFRAME.
	GMAC_NCFGR_JFRAME = 0x8
	// Position of CAF field.
	GMAC_NCFGR_CAF_Pos = 0x4
	// Bit mask of CAF field.
	GMAC_NCFGR_CAF_Msk = 0x10
	// Bit CAF.
	GMAC_NCFGR_CAF = 0x10
	// Position of NBC field.
	GMAC_NCFGR_NBC_Pos = 0x5
	// Bit mask of NBC field.
	GMAC_NCFGR_NBC_Msk = 0x20
	// Bit NBC.
	GMAC_NCFGR_NBC = 0x20
	// Position of MTIHEN field.
	GMAC_NCFGR_MTIHEN_Pos = 0x6
	// Bit mask of MTIHEN field.
	GMAC_NCFGR_MTIHEN_Msk = 0x40
	// Bit MTIHEN.
	GMAC_NCFGR_MTIHEN = 0x40
	// Position of UNIHEN field.
	GMAC_NCFGR_UNIHEN_Pos = 0x7
	// Bit mask of UNIHEN field.
	GMAC_NCFGR_UNIHEN_Msk = 0x80
	// Bit UNIHEN.
	GMAC_NCFGR_UNIHEN = 0x80
	// Position of MAXFS field.
	GMAC_NCFGR_MAXFS_Pos = 0x8
	// Bit mask of MAXFS field.
	GMAC_NCFGR_MAXFS_Msk = 0x100
	// Bit MAXFS.
	GMAC_NCFGR_MAXFS = 0x100
	// Position of RTY field.
	GMAC_NCFGR_RTY_Pos = 0xc
	// Bit mask of RTY field.
	GMAC_NCFGR_RTY_Msk = 0x1000
	// Bit RTY.
	GMAC_NCFGR_RTY = 0x1000
	// Position of PEN field.
	GMAC_NCFGR_PEN_Pos = 0xd
	// Bit mask of PEN field.
	GMAC_NCFGR_PEN_Msk = 0x2000
	// Bit PEN.
	GMAC_NCFGR_PEN = 0x2000
	// Position of RXBUFO field.
	GMAC_NCFGR_RXBUFO_Pos = 0xe
	// Bit mask of RXBUFO field.
	GMAC_NCFGR_RXBUFO_Msk = 0xc000
	// Position of LFERD field.
	GMAC_NCFGR_LFERD_Pos = 0x10
	// Bit mask of LFERD field.
	GMAC_NCFGR_LFERD_Msk = 0x10000
	// Bit LFERD.
	GMAC_NCFGR_LFERD = 0x10000
	// Position of RFCS field.
	GMAC_NCFGR_RFCS_Pos = 0x11
	// Bit mask of RFCS field.
	GMAC_NCFGR_RFCS_Msk = 0x20000
	// Bit RFCS.
	GMAC_NCFGR_RFCS = 0x20000
	// Position of CLK field.
	GMAC_NCFGR_CLK_Pos = 0x12
	// Bit mask of CLK field.
	GMAC_NCFGR_CLK_Msk = 0x1c0000
	// Position of DBW field.
	GMAC_NCFGR_DBW_Pos = 0x15
	// Bit mask of DBW field.
	GMAC_NCFGR_DBW_Msk = 0x600000
	// Position of DCPF field.
	GMAC_NCFGR_DCPF_Pos = 0x17
	// Bit mask of DCPF field.
	GMAC_NCFGR_DCPF_Msk = 0x800000
	// Bit DCPF.
	GMAC_NCFGR_DCPF = 0x800000
	// Position of RXCOEN field.
	GMAC_NCFGR_RXCOEN_Pos = 0x18
	// Bit mask of RXCOEN field.
	GMAC_NCFGR_RXCOEN_Msk = 0x1000000
	// Bit RXCOEN.
	GMAC_NCFGR_RXCOEN = 0x1000000
	// Position of EFRHD field.
	GMAC_NCFGR_EFRHD_Pos = 0x19
	// Bit mask of EFRHD field.
	GMAC_NCFGR_EFRHD_Msk = 0x2000000
	// Bit EFRHD.
	GMAC_NCFGR_EFRHD = 0x2000000
	// Position of IRXFCS field.
	GMAC_NCFGR_IRXFCS_Pos = 0x1a
	// Bit mask of IRXFCS field.
	GMAC_NCFGR_IRXFCS_Msk = 0x4000000
	// Bit IRXFCS.
	GMAC_NCFGR_IRXFCS = 0x4000000
	// Position of IPGSEN field.
	GMAC_NCFGR_IPGSEN_Pos = 0x1c
	// Bit mask of IPGSEN field.
	GMAC_NCFGR_IPGSEN_Msk = 0x10000000
	// Bit IPGSEN.
	GMAC_NCFGR_IPGSEN = 0x10000000
	// Position of RXBP field.
	GMAC_NCFGR_RXBP_Pos = 0x1d
	// Bit mask of RXBP field.
	GMAC_NCFGR_RXBP_Msk = 0x20000000
	// Bit RXBP.
	GMAC_NCFGR_RXBP = 0x20000000
	// Position of IRXER field.
	GMAC_NCFGR_IRXER_Pos = 0x1e
	// Bit mask of IRXER field.
	GMAC_NCFGR_IRXER_Msk = 0x40000000
	// Bit IRXER.
	GMAC_NCFGR_IRXER = 0x40000000

	// NSR: Network Status Register
	// Position of MDIO field.
	GMAC_NSR_MDIO_Pos = 0x1
	// Bit mask of MDIO field.
	GMAC_NSR_MDIO_Msk = 0x2
	// Bit MDIO.
	GMAC_NSR_MDIO = 0x2
	// Position of IDLE field.
	GMAC_NSR_IDLE_Pos = 0x2
	// Bit mask of IDLE field.
	GMAC_NSR_IDLE_Msk = 0x4
	// Bit IDLE.
	GMAC_NSR_IDLE = 0x4

	// UR: User Register
	// Position of MII field.
	GMAC_UR_MII_Pos = 0x0
	// Bit mask of MII field.
	GMAC_UR_MII_Msk = 0x1
	// Bit MII.
	GMAC_UR_MII = 0x1

	// DCFGR: DMA Configuration Register
	// Position of FBLDO field.
	GMAC_DCFGR_FBLDO_Pos = 0x0
	// Bit mask of FBLDO field.
	GMAC_DCFGR_FBLDO_Msk = 0x1f
	// Position of ESMA field.
	GMAC_DCFGR_ESMA_Pos = 0x6
	// Bit mask of ESMA field.
	GMAC_DCFGR_ESMA_Msk = 0x40
	// Bit ESMA.
	GMAC_DCFGR_ESMA = 0x40
	// Position of ESPA field.
	GMAC_DCFGR_ESPA_Pos = 0x7
	// Bit mask of ESPA field.
	GMAC_DCFGR_ESPA_Msk = 0x80
	// Bit ESPA.
	GMAC_DCFGR_ESPA = 0x80
	// Position of RXBMS field.
	GMAC_DCFGR_RXBMS_Pos = 0x8
	// Bit mask of RXBMS field.
	GMAC_DCFGR_RXBMS_Msk = 0x300
	// Position of TXPBMS field.
	GMAC_DCFGR_TXPBMS_Pos = 0xa
	// Bit mask of TXPBMS field.
	GMAC_DCFGR_TXPBMS_Msk = 0x400
	// Bit TXPBMS.
	GMAC_DCFGR_TXPBMS = 0x400
	// Position of TXCOEN field.
	GMAC_DCFGR_TXCOEN_Pos = 0xb
	// Bit mask of TXCOEN field.
	GMAC_DCFGR_TXCOEN_Msk = 0x800
	// Bit TXCOEN.
	GMAC_DCFGR_TXCOEN = 0x800
	// Position of DRBS field.
	GMAC_DCFGR_DRBS_Pos = 0x10
	// Bit mask of DRBS field.
	GMAC_DCFGR_DRBS_Msk = 0xff0000
	// Position of DDRP field.
	GMAC_DCFGR_DDRP_Pos = 0x18
	// Bit mask of DDRP field.
	GMAC_DCFGR_DDRP_Msk = 0x1000000
	// Bit DDRP.
	GMAC_DCFGR_DDRP = 0x1000000

	// TSR: Transmit Status Register
	// Position of UBR field.
	GMAC_TSR_UBR_Pos = 0x0
	// Bit mask of UBR field.
	GMAC_TSR_UBR_Msk = 0x1
	// Bit UBR.
	GMAC_TSR_UBR = 0x1
	// Position of COL field.
	GMAC_TSR_COL_Pos = 0x1
	// Bit mask of COL field.
	GMAC_TSR_COL_Msk = 0x2
	// Bit COL.
	GMAC_TSR_COL = 0x2
	// Position of RLE field.
	GMAC_TSR_RLE_Pos = 0x2
	// Bit mask of RLE field.
	GMAC_TSR_RLE_Msk = 0x4
	// Bit RLE.
	GMAC_TSR_RLE = 0x4
	// Position of TXGO field.
	GMAC_TSR_TXGO_Pos = 0x3
	// Bit mask of TXGO field.
	GMAC_TSR_TXGO_Msk = 0x8
	// Bit TXGO.
	GMAC_TSR_TXGO = 0x8
	// Position of TFC field.
	GMAC_TSR_TFC_Pos = 0x4
	// Bit mask of TFC field.
	GMAC_TSR_TFC_Msk = 0x10
	// Bit TFC.
	GMAC_TSR_TFC = 0x10
	// Position of TXCOMP field.
	GMAC_TSR_TXCOMP_Pos = 0x5
	// Bit mask of TXCOMP field.
	GMAC_TSR_TXCOMP_Msk = 0x20
	// Bit TXCOMP.
	GMAC_TSR_TXCOMP = 0x20
	// Position of UND field.
	GMAC_TSR_UND_Pos = 0x6
	// Bit mask of UND field.
	GMAC_TSR_UND_Msk = 0x40
	// Bit UND.
	GMAC_TSR_UND = 0x40
	// Position of HRESP field.
	GMAC_TSR_HRESP_Pos = 0x8
	// Bit mask of HRESP field.
	GMAC_TSR_HRESP_Msk = 0x100
	// Bit HRESP.
	GMAC_TSR_HRESP = 0x100

	// RBQB: Receive Buffer Queue Base Address
	// Position of ADDR field.
	GMAC_RBQB_ADDR_Pos = 0x2
	// Bit mask of ADDR field.
	GMAC_RBQB_ADDR_Msk = 0xfffffffc

	// TBQB: Transmit Buffer Queue Base Address
	// Position of ADDR field.
	GMAC_TBQB_ADDR_Pos = 0x2
	// Bit mask of ADDR field.
	GMAC_TBQB_ADDR_Msk = 0xfffffffc

	// RSR: Receive Status Register
	// Position of BNA field.
	GMAC_RSR_BNA_Pos = 0x0
	// Bit mask of BNA field.
	GMAC_RSR_BNA_Msk = 0x1
	// Bit BNA.
	GMAC_RSR_BNA = 0x1
	// Position of REC field.
	GMAC_RSR_REC_Pos = 0x1
	// Bit mask of REC field.
	GMAC_RSR_REC_Msk = 0x2
	// Bit REC.
	GMAC_RSR_REC = 0x2
	// Position of RXOVR field.
	GMAC_RSR_RXOVR_Pos = 0x2
	// Bit mask of RXOVR field.
	GMAC_RSR_RXOVR_Msk = 0x4
	// Bit RXOVR.
	GMAC_RSR_RXOVR = 0x4
	// Position of HNO field.
	GMAC_RSR_HNO_Pos = 0x3
	// Bit mask of HNO field.
	GMAC_RSR_HNO_Msk = 0x8
	// Bit HNO.
	GMAC_RSR_HNO = 0x8

	// ISR: Interrupt Status Register
	// Position of MFS field.
	GMAC_ISR_MFS_Pos = 0x0
	// Bit mask of MFS field.
	GMAC_ISR_MFS_Msk = 0x1
	// Bit MFS.
	GMAC_ISR_MFS = 0x1
	// Position of RCOMP field.
	GMAC_ISR_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	GMAC_ISR_RCOMP_Msk = 0x2
	// Bit RCOMP.
	GMAC_ISR_RCOMP = 0x2
	// Position of RXUBR field.
	GMAC_ISR_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	GMAC_ISR_RXUBR_Msk = 0x4
	// Bit RXUBR.
	GMAC_ISR_RXUBR = 0x4
	// Position of TXUBR field.
	GMAC_ISR_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	GMAC_ISR_TXUBR_Msk = 0x8
	// Bit TXUBR.
	GMAC_ISR_TXUBR = 0x8
	// Position of TUR field.
	GMAC_ISR_TUR_Pos = 0x4
	// Bit mask of TUR field.
	GMAC_ISR_TUR_Msk = 0x10
	// Bit TUR.
	GMAC_ISR_TUR = 0x10
	// Position of RLEX field.
	GMAC_ISR_RLEX_Pos = 0x5
	// Bit mask of RLEX field.
	GMAC_ISR_RLEX_Msk = 0x20
	// Bit RLEX.
	GMAC_ISR_RLEX = 0x20
	// Position of TFC field.
	GMAC_ISR_TFC_Pos = 0x6
	// Bit mask of TFC field.
	GMAC_ISR_TFC_Msk = 0x40
	// Bit TFC.
	GMAC_ISR_TFC = 0x40
	// Position of TCOMP field.
	GMAC_ISR_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	GMAC_ISR_TCOMP_Msk = 0x80
	// Bit TCOMP.
	GMAC_ISR_TCOMP = 0x80
	// Position of ROVR field.
	GMAC_ISR_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	GMAC_ISR_ROVR_Msk = 0x400
	// Bit ROVR.
	GMAC_ISR_ROVR = 0x400
	// Position of HRESP field.
	GMAC_ISR_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	GMAC_ISR_HRESP_Msk = 0x800
	// Bit HRESP.
	GMAC_ISR_HRESP = 0x800
	// Position of PFNZ field.
	GMAC_ISR_PFNZ_Pos = 0xc
	// Bit mask of PFNZ field.
	GMAC_ISR_PFNZ_Msk = 0x1000
	// Bit PFNZ.
	GMAC_ISR_PFNZ = 0x1000
	// Position of PTZ field.
	GMAC_ISR_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	GMAC_ISR_PTZ_Msk = 0x2000
	// Bit PTZ.
	GMAC_ISR_PTZ = 0x2000
	// Position of PFTR field.
	GMAC_ISR_PFTR_Pos = 0xe
	// Bit mask of PFTR field.
	GMAC_ISR_PFTR_Msk = 0x4000
	// Bit PFTR.
	GMAC_ISR_PFTR = 0x4000
	// Position of DRQFR field.
	GMAC_ISR_DRQFR_Pos = 0x12
	// Bit mask of DRQFR field.
	GMAC_ISR_DRQFR_Msk = 0x40000
	// Bit DRQFR.
	GMAC_ISR_DRQFR = 0x40000
	// Position of SFR field.
	GMAC_ISR_SFR_Pos = 0x13
	// Bit mask of SFR field.
	GMAC_ISR_SFR_Msk = 0x80000
	// Bit SFR.
	GMAC_ISR_SFR = 0x80000
	// Position of DRQFT field.
	GMAC_ISR_DRQFT_Pos = 0x14
	// Bit mask of DRQFT field.
	GMAC_ISR_DRQFT_Msk = 0x100000
	// Bit DRQFT.
	GMAC_ISR_DRQFT = 0x100000
	// Position of SFT field.
	GMAC_ISR_SFT_Pos = 0x15
	// Bit mask of SFT field.
	GMAC_ISR_SFT_Msk = 0x200000
	// Bit SFT.
	GMAC_ISR_SFT = 0x200000
	// Position of PDRQFR field.
	GMAC_ISR_PDRQFR_Pos = 0x16
	// Bit mask of PDRQFR field.
	GMAC_ISR_PDRQFR_Msk = 0x400000
	// Bit PDRQFR.
	GMAC_ISR_PDRQFR = 0x400000
	// Position of PDRSFR field.
	GMAC_ISR_PDRSFR_Pos = 0x17
	// Bit mask of PDRSFR field.
	GMAC_ISR_PDRSFR_Msk = 0x800000
	// Bit PDRSFR.
	GMAC_ISR_PDRSFR = 0x800000
	// Position of PDRQFT field.
	GMAC_ISR_PDRQFT_Pos = 0x18
	// Bit mask of PDRQFT field.
	GMAC_ISR_PDRQFT_Msk = 0x1000000
	// Bit PDRQFT.
	GMAC_ISR_PDRQFT = 0x1000000
	// Position of PDRSFT field.
	GMAC_ISR_PDRSFT_Pos = 0x19
	// Bit mask of PDRSFT field.
	GMAC_ISR_PDRSFT_Msk = 0x2000000
	// Bit PDRSFT.
	GMAC_ISR_PDRSFT = 0x2000000
	// Position of SRI field.
	GMAC_ISR_SRI_Pos = 0x1a
	// Bit mask of SRI field.
	GMAC_ISR_SRI_Msk = 0x4000000
	// Bit SRI.
	GMAC_ISR_SRI = 0x4000000
	// Position of WOL field.
	GMAC_ISR_WOL_Pos = 0x1c
	// Bit mask of WOL field.
	GMAC_ISR_WOL_Msk = 0x10000000
	// Bit WOL.
	GMAC_ISR_WOL = 0x10000000
	// Position of TSUCMP field.
	GMAC_ISR_TSUCMP_Pos = 0x1d
	// Bit mask of TSUCMP field.
	GMAC_ISR_TSUCMP_Msk = 0x20000000
	// Bit TSUCMP.
	GMAC_ISR_TSUCMP = 0x20000000

	// IER: Interrupt Enable Register
	// Position of MFS field.
	GMAC_IER_MFS_Pos = 0x0
	// Bit mask of MFS field.
	GMAC_IER_MFS_Msk = 0x1
	// Bit MFS.
	GMAC_IER_MFS = 0x1
	// Position of RCOMP field.
	GMAC_IER_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	GMAC_IER_RCOMP_Msk = 0x2
	// Bit RCOMP.
	GMAC_IER_RCOMP = 0x2
	// Position of RXUBR field.
	GMAC_IER_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	GMAC_IER_RXUBR_Msk = 0x4
	// Bit RXUBR.
	GMAC_IER_RXUBR = 0x4
	// Position of TXUBR field.
	GMAC_IER_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	GMAC_IER_TXUBR_Msk = 0x8
	// Bit TXUBR.
	GMAC_IER_TXUBR = 0x8
	// Position of TUR field.
	GMAC_IER_TUR_Pos = 0x4
	// Bit mask of TUR field.
	GMAC_IER_TUR_Msk = 0x10
	// Bit TUR.
	GMAC_IER_TUR = 0x10
	// Position of RLEX field.
	GMAC_IER_RLEX_Pos = 0x5
	// Bit mask of RLEX field.
	GMAC_IER_RLEX_Msk = 0x20
	// Bit RLEX.
	GMAC_IER_RLEX = 0x20
	// Position of TFC field.
	GMAC_IER_TFC_Pos = 0x6
	// Bit mask of TFC field.
	GMAC_IER_TFC_Msk = 0x40
	// Bit TFC.
	GMAC_IER_TFC = 0x40
	// Position of TCOMP field.
	GMAC_IER_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	GMAC_IER_TCOMP_Msk = 0x80
	// Bit TCOMP.
	GMAC_IER_TCOMP = 0x80
	// Position of ROVR field.
	GMAC_IER_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	GMAC_IER_ROVR_Msk = 0x400
	// Bit ROVR.
	GMAC_IER_ROVR = 0x400
	// Position of HRESP field.
	GMAC_IER_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	GMAC_IER_HRESP_Msk = 0x800
	// Bit HRESP.
	GMAC_IER_HRESP = 0x800
	// Position of PFNZ field.
	GMAC_IER_PFNZ_Pos = 0xc
	// Bit mask of PFNZ field.
	GMAC_IER_PFNZ_Msk = 0x1000
	// Bit PFNZ.
	GMAC_IER_PFNZ = 0x1000
	// Position of PTZ field.
	GMAC_IER_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	GMAC_IER_PTZ_Msk = 0x2000
	// Bit PTZ.
	GMAC_IER_PTZ = 0x2000
	// Position of PFTR field.
	GMAC_IER_PFTR_Pos = 0xe
	// Bit mask of PFTR field.
	GMAC_IER_PFTR_Msk = 0x4000
	// Bit PFTR.
	GMAC_IER_PFTR = 0x4000
	// Position of EXINT field.
	GMAC_IER_EXINT_Pos = 0xf
	// Bit mask of EXINT field.
	GMAC_IER_EXINT_Msk = 0x8000
	// Bit EXINT.
	GMAC_IER_EXINT = 0x8000
	// Position of DRQFR field.
	GMAC_IER_DRQFR_Pos = 0x12
	// Bit mask of DRQFR field.
	GMAC_IER_DRQFR_Msk = 0x40000
	// Bit DRQFR.
	GMAC_IER_DRQFR = 0x40000
	// Position of SFR field.
	GMAC_IER_SFR_Pos = 0x13
	// Bit mask of SFR field.
	GMAC_IER_SFR_Msk = 0x80000
	// Bit SFR.
	GMAC_IER_SFR = 0x80000
	// Position of DRQFT field.
	GMAC_IER_DRQFT_Pos = 0x14
	// Bit mask of DRQFT field.
	GMAC_IER_DRQFT_Msk = 0x100000
	// Bit DRQFT.
	GMAC_IER_DRQFT = 0x100000
	// Position of SFT field.
	GMAC_IER_SFT_Pos = 0x15
	// Bit mask of SFT field.
	GMAC_IER_SFT_Msk = 0x200000
	// Bit SFT.
	GMAC_IER_SFT = 0x200000
	// Position of PDRQFR field.
	GMAC_IER_PDRQFR_Pos = 0x16
	// Bit mask of PDRQFR field.
	GMAC_IER_PDRQFR_Msk = 0x400000
	// Bit PDRQFR.
	GMAC_IER_PDRQFR = 0x400000
	// Position of PDRSFR field.
	GMAC_IER_PDRSFR_Pos = 0x17
	// Bit mask of PDRSFR field.
	GMAC_IER_PDRSFR_Msk = 0x800000
	// Bit PDRSFR.
	GMAC_IER_PDRSFR = 0x800000
	// Position of PDRQFT field.
	GMAC_IER_PDRQFT_Pos = 0x18
	// Bit mask of PDRQFT field.
	GMAC_IER_PDRQFT_Msk = 0x1000000
	// Bit PDRQFT.
	GMAC_IER_PDRQFT = 0x1000000
	// Position of PDRSFT field.
	GMAC_IER_PDRSFT_Pos = 0x19
	// Bit mask of PDRSFT field.
	GMAC_IER_PDRSFT_Msk = 0x2000000
	// Bit PDRSFT.
	GMAC_IER_PDRSFT = 0x2000000
	// Position of SRI field.
	GMAC_IER_SRI_Pos = 0x1a
	// Bit mask of SRI field.
	GMAC_IER_SRI_Msk = 0x4000000
	// Bit SRI.
	GMAC_IER_SRI = 0x4000000
	// Position of WOL field.
	GMAC_IER_WOL_Pos = 0x1c
	// Bit mask of WOL field.
	GMAC_IER_WOL_Msk = 0x10000000
	// Bit WOL.
	GMAC_IER_WOL = 0x10000000
	// Position of TSUCMP field.
	GMAC_IER_TSUCMP_Pos = 0x1d
	// Bit mask of TSUCMP field.
	GMAC_IER_TSUCMP_Msk = 0x20000000
	// Bit TSUCMP.
	GMAC_IER_TSUCMP = 0x20000000

	// IDR: Interrupt Disable Register
	// Position of MFS field.
	GMAC_IDR_MFS_Pos = 0x0
	// Bit mask of MFS field.
	GMAC_IDR_MFS_Msk = 0x1
	// Bit MFS.
	GMAC_IDR_MFS = 0x1
	// Position of RCOMP field.
	GMAC_IDR_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	GMAC_IDR_RCOMP_Msk = 0x2
	// Bit RCOMP.
	GMAC_IDR_RCOMP = 0x2
	// Position of RXUBR field.
	GMAC_IDR_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	GMAC_IDR_RXUBR_Msk = 0x4
	// Bit RXUBR.
	GMAC_IDR_RXUBR = 0x4
	// Position of TXUBR field.
	GMAC_IDR_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	GMAC_IDR_TXUBR_Msk = 0x8
	// Bit TXUBR.
	GMAC_IDR_TXUBR = 0x8
	// Position of TUR field.
	GMAC_IDR_TUR_Pos = 0x4
	// Bit mask of TUR field.
	GMAC_IDR_TUR_Msk = 0x10
	// Bit TUR.
	GMAC_IDR_TUR = 0x10
	// Position of RLEX field.
	GMAC_IDR_RLEX_Pos = 0x5
	// Bit mask of RLEX field.
	GMAC_IDR_RLEX_Msk = 0x20
	// Bit RLEX.
	GMAC_IDR_RLEX = 0x20
	// Position of TFC field.
	GMAC_IDR_TFC_Pos = 0x6
	// Bit mask of TFC field.
	GMAC_IDR_TFC_Msk = 0x40
	// Bit TFC.
	GMAC_IDR_TFC = 0x40
	// Position of TCOMP field.
	GMAC_IDR_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	GMAC_IDR_TCOMP_Msk = 0x80
	// Bit TCOMP.
	GMAC_IDR_TCOMP = 0x80
	// Position of ROVR field.
	GMAC_IDR_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	GMAC_IDR_ROVR_Msk = 0x400
	// Bit ROVR.
	GMAC_IDR_ROVR = 0x400
	// Position of HRESP field.
	GMAC_IDR_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	GMAC_IDR_HRESP_Msk = 0x800
	// Bit HRESP.
	GMAC_IDR_HRESP = 0x800
	// Position of PFNZ field.
	GMAC_IDR_PFNZ_Pos = 0xc
	// Bit mask of PFNZ field.
	GMAC_IDR_PFNZ_Msk = 0x1000
	// Bit PFNZ.
	GMAC_IDR_PFNZ = 0x1000
	// Position of PTZ field.
	GMAC_IDR_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	GMAC_IDR_PTZ_Msk = 0x2000
	// Bit PTZ.
	GMAC_IDR_PTZ = 0x2000
	// Position of PFTR field.
	GMAC_IDR_PFTR_Pos = 0xe
	// Bit mask of PFTR field.
	GMAC_IDR_PFTR_Msk = 0x4000
	// Bit PFTR.
	GMAC_IDR_PFTR = 0x4000
	// Position of EXINT field.
	GMAC_IDR_EXINT_Pos = 0xf
	// Bit mask of EXINT field.
	GMAC_IDR_EXINT_Msk = 0x8000
	// Bit EXINT.
	GMAC_IDR_EXINT = 0x8000
	// Position of DRQFR field.
	GMAC_IDR_DRQFR_Pos = 0x12
	// Bit mask of DRQFR field.
	GMAC_IDR_DRQFR_Msk = 0x40000
	// Bit DRQFR.
	GMAC_IDR_DRQFR = 0x40000
	// Position of SFR field.
	GMAC_IDR_SFR_Pos = 0x13
	// Bit mask of SFR field.
	GMAC_IDR_SFR_Msk = 0x80000
	// Bit SFR.
	GMAC_IDR_SFR = 0x80000
	// Position of DRQFT field.
	GMAC_IDR_DRQFT_Pos = 0x14
	// Bit mask of DRQFT field.
	GMAC_IDR_DRQFT_Msk = 0x100000
	// Bit DRQFT.
	GMAC_IDR_DRQFT = 0x100000
	// Position of SFT field.
	GMAC_IDR_SFT_Pos = 0x15
	// Bit mask of SFT field.
	GMAC_IDR_SFT_Msk = 0x200000
	// Bit SFT.
	GMAC_IDR_SFT = 0x200000
	// Position of PDRQFR field.
	GMAC_IDR_PDRQFR_Pos = 0x16
	// Bit mask of PDRQFR field.
	GMAC_IDR_PDRQFR_Msk = 0x400000
	// Bit PDRQFR.
	GMAC_IDR_PDRQFR = 0x400000
	// Position of PDRSFR field.
	GMAC_IDR_PDRSFR_Pos = 0x17
	// Bit mask of PDRSFR field.
	GMAC_IDR_PDRSFR_Msk = 0x800000
	// Bit PDRSFR.
	GMAC_IDR_PDRSFR = 0x800000
	// Position of PDRQFT field.
	GMAC_IDR_PDRQFT_Pos = 0x18
	// Bit mask of PDRQFT field.
	GMAC_IDR_PDRQFT_Msk = 0x1000000
	// Bit PDRQFT.
	GMAC_IDR_PDRQFT = 0x1000000
	// Position of PDRSFT field.
	GMAC_IDR_PDRSFT_Pos = 0x19
	// Bit mask of PDRSFT field.
	GMAC_IDR_PDRSFT_Msk = 0x2000000
	// Bit PDRSFT.
	GMAC_IDR_PDRSFT = 0x2000000
	// Position of SRI field.
	GMAC_IDR_SRI_Pos = 0x1a
	// Bit mask of SRI field.
	GMAC_IDR_SRI_Msk = 0x4000000
	// Bit SRI.
	GMAC_IDR_SRI = 0x4000000
	// Position of WOL field.
	GMAC_IDR_WOL_Pos = 0x1c
	// Bit mask of WOL field.
	GMAC_IDR_WOL_Msk = 0x10000000
	// Bit WOL.
	GMAC_IDR_WOL = 0x10000000
	// Position of TSUCMP field.
	GMAC_IDR_TSUCMP_Pos = 0x1d
	// Bit mask of TSUCMP field.
	GMAC_IDR_TSUCMP_Msk = 0x20000000
	// Bit TSUCMP.
	GMAC_IDR_TSUCMP = 0x20000000

	// IMR: Interrupt Mask Register
	// Position of MFS field.
	GMAC_IMR_MFS_Pos = 0x0
	// Bit mask of MFS field.
	GMAC_IMR_MFS_Msk = 0x1
	// Bit MFS.
	GMAC_IMR_MFS = 0x1
	// Position of RCOMP field.
	GMAC_IMR_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	GMAC_IMR_RCOMP_Msk = 0x2
	// Bit RCOMP.
	GMAC_IMR_RCOMP = 0x2
	// Position of RXUBR field.
	GMAC_IMR_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	GMAC_IMR_RXUBR_Msk = 0x4
	// Bit RXUBR.
	GMAC_IMR_RXUBR = 0x4
	// Position of TXUBR field.
	GMAC_IMR_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	GMAC_IMR_TXUBR_Msk = 0x8
	// Bit TXUBR.
	GMAC_IMR_TXUBR = 0x8
	// Position of TUR field.
	GMAC_IMR_TUR_Pos = 0x4
	// Bit mask of TUR field.
	GMAC_IMR_TUR_Msk = 0x10
	// Bit TUR.
	GMAC_IMR_TUR = 0x10
	// Position of RLEX field.
	GMAC_IMR_RLEX_Pos = 0x5
	// Bit mask of RLEX field.
	GMAC_IMR_RLEX_Msk = 0x20
	// Bit RLEX.
	GMAC_IMR_RLEX = 0x20
	// Position of TFC field.
	GMAC_IMR_TFC_Pos = 0x6
	// Bit mask of TFC field.
	GMAC_IMR_TFC_Msk = 0x40
	// Bit TFC.
	GMAC_IMR_TFC = 0x40
	// Position of TCOMP field.
	GMAC_IMR_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	GMAC_IMR_TCOMP_Msk = 0x80
	// Bit TCOMP.
	GMAC_IMR_TCOMP = 0x80
	// Position of ROVR field.
	GMAC_IMR_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	GMAC_IMR_ROVR_Msk = 0x400
	// Bit ROVR.
	GMAC_IMR_ROVR = 0x400
	// Position of HRESP field.
	GMAC_IMR_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	GMAC_IMR_HRESP_Msk = 0x800
	// Bit HRESP.
	GMAC_IMR_HRESP = 0x800
	// Position of PFNZ field.
	GMAC_IMR_PFNZ_Pos = 0xc
	// Bit mask of PFNZ field.
	GMAC_IMR_PFNZ_Msk = 0x1000
	// Bit PFNZ.
	GMAC_IMR_PFNZ = 0x1000
	// Position of PTZ field.
	GMAC_IMR_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	GMAC_IMR_PTZ_Msk = 0x2000
	// Bit PTZ.
	GMAC_IMR_PTZ = 0x2000
	// Position of PFTR field.
	GMAC_IMR_PFTR_Pos = 0xe
	// Bit mask of PFTR field.
	GMAC_IMR_PFTR_Msk = 0x4000
	// Bit PFTR.
	GMAC_IMR_PFTR = 0x4000
	// Position of EXINT field.
	GMAC_IMR_EXINT_Pos = 0xf
	// Bit mask of EXINT field.
	GMAC_IMR_EXINT_Msk = 0x8000
	// Bit EXINT.
	GMAC_IMR_EXINT = 0x8000
	// Position of DRQFR field.
	GMAC_IMR_DRQFR_Pos = 0x12
	// Bit mask of DRQFR field.
	GMAC_IMR_DRQFR_Msk = 0x40000
	// Bit DRQFR.
	GMAC_IMR_DRQFR = 0x40000
	// Position of SFR field.
	GMAC_IMR_SFR_Pos = 0x13
	// Bit mask of SFR field.
	GMAC_IMR_SFR_Msk = 0x80000
	// Bit SFR.
	GMAC_IMR_SFR = 0x80000
	// Position of DRQFT field.
	GMAC_IMR_DRQFT_Pos = 0x14
	// Bit mask of DRQFT field.
	GMAC_IMR_DRQFT_Msk = 0x100000
	// Bit DRQFT.
	GMAC_IMR_DRQFT = 0x100000
	// Position of SFT field.
	GMAC_IMR_SFT_Pos = 0x15
	// Bit mask of SFT field.
	GMAC_IMR_SFT_Msk = 0x200000
	// Bit SFT.
	GMAC_IMR_SFT = 0x200000
	// Position of PDRQFR field.
	GMAC_IMR_PDRQFR_Pos = 0x16
	// Bit mask of PDRQFR field.
	GMAC_IMR_PDRQFR_Msk = 0x400000
	// Bit PDRQFR.
	GMAC_IMR_PDRQFR = 0x400000
	// Position of PDRSFR field.
	GMAC_IMR_PDRSFR_Pos = 0x17
	// Bit mask of PDRSFR field.
	GMAC_IMR_PDRSFR_Msk = 0x800000
	// Bit PDRSFR.
	GMAC_IMR_PDRSFR = 0x800000
	// Position of PDRQFT field.
	GMAC_IMR_PDRQFT_Pos = 0x18
	// Bit mask of PDRQFT field.
	GMAC_IMR_PDRQFT_Msk = 0x1000000
	// Bit PDRQFT.
	GMAC_IMR_PDRQFT = 0x1000000
	// Position of PDRSFT field.
	GMAC_IMR_PDRSFT_Pos = 0x19
	// Bit mask of PDRSFT field.
	GMAC_IMR_PDRSFT_Msk = 0x2000000
	// Bit PDRSFT.
	GMAC_IMR_PDRSFT = 0x2000000
	// Position of SRI field.
	GMAC_IMR_SRI_Pos = 0x1a
	// Bit mask of SRI field.
	GMAC_IMR_SRI_Msk = 0x4000000
	// Bit SRI.
	GMAC_IMR_SRI = 0x4000000
	// Position of WOL field.
	GMAC_IMR_WOL_Pos = 0x1c
	// Bit mask of WOL field.
	GMAC_IMR_WOL_Msk = 0x10000000
	// Bit WOL.
	GMAC_IMR_WOL = 0x10000000
	// Position of TSUCMP field.
	GMAC_IMR_TSUCMP_Pos = 0x1d
	// Bit mask of TSUCMP field.
	GMAC_IMR_TSUCMP_Msk = 0x20000000
	// Bit TSUCMP.
	GMAC_IMR_TSUCMP = 0x20000000

	// MAN: PHY Maintenance Register
	// Position of DATA field.
	GMAC_MAN_DATA_Pos = 0x0
	// Bit mask of DATA field.
	GMAC_MAN_DATA_Msk = 0xffff
	// Position of WTN field.
	GMAC_MAN_WTN_Pos = 0x10
	// Bit mask of WTN field.
	GMAC_MAN_WTN_Msk = 0x30000
	// Position of REGA field.
	GMAC_MAN_REGA_Pos = 0x12
	// Bit mask of REGA field.
	GMAC_MAN_REGA_Msk = 0x7c0000
	// Position of PHYA field.
	GMAC_MAN_PHYA_Pos = 0x17
	// Bit mask of PHYA field.
	GMAC_MAN_PHYA_Msk = 0xf800000
	// Position of OP field.
	GMAC_MAN_OP_Pos = 0x1c
	// Bit mask of OP field.
	GMAC_MAN_OP_Msk = 0x30000000
	// Position of CLTTO field.
	GMAC_MAN_CLTTO_Pos = 0x1e
	// Bit mask of CLTTO field.
	GMAC_MAN_CLTTO_Msk = 0x40000000
	// Bit CLTTO.
	GMAC_MAN_CLTTO = 0x40000000
	// Position of WZO field.
	GMAC_MAN_WZO_Pos = 0x1f
	// Bit mask of WZO field.
	GMAC_MAN_WZO_Msk = 0x80000000
	// Bit WZO.
	GMAC_MAN_WZO = 0x80000000

	// RPQ: Received Pause Quantum Register
	// Position of RPQ field.
	GMAC_RPQ_RPQ_Pos = 0x0
	// Bit mask of RPQ field.
	GMAC_RPQ_RPQ_Msk = 0xffff

	// TPQ: Transmit Pause Quantum Register
	// Position of TPQ field.
	GMAC_TPQ_TPQ_Pos = 0x0
	// Bit mask of TPQ field.
	GMAC_TPQ_TPQ_Msk = 0xffff

	// TPSF: TX partial store and forward Register
	// Position of TPB1ADR field.
	GMAC_TPSF_TPB1ADR_Pos = 0x0
	// Bit mask of TPB1ADR field.
	GMAC_TPSF_TPB1ADR_Msk = 0x3ff
	// Position of ENTXP field.
	GMAC_TPSF_ENTXP_Pos = 0x1f
	// Bit mask of ENTXP field.
	GMAC_TPSF_ENTXP_Msk = 0x80000000
	// Bit ENTXP.
	GMAC_TPSF_ENTXP = 0x80000000

	// RPSF: RX partial store and forward Register
	// Position of RPB1ADR field.
	GMAC_RPSF_RPB1ADR_Pos = 0x0
	// Bit mask of RPB1ADR field.
	GMAC_RPSF_RPB1ADR_Msk = 0x3ff
	// Position of ENRXP field.
	GMAC_RPSF_ENRXP_Pos = 0x1f
	// Bit mask of ENRXP field.
	GMAC_RPSF_ENRXP_Msk = 0x80000000
	// Bit ENRXP.
	GMAC_RPSF_ENRXP = 0x80000000

	// RJFML: RX Jumbo Frame Max Length Register
	// Position of FML field.
	GMAC_RJFML_FML_Pos = 0x0
	// Bit mask of FML field.
	GMAC_RJFML_FML_Msk = 0x3fff

	// HRB: Hash Register Bottom [31:0]
	// Position of ADDR field.
	GMAC_HRB_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	GMAC_HRB_ADDR_Msk = 0xffffffff

	// HRT: Hash Register Top [63:32]
	// Position of ADDR field.
	GMAC_HRT_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	GMAC_HRT_ADDR_Msk = 0xffffffff

	// SA.SAB: Specific Address Bottom [31:0] Register
	// Position of ADDR field.
	GMAC_SA_SAB_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	GMAC_SA_SAB_ADDR_Msk = 0xffffffff

	// SA.SAT: Specific Address Top [47:32] Register
	// Position of ADDR field.
	GMAC_SA_SAT_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	GMAC_SA_SAT_ADDR_Msk = 0xffff

	// TIDM: Type ID Match Register
	// Position of TID field.
	GMAC_TIDM_TID_Pos = 0x0
	// Bit mask of TID field.
	GMAC_TIDM_TID_Msk = 0xffff

	// WOL: Wake on LAN
	// Position of IP field.
	GMAC_WOL_IP_Pos = 0x0
	// Bit mask of IP field.
	GMAC_WOL_IP_Msk = 0xffff
	// Position of MAG field.
	GMAC_WOL_MAG_Pos = 0x10
	// Bit mask of MAG field.
	GMAC_WOL_MAG_Msk = 0x10000
	// Bit MAG.
	GMAC_WOL_MAG = 0x10000
	// Position of ARP field.
	GMAC_WOL_ARP_Pos = 0x11
	// Bit mask of ARP field.
	GMAC_WOL_ARP_Msk = 0x20000
	// Bit ARP.
	GMAC_WOL_ARP = 0x20000
	// Position of SA1 field.
	GMAC_WOL_SA1_Pos = 0x12
	// Bit mask of SA1 field.
	GMAC_WOL_SA1_Msk = 0x40000
	// Bit SA1.
	GMAC_WOL_SA1 = 0x40000
	// Position of MTI field.
	GMAC_WOL_MTI_Pos = 0x13
	// Bit mask of MTI field.
	GMAC_WOL_MTI_Msk = 0x80000
	// Bit MTI.
	GMAC_WOL_MTI = 0x80000

	// IPGS: IPG Stretch Register
	// Position of FL field.
	GMAC_IPGS_FL_Pos = 0x0
	// Bit mask of FL field.
	GMAC_IPGS_FL_Msk = 0xffff

	// SVLAN: Stacked VLAN Register
	// Position of VLAN_TYPE field.
	GMAC_SVLAN_VLAN_TYPE_Pos = 0x0
	// Bit mask of VLAN_TYPE field.
	GMAC_SVLAN_VLAN_TYPE_Msk = 0xffff
	// Position of ESVLAN field.
	GMAC_SVLAN_ESVLAN_Pos = 0x1f
	// Bit mask of ESVLAN field.
	GMAC_SVLAN_ESVLAN_Msk = 0x80000000
	// Bit ESVLAN.
	GMAC_SVLAN_ESVLAN = 0x80000000

	// TPFCP: Transmit PFC Pause Register
	// Position of PEV field.
	GMAC_TPFCP_PEV_Pos = 0x0
	// Bit mask of PEV field.
	GMAC_TPFCP_PEV_Msk = 0xff
	// Position of PQ field.
	GMAC_TPFCP_PQ_Pos = 0x8
	// Bit mask of PQ field.
	GMAC_TPFCP_PQ_Msk = 0xff00

	// SAMB1: Specific Address 1 Mask Bottom [31:0] Register
	// Position of ADDR field.
	GMAC_SAMB1_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	GMAC_SAMB1_ADDR_Msk = 0xffffffff

	// SAMT1: Specific Address 1 Mask Top [47:32] Register
	// Position of ADDR field.
	GMAC_SAMT1_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	GMAC_SAMT1_ADDR_Msk = 0xffff

	// NSC: Tsu timer comparison nanoseconds Register
	// Position of NANOSEC field.
	GMAC_NSC_NANOSEC_Pos = 0x0
	// Bit mask of NANOSEC field.
	GMAC_NSC_NANOSEC_Msk = 0x1fffff

	// SCL: Tsu timer second comparison Register
	// Position of SEC field.
	GMAC_SCL_SEC_Pos = 0x0
	// Bit mask of SEC field.
	GMAC_SCL_SEC_Msk = 0xffffffff

	// SCH: Tsu timer second comparison Register
	// Position of SEC field.
	GMAC_SCH_SEC_Pos = 0x0
	// Bit mask of SEC field.
	GMAC_SCH_SEC_Msk = 0xffff

	// EFTSH: PTP Event Frame Transmitted Seconds High Register
	// Position of RUD field.
	GMAC_EFTSH_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_EFTSH_RUD_Msk = 0xffff

	// EFRSH: PTP Event Frame Received Seconds High Register
	// Position of RUD field.
	GMAC_EFRSH_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_EFRSH_RUD_Msk = 0xffff

	// PEFTSH: PTP Peer Event Frame Transmitted Seconds High Register
	// Position of RUD field.
	GMAC_PEFTSH_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_PEFTSH_RUD_Msk = 0xffff

	// PEFRSH: PTP Peer Event Frame Received Seconds High Register
	// Position of RUD field.
	GMAC_PEFRSH_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_PEFRSH_RUD_Msk = 0xffff

	// OTLO: Octets Transmitted [31:0] Register
	// Position of TXO field.
	GMAC_OTLO_TXO_Pos = 0x0
	// Bit mask of TXO field.
	GMAC_OTLO_TXO_Msk = 0xffffffff

	// OTHI: Octets Transmitted [47:32] Register
	// Position of TXO field.
	GMAC_OTHI_TXO_Pos = 0x0
	// Bit mask of TXO field.
	GMAC_OTHI_TXO_Msk = 0xffff

	// FT: Frames Transmitted Register
	// Position of FTX field.
	GMAC_FT_FTX_Pos = 0x0
	// Bit mask of FTX field.
	GMAC_FT_FTX_Msk = 0xffffffff

	// BCFT: Broadcast Frames Transmitted Register
	// Position of BFTX field.
	GMAC_BCFT_BFTX_Pos = 0x0
	// Bit mask of BFTX field.
	GMAC_BCFT_BFTX_Msk = 0xffffffff

	// MFT: Multicast Frames Transmitted Register
	// Position of MFTX field.
	GMAC_MFT_MFTX_Pos = 0x0
	// Bit mask of MFTX field.
	GMAC_MFT_MFTX_Msk = 0xffffffff

	// PFT: Pause Frames Transmitted Register
	// Position of PFTX field.
	GMAC_PFT_PFTX_Pos = 0x0
	// Bit mask of PFTX field.
	GMAC_PFT_PFTX_Msk = 0xffff

	// BFT64: 64 Byte Frames Transmitted Register
	// Position of NFTX field.
	GMAC_BFT64_NFTX_Pos = 0x0
	// Bit mask of NFTX field.
	GMAC_BFT64_NFTX_Msk = 0xffffffff

	// TBFT127: 65 to 127 Byte Frames Transmitted Register
	// Position of NFTX field.
	GMAC_TBFT127_NFTX_Pos = 0x0
	// Bit mask of NFTX field.
	GMAC_TBFT127_NFTX_Msk = 0xffffffff

	// TBFT255: 128 to 255 Byte Frames Transmitted Register
	// Position of NFTX field.
	GMAC_TBFT255_NFTX_Pos = 0x0
	// Bit mask of NFTX field.
	GMAC_TBFT255_NFTX_Msk = 0xffffffff

	// TBFT511: 256 to 511 Byte Frames Transmitted Register
	// Position of NFTX field.
	GMAC_TBFT511_NFTX_Pos = 0x0
	// Bit mask of NFTX field.
	GMAC_TBFT511_NFTX_Msk = 0xffffffff

	// TBFT1023: 512 to 1023 Byte Frames Transmitted Register
	// Position of NFTX field.
	GMAC_TBFT1023_NFTX_Pos = 0x0
	// Bit mask of NFTX field.
	GMAC_TBFT1023_NFTX_Msk = 0xffffffff

	// TBFT1518: 1024 to 1518 Byte Frames Transmitted Register
	// Position of NFTX field.
	GMAC_TBFT1518_NFTX_Pos = 0x0
	// Bit mask of NFTX field.
	GMAC_TBFT1518_NFTX_Msk = 0xffffffff

	// GTBFT1518: Greater Than 1518 Byte Frames Transmitted Register
	// Position of NFTX field.
	GMAC_GTBFT1518_NFTX_Pos = 0x0
	// Bit mask of NFTX field.
	GMAC_GTBFT1518_NFTX_Msk = 0xffffffff

	// TUR: Transmit Underruns Register
	// Position of TXUNR field.
	GMAC_TUR_TXUNR_Pos = 0x0
	// Bit mask of TXUNR field.
	GMAC_TUR_TXUNR_Msk = 0x3ff

	// SCF: Single Collision Frames Register
	// Position of SCOL field.
	GMAC_SCF_SCOL_Pos = 0x0
	// Bit mask of SCOL field.
	GMAC_SCF_SCOL_Msk = 0x3ffff

	// MCF: Multiple Collision Frames Register
	// Position of MCOL field.
	GMAC_MCF_MCOL_Pos = 0x0
	// Bit mask of MCOL field.
	GMAC_MCF_MCOL_Msk = 0x3ffff

	// EC: Excessive Collisions Register
	// Position of XCOL field.
	GMAC_EC_XCOL_Pos = 0x0
	// Bit mask of XCOL field.
	GMAC_EC_XCOL_Msk = 0x3ff

	// LC: Late Collisions Register
	// Position of LCOL field.
	GMAC_LC_LCOL_Pos = 0x0
	// Bit mask of LCOL field.
	GMAC_LC_LCOL_Msk = 0x3ff

	// DTF: Deferred Transmission Frames Register
	// Position of DEFT field.
	GMAC_DTF_DEFT_Pos = 0x0
	// Bit mask of DEFT field.
	GMAC_DTF_DEFT_Msk = 0x3ffff

	// CSE: Carrier Sense Errors Register
	// Position of CSR field.
	GMAC_CSE_CSR_Pos = 0x0
	// Bit mask of CSR field.
	GMAC_CSE_CSR_Msk = 0x3ff

	// ORLO: Octets Received [31:0] Received
	// Position of RXO field.
	GMAC_ORLO_RXO_Pos = 0x0
	// Bit mask of RXO field.
	GMAC_ORLO_RXO_Msk = 0xffffffff

	// ORHI: Octets Received [47:32] Received
	// Position of RXO field.
	GMAC_ORHI_RXO_Pos = 0x0
	// Bit mask of RXO field.
	GMAC_ORHI_RXO_Msk = 0xffff

	// FR: Frames Received Register
	// Position of FRX field.
	GMAC_FR_FRX_Pos = 0x0
	// Bit mask of FRX field.
	GMAC_FR_FRX_Msk = 0xffffffff

	// BCFR: Broadcast Frames Received Register
	// Position of BFRX field.
	GMAC_BCFR_BFRX_Pos = 0x0
	// Bit mask of BFRX field.
	GMAC_BCFR_BFRX_Msk = 0xffffffff

	// MFR: Multicast Frames Received Register
	// Position of MFRX field.
	GMAC_MFR_MFRX_Pos = 0x0
	// Bit mask of MFRX field.
	GMAC_MFR_MFRX_Msk = 0xffffffff

	// PFR: Pause Frames Received Register
	// Position of PFRX field.
	GMAC_PFR_PFRX_Pos = 0x0
	// Bit mask of PFRX field.
	GMAC_PFR_PFRX_Msk = 0xffff

	// BFR64: 64 Byte Frames Received Register
	// Position of NFRX field.
	GMAC_BFR64_NFRX_Pos = 0x0
	// Bit mask of NFRX field.
	GMAC_BFR64_NFRX_Msk = 0xffffffff

	// TBFR127: 65 to 127 Byte Frames Received Register
	// Position of NFRX field.
	GMAC_TBFR127_NFRX_Pos = 0x0
	// Bit mask of NFRX field.
	GMAC_TBFR127_NFRX_Msk = 0xffffffff

	// TBFR255: 128 to 255 Byte Frames Received Register
	// Position of NFRX field.
	GMAC_TBFR255_NFRX_Pos = 0x0
	// Bit mask of NFRX field.
	GMAC_TBFR255_NFRX_Msk = 0xffffffff

	// TBFR511: 256 to 511Byte Frames Received Register
	// Position of NFRX field.
	GMAC_TBFR511_NFRX_Pos = 0x0
	// Bit mask of NFRX field.
	GMAC_TBFR511_NFRX_Msk = 0xffffffff

	// TBFR1023: 512 to 1023 Byte Frames Received Register
	// Position of NFRX field.
	GMAC_TBFR1023_NFRX_Pos = 0x0
	// Bit mask of NFRX field.
	GMAC_TBFR1023_NFRX_Msk = 0xffffffff

	// TBFR1518: 1024 to 1518 Byte Frames Received Register
	// Position of NFRX field.
	GMAC_TBFR1518_NFRX_Pos = 0x0
	// Bit mask of NFRX field.
	GMAC_TBFR1518_NFRX_Msk = 0xffffffff

	// TMXBFR: 1519 to Maximum Byte Frames Received Register
	// Position of NFRX field.
	GMAC_TMXBFR_NFRX_Pos = 0x0
	// Bit mask of NFRX field.
	GMAC_TMXBFR_NFRX_Msk = 0xffffffff

	// UFR: Undersize Frames Received Register
	// Position of UFRX field.
	GMAC_UFR_UFRX_Pos = 0x0
	// Bit mask of UFRX field.
	GMAC_UFR_UFRX_Msk = 0x3ff

	// OFR: Oversize Frames Received Register
	// Position of OFRX field.
	GMAC_OFR_OFRX_Pos = 0x0
	// Bit mask of OFRX field.
	GMAC_OFR_OFRX_Msk = 0x3ff

	// JR: Jabbers Received Register
	// Position of JRX field.
	GMAC_JR_JRX_Pos = 0x0
	// Bit mask of JRX field.
	GMAC_JR_JRX_Msk = 0x3ff

	// FCSE: Frame Check Sequence Errors Register
	// Position of FCKR field.
	GMAC_FCSE_FCKR_Pos = 0x0
	// Bit mask of FCKR field.
	GMAC_FCSE_FCKR_Msk = 0x3ff

	// LFFE: Length Field Frame Errors Register
	// Position of LFER field.
	GMAC_LFFE_LFER_Pos = 0x0
	// Bit mask of LFER field.
	GMAC_LFFE_LFER_Msk = 0x3ff

	// RSE: Receive Symbol Errors Register
	// Position of RXSE field.
	GMAC_RSE_RXSE_Pos = 0x0
	// Bit mask of RXSE field.
	GMAC_RSE_RXSE_Msk = 0x3ff

	// AE: Alignment Errors Register
	// Position of AER field.
	GMAC_AE_AER_Pos = 0x0
	// Bit mask of AER field.
	GMAC_AE_AER_Msk = 0x3ff

	// RRE: Receive Resource Errors Register
	// Position of RXRER field.
	GMAC_RRE_RXRER_Pos = 0x0
	// Bit mask of RXRER field.
	GMAC_RRE_RXRER_Msk = 0x3ffff

	// ROE: Receive Overrun Register
	// Position of RXOVR field.
	GMAC_ROE_RXOVR_Pos = 0x0
	// Bit mask of RXOVR field.
	GMAC_ROE_RXOVR_Msk = 0x3ff

	// IHCE: IP Header Checksum Errors Register
	// Position of HCKER field.
	GMAC_IHCE_HCKER_Pos = 0x0
	// Bit mask of HCKER field.
	GMAC_IHCE_HCKER_Msk = 0xff

	// TCE: TCP Checksum Errors Register
	// Position of TCKER field.
	GMAC_TCE_TCKER_Pos = 0x0
	// Bit mask of TCKER field.
	GMAC_TCE_TCKER_Msk = 0xff

	// UCE: UDP Checksum Errors Register
	// Position of UCKER field.
	GMAC_UCE_UCKER_Pos = 0x0
	// Bit mask of UCKER field.
	GMAC_UCE_UCKER_Msk = 0xff

	// TISUBN: 1588 Timer Increment [15:0] Sub-Nanoseconds Register
	// Position of LSBTIR field.
	GMAC_TISUBN_LSBTIR_Pos = 0x0
	// Bit mask of LSBTIR field.
	GMAC_TISUBN_LSBTIR_Msk = 0xffff

	// TSH: 1588 Timer Seconds High [15:0] Register
	// Position of TCS field.
	GMAC_TSH_TCS_Pos = 0x0
	// Bit mask of TCS field.
	GMAC_TSH_TCS_Msk = 0xffff

	// TSSSL: 1588 Timer Sync Strobe Seconds [31:0] Register
	// Position of VTS field.
	GMAC_TSSSL_VTS_Pos = 0x0
	// Bit mask of VTS field.
	GMAC_TSSSL_VTS_Msk = 0xffffffff

	// TSSN: 1588 Timer Sync Strobe Nanoseconds Register
	// Position of VTN field.
	GMAC_TSSN_VTN_Pos = 0x0
	// Bit mask of VTN field.
	GMAC_TSSN_VTN_Msk = 0x3fffffff

	// TSL: 1588 Timer Seconds [31:0] Register
	// Position of TCS field.
	GMAC_TSL_TCS_Pos = 0x0
	// Bit mask of TCS field.
	GMAC_TSL_TCS_Msk = 0xffffffff

	// TN: 1588 Timer Nanoseconds Register
	// Position of TNS field.
	GMAC_TN_TNS_Pos = 0x0
	// Bit mask of TNS field.
	GMAC_TN_TNS_Msk = 0x3fffffff

	// TA: 1588 Timer Adjust Register
	// Position of ITDT field.
	GMAC_TA_ITDT_Pos = 0x0
	// Bit mask of ITDT field.
	GMAC_TA_ITDT_Msk = 0x3fffffff
	// Position of ADJ field.
	GMAC_TA_ADJ_Pos = 0x1f
	// Bit mask of ADJ field.
	GMAC_TA_ADJ_Msk = 0x80000000
	// Bit ADJ.
	GMAC_TA_ADJ = 0x80000000

	// TI: 1588 Timer Increment Register
	// Position of CNS field.
	GMAC_TI_CNS_Pos = 0x0
	// Bit mask of CNS field.
	GMAC_TI_CNS_Msk = 0xff
	// Position of ACNS field.
	GMAC_TI_ACNS_Pos = 0x8
	// Bit mask of ACNS field.
	GMAC_TI_ACNS_Msk = 0xff00
	// Position of NIT field.
	GMAC_TI_NIT_Pos = 0x10
	// Bit mask of NIT field.
	GMAC_TI_NIT_Msk = 0xff0000

	// EFTSL: PTP Event Frame Transmitted Seconds Low Register
	// Position of RUD field.
	GMAC_EFTSL_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_EFTSL_RUD_Msk = 0xffffffff

	// EFTN: PTP Event Frame Transmitted Nanoseconds
	// Position of RUD field.
	GMAC_EFTN_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_EFTN_RUD_Msk = 0x3fffffff

	// EFRSL: PTP Event Frame Received Seconds Low Register
	// Position of RUD field.
	GMAC_EFRSL_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_EFRSL_RUD_Msk = 0xffffffff

	// EFRN: PTP Event Frame Received Nanoseconds
	// Position of RUD field.
	GMAC_EFRN_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_EFRN_RUD_Msk = 0x3fffffff

	// PEFTSL: PTP Peer Event Frame Transmitted Seconds Low Register
	// Position of RUD field.
	GMAC_PEFTSL_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_PEFTSL_RUD_Msk = 0xffffffff

	// PEFTN: PTP Peer Event Frame Transmitted Nanoseconds
	// Position of RUD field.
	GMAC_PEFTN_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_PEFTN_RUD_Msk = 0x3fffffff

	// PEFRSL: PTP Peer Event Frame Received Seconds Low Register
	// Position of RUD field.
	GMAC_PEFRSL_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_PEFRSL_RUD_Msk = 0xffffffff

	// PEFRN: PTP Peer Event Frame Received Nanoseconds
	// Position of RUD field.
	GMAC_PEFRN_RUD_Pos = 0x0
	// Bit mask of RUD field.
	GMAC_PEFRN_RUD_Msk = 0x3fffffff

	// RLPITR: Receive LPI transition Register
	// Position of RLPITR field.
	GMAC_RLPITR_RLPITR_Pos = 0x0
	// Bit mask of RLPITR field.
	GMAC_RLPITR_RLPITR_Msk = 0xffff

	// RLPITI: Receive LPI Time Register
	// Position of RLPITI field.
	GMAC_RLPITI_RLPITI_Pos = 0x0
	// Bit mask of RLPITI field.
	GMAC_RLPITI_RLPITI_Msk = 0xffffff

	// TLPITR: Receive LPI transition Register
	// Position of TLPITR field.
	GMAC_TLPITR_TLPITR_Pos = 0x0
	// Bit mask of TLPITR field.
	GMAC_TLPITR_TLPITR_Msk = 0xffff

	// TLPITI: Receive LPI Time Register
	// Position of TLPITI field.
	GMAC_TLPITI_TLPITI_Pos = 0x0
	// Bit mask of TLPITI field.
	GMAC_TLPITI_TLPITI_Msk = 0xffffff
)

// Bitfields for HMATRIX: HSB Matrix
const (
// PRS.PRAS: Priority A for Slave

// PRS.PRBS: Priority B for Slave
)

// Bitfields for ICM: Integrity Check Monitor
const (
	// CFG: Configuration
	// Position of WBDIS field.
	ICM_CFG_WBDIS_Pos = 0x0
	// Bit mask of WBDIS field.
	ICM_CFG_WBDIS_Msk = 0x1
	// Bit WBDIS.
	ICM_CFG_WBDIS = 0x1
	// Position of EOMDIS field.
	ICM_CFG_EOMDIS_Pos = 0x1
	// Bit mask of EOMDIS field.
	ICM_CFG_EOMDIS_Msk = 0x2
	// Bit EOMDIS.
	ICM_CFG_EOMDIS = 0x2
	// Position of SLBDIS field.
	ICM_CFG_SLBDIS_Pos = 0x2
	// Bit mask of SLBDIS field.
	ICM_CFG_SLBDIS_Msk = 0x4
	// Bit SLBDIS.
	ICM_CFG_SLBDIS = 0x4
	// Position of BBC field.
	ICM_CFG_BBC_Pos = 0x4
	// Bit mask of BBC field.
	ICM_CFG_BBC_Msk = 0xf0
	// Position of ASCD field.
	ICM_CFG_ASCD_Pos = 0x8
	// Bit mask of ASCD field.
	ICM_CFG_ASCD_Msk = 0x100
	// Bit ASCD.
	ICM_CFG_ASCD = 0x100
	// Position of DUALBUFF field.
	ICM_CFG_DUALBUFF_Pos = 0x9
	// Bit mask of DUALBUFF field.
	ICM_CFG_DUALBUFF_Msk = 0x200
	// Bit DUALBUFF.
	ICM_CFG_DUALBUFF = 0x200
	// Position of UIHASH field.
	ICM_CFG_UIHASH_Pos = 0xc
	// Bit mask of UIHASH field.
	ICM_CFG_UIHASH_Msk = 0x1000
	// Bit UIHASH.
	ICM_CFG_UIHASH = 0x1000
	// Position of UALGO field.
	ICM_CFG_UALGO_Pos = 0xd
	// Bit mask of UALGO field.
	ICM_CFG_UALGO_Msk = 0xe000
	// SHA1 Algorithm
	ICM_CFG_UALGO_SHA1 = 0x0
	// SHA256 Algorithm
	ICM_CFG_UALGO_SHA256 = 0x1
	// SHA224 Algorithm
	ICM_CFG_UALGO_SHA224 = 0x4
	// Position of HAPROT field.
	ICM_CFG_HAPROT_Pos = 0x10
	// Bit mask of HAPROT field.
	ICM_CFG_HAPROT_Msk = 0x3f0000
	// Position of DAPROT field.
	ICM_CFG_DAPROT_Pos = 0x18
	// Bit mask of DAPROT field.
	ICM_CFG_DAPROT_Msk = 0x3f000000

	// CTRL: Control
	// Position of ENABLE field.
	ICM_CTRL_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	ICM_CTRL_ENABLE_Msk = 0x1
	// Bit ENABLE.
	ICM_CTRL_ENABLE = 0x1
	// Position of DISABLE field.
	ICM_CTRL_DISABLE_Pos = 0x1
	// Bit mask of DISABLE field.
	ICM_CTRL_DISABLE_Msk = 0x2
	// Bit DISABLE.
	ICM_CTRL_DISABLE = 0x2
	// Position of SWRST field.
	ICM_CTRL_SWRST_Pos = 0x2
	// Bit mask of SWRST field.
	ICM_CTRL_SWRST_Msk = 0x4
	// Bit SWRST.
	ICM_CTRL_SWRST = 0x4
	// Position of REHASH field.
	ICM_CTRL_REHASH_Pos = 0x4
	// Bit mask of REHASH field.
	ICM_CTRL_REHASH_Msk = 0xf0
	// Position of RMDIS field.
	ICM_CTRL_RMDIS_Pos = 0x8
	// Bit mask of RMDIS field.
	ICM_CTRL_RMDIS_Msk = 0xf00
	// Position of RMEN field.
	ICM_CTRL_RMEN_Pos = 0xc
	// Bit mask of RMEN field.
	ICM_CTRL_RMEN_Msk = 0xf000

	// SR: Status
	// Position of ENABLE field.
	ICM_SR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	ICM_SR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	ICM_SR_ENABLE = 0x1
	// Position of RAWRMDIS field.
	ICM_SR_RAWRMDIS_Pos = 0x8
	// Bit mask of RAWRMDIS field.
	ICM_SR_RAWRMDIS_Msk = 0xf00
	// Position of RMDIS field.
	ICM_SR_RMDIS_Pos = 0xc
	// Bit mask of RMDIS field.
	ICM_SR_RMDIS_Msk = 0xf000

	// IER: Interrupt Enable
	// Position of RHC field.
	ICM_IER_RHC_Pos = 0x0
	// Bit mask of RHC field.
	ICM_IER_RHC_Msk = 0xf
	// Position of RDM field.
	ICM_IER_RDM_Pos = 0x4
	// Bit mask of RDM field.
	ICM_IER_RDM_Msk = 0xf0
	// Position of RBE field.
	ICM_IER_RBE_Pos = 0x8
	// Bit mask of RBE field.
	ICM_IER_RBE_Msk = 0xf00
	// Position of RWC field.
	ICM_IER_RWC_Pos = 0xc
	// Bit mask of RWC field.
	ICM_IER_RWC_Msk = 0xf000
	// Position of REC field.
	ICM_IER_REC_Pos = 0x10
	// Bit mask of REC field.
	ICM_IER_REC_Msk = 0xf0000
	// Position of RSU field.
	ICM_IER_RSU_Pos = 0x14
	// Bit mask of RSU field.
	ICM_IER_RSU_Msk = 0xf00000
	// Position of URAD field.
	ICM_IER_URAD_Pos = 0x18
	// Bit mask of URAD field.
	ICM_IER_URAD_Msk = 0x1000000
	// Bit URAD.
	ICM_IER_URAD = 0x1000000

	// IDR: Interrupt Disable
	// Position of RHC field.
	ICM_IDR_RHC_Pos = 0x0
	// Bit mask of RHC field.
	ICM_IDR_RHC_Msk = 0xf
	// Position of RDM field.
	ICM_IDR_RDM_Pos = 0x4
	// Bit mask of RDM field.
	ICM_IDR_RDM_Msk = 0xf0
	// Position of RBE field.
	ICM_IDR_RBE_Pos = 0x8
	// Bit mask of RBE field.
	ICM_IDR_RBE_Msk = 0xf00
	// Position of RWC field.
	ICM_IDR_RWC_Pos = 0xc
	// Bit mask of RWC field.
	ICM_IDR_RWC_Msk = 0xf000
	// Position of REC field.
	ICM_IDR_REC_Pos = 0x10
	// Bit mask of REC field.
	ICM_IDR_REC_Msk = 0xf0000
	// Position of RSU field.
	ICM_IDR_RSU_Pos = 0x14
	// Bit mask of RSU field.
	ICM_IDR_RSU_Msk = 0xf00000
	// Position of URAD field.
	ICM_IDR_URAD_Pos = 0x18
	// Bit mask of URAD field.
	ICM_IDR_URAD_Msk = 0x1000000
	// Bit URAD.
	ICM_IDR_URAD = 0x1000000

	// IMR: Interrupt Mask
	// Position of RHC field.
	ICM_IMR_RHC_Pos = 0x0
	// Bit mask of RHC field.
	ICM_IMR_RHC_Msk = 0xf
	// Position of RDM field.
	ICM_IMR_RDM_Pos = 0x4
	// Bit mask of RDM field.
	ICM_IMR_RDM_Msk = 0xf0
	// Position of RBE field.
	ICM_IMR_RBE_Pos = 0x8
	// Bit mask of RBE field.
	ICM_IMR_RBE_Msk = 0xf00
	// Position of RWC field.
	ICM_IMR_RWC_Pos = 0xc
	// Bit mask of RWC field.
	ICM_IMR_RWC_Msk = 0xf000
	// Position of REC field.
	ICM_IMR_REC_Pos = 0x10
	// Bit mask of REC field.
	ICM_IMR_REC_Msk = 0xf0000
	// Position of RSU field.
	ICM_IMR_RSU_Pos = 0x14
	// Bit mask of RSU field.
	ICM_IMR_RSU_Msk = 0xf00000
	// Position of URAD field.
	ICM_IMR_URAD_Pos = 0x18
	// Bit mask of URAD field.
	ICM_IMR_URAD_Msk = 0x1000000
	// Bit URAD.
	ICM_IMR_URAD = 0x1000000

	// ISR: Interrupt Status
	// Position of RHC field.
	ICM_ISR_RHC_Pos = 0x0
	// Bit mask of RHC field.
	ICM_ISR_RHC_Msk = 0xf
	// Position of RDM field.
	ICM_ISR_RDM_Pos = 0x4
	// Bit mask of RDM field.
	ICM_ISR_RDM_Msk = 0xf0
	// Position of RBE field.
	ICM_ISR_RBE_Pos = 0x8
	// Bit mask of RBE field.
	ICM_ISR_RBE_Msk = 0xf00
	// Position of RWC field.
	ICM_ISR_RWC_Pos = 0xc
	// Bit mask of RWC field.
	ICM_ISR_RWC_Msk = 0xf000
	// Position of REC field.
	ICM_ISR_REC_Pos = 0x10
	// Bit mask of REC field.
	ICM_ISR_REC_Msk = 0xf0000
	// Position of RSU field.
	ICM_ISR_RSU_Pos = 0x14
	// Bit mask of RSU field.
	ICM_ISR_RSU_Msk = 0xf00000
	// Position of URAD field.
	ICM_ISR_URAD_Pos = 0x18
	// Bit mask of URAD field.
	ICM_ISR_URAD_Msk = 0x1000000
	// Bit URAD.
	ICM_ISR_URAD = 0x1000000

	// UASR: Undefined Access Status
	// Position of URAT field.
	ICM_UASR_URAT_Pos = 0x0
	// Bit mask of URAT field.
	ICM_UASR_URAT_Msk = 0x7
	// Unspecified structure member set to one detected when the descriptor is loaded
	ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER = 0x0
	// CFG modified during active monitoring
	ICM_UASR_URAT_CFG_MODIFIED = 0x1
	// DSCR modified during active monitoring
	ICM_UASR_URAT_DSCR_MODIFIED = 0x2
	// HASH modified during active monitoring
	ICM_UASR_URAT_HASH_MODIFIED = 0x3
	// Write-only register read access
	ICM_UASR_URAT_READ_ACCESS = 0x4

	// DSCR: Region Descriptor Area Start Address
	// Position of DASA field.
	ICM_DSCR_DASA_Pos = 0x6
	// Bit mask of DASA field.
	ICM_DSCR_DASA_Msk = 0xffffffc0

	// HASH: Region Hash Area Start Address
	// Position of HASA field.
	ICM_HASH_HASA_Pos = 0x7
	// Bit mask of HASA field.
	ICM_HASH_HASA_Msk = 0xffffff80

	// UIHVAL: User Initial Hash Value n
	// Position of VAL field.
	ICM_UIHVAL_VAL_Pos = 0x0
	// Bit mask of VAL field.
	ICM_UIHVAL_VAL_Msk = 0xffffffff
)

// Bitfields for I2S: Inter-IC Sound Interface
const (
	// CTRLA: Control A
	// Position of SWRST field.
	I2S_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	I2S_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	I2S_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	I2S_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	I2S_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	I2S_CTRLA_ENABLE = 0x2
	// Position of CKEN0 field.
	I2S_CTRLA_CKEN0_Pos = 0x2
	// Bit mask of CKEN0 field.
	I2S_CTRLA_CKEN0_Msk = 0x4
	// Bit CKEN0.
	I2S_CTRLA_CKEN0 = 0x4
	// Position of CKEN1 field.
	I2S_CTRLA_CKEN1_Pos = 0x3
	// Bit mask of CKEN1 field.
	I2S_CTRLA_CKEN1_Msk = 0x8
	// Bit CKEN1.
	I2S_CTRLA_CKEN1 = 0x8
	// Position of TXEN field.
	I2S_CTRLA_TXEN_Pos = 0x4
	// Bit mask of TXEN field.
	I2S_CTRLA_TXEN_Msk = 0x10
	// Bit TXEN.
	I2S_CTRLA_TXEN = 0x10
	// Position of RXEN field.
	I2S_CTRLA_RXEN_Pos = 0x5
	// Bit mask of RXEN field.
	I2S_CTRLA_RXEN_Msk = 0x20
	// Bit RXEN.
	I2S_CTRLA_RXEN = 0x20

	// CLKCTRL: Clock Unit n Control
	// Position of SLOTSIZE field.
	I2S_CLKCTRL_SLOTSIZE_Pos = 0x0
	// Bit mask of SLOTSIZE field.
	I2S_CLKCTRL_SLOTSIZE_Msk = 0x3
	// 8-bit Slot for Clock Unit n
	I2S_CLKCTRL_SLOTSIZE_8 = 0x0
	// 16-bit Slot for Clock Unit n
	I2S_CLKCTRL_SLOTSIZE_16 = 0x1
	// 24-bit Slot for Clock Unit n
	I2S_CLKCTRL_SLOTSIZE_24 = 0x2
	// 32-bit Slot for Clock Unit n
	I2S_CLKCTRL_SLOTSIZE_32 = 0x3
	// Position of NBSLOTS field.
	I2S_CLKCTRL_NBSLOTS_Pos = 0x2
	// Bit mask of NBSLOTS field.
	I2S_CLKCTRL_NBSLOTS_Msk = 0x1c
	// Position of FSWIDTH field.
	I2S_CLKCTRL_FSWIDTH_Pos = 0x5
	// Bit mask of FSWIDTH field.
	I2S_CLKCTRL_FSWIDTH_Msk = 0x60
	// Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
	I2S_CLKCTRL_FSWIDTH_SLOT = 0x0
	// Frame Sync Pulse is half a Frame wide
	I2S_CLKCTRL_FSWIDTH_HALF = 0x1
	// Frame Sync Pulse is 1 Bit wide
	I2S_CLKCTRL_FSWIDTH_BIT = 0x2
	// Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
	I2S_CLKCTRL_FSWIDTH_BURST = 0x3
	// Position of BITDELAY field.
	I2S_CLKCTRL_BITDELAY_Pos = 0x7
	// Bit mask of BITDELAY field.
	I2S_CLKCTRL_BITDELAY_Msk = 0x80
	// Bit BITDELAY.
	I2S_CLKCTRL_BITDELAY = 0x80
	// Left Justified (0 Bit Delay)
	I2S_CLKCTRL_BITDELAY_LJ = 0x0
	// I2S (1 Bit Delay)
	I2S_CLKCTRL_BITDELAY_I2S = 0x1
	// Position of FSSEL field.
	I2S_CLKCTRL_FSSEL_Pos = 0x8
	// Bit mask of FSSEL field.
	I2S_CLKCTRL_FSSEL_Msk = 0x100
	// Bit FSSEL.
	I2S_CLKCTRL_FSSEL = 0x100
	// Divided Serial Clock n is used as Frame Sync n source
	I2S_CLKCTRL_FSSEL_SCKDIV = 0x0
	// FSn input pin is used as Frame Sync n source
	I2S_CLKCTRL_FSSEL_FSPIN = 0x1
	// Position of FSINV field.
	I2S_CLKCTRL_FSINV_Pos = 0x9
	// Bit mask of FSINV field.
	I2S_CLKCTRL_FSINV_Msk = 0x200
	// Bit FSINV.
	I2S_CLKCTRL_FSINV = 0x200
	// Position of FSOUTINV field.
	I2S_CLKCTRL_FSOUTINV_Pos = 0xa
	// Bit mask of FSOUTINV field.
	I2S_CLKCTRL_FSOUTINV_Msk = 0x400
	// Bit FSOUTINV.
	I2S_CLKCTRL_FSOUTINV = 0x400
	// Position of SCKSEL field.
	I2S_CLKCTRL_SCKSEL_Pos = 0xb
	// Bit mask of SCKSEL field.
	I2S_CLKCTRL_SCKSEL_Msk = 0x800
	// Bit SCKSEL.
	I2S_CLKCTRL_SCKSEL = 0x800
	// Divided Master Clock n is used as Serial Clock n source
	I2S_CLKCTRL_SCKSEL_MCKDIV = 0x0
	// SCKn input pin is used as Serial Clock n source
	I2S_CLKCTRL_SCKSEL_SCKPIN = 0x1
	// Position of SCKOUTINV field.
	I2S_CLKCTRL_SCKOUTINV_Pos = 0xc
	// Bit mask of SCKOUTINV field.
	I2S_CLKCTRL_SCKOUTINV_Msk = 0x1000
	// Bit SCKOUTINV.
	I2S_CLKCTRL_SCKOUTINV = 0x1000
	// Position of MCKSEL field.
	I2S_CLKCTRL_MCKSEL_Pos = 0xd
	// Bit mask of MCKSEL field.
	I2S_CLKCTRL_MCKSEL_Msk = 0x2000
	// Bit MCKSEL.
	I2S_CLKCTRL_MCKSEL = 0x2000
	// GCLK_I2S_n is used as Master Clock n source
	I2S_CLKCTRL_MCKSEL_GCLK = 0x0
	// MCKn input pin is used as Master Clock n source
	I2S_CLKCTRL_MCKSEL_MCKPIN = 0x1
	// Position of MCKEN field.
	I2S_CLKCTRL_MCKEN_Pos = 0xe
	// Bit mask of MCKEN field.
	I2S_CLKCTRL_MCKEN_Msk = 0x4000
	// Bit MCKEN.
	I2S_CLKCTRL_MCKEN = 0x4000
	// Position of MCKOUTINV field.
	I2S_CLKCTRL_MCKOUTINV_Pos = 0xf
	// Bit mask of MCKOUTINV field.
	I2S_CLKCTRL_MCKOUTINV_Msk = 0x8000
	// Bit MCKOUTINV.
	I2S_CLKCTRL_MCKOUTINV = 0x8000
	// Position of MCKDIV field.
	I2S_CLKCTRL_MCKDIV_Pos = 0x10
	// Bit mask of MCKDIV field.
	I2S_CLKCTRL_MCKDIV_Msk = 0x3f0000
	// Position of MCKOUTDIV field.
	I2S_CLKCTRL_MCKOUTDIV_Pos = 0x18
	// Bit mask of MCKOUTDIV field.
	I2S_CLKCTRL_MCKOUTDIV_Msk = 0x3f000000

	// INTENCLR: Interrupt Enable Clear
	// Position of RXRDY0 field.
	I2S_INTENCLR_RXRDY0_Pos = 0x0
	// Bit mask of RXRDY0 field.
	I2S_INTENCLR_RXRDY0_Msk = 0x1
	// Bit RXRDY0.
	I2S_INTENCLR_RXRDY0 = 0x1
	// Position of RXRDY1 field.
	I2S_INTENCLR_RXRDY1_Pos = 0x1
	// Bit mask of RXRDY1 field.
	I2S_INTENCLR_RXRDY1_Msk = 0x2
	// Bit RXRDY1.
	I2S_INTENCLR_RXRDY1 = 0x2
	// Position of RXOR0 field.
	I2S_INTENCLR_RXOR0_Pos = 0x4
	// Bit mask of RXOR0 field.
	I2S_INTENCLR_RXOR0_Msk = 0x10
	// Bit RXOR0.
	I2S_INTENCLR_RXOR0 = 0x10
	// Position of RXOR1 field.
	I2S_INTENCLR_RXOR1_Pos = 0x5
	// Bit mask of RXOR1 field.
	I2S_INTENCLR_RXOR1_Msk = 0x20
	// Bit RXOR1.
	I2S_INTENCLR_RXOR1 = 0x20
	// Position of TXRDY0 field.
	I2S_INTENCLR_TXRDY0_Pos = 0x8
	// Bit mask of TXRDY0 field.
	I2S_INTENCLR_TXRDY0_Msk = 0x100
	// Bit TXRDY0.
	I2S_INTENCLR_TXRDY0 = 0x100
	// Position of TXRDY1 field.
	I2S_INTENCLR_TXRDY1_Pos = 0x9
	// Bit mask of TXRDY1 field.
	I2S_INTENCLR_TXRDY1_Msk = 0x200
	// Bit TXRDY1.
	I2S_INTENCLR_TXRDY1 = 0x200
	// Position of TXUR0 field.
	I2S_INTENCLR_TXUR0_Pos = 0xc
	// Bit mask of TXUR0 field.
	I2S_INTENCLR_TXUR0_Msk = 0x1000
	// Bit TXUR0.
	I2S_INTENCLR_TXUR0 = 0x1000
	// Position of TXUR1 field.
	I2S_INTENCLR_TXUR1_Pos = 0xd
	// Bit mask of TXUR1 field.
	I2S_INTENCLR_TXUR1_Msk = 0x2000
	// Bit TXUR1.
	I2S_INTENCLR_TXUR1 = 0x2000

	// INTENSET: Interrupt Enable Set
	// Position of RXRDY0 field.
	I2S_INTENSET_RXRDY0_Pos = 0x0
	// Bit mask of RXRDY0 field.
	I2S_INTENSET_RXRDY0_Msk = 0x1
	// Bit RXRDY0.
	I2S_INTENSET_RXRDY0 = 0x1
	// Position of RXRDY1 field.
	I2S_INTENSET_RXRDY1_Pos = 0x1
	// Bit mask of RXRDY1 field.
	I2S_INTENSET_RXRDY1_Msk = 0x2
	// Bit RXRDY1.
	I2S_INTENSET_RXRDY1 = 0x2
	// Position of RXOR0 field.
	I2S_INTENSET_RXOR0_Pos = 0x4
	// Bit mask of RXOR0 field.
	I2S_INTENSET_RXOR0_Msk = 0x10
	// Bit RXOR0.
	I2S_INTENSET_RXOR0 = 0x10
	// Position of RXOR1 field.
	I2S_INTENSET_RXOR1_Pos = 0x5
	// Bit mask of RXOR1 field.
	I2S_INTENSET_RXOR1_Msk = 0x20
	// Bit RXOR1.
	I2S_INTENSET_RXOR1 = 0x20
	// Position of TXRDY0 field.
	I2S_INTENSET_TXRDY0_Pos = 0x8
	// Bit mask of TXRDY0 field.
	I2S_INTENSET_TXRDY0_Msk = 0x100
	// Bit TXRDY0.
	I2S_INTENSET_TXRDY0 = 0x100
	// Position of TXRDY1 field.
	I2S_INTENSET_TXRDY1_Pos = 0x9
	// Bit mask of TXRDY1 field.
	I2S_INTENSET_TXRDY1_Msk = 0x200
	// Bit TXRDY1.
	I2S_INTENSET_TXRDY1 = 0x200
	// Position of TXUR0 field.
	I2S_INTENSET_TXUR0_Pos = 0xc
	// Bit mask of TXUR0 field.
	I2S_INTENSET_TXUR0_Msk = 0x1000
	// Bit TXUR0.
	I2S_INTENSET_TXUR0 = 0x1000
	// Position of TXUR1 field.
	I2S_INTENSET_TXUR1_Pos = 0xd
	// Bit mask of TXUR1 field.
	I2S_INTENSET_TXUR1_Msk = 0x2000
	// Bit TXUR1.
	I2S_INTENSET_TXUR1 = 0x2000

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of RXRDY0 field.
	I2S_INTFLAG_RXRDY0_Pos = 0x0
	// Bit mask of RXRDY0 field.
	I2S_INTFLAG_RXRDY0_Msk = 0x1
	// Bit RXRDY0.
	I2S_INTFLAG_RXRDY0 = 0x1
	// Position of RXRDY1 field.
	I2S_INTFLAG_RXRDY1_Pos = 0x1
	// Bit mask of RXRDY1 field.
	I2S_INTFLAG_RXRDY1_Msk = 0x2
	// Bit RXRDY1.
	I2S_INTFLAG_RXRDY1 = 0x2
	// Position of RXOR0 field.
	I2S_INTFLAG_RXOR0_Pos = 0x4
	// Bit mask of RXOR0 field.
	I2S_INTFLAG_RXOR0_Msk = 0x10
	// Bit RXOR0.
	I2S_INTFLAG_RXOR0 = 0x10
	// Position of RXOR1 field.
	I2S_INTFLAG_RXOR1_Pos = 0x5
	// Bit mask of RXOR1 field.
	I2S_INTFLAG_RXOR1_Msk = 0x20
	// Bit RXOR1.
	I2S_INTFLAG_RXOR1 = 0x20
	// Position of TXRDY0 field.
	I2S_INTFLAG_TXRDY0_Pos = 0x8
	// Bit mask of TXRDY0 field.
	I2S_INTFLAG_TXRDY0_Msk = 0x100
	// Bit TXRDY0.
	I2S_INTFLAG_TXRDY0 = 0x100
	// Position of TXRDY1 field.
	I2S_INTFLAG_TXRDY1_Pos = 0x9
	// Bit mask of TXRDY1 field.
	I2S_INTFLAG_TXRDY1_Msk = 0x200
	// Bit TXRDY1.
	I2S_INTFLAG_TXRDY1 = 0x200
	// Position of TXUR0 field.
	I2S_INTFLAG_TXUR0_Pos = 0xc
	// Bit mask of TXUR0 field.
	I2S_INTFLAG_TXUR0_Msk = 0x1000
	// Bit TXUR0.
	I2S_INTFLAG_TXUR0 = 0x1000
	// Position of TXUR1 field.
	I2S_INTFLAG_TXUR1_Pos = 0xd
	// Bit mask of TXUR1 field.
	I2S_INTFLAG_TXUR1_Msk = 0x2000
	// Bit TXUR1.
	I2S_INTFLAG_TXUR1 = 0x2000

	// SYNCBUSY: Synchronization Status
	// Position of SWRST field.
	I2S_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	I2S_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	I2S_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	I2S_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	I2S_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	I2S_SYNCBUSY_ENABLE = 0x2
	// Position of CKEN0 field.
	I2S_SYNCBUSY_CKEN0_Pos = 0x2
	// Bit mask of CKEN0 field.
	I2S_SYNCBUSY_CKEN0_Msk = 0x4
	// Bit CKEN0.
	I2S_SYNCBUSY_CKEN0 = 0x4
	// Position of CKEN1 field.
	I2S_SYNCBUSY_CKEN1_Pos = 0x3
	// Bit mask of CKEN1 field.
	I2S_SYNCBUSY_CKEN1_Msk = 0x8
	// Bit CKEN1.
	I2S_SYNCBUSY_CKEN1 = 0x8
	// Position of TXEN field.
	I2S_SYNCBUSY_TXEN_Pos = 0x4
	// Bit mask of TXEN field.
	I2S_SYNCBUSY_TXEN_Msk = 0x10
	// Bit TXEN.
	I2S_SYNCBUSY_TXEN = 0x10
	// Position of RXEN field.
	I2S_SYNCBUSY_RXEN_Pos = 0x5
	// Bit mask of RXEN field.
	I2S_SYNCBUSY_RXEN_Msk = 0x20
	// Bit RXEN.
	I2S_SYNCBUSY_RXEN = 0x20
	// Position of TXDATA field.
	I2S_SYNCBUSY_TXDATA_Pos = 0x8
	// Bit mask of TXDATA field.
	I2S_SYNCBUSY_TXDATA_Msk = 0x100
	// Bit TXDATA.
	I2S_SYNCBUSY_TXDATA = 0x100
	// Position of RXDATA field.
	I2S_SYNCBUSY_RXDATA_Pos = 0x9
	// Bit mask of RXDATA field.
	I2S_SYNCBUSY_RXDATA_Msk = 0x200
	// Bit RXDATA.
	I2S_SYNCBUSY_RXDATA = 0x200

	// TXCTRL: Tx Serializer Control
	// Position of SERMODE field.
	I2S_TXCTRL_SERMODE_Pos = 0x0
	// Bit mask of SERMODE field.
	I2S_TXCTRL_SERMODE_Msk = 0x3
	// Receive
	I2S_TXCTRL_SERMODE_RX = 0x0
	// Transmit
	I2S_TXCTRL_SERMODE_TX = 0x1
	// Receive one PDM data on each serial clock edge
	I2S_TXCTRL_SERMODE_PDM2 = 0x2
	// Position of TXDEFAULT field.
	I2S_TXCTRL_TXDEFAULT_Pos = 0x2
	// Bit mask of TXDEFAULT field.
	I2S_TXCTRL_TXDEFAULT_Msk = 0xc
	// Output Default Value is 0
	I2S_TXCTRL_TXDEFAULT_ZERO = 0x0
	// Output Default Value is 1
	I2S_TXCTRL_TXDEFAULT_ONE = 0x1
	// Output Default Value is high impedance
	I2S_TXCTRL_TXDEFAULT_HIZ = 0x3
	// Position of TXSAME field.
	I2S_TXCTRL_TXSAME_Pos = 0x4
	// Bit mask of TXSAME field.
	I2S_TXCTRL_TXSAME_Msk = 0x10
	// Bit TXSAME.
	I2S_TXCTRL_TXSAME = 0x10
	// Zero data transmitted in case of underrun
	I2S_TXCTRL_TXSAME_ZERO = 0x0
	// Last data transmitted in case of underrun
	I2S_TXCTRL_TXSAME_SAME = 0x1
	// Position of CLKSEL field.
	I2S_TXCTRL_CLKSEL_Pos = 0x5
	// Bit mask of CLKSEL field.
	I2S_TXCTRL_CLKSEL_Msk = 0x20
	// Bit CLKSEL.
	I2S_TXCTRL_CLKSEL = 0x20
	// Use Clock Unit 0
	I2S_TXCTRL_CLKSEL_CLK0 = 0x0
	// Use Clock Unit 1
	I2S_TXCTRL_CLKSEL_CLK1 = 0x1
	// Position of SLOTADJ field.
	I2S_TXCTRL_SLOTADJ_Pos = 0x7
	// Bit mask of SLOTADJ field.
	I2S_TXCTRL_SLOTADJ_Msk = 0x80
	// Bit SLOTADJ.
	I2S_TXCTRL_SLOTADJ = 0x80
	// Data is right adjusted in slot
	I2S_TXCTRL_SLOTADJ_RIGHT = 0x0
	// Data is left adjusted in slot
	I2S_TXCTRL_SLOTADJ_LEFT = 0x1
	// Position of DATASIZE field.
	I2S_TXCTRL_DATASIZE_Pos = 0x8
	// Bit mask of DATASIZE field.
	I2S_TXCTRL_DATASIZE_Msk = 0x700
	// 32 bits
	I2S_TXCTRL_DATASIZE_32 = 0x0
	// 24 bits
	I2S_TXCTRL_DATASIZE_24 = 0x1
	// 20 bits
	I2S_TXCTRL_DATASIZE_20 = 0x2
	// 18 bits
	I2S_TXCTRL_DATASIZE_18 = 0x3
	// 16 bits
	I2S_TXCTRL_DATASIZE_16 = 0x4
	// 16 bits compact stereo
	I2S_TXCTRL_DATASIZE_16C = 0x5
	// 8 bits
	I2S_TXCTRL_DATASIZE_8 = 0x6
	// 8 bits compact stereo
	I2S_TXCTRL_DATASIZE_8C = 0x7
	// Position of WORDADJ field.
	I2S_TXCTRL_WORDADJ_Pos = 0xc
	// Bit mask of WORDADJ field.
	I2S_TXCTRL_WORDADJ_Msk = 0x1000
	// Bit WORDADJ.
	I2S_TXCTRL_WORDADJ = 0x1000
	// Data is right adjusted in word
	I2S_TXCTRL_WORDADJ_RIGHT = 0x0
	// Data is left adjusted in word
	I2S_TXCTRL_WORDADJ_LEFT = 0x1
	// Position of EXTEND field.
	I2S_TXCTRL_EXTEND_Pos = 0xd
	// Bit mask of EXTEND field.
	I2S_TXCTRL_EXTEND_Msk = 0x6000
	// Extend with zeroes
	I2S_TXCTRL_EXTEND_ZERO = 0x0
	// Extend with ones
	I2S_TXCTRL_EXTEND_ONE = 0x1
	// Extend with Most Significant Bit
	I2S_TXCTRL_EXTEND_MSBIT = 0x2
	// Extend with Least Significant Bit
	I2S_TXCTRL_EXTEND_LSBIT = 0x3
	// Position of BITREV field.
	I2S_TXCTRL_BITREV_Pos = 0xf
	// Bit mask of BITREV field.
	I2S_TXCTRL_BITREV_Msk = 0x8000
	// Bit BITREV.
	I2S_TXCTRL_BITREV = 0x8000
	// Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
	I2S_TXCTRL_BITREV_MSBIT = 0x0
	// Transfer Data Least Significant Bit (LSB) first
	I2S_TXCTRL_BITREV_LSBIT = 0x1
	// Position of SLOTDIS0 field.
	I2S_TXCTRL_SLOTDIS0_Pos = 0x10
	// Bit mask of SLOTDIS0 field.
	I2S_TXCTRL_SLOTDIS0_Msk = 0x10000
	// Bit SLOTDIS0.
	I2S_TXCTRL_SLOTDIS0 = 0x10000
	// Position of SLOTDIS1 field.
	I2S_TXCTRL_SLOTDIS1_Pos = 0x11
	// Bit mask of SLOTDIS1 field.
	I2S_TXCTRL_SLOTDIS1_Msk = 0x20000
	// Bit SLOTDIS1.
	I2S_TXCTRL_SLOTDIS1 = 0x20000
	// Position of SLOTDIS2 field.
	I2S_TXCTRL_SLOTDIS2_Pos = 0x12
	// Bit mask of SLOTDIS2 field.
	I2S_TXCTRL_SLOTDIS2_Msk = 0x40000
	// Bit SLOTDIS2.
	I2S_TXCTRL_SLOTDIS2 = 0x40000
	// Position of SLOTDIS3 field.
	I2S_TXCTRL_SLOTDIS3_Pos = 0x13
	// Bit mask of SLOTDIS3 field.
	I2S_TXCTRL_SLOTDIS3_Msk = 0x80000
	// Bit SLOTDIS3.
	I2S_TXCTRL_SLOTDIS3 = 0x80000
	// Position of SLOTDIS4 field.
	I2S_TXCTRL_SLOTDIS4_Pos = 0x14
	// Bit mask of SLOTDIS4 field.
	I2S_TXCTRL_SLOTDIS4_Msk = 0x100000
	// Bit SLOTDIS4.
	I2S_TXCTRL_SLOTDIS4 = 0x100000
	// Position of SLOTDIS5 field.
	I2S_TXCTRL_SLOTDIS5_Pos = 0x15
	// Bit mask of SLOTDIS5 field.
	I2S_TXCTRL_SLOTDIS5_Msk = 0x200000
	// Bit SLOTDIS5.
	I2S_TXCTRL_SLOTDIS5 = 0x200000
	// Position of SLOTDIS6 field.
	I2S_TXCTRL_SLOTDIS6_Pos = 0x16
	// Bit mask of SLOTDIS6 field.
	I2S_TXCTRL_SLOTDIS6_Msk = 0x400000
	// Bit SLOTDIS6.
	I2S_TXCTRL_SLOTDIS6 = 0x400000
	// Position of SLOTDIS7 field.
	I2S_TXCTRL_SLOTDIS7_Pos = 0x17
	// Bit mask of SLOTDIS7 field.
	I2S_TXCTRL_SLOTDIS7_Msk = 0x800000
	// Bit SLOTDIS7.
	I2S_TXCTRL_SLOTDIS7 = 0x800000
	// Position of MONO field.
	I2S_TXCTRL_MONO_Pos = 0x18
	// Bit mask of MONO field.
	I2S_TXCTRL_MONO_Msk = 0x1000000
	// Bit MONO.
	I2S_TXCTRL_MONO = 0x1000000
	// Normal mode
	I2S_TXCTRL_MONO_STEREO = 0x0
	// Left channel data is duplicated to right channel
	I2S_TXCTRL_MONO_MONO = 0x1
	// Position of DMA field.
	I2S_TXCTRL_DMA_Pos = 0x19
	// Bit mask of DMA field.
	I2S_TXCTRL_DMA_Msk = 0x2000000
	// Bit DMA.
	I2S_TXCTRL_DMA = 0x2000000
	// Single DMA channel
	I2S_TXCTRL_DMA_SINGLE = 0x0
	// One DMA channel per data channel
	I2S_TXCTRL_DMA_MULTIPLE = 0x1

	// RXCTRL: Rx Serializer Control
	// Position of SERMODE field.
	I2S_RXCTRL_SERMODE_Pos = 0x0
	// Bit mask of SERMODE field.
	I2S_RXCTRL_SERMODE_Msk = 0x3
	// Receive
	I2S_RXCTRL_SERMODE_RX = 0x0
	// Receive one PDM data on each serial clock edge
	I2S_RXCTRL_SERMODE_PDM2 = 0x2
	// Position of CLKSEL field.
	I2S_RXCTRL_CLKSEL_Pos = 0x5
	// Bit mask of CLKSEL field.
	I2S_RXCTRL_CLKSEL_Msk = 0x20
	// Bit CLKSEL.
	I2S_RXCTRL_CLKSEL = 0x20
	// Use Clock Unit 0
	I2S_RXCTRL_CLKSEL_CLK0 = 0x0
	// Use Clock Unit 1
	I2S_RXCTRL_CLKSEL_CLK1 = 0x1
	// Position of SLOTADJ field.
	I2S_RXCTRL_SLOTADJ_Pos = 0x7
	// Bit mask of SLOTADJ field.
	I2S_RXCTRL_SLOTADJ_Msk = 0x80
	// Bit SLOTADJ.
	I2S_RXCTRL_SLOTADJ = 0x80
	// Data is right adjusted in slot
	I2S_RXCTRL_SLOTADJ_RIGHT = 0x0
	// Data is left adjusted in slot
	I2S_RXCTRL_SLOTADJ_LEFT = 0x1
	// Position of DATASIZE field.
	I2S_RXCTRL_DATASIZE_Pos = 0x8
	// Bit mask of DATASIZE field.
	I2S_RXCTRL_DATASIZE_Msk = 0x700
	// 32 bits
	I2S_RXCTRL_DATASIZE_32 = 0x0
	// 24 bits
	I2S_RXCTRL_DATASIZE_24 = 0x1
	// 20 bits
	I2S_RXCTRL_DATASIZE_20 = 0x2
	// 18 bits
	I2S_RXCTRL_DATASIZE_18 = 0x3
	// 16 bits
	I2S_RXCTRL_DATASIZE_16 = 0x4
	// 16 bits compact stereo
	I2S_RXCTRL_DATASIZE_16C = 0x5
	// 8 bits
	I2S_RXCTRL_DATASIZE_8 = 0x6
	// 8 bits compact stereo
	I2S_RXCTRL_DATASIZE_8C = 0x7
	// Position of WORDADJ field.
	I2S_RXCTRL_WORDADJ_Pos = 0xc
	// Bit mask of WORDADJ field.
	I2S_RXCTRL_WORDADJ_Msk = 0x1000
	// Bit WORDADJ.
	I2S_RXCTRL_WORDADJ = 0x1000
	// Data is right adjusted in word
	I2S_RXCTRL_WORDADJ_RIGHT = 0x0
	// Data is left adjusted in word
	I2S_RXCTRL_WORDADJ_LEFT = 0x1
	// Position of EXTEND field.
	I2S_RXCTRL_EXTEND_Pos = 0xd
	// Bit mask of EXTEND field.
	I2S_RXCTRL_EXTEND_Msk = 0x6000
	// Extend with zeroes
	I2S_RXCTRL_EXTEND_ZERO = 0x0
	// Extend with ones
	I2S_RXCTRL_EXTEND_ONE = 0x1
	// Extend with Most Significant Bit
	I2S_RXCTRL_EXTEND_MSBIT = 0x2
	// Extend with Least Significant Bit
	I2S_RXCTRL_EXTEND_LSBIT = 0x3
	// Position of BITREV field.
	I2S_RXCTRL_BITREV_Pos = 0xf
	// Bit mask of BITREV field.
	I2S_RXCTRL_BITREV_Msk = 0x8000
	// Bit BITREV.
	I2S_RXCTRL_BITREV = 0x8000
	// Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
	I2S_RXCTRL_BITREV_MSBIT = 0x0
	// Transfer Data Least Significant Bit (LSB) first
	I2S_RXCTRL_BITREV_LSBIT = 0x1
	// Position of SLOTDIS0 field.
	I2S_RXCTRL_SLOTDIS0_Pos = 0x10
	// Bit mask of SLOTDIS0 field.
	I2S_RXCTRL_SLOTDIS0_Msk = 0x10000
	// Bit SLOTDIS0.
	I2S_RXCTRL_SLOTDIS0 = 0x10000
	// Position of SLOTDIS1 field.
	I2S_RXCTRL_SLOTDIS1_Pos = 0x11
	// Bit mask of SLOTDIS1 field.
	I2S_RXCTRL_SLOTDIS1_Msk = 0x20000
	// Bit SLOTDIS1.
	I2S_RXCTRL_SLOTDIS1 = 0x20000
	// Position of SLOTDIS2 field.
	I2S_RXCTRL_SLOTDIS2_Pos = 0x12
	// Bit mask of SLOTDIS2 field.
	I2S_RXCTRL_SLOTDIS2_Msk = 0x40000
	// Bit SLOTDIS2.
	I2S_RXCTRL_SLOTDIS2 = 0x40000
	// Position of SLOTDIS3 field.
	I2S_RXCTRL_SLOTDIS3_Pos = 0x13
	// Bit mask of SLOTDIS3 field.
	I2S_RXCTRL_SLOTDIS3_Msk = 0x80000
	// Bit SLOTDIS3.
	I2S_RXCTRL_SLOTDIS3 = 0x80000
	// Position of SLOTDIS4 field.
	I2S_RXCTRL_SLOTDIS4_Pos = 0x14
	// Bit mask of SLOTDIS4 field.
	I2S_RXCTRL_SLOTDIS4_Msk = 0x100000
	// Bit SLOTDIS4.
	I2S_RXCTRL_SLOTDIS4 = 0x100000
	// Position of SLOTDIS5 field.
	I2S_RXCTRL_SLOTDIS5_Pos = 0x15
	// Bit mask of SLOTDIS5 field.
	I2S_RXCTRL_SLOTDIS5_Msk = 0x200000
	// Bit SLOTDIS5.
	I2S_RXCTRL_SLOTDIS5 = 0x200000
	// Position of SLOTDIS6 field.
	I2S_RXCTRL_SLOTDIS6_Pos = 0x16
	// Bit mask of SLOTDIS6 field.
	I2S_RXCTRL_SLOTDIS6_Msk = 0x400000
	// Bit SLOTDIS6.
	I2S_RXCTRL_SLOTDIS6 = 0x400000
	// Position of SLOTDIS7 field.
	I2S_RXCTRL_SLOTDIS7_Pos = 0x17
	// Bit mask of SLOTDIS7 field.
	I2S_RXCTRL_SLOTDIS7_Msk = 0x800000
	// Bit SLOTDIS7.
	I2S_RXCTRL_SLOTDIS7 = 0x800000
	// Position of MONO field.
	I2S_RXCTRL_MONO_Pos = 0x18
	// Bit mask of MONO field.
	I2S_RXCTRL_MONO_Msk = 0x1000000
	// Bit MONO.
	I2S_RXCTRL_MONO = 0x1000000
	// Normal mode
	I2S_RXCTRL_MONO_STEREO = 0x0
	// Left channel data is duplicated to right channel
	I2S_RXCTRL_MONO_MONO = 0x1
	// Position of DMA field.
	I2S_RXCTRL_DMA_Pos = 0x19
	// Bit mask of DMA field.
	I2S_RXCTRL_DMA_Msk = 0x2000000
	// Bit DMA.
	I2S_RXCTRL_DMA = 0x2000000
	// Single DMA channel
	I2S_RXCTRL_DMA_SINGLE = 0x0
	// One DMA channel per data channel
	I2S_RXCTRL_DMA_MULTIPLE = 0x1
	// Position of RXLOOP field.
	I2S_RXCTRL_RXLOOP_Pos = 0x1a
	// Bit mask of RXLOOP field.
	I2S_RXCTRL_RXLOOP_Msk = 0x4000000
	// Bit RXLOOP.
	I2S_RXCTRL_RXLOOP = 0x4000000

	// TXDATA: Tx Data
	// Position of DATA field.
	I2S_TXDATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	I2S_TXDATA_DATA_Msk = 0xffffffff

	// RXDATA: Rx Data
	// Position of DATA field.
	I2S_RXDATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	I2S_RXDATA_DATA_Msk = 0xffffffff
)

// Bitfields for MCLK: Main Clock
const (
	// INTENCLR: Interrupt Enable Clear
	// Position of CKRDY field.
	MCLK_INTENCLR_CKRDY_Pos = 0x0
	// Bit mask of CKRDY field.
	MCLK_INTENCLR_CKRDY_Msk = 0x1
	// Bit CKRDY.
	MCLK_INTENCLR_CKRDY = 0x1

	// INTENSET: Interrupt Enable Set
	// Position of CKRDY field.
	MCLK_INTENSET_CKRDY_Pos = 0x0
	// Bit mask of CKRDY field.
	MCLK_INTENSET_CKRDY_Msk = 0x1
	// Bit CKRDY.
	MCLK_INTENSET_CKRDY = 0x1

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of CKRDY field.
	MCLK_INTFLAG_CKRDY_Pos = 0x0
	// Bit mask of CKRDY field.
	MCLK_INTFLAG_CKRDY_Msk = 0x1
	// Bit CKRDY.
	MCLK_INTFLAG_CKRDY = 0x1

	// HSDIV: HS Clock Division
	// Position of DIV field.
	MCLK_HSDIV_DIV_Pos = 0x0
	// Bit mask of DIV field.
	MCLK_HSDIV_DIV_Msk = 0xff
	// Divide by 1
	MCLK_HSDIV_DIV_DIV1 = 0x1

	// CPUDIV: CPU Clock Division
	// Position of DIV field.
	MCLK_CPUDIV_DIV_Pos = 0x0
	// Bit mask of DIV field.
	MCLK_CPUDIV_DIV_Msk = 0xff
	// Divide by 1
	MCLK_CPUDIV_DIV_DIV1 = 0x1
	// Divide by 2
	MCLK_CPUDIV_DIV_DIV2 = 0x2
	// Divide by 4
	MCLK_CPUDIV_DIV_DIV4 = 0x4
	// Divide by 8
	MCLK_CPUDIV_DIV_DIV8 = 0x8
	// Divide by 16
	MCLK_CPUDIV_DIV_DIV16 = 0x10
	// Divide by 32
	MCLK_CPUDIV_DIV_DIV32 = 0x20
	// Divide by 64
	MCLK_CPUDIV_DIV_DIV64 = 0x40
	// Divide by 128
	MCLK_CPUDIV_DIV_DIV128 = 0x80

	// AHBMASK: AHB Mask
	// Position of HPB0_ field.
	MCLK_AHBMASK_HPB0__Pos = 0x0
	// Bit mask of HPB0_ field.
	MCLK_AHBMASK_HPB0__Msk = 0x1
	// Bit HPB0_.
	MCLK_AHBMASK_HPB0_ = 0x1
	// Position of HPB1_ field.
	MCLK_AHBMASK_HPB1__Pos = 0x1
	// Bit mask of HPB1_ field.
	MCLK_AHBMASK_HPB1__Msk = 0x2
	// Bit HPB1_.
	MCLK_AHBMASK_HPB1_ = 0x2
	// Position of HPB2_ field.
	MCLK_AHBMASK_HPB2__Pos = 0x2
	// Bit mask of HPB2_ field.
	MCLK_AHBMASK_HPB2__Msk = 0x4
	// Bit HPB2_.
	MCLK_AHBMASK_HPB2_ = 0x4
	// Position of HPB3_ field.
	MCLK_AHBMASK_HPB3__Pos = 0x3
	// Bit mask of HPB3_ field.
	MCLK_AHBMASK_HPB3__Msk = 0x8
	// Bit HPB3_.
	MCLK_AHBMASK_HPB3_ = 0x8
	// Position of DSU_ field.
	MCLK_AHBMASK_DSU__Pos = 0x4
	// Bit mask of DSU_ field.
	MCLK_AHBMASK_DSU__Msk = 0x10
	// Bit DSU_.
	MCLK_AHBMASK_DSU_ = 0x10
	// Position of HMATRIX_ field.
	MCLK_AHBMASK_HMATRIX__Pos = 0x5
	// Bit mask of HMATRIX_ field.
	MCLK_AHBMASK_HMATRIX__Msk = 0x20
	// Bit HMATRIX_.
	MCLK_AHBMASK_HMATRIX_ = 0x20
	// Position of NVMCTRL_ field.
	MCLK_AHBMASK_NVMCTRL__Pos = 0x6
	// Bit mask of NVMCTRL_ field.
	MCLK_AHBMASK_NVMCTRL__Msk = 0x40
	// Bit NVMCTRL_.
	MCLK_AHBMASK_NVMCTRL_ = 0x40
	// Position of HSRAM_ field.
	MCLK_AHBMASK_HSRAM__Pos = 0x7
	// Bit mask of HSRAM_ field.
	MCLK_AHBMASK_HSRAM__Msk = 0x80
	// Bit HSRAM_.
	MCLK_AHBMASK_HSRAM_ = 0x80
	// Position of CMCC_ field.
	MCLK_AHBMASK_CMCC__Pos = 0x8
	// Bit mask of CMCC_ field.
	MCLK_AHBMASK_CMCC__Msk = 0x100
	// Bit CMCC_.
	MCLK_AHBMASK_CMCC_ = 0x100
	// Position of DMAC_ field.
	MCLK_AHBMASK_DMAC__Pos = 0x9
	// Bit mask of DMAC_ field.
	MCLK_AHBMASK_DMAC__Msk = 0x200
	// Bit DMAC_.
	MCLK_AHBMASK_DMAC_ = 0x200
	// Position of USB_ field.
	MCLK_AHBMASK_USB__Pos = 0xa
	// Bit mask of USB_ field.
	MCLK_AHBMASK_USB__Msk = 0x400
	// Bit USB_.
	MCLK_AHBMASK_USB_ = 0x400
	// Position of BKUPRAM_ field.
	MCLK_AHBMASK_BKUPRAM__Pos = 0xb
	// Bit mask of BKUPRAM_ field.
	MCLK_AHBMASK_BKUPRAM__Msk = 0x800
	// Bit BKUPRAM_.
	MCLK_AHBMASK_BKUPRAM_ = 0x800
	// Position of PAC_ field.
	MCLK_AHBMASK_PAC__Pos = 0xc
	// Bit mask of PAC_ field.
	MCLK_AHBMASK_PAC__Msk = 0x1000
	// Bit PAC_.
	MCLK_AHBMASK_PAC_ = 0x1000
	// Position of QSPI_ field.
	MCLK_AHBMASK_QSPI__Pos = 0xd
	// Bit mask of QSPI_ field.
	MCLK_AHBMASK_QSPI__Msk = 0x2000
	// Bit QSPI_.
	MCLK_AHBMASK_QSPI_ = 0x2000
	// Position of GMAC_ field.
	MCLK_AHBMASK_GMAC__Pos = 0xe
	// Bit mask of GMAC_ field.
	MCLK_AHBMASK_GMAC__Msk = 0x4000
	// Bit GMAC_.
	MCLK_AHBMASK_GMAC_ = 0x4000
	// Position of SDHC0_ field.
	MCLK_AHBMASK_SDHC0__Pos = 0xf
	// Bit mask of SDHC0_ field.
	MCLK_AHBMASK_SDHC0__Msk = 0x8000
	// Bit SDHC0_.
	MCLK_AHBMASK_SDHC0_ = 0x8000
	// Position of SDHC1_ field.
	MCLK_AHBMASK_SDHC1__Pos = 0x10
	// Bit mask of SDHC1_ field.
	MCLK_AHBMASK_SDHC1__Msk = 0x10000
	// Bit SDHC1_.
	MCLK_AHBMASK_SDHC1_ = 0x10000
	// Position of CAN0_ field.
	MCLK_AHBMASK_CAN0__Pos = 0x11
	// Bit mask of CAN0_ field.
	MCLK_AHBMASK_CAN0__Msk = 0x20000
	// Bit CAN0_.
	MCLK_AHBMASK_CAN0_ = 0x20000
	// Position of CAN1_ field.
	MCLK_AHBMASK_CAN1__Pos = 0x12
	// Bit mask of CAN1_ field.
	MCLK_AHBMASK_CAN1__Msk = 0x40000
	// Bit CAN1_.
	MCLK_AHBMASK_CAN1_ = 0x40000
	// Position of ICM_ field.
	MCLK_AHBMASK_ICM__Pos = 0x13
	// Bit mask of ICM_ field.
	MCLK_AHBMASK_ICM__Msk = 0x80000
	// Bit ICM_.
	MCLK_AHBMASK_ICM_ = 0x80000
	// Position of PUKCC_ field.
	MCLK_AHBMASK_PUKCC__Pos = 0x14
	// Bit mask of PUKCC_ field.
	MCLK_AHBMASK_PUKCC__Msk = 0x100000
	// Bit PUKCC_.
	MCLK_AHBMASK_PUKCC_ = 0x100000
	// Position of QSPI_2X_ field.
	MCLK_AHBMASK_QSPI_2X__Pos = 0x15
	// Bit mask of QSPI_2X_ field.
	MCLK_AHBMASK_QSPI_2X__Msk = 0x200000
	// Bit QSPI_2X_.
	MCLK_AHBMASK_QSPI_2X_ = 0x200000
	// Position of NVMCTRL_SMEEPROM_ field.
	MCLK_AHBMASK_NVMCTRL_SMEEPROM__Pos = 0x16
	// Bit mask of NVMCTRL_SMEEPROM_ field.
	MCLK_AHBMASK_NVMCTRL_SMEEPROM__Msk = 0x400000
	// Bit NVMCTRL_SMEEPROM_.
	MCLK_AHBMASK_NVMCTRL_SMEEPROM_ = 0x400000
	// Position of NVMCTRL_CACHE_ field.
	MCLK_AHBMASK_NVMCTRL_CACHE__Pos = 0x17
	// Bit mask of NVMCTRL_CACHE_ field.
	MCLK_AHBMASK_NVMCTRL_CACHE__Msk = 0x800000
	// Bit NVMCTRL_CACHE_.
	MCLK_AHBMASK_NVMCTRL_CACHE_ = 0x800000

	// APBAMASK: APBA Mask
	// Position of PAC_ field.
	MCLK_APBAMASK_PAC__Pos = 0x0
	// Bit mask of PAC_ field.
	MCLK_APBAMASK_PAC__Msk = 0x1
	// Bit PAC_.
	MCLK_APBAMASK_PAC_ = 0x1
	// Position of PM_ field.
	MCLK_APBAMASK_PM__Pos = 0x1
	// Bit mask of PM_ field.
	MCLK_APBAMASK_PM__Msk = 0x2
	// Bit PM_.
	MCLK_APBAMASK_PM_ = 0x2
	// Position of MCLK_ field.
	MCLK_APBAMASK_MCLK__Pos = 0x2
	// Bit mask of MCLK_ field.
	MCLK_APBAMASK_MCLK__Msk = 0x4
	// Bit MCLK_.
	MCLK_APBAMASK_MCLK_ = 0x4
	// Position of RSTC_ field.
	MCLK_APBAMASK_RSTC__Pos = 0x3
	// Bit mask of RSTC_ field.
	MCLK_APBAMASK_RSTC__Msk = 0x8
	// Bit RSTC_.
	MCLK_APBAMASK_RSTC_ = 0x8
	// Position of OSCCTRL_ field.
	MCLK_APBAMASK_OSCCTRL__Pos = 0x4
	// Bit mask of OSCCTRL_ field.
	MCLK_APBAMASK_OSCCTRL__Msk = 0x10
	// Bit OSCCTRL_.
	MCLK_APBAMASK_OSCCTRL_ = 0x10
	// Position of OSC32KCTRL_ field.
	MCLK_APBAMASK_OSC32KCTRL__Pos = 0x5
	// Bit mask of OSC32KCTRL_ field.
	MCLK_APBAMASK_OSC32KCTRL__Msk = 0x20
	// Bit OSC32KCTRL_.
	MCLK_APBAMASK_OSC32KCTRL_ = 0x20
	// Position of SUPC_ field.
	MCLK_APBAMASK_SUPC__Pos = 0x6
	// Bit mask of SUPC_ field.
	MCLK_APBAMASK_SUPC__Msk = 0x40
	// Bit SUPC_.
	MCLK_APBAMASK_SUPC_ = 0x40
	// Position of GCLK_ field.
	MCLK_APBAMASK_GCLK__Pos = 0x7
	// Bit mask of GCLK_ field.
	MCLK_APBAMASK_GCLK__Msk = 0x80
	// Bit GCLK_.
	MCLK_APBAMASK_GCLK_ = 0x80
	// Position of WDT_ field.
	MCLK_APBAMASK_WDT__Pos = 0x8
	// Bit mask of WDT_ field.
	MCLK_APBAMASK_WDT__Msk = 0x100
	// Bit WDT_.
	MCLK_APBAMASK_WDT_ = 0x100
	// Position of RTC_ field.
	MCLK_APBAMASK_RTC__Pos = 0x9
	// Bit mask of RTC_ field.
	MCLK_APBAMASK_RTC__Msk = 0x200
	// Bit RTC_.
	MCLK_APBAMASK_RTC_ = 0x200
	// Position of EIC_ field.
	MCLK_APBAMASK_EIC__Pos = 0xa
	// Bit mask of EIC_ field.
	MCLK_APBAMASK_EIC__Msk = 0x400
	// Bit EIC_.
	MCLK_APBAMASK_EIC_ = 0x400
	// Position of FREQM_ field.
	MCLK_APBAMASK_FREQM__Pos = 0xb
	// Bit mask of FREQM_ field.
	MCLK_APBAMASK_FREQM__Msk = 0x800
	// Bit FREQM_.
	MCLK_APBAMASK_FREQM_ = 0x800
	// Position of SERCOM0_ field.
	MCLK_APBAMASK_SERCOM0__Pos = 0xc
	// Bit mask of SERCOM0_ field.
	MCLK_APBAMASK_SERCOM0__Msk = 0x1000
	// Bit SERCOM0_.
	MCLK_APBAMASK_SERCOM0_ = 0x1000
	// Position of SERCOM1_ field.
	MCLK_APBAMASK_SERCOM1__Pos = 0xd
	// Bit mask of SERCOM1_ field.
	MCLK_APBAMASK_SERCOM1__Msk = 0x2000
	// Bit SERCOM1_.
	MCLK_APBAMASK_SERCOM1_ = 0x2000
	// Position of TC0_ field.
	MCLK_APBAMASK_TC0__Pos = 0xe
	// Bit mask of TC0_ field.
	MCLK_APBAMASK_TC0__Msk = 0x4000
	// Bit TC0_.
	MCLK_APBAMASK_TC0_ = 0x4000
	// Position of TC1_ field.
	MCLK_APBAMASK_TC1__Pos = 0xf
	// Bit mask of TC1_ field.
	MCLK_APBAMASK_TC1__Msk = 0x8000
	// Bit TC1_.
	MCLK_APBAMASK_TC1_ = 0x8000

	// APBBMASK: APBB Mask
	// Position of USB_ field.
	MCLK_APBBMASK_USB__Pos = 0x0
	// Bit mask of USB_ field.
	MCLK_APBBMASK_USB__Msk = 0x1
	// Bit USB_.
	MCLK_APBBMASK_USB_ = 0x1
	// Position of DSU_ field.
	MCLK_APBBMASK_DSU__Pos = 0x1
	// Bit mask of DSU_ field.
	MCLK_APBBMASK_DSU__Msk = 0x2
	// Bit DSU_.
	MCLK_APBBMASK_DSU_ = 0x2
	// Position of NVMCTRL_ field.
	MCLK_APBBMASK_NVMCTRL__Pos = 0x2
	// Bit mask of NVMCTRL_ field.
	MCLK_APBBMASK_NVMCTRL__Msk = 0x4
	// Bit NVMCTRL_.
	MCLK_APBBMASK_NVMCTRL_ = 0x4
	// Position of PORT_ field.
	MCLK_APBBMASK_PORT__Pos = 0x4
	// Bit mask of PORT_ field.
	MCLK_APBBMASK_PORT__Msk = 0x10
	// Bit PORT_.
	MCLK_APBBMASK_PORT_ = 0x10
	// Position of HMATRIX_ field.
	MCLK_APBBMASK_HMATRIX__Pos = 0x6
	// Bit mask of HMATRIX_ field.
	MCLK_APBBMASK_HMATRIX__Msk = 0x40
	// Bit HMATRIX_.
	MCLK_APBBMASK_HMATRIX_ = 0x40
	// Position of EVSYS_ field.
	MCLK_APBBMASK_EVSYS__Pos = 0x7
	// Bit mask of EVSYS_ field.
	MCLK_APBBMASK_EVSYS__Msk = 0x80
	// Bit EVSYS_.
	MCLK_APBBMASK_EVSYS_ = 0x80
	// Position of SERCOM2_ field.
	MCLK_APBBMASK_SERCOM2__Pos = 0x9
	// Bit mask of SERCOM2_ field.
	MCLK_APBBMASK_SERCOM2__Msk = 0x200
	// Bit SERCOM2_.
	MCLK_APBBMASK_SERCOM2_ = 0x200
	// Position of SERCOM3_ field.
	MCLK_APBBMASK_SERCOM3__Pos = 0xa
	// Bit mask of SERCOM3_ field.
	MCLK_APBBMASK_SERCOM3__Msk = 0x400
	// Bit SERCOM3_.
	MCLK_APBBMASK_SERCOM3_ = 0x400
	// Position of TCC0_ field.
	MCLK_APBBMASK_TCC0__Pos = 0xb
	// Bit mask of TCC0_ field.
	MCLK_APBBMASK_TCC0__Msk = 0x800
	// Bit TCC0_.
	MCLK_APBBMASK_TCC0_ = 0x800
	// Position of TCC1_ field.
	MCLK_APBBMASK_TCC1__Pos = 0xc
	// Bit mask of TCC1_ field.
	MCLK_APBBMASK_TCC1__Msk = 0x1000
	// Bit TCC1_.
	MCLK_APBBMASK_TCC1_ = 0x1000
	// Position of TC2_ field.
	MCLK_APBBMASK_TC2__Pos = 0xd
	// Bit mask of TC2_ field.
	MCLK_APBBMASK_TC2__Msk = 0x2000
	// Bit TC2_.
	MCLK_APBBMASK_TC2_ = 0x2000
	// Position of TC3_ field.
	MCLK_APBBMASK_TC3__Pos = 0xe
	// Bit mask of TC3_ field.
	MCLK_APBBMASK_TC3__Msk = 0x4000
	// Bit TC3_.
	MCLK_APBBMASK_TC3_ = 0x4000
	// Position of RAMECC_ field.
	MCLK_APBBMASK_RAMECC__Pos = 0x10
	// Bit mask of RAMECC_ field.
	MCLK_APBBMASK_RAMECC__Msk = 0x10000
	// Bit RAMECC_.
	MCLK_APBBMASK_RAMECC_ = 0x10000

	// APBCMASK: APBC Mask
	// Position of GMAC_ field.
	MCLK_APBCMASK_GMAC__Pos = 0x2
	// Bit mask of GMAC_ field.
	MCLK_APBCMASK_GMAC__Msk = 0x4
	// Bit GMAC_.
	MCLK_APBCMASK_GMAC_ = 0x4
	// Position of TCC2_ field.
	MCLK_APBCMASK_TCC2__Pos = 0x3
	// Bit mask of TCC2_ field.
	MCLK_APBCMASK_TCC2__Msk = 0x8
	// Bit TCC2_.
	MCLK_APBCMASK_TCC2_ = 0x8
	// Position of TCC3_ field.
	MCLK_APBCMASK_TCC3__Pos = 0x4
	// Bit mask of TCC3_ field.
	MCLK_APBCMASK_TCC3__Msk = 0x10
	// Bit TCC3_.
	MCLK_APBCMASK_TCC3_ = 0x10
	// Position of TC4_ field.
	MCLK_APBCMASK_TC4__Pos = 0x5
	// Bit mask of TC4_ field.
	MCLK_APBCMASK_TC4__Msk = 0x20
	// Bit TC4_.
	MCLK_APBCMASK_TC4_ = 0x20
	// Position of TC5_ field.
	MCLK_APBCMASK_TC5__Pos = 0x6
	// Bit mask of TC5_ field.
	MCLK_APBCMASK_TC5__Msk = 0x40
	// Bit TC5_.
	MCLK_APBCMASK_TC5_ = 0x40
	// Position of PDEC_ field.
	MCLK_APBCMASK_PDEC__Pos = 0x7
	// Bit mask of PDEC_ field.
	MCLK_APBCMASK_PDEC__Msk = 0x80
	// Bit PDEC_.
	MCLK_APBCMASK_PDEC_ = 0x80
	// Position of AC_ field.
	MCLK_APBCMASK_AC__Pos = 0x8
	// Bit mask of AC_ field.
	MCLK_APBCMASK_AC__Msk = 0x100
	// Bit AC_.
	MCLK_APBCMASK_AC_ = 0x100
	// Position of AES_ field.
	MCLK_APBCMASK_AES__Pos = 0x9
	// Bit mask of AES_ field.
	MCLK_APBCMASK_AES__Msk = 0x200
	// Bit AES_.
	MCLK_APBCMASK_AES_ = 0x200
	// Position of TRNG_ field.
	MCLK_APBCMASK_TRNG__Pos = 0xa
	// Bit mask of TRNG_ field.
	MCLK_APBCMASK_TRNG__Msk = 0x400
	// Bit TRNG_.
	MCLK_APBCMASK_TRNG_ = 0x400
	// Position of ICM_ field.
	MCLK_APBCMASK_ICM__Pos = 0xb
	// Bit mask of ICM_ field.
	MCLK_APBCMASK_ICM__Msk = 0x800
	// Bit ICM_.
	MCLK_APBCMASK_ICM_ = 0x800
	// Position of QSPI_ field.
	MCLK_APBCMASK_QSPI__Pos = 0xd
	// Bit mask of QSPI_ field.
	MCLK_APBCMASK_QSPI__Msk = 0x2000
	// Bit QSPI_.
	MCLK_APBCMASK_QSPI_ = 0x2000
	// Position of CCL_ field.
	MCLK_APBCMASK_CCL__Pos = 0xe
	// Bit mask of CCL_ field.
	MCLK_APBCMASK_CCL__Msk = 0x4000
	// Bit CCL_.
	MCLK_APBCMASK_CCL_ = 0x4000

	// APBDMASK: APBD Mask
	// Position of SERCOM4_ field.
	MCLK_APBDMASK_SERCOM4__Pos = 0x0
	// Bit mask of SERCOM4_ field.
	MCLK_APBDMASK_SERCOM4__Msk = 0x1
	// Bit SERCOM4_.
	MCLK_APBDMASK_SERCOM4_ = 0x1
	// Position of SERCOM5_ field.
	MCLK_APBDMASK_SERCOM5__Pos = 0x1
	// Bit mask of SERCOM5_ field.
	MCLK_APBDMASK_SERCOM5__Msk = 0x2
	// Bit SERCOM5_.
	MCLK_APBDMASK_SERCOM5_ = 0x2
	// Position of SERCOM6_ field.
	MCLK_APBDMASK_SERCOM6__Pos = 0x2
	// Bit mask of SERCOM6_ field.
	MCLK_APBDMASK_SERCOM6__Msk = 0x4
	// Bit SERCOM6_.
	MCLK_APBDMASK_SERCOM6_ = 0x4
	// Position of SERCOM7_ field.
	MCLK_APBDMASK_SERCOM7__Pos = 0x3
	// Bit mask of SERCOM7_ field.
	MCLK_APBDMASK_SERCOM7__Msk = 0x8
	// Bit SERCOM7_.
	MCLK_APBDMASK_SERCOM7_ = 0x8
	// Position of TCC4_ field.
	MCLK_APBDMASK_TCC4__Pos = 0x4
	// Bit mask of TCC4_ field.
	MCLK_APBDMASK_TCC4__Msk = 0x10
	// Bit TCC4_.
	MCLK_APBDMASK_TCC4_ = 0x10
	// Position of TC6_ field.
	MCLK_APBDMASK_TC6__Pos = 0x5
	// Bit mask of TC6_ field.
	MCLK_APBDMASK_TC6__Msk = 0x20
	// Bit TC6_.
	MCLK_APBDMASK_TC6_ = 0x20
	// Position of TC7_ field.
	MCLK_APBDMASK_TC7__Pos = 0x6
	// Bit mask of TC7_ field.
	MCLK_APBDMASK_TC7__Msk = 0x40
	// Bit TC7_.
	MCLK_APBDMASK_TC7_ = 0x40
	// Position of ADC0_ field.
	MCLK_APBDMASK_ADC0__Pos = 0x7
	// Bit mask of ADC0_ field.
	MCLK_APBDMASK_ADC0__Msk = 0x80
	// Bit ADC0_.
	MCLK_APBDMASK_ADC0_ = 0x80
	// Position of ADC1_ field.
	MCLK_APBDMASK_ADC1__Pos = 0x8
	// Bit mask of ADC1_ field.
	MCLK_APBDMASK_ADC1__Msk = 0x100
	// Bit ADC1_.
	MCLK_APBDMASK_ADC1_ = 0x100
	// Position of DAC_ field.
	MCLK_APBDMASK_DAC__Pos = 0x9
	// Bit mask of DAC_ field.
	MCLK_APBDMASK_DAC__Msk = 0x200
	// Bit DAC_.
	MCLK_APBDMASK_DAC_ = 0x200
	// Position of I2S_ field.
	MCLK_APBDMASK_I2S__Pos = 0xa
	// Bit mask of I2S_ field.
	MCLK_APBDMASK_I2S__Msk = 0x400
	// Bit I2S_.
	MCLK_APBDMASK_I2S_ = 0x400
	// Position of PCC_ field.
	MCLK_APBDMASK_PCC__Pos = 0xb
	// Bit mask of PCC_ field.
	MCLK_APBDMASK_PCC__Msk = 0x800
	// Bit PCC_.
	MCLK_APBDMASK_PCC_ = 0x800
)

// Bitfields for NVMCTRL: Non-Volatile Memory Controller
const (
	// CTRLA: Control A
	// Position of AUTOWS field.
	NVMCTRL_CTRLA_AUTOWS_Pos = 0x2
	// Bit mask of AUTOWS field.
	NVMCTRL_CTRLA_AUTOWS_Msk = 0x4
	// Bit AUTOWS.
	NVMCTRL_CTRLA_AUTOWS = 0x4
	// Position of SUSPEN field.
	NVMCTRL_CTRLA_SUSPEN_Pos = 0x3
	// Bit mask of SUSPEN field.
	NVMCTRL_CTRLA_SUSPEN_Msk = 0x8
	// Bit SUSPEN.
	NVMCTRL_CTRLA_SUSPEN = 0x8
	// Position of WMODE field.
	NVMCTRL_CTRLA_WMODE_Pos = 0x4
	// Bit mask of WMODE field.
	NVMCTRL_CTRLA_WMODE_Msk = 0x30
	// Manual Write
	NVMCTRL_CTRLA_WMODE_MAN = 0x0
	// Automatic Double Word Write
	NVMCTRL_CTRLA_WMODE_ADW = 0x1
	// Automatic Quad Word
	NVMCTRL_CTRLA_WMODE_AQW = 0x2
	// Automatic Page Write
	NVMCTRL_CTRLA_WMODE_AP = 0x3
	// Position of PRM field.
	NVMCTRL_CTRLA_PRM_Pos = 0x6
	// Bit mask of PRM field.
	NVMCTRL_CTRLA_PRM_Msk = 0xc0
	// NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.
	NVMCTRL_CTRLA_PRM_SEMIAUTO = 0x0
	// NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode.
	NVMCTRL_CTRLA_PRM_FULLAUTO = 0x1
	// NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.
	NVMCTRL_CTRLA_PRM_MANUAL = 0x3
	// Position of RWS field.
	NVMCTRL_CTRLA_RWS_Pos = 0x8
	// Bit mask of RWS field.
	NVMCTRL_CTRLA_RWS_Msk = 0xf00
	// Position of AHBNS0 field.
	NVMCTRL_CTRLA_AHBNS0_Pos = 0xc
	// Bit mask of AHBNS0 field.
	NVMCTRL_CTRLA_AHBNS0_Msk = 0x1000
	// Bit AHBNS0.
	NVMCTRL_CTRLA_AHBNS0 = 0x1000
	// Position of AHBNS1 field.
	NVMCTRL_CTRLA_AHBNS1_Pos = 0xd
	// Bit mask of AHBNS1 field.
	NVMCTRL_CTRLA_AHBNS1_Msk = 0x2000
	// Bit AHBNS1.
	NVMCTRL_CTRLA_AHBNS1 = 0x2000
	// Position of CACHEDIS0 field.
	NVMCTRL_CTRLA_CACHEDIS0_Pos = 0xe
	// Bit mask of CACHEDIS0 field.
	NVMCTRL_CTRLA_CACHEDIS0_Msk = 0x4000
	// Bit CACHEDIS0.
	NVMCTRL_CTRLA_CACHEDIS0 = 0x4000
	// Position of CACHEDIS1 field.
	NVMCTRL_CTRLA_CACHEDIS1_Pos = 0xf
	// Bit mask of CACHEDIS1 field.
	NVMCTRL_CTRLA_CACHEDIS1_Msk = 0x8000
	// Bit CACHEDIS1.
	NVMCTRL_CTRLA_CACHEDIS1 = 0x8000

	// CTRLB: Control B
	// Position of CMD field.
	NVMCTRL_CTRLB_CMD_Pos = 0x0
	// Bit mask of CMD field.
	NVMCTRL_CTRLB_CMD_Msk = 0x7f
	// Erase Page - Only supported in the USER and AUX pages.
	NVMCTRL_CTRLB_CMD_EP = 0x0
	// Erase Block - Erases the block addressed by the ADDR register, not supported in the user page
	NVMCTRL_CTRLB_CMD_EB = 0x1
	// Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page
	NVMCTRL_CTRLB_CMD_WP = 0x3
	// Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register.
	NVMCTRL_CTRLB_CMD_WQW = 0x4
	// Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers
	NVMCTRL_CTRLB_CMD_SWRST = 0x10
	// Lock Region - Locks the region containing the address location in the ADDR register.
	NVMCTRL_CTRLB_CMD_LR = 0x11
	// Unlock Region - Unlocks the region containing the address location in the ADDR register.
	NVMCTRL_CTRLB_CMD_UR = 0x12
	// Sets the power reduction mode.
	NVMCTRL_CTRLB_CMD_SPRM = 0x13
	// Clears the power reduction mode.
	NVMCTRL_CTRLB_CMD_CPRM = 0x14
	// Page Buffer Clear - Clears the page buffer.
	NVMCTRL_CTRLB_CMD_PBC = 0x15
	// Set Security Bit
	NVMCTRL_CTRLB_CMD_SSB = 0x16
	// Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK
	NVMCTRL_CTRLB_CMD_BKSWRST = 0x17
	// Chip Erase Lock - DSU.CE command is not available
	NVMCTRL_CTRLB_CMD_CELCK = 0x18
	// Chip Erase Unlock - DSU.CE command is available
	NVMCTRL_CTRLB_CMD_CEULCK = 0x19
	// Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence
	NVMCTRL_CTRLB_CMD_SBPDIS = 0x1a
	// Clears STATUS.BPDIS, Boot loader protection is not discarded
	NVMCTRL_CTRLB_CMD_CBPDIS = 0x1b
	// Activate SmartEEPROM Sector 0, deactivate Sector 1
	NVMCTRL_CTRLB_CMD_ASEES0 = 0x30
	// Activate SmartEEPROM Sector 1, deactivate Sector 0
	NVMCTRL_CTRLB_CMD_ASEES1 = 0x31
	// Starts SmartEEPROM sector reallocation algorithm
	NVMCTRL_CTRLB_CMD_SEERALOC = 0x32
	// Flush SMEE data when in buffered mode
	NVMCTRL_CTRLB_CMD_SEEFLUSH = 0x33
	// Lock access to SmartEEPROM data from any mean
	NVMCTRL_CTRLB_CMD_LSEE = 0x34
	// Unlock access to SmartEEPROM data
	NVMCTRL_CTRLB_CMD_USEE = 0x35
	// Lock access to the SmartEEPROM Register Address Space (above 64KB)
	NVMCTRL_CTRLB_CMD_LSEER = 0x36
	// Unlock access to the SmartEEPROM Register Address Space (above 64KB)
	NVMCTRL_CTRLB_CMD_USEER = 0x37
	// Position of CMDEX field.
	NVMCTRL_CTRLB_CMDEX_Pos = 0x8
	// Bit mask of CMDEX field.
	NVMCTRL_CTRLB_CMDEX_Msk = 0xff00
	// Execution Key
	NVMCTRL_CTRLB_CMDEX_KEY = 0xa5

	// PARAM: NVM Parameter
	// Position of NVMP field.
	NVMCTRL_PARAM_NVMP_Pos = 0x0
	// Bit mask of NVMP field.
	NVMCTRL_PARAM_NVMP_Msk = 0xffff
	// Position of PSZ field.
	NVMCTRL_PARAM_PSZ_Pos = 0x10
	// Bit mask of PSZ field.
	NVMCTRL_PARAM_PSZ_Msk = 0x70000
	// 8 bytes
	NVMCTRL_PARAM_PSZ_8 = 0x0
	// 16 bytes
	NVMCTRL_PARAM_PSZ_16 = 0x1
	// 32 bytes
	NVMCTRL_PARAM_PSZ_32 = 0x2
	// 64 bytes
	NVMCTRL_PARAM_PSZ_64 = 0x3
	// 128 bytes
	NVMCTRL_PARAM_PSZ_128 = 0x4
	// 256 bytes
	NVMCTRL_PARAM_PSZ_256 = 0x5
	// 512 bytes
	NVMCTRL_PARAM_PSZ_512 = 0x6
	// 1024 bytes
	NVMCTRL_PARAM_PSZ_1024 = 0x7
	// Position of SEE field.
	NVMCTRL_PARAM_SEE_Pos = 0x1f
	// Bit mask of SEE field.
	NVMCTRL_PARAM_SEE_Msk = 0x80000000
	// Bit SEE.
	NVMCTRL_PARAM_SEE = 0x80000000
	// 163840 bytes
	NVMCTRL_PARAM_SEE_A = 0xa
	// 147456 bytes
	NVMCTRL_PARAM_SEE_9 = 0x9
	// 131072 bytes
	NVMCTRL_PARAM_SEE_8 = 0x8
	// 114688 bytes
	NVMCTRL_PARAM_SEE_7 = 0x7
	// 98304 bytes
	NVMCTRL_PARAM_SEE_6 = 0x6
	// 81920 bytes
	NVMCTRL_PARAM_SEE_5 = 0x5
	// 65536 bytes
	NVMCTRL_PARAM_SEE_4 = 0x4
	// 49152 bytes
	NVMCTRL_PARAM_SEE_3 = 0x3
	// 32768 bytes
	NVMCTRL_PARAM_SEE_2 = 0x2
	// 16384 bytes
	NVMCTRL_PARAM_SEE_1 = 0x1
	// 0 bytes
	NVMCTRL_PARAM_SEE_0 = 0x0

	// INTENCLR: Interrupt Enable Clear
	// Position of DONE field.
	NVMCTRL_INTENCLR_DONE_Pos = 0x0
	// Bit mask of DONE field.
	NVMCTRL_INTENCLR_DONE_Msk = 0x1
	// Bit DONE.
	NVMCTRL_INTENCLR_DONE = 0x1
	// Position of ADDRE field.
	NVMCTRL_INTENCLR_ADDRE_Pos = 0x1
	// Bit mask of ADDRE field.
	NVMCTRL_INTENCLR_ADDRE_Msk = 0x2
	// Bit ADDRE.
	NVMCTRL_INTENCLR_ADDRE = 0x2
	// Position of PROGE field.
	NVMCTRL_INTENCLR_PROGE_Pos = 0x2
	// Bit mask of PROGE field.
	NVMCTRL_INTENCLR_PROGE_Msk = 0x4
	// Bit PROGE.
	NVMCTRL_INTENCLR_PROGE = 0x4
	// Position of LOCKE field.
	NVMCTRL_INTENCLR_LOCKE_Pos = 0x3
	// Bit mask of LOCKE field.
	NVMCTRL_INTENCLR_LOCKE_Msk = 0x8
	// Bit LOCKE.
	NVMCTRL_INTENCLR_LOCKE = 0x8
	// Position of ECCSE field.
	NVMCTRL_INTENCLR_ECCSE_Pos = 0x4
	// Bit mask of ECCSE field.
	NVMCTRL_INTENCLR_ECCSE_Msk = 0x10
	// Bit ECCSE.
	NVMCTRL_INTENCLR_ECCSE = 0x10
	// Position of ECCDE field.
	NVMCTRL_INTENCLR_ECCDE_Pos = 0x5
	// Bit mask of ECCDE field.
	NVMCTRL_INTENCLR_ECCDE_Msk = 0x20
	// Bit ECCDE.
	NVMCTRL_INTENCLR_ECCDE = 0x20
	// Position of NVME field.
	NVMCTRL_INTENCLR_NVME_Pos = 0x6
	// Bit mask of NVME field.
	NVMCTRL_INTENCLR_NVME_Msk = 0x40
	// Bit NVME.
	NVMCTRL_INTENCLR_NVME = 0x40
	// Position of SUSP field.
	NVMCTRL_INTENCLR_SUSP_Pos = 0x7
	// Bit mask of SUSP field.
	NVMCTRL_INTENCLR_SUSP_Msk = 0x80
	// Bit SUSP.
	NVMCTRL_INTENCLR_SUSP = 0x80
	// Position of SEESFULL field.
	NVMCTRL_INTENCLR_SEESFULL_Pos = 0x8
	// Bit mask of SEESFULL field.
	NVMCTRL_INTENCLR_SEESFULL_Msk = 0x100
	// Bit SEESFULL.
	NVMCTRL_INTENCLR_SEESFULL = 0x100
	// Position of SEESOVF field.
	NVMCTRL_INTENCLR_SEESOVF_Pos = 0x9
	// Bit mask of SEESOVF field.
	NVMCTRL_INTENCLR_SEESOVF_Msk = 0x200
	// Bit SEESOVF.
	NVMCTRL_INTENCLR_SEESOVF = 0x200
	// Position of SEEWRC field.
	NVMCTRL_INTENCLR_SEEWRC_Pos = 0xa
	// Bit mask of SEEWRC field.
	NVMCTRL_INTENCLR_SEEWRC_Msk = 0x400
	// Bit SEEWRC.
	NVMCTRL_INTENCLR_SEEWRC = 0x400

	// INTENSET: Interrupt Enable Set
	// Position of DONE field.
	NVMCTRL_INTENSET_DONE_Pos = 0x0
	// Bit mask of DONE field.
	NVMCTRL_INTENSET_DONE_Msk = 0x1
	// Bit DONE.
	NVMCTRL_INTENSET_DONE = 0x1
	// Position of ADDRE field.
	NVMCTRL_INTENSET_ADDRE_Pos = 0x1
	// Bit mask of ADDRE field.
	NVMCTRL_INTENSET_ADDRE_Msk = 0x2
	// Bit ADDRE.
	NVMCTRL_INTENSET_ADDRE = 0x2
	// Position of PROGE field.
	NVMCTRL_INTENSET_PROGE_Pos = 0x2
	// Bit mask of PROGE field.
	NVMCTRL_INTENSET_PROGE_Msk = 0x4
	// Bit PROGE.
	NVMCTRL_INTENSET_PROGE = 0x4
	// Position of LOCKE field.
	NVMCTRL_INTENSET_LOCKE_Pos = 0x3
	// Bit mask of LOCKE field.
	NVMCTRL_INTENSET_LOCKE_Msk = 0x8
	// Bit LOCKE.
	NVMCTRL_INTENSET_LOCKE = 0x8
	// Position of ECCSE field.
	NVMCTRL_INTENSET_ECCSE_Pos = 0x4
	// Bit mask of ECCSE field.
	NVMCTRL_INTENSET_ECCSE_Msk = 0x10
	// Bit ECCSE.
	NVMCTRL_INTENSET_ECCSE = 0x10
	// Position of ECCDE field.
	NVMCTRL_INTENSET_ECCDE_Pos = 0x5
	// Bit mask of ECCDE field.
	NVMCTRL_INTENSET_ECCDE_Msk = 0x20
	// Bit ECCDE.
	NVMCTRL_INTENSET_ECCDE = 0x20
	// Position of NVME field.
	NVMCTRL_INTENSET_NVME_Pos = 0x6
	// Bit mask of NVME field.
	NVMCTRL_INTENSET_NVME_Msk = 0x40
	// Bit NVME.
	NVMCTRL_INTENSET_NVME = 0x40
	// Position of SUSP field.
	NVMCTRL_INTENSET_SUSP_Pos = 0x7
	// Bit mask of SUSP field.
	NVMCTRL_INTENSET_SUSP_Msk = 0x80
	// Bit SUSP.
	NVMCTRL_INTENSET_SUSP = 0x80
	// Position of SEESFULL field.
	NVMCTRL_INTENSET_SEESFULL_Pos = 0x8
	// Bit mask of SEESFULL field.
	NVMCTRL_INTENSET_SEESFULL_Msk = 0x100
	// Bit SEESFULL.
	NVMCTRL_INTENSET_SEESFULL = 0x100
	// Position of SEESOVF field.
	NVMCTRL_INTENSET_SEESOVF_Pos = 0x9
	// Bit mask of SEESOVF field.
	NVMCTRL_INTENSET_SEESOVF_Msk = 0x200
	// Bit SEESOVF.
	NVMCTRL_INTENSET_SEESOVF = 0x200
	// Position of SEEWRC field.
	NVMCTRL_INTENSET_SEEWRC_Pos = 0xa
	// Bit mask of SEEWRC field.
	NVMCTRL_INTENSET_SEEWRC_Msk = 0x400
	// Bit SEEWRC.
	NVMCTRL_INTENSET_SEEWRC = 0x400

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of DONE field.
	NVMCTRL_INTFLAG_DONE_Pos = 0x0
	// Bit mask of DONE field.
	NVMCTRL_INTFLAG_DONE_Msk = 0x1
	// Bit DONE.
	NVMCTRL_INTFLAG_DONE = 0x1
	// Position of ADDRE field.
	NVMCTRL_INTFLAG_ADDRE_Pos = 0x1
	// Bit mask of ADDRE field.
	NVMCTRL_INTFLAG_ADDRE_Msk = 0x2
	// Bit ADDRE.
	NVMCTRL_INTFLAG_ADDRE = 0x2
	// Position of PROGE field.
	NVMCTRL_INTFLAG_PROGE_Pos = 0x2
	// Bit mask of PROGE field.
	NVMCTRL_INTFLAG_PROGE_Msk = 0x4
	// Bit PROGE.
	NVMCTRL_INTFLAG_PROGE = 0x4
	// Position of LOCKE field.
	NVMCTRL_INTFLAG_LOCKE_Pos = 0x3
	// Bit mask of LOCKE field.
	NVMCTRL_INTFLAG_LOCKE_Msk = 0x8
	// Bit LOCKE.
	NVMCTRL_INTFLAG_LOCKE = 0x8
	// Position of ECCSE field.
	NVMCTRL_INTFLAG_ECCSE_Pos = 0x4
	// Bit mask of ECCSE field.
	NVMCTRL_INTFLAG_ECCSE_Msk = 0x10
	// Bit ECCSE.
	NVMCTRL_INTFLAG_ECCSE = 0x10
	// Position of ECCDE field.
	NVMCTRL_INTFLAG_ECCDE_Pos = 0x5
	// Bit mask of ECCDE field.
	NVMCTRL_INTFLAG_ECCDE_Msk = 0x20
	// Bit ECCDE.
	NVMCTRL_INTFLAG_ECCDE = 0x20
	// Position of NVME field.
	NVMCTRL_INTFLAG_NVME_Pos = 0x6
	// Bit mask of NVME field.
	NVMCTRL_INTFLAG_NVME_Msk = 0x40
	// Bit NVME.
	NVMCTRL_INTFLAG_NVME = 0x40
	// Position of SUSP field.
	NVMCTRL_INTFLAG_SUSP_Pos = 0x7
	// Bit mask of SUSP field.
	NVMCTRL_INTFLAG_SUSP_Msk = 0x80
	// Bit SUSP.
	NVMCTRL_INTFLAG_SUSP = 0x80
	// Position of SEESFULL field.
	NVMCTRL_INTFLAG_SEESFULL_Pos = 0x8
	// Bit mask of SEESFULL field.
	NVMCTRL_INTFLAG_SEESFULL_Msk = 0x100
	// Bit SEESFULL.
	NVMCTRL_INTFLAG_SEESFULL = 0x100
	// Position of SEESOVF field.
	NVMCTRL_INTFLAG_SEESOVF_Pos = 0x9
	// Bit mask of SEESOVF field.
	NVMCTRL_INTFLAG_SEESOVF_Msk = 0x200
	// Bit SEESOVF.
	NVMCTRL_INTFLAG_SEESOVF = 0x200
	// Position of SEEWRC field.
	NVMCTRL_INTFLAG_SEEWRC_Pos = 0xa
	// Bit mask of SEEWRC field.
	NVMCTRL_INTFLAG_SEEWRC_Msk = 0x400
	// Bit SEEWRC.
	NVMCTRL_INTFLAG_SEEWRC = 0x400

	// STATUS: Status
	// Position of READY field.
	NVMCTRL_STATUS_READY_Pos = 0x0
	// Bit mask of READY field.
	NVMCTRL_STATUS_READY_Msk = 0x1
	// Bit READY.
	NVMCTRL_STATUS_READY = 0x1
	// Position of PRM field.
	NVMCTRL_STATUS_PRM_Pos = 0x1
	// Bit mask of PRM field.
	NVMCTRL_STATUS_PRM_Msk = 0x2
	// Bit PRM.
	NVMCTRL_STATUS_PRM = 0x2
	// Position of LOAD field.
	NVMCTRL_STATUS_LOAD_Pos = 0x2
	// Bit mask of LOAD field.
	NVMCTRL_STATUS_LOAD_Msk = 0x4
	// Bit LOAD.
	NVMCTRL_STATUS_LOAD = 0x4
	// Position of SUSP field.
	NVMCTRL_STATUS_SUSP_Pos = 0x3
	// Bit mask of SUSP field.
	NVMCTRL_STATUS_SUSP_Msk = 0x8
	// Bit SUSP.
	NVMCTRL_STATUS_SUSP = 0x8
	// Position of AFIRST field.
	NVMCTRL_STATUS_AFIRST_Pos = 0x4
	// Bit mask of AFIRST field.
	NVMCTRL_STATUS_AFIRST_Msk = 0x10
	// Bit AFIRST.
	NVMCTRL_STATUS_AFIRST = 0x10
	// Position of BPDIS field.
	NVMCTRL_STATUS_BPDIS_Pos = 0x5
	// Bit mask of BPDIS field.
	NVMCTRL_STATUS_BPDIS_Msk = 0x20
	// Bit BPDIS.
	NVMCTRL_STATUS_BPDIS = 0x20
	// Position of BOOTPROT field.
	NVMCTRL_STATUS_BOOTPROT_Pos = 0x8
	// Bit mask of BOOTPROT field.
	NVMCTRL_STATUS_BOOTPROT_Msk = 0xf00
	// 0 kbytes
	NVMCTRL_STATUS_BOOTPROT_0 = 0xf
	// 8 kbytes
	NVMCTRL_STATUS_BOOTPROT_8 = 0xe
	// 16 kbytes
	NVMCTRL_STATUS_BOOTPROT_16 = 0xd
	// 24 kbytes
	NVMCTRL_STATUS_BOOTPROT_24 = 0xc
	// 32 kbytes
	NVMCTRL_STATUS_BOOTPROT_32 = 0xb
	// 40 kbytes
	NVMCTRL_STATUS_BOOTPROT_40 = 0xa
	// 48 kbytes
	NVMCTRL_STATUS_BOOTPROT_48 = 0x9
	// 56 kbytes
	NVMCTRL_STATUS_BOOTPROT_56 = 0x8
	// 64 kbytes
	NVMCTRL_STATUS_BOOTPROT_64 = 0x7
	// 72 kbytes
	NVMCTRL_STATUS_BOOTPROT_72 = 0x6
	// 80 kbytes
	NVMCTRL_STATUS_BOOTPROT_80 = 0x5
	// 88 kbytes
	NVMCTRL_STATUS_BOOTPROT_88 = 0x4
	// 96 kbytes
	NVMCTRL_STATUS_BOOTPROT_96 = 0x3
	// 104 kbytes
	NVMCTRL_STATUS_BOOTPROT_104 = 0x2
	// 112 kbytes
	NVMCTRL_STATUS_BOOTPROT_112 = 0x1
	// 120 kbytes
	NVMCTRL_STATUS_BOOTPROT_120 = 0x0

	// ADDR: Address
	// Position of ADDR field.
	NVMCTRL_ADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	NVMCTRL_ADDR_ADDR_Msk = 0xffffff

	// RUNLOCK: Lock Section
	// Position of RUNLOCK field.
	NVMCTRL_RUNLOCK_RUNLOCK_Pos = 0x0
	// Bit mask of RUNLOCK field.
	NVMCTRL_RUNLOCK_RUNLOCK_Msk = 0xffffffff

	// PBLDATA: Page Buffer Load Data x
	// Position of DATA field.
	NVMCTRL_PBLDATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	NVMCTRL_PBLDATA_DATA_Msk = 0xffffffff

	// ECCERR: ECC Error Status Register
	// Position of ADDR field.
	NVMCTRL_ECCERR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	NVMCTRL_ECCERR_ADDR_Msk = 0xffffff
	// Position of TYPEL field.
	NVMCTRL_ECCERR_TYPEL_Pos = 0x1c
	// Bit mask of TYPEL field.
	NVMCTRL_ECCERR_TYPEL_Msk = 0x30000000
	// No Error Detected Since Last Read
	NVMCTRL_ECCERR_TYPEL_None = 0x0
	// At Least One Single Error Detected Since last Read
	NVMCTRL_ECCERR_TYPEL_Single = 0x1
	// At Least One Dual Error Detected Since Last Read
	NVMCTRL_ECCERR_TYPEL_Dual = 0x2
	// Position of TYPEH field.
	NVMCTRL_ECCERR_TYPEH_Pos = 0x1e
	// Bit mask of TYPEH field.
	NVMCTRL_ECCERR_TYPEH_Msk = 0xc0000000
	// No Error Detected Since Last Read
	NVMCTRL_ECCERR_TYPEH_None = 0x0
	// At Least One Single Error Detected Since last Read
	NVMCTRL_ECCERR_TYPEH_Single = 0x1
	// At Least One Dual Error Detected Since Last Read
	NVMCTRL_ECCERR_TYPEH_Dual = 0x2

	// DBGCTRL: Debug Control
	// Position of ECCDIS field.
	NVMCTRL_DBGCTRL_ECCDIS_Pos = 0x0
	// Bit mask of ECCDIS field.
	NVMCTRL_DBGCTRL_ECCDIS_Msk = 0x1
	// Bit ECCDIS.
	NVMCTRL_DBGCTRL_ECCDIS = 0x1
	// Position of ECCELOG field.
	NVMCTRL_DBGCTRL_ECCELOG_Pos = 0x1
	// Bit mask of ECCELOG field.
	NVMCTRL_DBGCTRL_ECCELOG_Msk = 0x2
	// Bit ECCELOG.
	NVMCTRL_DBGCTRL_ECCELOG = 0x2

	// SEECFG: SmartEEPROM Configuration Register
	// Position of WMODE field.
	NVMCTRL_SEECFG_WMODE_Pos = 0x0
	// Bit mask of WMODE field.
	NVMCTRL_SEECFG_WMODE_Msk = 0x1
	// Bit WMODE.
	NVMCTRL_SEECFG_WMODE = 0x1
	// A NVM write command is issued after each write in the pagebuffer
	NVMCTRL_SEECFG_WMODE_UNBUFFERED = 0x0
	// A NVM write command is issued when a write to a new page is requested
	NVMCTRL_SEECFG_WMODE_BUFFERED = 0x1
	// Position of APRDIS field.
	NVMCTRL_SEECFG_APRDIS_Pos = 0x1
	// Bit mask of APRDIS field.
	NVMCTRL_SEECFG_APRDIS_Msk = 0x2
	// Bit APRDIS.
	NVMCTRL_SEECFG_APRDIS = 0x2

	// SEESTAT: SmartEEPROM Status Register
	// Position of ASEES field.
	NVMCTRL_SEESTAT_ASEES_Pos = 0x0
	// Bit mask of ASEES field.
	NVMCTRL_SEESTAT_ASEES_Msk = 0x1
	// Bit ASEES.
	NVMCTRL_SEESTAT_ASEES = 0x1
	// Position of LOAD field.
	NVMCTRL_SEESTAT_LOAD_Pos = 0x1
	// Bit mask of LOAD field.
	NVMCTRL_SEESTAT_LOAD_Msk = 0x2
	// Bit LOAD.
	NVMCTRL_SEESTAT_LOAD = 0x2
	// Position of BUSY field.
	NVMCTRL_SEESTAT_BUSY_Pos = 0x2
	// Bit mask of BUSY field.
	NVMCTRL_SEESTAT_BUSY_Msk = 0x4
	// Bit BUSY.
	NVMCTRL_SEESTAT_BUSY = 0x4
	// Position of LOCK field.
	NVMCTRL_SEESTAT_LOCK_Pos = 0x3
	// Bit mask of LOCK field.
	NVMCTRL_SEESTAT_LOCK_Msk = 0x8
	// Bit LOCK.
	NVMCTRL_SEESTAT_LOCK = 0x8
	// Position of RLOCK field.
	NVMCTRL_SEESTAT_RLOCK_Pos = 0x4
	// Bit mask of RLOCK field.
	NVMCTRL_SEESTAT_RLOCK_Msk = 0x10
	// Bit RLOCK.
	NVMCTRL_SEESTAT_RLOCK = 0x10
	// Position of SBLK field.
	NVMCTRL_SEESTAT_SBLK_Pos = 0x8
	// Bit mask of SBLK field.
	NVMCTRL_SEESTAT_SBLK_Msk = 0xf00
	// Position of PSZ field.
	NVMCTRL_SEESTAT_PSZ_Pos = 0x10
	// Bit mask of PSZ field.
	NVMCTRL_SEESTAT_PSZ_Msk = 0x70000
)

// Bitfields for OSCCTRL: Oscillators Control
const (
	// EVCTRL: Event Control
	// Position of CFDEO0 field.
	OSCCTRL_EVCTRL_CFDEO0_Pos = 0x0
	// Bit mask of CFDEO0 field.
	OSCCTRL_EVCTRL_CFDEO0_Msk = 0x1
	// Bit CFDEO0.
	OSCCTRL_EVCTRL_CFDEO0 = 0x1
	// Position of CFDEO1 field.
	OSCCTRL_EVCTRL_CFDEO1_Pos = 0x1
	// Bit mask of CFDEO1 field.
	OSCCTRL_EVCTRL_CFDEO1_Msk = 0x2
	// Bit CFDEO1.
	OSCCTRL_EVCTRL_CFDEO1 = 0x2

	// INTENCLR: Interrupt Enable Clear
	// Position of XOSCRDY0 field.
	OSCCTRL_INTENCLR_XOSCRDY0_Pos = 0x0
	// Bit mask of XOSCRDY0 field.
	OSCCTRL_INTENCLR_XOSCRDY0_Msk = 0x1
	// Bit XOSCRDY0.
	OSCCTRL_INTENCLR_XOSCRDY0 = 0x1
	// Position of XOSCRDY1 field.
	OSCCTRL_INTENCLR_XOSCRDY1_Pos = 0x1
	// Bit mask of XOSCRDY1 field.
	OSCCTRL_INTENCLR_XOSCRDY1_Msk = 0x2
	// Bit XOSCRDY1.
	OSCCTRL_INTENCLR_XOSCRDY1 = 0x2
	// Position of XOSCFAIL0 field.
	OSCCTRL_INTENCLR_XOSCFAIL0_Pos = 0x2
	// Bit mask of XOSCFAIL0 field.
	OSCCTRL_INTENCLR_XOSCFAIL0_Msk = 0x4
	// Bit XOSCFAIL0.
	OSCCTRL_INTENCLR_XOSCFAIL0 = 0x4
	// Position of XOSCFAIL1 field.
	OSCCTRL_INTENCLR_XOSCFAIL1_Pos = 0x3
	// Bit mask of XOSCFAIL1 field.
	OSCCTRL_INTENCLR_XOSCFAIL1_Msk = 0x8
	// Bit XOSCFAIL1.
	OSCCTRL_INTENCLR_XOSCFAIL1 = 0x8
	// Position of DFLLRDY field.
	OSCCTRL_INTENCLR_DFLLRDY_Pos = 0x8
	// Bit mask of DFLLRDY field.
	OSCCTRL_INTENCLR_DFLLRDY_Msk = 0x100
	// Bit DFLLRDY.
	OSCCTRL_INTENCLR_DFLLRDY = 0x100
	// Position of DFLLOOB field.
	OSCCTRL_INTENCLR_DFLLOOB_Pos = 0x9
	// Bit mask of DFLLOOB field.
	OSCCTRL_INTENCLR_DFLLOOB_Msk = 0x200
	// Bit DFLLOOB.
	OSCCTRL_INTENCLR_DFLLOOB = 0x200
	// Position of DFLLLCKF field.
	OSCCTRL_INTENCLR_DFLLLCKF_Pos = 0xa
	// Bit mask of DFLLLCKF field.
	OSCCTRL_INTENCLR_DFLLLCKF_Msk = 0x400
	// Bit DFLLLCKF.
	OSCCTRL_INTENCLR_DFLLLCKF = 0x400
	// Position of DFLLLCKC field.
	OSCCTRL_INTENCLR_DFLLLCKC_Pos = 0xb
	// Bit mask of DFLLLCKC field.
	OSCCTRL_INTENCLR_DFLLLCKC_Msk = 0x800
	// Bit DFLLLCKC.
	OSCCTRL_INTENCLR_DFLLLCKC = 0x800
	// Position of DFLLRCS field.
	OSCCTRL_INTENCLR_DFLLRCS_Pos = 0xc
	// Bit mask of DFLLRCS field.
	OSCCTRL_INTENCLR_DFLLRCS_Msk = 0x1000
	// Bit DFLLRCS.
	OSCCTRL_INTENCLR_DFLLRCS = 0x1000
	// Position of DPLL0LCKR field.
	OSCCTRL_INTENCLR_DPLL0LCKR_Pos = 0x10
	// Bit mask of DPLL0LCKR field.
	OSCCTRL_INTENCLR_DPLL0LCKR_Msk = 0x10000
	// Bit DPLL0LCKR.
	OSCCTRL_INTENCLR_DPLL0LCKR = 0x10000
	// Position of DPLL0LCKF field.
	OSCCTRL_INTENCLR_DPLL0LCKF_Pos = 0x11
	// Bit mask of DPLL0LCKF field.
	OSCCTRL_INTENCLR_DPLL0LCKF_Msk = 0x20000
	// Bit DPLL0LCKF.
	OSCCTRL_INTENCLR_DPLL0LCKF = 0x20000
	// Position of DPLL0LTO field.
	OSCCTRL_INTENCLR_DPLL0LTO_Pos = 0x12
	// Bit mask of DPLL0LTO field.
	OSCCTRL_INTENCLR_DPLL0LTO_Msk = 0x40000
	// Bit DPLL0LTO.
	OSCCTRL_INTENCLR_DPLL0LTO = 0x40000
	// Position of DPLL0LDRTO field.
	OSCCTRL_INTENCLR_DPLL0LDRTO_Pos = 0x13
	// Bit mask of DPLL0LDRTO field.
	OSCCTRL_INTENCLR_DPLL0LDRTO_Msk = 0x80000
	// Bit DPLL0LDRTO.
	OSCCTRL_INTENCLR_DPLL0LDRTO = 0x80000
	// Position of DPLL1LCKR field.
	OSCCTRL_INTENCLR_DPLL1LCKR_Pos = 0x18
	// Bit mask of DPLL1LCKR field.
	OSCCTRL_INTENCLR_DPLL1LCKR_Msk = 0x1000000
	// Bit DPLL1LCKR.
	OSCCTRL_INTENCLR_DPLL1LCKR = 0x1000000
	// Position of DPLL1LCKF field.
	OSCCTRL_INTENCLR_DPLL1LCKF_Pos = 0x19
	// Bit mask of DPLL1LCKF field.
	OSCCTRL_INTENCLR_DPLL1LCKF_Msk = 0x2000000
	// Bit DPLL1LCKF.
	OSCCTRL_INTENCLR_DPLL1LCKF = 0x2000000
	// Position of DPLL1LTO field.
	OSCCTRL_INTENCLR_DPLL1LTO_Pos = 0x1a
	// Bit mask of DPLL1LTO field.
	OSCCTRL_INTENCLR_DPLL1LTO_Msk = 0x4000000
	// Bit DPLL1LTO.
	OSCCTRL_INTENCLR_DPLL1LTO = 0x4000000
	// Position of DPLL1LDRTO field.
	OSCCTRL_INTENCLR_DPLL1LDRTO_Pos = 0x1b
	// Bit mask of DPLL1LDRTO field.
	OSCCTRL_INTENCLR_DPLL1LDRTO_Msk = 0x8000000
	// Bit DPLL1LDRTO.
	OSCCTRL_INTENCLR_DPLL1LDRTO = 0x8000000

	// INTENSET: Interrupt Enable Set
	// Position of XOSCRDY0 field.
	OSCCTRL_INTENSET_XOSCRDY0_Pos = 0x0
	// Bit mask of XOSCRDY0 field.
	OSCCTRL_INTENSET_XOSCRDY0_Msk = 0x1
	// Bit XOSCRDY0.
	OSCCTRL_INTENSET_XOSCRDY0 = 0x1
	// Position of XOSCRDY1 field.
	OSCCTRL_INTENSET_XOSCRDY1_Pos = 0x1
	// Bit mask of XOSCRDY1 field.
	OSCCTRL_INTENSET_XOSCRDY1_Msk = 0x2
	// Bit XOSCRDY1.
	OSCCTRL_INTENSET_XOSCRDY1 = 0x2
	// Position of XOSCFAIL0 field.
	OSCCTRL_INTENSET_XOSCFAIL0_Pos = 0x2
	// Bit mask of XOSCFAIL0 field.
	OSCCTRL_INTENSET_XOSCFAIL0_Msk = 0x4
	// Bit XOSCFAIL0.
	OSCCTRL_INTENSET_XOSCFAIL0 = 0x4
	// Position of XOSCFAIL1 field.
	OSCCTRL_INTENSET_XOSCFAIL1_Pos = 0x3
	// Bit mask of XOSCFAIL1 field.
	OSCCTRL_INTENSET_XOSCFAIL1_Msk = 0x8
	// Bit XOSCFAIL1.
	OSCCTRL_INTENSET_XOSCFAIL1 = 0x8
	// Position of DFLLRDY field.
	OSCCTRL_INTENSET_DFLLRDY_Pos = 0x8
	// Bit mask of DFLLRDY field.
	OSCCTRL_INTENSET_DFLLRDY_Msk = 0x100
	// Bit DFLLRDY.
	OSCCTRL_INTENSET_DFLLRDY = 0x100
	// Position of DFLLOOB field.
	OSCCTRL_INTENSET_DFLLOOB_Pos = 0x9
	// Bit mask of DFLLOOB field.
	OSCCTRL_INTENSET_DFLLOOB_Msk = 0x200
	// Bit DFLLOOB.
	OSCCTRL_INTENSET_DFLLOOB = 0x200
	// Position of DFLLLCKF field.
	OSCCTRL_INTENSET_DFLLLCKF_Pos = 0xa
	// Bit mask of DFLLLCKF field.
	OSCCTRL_INTENSET_DFLLLCKF_Msk = 0x400
	// Bit DFLLLCKF.
	OSCCTRL_INTENSET_DFLLLCKF = 0x400
	// Position of DFLLLCKC field.
	OSCCTRL_INTENSET_DFLLLCKC_Pos = 0xb
	// Bit mask of DFLLLCKC field.
	OSCCTRL_INTENSET_DFLLLCKC_Msk = 0x800
	// Bit DFLLLCKC.
	OSCCTRL_INTENSET_DFLLLCKC = 0x800
	// Position of DFLLRCS field.
	OSCCTRL_INTENSET_DFLLRCS_Pos = 0xc
	// Bit mask of DFLLRCS field.
	OSCCTRL_INTENSET_DFLLRCS_Msk = 0x1000
	// Bit DFLLRCS.
	OSCCTRL_INTENSET_DFLLRCS = 0x1000
	// Position of DPLL0LCKR field.
	OSCCTRL_INTENSET_DPLL0LCKR_Pos = 0x10
	// Bit mask of DPLL0LCKR field.
	OSCCTRL_INTENSET_DPLL0LCKR_Msk = 0x10000
	// Bit DPLL0LCKR.
	OSCCTRL_INTENSET_DPLL0LCKR = 0x10000
	// Position of DPLL0LCKF field.
	OSCCTRL_INTENSET_DPLL0LCKF_Pos = 0x11
	// Bit mask of DPLL0LCKF field.
	OSCCTRL_INTENSET_DPLL0LCKF_Msk = 0x20000
	// Bit DPLL0LCKF.
	OSCCTRL_INTENSET_DPLL0LCKF = 0x20000
	// Position of DPLL0LTO field.
	OSCCTRL_INTENSET_DPLL0LTO_Pos = 0x12
	// Bit mask of DPLL0LTO field.
	OSCCTRL_INTENSET_DPLL0LTO_Msk = 0x40000
	// Bit DPLL0LTO.
	OSCCTRL_INTENSET_DPLL0LTO = 0x40000
	// Position of DPLL0LDRTO field.
	OSCCTRL_INTENSET_DPLL0LDRTO_Pos = 0x13
	// Bit mask of DPLL0LDRTO field.
	OSCCTRL_INTENSET_DPLL0LDRTO_Msk = 0x80000
	// Bit DPLL0LDRTO.
	OSCCTRL_INTENSET_DPLL0LDRTO = 0x80000
	// Position of DPLL1LCKR field.
	OSCCTRL_INTENSET_DPLL1LCKR_Pos = 0x18
	// Bit mask of DPLL1LCKR field.
	OSCCTRL_INTENSET_DPLL1LCKR_Msk = 0x1000000
	// Bit DPLL1LCKR.
	OSCCTRL_INTENSET_DPLL1LCKR = 0x1000000
	// Position of DPLL1LCKF field.
	OSCCTRL_INTENSET_DPLL1LCKF_Pos = 0x19
	// Bit mask of DPLL1LCKF field.
	OSCCTRL_INTENSET_DPLL1LCKF_Msk = 0x2000000
	// Bit DPLL1LCKF.
	OSCCTRL_INTENSET_DPLL1LCKF = 0x2000000
	// Position of DPLL1LTO field.
	OSCCTRL_INTENSET_DPLL1LTO_Pos = 0x1a
	// Bit mask of DPLL1LTO field.
	OSCCTRL_INTENSET_DPLL1LTO_Msk = 0x4000000
	// Bit DPLL1LTO.
	OSCCTRL_INTENSET_DPLL1LTO = 0x4000000
	// Position of DPLL1LDRTO field.
	OSCCTRL_INTENSET_DPLL1LDRTO_Pos = 0x1b
	// Bit mask of DPLL1LDRTO field.
	OSCCTRL_INTENSET_DPLL1LDRTO_Msk = 0x8000000
	// Bit DPLL1LDRTO.
	OSCCTRL_INTENSET_DPLL1LDRTO = 0x8000000

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of XOSCRDY0 field.
	OSCCTRL_INTFLAG_XOSCRDY0_Pos = 0x0
	// Bit mask of XOSCRDY0 field.
	OSCCTRL_INTFLAG_XOSCRDY0_Msk = 0x1
	// Bit XOSCRDY0.
	OSCCTRL_INTFLAG_XOSCRDY0 = 0x1
	// Position of XOSCRDY1 field.
	OSCCTRL_INTFLAG_XOSCRDY1_Pos = 0x1
	// Bit mask of XOSCRDY1 field.
	OSCCTRL_INTFLAG_XOSCRDY1_Msk = 0x2
	// Bit XOSCRDY1.
	OSCCTRL_INTFLAG_XOSCRDY1 = 0x2
	// Position of XOSCFAIL0 field.
	OSCCTRL_INTFLAG_XOSCFAIL0_Pos = 0x2
	// Bit mask of XOSCFAIL0 field.
	OSCCTRL_INTFLAG_XOSCFAIL0_Msk = 0x4
	// Bit XOSCFAIL0.
	OSCCTRL_INTFLAG_XOSCFAIL0 = 0x4
	// Position of XOSCFAIL1 field.
	OSCCTRL_INTFLAG_XOSCFAIL1_Pos = 0x3
	// Bit mask of XOSCFAIL1 field.
	OSCCTRL_INTFLAG_XOSCFAIL1_Msk = 0x8
	// Bit XOSCFAIL1.
	OSCCTRL_INTFLAG_XOSCFAIL1 = 0x8
	// Position of DFLLRDY field.
	OSCCTRL_INTFLAG_DFLLRDY_Pos = 0x8
	// Bit mask of DFLLRDY field.
	OSCCTRL_INTFLAG_DFLLRDY_Msk = 0x100
	// Bit DFLLRDY.
	OSCCTRL_INTFLAG_DFLLRDY = 0x100
	// Position of DFLLOOB field.
	OSCCTRL_INTFLAG_DFLLOOB_Pos = 0x9
	// Bit mask of DFLLOOB field.
	OSCCTRL_INTFLAG_DFLLOOB_Msk = 0x200
	// Bit DFLLOOB.
	OSCCTRL_INTFLAG_DFLLOOB = 0x200
	// Position of DFLLLCKF field.
	OSCCTRL_INTFLAG_DFLLLCKF_Pos = 0xa
	// Bit mask of DFLLLCKF field.
	OSCCTRL_INTFLAG_DFLLLCKF_Msk = 0x400
	// Bit DFLLLCKF.
	OSCCTRL_INTFLAG_DFLLLCKF = 0x400
	// Position of DFLLLCKC field.
	OSCCTRL_INTFLAG_DFLLLCKC_Pos = 0xb
	// Bit mask of DFLLLCKC field.
	OSCCTRL_INTFLAG_DFLLLCKC_Msk = 0x800
	// Bit DFLLLCKC.
	OSCCTRL_INTFLAG_DFLLLCKC = 0x800
	// Position of DFLLRCS field.
	OSCCTRL_INTFLAG_DFLLRCS_Pos = 0xc
	// Bit mask of DFLLRCS field.
	OSCCTRL_INTFLAG_DFLLRCS_Msk = 0x1000
	// Bit DFLLRCS.
	OSCCTRL_INTFLAG_DFLLRCS = 0x1000
	// Position of DPLL0LCKR field.
	OSCCTRL_INTFLAG_DPLL0LCKR_Pos = 0x10
	// Bit mask of DPLL0LCKR field.
	OSCCTRL_INTFLAG_DPLL0LCKR_Msk = 0x10000
	// Bit DPLL0LCKR.
	OSCCTRL_INTFLAG_DPLL0LCKR = 0x10000
	// Position of DPLL0LCKF field.
	OSCCTRL_INTFLAG_DPLL0LCKF_Pos = 0x11
	// Bit mask of DPLL0LCKF field.
	OSCCTRL_INTFLAG_DPLL0LCKF_Msk = 0x20000
	// Bit DPLL0LCKF.
	OSCCTRL_INTFLAG_DPLL0LCKF = 0x20000
	// Position of DPLL0LTO field.
	OSCCTRL_INTFLAG_DPLL0LTO_Pos = 0x12
	// Bit mask of DPLL0LTO field.
	OSCCTRL_INTFLAG_DPLL0LTO_Msk = 0x40000
	// Bit DPLL0LTO.
	OSCCTRL_INTFLAG_DPLL0LTO = 0x40000
	// Position of DPLL0LDRTO field.
	OSCCTRL_INTFLAG_DPLL0LDRTO_Pos = 0x13
	// Bit mask of DPLL0LDRTO field.
	OSCCTRL_INTFLAG_DPLL0LDRTO_Msk = 0x80000
	// Bit DPLL0LDRTO.
	OSCCTRL_INTFLAG_DPLL0LDRTO = 0x80000
	// Position of DPLL1LCKR field.
	OSCCTRL_INTFLAG_DPLL1LCKR_Pos = 0x18
	// Bit mask of DPLL1LCKR field.
	OSCCTRL_INTFLAG_DPLL1LCKR_Msk = 0x1000000
	// Bit DPLL1LCKR.
	OSCCTRL_INTFLAG_DPLL1LCKR = 0x1000000
	// Position of DPLL1LCKF field.
	OSCCTRL_INTFLAG_DPLL1LCKF_Pos = 0x19
	// Bit mask of DPLL1LCKF field.
	OSCCTRL_INTFLAG_DPLL1LCKF_Msk = 0x2000000
	// Bit DPLL1LCKF.
	OSCCTRL_INTFLAG_DPLL1LCKF = 0x2000000
	// Position of DPLL1LTO field.
	OSCCTRL_INTFLAG_DPLL1LTO_Pos = 0x1a
	// Bit mask of DPLL1LTO field.
	OSCCTRL_INTFLAG_DPLL1LTO_Msk = 0x4000000
	// Bit DPLL1LTO.
	OSCCTRL_INTFLAG_DPLL1LTO = 0x4000000
	// Position of DPLL1LDRTO field.
	OSCCTRL_INTFLAG_DPLL1LDRTO_Pos = 0x1b
	// Bit mask of DPLL1LDRTO field.
	OSCCTRL_INTFLAG_DPLL1LDRTO_Msk = 0x8000000
	// Bit DPLL1LDRTO.
	OSCCTRL_INTFLAG_DPLL1LDRTO = 0x8000000

	// STATUS: Status
	// Position of XOSCRDY0 field.
	OSCCTRL_STATUS_XOSCRDY0_Pos = 0x0
	// Bit mask of XOSCRDY0 field.
	OSCCTRL_STATUS_XOSCRDY0_Msk = 0x1
	// Bit XOSCRDY0.
	OSCCTRL_STATUS_XOSCRDY0 = 0x1
	// Position of XOSCRDY1 field.
	OSCCTRL_STATUS_XOSCRDY1_Pos = 0x1
	// Bit mask of XOSCRDY1 field.
	OSCCTRL_STATUS_XOSCRDY1_Msk = 0x2
	// Bit XOSCRDY1.
	OSCCTRL_STATUS_XOSCRDY1 = 0x2
	// Position of XOSCFAIL0 field.
	OSCCTRL_STATUS_XOSCFAIL0_Pos = 0x2
	// Bit mask of XOSCFAIL0 field.
	OSCCTRL_STATUS_XOSCFAIL0_Msk = 0x4
	// Bit XOSCFAIL0.
	OSCCTRL_STATUS_XOSCFAIL0 = 0x4
	// Position of XOSCFAIL1 field.
	OSCCTRL_STATUS_XOSCFAIL1_Pos = 0x3
	// Bit mask of XOSCFAIL1 field.
	OSCCTRL_STATUS_XOSCFAIL1_Msk = 0x8
	// Bit XOSCFAIL1.
	OSCCTRL_STATUS_XOSCFAIL1 = 0x8
	// Position of XOSCCKSW0 field.
	OSCCTRL_STATUS_XOSCCKSW0_Pos = 0x4
	// Bit mask of XOSCCKSW0 field.
	OSCCTRL_STATUS_XOSCCKSW0_Msk = 0x10
	// Bit XOSCCKSW0.
	OSCCTRL_STATUS_XOSCCKSW0 = 0x10
	// Position of XOSCCKSW1 field.
	OSCCTRL_STATUS_XOSCCKSW1_Pos = 0x5
	// Bit mask of XOSCCKSW1 field.
	OSCCTRL_STATUS_XOSCCKSW1_Msk = 0x20
	// Bit XOSCCKSW1.
	OSCCTRL_STATUS_XOSCCKSW1 = 0x20
	// Position of DFLLRDY field.
	OSCCTRL_STATUS_DFLLRDY_Pos = 0x8
	// Bit mask of DFLLRDY field.
	OSCCTRL_STATUS_DFLLRDY_Msk = 0x100
	// Bit DFLLRDY.
	OSCCTRL_STATUS_DFLLRDY = 0x100
	// Position of DFLLOOB field.
	OSCCTRL_STATUS_DFLLOOB_Pos = 0x9
	// Bit mask of DFLLOOB field.
	OSCCTRL_STATUS_DFLLOOB_Msk = 0x200
	// Bit DFLLOOB.
	OSCCTRL_STATUS_DFLLOOB = 0x200
	// Position of DFLLLCKF field.
	OSCCTRL_STATUS_DFLLLCKF_Pos = 0xa
	// Bit mask of DFLLLCKF field.
	OSCCTRL_STATUS_DFLLLCKF_Msk = 0x400
	// Bit DFLLLCKF.
	OSCCTRL_STATUS_DFLLLCKF = 0x400
	// Position of DFLLLCKC field.
	OSCCTRL_STATUS_DFLLLCKC_Pos = 0xb
	// Bit mask of DFLLLCKC field.
	OSCCTRL_STATUS_DFLLLCKC_Msk = 0x800
	// Bit DFLLLCKC.
	OSCCTRL_STATUS_DFLLLCKC = 0x800
	// Position of DFLLRCS field.
	OSCCTRL_STATUS_DFLLRCS_Pos = 0xc
	// Bit mask of DFLLRCS field.
	OSCCTRL_STATUS_DFLLRCS_Msk = 0x1000
	// Bit DFLLRCS.
	OSCCTRL_STATUS_DFLLRCS = 0x1000
	// Position of DPLL0LCKR field.
	OSCCTRL_STATUS_DPLL0LCKR_Pos = 0x10
	// Bit mask of DPLL0LCKR field.
	OSCCTRL_STATUS_DPLL0LCKR_Msk = 0x10000
	// Bit DPLL0LCKR.
	OSCCTRL_STATUS_DPLL0LCKR = 0x10000
	// Position of DPLL0LCKF field.
	OSCCTRL_STATUS_DPLL0LCKF_Pos = 0x11
	// Bit mask of DPLL0LCKF field.
	OSCCTRL_STATUS_DPLL0LCKF_Msk = 0x20000
	// Bit DPLL0LCKF.
	OSCCTRL_STATUS_DPLL0LCKF = 0x20000
	// Position of DPLL0TO field.
	OSCCTRL_STATUS_DPLL0TO_Pos = 0x12
	// Bit mask of DPLL0TO field.
	OSCCTRL_STATUS_DPLL0TO_Msk = 0x40000
	// Bit DPLL0TO.
	OSCCTRL_STATUS_DPLL0TO = 0x40000
	// Position of DPLL0LDRTO field.
	OSCCTRL_STATUS_DPLL0LDRTO_Pos = 0x13
	// Bit mask of DPLL0LDRTO field.
	OSCCTRL_STATUS_DPLL0LDRTO_Msk = 0x80000
	// Bit DPLL0LDRTO.
	OSCCTRL_STATUS_DPLL0LDRTO = 0x80000
	// Position of DPLL1LCKR field.
	OSCCTRL_STATUS_DPLL1LCKR_Pos = 0x18
	// Bit mask of DPLL1LCKR field.
	OSCCTRL_STATUS_DPLL1LCKR_Msk = 0x1000000
	// Bit DPLL1LCKR.
	OSCCTRL_STATUS_DPLL1LCKR = 0x1000000
	// Position of DPLL1LCKF field.
	OSCCTRL_STATUS_DPLL1LCKF_Pos = 0x19
	// Bit mask of DPLL1LCKF field.
	OSCCTRL_STATUS_DPLL1LCKF_Msk = 0x2000000
	// Bit DPLL1LCKF.
	OSCCTRL_STATUS_DPLL1LCKF = 0x2000000
	// Position of DPLL1TO field.
	OSCCTRL_STATUS_DPLL1TO_Pos = 0x1a
	// Bit mask of DPLL1TO field.
	OSCCTRL_STATUS_DPLL1TO_Msk = 0x4000000
	// Bit DPLL1TO.
	OSCCTRL_STATUS_DPLL1TO = 0x4000000
	// Position of DPLL1LDRTO field.
	OSCCTRL_STATUS_DPLL1LDRTO_Pos = 0x1b
	// Bit mask of DPLL1LDRTO field.
	OSCCTRL_STATUS_DPLL1LDRTO_Msk = 0x8000000
	// Bit DPLL1LDRTO.
	OSCCTRL_STATUS_DPLL1LDRTO = 0x8000000

	// XOSCCTRL: External Multipurpose Crystal Oscillator Control
	// Position of ENABLE field.
	OSCCTRL_XOSCCTRL_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	OSCCTRL_XOSCCTRL_ENABLE_Msk = 0x2
	// Bit ENABLE.
	OSCCTRL_XOSCCTRL_ENABLE = 0x2
	// Position of XTALEN field.
	OSCCTRL_XOSCCTRL_XTALEN_Pos = 0x2
	// Bit mask of XTALEN field.
	OSCCTRL_XOSCCTRL_XTALEN_Msk = 0x4
	// Bit XTALEN.
	OSCCTRL_XOSCCTRL_XTALEN = 0x4
	// Position of RUNSTDBY field.
	OSCCTRL_XOSCCTRL_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	OSCCTRL_XOSCCTRL_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	OSCCTRL_XOSCCTRL_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	OSCCTRL_XOSCCTRL_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	OSCCTRL_XOSCCTRL_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	OSCCTRL_XOSCCTRL_ONDEMAND = 0x80
	// Position of LOWBUFGAIN field.
	OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos = 0x8
	// Bit mask of LOWBUFGAIN field.
	OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk = 0x100
	// Bit LOWBUFGAIN.
	OSCCTRL_XOSCCTRL_LOWBUFGAIN = 0x100
	// Position of IPTAT field.
	OSCCTRL_XOSCCTRL_IPTAT_Pos = 0x9
	// Bit mask of IPTAT field.
	OSCCTRL_XOSCCTRL_IPTAT_Msk = 0x600
	// Position of IMULT field.
	OSCCTRL_XOSCCTRL_IMULT_Pos = 0xb
	// Bit mask of IMULT field.
	OSCCTRL_XOSCCTRL_IMULT_Msk = 0x7800
	// Position of ENALC field.
	OSCCTRL_XOSCCTRL_ENALC_Pos = 0xf
	// Bit mask of ENALC field.
	OSCCTRL_XOSCCTRL_ENALC_Msk = 0x8000
	// Bit ENALC.
	OSCCTRL_XOSCCTRL_ENALC = 0x8000
	// Position of CFDEN field.
	OSCCTRL_XOSCCTRL_CFDEN_Pos = 0x10
	// Bit mask of CFDEN field.
	OSCCTRL_XOSCCTRL_CFDEN_Msk = 0x10000
	// Bit CFDEN.
	OSCCTRL_XOSCCTRL_CFDEN = 0x10000
	// Position of SWBEN field.
	OSCCTRL_XOSCCTRL_SWBEN_Pos = 0x11
	// Bit mask of SWBEN field.
	OSCCTRL_XOSCCTRL_SWBEN_Msk = 0x20000
	// Bit SWBEN.
	OSCCTRL_XOSCCTRL_SWBEN = 0x20000
	// Position of STARTUP field.
	OSCCTRL_XOSCCTRL_STARTUP_Pos = 0x14
	// Bit mask of STARTUP field.
	OSCCTRL_XOSCCTRL_STARTUP_Msk = 0xf00000
	// 31 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE1 = 0x0
	// 61 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE2 = 0x1
	// 122 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE4 = 0x2
	// 244 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE8 = 0x3
	// 488 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE16 = 0x4
	// 977 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE32 = 0x5
	// 1953 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE64 = 0x6
	// 3906 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE128 = 0x7
	// 7813 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE256 = 0x8
	// 15625 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE512 = 0x9
	// 31250 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024 = 0xa
	// 62500 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048 = 0xb
	// 125000 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096 = 0xc
	// 250000 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192 = 0xd
	// 500000 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384 = 0xe
	// 1000000 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768 = 0xf
	// Position of CFDPRESC field.
	OSCCTRL_XOSCCTRL_CFDPRESC_Pos = 0x18
	// Bit mask of CFDPRESC field.
	OSCCTRL_XOSCCTRL_CFDPRESC_Msk = 0xf000000
	// 48 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV1 = 0x0
	// 24 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV2 = 0x1
	// 12 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV4 = 0x2
	// 6 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV8 = 0x3
	// 3 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV16 = 0x4
	// 1.5 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV32 = 0x5
	// 0.75 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV64 = 0x6
	// 0.3125 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV128 = 0x7

	// DFLLCTRLA: DFLL48M Control A
	// Position of ENABLE field.
	OSCCTRL_DFLLCTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	OSCCTRL_DFLLCTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	OSCCTRL_DFLLCTRLA_ENABLE = 0x2
	// Position of RUNSTDBY field.
	OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	OSCCTRL_DFLLCTRLA_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	OSCCTRL_DFLLCTRLA_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	OSCCTRL_DFLLCTRLA_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	OSCCTRL_DFLLCTRLA_ONDEMAND = 0x80

	// DFLLCTRLB: DFLL48M Control B
	// Position of MODE field.
	OSCCTRL_DFLLCTRLB_MODE_Pos = 0x0
	// Bit mask of MODE field.
	OSCCTRL_DFLLCTRLB_MODE_Msk = 0x1
	// Bit MODE.
	OSCCTRL_DFLLCTRLB_MODE = 0x1
	// Position of STABLE field.
	OSCCTRL_DFLLCTRLB_STABLE_Pos = 0x1
	// Bit mask of STABLE field.
	OSCCTRL_DFLLCTRLB_STABLE_Msk = 0x2
	// Bit STABLE.
	OSCCTRL_DFLLCTRLB_STABLE = 0x2
	// Position of LLAW field.
	OSCCTRL_DFLLCTRLB_LLAW_Pos = 0x2
	// Bit mask of LLAW field.
	OSCCTRL_DFLLCTRLB_LLAW_Msk = 0x4
	// Bit LLAW.
	OSCCTRL_DFLLCTRLB_LLAW = 0x4
	// Position of USBCRM field.
	OSCCTRL_DFLLCTRLB_USBCRM_Pos = 0x3
	// Bit mask of USBCRM field.
	OSCCTRL_DFLLCTRLB_USBCRM_Msk = 0x8
	// Bit USBCRM.
	OSCCTRL_DFLLCTRLB_USBCRM = 0x8
	// Position of CCDIS field.
	OSCCTRL_DFLLCTRLB_CCDIS_Pos = 0x4
	// Bit mask of CCDIS field.
	OSCCTRL_DFLLCTRLB_CCDIS_Msk = 0x10
	// Bit CCDIS.
	OSCCTRL_DFLLCTRLB_CCDIS = 0x10
	// Position of QLDIS field.
	OSCCTRL_DFLLCTRLB_QLDIS_Pos = 0x5
	// Bit mask of QLDIS field.
	OSCCTRL_DFLLCTRLB_QLDIS_Msk = 0x20
	// Bit QLDIS.
	OSCCTRL_DFLLCTRLB_QLDIS = 0x20
	// Position of BPLCKC field.
	OSCCTRL_DFLLCTRLB_BPLCKC_Pos = 0x6
	// Bit mask of BPLCKC field.
	OSCCTRL_DFLLCTRLB_BPLCKC_Msk = 0x40
	// Bit BPLCKC.
	OSCCTRL_DFLLCTRLB_BPLCKC = 0x40
	// Position of WAITLOCK field.
	OSCCTRL_DFLLCTRLB_WAITLOCK_Pos = 0x7
	// Bit mask of WAITLOCK field.
	OSCCTRL_DFLLCTRLB_WAITLOCK_Msk = 0x80
	// Bit WAITLOCK.
	OSCCTRL_DFLLCTRLB_WAITLOCK = 0x80

	// DFLLVAL: DFLL48M Value
	// Position of FINE field.
	OSCCTRL_DFLLVAL_FINE_Pos = 0x0
	// Bit mask of FINE field.
	OSCCTRL_DFLLVAL_FINE_Msk = 0xff
	// Position of COARSE field.
	OSCCTRL_DFLLVAL_COARSE_Pos = 0xa
	// Bit mask of COARSE field.
	OSCCTRL_DFLLVAL_COARSE_Msk = 0xfc00
	// Position of DIFF field.
	OSCCTRL_DFLLVAL_DIFF_Pos = 0x10
	// Bit mask of DIFF field.
	OSCCTRL_DFLLVAL_DIFF_Msk = 0xffff0000

	// DFLLMUL: DFLL48M Multiplier
	// Position of MUL field.
	OSCCTRL_DFLLMUL_MUL_Pos = 0x0
	// Bit mask of MUL field.
	OSCCTRL_DFLLMUL_MUL_Msk = 0xffff
	// Position of FSTEP field.
	OSCCTRL_DFLLMUL_FSTEP_Pos = 0x10
	// Bit mask of FSTEP field.
	OSCCTRL_DFLLMUL_FSTEP_Msk = 0xff0000
	// Position of CSTEP field.
	OSCCTRL_DFLLMUL_CSTEP_Pos = 0x1a
	// Bit mask of CSTEP field.
	OSCCTRL_DFLLMUL_CSTEP_Msk = 0xfc000000

	// DFLLSYNC: DFLL48M Synchronization
	// Position of ENABLE field.
	OSCCTRL_DFLLSYNC_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	OSCCTRL_DFLLSYNC_ENABLE_Msk = 0x2
	// Bit ENABLE.
	OSCCTRL_DFLLSYNC_ENABLE = 0x2
	// Position of DFLLCTRLB field.
	OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos = 0x2
	// Bit mask of DFLLCTRLB field.
	OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk = 0x4
	// Bit DFLLCTRLB.
	OSCCTRL_DFLLSYNC_DFLLCTRLB = 0x4
	// Position of DFLLVAL field.
	OSCCTRL_DFLLSYNC_DFLLVAL_Pos = 0x3
	// Bit mask of DFLLVAL field.
	OSCCTRL_DFLLSYNC_DFLLVAL_Msk = 0x8
	// Bit DFLLVAL.
	OSCCTRL_DFLLSYNC_DFLLVAL = 0x8
	// Position of DFLLMUL field.
	OSCCTRL_DFLLSYNC_DFLLMUL_Pos = 0x4
	// Bit mask of DFLLMUL field.
	OSCCTRL_DFLLSYNC_DFLLMUL_Msk = 0x10
	// Bit DFLLMUL.
	OSCCTRL_DFLLSYNC_DFLLMUL = 0x10

	// DPLL.DPLLCTRLA: DPLL Control A
	// Position of ENABLE field.
	OSCCTRL_DPLL_DPLLCTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	OSCCTRL_DPLL_DPLLCTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	OSCCTRL_DPLL_DPLLCTRLA_ENABLE = 0x2
	// Position of RUNSTDBY field.
	OSCCTRL_DPLL_DPLLCTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	OSCCTRL_DPLL_DPLLCTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	OSCCTRL_DPLL_DPLLCTRLA_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	OSCCTRL_DPLL_DPLLCTRLA_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	OSCCTRL_DPLL_DPLLCTRLA_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	OSCCTRL_DPLL_DPLLCTRLA_ONDEMAND = 0x80

	// DPLL.DPLLRATIO: DPLL Ratio Control
	// Position of LDR field.
	OSCCTRL_DPLL_DPLLRATIO_LDR_Pos = 0x0
	// Bit mask of LDR field.
	OSCCTRL_DPLL_DPLLRATIO_LDR_Msk = 0x1fff
	// Position of LDRFRAC field.
	OSCCTRL_DPLL_DPLLRATIO_LDRFRAC_Pos = 0x10
	// Bit mask of LDRFRAC field.
	OSCCTRL_DPLL_DPLLRATIO_LDRFRAC_Msk = 0x1f0000

	// DPLL.DPLLCTRLB: DPLL Control B
	// Position of FILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_Pos = 0x0
	// Bit mask of FILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_Msk = 0xf
	// Bandwidth = 92.7Khz and Damping Factor = 0.76
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER1 = 0x0
	// Bandwidth = 131Khz and Damping Factor = 1.08
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER2 = 0x1
	// Bandwidth = 46.4Khz and Damping Factor = 0.38
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER3 = 0x2
	// Bandwidth = 65.6Khz and Damping Factor = 0.54
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER4 = 0x3
	// Bandwidth = 131Khz and Damping Factor = 0.56
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER5 = 0x4
	// Bandwidth = 185Khz and Damping Factor = 0.79
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER6 = 0x5
	// Bandwidth = 65.6Khz and Damping Factor = 0.28
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER7 = 0x6
	// Bandwidth = 92.7Khz and Damping Factor = 0.39
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER8 = 0x7
	// Bandwidth = 46.4Khz and Damping Factor = 1.49
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER9 = 0x8
	// Bandwidth = 65.6Khz and Damping Factor = 2.11
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER10 = 0x9
	// Bandwidth = 23.2Khz and Damping Factor = 0.75
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER11 = 0xa
	// Bandwidth = 32.8Khz and Damping Factor = 1.06
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER12 = 0xb
	// Bandwidth = 65.6Khz and Damping Factor = 1.07
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER13 = 0xc
	// Bandwidth = 92.7Khz and Damping Factor = 1.51
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER14 = 0xd
	// Bandwidth = 32.8Khz and Damping Factor = 0.53
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER15 = 0xe
	// Bandwidth = 46.4Khz and Damping Factor = 0.75
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER16 = 0xf
	// Position of WUF field.
	OSCCTRL_DPLL_DPLLCTRLB_WUF_Pos = 0x4
	// Bit mask of WUF field.
	OSCCTRL_DPLL_DPLLCTRLB_WUF_Msk = 0x10
	// Bit WUF.
	OSCCTRL_DPLL_DPLLCTRLB_WUF = 0x10
	// Position of REFCLK field.
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_Pos = 0x5
	// Bit mask of REFCLK field.
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_Msk = 0xe0
	// Dedicated GCLK clock reference
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_GCLK = 0x0
	// XOSC32K clock reference
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_XOSC32 = 0x1
	// XOSC0 clock reference
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_XOSC0 = 0x2
	// XOSC1 clock reference
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_XOSC1 = 0x3
	// Position of LTIME field.
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_Pos = 0x8
	// Bit mask of LTIME field.
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_Msk = 0x700
	// No time-out. Automatic lock
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_DEFAULT = 0x0
	// Time-out if no lock within 800us
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_800US = 0x4
	// Time-out if no lock within 900us
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_900US = 0x5
	// Time-out if no lock within 1ms
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_1MS = 0x6
	// Time-out if no lock within 1.1ms
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_1P1MS = 0x7
	// Position of LBYPASS field.
	OSCCTRL_DPLL_DPLLCTRLB_LBYPASS_Pos = 0xb
	// Bit mask of LBYPASS field.
	OSCCTRL_DPLL_DPLLCTRLB_LBYPASS_Msk = 0x800
	// Bit LBYPASS.
	OSCCTRL_DPLL_DPLLCTRLB_LBYPASS = 0x800
	// Position of DCOFILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_Pos = 0xc
	// Bit mask of DCOFILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_Msk = 0x7000
	// Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER1 = 0x0
	// Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER2 = 0x1
	// Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER3 = 0x2
	// Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER4 = 0x3
	// Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER5 = 0x4
	// Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER6 = 0x5
	// Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER7 = 0x6
	// Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER8 = 0x7
	// Position of DCOEN field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOEN_Pos = 0xf
	// Bit mask of DCOEN field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOEN_Msk = 0x8000
	// Bit DCOEN.
	OSCCTRL_DPLL_DPLLCTRLB_DCOEN = 0x8000
	// Position of DIV field.
	OSCCTRL_DPLL_DPLLCTRLB_DIV_Pos = 0x10
	// Bit mask of DIV field.
	OSCCTRL_DPLL_DPLLCTRLB_DIV_Msk = 0x7ff0000

	// DPLL.DPLLSYNCBUSY: DPLL Synchronization Busy
	// Position of ENABLE field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	OSCCTRL_DPLL_DPLLSYNCBUSY_ENABLE = 0x2
	// Position of DPLLRATIO field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO_Pos = 0x2
	// Bit mask of DPLLRATIO field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO_Msk = 0x4
	// Bit DPLLRATIO.
	OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO = 0x4

	// DPLL.DPLLSTATUS: DPLL Status
	// Position of LOCK field.
	OSCCTRL_DPLL_DPLLSTATUS_LOCK_Pos = 0x0
	// Bit mask of LOCK field.
	OSCCTRL_DPLL_DPLLSTATUS_LOCK_Msk = 0x1
	// Bit LOCK.
	OSCCTRL_DPLL_DPLLSTATUS_LOCK = 0x1
	// Position of CLKRDY field.
	OSCCTRL_DPLL_DPLLSTATUS_CLKRDY_Pos = 0x1
	// Bit mask of CLKRDY field.
	OSCCTRL_DPLL_DPLLSTATUS_CLKRDY_Msk = 0x2
	// Bit CLKRDY.
	OSCCTRL_DPLL_DPLLSTATUS_CLKRDY = 0x2
)

// Bitfields for OSC32KCTRL: 32kHz Oscillators Control
const (
	// INTENCLR: Interrupt Enable Clear
	// Position of XOSC32KRDY field.
	OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos = 0x0
	// Bit mask of XOSC32KRDY field.
	OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk = 0x1
	// Bit XOSC32KRDY.
	OSC32KCTRL_INTENCLR_XOSC32KRDY = 0x1
	// Position of XOSC32KFAIL field.
	OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos = 0x2
	// Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk = 0x4
	// Bit XOSC32KFAIL.
	OSC32KCTRL_INTENCLR_XOSC32KFAIL = 0x4

	// INTENSET: Interrupt Enable Set
	// Position of XOSC32KRDY field.
	OSC32KCTRL_INTENSET_XOSC32KRDY_Pos = 0x0
	// Bit mask of XOSC32KRDY field.
	OSC32KCTRL_INTENSET_XOSC32KRDY_Msk = 0x1
	// Bit XOSC32KRDY.
	OSC32KCTRL_INTENSET_XOSC32KRDY = 0x1
	// Position of XOSC32KFAIL field.
	OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos = 0x2
	// Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk = 0x4
	// Bit XOSC32KFAIL.
	OSC32KCTRL_INTENSET_XOSC32KFAIL = 0x4

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of XOSC32KRDY field.
	OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos = 0x0
	// Bit mask of XOSC32KRDY field.
	OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk = 0x1
	// Bit XOSC32KRDY.
	OSC32KCTRL_INTFLAG_XOSC32KRDY = 0x1
	// Position of XOSC32KFAIL field.
	OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos = 0x2
	// Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk = 0x4
	// Bit XOSC32KFAIL.
	OSC32KCTRL_INTFLAG_XOSC32KFAIL = 0x4

	// STATUS: Power and Clocks Status
	// Position of XOSC32KRDY field.
	OSC32KCTRL_STATUS_XOSC32KRDY_Pos = 0x0
	// Bit mask of XOSC32KRDY field.
	OSC32KCTRL_STATUS_XOSC32KRDY_Msk = 0x1
	// Bit XOSC32KRDY.
	OSC32KCTRL_STATUS_XOSC32KRDY = 0x1
	// Position of XOSC32KFAIL field.
	OSC32KCTRL_STATUS_XOSC32KFAIL_Pos = 0x2
	// Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_STATUS_XOSC32KFAIL_Msk = 0x4
	// Bit XOSC32KFAIL.
	OSC32KCTRL_STATUS_XOSC32KFAIL = 0x4
	// Position of XOSC32KSW field.
	OSC32KCTRL_STATUS_XOSC32KSW_Pos = 0x3
	// Bit mask of XOSC32KSW field.
	OSC32KCTRL_STATUS_XOSC32KSW_Msk = 0x8
	// Bit XOSC32KSW.
	OSC32KCTRL_STATUS_XOSC32KSW = 0x8

	// RTCCTRL: RTC Clock Selection
	// Position of RTCSEL field.
	OSC32KCTRL_RTCCTRL_RTCSEL_Pos = 0x0
	// Bit mask of RTCSEL field.
	OSC32KCTRL_RTCCTRL_RTCSEL_Msk = 0x7
	// 1.024kHz from 32kHz internal ULP oscillator
	OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K = 0x0
	// 32.768kHz from 32kHz internal ULP oscillator
	OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K = 0x1
	// 1.024kHz from 32.768kHz internal oscillator
	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K = 0x4
	// 32.768kHz from 32.768kHz external crystal oscillator
	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K = 0x5

	// XOSC32K: 32kHz External Crystal Oscillator (XOSC32K) Control
	// Position of ENABLE field.
	OSC32KCTRL_XOSC32K_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	OSC32KCTRL_XOSC32K_ENABLE_Msk = 0x2
	// Bit ENABLE.
	OSC32KCTRL_XOSC32K_ENABLE = 0x2
	// Position of XTALEN field.
	OSC32KCTRL_XOSC32K_XTALEN_Pos = 0x2
	// Bit mask of XTALEN field.
	OSC32KCTRL_XOSC32K_XTALEN_Msk = 0x4
	// Bit XTALEN.
	OSC32KCTRL_XOSC32K_XTALEN = 0x4
	// Position of EN32K field.
	OSC32KCTRL_XOSC32K_EN32K_Pos = 0x3
	// Bit mask of EN32K field.
	OSC32KCTRL_XOSC32K_EN32K_Msk = 0x8
	// Bit EN32K.
	OSC32KCTRL_XOSC32K_EN32K = 0x8
	// Position of EN1K field.
	OSC32KCTRL_XOSC32K_EN1K_Pos = 0x4
	// Bit mask of EN1K field.
	OSC32KCTRL_XOSC32K_EN1K_Msk = 0x10
	// Bit EN1K.
	OSC32KCTRL_XOSC32K_EN1K = 0x10
	// Position of RUNSTDBY field.
	OSC32KCTRL_XOSC32K_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	OSC32KCTRL_XOSC32K_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	OSC32KCTRL_XOSC32K_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	OSC32KCTRL_XOSC32K_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	OSC32KCTRL_XOSC32K_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	OSC32KCTRL_XOSC32K_ONDEMAND = 0x80
	// Position of STARTUP field.
	OSC32KCTRL_XOSC32K_STARTUP_Pos = 0x8
	// Bit mask of STARTUP field.
	OSC32KCTRL_XOSC32K_STARTUP_Msk = 0x700
	// 62.6 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048 = 0x0
	// 125 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096 = 0x1
	// 500 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384 = 0x2
	// 1000 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768 = 0x3
	// 2000 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536 = 0x4
	// 4000 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072 = 0x5
	// 8000 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144 = 0x6
	// Position of WRTLOCK field.
	OSC32KCTRL_XOSC32K_WRTLOCK_Pos = 0xc
	// Bit mask of WRTLOCK field.
	OSC32KCTRL_XOSC32K_WRTLOCK_Msk = 0x1000
	// Bit WRTLOCK.
	OSC32KCTRL_XOSC32K_WRTLOCK = 0x1000
	// Position of CGM field.
	OSC32KCTRL_XOSC32K_CGM_Pos = 0xd
	// Bit mask of CGM field.
	OSC32KCTRL_XOSC32K_CGM_Msk = 0x6000
	// Standard mode
	OSC32KCTRL_XOSC32K_CGM_XT = 0x1
	// High Speed mode
	OSC32KCTRL_XOSC32K_CGM_HS = 0x2

	// CFDCTRL: Clock Failure Detector Control
	// Position of CFDEN field.
	OSC32KCTRL_CFDCTRL_CFDEN_Pos = 0x0
	// Bit mask of CFDEN field.
	OSC32KCTRL_CFDCTRL_CFDEN_Msk = 0x1
	// Bit CFDEN.
	OSC32KCTRL_CFDCTRL_CFDEN = 0x1
	// Position of SWBACK field.
	OSC32KCTRL_CFDCTRL_SWBACK_Pos = 0x1
	// Bit mask of SWBACK field.
	OSC32KCTRL_CFDCTRL_SWBACK_Msk = 0x2
	// Bit SWBACK.
	OSC32KCTRL_CFDCTRL_SWBACK = 0x2
	// Position of CFDPRESC field.
	OSC32KCTRL_CFDCTRL_CFDPRESC_Pos = 0x2
	// Bit mask of CFDPRESC field.
	OSC32KCTRL_CFDCTRL_CFDPRESC_Msk = 0x4
	// Bit CFDPRESC.
	OSC32KCTRL_CFDCTRL_CFDPRESC = 0x4

	// EVCTRL: Event Control
	// Position of CFDEO field.
	OSC32KCTRL_EVCTRL_CFDEO_Pos = 0x0
	// Bit mask of CFDEO field.
	OSC32KCTRL_EVCTRL_CFDEO_Msk = 0x1
	// Bit CFDEO.
	OSC32KCTRL_EVCTRL_CFDEO = 0x1

	// OSCULP32K: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
	// Position of EN32K field.
	OSC32KCTRL_OSCULP32K_EN32K_Pos = 0x1
	// Bit mask of EN32K field.
	OSC32KCTRL_OSCULP32K_EN32K_Msk = 0x2
	// Bit EN32K.
	OSC32KCTRL_OSCULP32K_EN32K = 0x2
	// Position of EN1K field.
	OSC32KCTRL_OSCULP32K_EN1K_Pos = 0x2
	// Bit mask of EN1K field.
	OSC32KCTRL_OSCULP32K_EN1K_Msk = 0x4
	// Bit EN1K.
	OSC32KCTRL_OSCULP32K_EN1K = 0x4
	// Position of CALIB field.
	OSC32KCTRL_OSCULP32K_CALIB_Pos = 0x8
	// Bit mask of CALIB field.
	OSC32KCTRL_OSCULP32K_CALIB_Msk = 0x3f00
	// Position of WRTLOCK field.
	OSC32KCTRL_OSCULP32K_WRTLOCK_Pos = 0xf
	// Bit mask of WRTLOCK field.
	OSC32KCTRL_OSCULP32K_WRTLOCK_Msk = 0x8000
	// Bit WRTLOCK.
	OSC32KCTRL_OSCULP32K_WRTLOCK = 0x8000
)

// Bitfields for PAC: Peripheral Access Controller
const (
	// WRCTRL: Write control
	// Position of PERID field.
	PAC_WRCTRL_PERID_Pos = 0x0
	// Bit mask of PERID field.
	PAC_WRCTRL_PERID_Msk = 0xffff
	// Position of KEY field.
	PAC_WRCTRL_KEY_Pos = 0x10
	// Bit mask of KEY field.
	PAC_WRCTRL_KEY_Msk = 0xff0000
	// No action
	PAC_WRCTRL_KEY_OFF = 0x0
	// Clear protection
	PAC_WRCTRL_KEY_CLR = 0x1
	// Set protection
	PAC_WRCTRL_KEY_SET = 0x2
	// Set and lock protection
	PAC_WRCTRL_KEY_SETLCK = 0x3

	// EVCTRL: Event control
	// Position of ERREO field.
	PAC_EVCTRL_ERREO_Pos = 0x0
	// Bit mask of ERREO field.
	PAC_EVCTRL_ERREO_Msk = 0x1
	// Bit ERREO.
	PAC_EVCTRL_ERREO = 0x1

	// INTENCLR: Interrupt enable clear
	// Position of ERR field.
	PAC_INTENCLR_ERR_Pos = 0x0
	// Bit mask of ERR field.
	PAC_INTENCLR_ERR_Msk = 0x1
	// Bit ERR.
	PAC_INTENCLR_ERR = 0x1

	// INTENSET: Interrupt enable set
	// Position of ERR field.
	PAC_INTENSET_ERR_Pos = 0x0
	// Bit mask of ERR field.
	PAC_INTENSET_ERR_Msk = 0x1
	// Bit ERR.
	PAC_INTENSET_ERR = 0x1

	// INTFLAGAHB: Bridge interrupt flag status
	// Position of FLASH_ field.
	PAC_INTFLAGAHB_FLASH__Pos = 0x0
	// Bit mask of FLASH_ field.
	PAC_INTFLAGAHB_FLASH__Msk = 0x1
	// Bit FLASH_.
	PAC_INTFLAGAHB_FLASH_ = 0x1
	// Position of FLASH_ALT_ field.
	PAC_INTFLAGAHB_FLASH_ALT__Pos = 0x1
	// Bit mask of FLASH_ALT_ field.
	PAC_INTFLAGAHB_FLASH_ALT__Msk = 0x2
	// Bit FLASH_ALT_.
	PAC_INTFLAGAHB_FLASH_ALT_ = 0x2
	// Position of SEEPROM_ field.
	PAC_INTFLAGAHB_SEEPROM__Pos = 0x2
	// Bit mask of SEEPROM_ field.
	PAC_INTFLAGAHB_SEEPROM__Msk = 0x4
	// Bit SEEPROM_.
	PAC_INTFLAGAHB_SEEPROM_ = 0x4
	// Position of RAMCM4S_ field.
	PAC_INTFLAGAHB_RAMCM4S__Pos = 0x3
	// Bit mask of RAMCM4S_ field.
	PAC_INTFLAGAHB_RAMCM4S__Msk = 0x8
	// Bit RAMCM4S_.
	PAC_INTFLAGAHB_RAMCM4S_ = 0x8
	// Position of RAMPPPDSU_ field.
	PAC_INTFLAGAHB_RAMPPPDSU__Pos = 0x4
	// Bit mask of RAMPPPDSU_ field.
	PAC_INTFLAGAHB_RAMPPPDSU__Msk = 0x10
	// Bit RAMPPPDSU_.
	PAC_INTFLAGAHB_RAMPPPDSU_ = 0x10
	// Position of RAMDMAWR_ field.
	PAC_INTFLAGAHB_RAMDMAWR__Pos = 0x5
	// Bit mask of RAMDMAWR_ field.
	PAC_INTFLAGAHB_RAMDMAWR__Msk = 0x20
	// Bit RAMDMAWR_.
	PAC_INTFLAGAHB_RAMDMAWR_ = 0x20
	// Position of RAMDMACICM_ field.
	PAC_INTFLAGAHB_RAMDMACICM__Pos = 0x6
	// Bit mask of RAMDMACICM_ field.
	PAC_INTFLAGAHB_RAMDMACICM__Msk = 0x40
	// Bit RAMDMACICM_.
	PAC_INTFLAGAHB_RAMDMACICM_ = 0x40
	// Position of HPB0_ field.
	PAC_INTFLAGAHB_HPB0__Pos = 0x7
	// Bit mask of HPB0_ field.
	PAC_INTFLAGAHB_HPB0__Msk = 0x80
	// Bit HPB0_.
	PAC_INTFLAGAHB_HPB0_ = 0x80
	// Position of HPB1_ field.
	PAC_INTFLAGAHB_HPB1__Pos = 0x8
	// Bit mask of HPB1_ field.
	PAC_INTFLAGAHB_HPB1__Msk = 0x100
	// Bit HPB1_.
	PAC_INTFLAGAHB_HPB1_ = 0x100
	// Position of HPB2_ field.
	PAC_INTFLAGAHB_HPB2__Pos = 0x9
	// Bit mask of HPB2_ field.
	PAC_INTFLAGAHB_HPB2__Msk = 0x200
	// Bit HPB2_.
	PAC_INTFLAGAHB_HPB2_ = 0x200
	// Position of HPB3_ field.
	PAC_INTFLAGAHB_HPB3__Pos = 0xa
	// Bit mask of HPB3_ field.
	PAC_INTFLAGAHB_HPB3__Msk = 0x400
	// Bit HPB3_.
	PAC_INTFLAGAHB_HPB3_ = 0x400
	// Position of PUKCC_ field.
	PAC_INTFLAGAHB_PUKCC__Pos = 0xb
	// Bit mask of PUKCC_ field.
	PAC_INTFLAGAHB_PUKCC__Msk = 0x800
	// Bit PUKCC_.
	PAC_INTFLAGAHB_PUKCC_ = 0x800
	// Position of SDHC0_ field.
	PAC_INTFLAGAHB_SDHC0__Pos = 0xc
	// Bit mask of SDHC0_ field.
	PAC_INTFLAGAHB_SDHC0__Msk = 0x1000
	// Bit SDHC0_.
	PAC_INTFLAGAHB_SDHC0_ = 0x1000
	// Position of SDHC1_ field.
	PAC_INTFLAGAHB_SDHC1__Pos = 0xd
	// Bit mask of SDHC1_ field.
	PAC_INTFLAGAHB_SDHC1__Msk = 0x2000
	// Bit SDHC1_.
	PAC_INTFLAGAHB_SDHC1_ = 0x2000
	// Position of QSPI_ field.
	PAC_INTFLAGAHB_QSPI__Pos = 0xe
	// Bit mask of QSPI_ field.
	PAC_INTFLAGAHB_QSPI__Msk = 0x4000
	// Bit QSPI_.
	PAC_INTFLAGAHB_QSPI_ = 0x4000
	// Position of BKUPRAM_ field.
	PAC_INTFLAGAHB_BKUPRAM__Pos = 0xf
	// Bit mask of BKUPRAM_ field.
	PAC_INTFLAGAHB_BKUPRAM__Msk = 0x8000
	// Bit BKUPRAM_.
	PAC_INTFLAGAHB_BKUPRAM_ = 0x8000

	// INTFLAGA: Peripheral interrupt flag status - Bridge A
	// Position of PAC_ field.
	PAC_INTFLAGA_PAC__Pos = 0x0
	// Bit mask of PAC_ field.
	PAC_INTFLAGA_PAC__Msk = 0x1
	// Bit PAC_.
	PAC_INTFLAGA_PAC_ = 0x1
	// Position of PM_ field.
	PAC_INTFLAGA_PM__Pos = 0x1
	// Bit mask of PM_ field.
	PAC_INTFLAGA_PM__Msk = 0x2
	// Bit PM_.
	PAC_INTFLAGA_PM_ = 0x2
	// Position of MCLK_ field.
	PAC_INTFLAGA_MCLK__Pos = 0x2
	// Bit mask of MCLK_ field.
	PAC_INTFLAGA_MCLK__Msk = 0x4
	// Bit MCLK_.
	PAC_INTFLAGA_MCLK_ = 0x4
	// Position of RSTC_ field.
	PAC_INTFLAGA_RSTC__Pos = 0x3
	// Bit mask of RSTC_ field.
	PAC_INTFLAGA_RSTC__Msk = 0x8
	// Bit RSTC_.
	PAC_INTFLAGA_RSTC_ = 0x8
	// Position of OSCCTRL_ field.
	PAC_INTFLAGA_OSCCTRL__Pos = 0x4
	// Bit mask of OSCCTRL_ field.
	PAC_INTFLAGA_OSCCTRL__Msk = 0x10
	// Bit OSCCTRL_.
	PAC_INTFLAGA_OSCCTRL_ = 0x10
	// Position of OSC32KCTRL_ field.
	PAC_INTFLAGA_OSC32KCTRL__Pos = 0x5
	// Bit mask of OSC32KCTRL_ field.
	PAC_INTFLAGA_OSC32KCTRL__Msk = 0x20
	// Bit OSC32KCTRL_.
	PAC_INTFLAGA_OSC32KCTRL_ = 0x20
	// Position of SUPC_ field.
	PAC_INTFLAGA_SUPC__Pos = 0x6
	// Bit mask of SUPC_ field.
	PAC_INTFLAGA_SUPC__Msk = 0x40
	// Bit SUPC_.
	PAC_INTFLAGA_SUPC_ = 0x40
	// Position of GCLK_ field.
	PAC_INTFLAGA_GCLK__Pos = 0x7
	// Bit mask of GCLK_ field.
	PAC_INTFLAGA_GCLK__Msk = 0x80
	// Bit GCLK_.
	PAC_INTFLAGA_GCLK_ = 0x80
	// Position of WDT_ field.
	PAC_INTFLAGA_WDT__Pos = 0x8
	// Bit mask of WDT_ field.
	PAC_INTFLAGA_WDT__Msk = 0x100
	// Bit WDT_.
	PAC_INTFLAGA_WDT_ = 0x100
	// Position of RTC_ field.
	PAC_INTFLAGA_RTC__Pos = 0x9
	// Bit mask of RTC_ field.
	PAC_INTFLAGA_RTC__Msk = 0x200
	// Bit RTC_.
	PAC_INTFLAGA_RTC_ = 0x200
	// Position of EIC_ field.
	PAC_INTFLAGA_EIC__Pos = 0xa
	// Bit mask of EIC_ field.
	PAC_INTFLAGA_EIC__Msk = 0x400
	// Bit EIC_.
	PAC_INTFLAGA_EIC_ = 0x400
	// Position of FREQM_ field.
	PAC_INTFLAGA_FREQM__Pos = 0xb
	// Bit mask of FREQM_ field.
	PAC_INTFLAGA_FREQM__Msk = 0x800
	// Bit FREQM_.
	PAC_INTFLAGA_FREQM_ = 0x800
	// Position of SERCOM0_ field.
	PAC_INTFLAGA_SERCOM0__Pos = 0xc
	// Bit mask of SERCOM0_ field.
	PAC_INTFLAGA_SERCOM0__Msk = 0x1000
	// Bit SERCOM0_.
	PAC_INTFLAGA_SERCOM0_ = 0x1000
	// Position of SERCOM1_ field.
	PAC_INTFLAGA_SERCOM1__Pos = 0xd
	// Bit mask of SERCOM1_ field.
	PAC_INTFLAGA_SERCOM1__Msk = 0x2000
	// Bit SERCOM1_.
	PAC_INTFLAGA_SERCOM1_ = 0x2000
	// Position of TC0_ field.
	PAC_INTFLAGA_TC0__Pos = 0xe
	// Bit mask of TC0_ field.
	PAC_INTFLAGA_TC0__Msk = 0x4000
	// Bit TC0_.
	PAC_INTFLAGA_TC0_ = 0x4000
	// Position of TC1_ field.
	PAC_INTFLAGA_TC1__Pos = 0xf
	// Bit mask of TC1_ field.
	PAC_INTFLAGA_TC1__Msk = 0x8000
	// Bit TC1_.
	PAC_INTFLAGA_TC1_ = 0x8000

	// INTFLAGB: Peripheral interrupt flag status - Bridge B
	// Position of USB_ field.
	PAC_INTFLAGB_USB__Pos = 0x0
	// Bit mask of USB_ field.
	PAC_INTFLAGB_USB__Msk = 0x1
	// Bit USB_.
	PAC_INTFLAGB_USB_ = 0x1
	// Position of DSU_ field.
	PAC_INTFLAGB_DSU__Pos = 0x1
	// Bit mask of DSU_ field.
	PAC_INTFLAGB_DSU__Msk = 0x2
	// Bit DSU_.
	PAC_INTFLAGB_DSU_ = 0x2
	// Position of NVMCTRL_ field.
	PAC_INTFLAGB_NVMCTRL__Pos = 0x2
	// Bit mask of NVMCTRL_ field.
	PAC_INTFLAGB_NVMCTRL__Msk = 0x4
	// Bit NVMCTRL_.
	PAC_INTFLAGB_NVMCTRL_ = 0x4
	// Position of CMCC_ field.
	PAC_INTFLAGB_CMCC__Pos = 0x3
	// Bit mask of CMCC_ field.
	PAC_INTFLAGB_CMCC__Msk = 0x8
	// Bit CMCC_.
	PAC_INTFLAGB_CMCC_ = 0x8
	// Position of PORT_ field.
	PAC_INTFLAGB_PORT__Pos = 0x4
	// Bit mask of PORT_ field.
	PAC_INTFLAGB_PORT__Msk = 0x10
	// Bit PORT_.
	PAC_INTFLAGB_PORT_ = 0x10
	// Position of DMAC_ field.
	PAC_INTFLAGB_DMAC__Pos = 0x5
	// Bit mask of DMAC_ field.
	PAC_INTFLAGB_DMAC__Msk = 0x20
	// Bit DMAC_.
	PAC_INTFLAGB_DMAC_ = 0x20
	// Position of HMATRIX_ field.
	PAC_INTFLAGB_HMATRIX__Pos = 0x6
	// Bit mask of HMATRIX_ field.
	PAC_INTFLAGB_HMATRIX__Msk = 0x40
	// Bit HMATRIX_.
	PAC_INTFLAGB_HMATRIX_ = 0x40
	// Position of EVSYS_ field.
	PAC_INTFLAGB_EVSYS__Pos = 0x7
	// Bit mask of EVSYS_ field.
	PAC_INTFLAGB_EVSYS__Msk = 0x80
	// Bit EVSYS_.
	PAC_INTFLAGB_EVSYS_ = 0x80
	// Position of SERCOM2_ field.
	PAC_INTFLAGB_SERCOM2__Pos = 0x9
	// Bit mask of SERCOM2_ field.
	PAC_INTFLAGB_SERCOM2__Msk = 0x200
	// Bit SERCOM2_.
	PAC_INTFLAGB_SERCOM2_ = 0x200
	// Position of SERCOM3_ field.
	PAC_INTFLAGB_SERCOM3__Pos = 0xa
	// Bit mask of SERCOM3_ field.
	PAC_INTFLAGB_SERCOM3__Msk = 0x400
	// Bit SERCOM3_.
	PAC_INTFLAGB_SERCOM3_ = 0x400
	// Position of TCC0_ field.
	PAC_INTFLAGB_TCC0__Pos = 0xb
	// Bit mask of TCC0_ field.
	PAC_INTFLAGB_TCC0__Msk = 0x800
	// Bit TCC0_.
	PAC_INTFLAGB_TCC0_ = 0x800
	// Position of TCC1_ field.
	PAC_INTFLAGB_TCC1__Pos = 0xc
	// Bit mask of TCC1_ field.
	PAC_INTFLAGB_TCC1__Msk = 0x1000
	// Bit TCC1_.
	PAC_INTFLAGB_TCC1_ = 0x1000
	// Position of TC2_ field.
	PAC_INTFLAGB_TC2__Pos = 0xd
	// Bit mask of TC2_ field.
	PAC_INTFLAGB_TC2__Msk = 0x2000
	// Bit TC2_.
	PAC_INTFLAGB_TC2_ = 0x2000
	// Position of TC3_ field.
	PAC_INTFLAGB_TC3__Pos = 0xe
	// Bit mask of TC3_ field.
	PAC_INTFLAGB_TC3__Msk = 0x4000
	// Bit TC3_.
	PAC_INTFLAGB_TC3_ = 0x4000
	// Position of RAMECC_ field.
	PAC_INTFLAGB_RAMECC__Pos = 0x10
	// Bit mask of RAMECC_ field.
	PAC_INTFLAGB_RAMECC__Msk = 0x10000
	// Bit RAMECC_.
	PAC_INTFLAGB_RAMECC_ = 0x10000

	// INTFLAGC: Peripheral interrupt flag status - Bridge C
	// Position of CAN0_ field.
	PAC_INTFLAGC_CAN0__Pos = 0x0
	// Bit mask of CAN0_ field.
	PAC_INTFLAGC_CAN0__Msk = 0x1
	// Bit CAN0_.
	PAC_INTFLAGC_CAN0_ = 0x1
	// Position of CAN1_ field.
	PAC_INTFLAGC_CAN1__Pos = 0x1
	// Bit mask of CAN1_ field.
	PAC_INTFLAGC_CAN1__Msk = 0x2
	// Bit CAN1_.
	PAC_INTFLAGC_CAN1_ = 0x2
	// Position of GMAC_ field.
	PAC_INTFLAGC_GMAC__Pos = 0x2
	// Bit mask of GMAC_ field.
	PAC_INTFLAGC_GMAC__Msk = 0x4
	// Bit GMAC_.
	PAC_INTFLAGC_GMAC_ = 0x4
	// Position of TCC2_ field.
	PAC_INTFLAGC_TCC2__Pos = 0x3
	// Bit mask of TCC2_ field.
	PAC_INTFLAGC_TCC2__Msk = 0x8
	// Bit TCC2_.
	PAC_INTFLAGC_TCC2_ = 0x8
	// Position of TCC3_ field.
	PAC_INTFLAGC_TCC3__Pos = 0x4
	// Bit mask of TCC3_ field.
	PAC_INTFLAGC_TCC3__Msk = 0x10
	// Bit TCC3_.
	PAC_INTFLAGC_TCC3_ = 0x10
	// Position of TC4_ field.
	PAC_INTFLAGC_TC4__Pos = 0x5
	// Bit mask of TC4_ field.
	PAC_INTFLAGC_TC4__Msk = 0x20
	// Bit TC4_.
	PAC_INTFLAGC_TC4_ = 0x20
	// Position of TC5_ field.
	PAC_INTFLAGC_TC5__Pos = 0x6
	// Bit mask of TC5_ field.
	PAC_INTFLAGC_TC5__Msk = 0x40
	// Bit TC5_.
	PAC_INTFLAGC_TC5_ = 0x40
	// Position of PDEC_ field.
	PAC_INTFLAGC_PDEC__Pos = 0x7
	// Bit mask of PDEC_ field.
	PAC_INTFLAGC_PDEC__Msk = 0x80
	// Bit PDEC_.
	PAC_INTFLAGC_PDEC_ = 0x80
	// Position of AC_ field.
	PAC_INTFLAGC_AC__Pos = 0x8
	// Bit mask of AC_ field.
	PAC_INTFLAGC_AC__Msk = 0x100
	// Bit AC_.
	PAC_INTFLAGC_AC_ = 0x100
	// Position of AES_ field.
	PAC_INTFLAGC_AES__Pos = 0x9
	// Bit mask of AES_ field.
	PAC_INTFLAGC_AES__Msk = 0x200
	// Bit AES_.
	PAC_INTFLAGC_AES_ = 0x200
	// Position of TRNG_ field.
	PAC_INTFLAGC_TRNG__Pos = 0xa
	// Bit mask of TRNG_ field.
	PAC_INTFLAGC_TRNG__Msk = 0x400
	// Bit TRNG_.
	PAC_INTFLAGC_TRNG_ = 0x400
	// Position of ICM_ field.
	PAC_INTFLAGC_ICM__Pos = 0xb
	// Bit mask of ICM_ field.
	PAC_INTFLAGC_ICM__Msk = 0x800
	// Bit ICM_.
	PAC_INTFLAGC_ICM_ = 0x800
	// Position of PUKCC_ field.
	PAC_INTFLAGC_PUKCC__Pos = 0xc
	// Bit mask of PUKCC_ field.
	PAC_INTFLAGC_PUKCC__Msk = 0x1000
	// Bit PUKCC_.
	PAC_INTFLAGC_PUKCC_ = 0x1000
	// Position of QSPI_ field.
	PAC_INTFLAGC_QSPI__Pos = 0xd
	// Bit mask of QSPI_ field.
	PAC_INTFLAGC_QSPI__Msk = 0x2000
	// Bit QSPI_.
	PAC_INTFLAGC_QSPI_ = 0x2000
	// Position of CCL_ field.
	PAC_INTFLAGC_CCL__Pos = 0xe
	// Bit mask of CCL_ field.
	PAC_INTFLAGC_CCL__Msk = 0x4000
	// Bit CCL_.
	PAC_INTFLAGC_CCL_ = 0x4000

	// INTFLAGD: Peripheral interrupt flag status - Bridge D
	// Position of SERCOM4_ field.
	PAC_INTFLAGD_SERCOM4__Pos = 0x0
	// Bit mask of SERCOM4_ field.
	PAC_INTFLAGD_SERCOM4__Msk = 0x1
	// Bit SERCOM4_.
	PAC_INTFLAGD_SERCOM4_ = 0x1
	// Position of SERCOM5_ field.
	PAC_INTFLAGD_SERCOM5__Pos = 0x1
	// Bit mask of SERCOM5_ field.
	PAC_INTFLAGD_SERCOM5__Msk = 0x2
	// Bit SERCOM5_.
	PAC_INTFLAGD_SERCOM5_ = 0x2
	// Position of SERCOM6_ field.
	PAC_INTFLAGD_SERCOM6__Pos = 0x2
	// Bit mask of SERCOM6_ field.
	PAC_INTFLAGD_SERCOM6__Msk = 0x4
	// Bit SERCOM6_.
	PAC_INTFLAGD_SERCOM6_ = 0x4
	// Position of SERCOM7_ field.
	PAC_INTFLAGD_SERCOM7__Pos = 0x3
	// Bit mask of SERCOM7_ field.
	PAC_INTFLAGD_SERCOM7__Msk = 0x8
	// Bit SERCOM7_.
	PAC_INTFLAGD_SERCOM7_ = 0x8
	// Position of TCC4_ field.
	PAC_INTFLAGD_TCC4__Pos = 0x4
	// Bit mask of TCC4_ field.
	PAC_INTFLAGD_TCC4__Msk = 0x10
	// Bit TCC4_.
	PAC_INTFLAGD_TCC4_ = 0x10
	// Position of TC6_ field.
	PAC_INTFLAGD_TC6__Pos = 0x5
	// Bit mask of TC6_ field.
	PAC_INTFLAGD_TC6__Msk = 0x20
	// Bit TC6_.
	PAC_INTFLAGD_TC6_ = 0x20
	// Position of TC7_ field.
	PAC_INTFLAGD_TC7__Pos = 0x6
	// Bit mask of TC7_ field.
	PAC_INTFLAGD_TC7__Msk = 0x40
	// Bit TC7_.
	PAC_INTFLAGD_TC7_ = 0x40
	// Position of ADC0_ field.
	PAC_INTFLAGD_ADC0__Pos = 0x7
	// Bit mask of ADC0_ field.
	PAC_INTFLAGD_ADC0__Msk = 0x80
	// Bit ADC0_.
	PAC_INTFLAGD_ADC0_ = 0x80
	// Position of ADC1_ field.
	PAC_INTFLAGD_ADC1__Pos = 0x8
	// Bit mask of ADC1_ field.
	PAC_INTFLAGD_ADC1__Msk = 0x100
	// Bit ADC1_.
	PAC_INTFLAGD_ADC1_ = 0x100
	// Position of DAC_ field.
	PAC_INTFLAGD_DAC__Pos = 0x9
	// Bit mask of DAC_ field.
	PAC_INTFLAGD_DAC__Msk = 0x200
	// Bit DAC_.
	PAC_INTFLAGD_DAC_ = 0x200
	// Position of I2S_ field.
	PAC_INTFLAGD_I2S__Pos = 0xa
	// Bit mask of I2S_ field.
	PAC_INTFLAGD_I2S__Msk = 0x400
	// Bit I2S_.
	PAC_INTFLAGD_I2S_ = 0x400
	// Position of PCC_ field.
	PAC_INTFLAGD_PCC__Pos = 0xb
	// Bit mask of PCC_ field.
	PAC_INTFLAGD_PCC__Msk = 0x800
	// Bit PCC_.
	PAC_INTFLAGD_PCC_ = 0x800

	// STATUSA: Peripheral write protection status - Bridge A
	// Position of PAC_ field.
	PAC_STATUSA_PAC__Pos = 0x0
	// Bit mask of PAC_ field.
	PAC_STATUSA_PAC__Msk = 0x1
	// Bit PAC_.
	PAC_STATUSA_PAC_ = 0x1
	// Position of PM_ field.
	PAC_STATUSA_PM__Pos = 0x1
	// Bit mask of PM_ field.
	PAC_STATUSA_PM__Msk = 0x2
	// Bit PM_.
	PAC_STATUSA_PM_ = 0x2
	// Position of MCLK_ field.
	PAC_STATUSA_MCLK__Pos = 0x2
	// Bit mask of MCLK_ field.
	PAC_STATUSA_MCLK__Msk = 0x4
	// Bit MCLK_.
	PAC_STATUSA_MCLK_ = 0x4
	// Position of RSTC_ field.
	PAC_STATUSA_RSTC__Pos = 0x3
	// Bit mask of RSTC_ field.
	PAC_STATUSA_RSTC__Msk = 0x8
	// Bit RSTC_.
	PAC_STATUSA_RSTC_ = 0x8
	// Position of OSCCTRL_ field.
	PAC_STATUSA_OSCCTRL__Pos = 0x4
	// Bit mask of OSCCTRL_ field.
	PAC_STATUSA_OSCCTRL__Msk = 0x10
	// Bit OSCCTRL_.
	PAC_STATUSA_OSCCTRL_ = 0x10
	// Position of OSC32KCTRL_ field.
	PAC_STATUSA_OSC32KCTRL__Pos = 0x5
	// Bit mask of OSC32KCTRL_ field.
	PAC_STATUSA_OSC32KCTRL__Msk = 0x20
	// Bit OSC32KCTRL_.
	PAC_STATUSA_OSC32KCTRL_ = 0x20
	// Position of SUPC_ field.
	PAC_STATUSA_SUPC__Pos = 0x6
	// Bit mask of SUPC_ field.
	PAC_STATUSA_SUPC__Msk = 0x40
	// Bit SUPC_.
	PAC_STATUSA_SUPC_ = 0x40
	// Position of GCLK_ field.
	PAC_STATUSA_GCLK__Pos = 0x7
	// Bit mask of GCLK_ field.
	PAC_STATUSA_GCLK__Msk = 0x80
	// Bit GCLK_.
	PAC_STATUSA_GCLK_ = 0x80
	// Position of WDT_ field.
	PAC_STATUSA_WDT__Pos = 0x8
	// Bit mask of WDT_ field.
	PAC_STATUSA_WDT__Msk = 0x100
	// Bit WDT_.
	PAC_STATUSA_WDT_ = 0x100
	// Position of RTC_ field.
	PAC_STATUSA_RTC__Pos = 0x9
	// Bit mask of RTC_ field.
	PAC_STATUSA_RTC__Msk = 0x200
	// Bit RTC_.
	PAC_STATUSA_RTC_ = 0x200
	// Position of EIC_ field.
	PAC_STATUSA_EIC__Pos = 0xa
	// Bit mask of EIC_ field.
	PAC_STATUSA_EIC__Msk = 0x400
	// Bit EIC_.
	PAC_STATUSA_EIC_ = 0x400
	// Position of FREQM_ field.
	PAC_STATUSA_FREQM__Pos = 0xb
	// Bit mask of FREQM_ field.
	PAC_STATUSA_FREQM__Msk = 0x800
	// Bit FREQM_.
	PAC_STATUSA_FREQM_ = 0x800
	// Position of SERCOM0_ field.
	PAC_STATUSA_SERCOM0__Pos = 0xc
	// Bit mask of SERCOM0_ field.
	PAC_STATUSA_SERCOM0__Msk = 0x1000
	// Bit SERCOM0_.
	PAC_STATUSA_SERCOM0_ = 0x1000
	// Position of SERCOM1_ field.
	PAC_STATUSA_SERCOM1__Pos = 0xd
	// Bit mask of SERCOM1_ field.
	PAC_STATUSA_SERCOM1__Msk = 0x2000
	// Bit SERCOM1_.
	PAC_STATUSA_SERCOM1_ = 0x2000
	// Position of TC0_ field.
	PAC_STATUSA_TC0__Pos = 0xe
	// Bit mask of TC0_ field.
	PAC_STATUSA_TC0__Msk = 0x4000
	// Bit TC0_.
	PAC_STATUSA_TC0_ = 0x4000
	// Position of TC1_ field.
	PAC_STATUSA_TC1__Pos = 0xf
	// Bit mask of TC1_ field.
	PAC_STATUSA_TC1__Msk = 0x8000
	// Bit TC1_.
	PAC_STATUSA_TC1_ = 0x8000

	// STATUSB: Peripheral write protection status - Bridge B
	// Position of USB_ field.
	PAC_STATUSB_USB__Pos = 0x0
	// Bit mask of USB_ field.
	PAC_STATUSB_USB__Msk = 0x1
	// Bit USB_.
	PAC_STATUSB_USB_ = 0x1
	// Position of DSU_ field.
	PAC_STATUSB_DSU__Pos = 0x1
	// Bit mask of DSU_ field.
	PAC_STATUSB_DSU__Msk = 0x2
	// Bit DSU_.
	PAC_STATUSB_DSU_ = 0x2
	// Position of NVMCTRL_ field.
	PAC_STATUSB_NVMCTRL__Pos = 0x2
	// Bit mask of NVMCTRL_ field.
	PAC_STATUSB_NVMCTRL__Msk = 0x4
	// Bit NVMCTRL_.
	PAC_STATUSB_NVMCTRL_ = 0x4
	// Position of CMCC_ field.
	PAC_STATUSB_CMCC__Pos = 0x3
	// Bit mask of CMCC_ field.
	PAC_STATUSB_CMCC__Msk = 0x8
	// Bit CMCC_.
	PAC_STATUSB_CMCC_ = 0x8
	// Position of PORT_ field.
	PAC_STATUSB_PORT__Pos = 0x4
	// Bit mask of PORT_ field.
	PAC_STATUSB_PORT__Msk = 0x10
	// Bit PORT_.
	PAC_STATUSB_PORT_ = 0x10
	// Position of DMAC_ field.
	PAC_STATUSB_DMAC__Pos = 0x5
	// Bit mask of DMAC_ field.
	PAC_STATUSB_DMAC__Msk = 0x20
	// Bit DMAC_.
	PAC_STATUSB_DMAC_ = 0x20
	// Position of HMATRIX_ field.
	PAC_STATUSB_HMATRIX__Pos = 0x6
	// Bit mask of HMATRIX_ field.
	PAC_STATUSB_HMATRIX__Msk = 0x40
	// Bit HMATRIX_.
	PAC_STATUSB_HMATRIX_ = 0x40
	// Position of EVSYS_ field.
	PAC_STATUSB_EVSYS__Pos = 0x7
	// Bit mask of EVSYS_ field.
	PAC_STATUSB_EVSYS__Msk = 0x80
	// Bit EVSYS_.
	PAC_STATUSB_EVSYS_ = 0x80
	// Position of SERCOM2_ field.
	PAC_STATUSB_SERCOM2__Pos = 0x9
	// Bit mask of SERCOM2_ field.
	PAC_STATUSB_SERCOM2__Msk = 0x200
	// Bit SERCOM2_.
	PAC_STATUSB_SERCOM2_ = 0x200
	// Position of SERCOM3_ field.
	PAC_STATUSB_SERCOM3__Pos = 0xa
	// Bit mask of SERCOM3_ field.
	PAC_STATUSB_SERCOM3__Msk = 0x400
	// Bit SERCOM3_.
	PAC_STATUSB_SERCOM3_ = 0x400
	// Position of TCC0_ field.
	PAC_STATUSB_TCC0__Pos = 0xb
	// Bit mask of TCC0_ field.
	PAC_STATUSB_TCC0__Msk = 0x800
	// Bit TCC0_.
	PAC_STATUSB_TCC0_ = 0x800
	// Position of TCC1_ field.
	PAC_STATUSB_TCC1__Pos = 0xc
	// Bit mask of TCC1_ field.
	PAC_STATUSB_TCC1__Msk = 0x1000
	// Bit TCC1_.
	PAC_STATUSB_TCC1_ = 0x1000
	// Position of TC2_ field.
	PAC_STATUSB_TC2__Pos = 0xd
	// Bit mask of TC2_ field.
	PAC_STATUSB_TC2__Msk = 0x2000
	// Bit TC2_.
	PAC_STATUSB_TC2_ = 0x2000
	// Position of TC3_ field.
	PAC_STATUSB_TC3__Pos = 0xe
	// Bit mask of TC3_ field.
	PAC_STATUSB_TC3__Msk = 0x4000
	// Bit TC3_.
	PAC_STATUSB_TC3_ = 0x4000
	// Position of RAMECC_ field.
	PAC_STATUSB_RAMECC__Pos = 0x10
	// Bit mask of RAMECC_ field.
	PAC_STATUSB_RAMECC__Msk = 0x10000
	// Bit RAMECC_.
	PAC_STATUSB_RAMECC_ = 0x10000

	// STATUSC: Peripheral write protection status - Bridge C
	// Position of CAN0_ field.
	PAC_STATUSC_CAN0__Pos = 0x0
	// Bit mask of CAN0_ field.
	PAC_STATUSC_CAN0__Msk = 0x1
	// Bit CAN0_.
	PAC_STATUSC_CAN0_ = 0x1
	// Position of CAN1_ field.
	PAC_STATUSC_CAN1__Pos = 0x1
	// Bit mask of CAN1_ field.
	PAC_STATUSC_CAN1__Msk = 0x2
	// Bit CAN1_.
	PAC_STATUSC_CAN1_ = 0x2
	// Position of GMAC_ field.
	PAC_STATUSC_GMAC__Pos = 0x2
	// Bit mask of GMAC_ field.
	PAC_STATUSC_GMAC__Msk = 0x4
	// Bit GMAC_.
	PAC_STATUSC_GMAC_ = 0x4
	// Position of TCC2_ field.
	PAC_STATUSC_TCC2__Pos = 0x3
	// Bit mask of TCC2_ field.
	PAC_STATUSC_TCC2__Msk = 0x8
	// Bit TCC2_.
	PAC_STATUSC_TCC2_ = 0x8
	// Position of TCC3_ field.
	PAC_STATUSC_TCC3__Pos = 0x4
	// Bit mask of TCC3_ field.
	PAC_STATUSC_TCC3__Msk = 0x10
	// Bit TCC3_.
	PAC_STATUSC_TCC3_ = 0x10
	// Position of TC4_ field.
	PAC_STATUSC_TC4__Pos = 0x5
	// Bit mask of TC4_ field.
	PAC_STATUSC_TC4__Msk = 0x20
	// Bit TC4_.
	PAC_STATUSC_TC4_ = 0x20
	// Position of TC5_ field.
	PAC_STATUSC_TC5__Pos = 0x6
	// Bit mask of TC5_ field.
	PAC_STATUSC_TC5__Msk = 0x40
	// Bit TC5_.
	PAC_STATUSC_TC5_ = 0x40
	// Position of PDEC_ field.
	PAC_STATUSC_PDEC__Pos = 0x7
	// Bit mask of PDEC_ field.
	PAC_STATUSC_PDEC__Msk = 0x80
	// Bit PDEC_.
	PAC_STATUSC_PDEC_ = 0x80
	// Position of AC_ field.
	PAC_STATUSC_AC__Pos = 0x8
	// Bit mask of AC_ field.
	PAC_STATUSC_AC__Msk = 0x100
	// Bit AC_.
	PAC_STATUSC_AC_ = 0x100
	// Position of AES_ field.
	PAC_STATUSC_AES__Pos = 0x9
	// Bit mask of AES_ field.
	PAC_STATUSC_AES__Msk = 0x200
	// Bit AES_.
	PAC_STATUSC_AES_ = 0x200
	// Position of TRNG_ field.
	PAC_STATUSC_TRNG__Pos = 0xa
	// Bit mask of TRNG_ field.
	PAC_STATUSC_TRNG__Msk = 0x400
	// Bit TRNG_.
	PAC_STATUSC_TRNG_ = 0x400
	// Position of ICM_ field.
	PAC_STATUSC_ICM__Pos = 0xb
	// Bit mask of ICM_ field.
	PAC_STATUSC_ICM__Msk = 0x800
	// Bit ICM_.
	PAC_STATUSC_ICM_ = 0x800
	// Position of PUKCC_ field.
	PAC_STATUSC_PUKCC__Pos = 0xc
	// Bit mask of PUKCC_ field.
	PAC_STATUSC_PUKCC__Msk = 0x1000
	// Bit PUKCC_.
	PAC_STATUSC_PUKCC_ = 0x1000
	// Position of QSPI_ field.
	PAC_STATUSC_QSPI__Pos = 0xd
	// Bit mask of QSPI_ field.
	PAC_STATUSC_QSPI__Msk = 0x2000
	// Bit QSPI_.
	PAC_STATUSC_QSPI_ = 0x2000
	// Position of CCL_ field.
	PAC_STATUSC_CCL__Pos = 0xe
	// Bit mask of CCL_ field.
	PAC_STATUSC_CCL__Msk = 0x4000
	// Bit CCL_.
	PAC_STATUSC_CCL_ = 0x4000

	// STATUSD: Peripheral write protection status - Bridge D
	// Position of SERCOM4_ field.
	PAC_STATUSD_SERCOM4__Pos = 0x0
	// Bit mask of SERCOM4_ field.
	PAC_STATUSD_SERCOM4__Msk = 0x1
	// Bit SERCOM4_.
	PAC_STATUSD_SERCOM4_ = 0x1
	// Position of SERCOM5_ field.
	PAC_STATUSD_SERCOM5__Pos = 0x1
	// Bit mask of SERCOM5_ field.
	PAC_STATUSD_SERCOM5__Msk = 0x2
	// Bit SERCOM5_.
	PAC_STATUSD_SERCOM5_ = 0x2
	// Position of SERCOM6_ field.
	PAC_STATUSD_SERCOM6__Pos = 0x2
	// Bit mask of SERCOM6_ field.
	PAC_STATUSD_SERCOM6__Msk = 0x4
	// Bit SERCOM6_.
	PAC_STATUSD_SERCOM6_ = 0x4
	// Position of SERCOM7_ field.
	PAC_STATUSD_SERCOM7__Pos = 0x3
	// Bit mask of SERCOM7_ field.
	PAC_STATUSD_SERCOM7__Msk = 0x8
	// Bit SERCOM7_.
	PAC_STATUSD_SERCOM7_ = 0x8
	// Position of TCC4_ field.
	PAC_STATUSD_TCC4__Pos = 0x4
	// Bit mask of TCC4_ field.
	PAC_STATUSD_TCC4__Msk = 0x10
	// Bit TCC4_.
	PAC_STATUSD_TCC4_ = 0x10
	// Position of TC6_ field.
	PAC_STATUSD_TC6__Pos = 0x5
	// Bit mask of TC6_ field.
	PAC_STATUSD_TC6__Msk = 0x20
	// Bit TC6_.
	PAC_STATUSD_TC6_ = 0x20
	// Position of TC7_ field.
	PAC_STATUSD_TC7__Pos = 0x6
	// Bit mask of TC7_ field.
	PAC_STATUSD_TC7__Msk = 0x40
	// Bit TC7_.
	PAC_STATUSD_TC7_ = 0x40
	// Position of ADC0_ field.
	PAC_STATUSD_ADC0__Pos = 0x7
	// Bit mask of ADC0_ field.
	PAC_STATUSD_ADC0__Msk = 0x80
	// Bit ADC0_.
	PAC_STATUSD_ADC0_ = 0x80
	// Position of ADC1_ field.
	PAC_STATUSD_ADC1__Pos = 0x8
	// Bit mask of ADC1_ field.
	PAC_STATUSD_ADC1__Msk = 0x100
	// Bit ADC1_.
	PAC_STATUSD_ADC1_ = 0x100
	// Position of DAC_ field.
	PAC_STATUSD_DAC__Pos = 0x9
	// Bit mask of DAC_ field.
	PAC_STATUSD_DAC__Msk = 0x200
	// Bit DAC_.
	PAC_STATUSD_DAC_ = 0x200
	// Position of I2S_ field.
	PAC_STATUSD_I2S__Pos = 0xa
	// Bit mask of I2S_ field.
	PAC_STATUSD_I2S__Msk = 0x400
	// Bit I2S_.
	PAC_STATUSD_I2S_ = 0x400
	// Position of PCC_ field.
	PAC_STATUSD_PCC__Pos = 0xb
	// Bit mask of PCC_ field.
	PAC_STATUSD_PCC__Msk = 0x800
	// Bit PCC_.
	PAC_STATUSD_PCC_ = 0x800
)

// Bitfields for PCC: Parallel Capture Controller
const (
	// MR: Mode Register
	// Position of PCEN field.
	PCC_MR_PCEN_Pos = 0x0
	// Bit mask of PCEN field.
	PCC_MR_PCEN_Msk = 0x1
	// Bit PCEN.
	PCC_MR_PCEN = 0x1
	// Position of DSIZE field.
	PCC_MR_DSIZE_Pos = 0x4
	// Bit mask of DSIZE field.
	PCC_MR_DSIZE_Msk = 0x30
	// Position of SCALE field.
	PCC_MR_SCALE_Pos = 0x8
	// Bit mask of SCALE field.
	PCC_MR_SCALE_Msk = 0x100
	// Bit SCALE.
	PCC_MR_SCALE = 0x100
	// Position of ALWYS field.
	PCC_MR_ALWYS_Pos = 0x9
	// Bit mask of ALWYS field.
	PCC_MR_ALWYS_Msk = 0x200
	// Bit ALWYS.
	PCC_MR_ALWYS = 0x200
	// Position of HALFS field.
	PCC_MR_HALFS_Pos = 0xa
	// Bit mask of HALFS field.
	PCC_MR_HALFS_Msk = 0x400
	// Bit HALFS.
	PCC_MR_HALFS = 0x400
	// Position of FRSTS field.
	PCC_MR_FRSTS_Pos = 0xb
	// Bit mask of FRSTS field.
	PCC_MR_FRSTS_Msk = 0x800
	// Bit FRSTS.
	PCC_MR_FRSTS = 0x800
	// Position of ISIZE field.
	PCC_MR_ISIZE_Pos = 0x10
	// Bit mask of ISIZE field.
	PCC_MR_ISIZE_Msk = 0x70000
	// Position of CID field.
	PCC_MR_CID_Pos = 0x1e
	// Bit mask of CID field.
	PCC_MR_CID_Msk = 0xc0000000

	// IER: Interrupt Enable Register
	// Position of DRDY field.
	PCC_IER_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	PCC_IER_DRDY_Msk = 0x1
	// Bit DRDY.
	PCC_IER_DRDY = 0x1
	// Position of OVRE field.
	PCC_IER_OVRE_Pos = 0x1
	// Bit mask of OVRE field.
	PCC_IER_OVRE_Msk = 0x2
	// Bit OVRE.
	PCC_IER_OVRE = 0x2

	// IDR: Interrupt Disable Register
	// Position of DRDY field.
	PCC_IDR_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	PCC_IDR_DRDY_Msk = 0x1
	// Bit DRDY.
	PCC_IDR_DRDY = 0x1
	// Position of OVRE field.
	PCC_IDR_OVRE_Pos = 0x1
	// Bit mask of OVRE field.
	PCC_IDR_OVRE_Msk = 0x2
	// Bit OVRE.
	PCC_IDR_OVRE = 0x2

	// IMR: Interrupt Mask Register
	// Position of DRDY field.
	PCC_IMR_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	PCC_IMR_DRDY_Msk = 0x1
	// Bit DRDY.
	PCC_IMR_DRDY = 0x1
	// Position of OVRE field.
	PCC_IMR_OVRE_Pos = 0x1
	// Bit mask of OVRE field.
	PCC_IMR_OVRE_Msk = 0x2
	// Bit OVRE.
	PCC_IMR_OVRE = 0x2

	// ISR: Interrupt Status Register
	// Position of DRDY field.
	PCC_ISR_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	PCC_ISR_DRDY_Msk = 0x1
	// Bit DRDY.
	PCC_ISR_DRDY = 0x1
	// Position of OVRE field.
	PCC_ISR_OVRE_Pos = 0x1
	// Bit mask of OVRE field.
	PCC_ISR_OVRE_Msk = 0x2
	// Bit OVRE.
	PCC_ISR_OVRE = 0x2

	// RHR: Reception Holding Register
	// Position of RDATA field.
	PCC_RHR_RDATA_Pos = 0x0
	// Bit mask of RDATA field.
	PCC_RHR_RDATA_Msk = 0xffffffff

	// WPMR: Write Protection Mode Register
	// Position of WPEN field.
	PCC_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	PCC_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	PCC_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	PCC_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	PCC_WPMR_WPKEY_Msk = 0xffffff00

	// WPSR: Write Protection Status Register
	// Position of WPVS field.
	PCC_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	PCC_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	PCC_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	PCC_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	PCC_WPSR_WPVSRC_Msk = 0xffff00
)

// Bitfields for PDEC: Quadrature Decodeur
const (
	// CTRLA: Control A
	// Position of SWRST field.
	PDEC_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	PDEC_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	PDEC_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	PDEC_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	PDEC_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	PDEC_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	PDEC_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	PDEC_CTRLA_MODE_Msk = 0xc
	// QDEC operating mode
	PDEC_CTRLA_MODE_QDEC = 0x0
	// HALL operating mode
	PDEC_CTRLA_MODE_HALL = 0x1
	// COUNTER operating mode
	PDEC_CTRLA_MODE_COUNTER = 0x2
	// Position of RUNSTDBY field.
	PDEC_CTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	PDEC_CTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	PDEC_CTRLA_RUNSTDBY = 0x40
	// Position of CONF field.
	PDEC_CTRLA_CONF_Pos = 0x8
	// Bit mask of CONF field.
	PDEC_CTRLA_CONF_Msk = 0x700
	// Quadrature decoder direction
	PDEC_CTRLA_CONF_X4 = 0x0
	// Secure Quadrature decoder direction
	PDEC_CTRLA_CONF_X4S = 0x1
	// Decoder direction
	PDEC_CTRLA_CONF_X2 = 0x2
	// Secure decoder direction
	PDEC_CTRLA_CONF_X2S = 0x3
	// Auto correction mode
	PDEC_CTRLA_CONF_AUTOC = 0x4
	// Position of ALOCK field.
	PDEC_CTRLA_ALOCK_Pos = 0xb
	// Bit mask of ALOCK field.
	PDEC_CTRLA_ALOCK_Msk = 0x800
	// Bit ALOCK.
	PDEC_CTRLA_ALOCK = 0x800
	// Position of SWAP field.
	PDEC_CTRLA_SWAP_Pos = 0xe
	// Bit mask of SWAP field.
	PDEC_CTRLA_SWAP_Msk = 0x4000
	// Bit SWAP.
	PDEC_CTRLA_SWAP = 0x4000
	// Position of PEREN field.
	PDEC_CTRLA_PEREN_Pos = 0xf
	// Bit mask of PEREN field.
	PDEC_CTRLA_PEREN_Msk = 0x8000
	// Bit PEREN.
	PDEC_CTRLA_PEREN = 0x8000
	// Position of PINEN0 field.
	PDEC_CTRLA_PINEN0_Pos = 0x10
	// Bit mask of PINEN0 field.
	PDEC_CTRLA_PINEN0_Msk = 0x10000
	// Bit PINEN0.
	PDEC_CTRLA_PINEN0 = 0x10000
	// Position of PINEN1 field.
	PDEC_CTRLA_PINEN1_Pos = 0x11
	// Bit mask of PINEN1 field.
	PDEC_CTRLA_PINEN1_Msk = 0x20000
	// Bit PINEN1.
	PDEC_CTRLA_PINEN1 = 0x20000
	// Position of PINEN2 field.
	PDEC_CTRLA_PINEN2_Pos = 0x12
	// Bit mask of PINEN2 field.
	PDEC_CTRLA_PINEN2_Msk = 0x40000
	// Bit PINEN2.
	PDEC_CTRLA_PINEN2 = 0x40000
	// Position of PINVEN0 field.
	PDEC_CTRLA_PINVEN0_Pos = 0x14
	// Bit mask of PINVEN0 field.
	PDEC_CTRLA_PINVEN0_Msk = 0x100000
	// Bit PINVEN0.
	PDEC_CTRLA_PINVEN0 = 0x100000
	// Position of PINVEN1 field.
	PDEC_CTRLA_PINVEN1_Pos = 0x15
	// Bit mask of PINVEN1 field.
	PDEC_CTRLA_PINVEN1_Msk = 0x200000
	// Bit PINVEN1.
	PDEC_CTRLA_PINVEN1 = 0x200000
	// Position of PINVEN2 field.
	PDEC_CTRLA_PINVEN2_Pos = 0x16
	// Bit mask of PINVEN2 field.
	PDEC_CTRLA_PINVEN2_Msk = 0x400000
	// Bit PINVEN2.
	PDEC_CTRLA_PINVEN2 = 0x400000
	// Position of ANGULAR field.
	PDEC_CTRLA_ANGULAR_Pos = 0x18
	// Bit mask of ANGULAR field.
	PDEC_CTRLA_ANGULAR_Msk = 0x7000000
	// Position of MAXCMP field.
	PDEC_CTRLA_MAXCMP_Pos = 0x1c
	// Bit mask of MAXCMP field.
	PDEC_CTRLA_MAXCMP_Msk = 0xf0000000

	// CTRLBCLR: Control B Clear
	// Position of LUPD field.
	PDEC_CTRLBCLR_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	PDEC_CTRLBCLR_LUPD_Msk = 0x2
	// Bit LUPD.
	PDEC_CTRLBCLR_LUPD = 0x2
	// Position of CMD field.
	PDEC_CTRLBCLR_CMD_Pos = 0x5
	// Bit mask of CMD field.
	PDEC_CTRLBCLR_CMD_Msk = 0xe0
	// No action
	PDEC_CTRLBCLR_CMD_NONE = 0x0
	// Force a counter restart or retrigger
	PDEC_CTRLBCLR_CMD_RETRIGGER = 0x1
	// Force update of double buffered registers
	PDEC_CTRLBCLR_CMD_UPDATE = 0x2
	// Force a read synchronization of COUNT
	PDEC_CTRLBCLR_CMD_READSYNC = 0x3
	// Start QDEC/HALL
	PDEC_CTRLBCLR_CMD_START = 0x4
	// Stop QDEC/HALL
	PDEC_CTRLBCLR_CMD_STOP = 0x5

	// CTRLBSET: Control B Set
	// Position of LUPD field.
	PDEC_CTRLBSET_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	PDEC_CTRLBSET_LUPD_Msk = 0x2
	// Bit LUPD.
	PDEC_CTRLBSET_LUPD = 0x2
	// Position of CMD field.
	PDEC_CTRLBSET_CMD_Pos = 0x5
	// Bit mask of CMD field.
	PDEC_CTRLBSET_CMD_Msk = 0xe0
	// No action
	PDEC_CTRLBSET_CMD_NONE = 0x0
	// Force a counter restart or retrigger
	PDEC_CTRLBSET_CMD_RETRIGGER = 0x1
	// Force update of double buffered registers
	PDEC_CTRLBSET_CMD_UPDATE = 0x2
	// Force a read synchronization of COUNT
	PDEC_CTRLBSET_CMD_READSYNC = 0x3
	// Start QDEC/HALL
	PDEC_CTRLBSET_CMD_START = 0x4
	// Stop QDEC/HALL
	PDEC_CTRLBSET_CMD_STOP = 0x5

	// EVCTRL: Event Control
	// Position of EVACT field.
	PDEC_EVCTRL_EVACT_Pos = 0x0
	// Bit mask of EVACT field.
	PDEC_EVCTRL_EVACT_Msk = 0x3
	// Event action disabled
	PDEC_EVCTRL_EVACT_OFF = 0x0
	// Start, restart or retrigger on event
	PDEC_EVCTRL_EVACT_RETRIGGER = 0x1
	// Count on event
	PDEC_EVCTRL_EVACT_COUNT = 0x2
	// Position of EVINV field.
	PDEC_EVCTRL_EVINV_Pos = 0x2
	// Bit mask of EVINV field.
	PDEC_EVCTRL_EVINV_Msk = 0x1c
	// Position of EVEI field.
	PDEC_EVCTRL_EVEI_Pos = 0x5
	// Bit mask of EVEI field.
	PDEC_EVCTRL_EVEI_Msk = 0xe0
	// Position of OVFEO field.
	PDEC_EVCTRL_OVFEO_Pos = 0x8
	// Bit mask of OVFEO field.
	PDEC_EVCTRL_OVFEO_Msk = 0x100
	// Bit OVFEO.
	PDEC_EVCTRL_OVFEO = 0x100
	// Position of ERREO field.
	PDEC_EVCTRL_ERREO_Pos = 0x9
	// Bit mask of ERREO field.
	PDEC_EVCTRL_ERREO_Msk = 0x200
	// Bit ERREO.
	PDEC_EVCTRL_ERREO = 0x200
	// Position of DIREO field.
	PDEC_EVCTRL_DIREO_Pos = 0xa
	// Bit mask of DIREO field.
	PDEC_EVCTRL_DIREO_Msk = 0x400
	// Bit DIREO.
	PDEC_EVCTRL_DIREO = 0x400
	// Position of VLCEO field.
	PDEC_EVCTRL_VLCEO_Pos = 0xb
	// Bit mask of VLCEO field.
	PDEC_EVCTRL_VLCEO_Msk = 0x800
	// Bit VLCEO.
	PDEC_EVCTRL_VLCEO = 0x800
	// Position of MCEO0 field.
	PDEC_EVCTRL_MCEO0_Pos = 0xc
	// Bit mask of MCEO0 field.
	PDEC_EVCTRL_MCEO0_Msk = 0x1000
	// Bit MCEO0.
	PDEC_EVCTRL_MCEO0 = 0x1000
	// Position of MCEO1 field.
	PDEC_EVCTRL_MCEO1_Pos = 0xd
	// Bit mask of MCEO1 field.
	PDEC_EVCTRL_MCEO1_Msk = 0x2000
	// Bit MCEO1.
	PDEC_EVCTRL_MCEO1 = 0x2000

	// INTENCLR: Interrupt Enable Clear
	// Position of OVF field.
	PDEC_INTENCLR_OVF_Pos = 0x0
	// Bit mask of OVF field.
	PDEC_INTENCLR_OVF_Msk = 0x1
	// Bit OVF.
	PDEC_INTENCLR_OVF = 0x1
	// Position of ERR field.
	PDEC_INTENCLR_ERR_Pos = 0x1
	// Bit mask of ERR field.
	PDEC_INTENCLR_ERR_Msk = 0x2
	// Bit ERR.
	PDEC_INTENCLR_ERR = 0x2
	// Position of DIR field.
	PDEC_INTENCLR_DIR_Pos = 0x2
	// Bit mask of DIR field.
	PDEC_INTENCLR_DIR_Msk = 0x4
	// Bit DIR.
	PDEC_INTENCLR_DIR = 0x4
	// Position of VLC field.
	PDEC_INTENCLR_VLC_Pos = 0x3
	// Bit mask of VLC field.
	PDEC_INTENCLR_VLC_Msk = 0x8
	// Bit VLC.
	PDEC_INTENCLR_VLC = 0x8
	// Position of MC0 field.
	PDEC_INTENCLR_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	PDEC_INTENCLR_MC0_Msk = 0x10
	// Bit MC0.
	PDEC_INTENCLR_MC0 = 0x10
	// Position of MC1 field.
	PDEC_INTENCLR_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	PDEC_INTENCLR_MC1_Msk = 0x20
	// Bit MC1.
	PDEC_INTENCLR_MC1 = 0x20

	// INTENSET: Interrupt Enable Set
	// Position of OVF field.
	PDEC_INTENSET_OVF_Pos = 0x0
	// Bit mask of OVF field.
	PDEC_INTENSET_OVF_Msk = 0x1
	// Bit OVF.
	PDEC_INTENSET_OVF = 0x1
	// Position of ERR field.
	PDEC_INTENSET_ERR_Pos = 0x1
	// Bit mask of ERR field.
	PDEC_INTENSET_ERR_Msk = 0x2
	// Bit ERR.
	PDEC_INTENSET_ERR = 0x2
	// Position of DIR field.
	PDEC_INTENSET_DIR_Pos = 0x2
	// Bit mask of DIR field.
	PDEC_INTENSET_DIR_Msk = 0x4
	// Bit DIR.
	PDEC_INTENSET_DIR = 0x4
	// Position of VLC field.
	PDEC_INTENSET_VLC_Pos = 0x3
	// Bit mask of VLC field.
	PDEC_INTENSET_VLC_Msk = 0x8
	// Bit VLC.
	PDEC_INTENSET_VLC = 0x8
	// Position of MC0 field.
	PDEC_INTENSET_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	PDEC_INTENSET_MC0_Msk = 0x10
	// Bit MC0.
	PDEC_INTENSET_MC0 = 0x10
	// Position of MC1 field.
	PDEC_INTENSET_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	PDEC_INTENSET_MC1_Msk = 0x20
	// Bit MC1.
	PDEC_INTENSET_MC1 = 0x20

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of OVF field.
	PDEC_INTFLAG_OVF_Pos = 0x0
	// Bit mask of OVF field.
	PDEC_INTFLAG_OVF_Msk = 0x1
	// Bit OVF.
	PDEC_INTFLAG_OVF = 0x1
	// Position of ERR field.
	PDEC_INTFLAG_ERR_Pos = 0x1
	// Bit mask of ERR field.
	PDEC_INTFLAG_ERR_Msk = 0x2
	// Bit ERR.
	PDEC_INTFLAG_ERR = 0x2
	// Position of DIR field.
	PDEC_INTFLAG_DIR_Pos = 0x2
	// Bit mask of DIR field.
	PDEC_INTFLAG_DIR_Msk = 0x4
	// Bit DIR.
	PDEC_INTFLAG_DIR = 0x4
	// Position of VLC field.
	PDEC_INTFLAG_VLC_Pos = 0x3
	// Bit mask of VLC field.
	PDEC_INTFLAG_VLC_Msk = 0x8
	// Bit VLC.
	PDEC_INTFLAG_VLC = 0x8
	// Position of MC0 field.
	PDEC_INTFLAG_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	PDEC_INTFLAG_MC0_Msk = 0x10
	// Bit MC0.
	PDEC_INTFLAG_MC0 = 0x10
	// Position of MC1 field.
	PDEC_INTFLAG_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	PDEC_INTFLAG_MC1_Msk = 0x20
	// Bit MC1.
	PDEC_INTFLAG_MC1 = 0x20

	// STATUS: Status
	// Position of QERR field.
	PDEC_STATUS_QERR_Pos = 0x0
	// Bit mask of QERR field.
	PDEC_STATUS_QERR_Msk = 0x1
	// Bit QERR.
	PDEC_STATUS_QERR = 0x1
	// Position of IDXERR field.
	PDEC_STATUS_IDXERR_Pos = 0x1
	// Bit mask of IDXERR field.
	PDEC_STATUS_IDXERR_Msk = 0x2
	// Bit IDXERR.
	PDEC_STATUS_IDXERR = 0x2
	// Position of MPERR field.
	PDEC_STATUS_MPERR_Pos = 0x2
	// Bit mask of MPERR field.
	PDEC_STATUS_MPERR_Msk = 0x4
	// Bit MPERR.
	PDEC_STATUS_MPERR = 0x4
	// Position of WINERR field.
	PDEC_STATUS_WINERR_Pos = 0x4
	// Bit mask of WINERR field.
	PDEC_STATUS_WINERR_Msk = 0x10
	// Bit WINERR.
	PDEC_STATUS_WINERR = 0x10
	// Position of HERR field.
	PDEC_STATUS_HERR_Pos = 0x5
	// Bit mask of HERR field.
	PDEC_STATUS_HERR_Msk = 0x20
	// Bit HERR.
	PDEC_STATUS_HERR = 0x20
	// Position of STOP field.
	PDEC_STATUS_STOP_Pos = 0x6
	// Bit mask of STOP field.
	PDEC_STATUS_STOP_Msk = 0x40
	// Bit STOP.
	PDEC_STATUS_STOP = 0x40
	// Position of DIR field.
	PDEC_STATUS_DIR_Pos = 0x7
	// Bit mask of DIR field.
	PDEC_STATUS_DIR_Msk = 0x80
	// Bit DIR.
	PDEC_STATUS_DIR = 0x80
	// Position of PRESCBUFV field.
	PDEC_STATUS_PRESCBUFV_Pos = 0x8
	// Bit mask of PRESCBUFV field.
	PDEC_STATUS_PRESCBUFV_Msk = 0x100
	// Bit PRESCBUFV.
	PDEC_STATUS_PRESCBUFV = 0x100
	// Position of FILTERBUFV field.
	PDEC_STATUS_FILTERBUFV_Pos = 0x9
	// Bit mask of FILTERBUFV field.
	PDEC_STATUS_FILTERBUFV_Msk = 0x200
	// Bit FILTERBUFV.
	PDEC_STATUS_FILTERBUFV = 0x200
	// Position of CCBUFV0 field.
	PDEC_STATUS_CCBUFV0_Pos = 0xc
	// Bit mask of CCBUFV0 field.
	PDEC_STATUS_CCBUFV0_Msk = 0x1000
	// Bit CCBUFV0.
	PDEC_STATUS_CCBUFV0 = 0x1000
	// Position of CCBUFV1 field.
	PDEC_STATUS_CCBUFV1_Pos = 0xd
	// Bit mask of CCBUFV1 field.
	PDEC_STATUS_CCBUFV1_Msk = 0x2000
	// Bit CCBUFV1.
	PDEC_STATUS_CCBUFV1 = 0x2000

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	PDEC_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	PDEC_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	PDEC_DBGCTRL_DBGRUN = 0x1

	// SYNCBUSY: Synchronization Status
	// Position of SWRST field.
	PDEC_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	PDEC_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	PDEC_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	PDEC_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	PDEC_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	PDEC_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	PDEC_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	PDEC_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	PDEC_SYNCBUSY_CTRLB = 0x4
	// Position of STATUS field.
	PDEC_SYNCBUSY_STATUS_Pos = 0x3
	// Bit mask of STATUS field.
	PDEC_SYNCBUSY_STATUS_Msk = 0x8
	// Bit STATUS.
	PDEC_SYNCBUSY_STATUS = 0x8
	// Position of PRESC field.
	PDEC_SYNCBUSY_PRESC_Pos = 0x4
	// Bit mask of PRESC field.
	PDEC_SYNCBUSY_PRESC_Msk = 0x10
	// Bit PRESC.
	PDEC_SYNCBUSY_PRESC = 0x10
	// Position of FILTER field.
	PDEC_SYNCBUSY_FILTER_Pos = 0x5
	// Bit mask of FILTER field.
	PDEC_SYNCBUSY_FILTER_Msk = 0x20
	// Bit FILTER.
	PDEC_SYNCBUSY_FILTER = 0x20
	// Position of COUNT field.
	PDEC_SYNCBUSY_COUNT_Pos = 0x6
	// Bit mask of COUNT field.
	PDEC_SYNCBUSY_COUNT_Msk = 0x40
	// Bit COUNT.
	PDEC_SYNCBUSY_COUNT = 0x40
	// Position of CC0 field.
	PDEC_SYNCBUSY_CC0_Pos = 0x7
	// Bit mask of CC0 field.
	PDEC_SYNCBUSY_CC0_Msk = 0x80
	// Bit CC0.
	PDEC_SYNCBUSY_CC0 = 0x80
	// Position of CC1 field.
	PDEC_SYNCBUSY_CC1_Pos = 0x8
	// Bit mask of CC1 field.
	PDEC_SYNCBUSY_CC1_Msk = 0x100
	// Bit CC1.
	PDEC_SYNCBUSY_CC1 = 0x100

	// PRESC: Prescaler Value
	// Position of PRESC field.
	PDEC_PRESC_PRESC_Pos = 0x0
	// Bit mask of PRESC field.
	PDEC_PRESC_PRESC_Msk = 0xf
	// No division
	PDEC_PRESC_PRESC_DIV1 = 0x0
	// Divide by 2
	PDEC_PRESC_PRESC_DIV2 = 0x1
	// Divide by 4
	PDEC_PRESC_PRESC_DIV4 = 0x2
	// Divide by 8
	PDEC_PRESC_PRESC_DIV8 = 0x3
	// Divide by 16
	PDEC_PRESC_PRESC_DIV16 = 0x4
	// Divide by 32
	PDEC_PRESC_PRESC_DIV32 = 0x5
	// Divide by 64
	PDEC_PRESC_PRESC_DIV64 = 0x6
	// Divide by 128
	PDEC_PRESC_PRESC_DIV128 = 0x7
	// Divide by 256
	PDEC_PRESC_PRESC_DIV256 = 0x8
	// Divide by 512
	PDEC_PRESC_PRESC_DIV512 = 0x9
	// Divide by 1024
	PDEC_PRESC_PRESC_DIV1024 = 0xa

	// FILTER: Filter Value
	// Position of FILTER field.
	PDEC_FILTER_FILTER_Pos = 0x0
	// Bit mask of FILTER field.
	PDEC_FILTER_FILTER_Msk = 0xff

	// PRESCBUF: Prescaler Buffer Value
	// Position of PRESCBUF field.
	PDEC_PRESCBUF_PRESCBUF_Pos = 0x0
	// Bit mask of PRESCBUF field.
	PDEC_PRESCBUF_PRESCBUF_Msk = 0xf
	// No division
	PDEC_PRESCBUF_PRESCBUF_DIV1 = 0x0
	// Divide by 2
	PDEC_PRESCBUF_PRESCBUF_DIV2 = 0x1
	// Divide by 4
	PDEC_PRESCBUF_PRESCBUF_DIV4 = 0x2
	// Divide by 8
	PDEC_PRESCBUF_PRESCBUF_DIV8 = 0x3
	// Divide by 16
	PDEC_PRESCBUF_PRESCBUF_DIV16 = 0x4
	// Divide by 32
	PDEC_PRESCBUF_PRESCBUF_DIV32 = 0x5
	// Divide by 64
	PDEC_PRESCBUF_PRESCBUF_DIV64 = 0x6
	// Divide by 128
	PDEC_PRESCBUF_PRESCBUF_DIV128 = 0x7
	// Divide by 256
	PDEC_PRESCBUF_PRESCBUF_DIV256 = 0x8
	// Divide by 512
	PDEC_PRESCBUF_PRESCBUF_DIV512 = 0x9
	// Divide by 1024
	PDEC_PRESCBUF_PRESCBUF_DIV1024 = 0xa

	// FILTERBUF: Filter Buffer Value
	// Position of FILTERBUF field.
	PDEC_FILTERBUF_FILTERBUF_Pos = 0x0
	// Bit mask of FILTERBUF field.
	PDEC_FILTERBUF_FILTERBUF_Msk = 0xff

	// COUNT: Counter Value
	// Position of COUNT field.
	PDEC_COUNT_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	PDEC_COUNT_COUNT_Msk = 0xffff

	// CC: Channel n Compare Value
	// Position of CC field.
	PDEC_CC_CC_Pos = 0x0
	// Bit mask of CC field.
	PDEC_CC_CC_Msk = 0xffff

	// CCBUF: Channel Compare Buffer Value
	// Position of CCBUF field.
	PDEC_CCBUF_CCBUF_Pos = 0x0
	// Bit mask of CCBUF field.
	PDEC_CCBUF_CCBUF_Msk = 0xffff
)

// Bitfields for PM: Power Manager
const (
	// CTRLA: Control A
	// Position of IORET field.
	PM_CTRLA_IORET_Pos = 0x2
	// Bit mask of IORET field.
	PM_CTRLA_IORET_Msk = 0x4
	// Bit IORET.
	PM_CTRLA_IORET = 0x4

	// SLEEPCFG: Sleep Configuration
	// Position of SLEEPMODE field.
	PM_SLEEPCFG_SLEEPMODE_Pos = 0x0
	// Bit mask of SLEEPMODE field.
	PM_SLEEPCFG_SLEEPMODE_Msk = 0x7
	// CPU, AHBx, and APBx clocks are OFF
	PM_SLEEPCFG_SLEEPMODE_IDLE = 0x2
	// All Clocks are OFF
	PM_SLEEPCFG_SLEEPMODE_STANDBY = 0x4
	// Backup domain is ON as well as some PDRAMs
	PM_SLEEPCFG_SLEEPMODE_HIBERNATE = 0x5
	// Only Backup domain is powered ON
	PM_SLEEPCFG_SLEEPMODE_BACKUP = 0x6
	// All power domains are powered OFF
	PM_SLEEPCFG_SLEEPMODE_OFF = 0x7

	// INTENCLR: Interrupt Enable Clear
	// Position of SLEEPRDY field.
	PM_INTENCLR_SLEEPRDY_Pos = 0x0
	// Bit mask of SLEEPRDY field.
	PM_INTENCLR_SLEEPRDY_Msk = 0x1
	// Bit SLEEPRDY.
	PM_INTENCLR_SLEEPRDY = 0x1

	// INTENSET: Interrupt Enable Set
	// Position of SLEEPRDY field.
	PM_INTENSET_SLEEPRDY_Pos = 0x0
	// Bit mask of SLEEPRDY field.
	PM_INTENSET_SLEEPRDY_Msk = 0x1
	// Bit SLEEPRDY.
	PM_INTENSET_SLEEPRDY = 0x1

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of SLEEPRDY field.
	PM_INTFLAG_SLEEPRDY_Pos = 0x0
	// Bit mask of SLEEPRDY field.
	PM_INTFLAG_SLEEPRDY_Msk = 0x1
	// Bit SLEEPRDY.
	PM_INTFLAG_SLEEPRDY = 0x1

	// STDBYCFG: Standby Configuration
	// Position of RAMCFG field.
	PM_STDBYCFG_RAMCFG_Pos = 0x0
	// Bit mask of RAMCFG field.
	PM_STDBYCFG_RAMCFG_Msk = 0x3
	// All the system RAM is retained
	PM_STDBYCFG_RAMCFG_RET = 0x0
	// Only the first 32Kbytes of the system RAM is retained
	PM_STDBYCFG_RAMCFG_PARTIAL = 0x1
	// All the system RAM is turned OFF
	PM_STDBYCFG_RAMCFG_OFF = 0x2
	// Position of FASTWKUP field.
	PM_STDBYCFG_FASTWKUP_Pos = 0x4
	// Bit mask of FASTWKUP field.
	PM_STDBYCFG_FASTWKUP_Msk = 0x30
	// Fast Wakeup is disabled
	PM_STDBYCFG_FASTWKUP_NO = 0x0
	// Fast Wakeup is enabled on NVM
	PM_STDBYCFG_FASTWKUP_NVM = 0x1
	// Fast Wakeup is enabled on the main voltage regulator (MAINVREG)
	PM_STDBYCFG_FASTWKUP_MAINVREG = 0x2
	// Fast Wakeup is enabled on both NVM and MAINVREG
	PM_STDBYCFG_FASTWKUP_BOTH = 0x3

	// HIBCFG: Hibernate Configuration
	// Position of RAMCFG field.
	PM_HIBCFG_RAMCFG_Pos = 0x0
	// Bit mask of RAMCFG field.
	PM_HIBCFG_RAMCFG_Msk = 0x3
	// All the system RAM is retained
	PM_HIBCFG_RAMCFG_RET = 0x0
	// Only the first 32Kbytes of the system RAM is retained
	PM_HIBCFG_RAMCFG_PARTIAL = 0x1
	// All the system RAM is turned OFF
	PM_HIBCFG_RAMCFG_OFF = 0x2
	// Position of BRAMCFG field.
	PM_HIBCFG_BRAMCFG_Pos = 0x2
	// Bit mask of BRAMCFG field.
	PM_HIBCFG_BRAMCFG_Msk = 0xc
	// All the backup RAM is retained
	PM_HIBCFG_BRAMCFG_RET = 0x0
	// Only the first 4Kbytes of the backup RAM is retained
	PM_HIBCFG_BRAMCFG_PARTIAL = 0x1
	// All the backup RAM is turned OFF
	PM_HIBCFG_BRAMCFG_OFF = 0x2

	// BKUPCFG: Backup Configuration
	// Position of BRAMCFG field.
	PM_BKUPCFG_BRAMCFG_Pos = 0x0
	// Bit mask of BRAMCFG field.
	PM_BKUPCFG_BRAMCFG_Msk = 0x3
	// All the backup RAM is retained
	PM_BKUPCFG_BRAMCFG_RET = 0x0
	// Only the first 4Kbytes of the backup RAM is retained
	PM_BKUPCFG_BRAMCFG_PARTIAL = 0x1
	// All the backup RAM is turned OFF
	PM_BKUPCFG_BRAMCFG_OFF = 0x2

	// PWSAKDLY: Power Switch Acknowledge Delay
	// Position of DLYVAL field.
	PM_PWSAKDLY_DLYVAL_Pos = 0x0
	// Bit mask of DLYVAL field.
	PM_PWSAKDLY_DLYVAL_Msk = 0x7f
	// Position of IGNACK field.
	PM_PWSAKDLY_IGNACK_Pos = 0x7
	// Bit mask of IGNACK field.
	PM_PWSAKDLY_IGNACK_Msk = 0x80
	// Bit IGNACK.
	PM_PWSAKDLY_IGNACK = 0x80
)

// Bitfields for PORT: Port Module
const (
	// GROUP.DIR: Data Direction
	// Position of DIR field.
	PORT_GROUP_DIR_DIR_Pos = 0x0
	// Bit mask of DIR field.
	PORT_GROUP_DIR_DIR_Msk = 0xffffffff

	// GROUP.DIRCLR: Data Direction Clear
	// Position of DIRCLR field.
	PORT_GROUP_DIRCLR_DIRCLR_Pos = 0x0
	// Bit mask of DIRCLR field.
	PORT_GROUP_DIRCLR_DIRCLR_Msk = 0xffffffff

	// GROUP.DIRSET: Data Direction Set
	// Position of DIRSET field.
	PORT_GROUP_DIRSET_DIRSET_Pos = 0x0
	// Bit mask of DIRSET field.
	PORT_GROUP_DIRSET_DIRSET_Msk = 0xffffffff

	// GROUP.DIRTGL: Data Direction Toggle
	// Position of DIRTGL field.
	PORT_GROUP_DIRTGL_DIRTGL_Pos = 0x0
	// Bit mask of DIRTGL field.
	PORT_GROUP_DIRTGL_DIRTGL_Msk = 0xffffffff

	// GROUP.OUT: Data Output Value
	// Position of OUT field.
	PORT_GROUP_OUT_OUT_Pos = 0x0
	// Bit mask of OUT field.
	PORT_GROUP_OUT_OUT_Msk = 0xffffffff

	// GROUP.OUTCLR: Data Output Value Clear
	// Position of OUTCLR field.
	PORT_GROUP_OUTCLR_OUTCLR_Pos = 0x0
	// Bit mask of OUTCLR field.
	PORT_GROUP_OUTCLR_OUTCLR_Msk = 0xffffffff

	// GROUP.OUTSET: Data Output Value Set
	// Position of OUTSET field.
	PORT_GROUP_OUTSET_OUTSET_Pos = 0x0
	// Bit mask of OUTSET field.
	PORT_GROUP_OUTSET_OUTSET_Msk = 0xffffffff

	// GROUP.OUTTGL: Data Output Value Toggle
	// Position of OUTTGL field.
	PORT_GROUP_OUTTGL_OUTTGL_Pos = 0x0
	// Bit mask of OUTTGL field.
	PORT_GROUP_OUTTGL_OUTTGL_Msk = 0xffffffff

	// GROUP.IN: Data Input Value
	// Position of IN field.
	PORT_GROUP_IN_IN_Pos = 0x0
	// Bit mask of IN field.
	PORT_GROUP_IN_IN_Msk = 0xffffffff

	// GROUP.CTRL: Control
	// Position of SAMPLING field.
	PORT_GROUP_CTRL_SAMPLING_Pos = 0x0
	// Bit mask of SAMPLING field.
	PORT_GROUP_CTRL_SAMPLING_Msk = 0xffffffff

	// GROUP.WRCONFIG: Write Configuration
	// Position of PINMASK field.
	PORT_GROUP_WRCONFIG_PINMASK_Pos = 0x0
	// Bit mask of PINMASK field.
	PORT_GROUP_WRCONFIG_PINMASK_Msk = 0xffff
	// Position of PMUXEN field.
	PORT_GROUP_WRCONFIG_PMUXEN_Pos = 0x10
	// Bit mask of PMUXEN field.
	PORT_GROUP_WRCONFIG_PMUXEN_Msk = 0x10000
	// Bit PMUXEN.
	PORT_GROUP_WRCONFIG_PMUXEN = 0x10000
	// Position of INEN field.
	PORT_GROUP_WRCONFIG_INEN_Pos = 0x11
	// Bit mask of INEN field.
	PORT_GROUP_WRCONFIG_INEN_Msk = 0x20000
	// Bit INEN.
	PORT_GROUP_WRCONFIG_INEN = 0x20000
	// Position of PULLEN field.
	PORT_GROUP_WRCONFIG_PULLEN_Pos = 0x12
	// Bit mask of PULLEN field.
	PORT_GROUP_WRCONFIG_PULLEN_Msk = 0x40000
	// Bit PULLEN.
	PORT_GROUP_WRCONFIG_PULLEN = 0x40000
	// Position of DRVSTR field.
	PORT_GROUP_WRCONFIG_DRVSTR_Pos = 0x16
	// Bit mask of DRVSTR field.
	PORT_GROUP_WRCONFIG_DRVSTR_Msk = 0x400000
	// Bit DRVSTR.
	PORT_GROUP_WRCONFIG_DRVSTR = 0x400000
	// Position of PMUX field.
	PORT_GROUP_WRCONFIG_PMUX_Pos = 0x18
	// Bit mask of PMUX field.
	PORT_GROUP_WRCONFIG_PMUX_Msk = 0xf000000
	// Position of WRPMUX field.
	PORT_GROUP_WRCONFIG_WRPMUX_Pos = 0x1c
	// Bit mask of WRPMUX field.
	PORT_GROUP_WRCONFIG_WRPMUX_Msk = 0x10000000
	// Bit WRPMUX.
	PORT_GROUP_WRCONFIG_WRPMUX = 0x10000000
	// Position of WRPINCFG field.
	PORT_GROUP_WRCONFIG_WRPINCFG_Pos = 0x1e
	// Bit mask of WRPINCFG field.
	PORT_GROUP_WRCONFIG_WRPINCFG_Msk = 0x40000000
	// Bit WRPINCFG.
	PORT_GROUP_WRCONFIG_WRPINCFG = 0x40000000
	// Position of HWSEL field.
	PORT_GROUP_WRCONFIG_HWSEL_Pos = 0x1f
	// Bit mask of HWSEL field.
	PORT_GROUP_WRCONFIG_HWSEL_Msk = 0x80000000
	// Bit HWSEL.
	PORT_GROUP_WRCONFIG_HWSEL = 0x80000000

	// GROUP.EVCTRL: Event Input Control
	// Position of PID0 field.
	PORT_GROUP_EVCTRL_PID0_Pos = 0x0
	// Bit mask of PID0 field.
	PORT_GROUP_EVCTRL_PID0_Msk = 0x1f
	// Position of EVACT0 field.
	PORT_GROUP_EVCTRL_EVACT0_Pos = 0x5
	// Bit mask of EVACT0 field.
	PORT_GROUP_EVCTRL_EVACT0_Msk = 0x60
	// Event output to pin
	PORT_GROUP_EVCTRL_EVACT0_OUT = 0x0
	// Set output register of pin on event
	PORT_GROUP_EVCTRL_EVACT0_SET = 0x1
	// Clear output register of pin on event
	PORT_GROUP_EVCTRL_EVACT0_CLR = 0x2
	// Toggle output register of pin on event
	PORT_GROUP_EVCTRL_EVACT0_TGL = 0x3
	// Position of PORTEI0 field.
	PORT_GROUP_EVCTRL_PORTEI0_Pos = 0x7
	// Bit mask of PORTEI0 field.
	PORT_GROUP_EVCTRL_PORTEI0_Msk = 0x80
	// Bit PORTEI0.
	PORT_GROUP_EVCTRL_PORTEI0 = 0x80
	// Position of PID1 field.
	PORT_GROUP_EVCTRL_PID1_Pos = 0x8
	// Bit mask of PID1 field.
	PORT_GROUP_EVCTRL_PID1_Msk = 0x1f00
	// Position of EVACT1 field.
	PORT_GROUP_EVCTRL_EVACT1_Pos = 0xd
	// Bit mask of EVACT1 field.
	PORT_GROUP_EVCTRL_EVACT1_Msk = 0x6000
	// Position of PORTEI1 field.
	PORT_GROUP_EVCTRL_PORTEI1_Pos = 0xf
	// Bit mask of PORTEI1 field.
	PORT_GROUP_EVCTRL_PORTEI1_Msk = 0x8000
	// Bit PORTEI1.
	PORT_GROUP_EVCTRL_PORTEI1 = 0x8000
	// Position of PID2 field.
	PORT_GROUP_EVCTRL_PID2_Pos = 0x10
	// Bit mask of PID2 field.
	PORT_GROUP_EVCTRL_PID2_Msk = 0x1f0000
	// Position of EVACT2 field.
	PORT_GROUP_EVCTRL_EVACT2_Pos = 0x15
	// Bit mask of EVACT2 field.
	PORT_GROUP_EVCTRL_EVACT2_Msk = 0x600000
	// Position of PORTEI2 field.
	PORT_GROUP_EVCTRL_PORTEI2_Pos = 0x17
	// Bit mask of PORTEI2 field.
	PORT_GROUP_EVCTRL_PORTEI2_Msk = 0x800000
	// Bit PORTEI2.
	PORT_GROUP_EVCTRL_PORTEI2 = 0x800000
	// Position of PID3 field.
	PORT_GROUP_EVCTRL_PID3_Pos = 0x18
	// Bit mask of PID3 field.
	PORT_GROUP_EVCTRL_PID3_Msk = 0x1f000000
	// Position of EVACT3 field.
	PORT_GROUP_EVCTRL_EVACT3_Pos = 0x1d
	// Bit mask of EVACT3 field.
	PORT_GROUP_EVCTRL_EVACT3_Msk = 0x60000000
	// Position of PORTEI3 field.
	PORT_GROUP_EVCTRL_PORTEI3_Pos = 0x1f
	// Bit mask of PORTEI3 field.
	PORT_GROUP_EVCTRL_PORTEI3_Msk = 0x80000000
	// Bit PORTEI3.
	PORT_GROUP_EVCTRL_PORTEI3 = 0x80000000

	// GROUP.PMUX: Peripheral Multiplexing
	// Position of PMUXE field.
	PORT_GROUP_PMUX_PMUXE_Pos = 0x0
	// Bit mask of PMUXE field.
	PORT_GROUP_PMUX_PMUXE_Msk = 0xf
	// Position of PMUXO field.
	PORT_GROUP_PMUX_PMUXO_Pos = 0x4
	// Bit mask of PMUXO field.
	PORT_GROUP_PMUX_PMUXO_Msk = 0xf0

	// GROUP.PINCFG: Pin Configuration
	// Position of PMUXEN field.
	PORT_GROUP_PINCFG_PMUXEN_Pos = 0x0
	// Bit mask of PMUXEN field.
	PORT_GROUP_PINCFG_PMUXEN_Msk = 0x1
	// Bit PMUXEN.
	PORT_GROUP_PINCFG_PMUXEN = 0x1
	// Position of INEN field.
	PORT_GROUP_PINCFG_INEN_Pos = 0x1
	// Bit mask of INEN field.
	PORT_GROUP_PINCFG_INEN_Msk = 0x2
	// Bit INEN.
	PORT_GROUP_PINCFG_INEN = 0x2
	// Position of PULLEN field.
	PORT_GROUP_PINCFG_PULLEN_Pos = 0x2
	// Bit mask of PULLEN field.
	PORT_GROUP_PINCFG_PULLEN_Msk = 0x4
	// Bit PULLEN.
	PORT_GROUP_PINCFG_PULLEN = 0x4
	// Position of DRVSTR field.
	PORT_GROUP_PINCFG_DRVSTR_Pos = 0x6
	// Bit mask of DRVSTR field.
	PORT_GROUP_PINCFG_DRVSTR_Msk = 0x40
	// Bit DRVSTR.
	PORT_GROUP_PINCFG_DRVSTR = 0x40
)

// Bitfields for QSPI: Quad SPI interface
const (
	// CTRLA: Control A
	// Position of SWRST field.
	QSPI_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	QSPI_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	QSPI_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	QSPI_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	QSPI_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	QSPI_CTRLA_ENABLE = 0x2
	// Position of LASTXFER field.
	QSPI_CTRLA_LASTXFER_Pos = 0x18
	// Bit mask of LASTXFER field.
	QSPI_CTRLA_LASTXFER_Msk = 0x1000000
	// Bit LASTXFER.
	QSPI_CTRLA_LASTXFER = 0x1000000

	// CTRLB: Control B
	// Position of MODE field.
	QSPI_CTRLB_MODE_Pos = 0x0
	// Bit mask of MODE field.
	QSPI_CTRLB_MODE_Msk = 0x1
	// Bit MODE.
	QSPI_CTRLB_MODE = 0x1
	// SPI operating mode
	QSPI_CTRLB_MODE_SPI = 0x0
	// Serial Memory operating mode
	QSPI_CTRLB_MODE_MEMORY = 0x1
	// Position of LOOPEN field.
	QSPI_CTRLB_LOOPEN_Pos = 0x1
	// Bit mask of LOOPEN field.
	QSPI_CTRLB_LOOPEN_Msk = 0x2
	// Bit LOOPEN.
	QSPI_CTRLB_LOOPEN = 0x2
	// Position of WDRBT field.
	QSPI_CTRLB_WDRBT_Pos = 0x2
	// Bit mask of WDRBT field.
	QSPI_CTRLB_WDRBT_Msk = 0x4
	// Bit WDRBT.
	QSPI_CTRLB_WDRBT = 0x4
	// Position of SMEMREG field.
	QSPI_CTRLB_SMEMREG_Pos = 0x3
	// Bit mask of SMEMREG field.
	QSPI_CTRLB_SMEMREG_Msk = 0x8
	// Bit SMEMREG.
	QSPI_CTRLB_SMEMREG = 0x8
	// Position of CSMODE field.
	QSPI_CTRLB_CSMODE_Pos = 0x4
	// Bit mask of CSMODE field.
	QSPI_CTRLB_CSMODE_Msk = 0x30
	// The chip select is deasserted if TD has not been reloaded before the end of the current transfer.
	QSPI_CTRLB_CSMODE_NORELOAD = 0x0
	// The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred.
	QSPI_CTRLB_CSMODE_LASTXFER = 0x1
	// The chip select is deasserted systematically after each transfer.
	QSPI_CTRLB_CSMODE_SYSTEMATICALLY = 0x2
	// Position of DATALEN field.
	QSPI_CTRLB_DATALEN_Pos = 0x8
	// Bit mask of DATALEN field.
	QSPI_CTRLB_DATALEN_Msk = 0xf00
	// 8-bits transfer
	QSPI_CTRLB_DATALEN_8BITS = 0x0
	// 9 bits transfer
	QSPI_CTRLB_DATALEN_9BITS = 0x1
	// 10-bits transfer
	QSPI_CTRLB_DATALEN_10BITS = 0x2
	// 11-bits transfer
	QSPI_CTRLB_DATALEN_11BITS = 0x3
	// 12-bits transfer
	QSPI_CTRLB_DATALEN_12BITS = 0x4
	// 13-bits transfer
	QSPI_CTRLB_DATALEN_13BITS = 0x5
	// 14-bits transfer
	QSPI_CTRLB_DATALEN_14BITS = 0x6
	// 15-bits transfer
	QSPI_CTRLB_DATALEN_15BITS = 0x7
	// 16-bits transfer
	QSPI_CTRLB_DATALEN_16BITS = 0x8
	// Position of DLYBCT field.
	QSPI_CTRLB_DLYBCT_Pos = 0x10
	// Bit mask of DLYBCT field.
	QSPI_CTRLB_DLYBCT_Msk = 0xff0000
	// Position of DLYCS field.
	QSPI_CTRLB_DLYCS_Pos = 0x18
	// Bit mask of DLYCS field.
	QSPI_CTRLB_DLYCS_Msk = 0xff000000

	// BAUD: Baud Rate
	// Position of CPOL field.
	QSPI_BAUD_CPOL_Pos = 0x0
	// Bit mask of CPOL field.
	QSPI_BAUD_CPOL_Msk = 0x1
	// Bit CPOL.
	QSPI_BAUD_CPOL = 0x1
	// Position of CPHA field.
	QSPI_BAUD_CPHA_Pos = 0x1
	// Bit mask of CPHA field.
	QSPI_BAUD_CPHA_Msk = 0x2
	// Bit CPHA.
	QSPI_BAUD_CPHA = 0x2
	// Position of BAUD field.
	QSPI_BAUD_BAUD_Pos = 0x8
	// Bit mask of BAUD field.
	QSPI_BAUD_BAUD_Msk = 0xff00
	// Position of DLYBS field.
	QSPI_BAUD_DLYBS_Pos = 0x10
	// Bit mask of DLYBS field.
	QSPI_BAUD_DLYBS_Msk = 0xff0000

	// RXDATA: Receive Data
	// Position of DATA field.
	QSPI_RXDATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	QSPI_RXDATA_DATA_Msk = 0xffff

	// TXDATA: Transmit Data
	// Position of DATA field.
	QSPI_TXDATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	QSPI_TXDATA_DATA_Msk = 0xffff

	// INTENCLR: Interrupt Enable Clear
	// Position of RXC field.
	QSPI_INTENCLR_RXC_Pos = 0x0
	// Bit mask of RXC field.
	QSPI_INTENCLR_RXC_Msk = 0x1
	// Bit RXC.
	QSPI_INTENCLR_RXC = 0x1
	// Position of DRE field.
	QSPI_INTENCLR_DRE_Pos = 0x1
	// Bit mask of DRE field.
	QSPI_INTENCLR_DRE_Msk = 0x2
	// Bit DRE.
	QSPI_INTENCLR_DRE = 0x2
	// Position of TXC field.
	QSPI_INTENCLR_TXC_Pos = 0x2
	// Bit mask of TXC field.
	QSPI_INTENCLR_TXC_Msk = 0x4
	// Bit TXC.
	QSPI_INTENCLR_TXC = 0x4
	// Position of ERROR field.
	QSPI_INTENCLR_ERROR_Pos = 0x3
	// Bit mask of ERROR field.
	QSPI_INTENCLR_ERROR_Msk = 0x8
	// Bit ERROR.
	QSPI_INTENCLR_ERROR = 0x8
	// Position of CSRISE field.
	QSPI_INTENCLR_CSRISE_Pos = 0x8
	// Bit mask of CSRISE field.
	QSPI_INTENCLR_CSRISE_Msk = 0x100
	// Bit CSRISE.
	QSPI_INTENCLR_CSRISE = 0x100
	// Position of INSTREND field.
	QSPI_INTENCLR_INSTREND_Pos = 0xa
	// Bit mask of INSTREND field.
	QSPI_INTENCLR_INSTREND_Msk = 0x400
	// Bit INSTREND.
	QSPI_INTENCLR_INSTREND = 0x400

	// INTENSET: Interrupt Enable Set
	// Position of RXC field.
	QSPI_INTENSET_RXC_Pos = 0x0
	// Bit mask of RXC field.
	QSPI_INTENSET_RXC_Msk = 0x1
	// Bit RXC.
	QSPI_INTENSET_RXC = 0x1
	// Position of DRE field.
	QSPI_INTENSET_DRE_Pos = 0x1
	// Bit mask of DRE field.
	QSPI_INTENSET_DRE_Msk = 0x2
	// Bit DRE.
	QSPI_INTENSET_DRE = 0x2
	// Position of TXC field.
	QSPI_INTENSET_TXC_Pos = 0x2
	// Bit mask of TXC field.
	QSPI_INTENSET_TXC_Msk = 0x4
	// Bit TXC.
	QSPI_INTENSET_TXC = 0x4
	// Position of ERROR field.
	QSPI_INTENSET_ERROR_Pos = 0x3
	// Bit mask of ERROR field.
	QSPI_INTENSET_ERROR_Msk = 0x8
	// Bit ERROR.
	QSPI_INTENSET_ERROR = 0x8
	// Position of CSRISE field.
	QSPI_INTENSET_CSRISE_Pos = 0x8
	// Bit mask of CSRISE field.
	QSPI_INTENSET_CSRISE_Msk = 0x100
	// Bit CSRISE.
	QSPI_INTENSET_CSRISE = 0x100
	// Position of INSTREND field.
	QSPI_INTENSET_INSTREND_Pos = 0xa
	// Bit mask of INSTREND field.
	QSPI_INTENSET_INSTREND_Msk = 0x400
	// Bit INSTREND.
	QSPI_INTENSET_INSTREND = 0x400

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of RXC field.
	QSPI_INTFLAG_RXC_Pos = 0x0
	// Bit mask of RXC field.
	QSPI_INTFLAG_RXC_Msk = 0x1
	// Bit RXC.
	QSPI_INTFLAG_RXC = 0x1
	// Position of DRE field.
	QSPI_INTFLAG_DRE_Pos = 0x1
	// Bit mask of DRE field.
	QSPI_INTFLAG_DRE_Msk = 0x2
	// Bit DRE.
	QSPI_INTFLAG_DRE = 0x2
	// Position of TXC field.
	QSPI_INTFLAG_TXC_Pos = 0x2
	// Bit mask of TXC field.
	QSPI_INTFLAG_TXC_Msk = 0x4
	// Bit TXC.
	QSPI_INTFLAG_TXC = 0x4
	// Position of ERROR field.
	QSPI_INTFLAG_ERROR_Pos = 0x3
	// Bit mask of ERROR field.
	QSPI_INTFLAG_ERROR_Msk = 0x8
	// Bit ERROR.
	QSPI_INTFLAG_ERROR = 0x8
	// Position of CSRISE field.
	QSPI_INTFLAG_CSRISE_Pos = 0x8
	// Bit mask of CSRISE field.
	QSPI_INTFLAG_CSRISE_Msk = 0x100
	// Bit CSRISE.
	QSPI_INTFLAG_CSRISE = 0x100
	// Position of INSTREND field.
	QSPI_INTFLAG_INSTREND_Pos = 0xa
	// Bit mask of INSTREND field.
	QSPI_INTFLAG_INSTREND_Msk = 0x400
	// Bit INSTREND.
	QSPI_INTFLAG_INSTREND = 0x400

	// STATUS: Status Register
	// Position of ENABLE field.
	QSPI_STATUS_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	QSPI_STATUS_ENABLE_Msk = 0x2
	// Bit ENABLE.
	QSPI_STATUS_ENABLE = 0x2
	// Position of CSSTATUS field.
	QSPI_STATUS_CSSTATUS_Pos = 0x9
	// Bit mask of CSSTATUS field.
	QSPI_STATUS_CSSTATUS_Msk = 0x200
	// Bit CSSTATUS.
	QSPI_STATUS_CSSTATUS = 0x200

	// INSTRADDR: Instruction Address
	// Position of ADDR field.
	QSPI_INSTRADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	QSPI_INSTRADDR_ADDR_Msk = 0xffffffff

	// INSTRCTRL: Instruction Code
	// Position of INSTR field.
	QSPI_INSTRCTRL_INSTR_Pos = 0x0
	// Bit mask of INSTR field.
	QSPI_INSTRCTRL_INSTR_Msk = 0xff
	// Position of OPTCODE field.
	QSPI_INSTRCTRL_OPTCODE_Pos = 0x10
	// Bit mask of OPTCODE field.
	QSPI_INSTRCTRL_OPTCODE_Msk = 0xff0000

	// INSTRFRAME: Instruction Frame
	// Position of WIDTH field.
	QSPI_INSTRFRAME_WIDTH_Pos = 0x0
	// Bit mask of WIDTH field.
	QSPI_INSTRFRAME_WIDTH_Msk = 0x7
	// Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
	QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI = 0x0
	// Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
	QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT = 0x1
	// Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
	QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT = 0x2
	// Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
	QSPI_INSTRFRAME_WIDTH_DUAL_IO = 0x3
	// Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
	QSPI_INSTRFRAME_WIDTH_QUAD_IO = 0x4
	// Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
	QSPI_INSTRFRAME_WIDTH_DUAL_CMD = 0x5
	// Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI
	QSPI_INSTRFRAME_WIDTH_QUAD_CMD = 0x6
	// Position of INSTREN field.
	QSPI_INSTRFRAME_INSTREN_Pos = 0x4
	// Bit mask of INSTREN field.
	QSPI_INSTRFRAME_INSTREN_Msk = 0x10
	// Bit INSTREN.
	QSPI_INSTRFRAME_INSTREN = 0x10
	// Position of ADDREN field.
	QSPI_INSTRFRAME_ADDREN_Pos = 0x5
	// Bit mask of ADDREN field.
	QSPI_INSTRFRAME_ADDREN_Msk = 0x20
	// Bit ADDREN.
	QSPI_INSTRFRAME_ADDREN = 0x20
	// Position of OPTCODEEN field.
	QSPI_INSTRFRAME_OPTCODEEN_Pos = 0x6
	// Bit mask of OPTCODEEN field.
	QSPI_INSTRFRAME_OPTCODEEN_Msk = 0x40
	// Bit OPTCODEEN.
	QSPI_INSTRFRAME_OPTCODEEN = 0x40
	// Position of DATAEN field.
	QSPI_INSTRFRAME_DATAEN_Pos = 0x7
	// Bit mask of DATAEN field.
	QSPI_INSTRFRAME_DATAEN_Msk = 0x80
	// Bit DATAEN.
	QSPI_INSTRFRAME_DATAEN = 0x80
	// Position of OPTCODELEN field.
	QSPI_INSTRFRAME_OPTCODELEN_Pos = 0x8
	// Bit mask of OPTCODELEN field.
	QSPI_INSTRFRAME_OPTCODELEN_Msk = 0x300
	// 1-bit length option code
	QSPI_INSTRFRAME_OPTCODELEN_1BIT = 0x0
	// 2-bits length option code
	QSPI_INSTRFRAME_OPTCODELEN_2BITS = 0x1
	// 4-bits length option code
	QSPI_INSTRFRAME_OPTCODELEN_4BITS = 0x2
	// 8-bits length option code
	QSPI_INSTRFRAME_OPTCODELEN_8BITS = 0x3
	// Position of ADDRLEN field.
	QSPI_INSTRFRAME_ADDRLEN_Pos = 0xa
	// Bit mask of ADDRLEN field.
	QSPI_INSTRFRAME_ADDRLEN_Msk = 0x400
	// Bit ADDRLEN.
	QSPI_INSTRFRAME_ADDRLEN = 0x400
	// 24-bits address length
	QSPI_INSTRFRAME_ADDRLEN_24BITS = 0x0
	// 32-bits address length
	QSPI_INSTRFRAME_ADDRLEN_32BITS = 0x1
	// Position of TFRTYPE field.
	QSPI_INSTRFRAME_TFRTYPE_Pos = 0xc
	// Bit mask of TFRTYPE field.
	QSPI_INSTRFRAME_TFRTYPE_Msk = 0x3000
	// Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible.
	QSPI_INSTRFRAME_TFRTYPE_READ = 0x0
	// Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible.
	QSPI_INSTRFRAME_TFRTYPE_READMEMORY = 0x1
	// Write transfer into the serial memory.Scrambling is not performed.
	QSPI_INSTRFRAME_TFRTYPE_WRITE = 0x2
	// Write data transfer into the serial memory.If enabled, scrambling is performed.
	QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY = 0x3
	// Position of CRMODE field.
	QSPI_INSTRFRAME_CRMODE_Pos = 0xe
	// Bit mask of CRMODE field.
	QSPI_INSTRFRAME_CRMODE_Msk = 0x4000
	// Bit CRMODE.
	QSPI_INSTRFRAME_CRMODE = 0x4000
	// Position of DDREN field.
	QSPI_INSTRFRAME_DDREN_Pos = 0xf
	// Bit mask of DDREN field.
	QSPI_INSTRFRAME_DDREN_Msk = 0x8000
	// Bit DDREN.
	QSPI_INSTRFRAME_DDREN = 0x8000
	// Position of DUMMYLEN field.
	QSPI_INSTRFRAME_DUMMYLEN_Pos = 0x10
	// Bit mask of DUMMYLEN field.
	QSPI_INSTRFRAME_DUMMYLEN_Msk = 0x1f0000

	// SCRAMBCTRL: Scrambling Mode
	// Position of ENABLE field.
	QSPI_SCRAMBCTRL_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	QSPI_SCRAMBCTRL_ENABLE_Msk = 0x1
	// Bit ENABLE.
	QSPI_SCRAMBCTRL_ENABLE = 0x1
	// Position of RANDOMDIS field.
	QSPI_SCRAMBCTRL_RANDOMDIS_Pos = 0x1
	// Bit mask of RANDOMDIS field.
	QSPI_SCRAMBCTRL_RANDOMDIS_Msk = 0x2
	// Bit RANDOMDIS.
	QSPI_SCRAMBCTRL_RANDOMDIS = 0x2

	// SCRAMBKEY: Scrambling Key
	// Position of KEY field.
	QSPI_SCRAMBKEY_KEY_Pos = 0x0
	// Bit mask of KEY field.
	QSPI_SCRAMBKEY_KEY_Msk = 0xffffffff
)

// Bitfields for RAMECC: RAM ECC
const (
	// INTENCLR: Interrupt Enable Clear
	// Position of SINGLEE field.
	RAMECC_INTENCLR_SINGLEE_Pos = 0x0
	// Bit mask of SINGLEE field.
	RAMECC_INTENCLR_SINGLEE_Msk = 0x1
	// Bit SINGLEE.
	RAMECC_INTENCLR_SINGLEE = 0x1
	// Position of DUALE field.
	RAMECC_INTENCLR_DUALE_Pos = 0x1
	// Bit mask of DUALE field.
	RAMECC_INTENCLR_DUALE_Msk = 0x2
	// Bit DUALE.
	RAMECC_INTENCLR_DUALE = 0x2

	// INTENSET: Interrupt Enable Set
	// Position of SINGLEE field.
	RAMECC_INTENSET_SINGLEE_Pos = 0x0
	// Bit mask of SINGLEE field.
	RAMECC_INTENSET_SINGLEE_Msk = 0x1
	// Bit SINGLEE.
	RAMECC_INTENSET_SINGLEE = 0x1
	// Position of DUALE field.
	RAMECC_INTENSET_DUALE_Pos = 0x1
	// Bit mask of DUALE field.
	RAMECC_INTENSET_DUALE_Msk = 0x2
	// Bit DUALE.
	RAMECC_INTENSET_DUALE = 0x2

	// INTFLAG: Interrupt Flag
	// Position of SINGLEE field.
	RAMECC_INTFLAG_SINGLEE_Pos = 0x0
	// Bit mask of SINGLEE field.
	RAMECC_INTFLAG_SINGLEE_Msk = 0x1
	// Bit SINGLEE.
	RAMECC_INTFLAG_SINGLEE = 0x1
	// Position of DUALE field.
	RAMECC_INTFLAG_DUALE_Pos = 0x1
	// Bit mask of DUALE field.
	RAMECC_INTFLAG_DUALE_Msk = 0x2
	// Bit DUALE.
	RAMECC_INTFLAG_DUALE = 0x2

	// STATUS: Status
	// Position of ECCDIS field.
	RAMECC_STATUS_ECCDIS_Pos = 0x0
	// Bit mask of ECCDIS field.
	RAMECC_STATUS_ECCDIS_Msk = 0x1
	// Bit ECCDIS.
	RAMECC_STATUS_ECCDIS = 0x1

	// ERRADDR: Error Address
	// Position of ERRADDR field.
	RAMECC_ERRADDR_ERRADDR_Pos = 0x0
	// Bit mask of ERRADDR field.
	RAMECC_ERRADDR_ERRADDR_Msk = 0x1ffff

	// DBGCTRL: Debug Control
	// Position of ECCDIS field.
	RAMECC_DBGCTRL_ECCDIS_Pos = 0x0
	// Bit mask of ECCDIS field.
	RAMECC_DBGCTRL_ECCDIS_Msk = 0x1
	// Bit ECCDIS.
	RAMECC_DBGCTRL_ECCDIS = 0x1
	// Position of ECCELOG field.
	RAMECC_DBGCTRL_ECCELOG_Pos = 0x1
	// Bit mask of ECCELOG field.
	RAMECC_DBGCTRL_ECCELOG_Msk = 0x2
	// Bit ECCELOG.
	RAMECC_DBGCTRL_ECCELOG = 0x2
)

// Bitfields for RSTC: Reset Controller
const (
	// RCAUSE: Reset Cause
	// Position of POR field.
	RSTC_RCAUSE_POR_Pos = 0x0
	// Bit mask of POR field.
	RSTC_RCAUSE_POR_Msk = 0x1
	// Bit POR.
	RSTC_RCAUSE_POR = 0x1
	// Position of BODCORE field.
	RSTC_RCAUSE_BODCORE_Pos = 0x1
	// Bit mask of BODCORE field.
	RSTC_RCAUSE_BODCORE_Msk = 0x2
	// Bit BODCORE.
	RSTC_RCAUSE_BODCORE = 0x2
	// Position of BODVDD field.
	RSTC_RCAUSE_BODVDD_Pos = 0x2
	// Bit mask of BODVDD field.
	RSTC_RCAUSE_BODVDD_Msk = 0x4
	// Bit BODVDD.
	RSTC_RCAUSE_BODVDD = 0x4
	// Position of NVM field.
	RSTC_RCAUSE_NVM_Pos = 0x3
	// Bit mask of NVM field.
	RSTC_RCAUSE_NVM_Msk = 0x8
	// Bit NVM.
	RSTC_RCAUSE_NVM = 0x8
	// Position of EXT field.
	RSTC_RCAUSE_EXT_Pos = 0x4
	// Bit mask of EXT field.
	RSTC_RCAUSE_EXT_Msk = 0x10
	// Bit EXT.
	RSTC_RCAUSE_EXT = 0x10
	// Position of WDT field.
	RSTC_RCAUSE_WDT_Pos = 0x5
	// Bit mask of WDT field.
	RSTC_RCAUSE_WDT_Msk = 0x20
	// Bit WDT.
	RSTC_RCAUSE_WDT = 0x20
	// Position of SYST field.
	RSTC_RCAUSE_SYST_Pos = 0x6
	// Bit mask of SYST field.
	RSTC_RCAUSE_SYST_Msk = 0x40
	// Bit SYST.
	RSTC_RCAUSE_SYST = 0x40
	// Position of BACKUP field.
	RSTC_RCAUSE_BACKUP_Pos = 0x7
	// Bit mask of BACKUP field.
	RSTC_RCAUSE_BACKUP_Msk = 0x80
	// Bit BACKUP.
	RSTC_RCAUSE_BACKUP = 0x80

	// BKUPEXIT: Backup Exit Source
	// Position of RTC field.
	RSTC_BKUPEXIT_RTC_Pos = 0x1
	// Bit mask of RTC field.
	RSTC_BKUPEXIT_RTC_Msk = 0x2
	// Bit RTC.
	RSTC_BKUPEXIT_RTC = 0x2
	// Position of BBPS field.
	RSTC_BKUPEXIT_BBPS_Pos = 0x2
	// Bit mask of BBPS field.
	RSTC_BKUPEXIT_BBPS_Msk = 0x4
	// Bit BBPS.
	RSTC_BKUPEXIT_BBPS = 0x4
	// Position of HIB field.
	RSTC_BKUPEXIT_HIB_Pos = 0x7
	// Bit mask of HIB field.
	RSTC_BKUPEXIT_HIB_Msk = 0x80
	// Bit HIB.
	RSTC_BKUPEXIT_HIB = 0x80
)

// Bitfields for RTC: Real-Time Counter
const ()

// Bitfields for RTC_MODE0: Real-Time Counter - MODE0
const (
	// CTRLA: MODE0 Control A
	// Position of SWRST field.
	RTC_MODE0_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	RTC_MODE0_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	RTC_MODE0_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	RTC_MODE0_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	RTC_MODE0_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	RTC_MODE0_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	RTC_MODE0_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	RTC_MODE0_CTRLA_MODE_Msk = 0xc
	// Mode 0: 32-bit Counter
	RTC_MODE0_CTRLA_MODE_COUNT32 = 0x0
	// Mode 1: 16-bit Counter
	RTC_MODE0_CTRLA_MODE_COUNT16 = 0x1
	// Mode 2: Clock/Calendar
	RTC_MODE0_CTRLA_MODE_CLOCK = 0x2
	// Position of MATCHCLR field.
	RTC_MODE0_CTRLA_MATCHCLR_Pos = 0x7
	// Bit mask of MATCHCLR field.
	RTC_MODE0_CTRLA_MATCHCLR_Msk = 0x80
	// Bit MATCHCLR.
	RTC_MODE0_CTRLA_MATCHCLR = 0x80
	// Position of PRESCALER field.
	RTC_MODE0_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	RTC_MODE0_CTRLA_PRESCALER_Msk = 0xf00
	// CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE0_CTRLA_PRESCALER_OFF = 0x0
	// CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE0_CTRLA_PRESCALER_DIV1 = 0x1
	// CLK_RTC_CNT = GCLK_RTC/2
	RTC_MODE0_CTRLA_PRESCALER_DIV2 = 0x2
	// CLK_RTC_CNT = GCLK_RTC/4
	RTC_MODE0_CTRLA_PRESCALER_DIV4 = 0x3
	// CLK_RTC_CNT = GCLK_RTC/8
	RTC_MODE0_CTRLA_PRESCALER_DIV8 = 0x4
	// CLK_RTC_CNT = GCLK_RTC/16
	RTC_MODE0_CTRLA_PRESCALER_DIV16 = 0x5
	// CLK_RTC_CNT = GCLK_RTC/32
	RTC_MODE0_CTRLA_PRESCALER_DIV32 = 0x6
	// CLK_RTC_CNT = GCLK_RTC/64
	RTC_MODE0_CTRLA_PRESCALER_DIV64 = 0x7
	// CLK_RTC_CNT = GCLK_RTC/128
	RTC_MODE0_CTRLA_PRESCALER_DIV128 = 0x8
	// CLK_RTC_CNT = GCLK_RTC/256
	RTC_MODE0_CTRLA_PRESCALER_DIV256 = 0x9
	// CLK_RTC_CNT = GCLK_RTC/512
	RTC_MODE0_CTRLA_PRESCALER_DIV512 = 0xa
	// CLK_RTC_CNT = GCLK_RTC/1024
	RTC_MODE0_CTRLA_PRESCALER_DIV1024 = 0xb
	// Position of BKTRST field.
	RTC_MODE0_CTRLA_BKTRST_Pos = 0xd
	// Bit mask of BKTRST field.
	RTC_MODE0_CTRLA_BKTRST_Msk = 0x2000
	// Bit BKTRST.
	RTC_MODE0_CTRLA_BKTRST = 0x2000
	// Position of GPTRST field.
	RTC_MODE0_CTRLA_GPTRST_Pos = 0xe
	// Bit mask of GPTRST field.
	RTC_MODE0_CTRLA_GPTRST_Msk = 0x4000
	// Bit GPTRST.
	RTC_MODE0_CTRLA_GPTRST = 0x4000
	// Position of COUNTSYNC field.
	RTC_MODE0_CTRLA_COUNTSYNC_Pos = 0xf
	// Bit mask of COUNTSYNC field.
	RTC_MODE0_CTRLA_COUNTSYNC_Msk = 0x8000
	// Bit COUNTSYNC.
	RTC_MODE0_CTRLA_COUNTSYNC = 0x8000

	// CTRLB: MODE0 Control B
	// Position of GP0EN field.
	RTC_MODE0_CTRLB_GP0EN_Pos = 0x0
	// Bit mask of GP0EN field.
	RTC_MODE0_CTRLB_GP0EN_Msk = 0x1
	// Bit GP0EN.
	RTC_MODE0_CTRLB_GP0EN = 0x1
	// Position of GP2EN field.
	RTC_MODE0_CTRLB_GP2EN_Pos = 0x1
	// Bit mask of GP2EN field.
	RTC_MODE0_CTRLB_GP2EN_Msk = 0x2
	// Bit GP2EN.
	RTC_MODE0_CTRLB_GP2EN = 0x2
	// Position of DEBMAJ field.
	RTC_MODE0_CTRLB_DEBMAJ_Pos = 0x4
	// Bit mask of DEBMAJ field.
	RTC_MODE0_CTRLB_DEBMAJ_Msk = 0x10
	// Bit DEBMAJ.
	RTC_MODE0_CTRLB_DEBMAJ = 0x10
	// Position of DEBASYNC field.
	RTC_MODE0_CTRLB_DEBASYNC_Pos = 0x5
	// Bit mask of DEBASYNC field.
	RTC_MODE0_CTRLB_DEBASYNC_Msk = 0x20
	// Bit DEBASYNC.
	RTC_MODE0_CTRLB_DEBASYNC = 0x20
	// Position of RTCOUT field.
	RTC_MODE0_CTRLB_RTCOUT_Pos = 0x6
	// Bit mask of RTCOUT field.
	RTC_MODE0_CTRLB_RTCOUT_Msk = 0x40
	// Bit RTCOUT.
	RTC_MODE0_CTRLB_RTCOUT = 0x40
	// Position of DMAEN field.
	RTC_MODE0_CTRLB_DMAEN_Pos = 0x7
	// Bit mask of DMAEN field.
	RTC_MODE0_CTRLB_DMAEN_Msk = 0x80
	// Bit DMAEN.
	RTC_MODE0_CTRLB_DMAEN = 0x80
	// Position of DEBF field.
	RTC_MODE0_CTRLB_DEBF_Pos = 0x8
	// Bit mask of DEBF field.
	RTC_MODE0_CTRLB_DEBF_Msk = 0x700
	// CLK_RTC_DEB = CLK_RTC/2
	RTC_MODE0_CTRLB_DEBF_DIV2 = 0x0
	// CLK_RTC_DEB = CLK_RTC/4
	RTC_MODE0_CTRLB_DEBF_DIV4 = 0x1
	// CLK_RTC_DEB = CLK_RTC/8
	RTC_MODE0_CTRLB_DEBF_DIV8 = 0x2
	// CLK_RTC_DEB = CLK_RTC/16
	RTC_MODE0_CTRLB_DEBF_DIV16 = 0x3
	// CLK_RTC_DEB = CLK_RTC/32
	RTC_MODE0_CTRLB_DEBF_DIV32 = 0x4
	// CLK_RTC_DEB = CLK_RTC/64
	RTC_MODE0_CTRLB_DEBF_DIV64 = 0x5
	// CLK_RTC_DEB = CLK_RTC/128
	RTC_MODE0_CTRLB_DEBF_DIV128 = 0x6
	// CLK_RTC_DEB = CLK_RTC/256
	RTC_MODE0_CTRLB_DEBF_DIV256 = 0x7
	// Position of ACTF field.
	RTC_MODE0_CTRLB_ACTF_Pos = 0xc
	// Bit mask of ACTF field.
	RTC_MODE0_CTRLB_ACTF_Msk = 0x7000
	// CLK_RTC_OUT = CLK_RTC/2
	RTC_MODE0_CTRLB_ACTF_DIV2 = 0x0
	// CLK_RTC_OUT = CLK_RTC/4
	RTC_MODE0_CTRLB_ACTF_DIV4 = 0x1
	// CLK_RTC_OUT = CLK_RTC/8
	RTC_MODE0_CTRLB_ACTF_DIV8 = 0x2
	// CLK_RTC_OUT = CLK_RTC/16
	RTC_MODE0_CTRLB_ACTF_DIV16 = 0x3
	// CLK_RTC_OUT = CLK_RTC/32
	RTC_MODE0_CTRLB_ACTF_DIV32 = 0x4
	// CLK_RTC_OUT = CLK_RTC/64
	RTC_MODE0_CTRLB_ACTF_DIV64 = 0x5
	// CLK_RTC_OUT = CLK_RTC/128
	RTC_MODE0_CTRLB_ACTF_DIV128 = 0x6
	// CLK_RTC_OUT = CLK_RTC/256
	RTC_MODE0_CTRLB_ACTF_DIV256 = 0x7

	// EVCTRL: MODE0 Event Control
	// Position of PEREO0 field.
	RTC_MODE0_EVCTRL_PEREO0_Pos = 0x0
	// Bit mask of PEREO0 field.
	RTC_MODE0_EVCTRL_PEREO0_Msk = 0x1
	// Bit PEREO0.
	RTC_MODE0_EVCTRL_PEREO0 = 0x1
	// Position of PEREO1 field.
	RTC_MODE0_EVCTRL_PEREO1_Pos = 0x1
	// Bit mask of PEREO1 field.
	RTC_MODE0_EVCTRL_PEREO1_Msk = 0x2
	// Bit PEREO1.
	RTC_MODE0_EVCTRL_PEREO1 = 0x2
	// Position of PEREO2 field.
	RTC_MODE0_EVCTRL_PEREO2_Pos = 0x2
	// Bit mask of PEREO2 field.
	RTC_MODE0_EVCTRL_PEREO2_Msk = 0x4
	// Bit PEREO2.
	RTC_MODE0_EVCTRL_PEREO2 = 0x4
	// Position of PEREO3 field.
	RTC_MODE0_EVCTRL_PEREO3_Pos = 0x3
	// Bit mask of PEREO3 field.
	RTC_MODE0_EVCTRL_PEREO3_Msk = 0x8
	// Bit PEREO3.
	RTC_MODE0_EVCTRL_PEREO3 = 0x8
	// Position of PEREO4 field.
	RTC_MODE0_EVCTRL_PEREO4_Pos = 0x4
	// Bit mask of PEREO4 field.
	RTC_MODE0_EVCTRL_PEREO4_Msk = 0x10
	// Bit PEREO4.
	RTC_MODE0_EVCTRL_PEREO4 = 0x10
	// Position of PEREO5 field.
	RTC_MODE0_EVCTRL_PEREO5_Pos = 0x5
	// Bit mask of PEREO5 field.
	RTC_MODE0_EVCTRL_PEREO5_Msk = 0x20
	// Bit PEREO5.
	RTC_MODE0_EVCTRL_PEREO5 = 0x20
	// Position of PEREO6 field.
	RTC_MODE0_EVCTRL_PEREO6_Pos = 0x6
	// Bit mask of PEREO6 field.
	RTC_MODE0_EVCTRL_PEREO6_Msk = 0x40
	// Bit PEREO6.
	RTC_MODE0_EVCTRL_PEREO6 = 0x40
	// Position of PEREO7 field.
	RTC_MODE0_EVCTRL_PEREO7_Pos = 0x7
	// Bit mask of PEREO7 field.
	RTC_MODE0_EVCTRL_PEREO7_Msk = 0x80
	// Bit PEREO7.
	RTC_MODE0_EVCTRL_PEREO7 = 0x80
	// Position of CMPEO0 field.
	RTC_MODE0_EVCTRL_CMPEO0_Pos = 0x8
	// Bit mask of CMPEO0 field.
	RTC_MODE0_EVCTRL_CMPEO0_Msk = 0x100
	// Bit CMPEO0.
	RTC_MODE0_EVCTRL_CMPEO0 = 0x100
	// Position of CMPEO1 field.
	RTC_MODE0_EVCTRL_CMPEO1_Pos = 0x9
	// Bit mask of CMPEO1 field.
	RTC_MODE0_EVCTRL_CMPEO1_Msk = 0x200
	// Bit CMPEO1.
	RTC_MODE0_EVCTRL_CMPEO1 = 0x200
	// Position of TAMPEREO field.
	RTC_MODE0_EVCTRL_TAMPEREO_Pos = 0xe
	// Bit mask of TAMPEREO field.
	RTC_MODE0_EVCTRL_TAMPEREO_Msk = 0x4000
	// Bit TAMPEREO.
	RTC_MODE0_EVCTRL_TAMPEREO = 0x4000
	// Position of OVFEO field.
	RTC_MODE0_EVCTRL_OVFEO_Pos = 0xf
	// Bit mask of OVFEO field.
	RTC_MODE0_EVCTRL_OVFEO_Msk = 0x8000
	// Bit OVFEO.
	RTC_MODE0_EVCTRL_OVFEO = 0x8000
	// Position of TAMPEVEI field.
	RTC_MODE0_EVCTRL_TAMPEVEI_Pos = 0x10
	// Bit mask of TAMPEVEI field.
	RTC_MODE0_EVCTRL_TAMPEVEI_Msk = 0x10000
	// Bit TAMPEVEI.
	RTC_MODE0_EVCTRL_TAMPEVEI = 0x10000

	// INTENCLR: MODE0 Interrupt Enable Clear
	// Position of PER0 field.
	RTC_MODE0_INTENCLR_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE0_INTENCLR_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE0_INTENCLR_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE0_INTENCLR_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE0_INTENCLR_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE0_INTENCLR_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE0_INTENCLR_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE0_INTENCLR_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE0_INTENCLR_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE0_INTENCLR_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE0_INTENCLR_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE0_INTENCLR_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE0_INTENCLR_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE0_INTENCLR_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE0_INTENCLR_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE0_INTENCLR_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE0_INTENCLR_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE0_INTENCLR_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE0_INTENCLR_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE0_INTENCLR_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE0_INTENCLR_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE0_INTENCLR_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE0_INTENCLR_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE0_INTENCLR_PER7 = 0x80
	// Position of CMP0 field.
	RTC_MODE0_INTENCLR_CMP0_Pos = 0x8
	// Bit mask of CMP0 field.
	RTC_MODE0_INTENCLR_CMP0_Msk = 0x100
	// Bit CMP0.
	RTC_MODE0_INTENCLR_CMP0 = 0x100
	// Position of CMP1 field.
	RTC_MODE0_INTENCLR_CMP1_Pos = 0x9
	// Bit mask of CMP1 field.
	RTC_MODE0_INTENCLR_CMP1_Msk = 0x200
	// Bit CMP1.
	RTC_MODE0_INTENCLR_CMP1 = 0x200
	// Position of TAMPER field.
	RTC_MODE0_INTENCLR_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE0_INTENCLR_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE0_INTENCLR_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE0_INTENCLR_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE0_INTENCLR_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE0_INTENCLR_OVF = 0x8000

	// INTENSET: MODE0 Interrupt Enable Set
	// Position of PER0 field.
	RTC_MODE0_INTENSET_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE0_INTENSET_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE0_INTENSET_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE0_INTENSET_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE0_INTENSET_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE0_INTENSET_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE0_INTENSET_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE0_INTENSET_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE0_INTENSET_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE0_INTENSET_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE0_INTENSET_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE0_INTENSET_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE0_INTENSET_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE0_INTENSET_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE0_INTENSET_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE0_INTENSET_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE0_INTENSET_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE0_INTENSET_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE0_INTENSET_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE0_INTENSET_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE0_INTENSET_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE0_INTENSET_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE0_INTENSET_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE0_INTENSET_PER7 = 0x80
	// Position of CMP0 field.
	RTC_MODE0_INTENSET_CMP0_Pos = 0x8
	// Bit mask of CMP0 field.
	RTC_MODE0_INTENSET_CMP0_Msk = 0x100
	// Bit CMP0.
	RTC_MODE0_INTENSET_CMP0 = 0x100
	// Position of CMP1 field.
	RTC_MODE0_INTENSET_CMP1_Pos = 0x9
	// Bit mask of CMP1 field.
	RTC_MODE0_INTENSET_CMP1_Msk = 0x200
	// Bit CMP1.
	RTC_MODE0_INTENSET_CMP1 = 0x200
	// Position of TAMPER field.
	RTC_MODE0_INTENSET_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE0_INTENSET_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE0_INTENSET_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE0_INTENSET_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE0_INTENSET_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE0_INTENSET_OVF = 0x8000

	// INTFLAG: MODE0 Interrupt Flag Status and Clear
	// Position of PER0 field.
	RTC_MODE0_INTFLAG_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE0_INTFLAG_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE0_INTFLAG_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE0_INTFLAG_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE0_INTFLAG_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE0_INTFLAG_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE0_INTFLAG_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE0_INTFLAG_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE0_INTFLAG_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE0_INTFLAG_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE0_INTFLAG_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE0_INTFLAG_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE0_INTFLAG_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE0_INTFLAG_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE0_INTFLAG_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE0_INTFLAG_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE0_INTFLAG_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE0_INTFLAG_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE0_INTFLAG_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE0_INTFLAG_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE0_INTFLAG_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE0_INTFLAG_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE0_INTFLAG_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE0_INTFLAG_PER7 = 0x80
	// Position of CMP0 field.
	RTC_MODE0_INTFLAG_CMP0_Pos = 0x8
	// Bit mask of CMP0 field.
	RTC_MODE0_INTFLAG_CMP0_Msk = 0x100
	// Bit CMP0.
	RTC_MODE0_INTFLAG_CMP0 = 0x100
	// Position of CMP1 field.
	RTC_MODE0_INTFLAG_CMP1_Pos = 0x9
	// Bit mask of CMP1 field.
	RTC_MODE0_INTFLAG_CMP1_Msk = 0x200
	// Bit CMP1.
	RTC_MODE0_INTFLAG_CMP1 = 0x200
	// Position of TAMPER field.
	RTC_MODE0_INTFLAG_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE0_INTFLAG_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE0_INTFLAG_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE0_INTFLAG_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE0_INTFLAG_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE0_INTFLAG_OVF = 0x8000

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	RTC_MODE0_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	RTC_MODE0_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	RTC_MODE0_DBGCTRL_DBGRUN = 0x1

	// SYNCBUSY: MODE0 Synchronization Busy Status
	// Position of SWRST field.
	RTC_MODE0_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	RTC_MODE0_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	RTC_MODE0_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	RTC_MODE0_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	RTC_MODE0_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	RTC_MODE0_SYNCBUSY_ENABLE = 0x2
	// Position of FREQCORR field.
	RTC_MODE0_SYNCBUSY_FREQCORR_Pos = 0x2
	// Bit mask of FREQCORR field.
	RTC_MODE0_SYNCBUSY_FREQCORR_Msk = 0x4
	// Bit FREQCORR.
	RTC_MODE0_SYNCBUSY_FREQCORR = 0x4
	// Position of COUNT field.
	RTC_MODE0_SYNCBUSY_COUNT_Pos = 0x3
	// Bit mask of COUNT field.
	RTC_MODE0_SYNCBUSY_COUNT_Msk = 0x8
	// Bit COUNT.
	RTC_MODE0_SYNCBUSY_COUNT = 0x8
	// Position of COMP0 field.
	RTC_MODE0_SYNCBUSY_COMP0_Pos = 0x5
	// Bit mask of COMP0 field.
	RTC_MODE0_SYNCBUSY_COMP0_Msk = 0x20
	// Bit COMP0.
	RTC_MODE0_SYNCBUSY_COMP0 = 0x20
	// Position of COMP1 field.
	RTC_MODE0_SYNCBUSY_COMP1_Pos = 0x6
	// Bit mask of COMP1 field.
	RTC_MODE0_SYNCBUSY_COMP1_Msk = 0x40
	// Bit COMP1.
	RTC_MODE0_SYNCBUSY_COMP1 = 0x40
	// Position of COUNTSYNC field.
	RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos = 0xf
	// Bit mask of COUNTSYNC field.
	RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk = 0x8000
	// Bit COUNTSYNC.
	RTC_MODE0_SYNCBUSY_COUNTSYNC = 0x8000
	// Position of GP0 field.
	RTC_MODE0_SYNCBUSY_GP0_Pos = 0x10
	// Bit mask of GP0 field.
	RTC_MODE0_SYNCBUSY_GP0_Msk = 0x10000
	// Bit GP0.
	RTC_MODE0_SYNCBUSY_GP0 = 0x10000
	// Position of GP1 field.
	RTC_MODE0_SYNCBUSY_GP1_Pos = 0x11
	// Bit mask of GP1 field.
	RTC_MODE0_SYNCBUSY_GP1_Msk = 0x20000
	// Bit GP1.
	RTC_MODE0_SYNCBUSY_GP1 = 0x20000
	// Position of GP2 field.
	RTC_MODE0_SYNCBUSY_GP2_Pos = 0x12
	// Bit mask of GP2 field.
	RTC_MODE0_SYNCBUSY_GP2_Msk = 0x40000
	// Bit GP2.
	RTC_MODE0_SYNCBUSY_GP2 = 0x40000
	// Position of GP3 field.
	RTC_MODE0_SYNCBUSY_GP3_Pos = 0x13
	// Bit mask of GP3 field.
	RTC_MODE0_SYNCBUSY_GP3_Msk = 0x80000
	// Bit GP3.
	RTC_MODE0_SYNCBUSY_GP3 = 0x80000

	// FREQCORR: Frequency Correction
	// Position of VALUE field.
	RTC_MODE0_FREQCORR_VALUE_Pos = 0x0
	// Bit mask of VALUE field.
	RTC_MODE0_FREQCORR_VALUE_Msk = 0x7f
	// Position of SIGN field.
	RTC_MODE0_FREQCORR_SIGN_Pos = 0x7
	// Bit mask of SIGN field.
	RTC_MODE0_FREQCORR_SIGN_Msk = 0x80
	// Bit SIGN.
	RTC_MODE0_FREQCORR_SIGN = 0x80

	// COUNT: MODE0 Counter Value
	// Position of COUNT field.
	RTC_MODE0_COUNT_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	RTC_MODE0_COUNT_COUNT_Msk = 0xffffffff

	// COMP: MODE0 Compare n Value
	// Position of COMP field.
	RTC_MODE0_COMP_COMP_Pos = 0x0
	// Bit mask of COMP field.
	RTC_MODE0_COMP_COMP_Msk = 0xffffffff

	// GP: General Purpose
	// Position of GP field.
	RTC_MODE0_GP_GP_Pos = 0x0
	// Bit mask of GP field.
	RTC_MODE0_GP_GP_Msk = 0xffffffff

	// TAMPCTRL: Tamper Control
	// Position of IN0ACT field.
	RTC_MODE0_TAMPCTRL_IN0ACT_Pos = 0x0
	// Bit mask of IN0ACT field.
	RTC_MODE0_TAMPCTRL_IN0ACT_Msk = 0x3
	// Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN0ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN0ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE0_TAMPCTRL_IN0ACT_CAPTURE = 0x2
	// Compare IN0 to OUT
	RTC_MODE0_TAMPCTRL_IN0ACT_ACTL = 0x3
	// Position of IN1ACT field.
	RTC_MODE0_TAMPCTRL_IN1ACT_Pos = 0x2
	// Bit mask of IN1ACT field.
	RTC_MODE0_TAMPCTRL_IN1ACT_Msk = 0xc
	// Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN1ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN1ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE0_TAMPCTRL_IN1ACT_CAPTURE = 0x2
	// Compare IN1 to OUT
	RTC_MODE0_TAMPCTRL_IN1ACT_ACTL = 0x3
	// Position of IN2ACT field.
	RTC_MODE0_TAMPCTRL_IN2ACT_Pos = 0x4
	// Bit mask of IN2ACT field.
	RTC_MODE0_TAMPCTRL_IN2ACT_Msk = 0x30
	// Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN2ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN2ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE0_TAMPCTRL_IN2ACT_CAPTURE = 0x2
	// Compare IN2 to OUT
	RTC_MODE0_TAMPCTRL_IN2ACT_ACTL = 0x3
	// Position of IN3ACT field.
	RTC_MODE0_TAMPCTRL_IN3ACT_Pos = 0x6
	// Bit mask of IN3ACT field.
	RTC_MODE0_TAMPCTRL_IN3ACT_Msk = 0xc0
	// Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN3ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN3ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE0_TAMPCTRL_IN3ACT_CAPTURE = 0x2
	// Compare IN3 to OUT
	RTC_MODE0_TAMPCTRL_IN3ACT_ACTL = 0x3
	// Position of IN4ACT field.
	RTC_MODE0_TAMPCTRL_IN4ACT_Pos = 0x8
	// Bit mask of IN4ACT field.
	RTC_MODE0_TAMPCTRL_IN4ACT_Msk = 0x300
	// Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN4ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN4ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE0_TAMPCTRL_IN4ACT_CAPTURE = 0x2
	// Compare IN4 to OUT
	RTC_MODE0_TAMPCTRL_IN4ACT_ACTL = 0x3
	// Position of TAMLVL0 field.
	RTC_MODE0_TAMPCTRL_TAMLVL0_Pos = 0x10
	// Bit mask of TAMLVL0 field.
	RTC_MODE0_TAMPCTRL_TAMLVL0_Msk = 0x10000
	// Bit TAMLVL0.
	RTC_MODE0_TAMPCTRL_TAMLVL0 = 0x10000
	// Position of TAMLVL1 field.
	RTC_MODE0_TAMPCTRL_TAMLVL1_Pos = 0x11
	// Bit mask of TAMLVL1 field.
	RTC_MODE0_TAMPCTRL_TAMLVL1_Msk = 0x20000
	// Bit TAMLVL1.
	RTC_MODE0_TAMPCTRL_TAMLVL1 = 0x20000
	// Position of TAMLVL2 field.
	RTC_MODE0_TAMPCTRL_TAMLVL2_Pos = 0x12
	// Bit mask of TAMLVL2 field.
	RTC_MODE0_TAMPCTRL_TAMLVL2_Msk = 0x40000
	// Bit TAMLVL2.
	RTC_MODE0_TAMPCTRL_TAMLVL2 = 0x40000
	// Position of TAMLVL3 field.
	RTC_MODE0_TAMPCTRL_TAMLVL3_Pos = 0x13
	// Bit mask of TAMLVL3 field.
	RTC_MODE0_TAMPCTRL_TAMLVL3_Msk = 0x80000
	// Bit TAMLVL3.
	RTC_MODE0_TAMPCTRL_TAMLVL3 = 0x80000
	// Position of TAMLVL4 field.
	RTC_MODE0_TAMPCTRL_TAMLVL4_Pos = 0x14
	// Bit mask of TAMLVL4 field.
	RTC_MODE0_TAMPCTRL_TAMLVL4_Msk = 0x100000
	// Bit TAMLVL4.
	RTC_MODE0_TAMPCTRL_TAMLVL4 = 0x100000
	// Position of DEBNC0 field.
	RTC_MODE0_TAMPCTRL_DEBNC0_Pos = 0x18
	// Bit mask of DEBNC0 field.
	RTC_MODE0_TAMPCTRL_DEBNC0_Msk = 0x1000000
	// Bit DEBNC0.
	RTC_MODE0_TAMPCTRL_DEBNC0 = 0x1000000
	// Position of DEBNC1 field.
	RTC_MODE0_TAMPCTRL_DEBNC1_Pos = 0x19
	// Bit mask of DEBNC1 field.
	RTC_MODE0_TAMPCTRL_DEBNC1_Msk = 0x2000000
	// Bit DEBNC1.
	RTC_MODE0_TAMPCTRL_DEBNC1 = 0x2000000
	// Position of DEBNC2 field.
	RTC_MODE0_TAMPCTRL_DEBNC2_Pos = 0x1a
	// Bit mask of DEBNC2 field.
	RTC_MODE0_TAMPCTRL_DEBNC2_Msk = 0x4000000
	// Bit DEBNC2.
	RTC_MODE0_TAMPCTRL_DEBNC2 = 0x4000000
	// Position of DEBNC3 field.
	RTC_MODE0_TAMPCTRL_DEBNC3_Pos = 0x1b
	// Bit mask of DEBNC3 field.
	RTC_MODE0_TAMPCTRL_DEBNC3_Msk = 0x8000000
	// Bit DEBNC3.
	RTC_MODE0_TAMPCTRL_DEBNC3 = 0x8000000
	// Position of DEBNC4 field.
	RTC_MODE0_TAMPCTRL_DEBNC4_Pos = 0x1c
	// Bit mask of DEBNC4 field.
	RTC_MODE0_TAMPCTRL_DEBNC4_Msk = 0x10000000
	// Bit DEBNC4.
	RTC_MODE0_TAMPCTRL_DEBNC4 = 0x10000000

	// TIMESTAMP: MODE0 Timestamp
	// Position of COUNT field.
	RTC_MODE0_TIMESTAMP_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	RTC_MODE0_TIMESTAMP_COUNT_Msk = 0xffffffff

	// TAMPID: Tamper ID
	// Position of TAMPID0 field.
	RTC_MODE0_TAMPID_TAMPID0_Pos = 0x0
	// Bit mask of TAMPID0 field.
	RTC_MODE0_TAMPID_TAMPID0_Msk = 0x1
	// Bit TAMPID0.
	RTC_MODE0_TAMPID_TAMPID0 = 0x1
	// Position of TAMPID1 field.
	RTC_MODE0_TAMPID_TAMPID1_Pos = 0x1
	// Bit mask of TAMPID1 field.
	RTC_MODE0_TAMPID_TAMPID1_Msk = 0x2
	// Bit TAMPID1.
	RTC_MODE0_TAMPID_TAMPID1 = 0x2
	// Position of TAMPID2 field.
	RTC_MODE0_TAMPID_TAMPID2_Pos = 0x2
	// Bit mask of TAMPID2 field.
	RTC_MODE0_TAMPID_TAMPID2_Msk = 0x4
	// Bit TAMPID2.
	RTC_MODE0_TAMPID_TAMPID2 = 0x4
	// Position of TAMPID3 field.
	RTC_MODE0_TAMPID_TAMPID3_Pos = 0x3
	// Bit mask of TAMPID3 field.
	RTC_MODE0_TAMPID_TAMPID3_Msk = 0x8
	// Bit TAMPID3.
	RTC_MODE0_TAMPID_TAMPID3 = 0x8
	// Position of TAMPID4 field.
	RTC_MODE0_TAMPID_TAMPID4_Pos = 0x4
	// Bit mask of TAMPID4 field.
	RTC_MODE0_TAMPID_TAMPID4_Msk = 0x10
	// Bit TAMPID4.
	RTC_MODE0_TAMPID_TAMPID4 = 0x10
	// Position of TAMPEVT field.
	RTC_MODE0_TAMPID_TAMPEVT_Pos = 0x1f
	// Bit mask of TAMPEVT field.
	RTC_MODE0_TAMPID_TAMPEVT_Msk = 0x80000000
	// Bit TAMPEVT.
	RTC_MODE0_TAMPID_TAMPEVT = 0x80000000

	// BKUP: Backup
	// Position of BKUP field.
	RTC_MODE0_BKUP_BKUP_Pos = 0x0
	// Bit mask of BKUP field.
	RTC_MODE0_BKUP_BKUP_Msk = 0xffffffff
)

// Bitfields for RTC_MODE1: Real-Time Counter - MODE1
const (
	// CTRLA: MODE1 Control A
	// Position of SWRST field.
	RTC_MODE1_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	RTC_MODE1_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	RTC_MODE1_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	RTC_MODE1_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	RTC_MODE1_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	RTC_MODE1_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	RTC_MODE1_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	RTC_MODE1_CTRLA_MODE_Msk = 0xc
	// Mode 0: 32-bit Counter
	RTC_MODE1_CTRLA_MODE_COUNT32 = 0x0
	// Mode 1: 16-bit Counter
	RTC_MODE1_CTRLA_MODE_COUNT16 = 0x1
	// Mode 2: Clock/Calendar
	RTC_MODE1_CTRLA_MODE_CLOCK = 0x2
	// Position of PRESCALER field.
	RTC_MODE1_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	RTC_MODE1_CTRLA_PRESCALER_Msk = 0xf00
	// CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE1_CTRLA_PRESCALER_OFF = 0x0
	// CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE1_CTRLA_PRESCALER_DIV1 = 0x1
	// CLK_RTC_CNT = GCLK_RTC/2
	RTC_MODE1_CTRLA_PRESCALER_DIV2 = 0x2
	// CLK_RTC_CNT = GCLK_RTC/4
	RTC_MODE1_CTRLA_PRESCALER_DIV4 = 0x3
	// CLK_RTC_CNT = GCLK_RTC/8
	RTC_MODE1_CTRLA_PRESCALER_DIV8 = 0x4
	// CLK_RTC_CNT = GCLK_RTC/16
	RTC_MODE1_CTRLA_PRESCALER_DIV16 = 0x5
	// CLK_RTC_CNT = GCLK_RTC/32
	RTC_MODE1_CTRLA_PRESCALER_DIV32 = 0x6
	// CLK_RTC_CNT = GCLK_RTC/64
	RTC_MODE1_CTRLA_PRESCALER_DIV64 = 0x7
	// CLK_RTC_CNT = GCLK_RTC/128
	RTC_MODE1_CTRLA_PRESCALER_DIV128 = 0x8
	// CLK_RTC_CNT = GCLK_RTC/256
	RTC_MODE1_CTRLA_PRESCALER_DIV256 = 0x9
	// CLK_RTC_CNT = GCLK_RTC/512
	RTC_MODE1_CTRLA_PRESCALER_DIV512 = 0xa
	// CLK_RTC_CNT = GCLK_RTC/1024
	RTC_MODE1_CTRLA_PRESCALER_DIV1024 = 0xb
	// Position of BKTRST field.
	RTC_MODE1_CTRLA_BKTRST_Pos = 0xd
	// Bit mask of BKTRST field.
	RTC_MODE1_CTRLA_BKTRST_Msk = 0x2000
	// Bit BKTRST.
	RTC_MODE1_CTRLA_BKTRST = 0x2000
	// Position of GPTRST field.
	RTC_MODE1_CTRLA_GPTRST_Pos = 0xe
	// Bit mask of GPTRST field.
	RTC_MODE1_CTRLA_GPTRST_Msk = 0x4000
	// Bit GPTRST.
	RTC_MODE1_CTRLA_GPTRST = 0x4000
	// Position of COUNTSYNC field.
	RTC_MODE1_CTRLA_COUNTSYNC_Pos = 0xf
	// Bit mask of COUNTSYNC field.
	RTC_MODE1_CTRLA_COUNTSYNC_Msk = 0x8000
	// Bit COUNTSYNC.
	RTC_MODE1_CTRLA_COUNTSYNC = 0x8000

	// CTRLB: MODE1 Control B
	// Position of GP0EN field.
	RTC_MODE1_CTRLB_GP0EN_Pos = 0x0
	// Bit mask of GP0EN field.
	RTC_MODE1_CTRLB_GP0EN_Msk = 0x1
	// Bit GP0EN.
	RTC_MODE1_CTRLB_GP0EN = 0x1
	// Position of GP2EN field.
	RTC_MODE1_CTRLB_GP2EN_Pos = 0x1
	// Bit mask of GP2EN field.
	RTC_MODE1_CTRLB_GP2EN_Msk = 0x2
	// Bit GP2EN.
	RTC_MODE1_CTRLB_GP2EN = 0x2
	// Position of DEBMAJ field.
	RTC_MODE1_CTRLB_DEBMAJ_Pos = 0x4
	// Bit mask of DEBMAJ field.
	RTC_MODE1_CTRLB_DEBMAJ_Msk = 0x10
	// Bit DEBMAJ.
	RTC_MODE1_CTRLB_DEBMAJ = 0x10
	// Position of DEBASYNC field.
	RTC_MODE1_CTRLB_DEBASYNC_Pos = 0x5
	// Bit mask of DEBASYNC field.
	RTC_MODE1_CTRLB_DEBASYNC_Msk = 0x20
	// Bit DEBASYNC.
	RTC_MODE1_CTRLB_DEBASYNC = 0x20
	// Position of RTCOUT field.
	RTC_MODE1_CTRLB_RTCOUT_Pos = 0x6
	// Bit mask of RTCOUT field.
	RTC_MODE1_CTRLB_RTCOUT_Msk = 0x40
	// Bit RTCOUT.
	RTC_MODE1_CTRLB_RTCOUT = 0x40
	// Position of DMAEN field.
	RTC_MODE1_CTRLB_DMAEN_Pos = 0x7
	// Bit mask of DMAEN field.
	RTC_MODE1_CTRLB_DMAEN_Msk = 0x80
	// Bit DMAEN.
	RTC_MODE1_CTRLB_DMAEN = 0x80
	// Position of DEBF field.
	RTC_MODE1_CTRLB_DEBF_Pos = 0x8
	// Bit mask of DEBF field.
	RTC_MODE1_CTRLB_DEBF_Msk = 0x700
	// CLK_RTC_DEB = CLK_RTC/2
	RTC_MODE1_CTRLB_DEBF_DIV2 = 0x0
	// CLK_RTC_DEB = CLK_RTC/4
	RTC_MODE1_CTRLB_DEBF_DIV4 = 0x1
	// CLK_RTC_DEB = CLK_RTC/8
	RTC_MODE1_CTRLB_DEBF_DIV8 = 0x2
	// CLK_RTC_DEB = CLK_RTC/16
	RTC_MODE1_CTRLB_DEBF_DIV16 = 0x3
	// CLK_RTC_DEB = CLK_RTC/32
	RTC_MODE1_CTRLB_DEBF_DIV32 = 0x4
	// CLK_RTC_DEB = CLK_RTC/64
	RTC_MODE1_CTRLB_DEBF_DIV64 = 0x5
	// CLK_RTC_DEB = CLK_RTC/128
	RTC_MODE1_CTRLB_DEBF_DIV128 = 0x6
	// CLK_RTC_DEB = CLK_RTC/256
	RTC_MODE1_CTRLB_DEBF_DIV256 = 0x7
	// Position of ACTF field.
	RTC_MODE1_CTRLB_ACTF_Pos = 0xc
	// Bit mask of ACTF field.
	RTC_MODE1_CTRLB_ACTF_Msk = 0x7000
	// CLK_RTC_OUT = CLK_RTC/2
	RTC_MODE1_CTRLB_ACTF_DIV2 = 0x0
	// CLK_RTC_OUT = CLK_RTC/4
	RTC_MODE1_CTRLB_ACTF_DIV4 = 0x1
	// CLK_RTC_OUT = CLK_RTC/8
	RTC_MODE1_CTRLB_ACTF_DIV8 = 0x2
	// CLK_RTC_OUT = CLK_RTC/16
	RTC_MODE1_CTRLB_ACTF_DIV16 = 0x3
	// CLK_RTC_OUT = CLK_RTC/32
	RTC_MODE1_CTRLB_ACTF_DIV32 = 0x4
	// CLK_RTC_OUT = CLK_RTC/64
	RTC_MODE1_CTRLB_ACTF_DIV64 = 0x5
	// CLK_RTC_OUT = CLK_RTC/128
	RTC_MODE1_CTRLB_ACTF_DIV128 = 0x6
	// CLK_RTC_OUT = CLK_RTC/256
	RTC_MODE1_CTRLB_ACTF_DIV256 = 0x7

	// EVCTRL: MODE1 Event Control
	// Position of PEREO0 field.
	RTC_MODE1_EVCTRL_PEREO0_Pos = 0x0
	// Bit mask of PEREO0 field.
	RTC_MODE1_EVCTRL_PEREO0_Msk = 0x1
	// Bit PEREO0.
	RTC_MODE1_EVCTRL_PEREO0 = 0x1
	// Position of PEREO1 field.
	RTC_MODE1_EVCTRL_PEREO1_Pos = 0x1
	// Bit mask of PEREO1 field.
	RTC_MODE1_EVCTRL_PEREO1_Msk = 0x2
	// Bit PEREO1.
	RTC_MODE1_EVCTRL_PEREO1 = 0x2
	// Position of PEREO2 field.
	RTC_MODE1_EVCTRL_PEREO2_Pos = 0x2
	// Bit mask of PEREO2 field.
	RTC_MODE1_EVCTRL_PEREO2_Msk = 0x4
	// Bit PEREO2.
	RTC_MODE1_EVCTRL_PEREO2 = 0x4
	// Position of PEREO3 field.
	RTC_MODE1_EVCTRL_PEREO3_Pos = 0x3
	// Bit mask of PEREO3 field.
	RTC_MODE1_EVCTRL_PEREO3_Msk = 0x8
	// Bit PEREO3.
	RTC_MODE1_EVCTRL_PEREO3 = 0x8
	// Position of PEREO4 field.
	RTC_MODE1_EVCTRL_PEREO4_Pos = 0x4
	// Bit mask of PEREO4 field.
	RTC_MODE1_EVCTRL_PEREO4_Msk = 0x10
	// Bit PEREO4.
	RTC_MODE1_EVCTRL_PEREO4 = 0x10
	// Position of PEREO5 field.
	RTC_MODE1_EVCTRL_PEREO5_Pos = 0x5
	// Bit mask of PEREO5 field.
	RTC_MODE1_EVCTRL_PEREO5_Msk = 0x20
	// Bit PEREO5.
	RTC_MODE1_EVCTRL_PEREO5 = 0x20
	// Position of PEREO6 field.
	RTC_MODE1_EVCTRL_PEREO6_Pos = 0x6
	// Bit mask of PEREO6 field.
	RTC_MODE1_EVCTRL_PEREO6_Msk = 0x40
	// Bit PEREO6.
	RTC_MODE1_EVCTRL_PEREO6 = 0x40
	// Position of PEREO7 field.
	RTC_MODE1_EVCTRL_PEREO7_Pos = 0x7
	// Bit mask of PEREO7 field.
	RTC_MODE1_EVCTRL_PEREO7_Msk = 0x80
	// Bit PEREO7.
	RTC_MODE1_EVCTRL_PEREO7 = 0x80
	// Position of CMPEO0 field.
	RTC_MODE1_EVCTRL_CMPEO0_Pos = 0x8
	// Bit mask of CMPEO0 field.
	RTC_MODE1_EVCTRL_CMPEO0_Msk = 0x100
	// Bit CMPEO0.
	RTC_MODE1_EVCTRL_CMPEO0 = 0x100
	// Position of CMPEO1 field.
	RTC_MODE1_EVCTRL_CMPEO1_Pos = 0x9
	// Bit mask of CMPEO1 field.
	RTC_MODE1_EVCTRL_CMPEO1_Msk = 0x200
	// Bit CMPEO1.
	RTC_MODE1_EVCTRL_CMPEO1 = 0x200
	// Position of CMPEO2 field.
	RTC_MODE1_EVCTRL_CMPEO2_Pos = 0xa
	// Bit mask of CMPEO2 field.
	RTC_MODE1_EVCTRL_CMPEO2_Msk = 0x400
	// Bit CMPEO2.
	RTC_MODE1_EVCTRL_CMPEO2 = 0x400
	// Position of CMPEO3 field.
	RTC_MODE1_EVCTRL_CMPEO3_Pos = 0xb
	// Bit mask of CMPEO3 field.
	RTC_MODE1_EVCTRL_CMPEO3_Msk = 0x800
	// Bit CMPEO3.
	RTC_MODE1_EVCTRL_CMPEO3 = 0x800
	// Position of TAMPEREO field.
	RTC_MODE1_EVCTRL_TAMPEREO_Pos = 0xe
	// Bit mask of TAMPEREO field.
	RTC_MODE1_EVCTRL_TAMPEREO_Msk = 0x4000
	// Bit TAMPEREO.
	RTC_MODE1_EVCTRL_TAMPEREO = 0x4000
	// Position of OVFEO field.
	RTC_MODE1_EVCTRL_OVFEO_Pos = 0xf
	// Bit mask of OVFEO field.
	RTC_MODE1_EVCTRL_OVFEO_Msk = 0x8000
	// Bit OVFEO.
	RTC_MODE1_EVCTRL_OVFEO = 0x8000
	// Position of TAMPEVEI field.
	RTC_MODE1_EVCTRL_TAMPEVEI_Pos = 0x10
	// Bit mask of TAMPEVEI field.
	RTC_MODE1_EVCTRL_TAMPEVEI_Msk = 0x10000
	// Bit TAMPEVEI.
	RTC_MODE1_EVCTRL_TAMPEVEI = 0x10000

	// INTENCLR: MODE1 Interrupt Enable Clear
	// Position of PER0 field.
	RTC_MODE1_INTENCLR_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE1_INTENCLR_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE1_INTENCLR_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE1_INTENCLR_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE1_INTENCLR_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE1_INTENCLR_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE1_INTENCLR_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE1_INTENCLR_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE1_INTENCLR_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE1_INTENCLR_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE1_INTENCLR_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE1_INTENCLR_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE1_INTENCLR_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE1_INTENCLR_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE1_INTENCLR_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE1_INTENCLR_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE1_INTENCLR_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE1_INTENCLR_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE1_INTENCLR_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE1_INTENCLR_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE1_INTENCLR_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE1_INTENCLR_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE1_INTENCLR_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE1_INTENCLR_PER7 = 0x80
	// Position of CMP0 field.
	RTC_MODE1_INTENCLR_CMP0_Pos = 0x8
	// Bit mask of CMP0 field.
	RTC_MODE1_INTENCLR_CMP0_Msk = 0x100
	// Bit CMP0.
	RTC_MODE1_INTENCLR_CMP0 = 0x100
	// Position of CMP1 field.
	RTC_MODE1_INTENCLR_CMP1_Pos = 0x9
	// Bit mask of CMP1 field.
	RTC_MODE1_INTENCLR_CMP1_Msk = 0x200
	// Bit CMP1.
	RTC_MODE1_INTENCLR_CMP1 = 0x200
	// Position of CMP2 field.
	RTC_MODE1_INTENCLR_CMP2_Pos = 0xa
	// Bit mask of CMP2 field.
	RTC_MODE1_INTENCLR_CMP2_Msk = 0x400
	// Bit CMP2.
	RTC_MODE1_INTENCLR_CMP2 = 0x400
	// Position of CMP3 field.
	RTC_MODE1_INTENCLR_CMP3_Pos = 0xb
	// Bit mask of CMP3 field.
	RTC_MODE1_INTENCLR_CMP3_Msk = 0x800
	// Bit CMP3.
	RTC_MODE1_INTENCLR_CMP3 = 0x800
	// Position of TAMPER field.
	RTC_MODE1_INTENCLR_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE1_INTENCLR_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE1_INTENCLR_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE1_INTENCLR_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE1_INTENCLR_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE1_INTENCLR_OVF = 0x8000

	// INTENSET: MODE1 Interrupt Enable Set
	// Position of PER0 field.
	RTC_MODE1_INTENSET_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE1_INTENSET_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE1_INTENSET_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE1_INTENSET_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE1_INTENSET_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE1_INTENSET_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE1_INTENSET_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE1_INTENSET_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE1_INTENSET_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE1_INTENSET_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE1_INTENSET_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE1_INTENSET_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE1_INTENSET_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE1_INTENSET_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE1_INTENSET_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE1_INTENSET_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE1_INTENSET_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE1_INTENSET_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE1_INTENSET_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE1_INTENSET_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE1_INTENSET_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE1_INTENSET_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE1_INTENSET_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE1_INTENSET_PER7 = 0x80
	// Position of CMP0 field.
	RTC_MODE1_INTENSET_CMP0_Pos = 0x8
	// Bit mask of CMP0 field.
	RTC_MODE1_INTENSET_CMP0_Msk = 0x100
	// Bit CMP0.
	RTC_MODE1_INTENSET_CMP0 = 0x100
	// Position of CMP1 field.
	RTC_MODE1_INTENSET_CMP1_Pos = 0x9
	// Bit mask of CMP1 field.
	RTC_MODE1_INTENSET_CMP1_Msk = 0x200
	// Bit CMP1.
	RTC_MODE1_INTENSET_CMP1 = 0x200
	// Position of CMP2 field.
	RTC_MODE1_INTENSET_CMP2_Pos = 0xa
	// Bit mask of CMP2 field.
	RTC_MODE1_INTENSET_CMP2_Msk = 0x400
	// Bit CMP2.
	RTC_MODE1_INTENSET_CMP2 = 0x400
	// Position of CMP3 field.
	RTC_MODE1_INTENSET_CMP3_Pos = 0xb
	// Bit mask of CMP3 field.
	RTC_MODE1_INTENSET_CMP3_Msk = 0x800
	// Bit CMP3.
	RTC_MODE1_INTENSET_CMP3 = 0x800
	// Position of TAMPER field.
	RTC_MODE1_INTENSET_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE1_INTENSET_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE1_INTENSET_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE1_INTENSET_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE1_INTENSET_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE1_INTENSET_OVF = 0x8000

	// INTFLAG: MODE1 Interrupt Flag Status and Clear
	// Position of PER0 field.
	RTC_MODE1_INTFLAG_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE1_INTFLAG_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE1_INTFLAG_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE1_INTFLAG_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE1_INTFLAG_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE1_INTFLAG_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE1_INTFLAG_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE1_INTFLAG_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE1_INTFLAG_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE1_INTFLAG_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE1_INTFLAG_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE1_INTFLAG_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE1_INTFLAG_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE1_INTFLAG_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE1_INTFLAG_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE1_INTFLAG_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE1_INTFLAG_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE1_INTFLAG_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE1_INTFLAG_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE1_INTFLAG_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE1_INTFLAG_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE1_INTFLAG_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE1_INTFLAG_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE1_INTFLAG_PER7 = 0x80
	// Position of CMP0 field.
	RTC_MODE1_INTFLAG_CMP0_Pos = 0x8
	// Bit mask of CMP0 field.
	RTC_MODE1_INTFLAG_CMP0_Msk = 0x100
	// Bit CMP0.
	RTC_MODE1_INTFLAG_CMP0 = 0x100
	// Position of CMP1 field.
	RTC_MODE1_INTFLAG_CMP1_Pos = 0x9
	// Bit mask of CMP1 field.
	RTC_MODE1_INTFLAG_CMP1_Msk = 0x200
	// Bit CMP1.
	RTC_MODE1_INTFLAG_CMP1 = 0x200
	// Position of CMP2 field.
	RTC_MODE1_INTFLAG_CMP2_Pos = 0xa
	// Bit mask of CMP2 field.
	RTC_MODE1_INTFLAG_CMP2_Msk = 0x400
	// Bit CMP2.
	RTC_MODE1_INTFLAG_CMP2 = 0x400
	// Position of CMP3 field.
	RTC_MODE1_INTFLAG_CMP3_Pos = 0xb
	// Bit mask of CMP3 field.
	RTC_MODE1_INTFLAG_CMP3_Msk = 0x800
	// Bit CMP3.
	RTC_MODE1_INTFLAG_CMP3 = 0x800
	// Position of TAMPER field.
	RTC_MODE1_INTFLAG_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE1_INTFLAG_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE1_INTFLAG_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE1_INTFLAG_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE1_INTFLAG_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE1_INTFLAG_OVF = 0x8000

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	RTC_MODE1_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	RTC_MODE1_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	RTC_MODE1_DBGCTRL_DBGRUN = 0x1

	// SYNCBUSY: MODE1 Synchronization Busy Status
	// Position of SWRST field.
	RTC_MODE1_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	RTC_MODE1_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	RTC_MODE1_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	RTC_MODE1_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	RTC_MODE1_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	RTC_MODE1_SYNCBUSY_ENABLE = 0x2
	// Position of FREQCORR field.
	RTC_MODE1_SYNCBUSY_FREQCORR_Pos = 0x2
	// Bit mask of FREQCORR field.
	RTC_MODE1_SYNCBUSY_FREQCORR_Msk = 0x4
	// Bit FREQCORR.
	RTC_MODE1_SYNCBUSY_FREQCORR = 0x4
	// Position of COUNT field.
	RTC_MODE1_SYNCBUSY_COUNT_Pos = 0x3
	// Bit mask of COUNT field.
	RTC_MODE1_SYNCBUSY_COUNT_Msk = 0x8
	// Bit COUNT.
	RTC_MODE1_SYNCBUSY_COUNT = 0x8
	// Position of PER field.
	RTC_MODE1_SYNCBUSY_PER_Pos = 0x4
	// Bit mask of PER field.
	RTC_MODE1_SYNCBUSY_PER_Msk = 0x10
	// Bit PER.
	RTC_MODE1_SYNCBUSY_PER = 0x10
	// Position of COMP0 field.
	RTC_MODE1_SYNCBUSY_COMP0_Pos = 0x5
	// Bit mask of COMP0 field.
	RTC_MODE1_SYNCBUSY_COMP0_Msk = 0x20
	// Bit COMP0.
	RTC_MODE1_SYNCBUSY_COMP0 = 0x20
	// Position of COMP1 field.
	RTC_MODE1_SYNCBUSY_COMP1_Pos = 0x6
	// Bit mask of COMP1 field.
	RTC_MODE1_SYNCBUSY_COMP1_Msk = 0x40
	// Bit COMP1.
	RTC_MODE1_SYNCBUSY_COMP1 = 0x40
	// Position of COMP2 field.
	RTC_MODE1_SYNCBUSY_COMP2_Pos = 0x7
	// Bit mask of COMP2 field.
	RTC_MODE1_SYNCBUSY_COMP2_Msk = 0x80
	// Bit COMP2.
	RTC_MODE1_SYNCBUSY_COMP2 = 0x80
	// Position of COMP3 field.
	RTC_MODE1_SYNCBUSY_COMP3_Pos = 0x8
	// Bit mask of COMP3 field.
	RTC_MODE1_SYNCBUSY_COMP3_Msk = 0x100
	// Bit COMP3.
	RTC_MODE1_SYNCBUSY_COMP3 = 0x100
	// Position of COUNTSYNC field.
	RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos = 0xf
	// Bit mask of COUNTSYNC field.
	RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk = 0x8000
	// Bit COUNTSYNC.
	RTC_MODE1_SYNCBUSY_COUNTSYNC = 0x8000
	// Position of GP0 field.
	RTC_MODE1_SYNCBUSY_GP0_Pos = 0x10
	// Bit mask of GP0 field.
	RTC_MODE1_SYNCBUSY_GP0_Msk = 0x10000
	// Bit GP0.
	RTC_MODE1_SYNCBUSY_GP0 = 0x10000
	// Position of GP1 field.
	RTC_MODE1_SYNCBUSY_GP1_Pos = 0x11
	// Bit mask of GP1 field.
	RTC_MODE1_SYNCBUSY_GP1_Msk = 0x20000
	// Bit GP1.
	RTC_MODE1_SYNCBUSY_GP1 = 0x20000
	// Position of GP2 field.
	RTC_MODE1_SYNCBUSY_GP2_Pos = 0x12
	// Bit mask of GP2 field.
	RTC_MODE1_SYNCBUSY_GP2_Msk = 0x40000
	// Bit GP2.
	RTC_MODE1_SYNCBUSY_GP2 = 0x40000
	// Position of GP3 field.
	RTC_MODE1_SYNCBUSY_GP3_Pos = 0x13
	// Bit mask of GP3 field.
	RTC_MODE1_SYNCBUSY_GP3_Msk = 0x80000
	// Bit GP3.
	RTC_MODE1_SYNCBUSY_GP3 = 0x80000

	// FREQCORR: Frequency Correction
	// Position of VALUE field.
	RTC_MODE1_FREQCORR_VALUE_Pos = 0x0
	// Bit mask of VALUE field.
	RTC_MODE1_FREQCORR_VALUE_Msk = 0x7f
	// Position of SIGN field.
	RTC_MODE1_FREQCORR_SIGN_Pos = 0x7
	// Bit mask of SIGN field.
	RTC_MODE1_FREQCORR_SIGN_Msk = 0x80
	// Bit SIGN.
	RTC_MODE1_FREQCORR_SIGN = 0x80

	// COUNT: MODE1 Counter Value
	// Position of COUNT field.
	RTC_MODE1_COUNT_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	RTC_MODE1_COUNT_COUNT_Msk = 0xffff

	// PER: MODE1 Counter Period
	// Position of PER field.
	RTC_MODE1_PER_PER_Pos = 0x0
	// Bit mask of PER field.
	RTC_MODE1_PER_PER_Msk = 0xffff

	// COMP: MODE1 Compare n Value
	// Position of COMP field.
	RTC_MODE1_COMP_COMP_Pos = 0x0
	// Bit mask of COMP field.
	RTC_MODE1_COMP_COMP_Msk = 0xffff

	// GP: General Purpose
	// Position of GP field.
	RTC_MODE1_GP_GP_Pos = 0x0
	// Bit mask of GP field.
	RTC_MODE1_GP_GP_Msk = 0xffffffff

	// TAMPCTRL: Tamper Control
	// Position of IN0ACT field.
	RTC_MODE1_TAMPCTRL_IN0ACT_Pos = 0x0
	// Bit mask of IN0ACT field.
	RTC_MODE1_TAMPCTRL_IN0ACT_Msk = 0x3
	// Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN0ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN0ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE1_TAMPCTRL_IN0ACT_CAPTURE = 0x2
	// Compare IN0 to OUT
	RTC_MODE1_TAMPCTRL_IN0ACT_ACTL = 0x3
	// Position of IN1ACT field.
	RTC_MODE1_TAMPCTRL_IN1ACT_Pos = 0x2
	// Bit mask of IN1ACT field.
	RTC_MODE1_TAMPCTRL_IN1ACT_Msk = 0xc
	// Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN1ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN1ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE1_TAMPCTRL_IN1ACT_CAPTURE = 0x2
	// Compare IN1 to OUT
	RTC_MODE1_TAMPCTRL_IN1ACT_ACTL = 0x3
	// Position of IN2ACT field.
	RTC_MODE1_TAMPCTRL_IN2ACT_Pos = 0x4
	// Bit mask of IN2ACT field.
	RTC_MODE1_TAMPCTRL_IN2ACT_Msk = 0x30
	// Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN2ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN2ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE1_TAMPCTRL_IN2ACT_CAPTURE = 0x2
	// Compare IN2 to OUT
	RTC_MODE1_TAMPCTRL_IN2ACT_ACTL = 0x3
	// Position of IN3ACT field.
	RTC_MODE1_TAMPCTRL_IN3ACT_Pos = 0x6
	// Bit mask of IN3ACT field.
	RTC_MODE1_TAMPCTRL_IN3ACT_Msk = 0xc0
	// Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN3ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN3ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE1_TAMPCTRL_IN3ACT_CAPTURE = 0x2
	// Compare IN3 to OUT
	RTC_MODE1_TAMPCTRL_IN3ACT_ACTL = 0x3
	// Position of IN4ACT field.
	RTC_MODE1_TAMPCTRL_IN4ACT_Pos = 0x8
	// Bit mask of IN4ACT field.
	RTC_MODE1_TAMPCTRL_IN4ACT_Msk = 0x300
	// Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN4ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN4ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE1_TAMPCTRL_IN4ACT_CAPTURE = 0x2
	// Compare IN4 to OUT
	RTC_MODE1_TAMPCTRL_IN4ACT_ACTL = 0x3
	// Position of TAMLVL0 field.
	RTC_MODE1_TAMPCTRL_TAMLVL0_Pos = 0x10
	// Bit mask of TAMLVL0 field.
	RTC_MODE1_TAMPCTRL_TAMLVL0_Msk = 0x10000
	// Bit TAMLVL0.
	RTC_MODE1_TAMPCTRL_TAMLVL0 = 0x10000
	// Position of TAMLVL1 field.
	RTC_MODE1_TAMPCTRL_TAMLVL1_Pos = 0x11
	// Bit mask of TAMLVL1 field.
	RTC_MODE1_TAMPCTRL_TAMLVL1_Msk = 0x20000
	// Bit TAMLVL1.
	RTC_MODE1_TAMPCTRL_TAMLVL1 = 0x20000
	// Position of TAMLVL2 field.
	RTC_MODE1_TAMPCTRL_TAMLVL2_Pos = 0x12
	// Bit mask of TAMLVL2 field.
	RTC_MODE1_TAMPCTRL_TAMLVL2_Msk = 0x40000
	// Bit TAMLVL2.
	RTC_MODE1_TAMPCTRL_TAMLVL2 = 0x40000
	// Position of TAMLVL3 field.
	RTC_MODE1_TAMPCTRL_TAMLVL3_Pos = 0x13
	// Bit mask of TAMLVL3 field.
	RTC_MODE1_TAMPCTRL_TAMLVL3_Msk = 0x80000
	// Bit TAMLVL3.
	RTC_MODE1_TAMPCTRL_TAMLVL3 = 0x80000
	// Position of TAMLVL4 field.
	RTC_MODE1_TAMPCTRL_TAMLVL4_Pos = 0x14
	// Bit mask of TAMLVL4 field.
	RTC_MODE1_TAMPCTRL_TAMLVL4_Msk = 0x100000
	// Bit TAMLVL4.
	RTC_MODE1_TAMPCTRL_TAMLVL4 = 0x100000
	// Position of DEBNC0 field.
	RTC_MODE1_TAMPCTRL_DEBNC0_Pos = 0x18
	// Bit mask of DEBNC0 field.
	RTC_MODE1_TAMPCTRL_DEBNC0_Msk = 0x1000000
	// Bit DEBNC0.
	RTC_MODE1_TAMPCTRL_DEBNC0 = 0x1000000
	// Position of DEBNC1 field.
	RTC_MODE1_TAMPCTRL_DEBNC1_Pos = 0x19
	// Bit mask of DEBNC1 field.
	RTC_MODE1_TAMPCTRL_DEBNC1_Msk = 0x2000000
	// Bit DEBNC1.
	RTC_MODE1_TAMPCTRL_DEBNC1 = 0x2000000
	// Position of DEBNC2 field.
	RTC_MODE1_TAMPCTRL_DEBNC2_Pos = 0x1a
	// Bit mask of DEBNC2 field.
	RTC_MODE1_TAMPCTRL_DEBNC2_Msk = 0x4000000
	// Bit DEBNC2.
	RTC_MODE1_TAMPCTRL_DEBNC2 = 0x4000000
	// Position of DEBNC3 field.
	RTC_MODE1_TAMPCTRL_DEBNC3_Pos = 0x1b
	// Bit mask of DEBNC3 field.
	RTC_MODE1_TAMPCTRL_DEBNC3_Msk = 0x8000000
	// Bit DEBNC3.
	RTC_MODE1_TAMPCTRL_DEBNC3 = 0x8000000
	// Position of DEBNC4 field.
	RTC_MODE1_TAMPCTRL_DEBNC4_Pos = 0x1c
	// Bit mask of DEBNC4 field.
	RTC_MODE1_TAMPCTRL_DEBNC4_Msk = 0x10000000
	// Bit DEBNC4.
	RTC_MODE1_TAMPCTRL_DEBNC4 = 0x10000000

	// TIMESTAMP: MODE1 Timestamp
	// Position of COUNT field.
	RTC_MODE1_TIMESTAMP_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	RTC_MODE1_TIMESTAMP_COUNT_Msk = 0xffff

	// TAMPID: Tamper ID
	// Position of TAMPID0 field.
	RTC_MODE1_TAMPID_TAMPID0_Pos = 0x0
	// Bit mask of TAMPID0 field.
	RTC_MODE1_TAMPID_TAMPID0_Msk = 0x1
	// Bit TAMPID0.
	RTC_MODE1_TAMPID_TAMPID0 = 0x1
	// Position of TAMPID1 field.
	RTC_MODE1_TAMPID_TAMPID1_Pos = 0x1
	// Bit mask of TAMPID1 field.
	RTC_MODE1_TAMPID_TAMPID1_Msk = 0x2
	// Bit TAMPID1.
	RTC_MODE1_TAMPID_TAMPID1 = 0x2
	// Position of TAMPID2 field.
	RTC_MODE1_TAMPID_TAMPID2_Pos = 0x2
	// Bit mask of TAMPID2 field.
	RTC_MODE1_TAMPID_TAMPID2_Msk = 0x4
	// Bit TAMPID2.
	RTC_MODE1_TAMPID_TAMPID2 = 0x4
	// Position of TAMPID3 field.
	RTC_MODE1_TAMPID_TAMPID3_Pos = 0x3
	// Bit mask of TAMPID3 field.
	RTC_MODE1_TAMPID_TAMPID3_Msk = 0x8
	// Bit TAMPID3.
	RTC_MODE1_TAMPID_TAMPID3 = 0x8
	// Position of TAMPID4 field.
	RTC_MODE1_TAMPID_TAMPID4_Pos = 0x4
	// Bit mask of TAMPID4 field.
	RTC_MODE1_TAMPID_TAMPID4_Msk = 0x10
	// Bit TAMPID4.
	RTC_MODE1_TAMPID_TAMPID4 = 0x10
	// Position of TAMPEVT field.
	RTC_MODE1_TAMPID_TAMPEVT_Pos = 0x1f
	// Bit mask of TAMPEVT field.
	RTC_MODE1_TAMPID_TAMPEVT_Msk = 0x80000000
	// Bit TAMPEVT.
	RTC_MODE1_TAMPID_TAMPEVT = 0x80000000

	// BKUP: Backup
	// Position of BKUP field.
	RTC_MODE1_BKUP_BKUP_Pos = 0x0
	// Bit mask of BKUP field.
	RTC_MODE1_BKUP_BKUP_Msk = 0xffffffff
)

// Bitfields for RTC_MODE2: Real-Time Counter - MODE2
const (
	// CTRLA: MODE2 Control A
	// Position of SWRST field.
	RTC_MODE2_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	RTC_MODE2_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	RTC_MODE2_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	RTC_MODE2_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	RTC_MODE2_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	RTC_MODE2_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	RTC_MODE2_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	RTC_MODE2_CTRLA_MODE_Msk = 0xc
	// Mode 0: 32-bit Counter
	RTC_MODE2_CTRLA_MODE_COUNT32 = 0x0
	// Mode 1: 16-bit Counter
	RTC_MODE2_CTRLA_MODE_COUNT16 = 0x1
	// Mode 2: Clock/Calendar
	RTC_MODE2_CTRLA_MODE_CLOCK = 0x2
	// Position of CLKREP field.
	RTC_MODE2_CTRLA_CLKREP_Pos = 0x6
	// Bit mask of CLKREP field.
	RTC_MODE2_CTRLA_CLKREP_Msk = 0x40
	// Bit CLKREP.
	RTC_MODE2_CTRLA_CLKREP = 0x40
	// Position of MATCHCLR field.
	RTC_MODE2_CTRLA_MATCHCLR_Pos = 0x7
	// Bit mask of MATCHCLR field.
	RTC_MODE2_CTRLA_MATCHCLR_Msk = 0x80
	// Bit MATCHCLR.
	RTC_MODE2_CTRLA_MATCHCLR = 0x80
	// Position of PRESCALER field.
	RTC_MODE2_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	RTC_MODE2_CTRLA_PRESCALER_Msk = 0xf00
	// CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE2_CTRLA_PRESCALER_OFF = 0x0
	// CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE2_CTRLA_PRESCALER_DIV1 = 0x1
	// CLK_RTC_CNT = GCLK_RTC/2
	RTC_MODE2_CTRLA_PRESCALER_DIV2 = 0x2
	// CLK_RTC_CNT = GCLK_RTC/4
	RTC_MODE2_CTRLA_PRESCALER_DIV4 = 0x3
	// CLK_RTC_CNT = GCLK_RTC/8
	RTC_MODE2_CTRLA_PRESCALER_DIV8 = 0x4
	// CLK_RTC_CNT = GCLK_RTC/16
	RTC_MODE2_CTRLA_PRESCALER_DIV16 = 0x5
	// CLK_RTC_CNT = GCLK_RTC/32
	RTC_MODE2_CTRLA_PRESCALER_DIV32 = 0x6
	// CLK_RTC_CNT = GCLK_RTC/64
	RTC_MODE2_CTRLA_PRESCALER_DIV64 = 0x7
	// CLK_RTC_CNT = GCLK_RTC/128
	RTC_MODE2_CTRLA_PRESCALER_DIV128 = 0x8
	// CLK_RTC_CNT = GCLK_RTC/256
	RTC_MODE2_CTRLA_PRESCALER_DIV256 = 0x9
	// CLK_RTC_CNT = GCLK_RTC/512
	RTC_MODE2_CTRLA_PRESCALER_DIV512 = 0xa
	// CLK_RTC_CNT = GCLK_RTC/1024
	RTC_MODE2_CTRLA_PRESCALER_DIV1024 = 0xb
	// Position of BKTRST field.
	RTC_MODE2_CTRLA_BKTRST_Pos = 0xd
	// Bit mask of BKTRST field.
	RTC_MODE2_CTRLA_BKTRST_Msk = 0x2000
	// Bit BKTRST.
	RTC_MODE2_CTRLA_BKTRST = 0x2000
	// Position of GPTRST field.
	RTC_MODE2_CTRLA_GPTRST_Pos = 0xe
	// Bit mask of GPTRST field.
	RTC_MODE2_CTRLA_GPTRST_Msk = 0x4000
	// Bit GPTRST.
	RTC_MODE2_CTRLA_GPTRST = 0x4000
	// Position of CLOCKSYNC field.
	RTC_MODE2_CTRLA_CLOCKSYNC_Pos = 0xf
	// Bit mask of CLOCKSYNC field.
	RTC_MODE2_CTRLA_CLOCKSYNC_Msk = 0x8000
	// Bit CLOCKSYNC.
	RTC_MODE2_CTRLA_CLOCKSYNC = 0x8000

	// CTRLB: MODE2 Control B
	// Position of GP0EN field.
	RTC_MODE2_CTRLB_GP0EN_Pos = 0x0
	// Bit mask of GP0EN field.
	RTC_MODE2_CTRLB_GP0EN_Msk = 0x1
	// Bit GP0EN.
	RTC_MODE2_CTRLB_GP0EN = 0x1
	// Position of GP2EN field.
	RTC_MODE2_CTRLB_GP2EN_Pos = 0x1
	// Bit mask of GP2EN field.
	RTC_MODE2_CTRLB_GP2EN_Msk = 0x2
	// Bit GP2EN.
	RTC_MODE2_CTRLB_GP2EN = 0x2
	// Position of DEBMAJ field.
	RTC_MODE2_CTRLB_DEBMAJ_Pos = 0x4
	// Bit mask of DEBMAJ field.
	RTC_MODE2_CTRLB_DEBMAJ_Msk = 0x10
	// Bit DEBMAJ.
	RTC_MODE2_CTRLB_DEBMAJ = 0x10
	// Position of DEBASYNC field.
	RTC_MODE2_CTRLB_DEBASYNC_Pos = 0x5
	// Bit mask of DEBASYNC field.
	RTC_MODE2_CTRLB_DEBASYNC_Msk = 0x20
	// Bit DEBASYNC.
	RTC_MODE2_CTRLB_DEBASYNC = 0x20
	// Position of RTCOUT field.
	RTC_MODE2_CTRLB_RTCOUT_Pos = 0x6
	// Bit mask of RTCOUT field.
	RTC_MODE2_CTRLB_RTCOUT_Msk = 0x40
	// Bit RTCOUT.
	RTC_MODE2_CTRLB_RTCOUT = 0x40
	// Position of DMAEN field.
	RTC_MODE2_CTRLB_DMAEN_Pos = 0x7
	// Bit mask of DMAEN field.
	RTC_MODE2_CTRLB_DMAEN_Msk = 0x80
	// Bit DMAEN.
	RTC_MODE2_CTRLB_DMAEN = 0x80
	// Position of DEBF field.
	RTC_MODE2_CTRLB_DEBF_Pos = 0x8
	// Bit mask of DEBF field.
	RTC_MODE2_CTRLB_DEBF_Msk = 0x700
	// CLK_RTC_DEB = CLK_RTC/2
	RTC_MODE2_CTRLB_DEBF_DIV2 = 0x0
	// CLK_RTC_DEB = CLK_RTC/4
	RTC_MODE2_CTRLB_DEBF_DIV4 = 0x1
	// CLK_RTC_DEB = CLK_RTC/8
	RTC_MODE2_CTRLB_DEBF_DIV8 = 0x2
	// CLK_RTC_DEB = CLK_RTC/16
	RTC_MODE2_CTRLB_DEBF_DIV16 = 0x3
	// CLK_RTC_DEB = CLK_RTC/32
	RTC_MODE2_CTRLB_DEBF_DIV32 = 0x4
	// CLK_RTC_DEB = CLK_RTC/64
	RTC_MODE2_CTRLB_DEBF_DIV64 = 0x5
	// CLK_RTC_DEB = CLK_RTC/128
	RTC_MODE2_CTRLB_DEBF_DIV128 = 0x6
	// CLK_RTC_DEB = CLK_RTC/256
	RTC_MODE2_CTRLB_DEBF_DIV256 = 0x7
	// Position of ACTF field.
	RTC_MODE2_CTRLB_ACTF_Pos = 0xc
	// Bit mask of ACTF field.
	RTC_MODE2_CTRLB_ACTF_Msk = 0x7000
	// CLK_RTC_OUT = CLK_RTC/2
	RTC_MODE2_CTRLB_ACTF_DIV2 = 0x0
	// CLK_RTC_OUT = CLK_RTC/4
	RTC_MODE2_CTRLB_ACTF_DIV4 = 0x1
	// CLK_RTC_OUT = CLK_RTC/8
	RTC_MODE2_CTRLB_ACTF_DIV8 = 0x2
	// CLK_RTC_OUT = CLK_RTC/16
	RTC_MODE2_CTRLB_ACTF_DIV16 = 0x3
	// CLK_RTC_OUT = CLK_RTC/32
	RTC_MODE2_CTRLB_ACTF_DIV32 = 0x4
	// CLK_RTC_OUT = CLK_RTC/64
	RTC_MODE2_CTRLB_ACTF_DIV64 = 0x5
	// CLK_RTC_OUT = CLK_RTC/128
	RTC_MODE2_CTRLB_ACTF_DIV128 = 0x6
	// CLK_RTC_OUT = CLK_RTC/256
	RTC_MODE2_CTRLB_ACTF_DIV256 = 0x7

	// EVCTRL: MODE2 Event Control
	// Position of PEREO0 field.
	RTC_MODE2_EVCTRL_PEREO0_Pos = 0x0
	// Bit mask of PEREO0 field.
	RTC_MODE2_EVCTRL_PEREO0_Msk = 0x1
	// Bit PEREO0.
	RTC_MODE2_EVCTRL_PEREO0 = 0x1
	// Position of PEREO1 field.
	RTC_MODE2_EVCTRL_PEREO1_Pos = 0x1
	// Bit mask of PEREO1 field.
	RTC_MODE2_EVCTRL_PEREO1_Msk = 0x2
	// Bit PEREO1.
	RTC_MODE2_EVCTRL_PEREO1 = 0x2
	// Position of PEREO2 field.
	RTC_MODE2_EVCTRL_PEREO2_Pos = 0x2
	// Bit mask of PEREO2 field.
	RTC_MODE2_EVCTRL_PEREO2_Msk = 0x4
	// Bit PEREO2.
	RTC_MODE2_EVCTRL_PEREO2 = 0x4
	// Position of PEREO3 field.
	RTC_MODE2_EVCTRL_PEREO3_Pos = 0x3
	// Bit mask of PEREO3 field.
	RTC_MODE2_EVCTRL_PEREO3_Msk = 0x8
	// Bit PEREO3.
	RTC_MODE2_EVCTRL_PEREO3 = 0x8
	// Position of PEREO4 field.
	RTC_MODE2_EVCTRL_PEREO4_Pos = 0x4
	// Bit mask of PEREO4 field.
	RTC_MODE2_EVCTRL_PEREO4_Msk = 0x10
	// Bit PEREO4.
	RTC_MODE2_EVCTRL_PEREO4 = 0x10
	// Position of PEREO5 field.
	RTC_MODE2_EVCTRL_PEREO5_Pos = 0x5
	// Bit mask of PEREO5 field.
	RTC_MODE2_EVCTRL_PEREO5_Msk = 0x20
	// Bit PEREO5.
	RTC_MODE2_EVCTRL_PEREO5 = 0x20
	// Position of PEREO6 field.
	RTC_MODE2_EVCTRL_PEREO6_Pos = 0x6
	// Bit mask of PEREO6 field.
	RTC_MODE2_EVCTRL_PEREO6_Msk = 0x40
	// Bit PEREO6.
	RTC_MODE2_EVCTRL_PEREO6 = 0x40
	// Position of PEREO7 field.
	RTC_MODE2_EVCTRL_PEREO7_Pos = 0x7
	// Bit mask of PEREO7 field.
	RTC_MODE2_EVCTRL_PEREO7_Msk = 0x80
	// Bit PEREO7.
	RTC_MODE2_EVCTRL_PEREO7 = 0x80
	// Position of ALARMEO0 field.
	RTC_MODE2_EVCTRL_ALARMEO0_Pos = 0x8
	// Bit mask of ALARMEO0 field.
	RTC_MODE2_EVCTRL_ALARMEO0_Msk = 0x100
	// Bit ALARMEO0.
	RTC_MODE2_EVCTRL_ALARMEO0 = 0x100
	// Position of ALARMEO1 field.
	RTC_MODE2_EVCTRL_ALARMEO1_Pos = 0x9
	// Bit mask of ALARMEO1 field.
	RTC_MODE2_EVCTRL_ALARMEO1_Msk = 0x200
	// Bit ALARMEO1.
	RTC_MODE2_EVCTRL_ALARMEO1 = 0x200
	// Position of TAMPEREO field.
	RTC_MODE2_EVCTRL_TAMPEREO_Pos = 0xe
	// Bit mask of TAMPEREO field.
	RTC_MODE2_EVCTRL_TAMPEREO_Msk = 0x4000
	// Bit TAMPEREO.
	RTC_MODE2_EVCTRL_TAMPEREO = 0x4000
	// Position of OVFEO field.
	RTC_MODE2_EVCTRL_OVFEO_Pos = 0xf
	// Bit mask of OVFEO field.
	RTC_MODE2_EVCTRL_OVFEO_Msk = 0x8000
	// Bit OVFEO.
	RTC_MODE2_EVCTRL_OVFEO = 0x8000
	// Position of TAMPEVEI field.
	RTC_MODE2_EVCTRL_TAMPEVEI_Pos = 0x10
	// Bit mask of TAMPEVEI field.
	RTC_MODE2_EVCTRL_TAMPEVEI_Msk = 0x10000
	// Bit TAMPEVEI.
	RTC_MODE2_EVCTRL_TAMPEVEI = 0x10000

	// INTENCLR: MODE2 Interrupt Enable Clear
	// Position of PER0 field.
	RTC_MODE2_INTENCLR_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE2_INTENCLR_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE2_INTENCLR_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE2_INTENCLR_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE2_INTENCLR_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE2_INTENCLR_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE2_INTENCLR_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE2_INTENCLR_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE2_INTENCLR_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE2_INTENCLR_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE2_INTENCLR_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE2_INTENCLR_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE2_INTENCLR_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE2_INTENCLR_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE2_INTENCLR_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE2_INTENCLR_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE2_INTENCLR_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE2_INTENCLR_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE2_INTENCLR_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE2_INTENCLR_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE2_INTENCLR_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE2_INTENCLR_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE2_INTENCLR_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE2_INTENCLR_PER7 = 0x80
	// Position of ALARM0 field.
	RTC_MODE2_INTENCLR_ALARM0_Pos = 0x8
	// Bit mask of ALARM0 field.
	RTC_MODE2_INTENCLR_ALARM0_Msk = 0x100
	// Bit ALARM0.
	RTC_MODE2_INTENCLR_ALARM0 = 0x100
	// Position of ALARM1 field.
	RTC_MODE2_INTENCLR_ALARM1_Pos = 0x9
	// Bit mask of ALARM1 field.
	RTC_MODE2_INTENCLR_ALARM1_Msk = 0x200
	// Bit ALARM1.
	RTC_MODE2_INTENCLR_ALARM1 = 0x200
	// Position of TAMPER field.
	RTC_MODE2_INTENCLR_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE2_INTENCLR_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE2_INTENCLR_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE2_INTENCLR_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE2_INTENCLR_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE2_INTENCLR_OVF = 0x8000

	// INTENSET: MODE2 Interrupt Enable Set
	// Position of PER0 field.
	RTC_MODE2_INTENSET_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE2_INTENSET_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE2_INTENSET_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE2_INTENSET_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE2_INTENSET_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE2_INTENSET_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE2_INTENSET_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE2_INTENSET_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE2_INTENSET_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE2_INTENSET_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE2_INTENSET_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE2_INTENSET_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE2_INTENSET_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE2_INTENSET_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE2_INTENSET_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE2_INTENSET_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE2_INTENSET_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE2_INTENSET_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE2_INTENSET_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE2_INTENSET_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE2_INTENSET_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE2_INTENSET_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE2_INTENSET_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE2_INTENSET_PER7 = 0x80
	// Position of ALARM0 field.
	RTC_MODE2_INTENSET_ALARM0_Pos = 0x8
	// Bit mask of ALARM0 field.
	RTC_MODE2_INTENSET_ALARM0_Msk = 0x100
	// Bit ALARM0.
	RTC_MODE2_INTENSET_ALARM0 = 0x100
	// Position of ALARM1 field.
	RTC_MODE2_INTENSET_ALARM1_Pos = 0x9
	// Bit mask of ALARM1 field.
	RTC_MODE2_INTENSET_ALARM1_Msk = 0x200
	// Bit ALARM1.
	RTC_MODE2_INTENSET_ALARM1 = 0x200
	// Position of TAMPER field.
	RTC_MODE2_INTENSET_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE2_INTENSET_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE2_INTENSET_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE2_INTENSET_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE2_INTENSET_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE2_INTENSET_OVF = 0x8000

	// INTFLAG: MODE2 Interrupt Flag Status and Clear
	// Position of PER0 field.
	RTC_MODE2_INTFLAG_PER0_Pos = 0x0
	// Bit mask of PER0 field.
	RTC_MODE2_INTFLAG_PER0_Msk = 0x1
	// Bit PER0.
	RTC_MODE2_INTFLAG_PER0 = 0x1
	// Position of PER1 field.
	RTC_MODE2_INTFLAG_PER1_Pos = 0x1
	// Bit mask of PER1 field.
	RTC_MODE2_INTFLAG_PER1_Msk = 0x2
	// Bit PER1.
	RTC_MODE2_INTFLAG_PER1 = 0x2
	// Position of PER2 field.
	RTC_MODE2_INTFLAG_PER2_Pos = 0x2
	// Bit mask of PER2 field.
	RTC_MODE2_INTFLAG_PER2_Msk = 0x4
	// Bit PER2.
	RTC_MODE2_INTFLAG_PER2 = 0x4
	// Position of PER3 field.
	RTC_MODE2_INTFLAG_PER3_Pos = 0x3
	// Bit mask of PER3 field.
	RTC_MODE2_INTFLAG_PER3_Msk = 0x8
	// Bit PER3.
	RTC_MODE2_INTFLAG_PER3 = 0x8
	// Position of PER4 field.
	RTC_MODE2_INTFLAG_PER4_Pos = 0x4
	// Bit mask of PER4 field.
	RTC_MODE2_INTFLAG_PER4_Msk = 0x10
	// Bit PER4.
	RTC_MODE2_INTFLAG_PER4 = 0x10
	// Position of PER5 field.
	RTC_MODE2_INTFLAG_PER5_Pos = 0x5
	// Bit mask of PER5 field.
	RTC_MODE2_INTFLAG_PER5_Msk = 0x20
	// Bit PER5.
	RTC_MODE2_INTFLAG_PER5 = 0x20
	// Position of PER6 field.
	RTC_MODE2_INTFLAG_PER6_Pos = 0x6
	// Bit mask of PER6 field.
	RTC_MODE2_INTFLAG_PER6_Msk = 0x40
	// Bit PER6.
	RTC_MODE2_INTFLAG_PER6 = 0x40
	// Position of PER7 field.
	RTC_MODE2_INTFLAG_PER7_Pos = 0x7
	// Bit mask of PER7 field.
	RTC_MODE2_INTFLAG_PER7_Msk = 0x80
	// Bit PER7.
	RTC_MODE2_INTFLAG_PER7 = 0x80
	// Position of ALARM0 field.
	RTC_MODE2_INTFLAG_ALARM0_Pos = 0x8
	// Bit mask of ALARM0 field.
	RTC_MODE2_INTFLAG_ALARM0_Msk = 0x100
	// Bit ALARM0.
	RTC_MODE2_INTFLAG_ALARM0 = 0x100
	// Position of ALARM1 field.
	RTC_MODE2_INTFLAG_ALARM1_Pos = 0x9
	// Bit mask of ALARM1 field.
	RTC_MODE2_INTFLAG_ALARM1_Msk = 0x200
	// Bit ALARM1.
	RTC_MODE2_INTFLAG_ALARM1 = 0x200
	// Position of TAMPER field.
	RTC_MODE2_INTFLAG_TAMPER_Pos = 0xe
	// Bit mask of TAMPER field.
	RTC_MODE2_INTFLAG_TAMPER_Msk = 0x4000
	// Bit TAMPER.
	RTC_MODE2_INTFLAG_TAMPER = 0x4000
	// Position of OVF field.
	RTC_MODE2_INTFLAG_OVF_Pos = 0xf
	// Bit mask of OVF field.
	RTC_MODE2_INTFLAG_OVF_Msk = 0x8000
	// Bit OVF.
	RTC_MODE2_INTFLAG_OVF = 0x8000

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	RTC_MODE2_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	RTC_MODE2_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	RTC_MODE2_DBGCTRL_DBGRUN = 0x1

	// SYNCBUSY: MODE2 Synchronization Busy Status
	// Position of SWRST field.
	RTC_MODE2_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	RTC_MODE2_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	RTC_MODE2_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	RTC_MODE2_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	RTC_MODE2_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	RTC_MODE2_SYNCBUSY_ENABLE = 0x2
	// Position of FREQCORR field.
	RTC_MODE2_SYNCBUSY_FREQCORR_Pos = 0x2
	// Bit mask of FREQCORR field.
	RTC_MODE2_SYNCBUSY_FREQCORR_Msk = 0x4
	// Bit FREQCORR.
	RTC_MODE2_SYNCBUSY_FREQCORR = 0x4
	// Position of CLOCK field.
	RTC_MODE2_SYNCBUSY_CLOCK_Pos = 0x3
	// Bit mask of CLOCK field.
	RTC_MODE2_SYNCBUSY_CLOCK_Msk = 0x8
	// Bit CLOCK.
	RTC_MODE2_SYNCBUSY_CLOCK = 0x8
	// Position of ALARM0 field.
	RTC_MODE2_SYNCBUSY_ALARM0_Pos = 0x5
	// Bit mask of ALARM0 field.
	RTC_MODE2_SYNCBUSY_ALARM0_Msk = 0x20
	// Bit ALARM0.
	RTC_MODE2_SYNCBUSY_ALARM0 = 0x20
	// Position of ALARM1 field.
	RTC_MODE2_SYNCBUSY_ALARM1_Pos = 0x6
	// Bit mask of ALARM1 field.
	RTC_MODE2_SYNCBUSY_ALARM1_Msk = 0x40
	// Bit ALARM1.
	RTC_MODE2_SYNCBUSY_ALARM1 = 0x40
	// Position of MASK0 field.
	RTC_MODE2_SYNCBUSY_MASK0_Pos = 0xb
	// Bit mask of MASK0 field.
	RTC_MODE2_SYNCBUSY_MASK0_Msk = 0x800
	// Bit MASK0.
	RTC_MODE2_SYNCBUSY_MASK0 = 0x800
	// Position of MASK1 field.
	RTC_MODE2_SYNCBUSY_MASK1_Pos = 0xc
	// Bit mask of MASK1 field.
	RTC_MODE2_SYNCBUSY_MASK1_Msk = 0x1000
	// Bit MASK1.
	RTC_MODE2_SYNCBUSY_MASK1 = 0x1000
	// Position of CLOCKSYNC field.
	RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos = 0xf
	// Bit mask of CLOCKSYNC field.
	RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk = 0x8000
	// Bit CLOCKSYNC.
	RTC_MODE2_SYNCBUSY_CLOCKSYNC = 0x8000
	// Position of GP0 field.
	RTC_MODE2_SYNCBUSY_GP0_Pos = 0x10
	// Bit mask of GP0 field.
	RTC_MODE2_SYNCBUSY_GP0_Msk = 0x10000
	// Bit GP0.
	RTC_MODE2_SYNCBUSY_GP0 = 0x10000
	// Position of GP1 field.
	RTC_MODE2_SYNCBUSY_GP1_Pos = 0x11
	// Bit mask of GP1 field.
	RTC_MODE2_SYNCBUSY_GP1_Msk = 0x20000
	// Bit GP1.
	RTC_MODE2_SYNCBUSY_GP1 = 0x20000
	// Position of GP2 field.
	RTC_MODE2_SYNCBUSY_GP2_Pos = 0x12
	// Bit mask of GP2 field.
	RTC_MODE2_SYNCBUSY_GP2_Msk = 0x40000
	// Bit GP2.
	RTC_MODE2_SYNCBUSY_GP2 = 0x40000
	// Position of GP3 field.
	RTC_MODE2_SYNCBUSY_GP3_Pos = 0x13
	// Bit mask of GP3 field.
	RTC_MODE2_SYNCBUSY_GP3_Msk = 0x80000
	// Bit GP3.
	RTC_MODE2_SYNCBUSY_GP3 = 0x80000

	// FREQCORR: Frequency Correction
	// Position of VALUE field.
	RTC_MODE2_FREQCORR_VALUE_Pos = 0x0
	// Bit mask of VALUE field.
	RTC_MODE2_FREQCORR_VALUE_Msk = 0x7f
	// Position of SIGN field.
	RTC_MODE2_FREQCORR_SIGN_Pos = 0x7
	// Bit mask of SIGN field.
	RTC_MODE2_FREQCORR_SIGN_Msk = 0x80
	// Bit SIGN.
	RTC_MODE2_FREQCORR_SIGN = 0x80

	// CLOCK: MODE2 Clock Value
	// Position of SECOND field.
	RTC_MODE2_CLOCK_SECOND_Pos = 0x0
	// Bit mask of SECOND field.
	RTC_MODE2_CLOCK_SECOND_Msk = 0x3f
	// Position of MINUTE field.
	RTC_MODE2_CLOCK_MINUTE_Pos = 0x6
	// Bit mask of MINUTE field.
	RTC_MODE2_CLOCK_MINUTE_Msk = 0xfc0
	// Position of HOUR field.
	RTC_MODE2_CLOCK_HOUR_Pos = 0xc
	// Bit mask of HOUR field.
	RTC_MODE2_CLOCK_HOUR_Msk = 0x1f000
	// AM when CLKREP in 12-hour
	RTC_MODE2_CLOCK_HOUR_AM = 0x0
	// PM when CLKREP in 12-hour
	RTC_MODE2_CLOCK_HOUR_PM = 0x10
	// Position of DAY field.
	RTC_MODE2_CLOCK_DAY_Pos = 0x11
	// Bit mask of DAY field.
	RTC_MODE2_CLOCK_DAY_Msk = 0x3e0000
	// Position of MONTH field.
	RTC_MODE2_CLOCK_MONTH_Pos = 0x16
	// Bit mask of MONTH field.
	RTC_MODE2_CLOCK_MONTH_Msk = 0x3c00000
	// Position of YEAR field.
	RTC_MODE2_CLOCK_YEAR_Pos = 0x1a
	// Bit mask of YEAR field.
	RTC_MODE2_CLOCK_YEAR_Msk = 0xfc000000

	// ALARM0: MODE2_ALARM Alarm n Value
	// Position of SECOND field.
	RTC_MODE2_ALARM0_SECOND_Pos = 0x0
	// Bit mask of SECOND field.
	RTC_MODE2_ALARM0_SECOND_Msk = 0x3f
	// Position of MINUTE field.
	RTC_MODE2_ALARM0_MINUTE_Pos = 0x6
	// Bit mask of MINUTE field.
	RTC_MODE2_ALARM0_MINUTE_Msk = 0xfc0
	// Position of HOUR field.
	RTC_MODE2_ALARM0_HOUR_Pos = 0xc
	// Bit mask of HOUR field.
	RTC_MODE2_ALARM0_HOUR_Msk = 0x1f000
	// Morning hour
	RTC_MODE2_ALARM0_HOUR_AM = 0x0
	// Afternoon hour
	RTC_MODE2_ALARM0_HOUR_PM = 0x10
	// Position of DAY field.
	RTC_MODE2_ALARM0_DAY_Pos = 0x11
	// Bit mask of DAY field.
	RTC_MODE2_ALARM0_DAY_Msk = 0x3e0000
	// Position of MONTH field.
	RTC_MODE2_ALARM0_MONTH_Pos = 0x16
	// Bit mask of MONTH field.
	RTC_MODE2_ALARM0_MONTH_Msk = 0x3c00000
	// Position of YEAR field.
	RTC_MODE2_ALARM0_YEAR_Pos = 0x1a
	// Bit mask of YEAR field.
	RTC_MODE2_ALARM0_YEAR_Msk = 0xfc000000

	// MASK0: MODE2_ALARM Alarm n Mask
	// Position of SEL field.
	RTC_MODE2_MASK0_SEL_Pos = 0x0
	// Bit mask of SEL field.
	RTC_MODE2_MASK0_SEL_Msk = 0x7
	// Alarm Disabled
	RTC_MODE2_MASK0_SEL_OFF = 0x0
	// Match seconds only
	RTC_MODE2_MASK0_SEL_SS = 0x1
	// Match seconds and minutes only
	RTC_MODE2_MASK0_SEL_MMSS = 0x2
	// Match seconds, minutes, and hours only
	RTC_MODE2_MASK0_SEL_HHMMSS = 0x3
	// Match seconds, minutes, hours, and days only
	RTC_MODE2_MASK0_SEL_DDHHMMSS = 0x4
	// Match seconds, minutes, hours, days, and months only
	RTC_MODE2_MASK0_SEL_MMDDHHMMSS = 0x5
	// Match seconds, minutes, hours, days, months, and years
	RTC_MODE2_MASK0_SEL_YYMMDDHHMMSS = 0x6

	// ALARM1: MODE2_ALARM Alarm n Value
	// Position of SECOND field.
	RTC_MODE2_ALARM1_SECOND_Pos = 0x0
	// Bit mask of SECOND field.
	RTC_MODE2_ALARM1_SECOND_Msk = 0x3f
	// Position of MINUTE field.
	RTC_MODE2_ALARM1_MINUTE_Pos = 0x6
	// Bit mask of MINUTE field.
	RTC_MODE2_ALARM1_MINUTE_Msk = 0xfc0
	// Position of HOUR field.
	RTC_MODE2_ALARM1_HOUR_Pos = 0xc
	// Bit mask of HOUR field.
	RTC_MODE2_ALARM1_HOUR_Msk = 0x1f000
	// Morning hour
	RTC_MODE2_ALARM1_HOUR_AM = 0x0
	// Afternoon hour
	RTC_MODE2_ALARM1_HOUR_PM = 0x10
	// Position of DAY field.
	RTC_MODE2_ALARM1_DAY_Pos = 0x11
	// Bit mask of DAY field.
	RTC_MODE2_ALARM1_DAY_Msk = 0x3e0000
	// Position of MONTH field.
	RTC_MODE2_ALARM1_MONTH_Pos = 0x16
	// Bit mask of MONTH field.
	RTC_MODE2_ALARM1_MONTH_Msk = 0x3c00000
	// Position of YEAR field.
	RTC_MODE2_ALARM1_YEAR_Pos = 0x1a
	// Bit mask of YEAR field.
	RTC_MODE2_ALARM1_YEAR_Msk = 0xfc000000

	// MASK1: MODE2_ALARM Alarm n Mask
	// Position of SEL field.
	RTC_MODE2_MASK1_SEL_Pos = 0x0
	// Bit mask of SEL field.
	RTC_MODE2_MASK1_SEL_Msk = 0x7
	// Alarm Disabled
	RTC_MODE2_MASK1_SEL_OFF = 0x0
	// Match seconds only
	RTC_MODE2_MASK1_SEL_SS = 0x1
	// Match seconds and minutes only
	RTC_MODE2_MASK1_SEL_MMSS = 0x2
	// Match seconds, minutes, and hours only
	RTC_MODE2_MASK1_SEL_HHMMSS = 0x3
	// Match seconds, minutes, hours, and days only
	RTC_MODE2_MASK1_SEL_DDHHMMSS = 0x4
	// Match seconds, minutes, hours, days, and months only
	RTC_MODE2_MASK1_SEL_MMDDHHMMSS = 0x5
	// Match seconds, minutes, hours, days, months, and years
	RTC_MODE2_MASK1_SEL_YYMMDDHHMMSS = 0x6

	// GP: General Purpose
	// Position of GP field.
	RTC_MODE2_GP_GP_Pos = 0x0
	// Bit mask of GP field.
	RTC_MODE2_GP_GP_Msk = 0xffffffff

	// TAMPCTRL: Tamper Control
	// Position of IN0ACT field.
	RTC_MODE2_TAMPCTRL_IN0ACT_Pos = 0x0
	// Bit mask of IN0ACT field.
	RTC_MODE2_TAMPCTRL_IN0ACT_Msk = 0x3
	// Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN0ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN0ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE2_TAMPCTRL_IN0ACT_CAPTURE = 0x2
	// Compare IN0 to OUT
	RTC_MODE2_TAMPCTRL_IN0ACT_ACTL = 0x3
	// Position of IN1ACT field.
	RTC_MODE2_TAMPCTRL_IN1ACT_Pos = 0x2
	// Bit mask of IN1ACT field.
	RTC_MODE2_TAMPCTRL_IN1ACT_Msk = 0xc
	// Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN1ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN1ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE2_TAMPCTRL_IN1ACT_CAPTURE = 0x2
	// Compare IN1 to OUT
	RTC_MODE2_TAMPCTRL_IN1ACT_ACTL = 0x3
	// Position of IN2ACT field.
	RTC_MODE2_TAMPCTRL_IN2ACT_Pos = 0x4
	// Bit mask of IN2ACT field.
	RTC_MODE2_TAMPCTRL_IN2ACT_Msk = 0x30
	// Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN2ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN2ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE2_TAMPCTRL_IN2ACT_CAPTURE = 0x2
	// Compare IN2 to OUT
	RTC_MODE2_TAMPCTRL_IN2ACT_ACTL = 0x3
	// Position of IN3ACT field.
	RTC_MODE2_TAMPCTRL_IN3ACT_Pos = 0x6
	// Bit mask of IN3ACT field.
	RTC_MODE2_TAMPCTRL_IN3ACT_Msk = 0xc0
	// Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN3ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN3ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE2_TAMPCTRL_IN3ACT_CAPTURE = 0x2
	// Compare IN3 to OUT
	RTC_MODE2_TAMPCTRL_IN3ACT_ACTL = 0x3
	// Position of IN4ACT field.
	RTC_MODE2_TAMPCTRL_IN4ACT_Pos = 0x8
	// Bit mask of IN4ACT field.
	RTC_MODE2_TAMPCTRL_IN4ACT_Msk = 0x300
	// Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN4ACT_OFF = 0x0
	// Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN4ACT_WAKE = 0x1
	// Capture timestamp
	RTC_MODE2_TAMPCTRL_IN4ACT_CAPTURE = 0x2
	// Compare IN4 to OUT
	RTC_MODE2_TAMPCTRL_IN4ACT_ACTL = 0x3
	// Position of TAMLVL0 field.
	RTC_MODE2_TAMPCTRL_TAMLVL0_Pos = 0x10
	// Bit mask of TAMLVL0 field.
	RTC_MODE2_TAMPCTRL_TAMLVL0_Msk = 0x10000
	// Bit TAMLVL0.
	RTC_MODE2_TAMPCTRL_TAMLVL0 = 0x10000
	// Position of TAMLVL1 field.
	RTC_MODE2_TAMPCTRL_TAMLVL1_Pos = 0x11
	// Bit mask of TAMLVL1 field.
	RTC_MODE2_TAMPCTRL_TAMLVL1_Msk = 0x20000
	// Bit TAMLVL1.
	RTC_MODE2_TAMPCTRL_TAMLVL1 = 0x20000
	// Position of TAMLVL2 field.
	RTC_MODE2_TAMPCTRL_TAMLVL2_Pos = 0x12
	// Bit mask of TAMLVL2 field.
	RTC_MODE2_TAMPCTRL_TAMLVL2_Msk = 0x40000
	// Bit TAMLVL2.
	RTC_MODE2_TAMPCTRL_TAMLVL2 = 0x40000
	// Position of TAMLVL3 field.
	RTC_MODE2_TAMPCTRL_TAMLVL3_Pos = 0x13
	// Bit mask of TAMLVL3 field.
	RTC_MODE2_TAMPCTRL_TAMLVL3_Msk = 0x80000
	// Bit TAMLVL3.
	RTC_MODE2_TAMPCTRL_TAMLVL3 = 0x80000
	// Position of TAMLVL4 field.
	RTC_MODE2_TAMPCTRL_TAMLVL4_Pos = 0x14
	// Bit mask of TAMLVL4 field.
	RTC_MODE2_TAMPCTRL_TAMLVL4_Msk = 0x100000
	// Bit TAMLVL4.
	RTC_MODE2_TAMPCTRL_TAMLVL4 = 0x100000
	// Position of DEBNC0 field.
	RTC_MODE2_TAMPCTRL_DEBNC0_Pos = 0x18
	// Bit mask of DEBNC0 field.
	RTC_MODE2_TAMPCTRL_DEBNC0_Msk = 0x1000000
	// Bit DEBNC0.
	RTC_MODE2_TAMPCTRL_DEBNC0 = 0x1000000
	// Position of DEBNC1 field.
	RTC_MODE2_TAMPCTRL_DEBNC1_Pos = 0x19
	// Bit mask of DEBNC1 field.
	RTC_MODE2_TAMPCTRL_DEBNC1_Msk = 0x2000000
	// Bit DEBNC1.
	RTC_MODE2_TAMPCTRL_DEBNC1 = 0x2000000
	// Position of DEBNC2 field.
	RTC_MODE2_TAMPCTRL_DEBNC2_Pos = 0x1a
	// Bit mask of DEBNC2 field.
	RTC_MODE2_TAMPCTRL_DEBNC2_Msk = 0x4000000
	// Bit DEBNC2.
	RTC_MODE2_TAMPCTRL_DEBNC2 = 0x4000000
	// Position of DEBNC3 field.
	RTC_MODE2_TAMPCTRL_DEBNC3_Pos = 0x1b
	// Bit mask of DEBNC3 field.
	RTC_MODE2_TAMPCTRL_DEBNC3_Msk = 0x8000000
	// Bit DEBNC3.
	RTC_MODE2_TAMPCTRL_DEBNC3 = 0x8000000
	// Position of DEBNC4 field.
	RTC_MODE2_TAMPCTRL_DEBNC4_Pos = 0x1c
	// Bit mask of DEBNC4 field.
	RTC_MODE2_TAMPCTRL_DEBNC4_Msk = 0x10000000
	// Bit DEBNC4.
	RTC_MODE2_TAMPCTRL_DEBNC4 = 0x10000000

	// TIMESTAMP: MODE2 Timestamp
	// Position of SECOND field.
	RTC_MODE2_TIMESTAMP_SECOND_Pos = 0x0
	// Bit mask of SECOND field.
	RTC_MODE2_TIMESTAMP_SECOND_Msk = 0x3f
	// Position of MINUTE field.
	RTC_MODE2_TIMESTAMP_MINUTE_Pos = 0x6
	// Bit mask of MINUTE field.
	RTC_MODE2_TIMESTAMP_MINUTE_Msk = 0xfc0
	// Position of HOUR field.
	RTC_MODE2_TIMESTAMP_HOUR_Pos = 0xc
	// Bit mask of HOUR field.
	RTC_MODE2_TIMESTAMP_HOUR_Msk = 0x1f000
	// AM when CLKREP in 12-hour
	RTC_MODE2_TIMESTAMP_HOUR_AM = 0x0
	// PM when CLKREP in 12-hour
	RTC_MODE2_TIMESTAMP_HOUR_PM = 0x10
	// Position of DAY field.
	RTC_MODE2_TIMESTAMP_DAY_Pos = 0x11
	// Bit mask of DAY field.
	RTC_MODE2_TIMESTAMP_DAY_Msk = 0x3e0000
	// Position of MONTH field.
	RTC_MODE2_TIMESTAMP_MONTH_Pos = 0x16
	// Bit mask of MONTH field.
	RTC_MODE2_TIMESTAMP_MONTH_Msk = 0x3c00000
	// Position of YEAR field.
	RTC_MODE2_TIMESTAMP_YEAR_Pos = 0x1a
	// Bit mask of YEAR field.
	RTC_MODE2_TIMESTAMP_YEAR_Msk = 0xfc000000

	// TAMPID: Tamper ID
	// Position of TAMPID0 field.
	RTC_MODE2_TAMPID_TAMPID0_Pos = 0x0
	// Bit mask of TAMPID0 field.
	RTC_MODE2_TAMPID_TAMPID0_Msk = 0x1
	// Bit TAMPID0.
	RTC_MODE2_TAMPID_TAMPID0 = 0x1
	// Position of TAMPID1 field.
	RTC_MODE2_TAMPID_TAMPID1_Pos = 0x1
	// Bit mask of TAMPID1 field.
	RTC_MODE2_TAMPID_TAMPID1_Msk = 0x2
	// Bit TAMPID1.
	RTC_MODE2_TAMPID_TAMPID1 = 0x2
	// Position of TAMPID2 field.
	RTC_MODE2_TAMPID_TAMPID2_Pos = 0x2
	// Bit mask of TAMPID2 field.
	RTC_MODE2_TAMPID_TAMPID2_Msk = 0x4
	// Bit TAMPID2.
	RTC_MODE2_TAMPID_TAMPID2 = 0x4
	// Position of TAMPID3 field.
	RTC_MODE2_TAMPID_TAMPID3_Pos = 0x3
	// Bit mask of TAMPID3 field.
	RTC_MODE2_TAMPID_TAMPID3_Msk = 0x8
	// Bit TAMPID3.
	RTC_MODE2_TAMPID_TAMPID3 = 0x8
	// Position of TAMPID4 field.
	RTC_MODE2_TAMPID_TAMPID4_Pos = 0x4
	// Bit mask of TAMPID4 field.
	RTC_MODE2_TAMPID_TAMPID4_Msk = 0x10
	// Bit TAMPID4.
	RTC_MODE2_TAMPID_TAMPID4 = 0x10
	// Position of TAMPEVT field.
	RTC_MODE2_TAMPID_TAMPEVT_Pos = 0x1f
	// Bit mask of TAMPEVT field.
	RTC_MODE2_TAMPID_TAMPEVT_Msk = 0x80000000
	// Bit TAMPEVT.
	RTC_MODE2_TAMPID_TAMPEVT = 0x80000000

	// BKUP: Backup
	// Position of BKUP field.
	RTC_MODE2_BKUP_BKUP_Pos = 0x0
	// Bit mask of BKUP field.
	RTC_MODE2_BKUP_BKUP_Msk = 0xffffffff
)

// Bitfields for SDHC0: SD/MMC Host Controller
const (
	// SSAR: SDMA System Address / Argument 2
	// Position of ADDR field.
	SDHC_SSAR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	SDHC_SSAR_ADDR_Msk = 0xffffffff

	// SSAR_CMD23_MODE: SDMA System Address / Argument 2
	// Position of ARG2 field.
	SDHC_SSAR_CMD23_MODE_ARG2_Pos = 0x0
	// Bit mask of ARG2 field.
	SDHC_SSAR_CMD23_MODE_ARG2_Msk = 0xffffffff

	// BSR: Block Size
	// Position of BLOCKSIZE field.
	SDHC_BSR_BLOCKSIZE_Pos = 0x0
	// Bit mask of BLOCKSIZE field.
	SDHC_BSR_BLOCKSIZE_Msk = 0x3ff
	// Position of BOUNDARY field.
	SDHC_BSR_BOUNDARY_Pos = 0xc
	// Bit mask of BOUNDARY field.
	SDHC_BSR_BOUNDARY_Msk = 0x7000
	// 4k bytes
	SDHC_BSR_BOUNDARY_4K = 0x0
	// 8k bytes
	SDHC_BSR_BOUNDARY_8K = 0x1
	// 16k bytes
	SDHC_BSR_BOUNDARY_16K = 0x2
	// 32k bytes
	SDHC_BSR_BOUNDARY_32K = 0x3
	// 64k bytes
	SDHC_BSR_BOUNDARY_64K = 0x4
	// 128k bytes
	SDHC_BSR_BOUNDARY_128K = 0x5
	// 256k bytes
	SDHC_BSR_BOUNDARY_256K = 0x6
	// 512k bytes
	SDHC_BSR_BOUNDARY_512K = 0x7

	// BCR: Block Count
	// Position of BCNT field.
	SDHC_BCR_BCNT_Pos = 0x0
	// Bit mask of BCNT field.
	SDHC_BCR_BCNT_Msk = 0xffff

	// ARG1R: Argument 1
	// Position of ARG field.
	SDHC_ARG1R_ARG_Pos = 0x0
	// Bit mask of ARG field.
	SDHC_ARG1R_ARG_Msk = 0xffffffff

	// TMR: Transfer Mode
	// Position of DMAEN field.
	SDHC_TMR_DMAEN_Pos = 0x0
	// Bit mask of DMAEN field.
	SDHC_TMR_DMAEN_Msk = 0x1
	// Bit DMAEN.
	SDHC_TMR_DMAEN = 0x1
	// No data transfer or Non DMA data transfer
	SDHC_TMR_DMAEN_DISABLE = 0x0
	// DMA data transfer
	SDHC_TMR_DMAEN_ENABLE = 0x1
	// Position of BCEN field.
	SDHC_TMR_BCEN_Pos = 0x1
	// Bit mask of BCEN field.
	SDHC_TMR_BCEN_Msk = 0x2
	// Bit BCEN.
	SDHC_TMR_BCEN = 0x2
	// Disable
	SDHC_TMR_BCEN_DISABLE = 0x0
	// Enable
	SDHC_TMR_BCEN_ENABLE = 0x1
	// Position of ACMDEN field.
	SDHC_TMR_ACMDEN_Pos = 0x2
	// Bit mask of ACMDEN field.
	SDHC_TMR_ACMDEN_Msk = 0xc
	// Auto Command Disabled
	SDHC_TMR_ACMDEN_DISABLED = 0x0
	// Auto CMD12 Enable
	SDHC_TMR_ACMDEN_CMD12 = 0x1
	// Auto CMD23 Enable
	SDHC_TMR_ACMDEN_CMD23 = 0x2
	// Position of DTDSEL field.
	SDHC_TMR_DTDSEL_Pos = 0x4
	// Bit mask of DTDSEL field.
	SDHC_TMR_DTDSEL_Msk = 0x10
	// Bit DTDSEL.
	SDHC_TMR_DTDSEL = 0x10
	// Write (Host to Card)
	SDHC_TMR_DTDSEL_WRITE = 0x0
	// Read (Card to Host)
	SDHC_TMR_DTDSEL_READ = 0x1
	// Position of MSBSEL field.
	SDHC_TMR_MSBSEL_Pos = 0x5
	// Bit mask of MSBSEL field.
	SDHC_TMR_MSBSEL_Msk = 0x20
	// Bit MSBSEL.
	SDHC_TMR_MSBSEL = 0x20
	// Single Block
	SDHC_TMR_MSBSEL_SINGLE = 0x0
	// Multiple Block
	SDHC_TMR_MSBSEL_MULTIPLE = 0x1

	// CR: Command
	// Position of RESPTYP field.
	SDHC_CR_RESPTYP_Pos = 0x0
	// Bit mask of RESPTYP field.
	SDHC_CR_RESPTYP_Msk = 0x3
	// No response
	SDHC_CR_RESPTYP_NONE = 0x0
	// 136-bit response
	SDHC_CR_RESPTYP_136_BIT = 0x1
	// 48-bit response
	SDHC_CR_RESPTYP_48_BIT = 0x2
	// 48-bit response check busy after response
	SDHC_CR_RESPTYP_48_BIT_BUSY = 0x3
	// Position of CMDCCEN field.
	SDHC_CR_CMDCCEN_Pos = 0x3
	// Bit mask of CMDCCEN field.
	SDHC_CR_CMDCCEN_Msk = 0x8
	// Bit CMDCCEN.
	SDHC_CR_CMDCCEN = 0x8
	// Disable
	SDHC_CR_CMDCCEN_DISABLE = 0x0
	// Enable
	SDHC_CR_CMDCCEN_ENABLE = 0x1
	// Position of CMDICEN field.
	SDHC_CR_CMDICEN_Pos = 0x4
	// Bit mask of CMDICEN field.
	SDHC_CR_CMDICEN_Msk = 0x10
	// Bit CMDICEN.
	SDHC_CR_CMDICEN = 0x10
	// Disable
	SDHC_CR_CMDICEN_DISABLE = 0x0
	// Enable
	SDHC_CR_CMDICEN_ENABLE = 0x1
	// Position of DPSEL field.
	SDHC_CR_DPSEL_Pos = 0x5
	// Bit mask of DPSEL field.
	SDHC_CR_DPSEL_Msk = 0x20
	// Bit DPSEL.
	SDHC_CR_DPSEL = 0x20
	// No Data Present
	SDHC_CR_DPSEL_NO_DATA = 0x0
	// Data Present
	SDHC_CR_DPSEL_DATA = 0x1
	// Position of CMDTYP field.
	SDHC_CR_CMDTYP_Pos = 0x6
	// Bit mask of CMDTYP field.
	SDHC_CR_CMDTYP_Msk = 0xc0
	// Other commands
	SDHC_CR_CMDTYP_NORMAL = 0x0
	// CMD52 for writing Bus Suspend in CCCR
	SDHC_CR_CMDTYP_SUSPEND = 0x1
	// CMD52 for writing Function Select in CCCR
	SDHC_CR_CMDTYP_RESUME = 0x2
	// CMD12, CMD52 for writing I/O Abort in CCCR
	SDHC_CR_CMDTYP_ABORT = 0x3
	// Position of CMDIDX field.
	SDHC_CR_CMDIDX_Pos = 0x8
	// Bit mask of CMDIDX field.
	SDHC_CR_CMDIDX_Msk = 0x3f00

	// RR: Response
	// Position of CMDRESP field.
	SDHC_RR_CMDRESP_Pos = 0x0
	// Bit mask of CMDRESP field.
	SDHC_RR_CMDRESP_Msk = 0xffffffff

	// BDPR: Buffer Data Port
	// Position of BUFDATA field.
	SDHC_BDPR_BUFDATA_Pos = 0x0
	// Bit mask of BUFDATA field.
	SDHC_BDPR_BUFDATA_Msk = 0xffffffff

	// PSR: Present State
	// Position of CMDINHC field.
	SDHC_PSR_CMDINHC_Pos = 0x0
	// Bit mask of CMDINHC field.
	SDHC_PSR_CMDINHC_Msk = 0x1
	// Bit CMDINHC.
	SDHC_PSR_CMDINHC = 0x1
	// Can issue command using only CMD line
	SDHC_PSR_CMDINHC_CAN = 0x0
	// Cannot issue command
	SDHC_PSR_CMDINHC_CANNOT = 0x1
	// Position of CMDINHD field.
	SDHC_PSR_CMDINHD_Pos = 0x1
	// Bit mask of CMDINHD field.
	SDHC_PSR_CMDINHD_Msk = 0x2
	// Bit CMDINHD.
	SDHC_PSR_CMDINHD = 0x2
	// Can issue command which uses the DAT line
	SDHC_PSR_CMDINHD_CAN = 0x0
	// Cannot issue command which uses the DAT line
	SDHC_PSR_CMDINHD_CANNOT = 0x1
	// Position of DLACT field.
	SDHC_PSR_DLACT_Pos = 0x2
	// Bit mask of DLACT field.
	SDHC_PSR_DLACT_Msk = 0x4
	// Bit DLACT.
	SDHC_PSR_DLACT = 0x4
	// DAT Line Inactive
	SDHC_PSR_DLACT_INACTIVE = 0x0
	// DAT Line Active
	SDHC_PSR_DLACT_ACTIVE = 0x1
	// Position of RTREQ field.
	SDHC_PSR_RTREQ_Pos = 0x3
	// Bit mask of RTREQ field.
	SDHC_PSR_RTREQ_Msk = 0x8
	// Bit RTREQ.
	SDHC_PSR_RTREQ = 0x8
	// Fixed or well-tuned sampling clock
	SDHC_PSR_RTREQ_OK = 0x0
	// Sampling clock needs re-tuning
	SDHC_PSR_RTREQ_REQUIRED = 0x1
	// Position of WTACT field.
	SDHC_PSR_WTACT_Pos = 0x8
	// Bit mask of WTACT field.
	SDHC_PSR_WTACT_Msk = 0x100
	// Bit WTACT.
	SDHC_PSR_WTACT = 0x100
	// No valid data
	SDHC_PSR_WTACT_NO = 0x0
	// Transferring data
	SDHC_PSR_WTACT_YES = 0x1
	// Position of RTACT field.
	SDHC_PSR_RTACT_Pos = 0x9
	// Bit mask of RTACT field.
	SDHC_PSR_RTACT_Msk = 0x200
	// Bit RTACT.
	SDHC_PSR_RTACT = 0x200
	// No valid data
	SDHC_PSR_RTACT_NO = 0x0
	// Transferring data
	SDHC_PSR_RTACT_YES = 0x1
	// Position of BUFWREN field.
	SDHC_PSR_BUFWREN_Pos = 0xa
	// Bit mask of BUFWREN field.
	SDHC_PSR_BUFWREN_Msk = 0x400
	// Bit BUFWREN.
	SDHC_PSR_BUFWREN = 0x400
	// Write disable
	SDHC_PSR_BUFWREN_DISABLE = 0x0
	// Write enable
	SDHC_PSR_BUFWREN_ENABLE = 0x1
	// Position of BUFRDEN field.
	SDHC_PSR_BUFRDEN_Pos = 0xb
	// Bit mask of BUFRDEN field.
	SDHC_PSR_BUFRDEN_Msk = 0x800
	// Bit BUFRDEN.
	SDHC_PSR_BUFRDEN = 0x800
	// Read disable
	SDHC_PSR_BUFRDEN_DISABLE = 0x0
	// Read enable
	SDHC_PSR_BUFRDEN_ENABLE = 0x1
	// Position of CARDINS field.
	SDHC_PSR_CARDINS_Pos = 0x10
	// Bit mask of CARDINS field.
	SDHC_PSR_CARDINS_Msk = 0x10000
	// Bit CARDINS.
	SDHC_PSR_CARDINS = 0x10000
	// Reset or Debouncing or No Card
	SDHC_PSR_CARDINS_NO = 0x0
	// Card inserted
	SDHC_PSR_CARDINS_YES = 0x1
	// Position of CARDSS field.
	SDHC_PSR_CARDSS_Pos = 0x11
	// Bit mask of CARDSS field.
	SDHC_PSR_CARDSS_Msk = 0x20000
	// Bit CARDSS.
	SDHC_PSR_CARDSS = 0x20000
	// Reset or Debouncing
	SDHC_PSR_CARDSS_NO = 0x0
	// No Card or Insered
	SDHC_PSR_CARDSS_YES = 0x1
	// Position of CARDDPL field.
	SDHC_PSR_CARDDPL_Pos = 0x12
	// Bit mask of CARDDPL field.
	SDHC_PSR_CARDDPL_Msk = 0x40000
	// Bit CARDDPL.
	SDHC_PSR_CARDDPL = 0x40000
	// No card present (SDCD#=1)
	SDHC_PSR_CARDDPL_NO = 0x0
	// Card present (SDCD#=0)
	SDHC_PSR_CARDDPL_YES = 0x1
	// Position of WRPPL field.
	SDHC_PSR_WRPPL_Pos = 0x13
	// Bit mask of WRPPL field.
	SDHC_PSR_WRPPL_Msk = 0x80000
	// Bit WRPPL.
	SDHC_PSR_WRPPL = 0x80000
	// Write protected (SDWP#=0)
	SDHC_PSR_WRPPL_PROTECTED = 0x0
	// Write enabled (SDWP#=1)
	SDHC_PSR_WRPPL_ENABLED = 0x1
	// Position of DATLL field.
	SDHC_PSR_DATLL_Pos = 0x14
	// Bit mask of DATLL field.
	SDHC_PSR_DATLL_Msk = 0xf00000
	// Position of CMDLL field.
	SDHC_PSR_CMDLL_Pos = 0x18
	// Bit mask of CMDLL field.
	SDHC_PSR_CMDLL_Msk = 0x1000000
	// Bit CMDLL.
	SDHC_PSR_CMDLL = 0x1000000

	// HC1R: Host Control 1
	// Position of LEDCTRL field.
	SDHC_HC1R_LEDCTRL_Pos = 0x0
	// Bit mask of LEDCTRL field.
	SDHC_HC1R_LEDCTRL_Msk = 0x1
	// Bit LEDCTRL.
	SDHC_HC1R_LEDCTRL = 0x1
	// LED off
	SDHC_HC1R_LEDCTRL_OFF = 0x0
	// LED on
	SDHC_HC1R_LEDCTRL_ON = 0x1
	// Position of DW field.
	SDHC_HC1R_DW_Pos = 0x1
	// Bit mask of DW field.
	SDHC_HC1R_DW_Msk = 0x2
	// Bit DW.
	SDHC_HC1R_DW = 0x2
	// 1-bit mode
	SDHC_HC1R_DW_1BIT = 0x0
	// 4-bit mode
	SDHC_HC1R_DW_4BIT = 0x1
	// Position of HSEN field.
	SDHC_HC1R_HSEN_Pos = 0x2
	// Bit mask of HSEN field.
	SDHC_HC1R_HSEN_Msk = 0x4
	// Bit HSEN.
	SDHC_HC1R_HSEN = 0x4
	// Normal Speed mode
	SDHC_HC1R_HSEN_NORMAL = 0x0
	// High Speed mode
	SDHC_HC1R_HSEN_HIGH = 0x1
	// Position of DMASEL field.
	SDHC_HC1R_DMASEL_Pos = 0x3
	// Bit mask of DMASEL field.
	SDHC_HC1R_DMASEL_Msk = 0x18
	// SDMA is selected
	SDHC_HC1R_DMASEL_SDMA = 0x0
	// 32-bit Address ADMA2 is selected
	SDHC_HC1R_DMASEL_32BIT = 0x2
	// Position of CARDDTL field.
	SDHC_HC1R_CARDDTL_Pos = 0x6
	// Bit mask of CARDDTL field.
	SDHC_HC1R_CARDDTL_Msk = 0x40
	// Bit CARDDTL.
	SDHC_HC1R_CARDDTL = 0x40
	// No Card
	SDHC_HC1R_CARDDTL_NO = 0x0
	// Card Inserted
	SDHC_HC1R_CARDDTL_YES = 0x1
	// Position of CARDDSEL field.
	SDHC_HC1R_CARDDSEL_Pos = 0x7
	// Bit mask of CARDDSEL field.
	SDHC_HC1R_CARDDSEL_Msk = 0x80
	// Bit CARDDSEL.
	SDHC_HC1R_CARDDSEL = 0x80
	// SDCD# is selected (for normal use)
	SDHC_HC1R_CARDDSEL_NORMAL = 0x0
	// The Card Select Test Level is selected (for test purpose)
	SDHC_HC1R_CARDDSEL_TEST = 0x1

	// HC1R_EMMC_MODE: Host Control 1
	// Position of DW field.
	SDHC_HC1R_EMMC_MODE_DW_Pos = 0x1
	// Bit mask of DW field.
	SDHC_HC1R_EMMC_MODE_DW_Msk = 0x2
	// Bit DW.
	SDHC_HC1R_EMMC_MODE_DW = 0x2
	// 1-bit mode
	SDHC_HC1R_EMMC_MODE_DW_1BIT = 0x0
	// 4-bit mode
	SDHC_HC1R_EMMC_MODE_DW_4BIT = 0x1
	// Position of HSEN field.
	SDHC_HC1R_EMMC_MODE_HSEN_Pos = 0x2
	// Bit mask of HSEN field.
	SDHC_HC1R_EMMC_MODE_HSEN_Msk = 0x4
	// Bit HSEN.
	SDHC_HC1R_EMMC_MODE_HSEN = 0x4
	// Normal Speed mode
	SDHC_HC1R_EMMC_MODE_HSEN_NORMAL = 0x0
	// High Speed mode
	SDHC_HC1R_EMMC_MODE_HSEN_HIGH = 0x1
	// Position of DMASEL field.
	SDHC_HC1R_EMMC_MODE_DMASEL_Pos = 0x3
	// Bit mask of DMASEL field.
	SDHC_HC1R_EMMC_MODE_DMASEL_Msk = 0x18
	// SDMA is selected
	SDHC_HC1R_EMMC_MODE_DMASEL_SDMA = 0x0
	// 32-bit Address ADMA2 is selected
	SDHC_HC1R_EMMC_MODE_DMASEL_32BIT = 0x2

	// PCR: Power Control
	// Position of SDBPWR field.
	SDHC_PCR_SDBPWR_Pos = 0x0
	// Bit mask of SDBPWR field.
	SDHC_PCR_SDBPWR_Msk = 0x1
	// Bit SDBPWR.
	SDHC_PCR_SDBPWR = 0x1
	// Power off
	SDHC_PCR_SDBPWR_OFF = 0x0
	// Power on
	SDHC_PCR_SDBPWR_ON = 0x1
	// Position of SDBVSEL field.
	SDHC_PCR_SDBVSEL_Pos = 0x1
	// Bit mask of SDBVSEL field.
	SDHC_PCR_SDBVSEL_Msk = 0xe
	// 1.8V (Typ.)
	SDHC_PCR_SDBVSEL_1V8 = 0x5
	// 3.0V (Typ.)
	SDHC_PCR_SDBVSEL_3V0 = 0x6
	// 3.3V (Typ.)
	SDHC_PCR_SDBVSEL_3V3 = 0x7

	// BGCR: Block Gap Control
	// Position of STPBGR field.
	SDHC_BGCR_STPBGR_Pos = 0x0
	// Bit mask of STPBGR field.
	SDHC_BGCR_STPBGR_Msk = 0x1
	// Bit STPBGR.
	SDHC_BGCR_STPBGR = 0x1
	// Transfer
	SDHC_BGCR_STPBGR_TRANSFER = 0x0
	// Stop
	SDHC_BGCR_STPBGR_STOP = 0x1
	// Position of CONTR field.
	SDHC_BGCR_CONTR_Pos = 0x1
	// Bit mask of CONTR field.
	SDHC_BGCR_CONTR_Msk = 0x2
	// Bit CONTR.
	SDHC_BGCR_CONTR = 0x2
	// Not affected
	SDHC_BGCR_CONTR_GO_ON = 0x0
	// Restart
	SDHC_BGCR_CONTR_RESTART = 0x1
	// Position of RWCTRL field.
	SDHC_BGCR_RWCTRL_Pos = 0x2
	// Bit mask of RWCTRL field.
	SDHC_BGCR_RWCTRL_Msk = 0x4
	// Bit RWCTRL.
	SDHC_BGCR_RWCTRL = 0x4
	// Disable Read Wait Control
	SDHC_BGCR_RWCTRL_DISABLE = 0x0
	// Enable Read Wait Control
	SDHC_BGCR_RWCTRL_ENABLE = 0x1
	// Position of INTBG field.
	SDHC_BGCR_INTBG_Pos = 0x3
	// Bit mask of INTBG field.
	SDHC_BGCR_INTBG_Msk = 0x8
	// Bit INTBG.
	SDHC_BGCR_INTBG = 0x8
	// Disabled
	SDHC_BGCR_INTBG_DISABLED = 0x0
	// Enabled
	SDHC_BGCR_INTBG_ENABLED = 0x1

	// BGCR_EMMC_MODE: Block Gap Control
	// Position of STPBGR field.
	SDHC_BGCR_EMMC_MODE_STPBGR_Pos = 0x0
	// Bit mask of STPBGR field.
	SDHC_BGCR_EMMC_MODE_STPBGR_Msk = 0x1
	// Bit STPBGR.
	SDHC_BGCR_EMMC_MODE_STPBGR = 0x1
	// Transfer
	SDHC_BGCR_EMMC_MODE_STPBGR_TRANSFER = 0x0
	// Stop
	SDHC_BGCR_EMMC_MODE_STPBGR_STOP = 0x1
	// Position of CONTR field.
	SDHC_BGCR_EMMC_MODE_CONTR_Pos = 0x1
	// Bit mask of CONTR field.
	SDHC_BGCR_EMMC_MODE_CONTR_Msk = 0x2
	// Bit CONTR.
	SDHC_BGCR_EMMC_MODE_CONTR = 0x2
	// Not affected
	SDHC_BGCR_EMMC_MODE_CONTR_GO_ON = 0x0
	// Restart
	SDHC_BGCR_EMMC_MODE_CONTR_RESTART = 0x1

	// WCR: Wakeup Control
	// Position of WKENCINT field.
	SDHC_WCR_WKENCINT_Pos = 0x0
	// Bit mask of WKENCINT field.
	SDHC_WCR_WKENCINT_Msk = 0x1
	// Bit WKENCINT.
	SDHC_WCR_WKENCINT = 0x1
	// Disable
	SDHC_WCR_WKENCINT_DISABLE = 0x0
	// Enable
	SDHC_WCR_WKENCINT_ENABLE = 0x1
	// Position of WKENCINS field.
	SDHC_WCR_WKENCINS_Pos = 0x1
	// Bit mask of WKENCINS field.
	SDHC_WCR_WKENCINS_Msk = 0x2
	// Bit WKENCINS.
	SDHC_WCR_WKENCINS = 0x2
	// Disable
	SDHC_WCR_WKENCINS_DISABLE = 0x0
	// Enable
	SDHC_WCR_WKENCINS_ENABLE = 0x1
	// Position of WKENCREM field.
	SDHC_WCR_WKENCREM_Pos = 0x2
	// Bit mask of WKENCREM field.
	SDHC_WCR_WKENCREM_Msk = 0x4
	// Bit WKENCREM.
	SDHC_WCR_WKENCREM = 0x4
	// Disable
	SDHC_WCR_WKENCREM_DISABLE = 0x0
	// Enable
	SDHC_WCR_WKENCREM_ENABLE = 0x1

	// CCR: Clock Control
	// Position of INTCLKEN field.
	SDHC_CCR_INTCLKEN_Pos = 0x0
	// Bit mask of INTCLKEN field.
	SDHC_CCR_INTCLKEN_Msk = 0x1
	// Bit INTCLKEN.
	SDHC_CCR_INTCLKEN = 0x1
	// Stop
	SDHC_CCR_INTCLKEN_OFF = 0x0
	// Oscillate
	SDHC_CCR_INTCLKEN_ON = 0x1
	// Position of INTCLKS field.
	SDHC_CCR_INTCLKS_Pos = 0x1
	// Bit mask of INTCLKS field.
	SDHC_CCR_INTCLKS_Msk = 0x2
	// Bit INTCLKS.
	SDHC_CCR_INTCLKS = 0x2
	// Not Ready
	SDHC_CCR_INTCLKS_NOT_READY = 0x0
	// Ready
	SDHC_CCR_INTCLKS_READY = 0x1
	// Position of SDCLKEN field.
	SDHC_CCR_SDCLKEN_Pos = 0x2
	// Bit mask of SDCLKEN field.
	SDHC_CCR_SDCLKEN_Msk = 0x4
	// Bit SDCLKEN.
	SDHC_CCR_SDCLKEN = 0x4
	// Disable
	SDHC_CCR_SDCLKEN_DISABLE = 0x0
	// Enable
	SDHC_CCR_SDCLKEN_ENABLE = 0x1
	// Position of CLKGSEL field.
	SDHC_CCR_CLKGSEL_Pos = 0x5
	// Bit mask of CLKGSEL field.
	SDHC_CCR_CLKGSEL_Msk = 0x20
	// Bit CLKGSEL.
	SDHC_CCR_CLKGSEL = 0x20
	// Divided Clock Mode
	SDHC_CCR_CLKGSEL_DIV = 0x0
	// Programmable Clock Mode
	SDHC_CCR_CLKGSEL_PROG = 0x1
	// Position of USDCLKFSEL field.
	SDHC_CCR_USDCLKFSEL_Pos = 0x6
	// Bit mask of USDCLKFSEL field.
	SDHC_CCR_USDCLKFSEL_Msk = 0xc0
	// Position of SDCLKFSEL field.
	SDHC_CCR_SDCLKFSEL_Pos = 0x8
	// Bit mask of SDCLKFSEL field.
	SDHC_CCR_SDCLKFSEL_Msk = 0xff00

	// TCR: Timeout Control
	// Position of DTCVAL field.
	SDHC_TCR_DTCVAL_Pos = 0x0
	// Bit mask of DTCVAL field.
	SDHC_TCR_DTCVAL_Msk = 0xf

	// SRR: Software Reset
	// Position of SWRSTALL field.
	SDHC_SRR_SWRSTALL_Pos = 0x0
	// Bit mask of SWRSTALL field.
	SDHC_SRR_SWRSTALL_Msk = 0x1
	// Bit SWRSTALL.
	SDHC_SRR_SWRSTALL = 0x1
	// Work
	SDHC_SRR_SWRSTALL_WORK = 0x0
	// Reset
	SDHC_SRR_SWRSTALL_RESET = 0x1
	// Position of SWRSTCMD field.
	SDHC_SRR_SWRSTCMD_Pos = 0x1
	// Bit mask of SWRSTCMD field.
	SDHC_SRR_SWRSTCMD_Msk = 0x2
	// Bit SWRSTCMD.
	SDHC_SRR_SWRSTCMD = 0x2
	// Work
	SDHC_SRR_SWRSTCMD_WORK = 0x0
	// Reset
	SDHC_SRR_SWRSTCMD_RESET = 0x1
	// Position of SWRSTDAT field.
	SDHC_SRR_SWRSTDAT_Pos = 0x2
	// Bit mask of SWRSTDAT field.
	SDHC_SRR_SWRSTDAT_Msk = 0x4
	// Bit SWRSTDAT.
	SDHC_SRR_SWRSTDAT = 0x4
	// Work
	SDHC_SRR_SWRSTDAT_WORK = 0x0
	// Reset
	SDHC_SRR_SWRSTDAT_RESET = 0x1

	// NISTR: Normal Interrupt Status
	// Position of CMDC field.
	SDHC_NISTR_CMDC_Pos = 0x0
	// Bit mask of CMDC field.
	SDHC_NISTR_CMDC_Msk = 0x1
	// Bit CMDC.
	SDHC_NISTR_CMDC = 0x1
	// No command complete
	SDHC_NISTR_CMDC_NO = 0x0
	// Command complete
	SDHC_NISTR_CMDC_YES = 0x1
	// Position of TRFC field.
	SDHC_NISTR_TRFC_Pos = 0x1
	// Bit mask of TRFC field.
	SDHC_NISTR_TRFC_Msk = 0x2
	// Bit TRFC.
	SDHC_NISTR_TRFC = 0x2
	// Not complete
	SDHC_NISTR_TRFC_NO = 0x0
	// Command execution is completed
	SDHC_NISTR_TRFC_YES = 0x1
	// Position of BLKGE field.
	SDHC_NISTR_BLKGE_Pos = 0x2
	// Bit mask of BLKGE field.
	SDHC_NISTR_BLKGE_Msk = 0x4
	// Bit BLKGE.
	SDHC_NISTR_BLKGE = 0x4
	// No Block Gap Event
	SDHC_NISTR_BLKGE_NO = 0x0
	// Transaction stopped at block gap
	SDHC_NISTR_BLKGE_STOP = 0x1
	// Position of DMAINT field.
	SDHC_NISTR_DMAINT_Pos = 0x3
	// Bit mask of DMAINT field.
	SDHC_NISTR_DMAINT_Msk = 0x8
	// Bit DMAINT.
	SDHC_NISTR_DMAINT = 0x8
	// No DMA Interrupt
	SDHC_NISTR_DMAINT_NO = 0x0
	// DMA Interrupt is generated
	SDHC_NISTR_DMAINT_YES = 0x1
	// Position of BWRRDY field.
	SDHC_NISTR_BWRRDY_Pos = 0x4
	// Bit mask of BWRRDY field.
	SDHC_NISTR_BWRRDY_Msk = 0x10
	// Bit BWRRDY.
	SDHC_NISTR_BWRRDY = 0x10
	// Not ready to write buffer
	SDHC_NISTR_BWRRDY_NO = 0x0
	// Ready to write buffer
	SDHC_NISTR_BWRRDY_YES = 0x1
	// Position of BRDRDY field.
	SDHC_NISTR_BRDRDY_Pos = 0x5
	// Bit mask of BRDRDY field.
	SDHC_NISTR_BRDRDY_Msk = 0x20
	// Bit BRDRDY.
	SDHC_NISTR_BRDRDY = 0x20
	// Not ready to read buffer
	SDHC_NISTR_BRDRDY_NO = 0x0
	// Ready to read buffer
	SDHC_NISTR_BRDRDY_YES = 0x1
	// Position of CINS field.
	SDHC_NISTR_CINS_Pos = 0x6
	// Bit mask of CINS field.
	SDHC_NISTR_CINS_Msk = 0x40
	// Bit CINS.
	SDHC_NISTR_CINS = 0x40
	// Card state stable or Debouncing
	SDHC_NISTR_CINS_NO = 0x0
	// Card inserted
	SDHC_NISTR_CINS_YES = 0x1
	// Position of CREM field.
	SDHC_NISTR_CREM_Pos = 0x7
	// Bit mask of CREM field.
	SDHC_NISTR_CREM_Msk = 0x80
	// Bit CREM.
	SDHC_NISTR_CREM = 0x80
	// Card state stable or Debouncing
	SDHC_NISTR_CREM_NO = 0x0
	// Card Removed
	SDHC_NISTR_CREM_YES = 0x1
	// Position of CINT field.
	SDHC_NISTR_CINT_Pos = 0x8
	// Bit mask of CINT field.
	SDHC_NISTR_CINT_Msk = 0x100
	// Bit CINT.
	SDHC_NISTR_CINT = 0x100
	// No Card Interrupt
	SDHC_NISTR_CINT_NO = 0x0
	// Generate Card Interrupt
	SDHC_NISTR_CINT_YES = 0x1
	// Position of ERRINT field.
	SDHC_NISTR_ERRINT_Pos = 0xf
	// Bit mask of ERRINT field.
	SDHC_NISTR_ERRINT_Msk = 0x8000
	// Bit ERRINT.
	SDHC_NISTR_ERRINT = 0x8000
	// No Error
	SDHC_NISTR_ERRINT_NO = 0x0
	// Error
	SDHC_NISTR_ERRINT_YES = 0x1

	// NISTR_EMMC_MODE: Normal Interrupt Status
	// Position of CMDC field.
	SDHC_NISTR_EMMC_MODE_CMDC_Pos = 0x0
	// Bit mask of CMDC field.
	SDHC_NISTR_EMMC_MODE_CMDC_Msk = 0x1
	// Bit CMDC.
	SDHC_NISTR_EMMC_MODE_CMDC = 0x1
	// No command complete
	SDHC_NISTR_EMMC_MODE_CMDC_NO = 0x0
	// Command complete
	SDHC_NISTR_EMMC_MODE_CMDC_YES = 0x1
	// Position of TRFC field.
	SDHC_NISTR_EMMC_MODE_TRFC_Pos = 0x1
	// Bit mask of TRFC field.
	SDHC_NISTR_EMMC_MODE_TRFC_Msk = 0x2
	// Bit TRFC.
	SDHC_NISTR_EMMC_MODE_TRFC = 0x2
	// Not complete
	SDHC_NISTR_EMMC_MODE_TRFC_NO = 0x0
	// Command execution is completed
	SDHC_NISTR_EMMC_MODE_TRFC_YES = 0x1
	// Position of BLKGE field.
	SDHC_NISTR_EMMC_MODE_BLKGE_Pos = 0x2
	// Bit mask of BLKGE field.
	SDHC_NISTR_EMMC_MODE_BLKGE_Msk = 0x4
	// Bit BLKGE.
	SDHC_NISTR_EMMC_MODE_BLKGE = 0x4
	// No Block Gap Event
	SDHC_NISTR_EMMC_MODE_BLKGE_NO = 0x0
	// Transaction stopped at block gap
	SDHC_NISTR_EMMC_MODE_BLKGE_STOP = 0x1
	// Position of DMAINT field.
	SDHC_NISTR_EMMC_MODE_DMAINT_Pos = 0x3
	// Bit mask of DMAINT field.
	SDHC_NISTR_EMMC_MODE_DMAINT_Msk = 0x8
	// Bit DMAINT.
	SDHC_NISTR_EMMC_MODE_DMAINT = 0x8
	// No DMA Interrupt
	SDHC_NISTR_EMMC_MODE_DMAINT_NO = 0x0
	// DMA Interrupt is generated
	SDHC_NISTR_EMMC_MODE_DMAINT_YES = 0x1
	// Position of BWRRDY field.
	SDHC_NISTR_EMMC_MODE_BWRRDY_Pos = 0x4
	// Bit mask of BWRRDY field.
	SDHC_NISTR_EMMC_MODE_BWRRDY_Msk = 0x10
	// Bit BWRRDY.
	SDHC_NISTR_EMMC_MODE_BWRRDY = 0x10
	// Not ready to write buffer
	SDHC_NISTR_EMMC_MODE_BWRRDY_NO = 0x0
	// Ready to write buffer
	SDHC_NISTR_EMMC_MODE_BWRRDY_YES = 0x1
	// Position of BRDRDY field.
	SDHC_NISTR_EMMC_MODE_BRDRDY_Pos = 0x5
	// Bit mask of BRDRDY field.
	SDHC_NISTR_EMMC_MODE_BRDRDY_Msk = 0x20
	// Bit BRDRDY.
	SDHC_NISTR_EMMC_MODE_BRDRDY = 0x20
	// Not ready to read buffer
	SDHC_NISTR_EMMC_MODE_BRDRDY_NO = 0x0
	// Ready to read buffer
	SDHC_NISTR_EMMC_MODE_BRDRDY_YES = 0x1
	// Position of BOOTAR field.
	SDHC_NISTR_EMMC_MODE_BOOTAR_Pos = 0xe
	// Bit mask of BOOTAR field.
	SDHC_NISTR_EMMC_MODE_BOOTAR_Msk = 0x4000
	// Bit BOOTAR.
	SDHC_NISTR_EMMC_MODE_BOOTAR = 0x4000
	// Position of ERRINT field.
	SDHC_NISTR_EMMC_MODE_ERRINT_Pos = 0xf
	// Bit mask of ERRINT field.
	SDHC_NISTR_EMMC_MODE_ERRINT_Msk = 0x8000
	// Bit ERRINT.
	SDHC_NISTR_EMMC_MODE_ERRINT = 0x8000
	// No Error
	SDHC_NISTR_EMMC_MODE_ERRINT_NO = 0x0
	// Error
	SDHC_NISTR_EMMC_MODE_ERRINT_YES = 0x1

	// EISTR: Error Interrupt Status
	// Position of CMDTEO field.
	SDHC_EISTR_CMDTEO_Pos = 0x0
	// Bit mask of CMDTEO field.
	SDHC_EISTR_CMDTEO_Msk = 0x1
	// Bit CMDTEO.
	SDHC_EISTR_CMDTEO = 0x1
	// No Error
	SDHC_EISTR_CMDTEO_NO = 0x0
	// Timeout
	SDHC_EISTR_CMDTEO_YES = 0x1
	// Position of CMDCRC field.
	SDHC_EISTR_CMDCRC_Pos = 0x1
	// Bit mask of CMDCRC field.
	SDHC_EISTR_CMDCRC_Msk = 0x2
	// Bit CMDCRC.
	SDHC_EISTR_CMDCRC = 0x2
	// No Error
	SDHC_EISTR_CMDCRC_NO = 0x0
	// CRC Error Generated
	SDHC_EISTR_CMDCRC_YES = 0x1
	// Position of CMDEND field.
	SDHC_EISTR_CMDEND_Pos = 0x2
	// Bit mask of CMDEND field.
	SDHC_EISTR_CMDEND_Msk = 0x4
	// Bit CMDEND.
	SDHC_EISTR_CMDEND = 0x4
	// No error
	SDHC_EISTR_CMDEND_NO = 0x0
	// End Bit Error Generated
	SDHC_EISTR_CMDEND_YES = 0x1
	// Position of CMDIDX field.
	SDHC_EISTR_CMDIDX_Pos = 0x3
	// Bit mask of CMDIDX field.
	SDHC_EISTR_CMDIDX_Msk = 0x8
	// Bit CMDIDX.
	SDHC_EISTR_CMDIDX = 0x8
	// No Error
	SDHC_EISTR_CMDIDX_NO = 0x0
	// Error
	SDHC_EISTR_CMDIDX_YES = 0x1
	// Position of DATTEO field.
	SDHC_EISTR_DATTEO_Pos = 0x4
	// Bit mask of DATTEO field.
	SDHC_EISTR_DATTEO_Msk = 0x10
	// Bit DATTEO.
	SDHC_EISTR_DATTEO = 0x10
	// No Error
	SDHC_EISTR_DATTEO_NO = 0x0
	// Timeout
	SDHC_EISTR_DATTEO_YES = 0x1
	// Position of DATCRC field.
	SDHC_EISTR_DATCRC_Pos = 0x5
	// Bit mask of DATCRC field.
	SDHC_EISTR_DATCRC_Msk = 0x20
	// Bit DATCRC.
	SDHC_EISTR_DATCRC = 0x20
	// No Error
	SDHC_EISTR_DATCRC_NO = 0x0
	// Error
	SDHC_EISTR_DATCRC_YES = 0x1
	// Position of DATEND field.
	SDHC_EISTR_DATEND_Pos = 0x6
	// Bit mask of DATEND field.
	SDHC_EISTR_DATEND_Msk = 0x40
	// Bit DATEND.
	SDHC_EISTR_DATEND = 0x40
	// No Error
	SDHC_EISTR_DATEND_NO = 0x0
	// Error
	SDHC_EISTR_DATEND_YES = 0x1
	// Position of CURLIM field.
	SDHC_EISTR_CURLIM_Pos = 0x7
	// Bit mask of CURLIM field.
	SDHC_EISTR_CURLIM_Msk = 0x80
	// Bit CURLIM.
	SDHC_EISTR_CURLIM = 0x80
	// No Error
	SDHC_EISTR_CURLIM_NO = 0x0
	// Power Fail
	SDHC_EISTR_CURLIM_YES = 0x1
	// Position of ACMD field.
	SDHC_EISTR_ACMD_Pos = 0x8
	// Bit mask of ACMD field.
	SDHC_EISTR_ACMD_Msk = 0x100
	// Bit ACMD.
	SDHC_EISTR_ACMD = 0x100
	// No Error
	SDHC_EISTR_ACMD_NO = 0x0
	// Error
	SDHC_EISTR_ACMD_YES = 0x1
	// Position of ADMA field.
	SDHC_EISTR_ADMA_Pos = 0x9
	// Bit mask of ADMA field.
	SDHC_EISTR_ADMA_Msk = 0x200
	// Bit ADMA.
	SDHC_EISTR_ADMA = 0x200
	// No Error
	SDHC_EISTR_ADMA_NO = 0x0
	// Error
	SDHC_EISTR_ADMA_YES = 0x1

	// EISTR_EMMC_MODE: Error Interrupt Status
	// Position of CMDTEO field.
	SDHC_EISTR_EMMC_MODE_CMDTEO_Pos = 0x0
	// Bit mask of CMDTEO field.
	SDHC_EISTR_EMMC_MODE_CMDTEO_Msk = 0x1
	// Bit CMDTEO.
	SDHC_EISTR_EMMC_MODE_CMDTEO = 0x1
	// No Error
	SDHC_EISTR_EMMC_MODE_CMDTEO_NO = 0x0
	// Timeout
	SDHC_EISTR_EMMC_MODE_CMDTEO_YES = 0x1
	// Position of CMDCRC field.
	SDHC_EISTR_EMMC_MODE_CMDCRC_Pos = 0x1
	// Bit mask of CMDCRC field.
	SDHC_EISTR_EMMC_MODE_CMDCRC_Msk = 0x2
	// Bit CMDCRC.
	SDHC_EISTR_EMMC_MODE_CMDCRC = 0x2
	// No Error
	SDHC_EISTR_EMMC_MODE_CMDCRC_NO = 0x0
	// CRC Error Generated
	SDHC_EISTR_EMMC_MODE_CMDCRC_YES = 0x1
	// Position of CMDEND field.
	SDHC_EISTR_EMMC_MODE_CMDEND_Pos = 0x2
	// Bit mask of CMDEND field.
	SDHC_EISTR_EMMC_MODE_CMDEND_Msk = 0x4
	// Bit CMDEND.
	SDHC_EISTR_EMMC_MODE_CMDEND = 0x4
	// No error
	SDHC_EISTR_EMMC_MODE_CMDEND_NO = 0x0
	// End Bit Error Generated
	SDHC_EISTR_EMMC_MODE_CMDEND_YES = 0x1
	// Position of CMDIDX field.
	SDHC_EISTR_EMMC_MODE_CMDIDX_Pos = 0x3
	// Bit mask of CMDIDX field.
	SDHC_EISTR_EMMC_MODE_CMDIDX_Msk = 0x8
	// Bit CMDIDX.
	SDHC_EISTR_EMMC_MODE_CMDIDX = 0x8
	// No Error
	SDHC_EISTR_EMMC_MODE_CMDIDX_NO = 0x0
	// Error
	SDHC_EISTR_EMMC_MODE_CMDIDX_YES = 0x1
	// Position of DATTEO field.
	SDHC_EISTR_EMMC_MODE_DATTEO_Pos = 0x4
	// Bit mask of DATTEO field.
	SDHC_EISTR_EMMC_MODE_DATTEO_Msk = 0x10
	// Bit DATTEO.
	SDHC_EISTR_EMMC_MODE_DATTEO = 0x10
	// No Error
	SDHC_EISTR_EMMC_MODE_DATTEO_NO = 0x0
	// Timeout
	SDHC_EISTR_EMMC_MODE_DATTEO_YES = 0x1
	// Position of DATCRC field.
	SDHC_EISTR_EMMC_MODE_DATCRC_Pos = 0x5
	// Bit mask of DATCRC field.
	SDHC_EISTR_EMMC_MODE_DATCRC_Msk = 0x20
	// Bit DATCRC.
	SDHC_EISTR_EMMC_MODE_DATCRC = 0x20
	// No Error
	SDHC_EISTR_EMMC_MODE_DATCRC_NO = 0x0
	// Error
	SDHC_EISTR_EMMC_MODE_DATCRC_YES = 0x1
	// Position of DATEND field.
	SDHC_EISTR_EMMC_MODE_DATEND_Pos = 0x6
	// Bit mask of DATEND field.
	SDHC_EISTR_EMMC_MODE_DATEND_Msk = 0x40
	// Bit DATEND.
	SDHC_EISTR_EMMC_MODE_DATEND = 0x40
	// No Error
	SDHC_EISTR_EMMC_MODE_DATEND_NO = 0x0
	// Error
	SDHC_EISTR_EMMC_MODE_DATEND_YES = 0x1
	// Position of CURLIM field.
	SDHC_EISTR_EMMC_MODE_CURLIM_Pos = 0x7
	// Bit mask of CURLIM field.
	SDHC_EISTR_EMMC_MODE_CURLIM_Msk = 0x80
	// Bit CURLIM.
	SDHC_EISTR_EMMC_MODE_CURLIM = 0x80
	// No Error
	SDHC_EISTR_EMMC_MODE_CURLIM_NO = 0x0
	// Power Fail
	SDHC_EISTR_EMMC_MODE_CURLIM_YES = 0x1
	// Position of ACMD field.
	SDHC_EISTR_EMMC_MODE_ACMD_Pos = 0x8
	// Bit mask of ACMD field.
	SDHC_EISTR_EMMC_MODE_ACMD_Msk = 0x100
	// Bit ACMD.
	SDHC_EISTR_EMMC_MODE_ACMD = 0x100
	// No Error
	SDHC_EISTR_EMMC_MODE_ACMD_NO = 0x0
	// Error
	SDHC_EISTR_EMMC_MODE_ACMD_YES = 0x1
	// Position of ADMA field.
	SDHC_EISTR_EMMC_MODE_ADMA_Pos = 0x9
	// Bit mask of ADMA field.
	SDHC_EISTR_EMMC_MODE_ADMA_Msk = 0x200
	// Bit ADMA.
	SDHC_EISTR_EMMC_MODE_ADMA = 0x200
	// No Error
	SDHC_EISTR_EMMC_MODE_ADMA_NO = 0x0
	// Error
	SDHC_EISTR_EMMC_MODE_ADMA_YES = 0x1
	// Position of BOOTAE field.
	SDHC_EISTR_EMMC_MODE_BOOTAE_Pos = 0xc
	// Bit mask of BOOTAE field.
	SDHC_EISTR_EMMC_MODE_BOOTAE_Msk = 0x1000
	// Bit BOOTAE.
	SDHC_EISTR_EMMC_MODE_BOOTAE = 0x1000
	// FIFO contains at least one byte
	SDHC_EISTR_EMMC_MODE_BOOTAE_0 = 0x0
	// FIFO is empty
	SDHC_EISTR_EMMC_MODE_BOOTAE_1 = 0x1

	// NISTER: Normal Interrupt Status Enable
	// Position of CMDC field.
	SDHC_NISTER_CMDC_Pos = 0x0
	// Bit mask of CMDC field.
	SDHC_NISTER_CMDC_Msk = 0x1
	// Bit CMDC.
	SDHC_NISTER_CMDC = 0x1
	// Masked
	SDHC_NISTER_CMDC_MASKED = 0x0
	// Enabled
	SDHC_NISTER_CMDC_ENABLED = 0x1
	// Position of TRFC field.
	SDHC_NISTER_TRFC_Pos = 0x1
	// Bit mask of TRFC field.
	SDHC_NISTER_TRFC_Msk = 0x2
	// Bit TRFC.
	SDHC_NISTER_TRFC = 0x2
	// Masked
	SDHC_NISTER_TRFC_MASKED = 0x0
	// Enabled
	SDHC_NISTER_TRFC_ENABLED = 0x1
	// Position of BLKGE field.
	SDHC_NISTER_BLKGE_Pos = 0x2
	// Bit mask of BLKGE field.
	SDHC_NISTER_BLKGE_Msk = 0x4
	// Bit BLKGE.
	SDHC_NISTER_BLKGE = 0x4
	// Masked
	SDHC_NISTER_BLKGE_MASKED = 0x0
	// Enabled
	SDHC_NISTER_BLKGE_ENABLED = 0x1
	// Position of DMAINT field.
	SDHC_NISTER_DMAINT_Pos = 0x3
	// Bit mask of DMAINT field.
	SDHC_NISTER_DMAINT_Msk = 0x8
	// Bit DMAINT.
	SDHC_NISTER_DMAINT = 0x8
	// Masked
	SDHC_NISTER_DMAINT_MASKED = 0x0
	// Enabled
	SDHC_NISTER_DMAINT_ENABLED = 0x1
	// Position of BWRRDY field.
	SDHC_NISTER_BWRRDY_Pos = 0x4
	// Bit mask of BWRRDY field.
	SDHC_NISTER_BWRRDY_Msk = 0x10
	// Bit BWRRDY.
	SDHC_NISTER_BWRRDY = 0x10
	// Masked
	SDHC_NISTER_BWRRDY_MASKED = 0x0
	// Enabled
	SDHC_NISTER_BWRRDY_ENABLED = 0x1
	// Position of BRDRDY field.
	SDHC_NISTER_BRDRDY_Pos = 0x5
	// Bit mask of BRDRDY field.
	SDHC_NISTER_BRDRDY_Msk = 0x20
	// Bit BRDRDY.
	SDHC_NISTER_BRDRDY = 0x20
	// Masked
	SDHC_NISTER_BRDRDY_MASKED = 0x0
	// Enabled
	SDHC_NISTER_BRDRDY_ENABLED = 0x1
	// Position of CINS field.
	SDHC_NISTER_CINS_Pos = 0x6
	// Bit mask of CINS field.
	SDHC_NISTER_CINS_Msk = 0x40
	// Bit CINS.
	SDHC_NISTER_CINS = 0x40
	// Masked
	SDHC_NISTER_CINS_MASKED = 0x0
	// Enabled
	SDHC_NISTER_CINS_ENABLED = 0x1
	// Position of CREM field.
	SDHC_NISTER_CREM_Pos = 0x7
	// Bit mask of CREM field.
	SDHC_NISTER_CREM_Msk = 0x80
	// Bit CREM.
	SDHC_NISTER_CREM = 0x80
	// Masked
	SDHC_NISTER_CREM_MASKED = 0x0
	// Enabled
	SDHC_NISTER_CREM_ENABLED = 0x1
	// Position of CINT field.
	SDHC_NISTER_CINT_Pos = 0x8
	// Bit mask of CINT field.
	SDHC_NISTER_CINT_Msk = 0x100
	// Bit CINT.
	SDHC_NISTER_CINT = 0x100
	// Masked
	SDHC_NISTER_CINT_MASKED = 0x0
	// Enabled
	SDHC_NISTER_CINT_ENABLED = 0x1

	// NISTER_EMMC_MODE: Normal Interrupt Status Enable
	// Position of CMDC field.
	SDHC_NISTER_EMMC_MODE_CMDC_Pos = 0x0
	// Bit mask of CMDC field.
	SDHC_NISTER_EMMC_MODE_CMDC_Msk = 0x1
	// Bit CMDC.
	SDHC_NISTER_EMMC_MODE_CMDC = 0x1
	// Masked
	SDHC_NISTER_EMMC_MODE_CMDC_MASKED = 0x0
	// Enabled
	SDHC_NISTER_EMMC_MODE_CMDC_ENABLED = 0x1
	// Position of TRFC field.
	SDHC_NISTER_EMMC_MODE_TRFC_Pos = 0x1
	// Bit mask of TRFC field.
	SDHC_NISTER_EMMC_MODE_TRFC_Msk = 0x2
	// Bit TRFC.
	SDHC_NISTER_EMMC_MODE_TRFC = 0x2
	// Masked
	SDHC_NISTER_EMMC_MODE_TRFC_MASKED = 0x0
	// Enabled
	SDHC_NISTER_EMMC_MODE_TRFC_ENABLED = 0x1
	// Position of BLKGE field.
	SDHC_NISTER_EMMC_MODE_BLKGE_Pos = 0x2
	// Bit mask of BLKGE field.
	SDHC_NISTER_EMMC_MODE_BLKGE_Msk = 0x4
	// Bit BLKGE.
	SDHC_NISTER_EMMC_MODE_BLKGE = 0x4
	// Masked
	SDHC_NISTER_EMMC_MODE_BLKGE_MASKED = 0x0
	// Enabled
	SDHC_NISTER_EMMC_MODE_BLKGE_ENABLED = 0x1
	// Position of DMAINT field.
	SDHC_NISTER_EMMC_MODE_DMAINT_Pos = 0x3
	// Bit mask of DMAINT field.
	SDHC_NISTER_EMMC_MODE_DMAINT_Msk = 0x8
	// Bit DMAINT.
	SDHC_NISTER_EMMC_MODE_DMAINT = 0x8
	// Masked
	SDHC_NISTER_EMMC_MODE_DMAINT_MASKED = 0x0
	// Enabled
	SDHC_NISTER_EMMC_MODE_DMAINT_ENABLED = 0x1
	// Position of BWRRDY field.
	SDHC_NISTER_EMMC_MODE_BWRRDY_Pos = 0x4
	// Bit mask of BWRRDY field.
	SDHC_NISTER_EMMC_MODE_BWRRDY_Msk = 0x10
	// Bit BWRRDY.
	SDHC_NISTER_EMMC_MODE_BWRRDY = 0x10
	// Masked
	SDHC_NISTER_EMMC_MODE_BWRRDY_MASKED = 0x0
	// Enabled
	SDHC_NISTER_EMMC_MODE_BWRRDY_ENABLED = 0x1
	// Position of BRDRDY field.
	SDHC_NISTER_EMMC_MODE_BRDRDY_Pos = 0x5
	// Bit mask of BRDRDY field.
	SDHC_NISTER_EMMC_MODE_BRDRDY_Msk = 0x20
	// Bit BRDRDY.
	SDHC_NISTER_EMMC_MODE_BRDRDY = 0x20
	// Masked
	SDHC_NISTER_EMMC_MODE_BRDRDY_MASKED = 0x0
	// Enabled
	SDHC_NISTER_EMMC_MODE_BRDRDY_ENABLED = 0x1
	// Position of BOOTAR field.
	SDHC_NISTER_EMMC_MODE_BOOTAR_Pos = 0xe
	// Bit mask of BOOTAR field.
	SDHC_NISTER_EMMC_MODE_BOOTAR_Msk = 0x4000
	// Bit BOOTAR.
	SDHC_NISTER_EMMC_MODE_BOOTAR = 0x4000

	// EISTER: Error Interrupt Status Enable
	// Position of CMDTEO field.
	SDHC_EISTER_CMDTEO_Pos = 0x0
	// Bit mask of CMDTEO field.
	SDHC_EISTER_CMDTEO_Msk = 0x1
	// Bit CMDTEO.
	SDHC_EISTER_CMDTEO = 0x1
	// Masked
	SDHC_EISTER_CMDTEO_MASKED = 0x0
	// Enabled
	SDHC_EISTER_CMDTEO_ENABLED = 0x1
	// Position of CMDCRC field.
	SDHC_EISTER_CMDCRC_Pos = 0x1
	// Bit mask of CMDCRC field.
	SDHC_EISTER_CMDCRC_Msk = 0x2
	// Bit CMDCRC.
	SDHC_EISTER_CMDCRC = 0x2
	// Masked
	SDHC_EISTER_CMDCRC_MASKED = 0x0
	// Enabled
	SDHC_EISTER_CMDCRC_ENABLED = 0x1
	// Position of CMDEND field.
	SDHC_EISTER_CMDEND_Pos = 0x2
	// Bit mask of CMDEND field.
	SDHC_EISTER_CMDEND_Msk = 0x4
	// Bit CMDEND.
	SDHC_EISTER_CMDEND = 0x4
	// Masked
	SDHC_EISTER_CMDEND_MASKED = 0x0
	// Enabled
	SDHC_EISTER_CMDEND_ENABLED = 0x1
	// Position of CMDIDX field.
	SDHC_EISTER_CMDIDX_Pos = 0x3
	// Bit mask of CMDIDX field.
	SDHC_EISTER_CMDIDX_Msk = 0x8
	// Bit CMDIDX.
	SDHC_EISTER_CMDIDX = 0x8
	// Masked
	SDHC_EISTER_CMDIDX_MASKED = 0x0
	// Enabled
	SDHC_EISTER_CMDIDX_ENABLED = 0x1
	// Position of DATTEO field.
	SDHC_EISTER_DATTEO_Pos = 0x4
	// Bit mask of DATTEO field.
	SDHC_EISTER_DATTEO_Msk = 0x10
	// Bit DATTEO.
	SDHC_EISTER_DATTEO = 0x10
	// Masked
	SDHC_EISTER_DATTEO_MASKED = 0x0
	// Enabled
	SDHC_EISTER_DATTEO_ENABLED = 0x1
	// Position of DATCRC field.
	SDHC_EISTER_DATCRC_Pos = 0x5
	// Bit mask of DATCRC field.
	SDHC_EISTER_DATCRC_Msk = 0x20
	// Bit DATCRC.
	SDHC_EISTER_DATCRC = 0x20
	// Masked
	SDHC_EISTER_DATCRC_MASKED = 0x0
	// Enabled
	SDHC_EISTER_DATCRC_ENABLED = 0x1
	// Position of DATEND field.
	SDHC_EISTER_DATEND_Pos = 0x6
	// Bit mask of DATEND field.
	SDHC_EISTER_DATEND_Msk = 0x40
	// Bit DATEND.
	SDHC_EISTER_DATEND = 0x40
	// Masked
	SDHC_EISTER_DATEND_MASKED = 0x0
	// Enabled
	SDHC_EISTER_DATEND_ENABLED = 0x1
	// Position of CURLIM field.
	SDHC_EISTER_CURLIM_Pos = 0x7
	// Bit mask of CURLIM field.
	SDHC_EISTER_CURLIM_Msk = 0x80
	// Bit CURLIM.
	SDHC_EISTER_CURLIM = 0x80
	// Masked
	SDHC_EISTER_CURLIM_MASKED = 0x0
	// Enabled
	SDHC_EISTER_CURLIM_ENABLED = 0x1
	// Position of ACMD field.
	SDHC_EISTER_ACMD_Pos = 0x8
	// Bit mask of ACMD field.
	SDHC_EISTER_ACMD_Msk = 0x100
	// Bit ACMD.
	SDHC_EISTER_ACMD = 0x100
	// Masked
	SDHC_EISTER_ACMD_MASKED = 0x0
	// Enabled
	SDHC_EISTER_ACMD_ENABLED = 0x1
	// Position of ADMA field.
	SDHC_EISTER_ADMA_Pos = 0x9
	// Bit mask of ADMA field.
	SDHC_EISTER_ADMA_Msk = 0x200
	// Bit ADMA.
	SDHC_EISTER_ADMA = 0x200
	// Masked
	SDHC_EISTER_ADMA_MASKED = 0x0
	// Enabled
	SDHC_EISTER_ADMA_ENABLED = 0x1

	// EISTER_EMMC_MODE: Error Interrupt Status Enable
	// Position of CMDTEO field.
	SDHC_EISTER_EMMC_MODE_CMDTEO_Pos = 0x0
	// Bit mask of CMDTEO field.
	SDHC_EISTER_EMMC_MODE_CMDTEO_Msk = 0x1
	// Bit CMDTEO.
	SDHC_EISTER_EMMC_MODE_CMDTEO = 0x1
	// Masked
	SDHC_EISTER_EMMC_MODE_CMDTEO_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_CMDTEO_ENABLED = 0x1
	// Position of CMDCRC field.
	SDHC_EISTER_EMMC_MODE_CMDCRC_Pos = 0x1
	// Bit mask of CMDCRC field.
	SDHC_EISTER_EMMC_MODE_CMDCRC_Msk = 0x2
	// Bit CMDCRC.
	SDHC_EISTER_EMMC_MODE_CMDCRC = 0x2
	// Masked
	SDHC_EISTER_EMMC_MODE_CMDCRC_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_CMDCRC_ENABLED = 0x1
	// Position of CMDEND field.
	SDHC_EISTER_EMMC_MODE_CMDEND_Pos = 0x2
	// Bit mask of CMDEND field.
	SDHC_EISTER_EMMC_MODE_CMDEND_Msk = 0x4
	// Bit CMDEND.
	SDHC_EISTER_EMMC_MODE_CMDEND = 0x4
	// Masked
	SDHC_EISTER_EMMC_MODE_CMDEND_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_CMDEND_ENABLED = 0x1
	// Position of CMDIDX field.
	SDHC_EISTER_EMMC_MODE_CMDIDX_Pos = 0x3
	// Bit mask of CMDIDX field.
	SDHC_EISTER_EMMC_MODE_CMDIDX_Msk = 0x8
	// Bit CMDIDX.
	SDHC_EISTER_EMMC_MODE_CMDIDX = 0x8
	// Masked
	SDHC_EISTER_EMMC_MODE_CMDIDX_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_CMDIDX_ENABLED = 0x1
	// Position of DATTEO field.
	SDHC_EISTER_EMMC_MODE_DATTEO_Pos = 0x4
	// Bit mask of DATTEO field.
	SDHC_EISTER_EMMC_MODE_DATTEO_Msk = 0x10
	// Bit DATTEO.
	SDHC_EISTER_EMMC_MODE_DATTEO = 0x10
	// Masked
	SDHC_EISTER_EMMC_MODE_DATTEO_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_DATTEO_ENABLED = 0x1
	// Position of DATCRC field.
	SDHC_EISTER_EMMC_MODE_DATCRC_Pos = 0x5
	// Bit mask of DATCRC field.
	SDHC_EISTER_EMMC_MODE_DATCRC_Msk = 0x20
	// Bit DATCRC.
	SDHC_EISTER_EMMC_MODE_DATCRC = 0x20
	// Masked
	SDHC_EISTER_EMMC_MODE_DATCRC_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_DATCRC_ENABLED = 0x1
	// Position of DATEND field.
	SDHC_EISTER_EMMC_MODE_DATEND_Pos = 0x6
	// Bit mask of DATEND field.
	SDHC_EISTER_EMMC_MODE_DATEND_Msk = 0x40
	// Bit DATEND.
	SDHC_EISTER_EMMC_MODE_DATEND = 0x40
	// Masked
	SDHC_EISTER_EMMC_MODE_DATEND_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_DATEND_ENABLED = 0x1
	// Position of CURLIM field.
	SDHC_EISTER_EMMC_MODE_CURLIM_Pos = 0x7
	// Bit mask of CURLIM field.
	SDHC_EISTER_EMMC_MODE_CURLIM_Msk = 0x80
	// Bit CURLIM.
	SDHC_EISTER_EMMC_MODE_CURLIM = 0x80
	// Masked
	SDHC_EISTER_EMMC_MODE_CURLIM_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_CURLIM_ENABLED = 0x1
	// Position of ACMD field.
	SDHC_EISTER_EMMC_MODE_ACMD_Pos = 0x8
	// Bit mask of ACMD field.
	SDHC_EISTER_EMMC_MODE_ACMD_Msk = 0x100
	// Bit ACMD.
	SDHC_EISTER_EMMC_MODE_ACMD = 0x100
	// Masked
	SDHC_EISTER_EMMC_MODE_ACMD_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_ACMD_ENABLED = 0x1
	// Position of ADMA field.
	SDHC_EISTER_EMMC_MODE_ADMA_Pos = 0x9
	// Bit mask of ADMA field.
	SDHC_EISTER_EMMC_MODE_ADMA_Msk = 0x200
	// Bit ADMA.
	SDHC_EISTER_EMMC_MODE_ADMA = 0x200
	// Masked
	SDHC_EISTER_EMMC_MODE_ADMA_MASKED = 0x0
	// Enabled
	SDHC_EISTER_EMMC_MODE_ADMA_ENABLED = 0x1
	// Position of BOOTAE field.
	SDHC_EISTER_EMMC_MODE_BOOTAE_Pos = 0xc
	// Bit mask of BOOTAE field.
	SDHC_EISTER_EMMC_MODE_BOOTAE_Msk = 0x1000
	// Bit BOOTAE.
	SDHC_EISTER_EMMC_MODE_BOOTAE = 0x1000

	// NISIER: Normal Interrupt Signal Enable
	// Position of CMDC field.
	SDHC_NISIER_CMDC_Pos = 0x0
	// Bit mask of CMDC field.
	SDHC_NISIER_CMDC_Msk = 0x1
	// Bit CMDC.
	SDHC_NISIER_CMDC = 0x1
	// Masked
	SDHC_NISIER_CMDC_MASKED = 0x0
	// Enabled
	SDHC_NISIER_CMDC_ENABLED = 0x1
	// Position of TRFC field.
	SDHC_NISIER_TRFC_Pos = 0x1
	// Bit mask of TRFC field.
	SDHC_NISIER_TRFC_Msk = 0x2
	// Bit TRFC.
	SDHC_NISIER_TRFC = 0x2
	// Masked
	SDHC_NISIER_TRFC_MASKED = 0x0
	// Enabled
	SDHC_NISIER_TRFC_ENABLED = 0x1
	// Position of BLKGE field.
	SDHC_NISIER_BLKGE_Pos = 0x2
	// Bit mask of BLKGE field.
	SDHC_NISIER_BLKGE_Msk = 0x4
	// Bit BLKGE.
	SDHC_NISIER_BLKGE = 0x4
	// Masked
	SDHC_NISIER_BLKGE_MASKED = 0x0
	// Enabled
	SDHC_NISIER_BLKGE_ENABLED = 0x1
	// Position of DMAINT field.
	SDHC_NISIER_DMAINT_Pos = 0x3
	// Bit mask of DMAINT field.
	SDHC_NISIER_DMAINT_Msk = 0x8
	// Bit DMAINT.
	SDHC_NISIER_DMAINT = 0x8
	// Masked
	SDHC_NISIER_DMAINT_MASKED = 0x0
	// Enabled
	SDHC_NISIER_DMAINT_ENABLED = 0x1
	// Position of BWRRDY field.
	SDHC_NISIER_BWRRDY_Pos = 0x4
	// Bit mask of BWRRDY field.
	SDHC_NISIER_BWRRDY_Msk = 0x10
	// Bit BWRRDY.
	SDHC_NISIER_BWRRDY = 0x10
	// Masked
	SDHC_NISIER_BWRRDY_MASKED = 0x0
	// Enabled
	SDHC_NISIER_BWRRDY_ENABLED = 0x1
	// Position of BRDRDY field.
	SDHC_NISIER_BRDRDY_Pos = 0x5
	// Bit mask of BRDRDY field.
	SDHC_NISIER_BRDRDY_Msk = 0x20
	// Bit BRDRDY.
	SDHC_NISIER_BRDRDY = 0x20
	// Masked
	SDHC_NISIER_BRDRDY_MASKED = 0x0
	// Enabled
	SDHC_NISIER_BRDRDY_ENABLED = 0x1
	// Position of CINS field.
	SDHC_NISIER_CINS_Pos = 0x6
	// Bit mask of CINS field.
	SDHC_NISIER_CINS_Msk = 0x40
	// Bit CINS.
	SDHC_NISIER_CINS = 0x40
	// Masked
	SDHC_NISIER_CINS_MASKED = 0x0
	// Enabled
	SDHC_NISIER_CINS_ENABLED = 0x1
	// Position of CREM field.
	SDHC_NISIER_CREM_Pos = 0x7
	// Bit mask of CREM field.
	SDHC_NISIER_CREM_Msk = 0x80
	// Bit CREM.
	SDHC_NISIER_CREM = 0x80
	// Masked
	SDHC_NISIER_CREM_MASKED = 0x0
	// Enabled
	SDHC_NISIER_CREM_ENABLED = 0x1
	// Position of CINT field.
	SDHC_NISIER_CINT_Pos = 0x8
	// Bit mask of CINT field.
	SDHC_NISIER_CINT_Msk = 0x100
	// Bit CINT.
	SDHC_NISIER_CINT = 0x100
	// Masked
	SDHC_NISIER_CINT_MASKED = 0x0
	// Enabled
	SDHC_NISIER_CINT_ENABLED = 0x1

	// NISIER_EMMC_MODE: Normal Interrupt Signal Enable
	// Position of CMDC field.
	SDHC_NISIER_EMMC_MODE_CMDC_Pos = 0x0
	// Bit mask of CMDC field.
	SDHC_NISIER_EMMC_MODE_CMDC_Msk = 0x1
	// Bit CMDC.
	SDHC_NISIER_EMMC_MODE_CMDC = 0x1
	// Masked
	SDHC_NISIER_EMMC_MODE_CMDC_MASKED = 0x0
	// Enabled
	SDHC_NISIER_EMMC_MODE_CMDC_ENABLED = 0x1
	// Position of TRFC field.
	SDHC_NISIER_EMMC_MODE_TRFC_Pos = 0x1
	// Bit mask of TRFC field.
	SDHC_NISIER_EMMC_MODE_TRFC_Msk = 0x2
	// Bit TRFC.
	SDHC_NISIER_EMMC_MODE_TRFC = 0x2
	// Masked
	SDHC_NISIER_EMMC_MODE_TRFC_MASKED = 0x0
	// Enabled
	SDHC_NISIER_EMMC_MODE_TRFC_ENABLED = 0x1
	// Position of BLKGE field.
	SDHC_NISIER_EMMC_MODE_BLKGE_Pos = 0x2
	// Bit mask of BLKGE field.
	SDHC_NISIER_EMMC_MODE_BLKGE_Msk = 0x4
	// Bit BLKGE.
	SDHC_NISIER_EMMC_MODE_BLKGE = 0x4
	// Masked
	SDHC_NISIER_EMMC_MODE_BLKGE_MASKED = 0x0
	// Enabled
	SDHC_NISIER_EMMC_MODE_BLKGE_ENABLED = 0x1
	// Position of DMAINT field.
	SDHC_NISIER_EMMC_MODE_DMAINT_Pos = 0x3
	// Bit mask of DMAINT field.
	SDHC_NISIER_EMMC_MODE_DMAINT_Msk = 0x8
	// Bit DMAINT.
	SDHC_NISIER_EMMC_MODE_DMAINT = 0x8
	// Masked
	SDHC_NISIER_EMMC_MODE_DMAINT_MASKED = 0x0
	// Enabled
	SDHC_NISIER_EMMC_MODE_DMAINT_ENABLED = 0x1
	// Position of BWRRDY field.
	SDHC_NISIER_EMMC_MODE_BWRRDY_Pos = 0x4
	// Bit mask of BWRRDY field.
	SDHC_NISIER_EMMC_MODE_BWRRDY_Msk = 0x10
	// Bit BWRRDY.
	SDHC_NISIER_EMMC_MODE_BWRRDY = 0x10
	// Masked
	SDHC_NISIER_EMMC_MODE_BWRRDY_MASKED = 0x0
	// Enabled
	SDHC_NISIER_EMMC_MODE_BWRRDY_ENABLED = 0x1
	// Position of BRDRDY field.
	SDHC_NISIER_EMMC_MODE_BRDRDY_Pos = 0x5
	// Bit mask of BRDRDY field.
	SDHC_NISIER_EMMC_MODE_BRDRDY_Msk = 0x20
	// Bit BRDRDY.
	SDHC_NISIER_EMMC_MODE_BRDRDY = 0x20
	// Masked
	SDHC_NISIER_EMMC_MODE_BRDRDY_MASKED = 0x0
	// Enabled
	SDHC_NISIER_EMMC_MODE_BRDRDY_ENABLED = 0x1
	// Position of BOOTAR field.
	SDHC_NISIER_EMMC_MODE_BOOTAR_Pos = 0xe
	// Bit mask of BOOTAR field.
	SDHC_NISIER_EMMC_MODE_BOOTAR_Msk = 0x4000
	// Bit BOOTAR.
	SDHC_NISIER_EMMC_MODE_BOOTAR = 0x4000

	// EISIER: Error Interrupt Signal Enable
	// Position of CMDTEO field.
	SDHC_EISIER_CMDTEO_Pos = 0x0
	// Bit mask of CMDTEO field.
	SDHC_EISIER_CMDTEO_Msk = 0x1
	// Bit CMDTEO.
	SDHC_EISIER_CMDTEO = 0x1
	// Masked
	SDHC_EISIER_CMDTEO_MASKED = 0x0
	// Enabled
	SDHC_EISIER_CMDTEO_ENABLED = 0x1
	// Position of CMDCRC field.
	SDHC_EISIER_CMDCRC_Pos = 0x1
	// Bit mask of CMDCRC field.
	SDHC_EISIER_CMDCRC_Msk = 0x2
	// Bit CMDCRC.
	SDHC_EISIER_CMDCRC = 0x2
	// Masked
	SDHC_EISIER_CMDCRC_MASKED = 0x0
	// Enabled
	SDHC_EISIER_CMDCRC_ENABLED = 0x1
	// Position of CMDEND field.
	SDHC_EISIER_CMDEND_Pos = 0x2
	// Bit mask of CMDEND field.
	SDHC_EISIER_CMDEND_Msk = 0x4
	// Bit CMDEND.
	SDHC_EISIER_CMDEND = 0x4
	// Masked
	SDHC_EISIER_CMDEND_MASKED = 0x0
	// Enabled
	SDHC_EISIER_CMDEND_ENABLED = 0x1
	// Position of CMDIDX field.
	SDHC_EISIER_CMDIDX_Pos = 0x3
	// Bit mask of CMDIDX field.
	SDHC_EISIER_CMDIDX_Msk = 0x8
	// Bit CMDIDX.
	SDHC_EISIER_CMDIDX = 0x8
	// Masked
	SDHC_EISIER_CMDIDX_MASKED = 0x0
	// Enabled
	SDHC_EISIER_CMDIDX_ENABLED = 0x1
	// Position of DATTEO field.
	SDHC_EISIER_DATTEO_Pos = 0x4
	// Bit mask of DATTEO field.
	SDHC_EISIER_DATTEO_Msk = 0x10
	// Bit DATTEO.
	SDHC_EISIER_DATTEO = 0x10
	// Masked
	SDHC_EISIER_DATTEO_MASKED = 0x0
	// Enabled
	SDHC_EISIER_DATTEO_ENABLED = 0x1
	// Position of DATCRC field.
	SDHC_EISIER_DATCRC_Pos = 0x5
	// Bit mask of DATCRC field.
	SDHC_EISIER_DATCRC_Msk = 0x20
	// Bit DATCRC.
	SDHC_EISIER_DATCRC = 0x20
	// Masked
	SDHC_EISIER_DATCRC_MASKED = 0x0
	// Enabled
	SDHC_EISIER_DATCRC_ENABLED = 0x1
	// Position of DATEND field.
	SDHC_EISIER_DATEND_Pos = 0x6
	// Bit mask of DATEND field.
	SDHC_EISIER_DATEND_Msk = 0x40
	// Bit DATEND.
	SDHC_EISIER_DATEND = 0x40
	// Masked
	SDHC_EISIER_DATEND_MASKED = 0x0
	// Enabled
	SDHC_EISIER_DATEND_ENABLED = 0x1
	// Position of CURLIM field.
	SDHC_EISIER_CURLIM_Pos = 0x7
	// Bit mask of CURLIM field.
	SDHC_EISIER_CURLIM_Msk = 0x80
	// Bit CURLIM.
	SDHC_EISIER_CURLIM = 0x80
	// Masked
	SDHC_EISIER_CURLIM_MASKED = 0x0
	// Enabled
	SDHC_EISIER_CURLIM_ENABLED = 0x1
	// Position of ACMD field.
	SDHC_EISIER_ACMD_Pos = 0x8
	// Bit mask of ACMD field.
	SDHC_EISIER_ACMD_Msk = 0x100
	// Bit ACMD.
	SDHC_EISIER_ACMD = 0x100
	// Masked
	SDHC_EISIER_ACMD_MASKED = 0x0
	// Enabled
	SDHC_EISIER_ACMD_ENABLED = 0x1
	// Position of ADMA field.
	SDHC_EISIER_ADMA_Pos = 0x9
	// Bit mask of ADMA field.
	SDHC_EISIER_ADMA_Msk = 0x200
	// Bit ADMA.
	SDHC_EISIER_ADMA = 0x200
	// Masked
	SDHC_EISIER_ADMA_MASKED = 0x0
	// Enabled
	SDHC_EISIER_ADMA_ENABLED = 0x1

	// EISIER_EMMC_MODE: Error Interrupt Signal Enable
	// Position of CMDTEO field.
	SDHC_EISIER_EMMC_MODE_CMDTEO_Pos = 0x0
	// Bit mask of CMDTEO field.
	SDHC_EISIER_EMMC_MODE_CMDTEO_Msk = 0x1
	// Bit CMDTEO.
	SDHC_EISIER_EMMC_MODE_CMDTEO = 0x1
	// Masked
	SDHC_EISIER_EMMC_MODE_CMDTEO_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_CMDTEO_ENABLED = 0x1
	// Position of CMDCRC field.
	SDHC_EISIER_EMMC_MODE_CMDCRC_Pos = 0x1
	// Bit mask of CMDCRC field.
	SDHC_EISIER_EMMC_MODE_CMDCRC_Msk = 0x2
	// Bit CMDCRC.
	SDHC_EISIER_EMMC_MODE_CMDCRC = 0x2
	// Masked
	SDHC_EISIER_EMMC_MODE_CMDCRC_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_CMDCRC_ENABLED = 0x1
	// Position of CMDEND field.
	SDHC_EISIER_EMMC_MODE_CMDEND_Pos = 0x2
	// Bit mask of CMDEND field.
	SDHC_EISIER_EMMC_MODE_CMDEND_Msk = 0x4
	// Bit CMDEND.
	SDHC_EISIER_EMMC_MODE_CMDEND = 0x4
	// Masked
	SDHC_EISIER_EMMC_MODE_CMDEND_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_CMDEND_ENABLED = 0x1
	// Position of CMDIDX field.
	SDHC_EISIER_EMMC_MODE_CMDIDX_Pos = 0x3
	// Bit mask of CMDIDX field.
	SDHC_EISIER_EMMC_MODE_CMDIDX_Msk = 0x8
	// Bit CMDIDX.
	SDHC_EISIER_EMMC_MODE_CMDIDX = 0x8
	// Masked
	SDHC_EISIER_EMMC_MODE_CMDIDX_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_CMDIDX_ENABLED = 0x1
	// Position of DATTEO field.
	SDHC_EISIER_EMMC_MODE_DATTEO_Pos = 0x4
	// Bit mask of DATTEO field.
	SDHC_EISIER_EMMC_MODE_DATTEO_Msk = 0x10
	// Bit DATTEO.
	SDHC_EISIER_EMMC_MODE_DATTEO = 0x10
	// Masked
	SDHC_EISIER_EMMC_MODE_DATTEO_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_DATTEO_ENABLED = 0x1
	// Position of DATCRC field.
	SDHC_EISIER_EMMC_MODE_DATCRC_Pos = 0x5
	// Bit mask of DATCRC field.
	SDHC_EISIER_EMMC_MODE_DATCRC_Msk = 0x20
	// Bit DATCRC.
	SDHC_EISIER_EMMC_MODE_DATCRC = 0x20
	// Masked
	SDHC_EISIER_EMMC_MODE_DATCRC_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_DATCRC_ENABLED = 0x1
	// Position of DATEND field.
	SDHC_EISIER_EMMC_MODE_DATEND_Pos = 0x6
	// Bit mask of DATEND field.
	SDHC_EISIER_EMMC_MODE_DATEND_Msk = 0x40
	// Bit DATEND.
	SDHC_EISIER_EMMC_MODE_DATEND = 0x40
	// Masked
	SDHC_EISIER_EMMC_MODE_DATEND_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_DATEND_ENABLED = 0x1
	// Position of CURLIM field.
	SDHC_EISIER_EMMC_MODE_CURLIM_Pos = 0x7
	// Bit mask of CURLIM field.
	SDHC_EISIER_EMMC_MODE_CURLIM_Msk = 0x80
	// Bit CURLIM.
	SDHC_EISIER_EMMC_MODE_CURLIM = 0x80
	// Masked
	SDHC_EISIER_EMMC_MODE_CURLIM_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_CURLIM_ENABLED = 0x1
	// Position of ACMD field.
	SDHC_EISIER_EMMC_MODE_ACMD_Pos = 0x8
	// Bit mask of ACMD field.
	SDHC_EISIER_EMMC_MODE_ACMD_Msk = 0x100
	// Bit ACMD.
	SDHC_EISIER_EMMC_MODE_ACMD = 0x100
	// Masked
	SDHC_EISIER_EMMC_MODE_ACMD_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_ACMD_ENABLED = 0x1
	// Position of ADMA field.
	SDHC_EISIER_EMMC_MODE_ADMA_Pos = 0x9
	// Bit mask of ADMA field.
	SDHC_EISIER_EMMC_MODE_ADMA_Msk = 0x200
	// Bit ADMA.
	SDHC_EISIER_EMMC_MODE_ADMA = 0x200
	// Masked
	SDHC_EISIER_EMMC_MODE_ADMA_MASKED = 0x0
	// Enabled
	SDHC_EISIER_EMMC_MODE_ADMA_ENABLED = 0x1
	// Position of BOOTAE field.
	SDHC_EISIER_EMMC_MODE_BOOTAE_Pos = 0xc
	// Bit mask of BOOTAE field.
	SDHC_EISIER_EMMC_MODE_BOOTAE_Msk = 0x1000
	// Bit BOOTAE.
	SDHC_EISIER_EMMC_MODE_BOOTAE = 0x1000

	// ACESR: Auto CMD Error Status
	// Position of ACMD12NE field.
	SDHC_ACESR_ACMD12NE_Pos = 0x0
	// Bit mask of ACMD12NE field.
	SDHC_ACESR_ACMD12NE_Msk = 0x1
	// Bit ACMD12NE.
	SDHC_ACESR_ACMD12NE = 0x1
	// Executed
	SDHC_ACESR_ACMD12NE_EXEC = 0x0
	// Not executed
	SDHC_ACESR_ACMD12NE_NOT_EXEC = 0x1
	// Position of ACMDTEO field.
	SDHC_ACESR_ACMDTEO_Pos = 0x1
	// Bit mask of ACMDTEO field.
	SDHC_ACESR_ACMDTEO_Msk = 0x2
	// Bit ACMDTEO.
	SDHC_ACESR_ACMDTEO = 0x2
	// No error
	SDHC_ACESR_ACMDTEO_NO = 0x0
	// Timeout
	SDHC_ACESR_ACMDTEO_YES = 0x1
	// Position of ACMDCRC field.
	SDHC_ACESR_ACMDCRC_Pos = 0x2
	// Bit mask of ACMDCRC field.
	SDHC_ACESR_ACMDCRC_Msk = 0x4
	// Bit ACMDCRC.
	SDHC_ACESR_ACMDCRC = 0x4
	// No error
	SDHC_ACESR_ACMDCRC_NO = 0x0
	// CRC Error Generated
	SDHC_ACESR_ACMDCRC_YES = 0x1
	// Position of ACMDEND field.
	SDHC_ACESR_ACMDEND_Pos = 0x3
	// Bit mask of ACMDEND field.
	SDHC_ACESR_ACMDEND_Msk = 0x8
	// Bit ACMDEND.
	SDHC_ACESR_ACMDEND = 0x8
	// No error
	SDHC_ACESR_ACMDEND_NO = 0x0
	// End Bit Error Generated
	SDHC_ACESR_ACMDEND_YES = 0x1
	// Position of ACMDIDX field.
	SDHC_ACESR_ACMDIDX_Pos = 0x4
	// Bit mask of ACMDIDX field.
	SDHC_ACESR_ACMDIDX_Msk = 0x10
	// Bit ACMDIDX.
	SDHC_ACESR_ACMDIDX = 0x10
	// No error
	SDHC_ACESR_ACMDIDX_NO = 0x0
	// Error
	SDHC_ACESR_ACMDIDX_YES = 0x1
	// Position of CMDNI field.
	SDHC_ACESR_CMDNI_Pos = 0x7
	// Bit mask of CMDNI field.
	SDHC_ACESR_CMDNI_Msk = 0x80
	// Bit CMDNI.
	SDHC_ACESR_CMDNI = 0x80
	// No error
	SDHC_ACESR_CMDNI_OK = 0x0
	// Not Issued
	SDHC_ACESR_CMDNI_NOT_ISSUED = 0x1

	// HC2R: Host Control 2
	// Position of UHSMS field.
	SDHC_HC2R_UHSMS_Pos = 0x0
	// Bit mask of UHSMS field.
	SDHC_HC2R_UHSMS_Msk = 0x7
	// SDR12
	SDHC_HC2R_UHSMS_SDR12 = 0x0
	// SDR25
	SDHC_HC2R_UHSMS_SDR25 = 0x1
	// SDR50
	SDHC_HC2R_UHSMS_SDR50 = 0x2
	// SDR104
	SDHC_HC2R_UHSMS_SDR104 = 0x3
	// DDR50
	SDHC_HC2R_UHSMS_DDR50 = 0x4
	// Position of VS18EN field.
	SDHC_HC2R_VS18EN_Pos = 0x3
	// Bit mask of VS18EN field.
	SDHC_HC2R_VS18EN_Msk = 0x8
	// Bit VS18EN.
	SDHC_HC2R_VS18EN = 0x8
	// 3.3V Signaling
	SDHC_HC2R_VS18EN_S33V = 0x0
	// 1.8V Signaling
	SDHC_HC2R_VS18EN_S18V = 0x1
	// Position of DRVSEL field.
	SDHC_HC2R_DRVSEL_Pos = 0x4
	// Bit mask of DRVSEL field.
	SDHC_HC2R_DRVSEL_Msk = 0x30
	// Driver Type B is Selected (Default)
	SDHC_HC2R_DRVSEL_B = 0x0
	// Driver Type A is Selected
	SDHC_HC2R_DRVSEL_A = 0x1
	// Driver Type C is Selected
	SDHC_HC2R_DRVSEL_C = 0x2
	// Driver Type D is Selected
	SDHC_HC2R_DRVSEL_D = 0x3
	// Position of EXTUN field.
	SDHC_HC2R_EXTUN_Pos = 0x6
	// Bit mask of EXTUN field.
	SDHC_HC2R_EXTUN_Msk = 0x40
	// Bit EXTUN.
	SDHC_HC2R_EXTUN = 0x40
	// Not Tuned or Tuning Completed
	SDHC_HC2R_EXTUN_NO = 0x0
	// Execute Tuning
	SDHC_HC2R_EXTUN_REQUESTED = 0x1
	// Position of SLCKSEL field.
	SDHC_HC2R_SLCKSEL_Pos = 0x7
	// Bit mask of SLCKSEL field.
	SDHC_HC2R_SLCKSEL_Msk = 0x80
	// Bit SLCKSEL.
	SDHC_HC2R_SLCKSEL = 0x80
	// Fixed clock is used to sample data
	SDHC_HC2R_SLCKSEL_FIXED = 0x0
	// Tuned clock is used to sample data
	SDHC_HC2R_SLCKSEL_TUNED = 0x1
	// Position of ASINTEN field.
	SDHC_HC2R_ASINTEN_Pos = 0xe
	// Bit mask of ASINTEN field.
	SDHC_HC2R_ASINTEN_Msk = 0x4000
	// Bit ASINTEN.
	SDHC_HC2R_ASINTEN = 0x4000
	// Disabled
	SDHC_HC2R_ASINTEN_DISABLED = 0x0
	// Enabled
	SDHC_HC2R_ASINTEN_ENABLED = 0x1
	// Position of PVALEN field.
	SDHC_HC2R_PVALEN_Pos = 0xf
	// Bit mask of PVALEN field.
	SDHC_HC2R_PVALEN_Msk = 0x8000
	// Bit PVALEN.
	SDHC_HC2R_PVALEN = 0x8000
	// SDCLK and Driver Strength are controlled by Host Controller
	SDHC_HC2R_PVALEN_HOST = 0x0
	// Automatic Selection by Preset Value is Enabled
	SDHC_HC2R_PVALEN_AUTO = 0x1

	// HC2R_EMMC_MODE: Host Control 2
	// Position of HS200EN field.
	SDHC_HC2R_EMMC_MODE_HS200EN_Pos = 0x0
	// Bit mask of HS200EN field.
	SDHC_HC2R_EMMC_MODE_HS200EN_Msk = 0xf
	// SDR12
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR12 = 0x0
	// SDR25
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR25 = 0x1
	// SDR50
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR50 = 0x2
	// SDR104
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR104 = 0x3
	// DDR50
	SDHC_HC2R_EMMC_MODE_HS200EN_DDR50 = 0x4
	// Position of DRVSEL field.
	SDHC_HC2R_EMMC_MODE_DRVSEL_Pos = 0x4
	// Bit mask of DRVSEL field.
	SDHC_HC2R_EMMC_MODE_DRVSEL_Msk = 0x30
	// Driver Type B is Selected (Default)
	SDHC_HC2R_EMMC_MODE_DRVSEL_B = 0x0
	// Driver Type A is Selected
	SDHC_HC2R_EMMC_MODE_DRVSEL_A = 0x1
	// Driver Type C is Selected
	SDHC_HC2R_EMMC_MODE_DRVSEL_C = 0x2
	// Driver Type D is Selected
	SDHC_HC2R_EMMC_MODE_DRVSEL_D = 0x3
	// Position of EXTUN field.
	SDHC_HC2R_EMMC_MODE_EXTUN_Pos = 0x6
	// Bit mask of EXTUN field.
	SDHC_HC2R_EMMC_MODE_EXTUN_Msk = 0x40
	// Bit EXTUN.
	SDHC_HC2R_EMMC_MODE_EXTUN = 0x40
	// Not Tuned or Tuning Completed
	SDHC_HC2R_EMMC_MODE_EXTUN_NO = 0x0
	// Execute Tuning
	SDHC_HC2R_EMMC_MODE_EXTUN_REQUESTED = 0x1
	// Position of SLCKSEL field.
	SDHC_HC2R_EMMC_MODE_SLCKSEL_Pos = 0x7
	// Bit mask of SLCKSEL field.
	SDHC_HC2R_EMMC_MODE_SLCKSEL_Msk = 0x80
	// Bit SLCKSEL.
	SDHC_HC2R_EMMC_MODE_SLCKSEL = 0x80
	// Fixed clock is used to sample data
	SDHC_HC2R_EMMC_MODE_SLCKSEL_FIXED = 0x0
	// Tuned clock is used to sample data
	SDHC_HC2R_EMMC_MODE_SLCKSEL_TUNED = 0x1
	// Position of PVALEN field.
	SDHC_HC2R_EMMC_MODE_PVALEN_Pos = 0xf
	// Bit mask of PVALEN field.
	SDHC_HC2R_EMMC_MODE_PVALEN_Msk = 0x8000
	// Bit PVALEN.
	SDHC_HC2R_EMMC_MODE_PVALEN = 0x8000
	// SDCLK and Driver Strength are controlled by Host Controller
	SDHC_HC2R_EMMC_MODE_PVALEN_HOST = 0x0
	// Automatic Selection by Preset Value is Enabled
	SDHC_HC2R_EMMC_MODE_PVALEN_AUTO = 0x1

	// CA0R: Capabilities 0
	// Position of TEOCLKF field.
	SDHC_CA0R_TEOCLKF_Pos = 0x0
	// Bit mask of TEOCLKF field.
	SDHC_CA0R_TEOCLKF_Msk = 0x3f
	// Get information via another method
	SDHC_CA0R_TEOCLKF_OTHER = 0x0
	// Position of TEOCLKU field.
	SDHC_CA0R_TEOCLKU_Pos = 0x7
	// Bit mask of TEOCLKU field.
	SDHC_CA0R_TEOCLKU_Msk = 0x80
	// Bit TEOCLKU.
	SDHC_CA0R_TEOCLKU = 0x80
	// KHz
	SDHC_CA0R_TEOCLKU_KHZ = 0x0
	// MHz
	SDHC_CA0R_TEOCLKU_MHZ = 0x1
	// Position of BASECLKF field.
	SDHC_CA0R_BASECLKF_Pos = 0x8
	// Bit mask of BASECLKF field.
	SDHC_CA0R_BASECLKF_Msk = 0xff00
	// Get information via another method
	SDHC_CA0R_BASECLKF_OTHER = 0x0
	// Position of MAXBLKL field.
	SDHC_CA0R_MAXBLKL_Pos = 0x10
	// Bit mask of MAXBLKL field.
	SDHC_CA0R_MAXBLKL_Msk = 0x30000
	// 512 bytes
	SDHC_CA0R_MAXBLKL_512 = 0x0
	// 1024 bytes
	SDHC_CA0R_MAXBLKL_1024 = 0x1
	// 2048 bytes
	SDHC_CA0R_MAXBLKL_2048 = 0x2
	// Position of ED8SUP field.
	SDHC_CA0R_ED8SUP_Pos = 0x12
	// Bit mask of ED8SUP field.
	SDHC_CA0R_ED8SUP_Msk = 0x40000
	// Bit ED8SUP.
	SDHC_CA0R_ED8SUP = 0x40000
	// 8-bit Bus Width not Supported
	SDHC_CA0R_ED8SUP_NO = 0x0
	// 8-bit Bus Width Supported
	SDHC_CA0R_ED8SUP_YES = 0x1
	// Position of ADMA2SUP field.
	SDHC_CA0R_ADMA2SUP_Pos = 0x13
	// Bit mask of ADMA2SUP field.
	SDHC_CA0R_ADMA2SUP_Msk = 0x80000
	// Bit ADMA2SUP.
	SDHC_CA0R_ADMA2SUP = 0x80000
	// ADMA2 not Supported
	SDHC_CA0R_ADMA2SUP_NO = 0x0
	// ADMA2 Supported
	SDHC_CA0R_ADMA2SUP_YES = 0x1
	// Position of HSSUP field.
	SDHC_CA0R_HSSUP_Pos = 0x15
	// Bit mask of HSSUP field.
	SDHC_CA0R_HSSUP_Msk = 0x200000
	// Bit HSSUP.
	SDHC_CA0R_HSSUP = 0x200000
	// High Speed not Supported
	SDHC_CA0R_HSSUP_NO = 0x0
	// High Speed Supported
	SDHC_CA0R_HSSUP_YES = 0x1
	// Position of SDMASUP field.
	SDHC_CA0R_SDMASUP_Pos = 0x16
	// Bit mask of SDMASUP field.
	SDHC_CA0R_SDMASUP_Msk = 0x400000
	// Bit SDMASUP.
	SDHC_CA0R_SDMASUP = 0x400000
	// SDMA not Supported
	SDHC_CA0R_SDMASUP_NO = 0x0
	// SDMA Supported
	SDHC_CA0R_SDMASUP_YES = 0x1
	// Position of SRSUP field.
	SDHC_CA0R_SRSUP_Pos = 0x17
	// Bit mask of SRSUP field.
	SDHC_CA0R_SRSUP_Msk = 0x800000
	// Bit SRSUP.
	SDHC_CA0R_SRSUP = 0x800000
	// Suspend/Resume not Supported
	SDHC_CA0R_SRSUP_NO = 0x0
	// Suspend/Resume Supported
	SDHC_CA0R_SRSUP_YES = 0x1
	// Position of V33VSUP field.
	SDHC_CA0R_V33VSUP_Pos = 0x18
	// Bit mask of V33VSUP field.
	SDHC_CA0R_V33VSUP_Msk = 0x1000000
	// Bit V33VSUP.
	SDHC_CA0R_V33VSUP = 0x1000000
	// 3.3V Not Supported
	SDHC_CA0R_V33VSUP_NO = 0x0
	// 3.3V Supported
	SDHC_CA0R_V33VSUP_YES = 0x1
	// Position of V30VSUP field.
	SDHC_CA0R_V30VSUP_Pos = 0x19
	// Bit mask of V30VSUP field.
	SDHC_CA0R_V30VSUP_Msk = 0x2000000
	// Bit V30VSUP.
	SDHC_CA0R_V30VSUP = 0x2000000
	// 3.0V Not Supported
	SDHC_CA0R_V30VSUP_NO = 0x0
	// 3.0V Supported
	SDHC_CA0R_V30VSUP_YES = 0x1
	// Position of V18VSUP field.
	SDHC_CA0R_V18VSUP_Pos = 0x1a
	// Bit mask of V18VSUP field.
	SDHC_CA0R_V18VSUP_Msk = 0x4000000
	// Bit V18VSUP.
	SDHC_CA0R_V18VSUP = 0x4000000
	// 1.8V Not Supported
	SDHC_CA0R_V18VSUP_NO = 0x0
	// 1.8V Supported
	SDHC_CA0R_V18VSUP_YES = 0x1
	// Position of SB64SUP field.
	SDHC_CA0R_SB64SUP_Pos = 0x1c
	// Bit mask of SB64SUP field.
	SDHC_CA0R_SB64SUP_Msk = 0x10000000
	// Bit SB64SUP.
	SDHC_CA0R_SB64SUP = 0x10000000
	// 32-bit Address Descriptors and System Bus
	SDHC_CA0R_SB64SUP_NO = 0x0
	// 64-bit Address Descriptors and System Bus
	SDHC_CA0R_SB64SUP_YES = 0x1
	// Position of ASINTSUP field.
	SDHC_CA0R_ASINTSUP_Pos = 0x1d
	// Bit mask of ASINTSUP field.
	SDHC_CA0R_ASINTSUP_Msk = 0x20000000
	// Bit ASINTSUP.
	SDHC_CA0R_ASINTSUP = 0x20000000
	// Asynchronous Interrupt not Supported
	SDHC_CA0R_ASINTSUP_NO = 0x0
	// Asynchronous Interrupt supported
	SDHC_CA0R_ASINTSUP_YES = 0x1
	// Position of SLTYPE field.
	SDHC_CA0R_SLTYPE_Pos = 0x1e
	// Bit mask of SLTYPE field.
	SDHC_CA0R_SLTYPE_Msk = 0xc0000000
	// Removable Card Slot
	SDHC_CA0R_SLTYPE_REMOVABLE = 0x0
	// Embedded Slot for One Device
	SDHC_CA0R_SLTYPE_EMBEDDED = 0x1

	// CA1R: Capabilities 1
	// Position of SDR50SUP field.
	SDHC_CA1R_SDR50SUP_Pos = 0x0
	// Bit mask of SDR50SUP field.
	SDHC_CA1R_SDR50SUP_Msk = 0x1
	// Bit SDR50SUP.
	SDHC_CA1R_SDR50SUP = 0x1
	// SDR50 is Not Supported
	SDHC_CA1R_SDR50SUP_NO = 0x0
	// SDR50 is Supported
	SDHC_CA1R_SDR50SUP_YES = 0x1
	// Position of SDR104SUP field.
	SDHC_CA1R_SDR104SUP_Pos = 0x1
	// Bit mask of SDR104SUP field.
	SDHC_CA1R_SDR104SUP_Msk = 0x2
	// Bit SDR104SUP.
	SDHC_CA1R_SDR104SUP = 0x2
	// SDR104 is Not Supported
	SDHC_CA1R_SDR104SUP_NO = 0x0
	// SDR104 is Supported
	SDHC_CA1R_SDR104SUP_YES = 0x1
	// Position of DDR50SUP field.
	SDHC_CA1R_DDR50SUP_Pos = 0x2
	// Bit mask of DDR50SUP field.
	SDHC_CA1R_DDR50SUP_Msk = 0x4
	// Bit DDR50SUP.
	SDHC_CA1R_DDR50SUP = 0x4
	// DDR50 is Not Supported
	SDHC_CA1R_DDR50SUP_NO = 0x0
	// DDR50 is Supported
	SDHC_CA1R_DDR50SUP_YES = 0x1
	// Position of DRVASUP field.
	SDHC_CA1R_DRVASUP_Pos = 0x4
	// Bit mask of DRVASUP field.
	SDHC_CA1R_DRVASUP_Msk = 0x10
	// Bit DRVASUP.
	SDHC_CA1R_DRVASUP = 0x10
	// Driver Type A is Not Supported
	SDHC_CA1R_DRVASUP_NO = 0x0
	// Driver Type A is Supported
	SDHC_CA1R_DRVASUP_YES = 0x1
	// Position of DRVCSUP field.
	SDHC_CA1R_DRVCSUP_Pos = 0x5
	// Bit mask of DRVCSUP field.
	SDHC_CA1R_DRVCSUP_Msk = 0x20
	// Bit DRVCSUP.
	SDHC_CA1R_DRVCSUP = 0x20
	// Driver Type C is Not Supported
	SDHC_CA1R_DRVCSUP_NO = 0x0
	// Driver Type C is Supported
	SDHC_CA1R_DRVCSUP_YES = 0x1
	// Position of DRVDSUP field.
	SDHC_CA1R_DRVDSUP_Pos = 0x6
	// Bit mask of DRVDSUP field.
	SDHC_CA1R_DRVDSUP_Msk = 0x40
	// Bit DRVDSUP.
	SDHC_CA1R_DRVDSUP = 0x40
	// Driver Type D is Not Supported
	SDHC_CA1R_DRVDSUP_NO = 0x0
	// Driver Type D is Supported
	SDHC_CA1R_DRVDSUP_YES = 0x1
	// Position of TCNTRT field.
	SDHC_CA1R_TCNTRT_Pos = 0x8
	// Bit mask of TCNTRT field.
	SDHC_CA1R_TCNTRT_Msk = 0xf00
	// Re-Tuning Timer disabled
	SDHC_CA1R_TCNTRT_DISABLED = 0x0
	// 1 second
	SDHC_CA1R_TCNTRT_1S = 0x1
	// 2 seconds
	SDHC_CA1R_TCNTRT_2S = 0x2
	// 4 seconds
	SDHC_CA1R_TCNTRT_4S = 0x3
	// 8 seconds
	SDHC_CA1R_TCNTRT_8S = 0x4
	// 16 seconds
	SDHC_CA1R_TCNTRT_16S = 0x5
	// 32 seconds
	SDHC_CA1R_TCNTRT_32S = 0x6
	// 64 seconds
	SDHC_CA1R_TCNTRT_64S = 0x7
	// 128 seconds
	SDHC_CA1R_TCNTRT_128S = 0x8
	// 256 seconds
	SDHC_CA1R_TCNTRT_256S = 0x9
	// 512 seconds
	SDHC_CA1R_TCNTRT_512S = 0xa
	// 1024 seconds
	SDHC_CA1R_TCNTRT_1024S = 0xb
	// Get information from other source
	SDHC_CA1R_TCNTRT_OTHER = 0xf
	// Position of TSDR50 field.
	SDHC_CA1R_TSDR50_Pos = 0xd
	// Bit mask of TSDR50 field.
	SDHC_CA1R_TSDR50_Msk = 0x2000
	// Bit TSDR50.
	SDHC_CA1R_TSDR50 = 0x2000
	// SDR50 does not require tuning
	SDHC_CA1R_TSDR50_NO = 0x0
	// SDR50 requires tuning
	SDHC_CA1R_TSDR50_YES = 0x1
	// Position of CLKMULT field.
	SDHC_CA1R_CLKMULT_Pos = 0x10
	// Bit mask of CLKMULT field.
	SDHC_CA1R_CLKMULT_Msk = 0xff0000
	// Clock Multiplier is Not Supported
	SDHC_CA1R_CLKMULT_NO = 0x0

	// MCCAR: Maximum Current Capabilities
	// Position of MAXCUR33V field.
	SDHC_MCCAR_MAXCUR33V_Pos = 0x0
	// Bit mask of MAXCUR33V field.
	SDHC_MCCAR_MAXCUR33V_Msk = 0xff
	// Get information via another method
	SDHC_MCCAR_MAXCUR33V_OTHER = 0x0
	// 4mA
	SDHC_MCCAR_MAXCUR33V_4MA = 0x1
	// 8mA
	SDHC_MCCAR_MAXCUR33V_8MA = 0x2
	// 12mA
	SDHC_MCCAR_MAXCUR33V_12MA = 0x3
	// Position of MAXCUR30V field.
	SDHC_MCCAR_MAXCUR30V_Pos = 0x8
	// Bit mask of MAXCUR30V field.
	SDHC_MCCAR_MAXCUR30V_Msk = 0xff00
	// Get information via another method
	SDHC_MCCAR_MAXCUR30V_OTHER = 0x0
	// 4mA
	SDHC_MCCAR_MAXCUR30V_4MA = 0x1
	// 8mA
	SDHC_MCCAR_MAXCUR30V_8MA = 0x2
	// 12mA
	SDHC_MCCAR_MAXCUR30V_12MA = 0x3
	// Position of MAXCUR18V field.
	SDHC_MCCAR_MAXCUR18V_Pos = 0x10
	// Bit mask of MAXCUR18V field.
	SDHC_MCCAR_MAXCUR18V_Msk = 0xff0000
	// Get information via another method
	SDHC_MCCAR_MAXCUR18V_OTHER = 0x0
	// 4mA
	SDHC_MCCAR_MAXCUR18V_4MA = 0x1
	// 8mA
	SDHC_MCCAR_MAXCUR18V_8MA = 0x2
	// 12mA
	SDHC_MCCAR_MAXCUR18V_12MA = 0x3

	// FERACES: Force Event for Auto CMD Error Status
	// Position of ACMD12NE field.
	SDHC_FERACES_ACMD12NE_Pos = 0x0
	// Bit mask of ACMD12NE field.
	SDHC_FERACES_ACMD12NE_Msk = 0x1
	// Bit ACMD12NE.
	SDHC_FERACES_ACMD12NE = 0x1
	// No Interrupt
	SDHC_FERACES_ACMD12NE_NO = 0x0
	// Interrupt is generated
	SDHC_FERACES_ACMD12NE_YES = 0x1
	// Position of ACMDTEO field.
	SDHC_FERACES_ACMDTEO_Pos = 0x1
	// Bit mask of ACMDTEO field.
	SDHC_FERACES_ACMDTEO_Msk = 0x2
	// Bit ACMDTEO.
	SDHC_FERACES_ACMDTEO = 0x2
	// No Interrupt
	SDHC_FERACES_ACMDTEO_NO = 0x0
	// Interrupt is generated
	SDHC_FERACES_ACMDTEO_YES = 0x1
	// Position of ACMDCRC field.
	SDHC_FERACES_ACMDCRC_Pos = 0x2
	// Bit mask of ACMDCRC field.
	SDHC_FERACES_ACMDCRC_Msk = 0x4
	// Bit ACMDCRC.
	SDHC_FERACES_ACMDCRC = 0x4
	// No Interrupt
	SDHC_FERACES_ACMDCRC_NO = 0x0
	// Interrupt is generated
	SDHC_FERACES_ACMDCRC_YES = 0x1
	// Position of ACMDEND field.
	SDHC_FERACES_ACMDEND_Pos = 0x3
	// Bit mask of ACMDEND field.
	SDHC_FERACES_ACMDEND_Msk = 0x8
	// Bit ACMDEND.
	SDHC_FERACES_ACMDEND = 0x8
	// No Interrupt
	SDHC_FERACES_ACMDEND_NO = 0x0
	// Interrupt is generated
	SDHC_FERACES_ACMDEND_YES = 0x1
	// Position of ACMDIDX field.
	SDHC_FERACES_ACMDIDX_Pos = 0x4
	// Bit mask of ACMDIDX field.
	SDHC_FERACES_ACMDIDX_Msk = 0x10
	// Bit ACMDIDX.
	SDHC_FERACES_ACMDIDX = 0x10
	// No Interrupt
	SDHC_FERACES_ACMDIDX_NO = 0x0
	// Interrupt is generated
	SDHC_FERACES_ACMDIDX_YES = 0x1
	// Position of CMDNI field.
	SDHC_FERACES_CMDNI_Pos = 0x7
	// Bit mask of CMDNI field.
	SDHC_FERACES_CMDNI_Msk = 0x80
	// Bit CMDNI.
	SDHC_FERACES_CMDNI = 0x80
	// No Interrupt
	SDHC_FERACES_CMDNI_NO = 0x0
	// Interrupt is generated
	SDHC_FERACES_CMDNI_YES = 0x1

	// FEREIS: Force Event for Error Interrupt Status
	// Position of CMDTEO field.
	SDHC_FEREIS_CMDTEO_Pos = 0x0
	// Bit mask of CMDTEO field.
	SDHC_FEREIS_CMDTEO_Msk = 0x1
	// Bit CMDTEO.
	SDHC_FEREIS_CMDTEO = 0x1
	// No Interrupt
	SDHC_FEREIS_CMDTEO_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_CMDTEO_YES = 0x1
	// Position of CMDCRC field.
	SDHC_FEREIS_CMDCRC_Pos = 0x1
	// Bit mask of CMDCRC field.
	SDHC_FEREIS_CMDCRC_Msk = 0x2
	// Bit CMDCRC.
	SDHC_FEREIS_CMDCRC = 0x2
	// No Interrupt
	SDHC_FEREIS_CMDCRC_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_CMDCRC_YES = 0x1
	// Position of CMDEND field.
	SDHC_FEREIS_CMDEND_Pos = 0x2
	// Bit mask of CMDEND field.
	SDHC_FEREIS_CMDEND_Msk = 0x4
	// Bit CMDEND.
	SDHC_FEREIS_CMDEND = 0x4
	// No Interrupt
	SDHC_FEREIS_CMDEND_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_CMDEND_YES = 0x1
	// Position of CMDIDX field.
	SDHC_FEREIS_CMDIDX_Pos = 0x3
	// Bit mask of CMDIDX field.
	SDHC_FEREIS_CMDIDX_Msk = 0x8
	// Bit CMDIDX.
	SDHC_FEREIS_CMDIDX = 0x8
	// No Interrupt
	SDHC_FEREIS_CMDIDX_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_CMDIDX_YES = 0x1
	// Position of DATTEO field.
	SDHC_FEREIS_DATTEO_Pos = 0x4
	// Bit mask of DATTEO field.
	SDHC_FEREIS_DATTEO_Msk = 0x10
	// Bit DATTEO.
	SDHC_FEREIS_DATTEO = 0x10
	// No Interrupt
	SDHC_FEREIS_DATTEO_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_DATTEO_YES = 0x1
	// Position of DATCRC field.
	SDHC_FEREIS_DATCRC_Pos = 0x5
	// Bit mask of DATCRC field.
	SDHC_FEREIS_DATCRC_Msk = 0x20
	// Bit DATCRC.
	SDHC_FEREIS_DATCRC = 0x20
	// No Interrupt
	SDHC_FEREIS_DATCRC_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_DATCRC_YES = 0x1
	// Position of DATEND field.
	SDHC_FEREIS_DATEND_Pos = 0x6
	// Bit mask of DATEND field.
	SDHC_FEREIS_DATEND_Msk = 0x40
	// Bit DATEND.
	SDHC_FEREIS_DATEND = 0x40
	// No Interrupt
	SDHC_FEREIS_DATEND_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_DATEND_YES = 0x1
	// Position of CURLIM field.
	SDHC_FEREIS_CURLIM_Pos = 0x7
	// Bit mask of CURLIM field.
	SDHC_FEREIS_CURLIM_Msk = 0x80
	// Bit CURLIM.
	SDHC_FEREIS_CURLIM = 0x80
	// No Interrupt
	SDHC_FEREIS_CURLIM_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_CURLIM_YES = 0x1
	// Position of ACMD field.
	SDHC_FEREIS_ACMD_Pos = 0x8
	// Bit mask of ACMD field.
	SDHC_FEREIS_ACMD_Msk = 0x100
	// Bit ACMD.
	SDHC_FEREIS_ACMD = 0x100
	// No Interrupt
	SDHC_FEREIS_ACMD_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_ACMD_YES = 0x1
	// Position of ADMA field.
	SDHC_FEREIS_ADMA_Pos = 0x9
	// Bit mask of ADMA field.
	SDHC_FEREIS_ADMA_Msk = 0x200
	// Bit ADMA.
	SDHC_FEREIS_ADMA = 0x200
	// No Interrupt
	SDHC_FEREIS_ADMA_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_ADMA_YES = 0x1
	// Position of BOOTAE field.
	SDHC_FEREIS_BOOTAE_Pos = 0xc
	// Bit mask of BOOTAE field.
	SDHC_FEREIS_BOOTAE_Msk = 0x1000
	// Bit BOOTAE.
	SDHC_FEREIS_BOOTAE = 0x1000
	// No Interrupt
	SDHC_FEREIS_BOOTAE_NO = 0x0
	// Interrupt is generated
	SDHC_FEREIS_BOOTAE_YES = 0x1

	// AESR: ADMA Error Status
	// Position of ERRST field.
	SDHC_AESR_ERRST_Pos = 0x0
	// Bit mask of ERRST field.
	SDHC_AESR_ERRST_Msk = 0x3
	// ST_STOP (Stop DMA)
	SDHC_AESR_ERRST_STOP = 0x0
	// ST_FDS (Fetch Descriptor)
	SDHC_AESR_ERRST_FDS = 0x1
	// ST_TFR (Transfer Data)
	SDHC_AESR_ERRST_TFR = 0x3
	// Position of LMIS field.
	SDHC_AESR_LMIS_Pos = 0x2
	// Bit mask of LMIS field.
	SDHC_AESR_LMIS_Msk = 0x4
	// Bit LMIS.
	SDHC_AESR_LMIS = 0x4
	// No Error
	SDHC_AESR_LMIS_NO = 0x0
	// Error
	SDHC_AESR_LMIS_YES = 0x1

	// ASAR: ADMA System Address n
	// Position of ADMASA field.
	SDHC_ASAR_ADMASA_Pos = 0x0
	// Bit mask of ADMASA field.
	SDHC_ASAR_ADMASA_Msk = 0xffffffff

	// PVR: Preset Value n
	// Position of SDCLKFSEL field.
	SDHC_PVR_SDCLKFSEL_Pos = 0x0
	// Bit mask of SDCLKFSEL field.
	SDHC_PVR_SDCLKFSEL_Msk = 0x3ff
	// Position of CLKGSEL field.
	SDHC_PVR_CLKGSEL_Pos = 0xa
	// Bit mask of CLKGSEL field.
	SDHC_PVR_CLKGSEL_Msk = 0x400
	// Bit CLKGSEL.
	SDHC_PVR_CLKGSEL = 0x400
	// Host Controller Ver2.00 Compatible Clock Generator (Divider)
	SDHC_PVR_CLKGSEL_DIV = 0x0
	// Programmable Clock Generator
	SDHC_PVR_CLKGSEL_PROG = 0x1
	// Position of DRVSEL field.
	SDHC_PVR_DRVSEL_Pos = 0xe
	// Bit mask of DRVSEL field.
	SDHC_PVR_DRVSEL_Msk = 0xc000
	// Driver Type B is Selected
	SDHC_PVR_DRVSEL_B = 0x0
	// Driver Type A is Selected
	SDHC_PVR_DRVSEL_A = 0x1
	// Driver Type C is Selected
	SDHC_PVR_DRVSEL_C = 0x2
	// Driver Type D is Selected
	SDHC_PVR_DRVSEL_D = 0x3

	// SISR: Slot Interrupt Status
	// Position of INTSSL field.
	SDHC_SISR_INTSSL_Pos = 0x0
	// Bit mask of INTSSL field.
	SDHC_SISR_INTSSL_Msk = 0x1
	// Bit INTSSL.
	SDHC_SISR_INTSSL = 0x1

	// HCVR: Host Controller Version
	// Position of SVER field.
	SDHC_HCVR_SVER_Pos = 0x0
	// Bit mask of SVER field.
	SDHC_HCVR_SVER_Msk = 0xff
	// Position of VVER field.
	SDHC_HCVR_VVER_Pos = 0x8
	// Bit mask of VVER field.
	SDHC_HCVR_VVER_Msk = 0xff00

	// MC1R: MMC Control 1
	// Position of CMDTYP field.
	SDHC_MC1R_CMDTYP_Pos = 0x0
	// Bit mask of CMDTYP field.
	SDHC_MC1R_CMDTYP_Msk = 0x3
	// Not a MMC specific command
	SDHC_MC1R_CMDTYP_NORMAL = 0x0
	// Wait IRQ Command
	SDHC_MC1R_CMDTYP_WAITIRQ = 0x1
	// Stream Command
	SDHC_MC1R_CMDTYP_STREAM = 0x2
	// Boot Command
	SDHC_MC1R_CMDTYP_BOOT = 0x3
	// Position of DDR field.
	SDHC_MC1R_DDR_Pos = 0x3
	// Bit mask of DDR field.
	SDHC_MC1R_DDR_Msk = 0x8
	// Bit DDR.
	SDHC_MC1R_DDR = 0x8
	// Position of OPD field.
	SDHC_MC1R_OPD_Pos = 0x4
	// Bit mask of OPD field.
	SDHC_MC1R_OPD_Msk = 0x10
	// Bit OPD.
	SDHC_MC1R_OPD = 0x10
	// Position of BOOTA field.
	SDHC_MC1R_BOOTA_Pos = 0x5
	// Bit mask of BOOTA field.
	SDHC_MC1R_BOOTA_Msk = 0x20
	// Bit BOOTA.
	SDHC_MC1R_BOOTA = 0x20
	// Position of RSTN field.
	SDHC_MC1R_RSTN_Pos = 0x6
	// Bit mask of RSTN field.
	SDHC_MC1R_RSTN_Msk = 0x40
	// Bit RSTN.
	SDHC_MC1R_RSTN = 0x40
	// Position of FCD field.
	SDHC_MC1R_FCD_Pos = 0x7
	// Bit mask of FCD field.
	SDHC_MC1R_FCD_Msk = 0x80
	// Bit FCD.
	SDHC_MC1R_FCD = 0x80

	// MC2R: MMC Control 2
	// Position of SRESP field.
	SDHC_MC2R_SRESP_Pos = 0x0
	// Bit mask of SRESP field.
	SDHC_MC2R_SRESP_Msk = 0x1
	// Bit SRESP.
	SDHC_MC2R_SRESP = 0x1
	// Position of ABOOT field.
	SDHC_MC2R_ABOOT_Pos = 0x1
	// Bit mask of ABOOT field.
	SDHC_MC2R_ABOOT_Msk = 0x2
	// Bit ABOOT.
	SDHC_MC2R_ABOOT = 0x2

	// ACR: AHB Control
	// Position of BMAX field.
	SDHC_ACR_BMAX_Pos = 0x0
	// Bit mask of BMAX field.
	SDHC_ACR_BMAX_Msk    = 0x3
	SDHC_ACR_BMAX_INCR16 = 0x0
	SDHC_ACR_BMAX_INCR8  = 0x1
	SDHC_ACR_BMAX_INCR4  = 0x2
	SDHC_ACR_BMAX_SINGLE = 0x3

	// CC2R: Clock Control 2
	// Position of FSDCLKD field.
	SDHC_CC2R_FSDCLKD_Pos = 0x0
	// Bit mask of FSDCLKD field.
	SDHC_CC2R_FSDCLKD_Msk = 0x1
	// Bit FSDCLKD.
	SDHC_CC2R_FSDCLKD = 0x1
	// No effect
	SDHC_CC2R_FSDCLKD_NOEFFECT = 0x0
	// SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled
	SDHC_CC2R_FSDCLKD_DISABLE = 0x1

	// CACR: Capabilities Control
	// Position of CAPWREN field.
	SDHC_CACR_CAPWREN_Pos = 0x0
	// Bit mask of CAPWREN field.
	SDHC_CACR_CAPWREN_Msk = 0x1
	// Bit CAPWREN.
	SDHC_CACR_CAPWREN = 0x1
	// Position of KEY field.
	SDHC_CACR_KEY_Pos = 0x8
	// Bit mask of KEY field.
	SDHC_CACR_KEY_Msk = 0xff00

	// DBGR: Debug
	// Position of NIDBG field.
	SDHC_DBGR_NIDBG_Pos = 0x0
	// Bit mask of NIDBG field.
	SDHC_DBGR_NIDBG_Msk = 0x1
	// Bit NIDBG.
	SDHC_DBGR_NIDBG = 0x1
	// Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer)
	SDHC_DBGR_NIDBG_IDBG = 0x0
	// Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer)
	SDHC_DBGR_NIDBG_NIDBG = 0x1
)

// Bitfields for SERCOM0: Serial Communication Interface
const ()

// Bitfields for SERCOM0_I2CM: Serial Communication Interface - I2CM
const (
	// CTRLA: I2CM Control A
	// Position of SWRST field.
	SERCOM_I2CM_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_I2CM_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_I2CM_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_I2CM_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_I2CM_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_I2CM_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	SERCOM_I2CM_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	SERCOM_I2CM_CTRLA_MODE_Msk = 0x1c
	// USART with external clock
	SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK = 0x0
	// USART with internal clock
	SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK = 0x1
	// SPI in slave operation
	SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE = 0x2
	// SPI in master operation
	SERCOM_I2CM_CTRLA_MODE_SPI_MASTER = 0x3
	// I2C slave operation
	SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE = 0x4
	// I2C master operation
	SERCOM_I2CM_CTRLA_MODE_I2C_MASTER = 0x5
	// Position of RUNSTDBY field.
	SERCOM_I2CM_CTRLA_RUNSTDBY_Pos = 0x7
	// Bit mask of RUNSTDBY field.
	SERCOM_I2CM_CTRLA_RUNSTDBY_Msk = 0x80
	// Bit RUNSTDBY.
	SERCOM_I2CM_CTRLA_RUNSTDBY = 0x80
	// Position of PINOUT field.
	SERCOM_I2CM_CTRLA_PINOUT_Pos = 0x10
	// Bit mask of PINOUT field.
	SERCOM_I2CM_CTRLA_PINOUT_Msk = 0x10000
	// Bit PINOUT.
	SERCOM_I2CM_CTRLA_PINOUT = 0x10000
	// Position of SDAHOLD field.
	SERCOM_I2CM_CTRLA_SDAHOLD_Pos = 0x14
	// Bit mask of SDAHOLD field.
	SERCOM_I2CM_CTRLA_SDAHOLD_Msk = 0x300000
	// Disabled
	SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE = 0x0
	// 50-100ns hold time
	SERCOM_I2CM_CTRLA_SDAHOLD_75NS = 0x1
	// 300-600ns hold time
	SERCOM_I2CM_CTRLA_SDAHOLD_450NS = 0x2
	// 400-800ns hold time
	SERCOM_I2CM_CTRLA_SDAHOLD_600NS = 0x3
	// Position of MEXTTOEN field.
	SERCOM_I2CM_CTRLA_MEXTTOEN_Pos = 0x16
	// Bit mask of MEXTTOEN field.
	SERCOM_I2CM_CTRLA_MEXTTOEN_Msk = 0x400000
	// Bit MEXTTOEN.
	SERCOM_I2CM_CTRLA_MEXTTOEN = 0x400000
	// Position of SEXTTOEN field.
	SERCOM_I2CM_CTRLA_SEXTTOEN_Pos = 0x17
	// Bit mask of SEXTTOEN field.
	SERCOM_I2CM_CTRLA_SEXTTOEN_Msk = 0x800000
	// Bit SEXTTOEN.
	SERCOM_I2CM_CTRLA_SEXTTOEN = 0x800000
	// Position of SPEED field.
	SERCOM_I2CM_CTRLA_SPEED_Pos = 0x18
	// Bit mask of SPEED field.
	SERCOM_I2CM_CTRLA_SPEED_Msk = 0x3000000
	// Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
	SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE = 0x0
	// Fast-mode Plus Upto 1MHz
	SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE = 0x1
	// High-speed mode Upto 3.4MHz
	SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE = 0x2
	// Position of SCLSM field.
	SERCOM_I2CM_CTRLA_SCLSM_Pos = 0x1b
	// Bit mask of SCLSM field.
	SERCOM_I2CM_CTRLA_SCLSM_Msk = 0x8000000
	// Bit SCLSM.
	SERCOM_I2CM_CTRLA_SCLSM = 0x8000000
	// Position of INACTOUT field.
	SERCOM_I2CM_CTRLA_INACTOUT_Pos = 0x1c
	// Bit mask of INACTOUT field.
	SERCOM_I2CM_CTRLA_INACTOUT_Msk = 0x30000000
	// Disabled
	SERCOM_I2CM_CTRLA_INACTOUT_DISABLE = 0x0
	// 5-6 SCL Time-Out(50-60us)
	SERCOM_I2CM_CTRLA_INACTOUT_55US = 0x1
	// 10-11 SCL Time-Out(100-110us)
	SERCOM_I2CM_CTRLA_INACTOUT_105US = 0x2
	// 20-21 SCL Time-Out(200-210us)
	SERCOM_I2CM_CTRLA_INACTOUT_205US = 0x3
	// Position of LOWTOUTEN field.
	SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos = 0x1e
	// Bit mask of LOWTOUTEN field.
	SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk = 0x40000000
	// Bit LOWTOUTEN.
	SERCOM_I2CM_CTRLA_LOWTOUTEN = 0x40000000

	// CTRLB: I2CM Control B
	// Position of SMEN field.
	SERCOM_I2CM_CTRLB_SMEN_Pos = 0x8
	// Bit mask of SMEN field.
	SERCOM_I2CM_CTRLB_SMEN_Msk = 0x100
	// Bit SMEN.
	SERCOM_I2CM_CTRLB_SMEN = 0x100
	// Position of QCEN field.
	SERCOM_I2CM_CTRLB_QCEN_Pos = 0x9
	// Bit mask of QCEN field.
	SERCOM_I2CM_CTRLB_QCEN_Msk = 0x200
	// Bit QCEN.
	SERCOM_I2CM_CTRLB_QCEN = 0x200
	// Position of CMD field.
	SERCOM_I2CM_CTRLB_CMD_Pos = 0x10
	// Bit mask of CMD field.
	SERCOM_I2CM_CTRLB_CMD_Msk = 0x30000
	// Position of ACKACT field.
	SERCOM_I2CM_CTRLB_ACKACT_Pos = 0x12
	// Bit mask of ACKACT field.
	SERCOM_I2CM_CTRLB_ACKACT_Msk = 0x40000
	// Bit ACKACT.
	SERCOM_I2CM_CTRLB_ACKACT = 0x40000

	// CTRLC: I2CM Control C
	// Position of DATA32B field.
	SERCOM_I2CM_CTRLC_DATA32B_Pos = 0x18
	// Bit mask of DATA32B field.
	SERCOM_I2CM_CTRLC_DATA32B_Msk = 0x1000000
	// Bit DATA32B.
	SERCOM_I2CM_CTRLC_DATA32B = 0x1000000
	// Data transaction from/to DATA register are 8-bit
	SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT = 0x0
	// Data transaction from/to DATA register are 32-bit
	SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1

	// BAUD: I2CM Baud Rate
	// Position of BAUD field.
	SERCOM_I2CM_BAUD_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_I2CM_BAUD_BAUD_Msk = 0xff
	// Position of BAUDLOW field.
	SERCOM_I2CM_BAUD_BAUDLOW_Pos = 0x8
	// Bit mask of BAUDLOW field.
	SERCOM_I2CM_BAUD_BAUDLOW_Msk = 0xff00
	// Position of HSBAUD field.
	SERCOM_I2CM_BAUD_HSBAUD_Pos = 0x10
	// Bit mask of HSBAUD field.
	SERCOM_I2CM_BAUD_HSBAUD_Msk = 0xff0000
	// Position of HSBAUDLOW field.
	SERCOM_I2CM_BAUD_HSBAUDLOW_Pos = 0x18
	// Bit mask of HSBAUDLOW field.
	SERCOM_I2CM_BAUD_HSBAUDLOW_Msk = 0xff000000

	// INTENCLR: I2CM Interrupt Enable Clear
	// Position of MB field.
	SERCOM_I2CM_INTENCLR_MB_Pos = 0x0
	// Bit mask of MB field.
	SERCOM_I2CM_INTENCLR_MB_Msk = 0x1
	// Bit MB.
	SERCOM_I2CM_INTENCLR_MB = 0x1
	// Position of SB field.
	SERCOM_I2CM_INTENCLR_SB_Pos = 0x1
	// Bit mask of SB field.
	SERCOM_I2CM_INTENCLR_SB_Msk = 0x2
	// Bit SB.
	SERCOM_I2CM_INTENCLR_SB = 0x2
	// Position of ERROR field.
	SERCOM_I2CM_INTENCLR_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_I2CM_INTENCLR_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_I2CM_INTENCLR_ERROR = 0x80

	// INTENSET: I2CM Interrupt Enable Set
	// Position of MB field.
	SERCOM_I2CM_INTENSET_MB_Pos = 0x0
	// Bit mask of MB field.
	SERCOM_I2CM_INTENSET_MB_Msk = 0x1
	// Bit MB.
	SERCOM_I2CM_INTENSET_MB = 0x1
	// Position of SB field.
	SERCOM_I2CM_INTENSET_SB_Pos = 0x1
	// Bit mask of SB field.
	SERCOM_I2CM_INTENSET_SB_Msk = 0x2
	// Bit SB.
	SERCOM_I2CM_INTENSET_SB = 0x2
	// Position of ERROR field.
	SERCOM_I2CM_INTENSET_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_I2CM_INTENSET_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_I2CM_INTENSET_ERROR = 0x80

	// INTFLAG: I2CM Interrupt Flag Status and Clear
	// Position of MB field.
	SERCOM_I2CM_INTFLAG_MB_Pos = 0x0
	// Bit mask of MB field.
	SERCOM_I2CM_INTFLAG_MB_Msk = 0x1
	// Bit MB.
	SERCOM_I2CM_INTFLAG_MB = 0x1
	// Position of SB field.
	SERCOM_I2CM_INTFLAG_SB_Pos = 0x1
	// Bit mask of SB field.
	SERCOM_I2CM_INTFLAG_SB_Msk = 0x2
	// Bit SB.
	SERCOM_I2CM_INTFLAG_SB = 0x2
	// Position of ERROR field.
	SERCOM_I2CM_INTFLAG_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_I2CM_INTFLAG_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_I2CM_INTFLAG_ERROR = 0x80

	// STATUS: I2CM Status
	// Position of BUSERR field.
	SERCOM_I2CM_STATUS_BUSERR_Pos = 0x0
	// Bit mask of BUSERR field.
	SERCOM_I2CM_STATUS_BUSERR_Msk = 0x1
	// Bit BUSERR.
	SERCOM_I2CM_STATUS_BUSERR = 0x1
	// Position of ARBLOST field.
	SERCOM_I2CM_STATUS_ARBLOST_Pos = 0x1
	// Bit mask of ARBLOST field.
	SERCOM_I2CM_STATUS_ARBLOST_Msk = 0x2
	// Bit ARBLOST.
	SERCOM_I2CM_STATUS_ARBLOST = 0x2
	// Position of RXNACK field.
	SERCOM_I2CM_STATUS_RXNACK_Pos = 0x2
	// Bit mask of RXNACK field.
	SERCOM_I2CM_STATUS_RXNACK_Msk = 0x4
	// Bit RXNACK.
	SERCOM_I2CM_STATUS_RXNACK = 0x4
	// Position of BUSSTATE field.
	SERCOM_I2CM_STATUS_BUSSTATE_Pos = 0x4
	// Bit mask of BUSSTATE field.
	SERCOM_I2CM_STATUS_BUSSTATE_Msk = 0x30
	// Position of LOWTOUT field.
	SERCOM_I2CM_STATUS_LOWTOUT_Pos = 0x6
	// Bit mask of LOWTOUT field.
	SERCOM_I2CM_STATUS_LOWTOUT_Msk = 0x40
	// Bit LOWTOUT.
	SERCOM_I2CM_STATUS_LOWTOUT = 0x40
	// Position of CLKHOLD field.
	SERCOM_I2CM_STATUS_CLKHOLD_Pos = 0x7
	// Bit mask of CLKHOLD field.
	SERCOM_I2CM_STATUS_CLKHOLD_Msk = 0x80
	// Bit CLKHOLD.
	SERCOM_I2CM_STATUS_CLKHOLD = 0x80
	// Position of MEXTTOUT field.
	SERCOM_I2CM_STATUS_MEXTTOUT_Pos = 0x8
	// Bit mask of MEXTTOUT field.
	SERCOM_I2CM_STATUS_MEXTTOUT_Msk = 0x100
	// Bit MEXTTOUT.
	SERCOM_I2CM_STATUS_MEXTTOUT = 0x100
	// Position of SEXTTOUT field.
	SERCOM_I2CM_STATUS_SEXTTOUT_Pos = 0x9
	// Bit mask of SEXTTOUT field.
	SERCOM_I2CM_STATUS_SEXTTOUT_Msk = 0x200
	// Bit SEXTTOUT.
	SERCOM_I2CM_STATUS_SEXTTOUT = 0x200
	// Position of LENERR field.
	SERCOM_I2CM_STATUS_LENERR_Pos = 0xa
	// Bit mask of LENERR field.
	SERCOM_I2CM_STATUS_LENERR_Msk = 0x400
	// Bit LENERR.
	SERCOM_I2CM_STATUS_LENERR = 0x400

	// SYNCBUSY: I2CM Synchronization Busy
	// Position of SWRST field.
	SERCOM_I2CM_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_I2CM_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_I2CM_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_I2CM_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_I2CM_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_I2CM_SYNCBUSY_ENABLE = 0x2
	// Position of SYSOP field.
	SERCOM_I2CM_SYNCBUSY_SYSOP_Pos = 0x2
	// Bit mask of SYSOP field.
	SERCOM_I2CM_SYNCBUSY_SYSOP_Msk = 0x4
	// Bit SYSOP.
	SERCOM_I2CM_SYNCBUSY_SYSOP = 0x4
	// Position of LENGTH field.
	SERCOM_I2CM_SYNCBUSY_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	SERCOM_I2CM_SYNCBUSY_LENGTH_Msk = 0x10
	// Bit LENGTH.
	SERCOM_I2CM_SYNCBUSY_LENGTH = 0x10

	// ADDR: I2CM Address
	// Position of ADDR field.
	SERCOM_I2CM_ADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	SERCOM_I2CM_ADDR_ADDR_Msk = 0x7ff
	// Position of LENEN field.
	SERCOM_I2CM_ADDR_LENEN_Pos = 0xd
	// Bit mask of LENEN field.
	SERCOM_I2CM_ADDR_LENEN_Msk = 0x2000
	// Bit LENEN.
	SERCOM_I2CM_ADDR_LENEN = 0x2000
	// Position of HS field.
	SERCOM_I2CM_ADDR_HS_Pos = 0xe
	// Bit mask of HS field.
	SERCOM_I2CM_ADDR_HS_Msk = 0x4000
	// Bit HS.
	SERCOM_I2CM_ADDR_HS = 0x4000
	// Position of TENBITEN field.
	SERCOM_I2CM_ADDR_TENBITEN_Pos = 0xf
	// Bit mask of TENBITEN field.
	SERCOM_I2CM_ADDR_TENBITEN_Msk = 0x8000
	// Bit TENBITEN.
	SERCOM_I2CM_ADDR_TENBITEN = 0x8000
	// Position of LEN field.
	SERCOM_I2CM_ADDR_LEN_Pos = 0x10
	// Bit mask of LEN field.
	SERCOM_I2CM_ADDR_LEN_Msk = 0xff0000

	// DATA: I2CM Data
	// Position of DATA field.
	SERCOM_I2CM_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SERCOM_I2CM_DATA_DATA_Msk = 0xff

	// DBGCTRL: I2CM Debug Control
	// Position of DBGSTOP field.
	SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos = 0x0
	// Bit mask of DBGSTOP field.
	SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk = 0x1
	// Bit DBGSTOP.
	SERCOM_I2CM_DBGCTRL_DBGSTOP = 0x1
)

// Bitfields for SERCOM0_I2CS: Serial Communication Interface - I2CS
const (
	// CTRLA: I2CS Control A
	// Position of SWRST field.
	SERCOM_I2CS_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_I2CS_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_I2CS_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_I2CS_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_I2CS_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_I2CS_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	SERCOM_I2CS_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	SERCOM_I2CS_CTRLA_MODE_Msk = 0x1c
	// USART with external clock
	SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK = 0x0
	// USART with internal clock
	SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK = 0x1
	// SPI in slave operation
	SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE = 0x2
	// SPI in master operation
	SERCOM_I2CS_CTRLA_MODE_SPI_MASTER = 0x3
	// I2C slave operation
	SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE = 0x4
	// I2C master operation
	SERCOM_I2CS_CTRLA_MODE_I2C_MASTER = 0x5
	// Position of RUNSTDBY field.
	SERCOM_I2CS_CTRLA_RUNSTDBY_Pos = 0x7
	// Bit mask of RUNSTDBY field.
	SERCOM_I2CS_CTRLA_RUNSTDBY_Msk = 0x80
	// Bit RUNSTDBY.
	SERCOM_I2CS_CTRLA_RUNSTDBY = 0x80
	// Position of PINOUT field.
	SERCOM_I2CS_CTRLA_PINOUT_Pos = 0x10
	// Bit mask of PINOUT field.
	SERCOM_I2CS_CTRLA_PINOUT_Msk = 0x10000
	// Bit PINOUT.
	SERCOM_I2CS_CTRLA_PINOUT = 0x10000
	// Position of SDAHOLD field.
	SERCOM_I2CS_CTRLA_SDAHOLD_Pos = 0x14
	// Bit mask of SDAHOLD field.
	SERCOM_I2CS_CTRLA_SDAHOLD_Msk = 0x300000
	// Disabled
	SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE = 0x0
	// 50-100ns hold time
	SERCOM_I2CS_CTRLA_SDAHOLD_75NS = 0x1
	// 300-600ns hold time
	SERCOM_I2CS_CTRLA_SDAHOLD_450NS = 0x2
	// 400-800ns hold time
	SERCOM_I2CS_CTRLA_SDAHOLD_600NS = 0x3
	// Position of SEXTTOEN field.
	SERCOM_I2CS_CTRLA_SEXTTOEN_Pos = 0x17
	// Bit mask of SEXTTOEN field.
	SERCOM_I2CS_CTRLA_SEXTTOEN_Msk = 0x800000
	// Bit SEXTTOEN.
	SERCOM_I2CS_CTRLA_SEXTTOEN = 0x800000
	// Position of SPEED field.
	SERCOM_I2CS_CTRLA_SPEED_Pos = 0x18
	// Bit mask of SPEED field.
	SERCOM_I2CS_CTRLA_SPEED_Msk = 0x3000000
	// Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
	SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE = 0x0
	// Fast-mode Plus Upto 1MHz
	SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE = 0x1
	// High-speed mode Upto 3.4MHz
	SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE = 0x2
	// Position of SCLSM field.
	SERCOM_I2CS_CTRLA_SCLSM_Pos = 0x1b
	// Bit mask of SCLSM field.
	SERCOM_I2CS_CTRLA_SCLSM_Msk = 0x8000000
	// Bit SCLSM.
	SERCOM_I2CS_CTRLA_SCLSM = 0x8000000
	// Position of LOWTOUTEN field.
	SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos = 0x1e
	// Bit mask of LOWTOUTEN field.
	SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk = 0x40000000
	// Bit LOWTOUTEN.
	SERCOM_I2CS_CTRLA_LOWTOUTEN = 0x40000000

	// CTRLB: I2CS Control B
	// Position of SMEN field.
	SERCOM_I2CS_CTRLB_SMEN_Pos = 0x8
	// Bit mask of SMEN field.
	SERCOM_I2CS_CTRLB_SMEN_Msk = 0x100
	// Bit SMEN.
	SERCOM_I2CS_CTRLB_SMEN = 0x100
	// Position of GCMD field.
	SERCOM_I2CS_CTRLB_GCMD_Pos = 0x9
	// Bit mask of GCMD field.
	SERCOM_I2CS_CTRLB_GCMD_Msk = 0x200
	// Bit GCMD.
	SERCOM_I2CS_CTRLB_GCMD = 0x200
	// Position of AACKEN field.
	SERCOM_I2CS_CTRLB_AACKEN_Pos = 0xa
	// Bit mask of AACKEN field.
	SERCOM_I2CS_CTRLB_AACKEN_Msk = 0x400
	// Bit AACKEN.
	SERCOM_I2CS_CTRLB_AACKEN = 0x400
	// Position of AMODE field.
	SERCOM_I2CS_CTRLB_AMODE_Pos = 0xe
	// Bit mask of AMODE field.
	SERCOM_I2CS_CTRLB_AMODE_Msk = 0xc000
	// Position of CMD field.
	SERCOM_I2CS_CTRLB_CMD_Pos = 0x10
	// Bit mask of CMD field.
	SERCOM_I2CS_CTRLB_CMD_Msk = 0x30000
	// Position of ACKACT field.
	SERCOM_I2CS_CTRLB_ACKACT_Pos = 0x12
	// Bit mask of ACKACT field.
	SERCOM_I2CS_CTRLB_ACKACT_Msk = 0x40000
	// Bit ACKACT.
	SERCOM_I2CS_CTRLB_ACKACT = 0x40000

	// CTRLC: I2CS Control C
	// Position of SDASETUP field.
	SERCOM_I2CS_CTRLC_SDASETUP_Pos = 0x0
	// Bit mask of SDASETUP field.
	SERCOM_I2CS_CTRLC_SDASETUP_Msk = 0xf
	// Position of DATA32B field.
	SERCOM_I2CS_CTRLC_DATA32B_Pos = 0x18
	// Bit mask of DATA32B field.
	SERCOM_I2CS_CTRLC_DATA32B_Msk = 0x1000000
	// Bit DATA32B.
	SERCOM_I2CS_CTRLC_DATA32B = 0x1000000
	// Data transaction from/to DATA register are 8-bit
	SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT = 0x0
	// Data transaction from/to DATA register are 32-bit
	SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1

	// INTENCLR: I2CS Interrupt Enable Clear
	// Position of PREC field.
	SERCOM_I2CS_INTENCLR_PREC_Pos = 0x0
	// Bit mask of PREC field.
	SERCOM_I2CS_INTENCLR_PREC_Msk = 0x1
	// Bit PREC.
	SERCOM_I2CS_INTENCLR_PREC = 0x1
	// Position of AMATCH field.
	SERCOM_I2CS_INTENCLR_AMATCH_Pos = 0x1
	// Bit mask of AMATCH field.
	SERCOM_I2CS_INTENCLR_AMATCH_Msk = 0x2
	// Bit AMATCH.
	SERCOM_I2CS_INTENCLR_AMATCH = 0x2
	// Position of DRDY field.
	SERCOM_I2CS_INTENCLR_DRDY_Pos = 0x2
	// Bit mask of DRDY field.
	SERCOM_I2CS_INTENCLR_DRDY_Msk = 0x4
	// Bit DRDY.
	SERCOM_I2CS_INTENCLR_DRDY = 0x4
	// Position of ERROR field.
	SERCOM_I2CS_INTENCLR_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_I2CS_INTENCLR_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_I2CS_INTENCLR_ERROR = 0x80

	// INTENSET: I2CS Interrupt Enable Set
	// Position of PREC field.
	SERCOM_I2CS_INTENSET_PREC_Pos = 0x0
	// Bit mask of PREC field.
	SERCOM_I2CS_INTENSET_PREC_Msk = 0x1
	// Bit PREC.
	SERCOM_I2CS_INTENSET_PREC = 0x1
	// Position of AMATCH field.
	SERCOM_I2CS_INTENSET_AMATCH_Pos = 0x1
	// Bit mask of AMATCH field.
	SERCOM_I2CS_INTENSET_AMATCH_Msk = 0x2
	// Bit AMATCH.
	SERCOM_I2CS_INTENSET_AMATCH = 0x2
	// Position of DRDY field.
	SERCOM_I2CS_INTENSET_DRDY_Pos = 0x2
	// Bit mask of DRDY field.
	SERCOM_I2CS_INTENSET_DRDY_Msk = 0x4
	// Bit DRDY.
	SERCOM_I2CS_INTENSET_DRDY = 0x4
	// Position of ERROR field.
	SERCOM_I2CS_INTENSET_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_I2CS_INTENSET_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_I2CS_INTENSET_ERROR = 0x80

	// INTFLAG: I2CS Interrupt Flag Status and Clear
	// Position of PREC field.
	SERCOM_I2CS_INTFLAG_PREC_Pos = 0x0
	// Bit mask of PREC field.
	SERCOM_I2CS_INTFLAG_PREC_Msk = 0x1
	// Bit PREC.
	SERCOM_I2CS_INTFLAG_PREC = 0x1
	// Position of AMATCH field.
	SERCOM_I2CS_INTFLAG_AMATCH_Pos = 0x1
	// Bit mask of AMATCH field.
	SERCOM_I2CS_INTFLAG_AMATCH_Msk = 0x2
	// Bit AMATCH.
	SERCOM_I2CS_INTFLAG_AMATCH = 0x2
	// Position of DRDY field.
	SERCOM_I2CS_INTFLAG_DRDY_Pos = 0x2
	// Bit mask of DRDY field.
	SERCOM_I2CS_INTFLAG_DRDY_Msk = 0x4
	// Bit DRDY.
	SERCOM_I2CS_INTFLAG_DRDY = 0x4
	// Position of ERROR field.
	SERCOM_I2CS_INTFLAG_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_I2CS_INTFLAG_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_I2CS_INTFLAG_ERROR = 0x80

	// STATUS: I2CS Status
	// Position of BUSERR field.
	SERCOM_I2CS_STATUS_BUSERR_Pos = 0x0
	// Bit mask of BUSERR field.
	SERCOM_I2CS_STATUS_BUSERR_Msk = 0x1
	// Bit BUSERR.
	SERCOM_I2CS_STATUS_BUSERR = 0x1
	// Position of COLL field.
	SERCOM_I2CS_STATUS_COLL_Pos = 0x1
	// Bit mask of COLL field.
	SERCOM_I2CS_STATUS_COLL_Msk = 0x2
	// Bit COLL.
	SERCOM_I2CS_STATUS_COLL = 0x2
	// Position of RXNACK field.
	SERCOM_I2CS_STATUS_RXNACK_Pos = 0x2
	// Bit mask of RXNACK field.
	SERCOM_I2CS_STATUS_RXNACK_Msk = 0x4
	// Bit RXNACK.
	SERCOM_I2CS_STATUS_RXNACK = 0x4
	// Position of DIR field.
	SERCOM_I2CS_STATUS_DIR_Pos = 0x3
	// Bit mask of DIR field.
	SERCOM_I2CS_STATUS_DIR_Msk = 0x8
	// Bit DIR.
	SERCOM_I2CS_STATUS_DIR = 0x8
	// Position of SR field.
	SERCOM_I2CS_STATUS_SR_Pos = 0x4
	// Bit mask of SR field.
	SERCOM_I2CS_STATUS_SR_Msk = 0x10
	// Bit SR.
	SERCOM_I2CS_STATUS_SR = 0x10
	// Position of LOWTOUT field.
	SERCOM_I2CS_STATUS_LOWTOUT_Pos = 0x6
	// Bit mask of LOWTOUT field.
	SERCOM_I2CS_STATUS_LOWTOUT_Msk = 0x40
	// Bit LOWTOUT.
	SERCOM_I2CS_STATUS_LOWTOUT = 0x40
	// Position of CLKHOLD field.
	SERCOM_I2CS_STATUS_CLKHOLD_Pos = 0x7
	// Bit mask of CLKHOLD field.
	SERCOM_I2CS_STATUS_CLKHOLD_Msk = 0x80
	// Bit CLKHOLD.
	SERCOM_I2CS_STATUS_CLKHOLD = 0x80
	// Position of SEXTTOUT field.
	SERCOM_I2CS_STATUS_SEXTTOUT_Pos = 0x9
	// Bit mask of SEXTTOUT field.
	SERCOM_I2CS_STATUS_SEXTTOUT_Msk = 0x200
	// Bit SEXTTOUT.
	SERCOM_I2CS_STATUS_SEXTTOUT = 0x200
	// Position of HS field.
	SERCOM_I2CS_STATUS_HS_Pos = 0xa
	// Bit mask of HS field.
	SERCOM_I2CS_STATUS_HS_Msk = 0x400
	// Bit HS.
	SERCOM_I2CS_STATUS_HS = 0x400
	// Position of LENERR field.
	SERCOM_I2CS_STATUS_LENERR_Pos = 0xb
	// Bit mask of LENERR field.
	SERCOM_I2CS_STATUS_LENERR_Msk = 0x800
	// Bit LENERR.
	SERCOM_I2CS_STATUS_LENERR = 0x800

	// SYNCBUSY: I2CS Synchronization Busy
	// Position of SWRST field.
	SERCOM_I2CS_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_I2CS_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_I2CS_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_I2CS_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_I2CS_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_I2CS_SYNCBUSY_ENABLE = 0x2
	// Position of LENGTH field.
	SERCOM_I2CS_SYNCBUSY_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	SERCOM_I2CS_SYNCBUSY_LENGTH_Msk = 0x10
	// Bit LENGTH.
	SERCOM_I2CS_SYNCBUSY_LENGTH = 0x10

	// LENGTH: I2CS Length
	// Position of LEN field.
	SERCOM_I2CS_LENGTH_LEN_Pos = 0x0
	// Bit mask of LEN field.
	SERCOM_I2CS_LENGTH_LEN_Msk = 0xff
	// Position of LENEN field.
	SERCOM_I2CS_LENGTH_LENEN_Pos = 0x8
	// Bit mask of LENEN field.
	SERCOM_I2CS_LENGTH_LENEN_Msk = 0x100
	// Bit LENEN.
	SERCOM_I2CS_LENGTH_LENEN = 0x100

	// ADDR: I2CS Address
	// Position of GENCEN field.
	SERCOM_I2CS_ADDR_GENCEN_Pos = 0x0
	// Bit mask of GENCEN field.
	SERCOM_I2CS_ADDR_GENCEN_Msk = 0x1
	// Bit GENCEN.
	SERCOM_I2CS_ADDR_GENCEN = 0x1
	// Position of ADDR field.
	SERCOM_I2CS_ADDR_ADDR_Pos = 0x1
	// Bit mask of ADDR field.
	SERCOM_I2CS_ADDR_ADDR_Msk = 0x7fe
	// Position of TENBITEN field.
	SERCOM_I2CS_ADDR_TENBITEN_Pos = 0xf
	// Bit mask of TENBITEN field.
	SERCOM_I2CS_ADDR_TENBITEN_Msk = 0x8000
	// Bit TENBITEN.
	SERCOM_I2CS_ADDR_TENBITEN = 0x8000
	// Position of ADDRMASK field.
	SERCOM_I2CS_ADDR_ADDRMASK_Pos = 0x11
	// Bit mask of ADDRMASK field.
	SERCOM_I2CS_ADDR_ADDRMASK_Msk = 0x7fe0000

	// DATA: I2CS Data
	// Position of DATA field.
	SERCOM_I2CS_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SERCOM_I2CS_DATA_DATA_Msk = 0xffffffff
)

// Bitfields for SERCOM0_SPIS: Serial Communication Interface - SPIS
const (
	// CTRLA: SPIS Control A
	// Position of SWRST field.
	SERCOM_SPIS_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_SPIS_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_SPIS_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_SPIS_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_SPIS_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_SPIS_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	SERCOM_SPIS_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	SERCOM_SPIS_CTRLA_MODE_Msk = 0x1c
	// USART with external clock
	SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK = 0x0
	// USART with internal clock
	SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK = 0x1
	// SPI in slave operation
	SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE = 0x2
	// SPI in master operation
	SERCOM_SPIS_CTRLA_MODE_SPI_MASTER = 0x3
	// I2C slave operation
	SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE = 0x4
	// I2C master operation
	SERCOM_SPIS_CTRLA_MODE_I2C_MASTER = 0x5
	// Position of RUNSTDBY field.
	SERCOM_SPIS_CTRLA_RUNSTDBY_Pos = 0x7
	// Bit mask of RUNSTDBY field.
	SERCOM_SPIS_CTRLA_RUNSTDBY_Msk = 0x80
	// Bit RUNSTDBY.
	SERCOM_SPIS_CTRLA_RUNSTDBY = 0x80
	// Position of IBON field.
	SERCOM_SPIS_CTRLA_IBON_Pos = 0x8
	// Bit mask of IBON field.
	SERCOM_SPIS_CTRLA_IBON_Msk = 0x100
	// Bit IBON.
	SERCOM_SPIS_CTRLA_IBON = 0x100
	// Position of DOPO field.
	SERCOM_SPIS_CTRLA_DOPO_Pos = 0x10
	// Bit mask of DOPO field.
	SERCOM_SPIS_CTRLA_DOPO_Msk = 0x30000
	// DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIS_CTRLA_DOPO_PAD0 = 0x0
	// DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIS_CTRLA_DOPO_PAD2 = 0x2
	// Position of DIPO field.
	SERCOM_SPIS_CTRLA_DIPO_Pos = 0x14
	// Bit mask of DIPO field.
	SERCOM_SPIS_CTRLA_DIPO_Msk = 0x300000
	// SERCOM PAD[0] is used as data input
	SERCOM_SPIS_CTRLA_DIPO_PAD0 = 0x0
	// SERCOM PAD[1] is used as data input
	SERCOM_SPIS_CTRLA_DIPO_PAD1 = 0x1
	// SERCOM PAD[2] is used as data input
	SERCOM_SPIS_CTRLA_DIPO_PAD2 = 0x2
	// SERCOM PAD[3] is used as data input
	SERCOM_SPIS_CTRLA_DIPO_PAD3 = 0x3
	// Position of FORM field.
	SERCOM_SPIS_CTRLA_FORM_Pos = 0x18
	// Bit mask of FORM field.
	SERCOM_SPIS_CTRLA_FORM_Msk = 0xf000000
	// SPI Frame
	SERCOM_SPIS_CTRLA_FORM_SPI_FRAME = 0x0
	// SPI Frame with Addr
	SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR = 0x2
	// Position of CPHA field.
	SERCOM_SPIS_CTRLA_CPHA_Pos = 0x1c
	// Bit mask of CPHA field.
	SERCOM_SPIS_CTRLA_CPHA_Msk = 0x10000000
	// Bit CPHA.
	SERCOM_SPIS_CTRLA_CPHA = 0x10000000
	// The data is sampled on a leading SCK edge and changed on a trailing SCK edge
	SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE = 0x0
	// The data is sampled on a trailing SCK edge and changed on a leading SCK edge
	SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE = 0x1
	// Position of CPOL field.
	SERCOM_SPIS_CTRLA_CPOL_Pos = 0x1d
	// Bit mask of CPOL field.
	SERCOM_SPIS_CTRLA_CPOL_Msk = 0x20000000
	// Bit CPOL.
	SERCOM_SPIS_CTRLA_CPOL = 0x20000000
	// SCK is low when idle
	SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW = 0x0
	// SCK is high when idle
	SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH = 0x1
	// Position of DORD field.
	SERCOM_SPIS_CTRLA_DORD_Pos = 0x1e
	// Bit mask of DORD field.
	SERCOM_SPIS_CTRLA_DORD_Msk = 0x40000000
	// Bit DORD.
	SERCOM_SPIS_CTRLA_DORD = 0x40000000
	// MSB is transferred first
	SERCOM_SPIS_CTRLA_DORD_MSB = 0x0
	// LSB is transferred first
	SERCOM_SPIS_CTRLA_DORD_LSB = 0x1

	// CTRLB: SPIS Control B
	// Position of CHSIZE field.
	SERCOM_SPIS_CTRLB_CHSIZE_Pos = 0x0
	// Bit mask of CHSIZE field.
	SERCOM_SPIS_CTRLB_CHSIZE_Msk = 0x7
	// 8 bits
	SERCOM_SPIS_CTRLB_CHSIZE_8_BIT = 0x0
	// 9 bits
	SERCOM_SPIS_CTRLB_CHSIZE_9_BIT = 0x1
	// Position of PLOADEN field.
	SERCOM_SPIS_CTRLB_PLOADEN_Pos = 0x6
	// Bit mask of PLOADEN field.
	SERCOM_SPIS_CTRLB_PLOADEN_Msk = 0x40
	// Bit PLOADEN.
	SERCOM_SPIS_CTRLB_PLOADEN = 0x40
	// Position of SSDE field.
	SERCOM_SPIS_CTRLB_SSDE_Pos = 0x9
	// Bit mask of SSDE field.
	SERCOM_SPIS_CTRLB_SSDE_Msk = 0x200
	// Bit SSDE.
	SERCOM_SPIS_CTRLB_SSDE = 0x200
	// Position of MSSEN field.
	SERCOM_SPIS_CTRLB_MSSEN_Pos = 0xd
	// Bit mask of MSSEN field.
	SERCOM_SPIS_CTRLB_MSSEN_Msk = 0x2000
	// Bit MSSEN.
	SERCOM_SPIS_CTRLB_MSSEN = 0x2000
	// Position of AMODE field.
	SERCOM_SPIS_CTRLB_AMODE_Pos = 0xe
	// Bit mask of AMODE field.
	SERCOM_SPIS_CTRLB_AMODE_Msk = 0xc000
	// SPI Address mask
	SERCOM_SPIS_CTRLB_AMODE_MASK = 0x0
	// Two unique Addressess
	SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES = 0x1
	// Address Range
	SERCOM_SPIS_CTRLB_AMODE_RANGE = 0x2
	// Position of RXEN field.
	SERCOM_SPIS_CTRLB_RXEN_Pos = 0x11
	// Bit mask of RXEN field.
	SERCOM_SPIS_CTRLB_RXEN_Msk = 0x20000
	// Bit RXEN.
	SERCOM_SPIS_CTRLB_RXEN = 0x20000

	// CTRLC: SPIS Control C
	// Position of ICSPACE field.
	SERCOM_SPIS_CTRLC_ICSPACE_Pos = 0x0
	// Bit mask of ICSPACE field.
	SERCOM_SPIS_CTRLC_ICSPACE_Msk = 0x3f
	// Position of DATA32B field.
	SERCOM_SPIS_CTRLC_DATA32B_Pos = 0x18
	// Bit mask of DATA32B field.
	SERCOM_SPIS_CTRLC_DATA32B_Msk = 0x1000000
	// Bit DATA32B.
	SERCOM_SPIS_CTRLC_DATA32B = 0x1000000
	// Transaction from and to DATA register are 8-bit
	SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT = 0x0
	// Transaction from and to DATA register are 32-bit
	SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1

	// BAUD: SPIS Baud Rate
	// Position of BAUD field.
	SERCOM_SPIS_BAUD_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_SPIS_BAUD_BAUD_Msk = 0xff

	// INTENCLR: SPIS Interrupt Enable Clear
	// Position of DRE field.
	SERCOM_SPIS_INTENCLR_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_SPIS_INTENCLR_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_SPIS_INTENCLR_DRE = 0x1
	// Position of TXC field.
	SERCOM_SPIS_INTENCLR_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_SPIS_INTENCLR_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_SPIS_INTENCLR_TXC = 0x2
	// Position of RXC field.
	SERCOM_SPIS_INTENCLR_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_SPIS_INTENCLR_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_SPIS_INTENCLR_RXC = 0x4
	// Position of SSL field.
	SERCOM_SPIS_INTENCLR_SSL_Pos = 0x3
	// Bit mask of SSL field.
	SERCOM_SPIS_INTENCLR_SSL_Msk = 0x8
	// Bit SSL.
	SERCOM_SPIS_INTENCLR_SSL = 0x8
	// Position of ERROR field.
	SERCOM_SPIS_INTENCLR_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_SPIS_INTENCLR_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_SPIS_INTENCLR_ERROR = 0x80

	// INTENSET: SPIS Interrupt Enable Set
	// Position of DRE field.
	SERCOM_SPIS_INTENSET_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_SPIS_INTENSET_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_SPIS_INTENSET_DRE = 0x1
	// Position of TXC field.
	SERCOM_SPIS_INTENSET_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_SPIS_INTENSET_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_SPIS_INTENSET_TXC = 0x2
	// Position of RXC field.
	SERCOM_SPIS_INTENSET_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_SPIS_INTENSET_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_SPIS_INTENSET_RXC = 0x4
	// Position of SSL field.
	SERCOM_SPIS_INTENSET_SSL_Pos = 0x3
	// Bit mask of SSL field.
	SERCOM_SPIS_INTENSET_SSL_Msk = 0x8
	// Bit SSL.
	SERCOM_SPIS_INTENSET_SSL = 0x8
	// Position of ERROR field.
	SERCOM_SPIS_INTENSET_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_SPIS_INTENSET_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_SPIS_INTENSET_ERROR = 0x80

	// INTFLAG: SPIS Interrupt Flag Status and Clear
	// Position of DRE field.
	SERCOM_SPIS_INTFLAG_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_SPIS_INTFLAG_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_SPIS_INTFLAG_DRE = 0x1
	// Position of TXC field.
	SERCOM_SPIS_INTFLAG_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_SPIS_INTFLAG_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_SPIS_INTFLAG_TXC = 0x2
	// Position of RXC field.
	SERCOM_SPIS_INTFLAG_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_SPIS_INTFLAG_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_SPIS_INTFLAG_RXC = 0x4
	// Position of SSL field.
	SERCOM_SPIS_INTFLAG_SSL_Pos = 0x3
	// Bit mask of SSL field.
	SERCOM_SPIS_INTFLAG_SSL_Msk = 0x8
	// Bit SSL.
	SERCOM_SPIS_INTFLAG_SSL = 0x8
	// Position of ERROR field.
	SERCOM_SPIS_INTFLAG_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_SPIS_INTFLAG_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_SPIS_INTFLAG_ERROR = 0x80

	// STATUS: SPIS Status
	// Position of BUFOVF field.
	SERCOM_SPIS_STATUS_BUFOVF_Pos = 0x2
	// Bit mask of BUFOVF field.
	SERCOM_SPIS_STATUS_BUFOVF_Msk = 0x4
	// Bit BUFOVF.
	SERCOM_SPIS_STATUS_BUFOVF = 0x4
	// Position of LENERR field.
	SERCOM_SPIS_STATUS_LENERR_Pos = 0xb
	// Bit mask of LENERR field.
	SERCOM_SPIS_STATUS_LENERR_Msk = 0x800
	// Bit LENERR.
	SERCOM_SPIS_STATUS_LENERR = 0x800

	// SYNCBUSY: SPIS Synchronization Busy
	// Position of SWRST field.
	SERCOM_SPIS_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_SPIS_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_SPIS_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_SPIS_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_SPIS_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_SPIS_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	SERCOM_SPIS_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	SERCOM_SPIS_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	SERCOM_SPIS_SYNCBUSY_CTRLB = 0x4
	// Position of LENGTH field.
	SERCOM_SPIS_SYNCBUSY_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	SERCOM_SPIS_SYNCBUSY_LENGTH_Msk = 0x10
	// Bit LENGTH.
	SERCOM_SPIS_SYNCBUSY_LENGTH = 0x10

	// LENGTH: SPIS Length
	// Position of LEN field.
	SERCOM_SPIS_LENGTH_LEN_Pos = 0x0
	// Bit mask of LEN field.
	SERCOM_SPIS_LENGTH_LEN_Msk = 0xff
	// Position of LENEN field.
	SERCOM_SPIS_LENGTH_LENEN_Pos = 0x8
	// Bit mask of LENEN field.
	SERCOM_SPIS_LENGTH_LENEN_Msk = 0x100
	// Bit LENEN.
	SERCOM_SPIS_LENGTH_LENEN = 0x100

	// ADDR: SPIS Address
	// Position of ADDR field.
	SERCOM_SPIS_ADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	SERCOM_SPIS_ADDR_ADDR_Msk = 0xff
	// Position of ADDRMASK field.
	SERCOM_SPIS_ADDR_ADDRMASK_Pos = 0x10
	// Bit mask of ADDRMASK field.
	SERCOM_SPIS_ADDR_ADDRMASK_Msk = 0xff0000

	// DATA: SPIS Data
	// Position of DATA field.
	SERCOM_SPIS_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SERCOM_SPIS_DATA_DATA_Msk = 0xffffffff

	// DBGCTRL: SPIS Debug Control
	// Position of DBGSTOP field.
	SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos = 0x0
	// Bit mask of DBGSTOP field.
	SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk = 0x1
	// Bit DBGSTOP.
	SERCOM_SPIS_DBGCTRL_DBGSTOP = 0x1
)

// Bitfields for SERCOM0_SPIM: Serial Communication Interface - SPIM
const (
	// CTRLA: SPIM Control A
	// Position of SWRST field.
	SERCOM_SPIM_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_SPIM_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_SPIM_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_SPIM_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_SPIM_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_SPIM_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	SERCOM_SPIM_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	SERCOM_SPIM_CTRLA_MODE_Msk = 0x1c
	// USART with external clock
	SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK = 0x0
	// USART with internal clock
	SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK = 0x1
	// SPI in slave operation
	SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE = 0x2
	// SPI in master operation
	SERCOM_SPIM_CTRLA_MODE_SPI_MASTER = 0x3
	// I2C slave operation
	SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE = 0x4
	// I2C master operation
	SERCOM_SPIM_CTRLA_MODE_I2C_MASTER = 0x5
	// Position of RUNSTDBY field.
	SERCOM_SPIM_CTRLA_RUNSTDBY_Pos = 0x7
	// Bit mask of RUNSTDBY field.
	SERCOM_SPIM_CTRLA_RUNSTDBY_Msk = 0x80
	// Bit RUNSTDBY.
	SERCOM_SPIM_CTRLA_RUNSTDBY = 0x80
	// Position of IBON field.
	SERCOM_SPIM_CTRLA_IBON_Pos = 0x8
	// Bit mask of IBON field.
	SERCOM_SPIM_CTRLA_IBON_Msk = 0x100
	// Bit IBON.
	SERCOM_SPIM_CTRLA_IBON = 0x100
	// Position of DOPO field.
	SERCOM_SPIM_CTRLA_DOPO_Pos = 0x10
	// Bit mask of DOPO field.
	SERCOM_SPIM_CTRLA_DOPO_Msk = 0x30000
	// DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIM_CTRLA_DOPO_PAD0 = 0x0
	// DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIM_CTRLA_DOPO_PAD2 = 0x2
	// Position of DIPO field.
	SERCOM_SPIM_CTRLA_DIPO_Pos = 0x14
	// Bit mask of DIPO field.
	SERCOM_SPIM_CTRLA_DIPO_Msk = 0x300000
	// SERCOM PAD[0] is used as data input
	SERCOM_SPIM_CTRLA_DIPO_PAD0 = 0x0
	// SERCOM PAD[1] is used as data input
	SERCOM_SPIM_CTRLA_DIPO_PAD1 = 0x1
	// SERCOM PAD[2] is used as data input
	SERCOM_SPIM_CTRLA_DIPO_PAD2 = 0x2
	// SERCOM PAD[3] is used as data input
	SERCOM_SPIM_CTRLA_DIPO_PAD3 = 0x3
	// Position of FORM field.
	SERCOM_SPIM_CTRLA_FORM_Pos = 0x18
	// Bit mask of FORM field.
	SERCOM_SPIM_CTRLA_FORM_Msk = 0xf000000
	// SPI Frame
	SERCOM_SPIM_CTRLA_FORM_SPI_FRAME = 0x0
	// SPI Frame with Addr
	SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR = 0x2
	// Position of CPHA field.
	SERCOM_SPIM_CTRLA_CPHA_Pos = 0x1c
	// Bit mask of CPHA field.
	SERCOM_SPIM_CTRLA_CPHA_Msk = 0x10000000
	// Bit CPHA.
	SERCOM_SPIM_CTRLA_CPHA = 0x10000000
	// The data is sampled on a leading SCK edge and changed on a trailing SCK edge
	SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE = 0x0
	// The data is sampled on a trailing SCK edge and changed on a leading SCK edge
	SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE = 0x1
	// Position of CPOL field.
	SERCOM_SPIM_CTRLA_CPOL_Pos = 0x1d
	// Bit mask of CPOL field.
	SERCOM_SPIM_CTRLA_CPOL_Msk = 0x20000000
	// Bit CPOL.
	SERCOM_SPIM_CTRLA_CPOL = 0x20000000
	// SCK is low when idle
	SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW = 0x0
	// SCK is high when idle
	SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH = 0x1
	// Position of DORD field.
	SERCOM_SPIM_CTRLA_DORD_Pos = 0x1e
	// Bit mask of DORD field.
	SERCOM_SPIM_CTRLA_DORD_Msk = 0x40000000
	// Bit DORD.
	SERCOM_SPIM_CTRLA_DORD = 0x40000000
	// MSB is transferred first
	SERCOM_SPIM_CTRLA_DORD_MSB = 0x0
	// LSB is transferred first
	SERCOM_SPIM_CTRLA_DORD_LSB = 0x1

	// CTRLB: SPIM Control B
	// Position of CHSIZE field.
	SERCOM_SPIM_CTRLB_CHSIZE_Pos = 0x0
	// Bit mask of CHSIZE field.
	SERCOM_SPIM_CTRLB_CHSIZE_Msk = 0x7
	// 8 bits
	SERCOM_SPIM_CTRLB_CHSIZE_8_BIT = 0x0
	// 9 bits
	SERCOM_SPIM_CTRLB_CHSIZE_9_BIT = 0x1
	// Position of PLOADEN field.
	SERCOM_SPIM_CTRLB_PLOADEN_Pos = 0x6
	// Bit mask of PLOADEN field.
	SERCOM_SPIM_CTRLB_PLOADEN_Msk = 0x40
	// Bit PLOADEN.
	SERCOM_SPIM_CTRLB_PLOADEN = 0x40
	// Position of SSDE field.
	SERCOM_SPIM_CTRLB_SSDE_Pos = 0x9
	// Bit mask of SSDE field.
	SERCOM_SPIM_CTRLB_SSDE_Msk = 0x200
	// Bit SSDE.
	SERCOM_SPIM_CTRLB_SSDE = 0x200
	// Position of MSSEN field.
	SERCOM_SPIM_CTRLB_MSSEN_Pos = 0xd
	// Bit mask of MSSEN field.
	SERCOM_SPIM_CTRLB_MSSEN_Msk = 0x2000
	// Bit MSSEN.
	SERCOM_SPIM_CTRLB_MSSEN = 0x2000
	// Position of AMODE field.
	SERCOM_SPIM_CTRLB_AMODE_Pos = 0xe
	// Bit mask of AMODE field.
	SERCOM_SPIM_CTRLB_AMODE_Msk = 0xc000
	// SPI Address mask
	SERCOM_SPIM_CTRLB_AMODE_MASK = 0x0
	// Two unique Addressess
	SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES = 0x1
	// Address Range
	SERCOM_SPIM_CTRLB_AMODE_RANGE = 0x2
	// Position of RXEN field.
	SERCOM_SPIM_CTRLB_RXEN_Pos = 0x11
	// Bit mask of RXEN field.
	SERCOM_SPIM_CTRLB_RXEN_Msk = 0x20000
	// Bit RXEN.
	SERCOM_SPIM_CTRLB_RXEN = 0x20000

	// CTRLC: SPIM Control C
	// Position of ICSPACE field.
	SERCOM_SPIM_CTRLC_ICSPACE_Pos = 0x0
	// Bit mask of ICSPACE field.
	SERCOM_SPIM_CTRLC_ICSPACE_Msk = 0x3f
	// Position of DATA32B field.
	SERCOM_SPIM_CTRLC_DATA32B_Pos = 0x18
	// Bit mask of DATA32B field.
	SERCOM_SPIM_CTRLC_DATA32B_Msk = 0x1000000
	// Bit DATA32B.
	SERCOM_SPIM_CTRLC_DATA32B = 0x1000000
	// Transaction from and to DATA register are 8-bit
	SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT = 0x0
	// Transaction from and to DATA register are 32-bit
	SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1

	// BAUD: SPIM Baud Rate
	// Position of BAUD field.
	SERCOM_SPIM_BAUD_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_SPIM_BAUD_BAUD_Msk = 0xff

	// INTENCLR: SPIM Interrupt Enable Clear
	// Position of DRE field.
	SERCOM_SPIM_INTENCLR_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_SPIM_INTENCLR_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_SPIM_INTENCLR_DRE = 0x1
	// Position of TXC field.
	SERCOM_SPIM_INTENCLR_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_SPIM_INTENCLR_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_SPIM_INTENCLR_TXC = 0x2
	// Position of RXC field.
	SERCOM_SPIM_INTENCLR_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_SPIM_INTENCLR_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_SPIM_INTENCLR_RXC = 0x4
	// Position of SSL field.
	SERCOM_SPIM_INTENCLR_SSL_Pos = 0x3
	// Bit mask of SSL field.
	SERCOM_SPIM_INTENCLR_SSL_Msk = 0x8
	// Bit SSL.
	SERCOM_SPIM_INTENCLR_SSL = 0x8
	// Position of ERROR field.
	SERCOM_SPIM_INTENCLR_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_SPIM_INTENCLR_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_SPIM_INTENCLR_ERROR = 0x80

	// INTENSET: SPIM Interrupt Enable Set
	// Position of DRE field.
	SERCOM_SPIM_INTENSET_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_SPIM_INTENSET_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_SPIM_INTENSET_DRE = 0x1
	// Position of TXC field.
	SERCOM_SPIM_INTENSET_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_SPIM_INTENSET_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_SPIM_INTENSET_TXC = 0x2
	// Position of RXC field.
	SERCOM_SPIM_INTENSET_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_SPIM_INTENSET_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_SPIM_INTENSET_RXC = 0x4
	// Position of SSL field.
	SERCOM_SPIM_INTENSET_SSL_Pos = 0x3
	// Bit mask of SSL field.
	SERCOM_SPIM_INTENSET_SSL_Msk = 0x8
	// Bit SSL.
	SERCOM_SPIM_INTENSET_SSL = 0x8
	// Position of ERROR field.
	SERCOM_SPIM_INTENSET_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_SPIM_INTENSET_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_SPIM_INTENSET_ERROR = 0x80

	// INTFLAG: SPIM Interrupt Flag Status and Clear
	// Position of DRE field.
	SERCOM_SPIM_INTFLAG_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_SPIM_INTFLAG_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_SPIM_INTFLAG_DRE = 0x1
	// Position of TXC field.
	SERCOM_SPIM_INTFLAG_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_SPIM_INTFLAG_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_SPIM_INTFLAG_TXC = 0x2
	// Position of RXC field.
	SERCOM_SPIM_INTFLAG_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_SPIM_INTFLAG_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_SPIM_INTFLAG_RXC = 0x4
	// Position of SSL field.
	SERCOM_SPIM_INTFLAG_SSL_Pos = 0x3
	// Bit mask of SSL field.
	SERCOM_SPIM_INTFLAG_SSL_Msk = 0x8
	// Bit SSL.
	SERCOM_SPIM_INTFLAG_SSL = 0x8
	// Position of ERROR field.
	SERCOM_SPIM_INTFLAG_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_SPIM_INTFLAG_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_SPIM_INTFLAG_ERROR = 0x80

	// STATUS: SPIM Status
	// Position of BUFOVF field.
	SERCOM_SPIM_STATUS_BUFOVF_Pos = 0x2
	// Bit mask of BUFOVF field.
	SERCOM_SPIM_STATUS_BUFOVF_Msk = 0x4
	// Bit BUFOVF.
	SERCOM_SPIM_STATUS_BUFOVF = 0x4
	// Position of LENERR field.
	SERCOM_SPIM_STATUS_LENERR_Pos = 0xb
	// Bit mask of LENERR field.
	SERCOM_SPIM_STATUS_LENERR_Msk = 0x800
	// Bit LENERR.
	SERCOM_SPIM_STATUS_LENERR = 0x800

	// SYNCBUSY: SPIM Synchronization Busy
	// Position of SWRST field.
	SERCOM_SPIM_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_SPIM_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_SPIM_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_SPIM_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_SPIM_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_SPIM_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	SERCOM_SPIM_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	SERCOM_SPIM_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	SERCOM_SPIM_SYNCBUSY_CTRLB = 0x4
	// Position of LENGTH field.
	SERCOM_SPIM_SYNCBUSY_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	SERCOM_SPIM_SYNCBUSY_LENGTH_Msk = 0x10
	// Bit LENGTH.
	SERCOM_SPIM_SYNCBUSY_LENGTH = 0x10

	// LENGTH: SPIM Length
	// Position of LEN field.
	SERCOM_SPIM_LENGTH_LEN_Pos = 0x0
	// Bit mask of LEN field.
	SERCOM_SPIM_LENGTH_LEN_Msk = 0xff
	// Position of LENEN field.
	SERCOM_SPIM_LENGTH_LENEN_Pos = 0x8
	// Bit mask of LENEN field.
	SERCOM_SPIM_LENGTH_LENEN_Msk = 0x100
	// Bit LENEN.
	SERCOM_SPIM_LENGTH_LENEN = 0x100

	// ADDR: SPIM Address
	// Position of ADDR field.
	SERCOM_SPIM_ADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	SERCOM_SPIM_ADDR_ADDR_Msk = 0xff
	// Position of ADDRMASK field.
	SERCOM_SPIM_ADDR_ADDRMASK_Pos = 0x10
	// Bit mask of ADDRMASK field.
	SERCOM_SPIM_ADDR_ADDRMASK_Msk = 0xff0000

	// DATA: SPIM Data
	// Position of DATA field.
	SERCOM_SPIM_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SERCOM_SPIM_DATA_DATA_Msk = 0xffffffff

	// DBGCTRL: SPIM Debug Control
	// Position of DBGSTOP field.
	SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos = 0x0
	// Bit mask of DBGSTOP field.
	SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk = 0x1
	// Bit DBGSTOP.
	SERCOM_SPIM_DBGCTRL_DBGSTOP = 0x1
)

// Bitfields for SERCOM0_USART_EXT: Serial Communication Interface - USART_EXT
const (
	// CTRLA: USART_EXT Control A
	// Position of SWRST field.
	SERCOM_USART_EXT_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_USART_EXT_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_USART_EXT_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_USART_EXT_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_USART_EXT_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_USART_EXT_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	SERCOM_USART_EXT_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	SERCOM_USART_EXT_CTRLA_MODE_Msk = 0x1c
	// USART with external clock
	SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK = 0x0
	// USART with internal clock
	SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK = 0x1
	// SPI in slave operation
	SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE = 0x2
	// SPI in master operation
	SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER = 0x3
	// I2C slave operation
	SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE = 0x4
	// I2C master operation
	SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER = 0x5
	// Position of RUNSTDBY field.
	SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos = 0x7
	// Bit mask of RUNSTDBY field.
	SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk = 0x80
	// Bit RUNSTDBY.
	SERCOM_USART_EXT_CTRLA_RUNSTDBY = 0x80
	// Position of IBON field.
	SERCOM_USART_EXT_CTRLA_IBON_Pos = 0x8
	// Bit mask of IBON field.
	SERCOM_USART_EXT_CTRLA_IBON_Msk = 0x100
	// Bit IBON.
	SERCOM_USART_EXT_CTRLA_IBON = 0x100
	// Position of TXINV field.
	SERCOM_USART_EXT_CTRLA_TXINV_Pos = 0x9
	// Bit mask of TXINV field.
	SERCOM_USART_EXT_CTRLA_TXINV_Msk = 0x200
	// Bit TXINV.
	SERCOM_USART_EXT_CTRLA_TXINV = 0x200
	// Position of RXINV field.
	SERCOM_USART_EXT_CTRLA_RXINV_Pos = 0xa
	// Bit mask of RXINV field.
	SERCOM_USART_EXT_CTRLA_RXINV_Msk = 0x400
	// Bit RXINV.
	SERCOM_USART_EXT_CTRLA_RXINV = 0x400
	// Position of SAMPR field.
	SERCOM_USART_EXT_CTRLA_SAMPR_Pos = 0xd
	// Bit mask of SAMPR field.
	SERCOM_USART_EXT_CTRLA_SAMPR_Msk = 0xe000
	// 16x over-sampling using arithmetic baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC = 0x0
	// 16x over-sampling using fractional baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL = 0x1
	// 8x over-sampling using arithmetic baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC = 0x2
	// 8x over-sampling using fractional baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL = 0x3
	// 3x over-sampling using arithmetic baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC = 0x4
	// Position of TXPO field.
	SERCOM_USART_EXT_CTRLA_TXPO_Pos = 0x10
	// Bit mask of TXPO field.
	SERCOM_USART_EXT_CTRLA_TXPO_Msk = 0x30000
	// SERCOM PAD[0] is used for data transmission
	SERCOM_USART_EXT_CTRLA_TXPO_PAD0 = 0x0
	// SERCOM_PAD[0] is used for data transmission
	SERCOM_USART_EXT_CTRLA_TXPO_PAD3 = 0x3
	// Position of RXPO field.
	SERCOM_USART_EXT_CTRLA_RXPO_Pos = 0x14
	// Bit mask of RXPO field.
	SERCOM_USART_EXT_CTRLA_RXPO_Msk = 0x300000
	// SERCOM PAD[0] is used for data reception
	SERCOM_USART_EXT_CTRLA_RXPO_PAD0 = 0x0
	// SERCOM PAD[1] is used for data reception
	SERCOM_USART_EXT_CTRLA_RXPO_PAD1 = 0x1
	// SERCOM PAD[2] is used for data reception
	SERCOM_USART_EXT_CTRLA_RXPO_PAD2 = 0x2
	// SERCOM PAD[3] is used for data reception
	SERCOM_USART_EXT_CTRLA_RXPO_PAD3 = 0x3
	// Position of SAMPA field.
	SERCOM_USART_EXT_CTRLA_SAMPA_Pos = 0x16
	// Bit mask of SAMPA field.
	SERCOM_USART_EXT_CTRLA_SAMPA_Msk = 0xc00000
	// Position of FORM field.
	SERCOM_USART_EXT_CTRLA_FORM_Pos = 0x18
	// Bit mask of FORM field.
	SERCOM_USART_EXT_CTRLA_FORM_Msk = 0xf000000
	// USART frame
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY = 0x0
	// USART frame with parity
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY = 0x1
	// LIN Master - Break and sync generation
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE = 0x2
	// Auto-baud - break detection and auto-baud
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY = 0x4
	// Auto-baud - break detection and auto-baud with parity
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY = 0x5
	// ISO 7816
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816 = 0x7
	// Position of CMODE field.
	SERCOM_USART_EXT_CTRLA_CMODE_Pos = 0x1c
	// Bit mask of CMODE field.
	SERCOM_USART_EXT_CTRLA_CMODE_Msk = 0x10000000
	// Bit CMODE.
	SERCOM_USART_EXT_CTRLA_CMODE = 0x10000000
	// Asynchronous Communication
	SERCOM_USART_EXT_CTRLA_CMODE_ASYNC = 0x0
	// Synchronous Communication
	SERCOM_USART_EXT_CTRLA_CMODE_SYNC = 0x1
	// Position of CPOL field.
	SERCOM_USART_EXT_CTRLA_CPOL_Pos = 0x1d
	// Bit mask of CPOL field.
	SERCOM_USART_EXT_CTRLA_CPOL_Msk = 0x20000000
	// Bit CPOL.
	SERCOM_USART_EXT_CTRLA_CPOL = 0x20000000
	// TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
	SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW = 0x0
	// TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
	SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH = 0x1
	// Position of DORD field.
	SERCOM_USART_EXT_CTRLA_DORD_Pos = 0x1e
	// Bit mask of DORD field.
	SERCOM_USART_EXT_CTRLA_DORD_Msk = 0x40000000
	// Bit DORD.
	SERCOM_USART_EXT_CTRLA_DORD = 0x40000000
	// MSB is transmitted first
	SERCOM_USART_EXT_CTRLA_DORD_MSB = 0x0
	// LSB is transmitted first
	SERCOM_USART_EXT_CTRLA_DORD_LSB = 0x1

	// CTRLB: USART_EXT Control B
	// Position of CHSIZE field.
	SERCOM_USART_EXT_CTRLB_CHSIZE_Pos = 0x0
	// Bit mask of CHSIZE field.
	SERCOM_USART_EXT_CTRLB_CHSIZE_Msk = 0x7
	// 8 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT = 0x0
	// 9 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT = 0x1
	// 5 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT = 0x5
	// 6 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT = 0x6
	// 7 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT = 0x7
	// Position of SBMODE field.
	SERCOM_USART_EXT_CTRLB_SBMODE_Pos = 0x6
	// Bit mask of SBMODE field.
	SERCOM_USART_EXT_CTRLB_SBMODE_Msk = 0x40
	// Bit SBMODE.
	SERCOM_USART_EXT_CTRLB_SBMODE = 0x40
	// One Stop Bit
	SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT = 0x0
	// Two Stop Bits
	SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT = 0x1
	// Position of COLDEN field.
	SERCOM_USART_EXT_CTRLB_COLDEN_Pos = 0x8
	// Bit mask of COLDEN field.
	SERCOM_USART_EXT_CTRLB_COLDEN_Msk = 0x100
	// Bit COLDEN.
	SERCOM_USART_EXT_CTRLB_COLDEN = 0x100
	// Position of SFDE field.
	SERCOM_USART_EXT_CTRLB_SFDE_Pos = 0x9
	// Bit mask of SFDE field.
	SERCOM_USART_EXT_CTRLB_SFDE_Msk = 0x200
	// Bit SFDE.
	SERCOM_USART_EXT_CTRLB_SFDE = 0x200
	// Position of ENC field.
	SERCOM_USART_EXT_CTRLB_ENC_Pos = 0xa
	// Bit mask of ENC field.
	SERCOM_USART_EXT_CTRLB_ENC_Msk = 0x400
	// Bit ENC.
	SERCOM_USART_EXT_CTRLB_ENC = 0x400
	// Position of PMODE field.
	SERCOM_USART_EXT_CTRLB_PMODE_Pos = 0xd
	// Bit mask of PMODE field.
	SERCOM_USART_EXT_CTRLB_PMODE_Msk = 0x2000
	// Bit PMODE.
	SERCOM_USART_EXT_CTRLB_PMODE = 0x2000
	// Even Parity
	SERCOM_USART_EXT_CTRLB_PMODE_EVEN = 0x0
	// Odd Parity
	SERCOM_USART_EXT_CTRLB_PMODE_ODD = 0x1
	// Position of TXEN field.
	SERCOM_USART_EXT_CTRLB_TXEN_Pos = 0x10
	// Bit mask of TXEN field.
	SERCOM_USART_EXT_CTRLB_TXEN_Msk = 0x10000
	// Bit TXEN.
	SERCOM_USART_EXT_CTRLB_TXEN = 0x10000
	// Position of RXEN field.
	SERCOM_USART_EXT_CTRLB_RXEN_Pos = 0x11
	// Bit mask of RXEN field.
	SERCOM_USART_EXT_CTRLB_RXEN_Msk = 0x20000
	// Bit RXEN.
	SERCOM_USART_EXT_CTRLB_RXEN = 0x20000
	// Position of LINCMD field.
	SERCOM_USART_EXT_CTRLB_LINCMD_Pos = 0x18
	// Bit mask of LINCMD field.
	SERCOM_USART_EXT_CTRLB_LINCMD_Msk = 0x3000000

	// CTRLC: USART_EXT Control C
	// Position of GTIME field.
	SERCOM_USART_EXT_CTRLC_GTIME_Pos = 0x0
	// Bit mask of GTIME field.
	SERCOM_USART_EXT_CTRLC_GTIME_Msk = 0x7
	// Position of BRKLEN field.
	SERCOM_USART_EXT_CTRLC_BRKLEN_Pos = 0x8
	// Bit mask of BRKLEN field.
	SERCOM_USART_EXT_CTRLC_BRKLEN_Msk = 0x300
	// Position of HDRDLY field.
	SERCOM_USART_EXT_CTRLC_HDRDLY_Pos = 0xa
	// Bit mask of HDRDLY field.
	SERCOM_USART_EXT_CTRLC_HDRDLY_Msk = 0xc00
	// Position of INACK field.
	SERCOM_USART_EXT_CTRLC_INACK_Pos = 0x10
	// Bit mask of INACK field.
	SERCOM_USART_EXT_CTRLC_INACK_Msk = 0x10000
	// Bit INACK.
	SERCOM_USART_EXT_CTRLC_INACK = 0x10000
	// Position of DSNACK field.
	SERCOM_USART_EXT_CTRLC_DSNACK_Pos = 0x11
	// Bit mask of DSNACK field.
	SERCOM_USART_EXT_CTRLC_DSNACK_Msk = 0x20000
	// Bit DSNACK.
	SERCOM_USART_EXT_CTRLC_DSNACK = 0x20000
	// Position of MAXITER field.
	SERCOM_USART_EXT_CTRLC_MAXITER_Pos = 0x14
	// Bit mask of MAXITER field.
	SERCOM_USART_EXT_CTRLC_MAXITER_Msk = 0x700000
	// Position of DATA32B field.
	SERCOM_USART_EXT_CTRLC_DATA32B_Pos = 0x18
	// Bit mask of DATA32B field.
	SERCOM_USART_EXT_CTRLC_DATA32B_Msk = 0x3000000
	// Data reads and writes according CTRLB.CHSIZE
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE = 0x0
	// Data reads according CTRLB.CHSIZE and writes according 32-bit extension
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT = 0x1
	// Data reads according 32-bit extension and writes according CTRLB.CHSIZE
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE = 0x2
	// Data reads and writes according 32-bit extension
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT = 0x3

	// BAUD: USART_EXT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_EXT_BAUD_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_EXT_BAUD_BAUD_Msk = 0xffff

	// BAUD_FRAC_MODE: USART_EXT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_EXT_BAUD_FRAC_MODE_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_EXT_BAUD_FRAC_MODE_BAUD_Msk = 0x1fff
	// Position of FP field.
	SERCOM_USART_EXT_BAUD_FRAC_MODE_FP_Pos = 0xd
	// Bit mask of FP field.
	SERCOM_USART_EXT_BAUD_FRAC_MODE_FP_Msk = 0xe000

	// BAUD_FRACFP_MODE: USART_EXT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_BAUD_Msk = 0x1fff
	// Position of FP field.
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_FP_Pos = 0xd
	// Bit mask of FP field.
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_FP_Msk = 0xe000

	// BAUD_USARTFP_MODE: USART_EXT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_EXT_BAUD_USARTFP_MODE_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_EXT_BAUD_USARTFP_MODE_BAUD_Msk = 0xffff

	// RXPL: USART_EXT Receive Pulse Length
	// Position of RXPL field.
	SERCOM_USART_EXT_RXPL_RXPL_Pos = 0x0
	// Bit mask of RXPL field.
	SERCOM_USART_EXT_RXPL_RXPL_Msk = 0xff

	// INTENCLR: USART_EXT Interrupt Enable Clear
	// Position of DRE field.
	SERCOM_USART_EXT_INTENCLR_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_USART_EXT_INTENCLR_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_USART_EXT_INTENCLR_DRE = 0x1
	// Position of TXC field.
	SERCOM_USART_EXT_INTENCLR_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_USART_EXT_INTENCLR_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_USART_EXT_INTENCLR_TXC = 0x2
	// Position of RXC field.
	SERCOM_USART_EXT_INTENCLR_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_USART_EXT_INTENCLR_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_USART_EXT_INTENCLR_RXC = 0x4
	// Position of RXS field.
	SERCOM_USART_EXT_INTENCLR_RXS_Pos = 0x3
	// Bit mask of RXS field.
	SERCOM_USART_EXT_INTENCLR_RXS_Msk = 0x8
	// Bit RXS.
	SERCOM_USART_EXT_INTENCLR_RXS = 0x8
	// Position of CTSIC field.
	SERCOM_USART_EXT_INTENCLR_CTSIC_Pos = 0x4
	// Bit mask of CTSIC field.
	SERCOM_USART_EXT_INTENCLR_CTSIC_Msk = 0x10
	// Bit CTSIC.
	SERCOM_USART_EXT_INTENCLR_CTSIC = 0x10
	// Position of RXBRK field.
	SERCOM_USART_EXT_INTENCLR_RXBRK_Pos = 0x5
	// Bit mask of RXBRK field.
	SERCOM_USART_EXT_INTENCLR_RXBRK_Msk = 0x20
	// Bit RXBRK.
	SERCOM_USART_EXT_INTENCLR_RXBRK = 0x20
	// Position of ERROR field.
	SERCOM_USART_EXT_INTENCLR_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_USART_EXT_INTENCLR_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_USART_EXT_INTENCLR_ERROR = 0x80

	// INTENSET: USART_EXT Interrupt Enable Set
	// Position of DRE field.
	SERCOM_USART_EXT_INTENSET_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_USART_EXT_INTENSET_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_USART_EXT_INTENSET_DRE = 0x1
	// Position of TXC field.
	SERCOM_USART_EXT_INTENSET_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_USART_EXT_INTENSET_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_USART_EXT_INTENSET_TXC = 0x2
	// Position of RXC field.
	SERCOM_USART_EXT_INTENSET_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_USART_EXT_INTENSET_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_USART_EXT_INTENSET_RXC = 0x4
	// Position of RXS field.
	SERCOM_USART_EXT_INTENSET_RXS_Pos = 0x3
	// Bit mask of RXS field.
	SERCOM_USART_EXT_INTENSET_RXS_Msk = 0x8
	// Bit RXS.
	SERCOM_USART_EXT_INTENSET_RXS = 0x8
	// Position of CTSIC field.
	SERCOM_USART_EXT_INTENSET_CTSIC_Pos = 0x4
	// Bit mask of CTSIC field.
	SERCOM_USART_EXT_INTENSET_CTSIC_Msk = 0x10
	// Bit CTSIC.
	SERCOM_USART_EXT_INTENSET_CTSIC = 0x10
	// Position of RXBRK field.
	SERCOM_USART_EXT_INTENSET_RXBRK_Pos = 0x5
	// Bit mask of RXBRK field.
	SERCOM_USART_EXT_INTENSET_RXBRK_Msk = 0x20
	// Bit RXBRK.
	SERCOM_USART_EXT_INTENSET_RXBRK = 0x20
	// Position of ERROR field.
	SERCOM_USART_EXT_INTENSET_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_USART_EXT_INTENSET_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_USART_EXT_INTENSET_ERROR = 0x80

	// INTFLAG: USART_EXT Interrupt Flag Status and Clear
	// Position of DRE field.
	SERCOM_USART_EXT_INTFLAG_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_USART_EXT_INTFLAG_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_USART_EXT_INTFLAG_DRE = 0x1
	// Position of TXC field.
	SERCOM_USART_EXT_INTFLAG_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_USART_EXT_INTFLAG_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_USART_EXT_INTFLAG_TXC = 0x2
	// Position of RXC field.
	SERCOM_USART_EXT_INTFLAG_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_USART_EXT_INTFLAG_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_USART_EXT_INTFLAG_RXC = 0x4
	// Position of RXS field.
	SERCOM_USART_EXT_INTFLAG_RXS_Pos = 0x3
	// Bit mask of RXS field.
	SERCOM_USART_EXT_INTFLAG_RXS_Msk = 0x8
	// Bit RXS.
	SERCOM_USART_EXT_INTFLAG_RXS = 0x8
	// Position of CTSIC field.
	SERCOM_USART_EXT_INTFLAG_CTSIC_Pos = 0x4
	// Bit mask of CTSIC field.
	SERCOM_USART_EXT_INTFLAG_CTSIC_Msk = 0x10
	// Bit CTSIC.
	SERCOM_USART_EXT_INTFLAG_CTSIC = 0x10
	// Position of RXBRK field.
	SERCOM_USART_EXT_INTFLAG_RXBRK_Pos = 0x5
	// Bit mask of RXBRK field.
	SERCOM_USART_EXT_INTFLAG_RXBRK_Msk = 0x20
	// Bit RXBRK.
	SERCOM_USART_EXT_INTFLAG_RXBRK = 0x20
	// Position of ERROR field.
	SERCOM_USART_EXT_INTFLAG_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_USART_EXT_INTFLAG_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_USART_EXT_INTFLAG_ERROR = 0x80

	// STATUS: USART_EXT Status
	// Position of PERR field.
	SERCOM_USART_EXT_STATUS_PERR_Pos = 0x0
	// Bit mask of PERR field.
	SERCOM_USART_EXT_STATUS_PERR_Msk = 0x1
	// Bit PERR.
	SERCOM_USART_EXT_STATUS_PERR = 0x1
	// Position of FERR field.
	SERCOM_USART_EXT_STATUS_FERR_Pos = 0x1
	// Bit mask of FERR field.
	SERCOM_USART_EXT_STATUS_FERR_Msk = 0x2
	// Bit FERR.
	SERCOM_USART_EXT_STATUS_FERR = 0x2
	// Position of BUFOVF field.
	SERCOM_USART_EXT_STATUS_BUFOVF_Pos = 0x2
	// Bit mask of BUFOVF field.
	SERCOM_USART_EXT_STATUS_BUFOVF_Msk = 0x4
	// Bit BUFOVF.
	SERCOM_USART_EXT_STATUS_BUFOVF = 0x4
	// Position of CTS field.
	SERCOM_USART_EXT_STATUS_CTS_Pos = 0x3
	// Bit mask of CTS field.
	SERCOM_USART_EXT_STATUS_CTS_Msk = 0x8
	// Bit CTS.
	SERCOM_USART_EXT_STATUS_CTS = 0x8
	// Position of ISF field.
	SERCOM_USART_EXT_STATUS_ISF_Pos = 0x4
	// Bit mask of ISF field.
	SERCOM_USART_EXT_STATUS_ISF_Msk = 0x10
	// Bit ISF.
	SERCOM_USART_EXT_STATUS_ISF = 0x10
	// Position of COLL field.
	SERCOM_USART_EXT_STATUS_COLL_Pos = 0x5
	// Bit mask of COLL field.
	SERCOM_USART_EXT_STATUS_COLL_Msk = 0x20
	// Bit COLL.
	SERCOM_USART_EXT_STATUS_COLL = 0x20
	// Position of TXE field.
	SERCOM_USART_EXT_STATUS_TXE_Pos = 0x6
	// Bit mask of TXE field.
	SERCOM_USART_EXT_STATUS_TXE_Msk = 0x40
	// Bit TXE.
	SERCOM_USART_EXT_STATUS_TXE = 0x40
	// Position of ITER field.
	SERCOM_USART_EXT_STATUS_ITER_Pos = 0x7
	// Bit mask of ITER field.
	SERCOM_USART_EXT_STATUS_ITER_Msk = 0x80
	// Bit ITER.
	SERCOM_USART_EXT_STATUS_ITER = 0x80

	// SYNCBUSY: USART_EXT Synchronization Busy
	// Position of SWRST field.
	SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_USART_EXT_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_USART_EXT_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	SERCOM_USART_EXT_SYNCBUSY_CTRLB = 0x4
	// Position of RXERRCNT field.
	SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos = 0x3
	// Bit mask of RXERRCNT field.
	SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Msk = 0x8
	// Bit RXERRCNT.
	SERCOM_USART_EXT_SYNCBUSY_RXERRCNT = 0x8
	// Position of LENGTH field.
	SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	SERCOM_USART_EXT_SYNCBUSY_LENGTH_Msk = 0x10
	// Bit LENGTH.
	SERCOM_USART_EXT_SYNCBUSY_LENGTH = 0x10

	// LENGTH: USART_EXT Length
	// Position of LEN field.
	SERCOM_USART_EXT_LENGTH_LEN_Pos = 0x0
	// Bit mask of LEN field.
	SERCOM_USART_EXT_LENGTH_LEN_Msk = 0xff
	// Position of LENEN field.
	SERCOM_USART_EXT_LENGTH_LENEN_Pos = 0x8
	// Bit mask of LENEN field.
	SERCOM_USART_EXT_LENGTH_LENEN_Msk = 0x300

	// DATA: USART_EXT Data
	// Position of DATA field.
	SERCOM_USART_EXT_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SERCOM_USART_EXT_DATA_DATA_Msk = 0xffffffff

	// DBGCTRL: USART_EXT Debug Control
	// Position of DBGSTOP field.
	SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos = 0x0
	// Bit mask of DBGSTOP field.
	SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk = 0x1
	// Bit DBGSTOP.
	SERCOM_USART_EXT_DBGCTRL_DBGSTOP = 0x1
)

// Bitfields for SERCOM0_USART_INT: Serial Communication Interface - USART_INT
const (
	// CTRLA: USART_INT Control A
	// Position of SWRST field.
	SERCOM_USART_INT_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_USART_INT_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_USART_INT_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_USART_INT_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_USART_INT_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_USART_INT_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	SERCOM_USART_INT_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	SERCOM_USART_INT_CTRLA_MODE_Msk = 0x1c
	// USART with external clock
	SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK = 0x0
	// USART with internal clock
	SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK = 0x1
	// SPI in slave operation
	SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE = 0x2
	// SPI in master operation
	SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER = 0x3
	// I2C slave operation
	SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE = 0x4
	// I2C master operation
	SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER = 0x5
	// Position of RUNSTDBY field.
	SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos = 0x7
	// Bit mask of RUNSTDBY field.
	SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk = 0x80
	// Bit RUNSTDBY.
	SERCOM_USART_INT_CTRLA_RUNSTDBY = 0x80
	// Position of IBON field.
	SERCOM_USART_INT_CTRLA_IBON_Pos = 0x8
	// Bit mask of IBON field.
	SERCOM_USART_INT_CTRLA_IBON_Msk = 0x100
	// Bit IBON.
	SERCOM_USART_INT_CTRLA_IBON = 0x100
	// Position of TXINV field.
	SERCOM_USART_INT_CTRLA_TXINV_Pos = 0x9
	// Bit mask of TXINV field.
	SERCOM_USART_INT_CTRLA_TXINV_Msk = 0x200
	// Bit TXINV.
	SERCOM_USART_INT_CTRLA_TXINV = 0x200
	// Position of RXINV field.
	SERCOM_USART_INT_CTRLA_RXINV_Pos = 0xa
	// Bit mask of RXINV field.
	SERCOM_USART_INT_CTRLA_RXINV_Msk = 0x400
	// Bit RXINV.
	SERCOM_USART_INT_CTRLA_RXINV = 0x400
	// Position of SAMPR field.
	SERCOM_USART_INT_CTRLA_SAMPR_Pos = 0xd
	// Bit mask of SAMPR field.
	SERCOM_USART_INT_CTRLA_SAMPR_Msk = 0xe000
	// 16x over-sampling using arithmetic baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC = 0x0
	// 16x over-sampling using fractional baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL = 0x1
	// 8x over-sampling using arithmetic baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC = 0x2
	// 8x over-sampling using fractional baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL = 0x3
	// 3x over-sampling using arithmetic baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC = 0x4
	// Position of TXPO field.
	SERCOM_USART_INT_CTRLA_TXPO_Pos = 0x10
	// Bit mask of TXPO field.
	SERCOM_USART_INT_CTRLA_TXPO_Msk = 0x30000
	// SERCOM PAD[0] is used for data transmission
	SERCOM_USART_INT_CTRLA_TXPO_PAD0 = 0x0
	// SERCOM_PAD[0] is used for data transmission
	SERCOM_USART_INT_CTRLA_TXPO_PAD3 = 0x3
	// Position of RXPO field.
	SERCOM_USART_INT_CTRLA_RXPO_Pos = 0x14
	// Bit mask of RXPO field.
	SERCOM_USART_INT_CTRLA_RXPO_Msk = 0x300000
	// SERCOM PAD[0] is used for data reception
	SERCOM_USART_INT_CTRLA_RXPO_PAD0 = 0x0
	// SERCOM PAD[1] is used for data reception
	SERCOM_USART_INT_CTRLA_RXPO_PAD1 = 0x1
	// SERCOM PAD[2] is used for data reception
	SERCOM_USART_INT_CTRLA_RXPO_PAD2 = 0x2
	// SERCOM PAD[3] is used for data reception
	SERCOM_USART_INT_CTRLA_RXPO_PAD3 = 0x3
	// Position of SAMPA field.
	SERCOM_USART_INT_CTRLA_SAMPA_Pos = 0x16
	// Bit mask of SAMPA field.
	SERCOM_USART_INT_CTRLA_SAMPA_Msk = 0xc00000
	// Position of FORM field.
	SERCOM_USART_INT_CTRLA_FORM_Pos = 0x18
	// Bit mask of FORM field.
	SERCOM_USART_INT_CTRLA_FORM_Msk = 0xf000000
	// USART frame
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY = 0x0
	// USART frame with parity
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY = 0x1
	// LIN Master - Break and sync generation
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE = 0x2
	// Auto-baud - break detection and auto-baud
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY = 0x4
	// Auto-baud - break detection and auto-baud with parity
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY = 0x5
	// ISO 7816
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816 = 0x7
	// Position of CMODE field.
	SERCOM_USART_INT_CTRLA_CMODE_Pos = 0x1c
	// Bit mask of CMODE field.
	SERCOM_USART_INT_CTRLA_CMODE_Msk = 0x10000000
	// Bit CMODE.
	SERCOM_USART_INT_CTRLA_CMODE = 0x10000000
	// Asynchronous Communication
	SERCOM_USART_INT_CTRLA_CMODE_ASYNC = 0x0
	// Synchronous Communication
	SERCOM_USART_INT_CTRLA_CMODE_SYNC = 0x1
	// Position of CPOL field.
	SERCOM_USART_INT_CTRLA_CPOL_Pos = 0x1d
	// Bit mask of CPOL field.
	SERCOM_USART_INT_CTRLA_CPOL_Msk = 0x20000000
	// Bit CPOL.
	SERCOM_USART_INT_CTRLA_CPOL = 0x20000000
	// TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
	SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW = 0x0
	// TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
	SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH = 0x1
	// Position of DORD field.
	SERCOM_USART_INT_CTRLA_DORD_Pos = 0x1e
	// Bit mask of DORD field.
	SERCOM_USART_INT_CTRLA_DORD_Msk = 0x40000000
	// Bit DORD.
	SERCOM_USART_INT_CTRLA_DORD = 0x40000000
	// MSB is transmitted first
	SERCOM_USART_INT_CTRLA_DORD_MSB = 0x0
	// LSB is transmitted first
	SERCOM_USART_INT_CTRLA_DORD_LSB = 0x1

	// CTRLB: USART_INT Control B
	// Position of CHSIZE field.
	SERCOM_USART_INT_CTRLB_CHSIZE_Pos = 0x0
	// Bit mask of CHSIZE field.
	SERCOM_USART_INT_CTRLB_CHSIZE_Msk = 0x7
	// 8 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT = 0x0
	// 9 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT = 0x1
	// 5 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT = 0x5
	// 6 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT = 0x6
	// 7 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT = 0x7
	// Position of SBMODE field.
	SERCOM_USART_INT_CTRLB_SBMODE_Pos = 0x6
	// Bit mask of SBMODE field.
	SERCOM_USART_INT_CTRLB_SBMODE_Msk = 0x40
	// Bit SBMODE.
	SERCOM_USART_INT_CTRLB_SBMODE = 0x40
	// One Stop Bit
	SERCOM_USART_INT_CTRLB_SBMODE_1_BIT = 0x0
	// Two Stop Bits
	SERCOM_USART_INT_CTRLB_SBMODE_2_BIT = 0x1
	// Position of COLDEN field.
	SERCOM_USART_INT_CTRLB_COLDEN_Pos = 0x8
	// Bit mask of COLDEN field.
	SERCOM_USART_INT_CTRLB_COLDEN_Msk = 0x100
	// Bit COLDEN.
	SERCOM_USART_INT_CTRLB_COLDEN = 0x100
	// Position of SFDE field.
	SERCOM_USART_INT_CTRLB_SFDE_Pos = 0x9
	// Bit mask of SFDE field.
	SERCOM_USART_INT_CTRLB_SFDE_Msk = 0x200
	// Bit SFDE.
	SERCOM_USART_INT_CTRLB_SFDE = 0x200
	// Position of ENC field.
	SERCOM_USART_INT_CTRLB_ENC_Pos = 0xa
	// Bit mask of ENC field.
	SERCOM_USART_INT_CTRLB_ENC_Msk = 0x400
	// Bit ENC.
	SERCOM_USART_INT_CTRLB_ENC = 0x400
	// Position of PMODE field.
	SERCOM_USART_INT_CTRLB_PMODE_Pos = 0xd
	// Bit mask of PMODE field.
	SERCOM_USART_INT_CTRLB_PMODE_Msk = 0x2000
	// Bit PMODE.
	SERCOM_USART_INT_CTRLB_PMODE = 0x2000
	// Even Parity
	SERCOM_USART_INT_CTRLB_PMODE_EVEN = 0x0
	// Odd Parity
	SERCOM_USART_INT_CTRLB_PMODE_ODD = 0x1
	// Position of TXEN field.
	SERCOM_USART_INT_CTRLB_TXEN_Pos = 0x10
	// Bit mask of TXEN field.
	SERCOM_USART_INT_CTRLB_TXEN_Msk = 0x10000
	// Bit TXEN.
	SERCOM_USART_INT_CTRLB_TXEN = 0x10000
	// Position of RXEN field.
	SERCOM_USART_INT_CTRLB_RXEN_Pos = 0x11
	// Bit mask of RXEN field.
	SERCOM_USART_INT_CTRLB_RXEN_Msk = 0x20000
	// Bit RXEN.
	SERCOM_USART_INT_CTRLB_RXEN = 0x20000
	// Position of LINCMD field.
	SERCOM_USART_INT_CTRLB_LINCMD_Pos = 0x18
	// Bit mask of LINCMD field.
	SERCOM_USART_INT_CTRLB_LINCMD_Msk = 0x3000000

	// CTRLC: USART_INT Control C
	// Position of GTIME field.
	SERCOM_USART_INT_CTRLC_GTIME_Pos = 0x0
	// Bit mask of GTIME field.
	SERCOM_USART_INT_CTRLC_GTIME_Msk = 0x7
	// Position of BRKLEN field.
	SERCOM_USART_INT_CTRLC_BRKLEN_Pos = 0x8
	// Bit mask of BRKLEN field.
	SERCOM_USART_INT_CTRLC_BRKLEN_Msk = 0x300
	// Position of HDRDLY field.
	SERCOM_USART_INT_CTRLC_HDRDLY_Pos = 0xa
	// Bit mask of HDRDLY field.
	SERCOM_USART_INT_CTRLC_HDRDLY_Msk = 0xc00
	// Position of INACK field.
	SERCOM_USART_INT_CTRLC_INACK_Pos = 0x10
	// Bit mask of INACK field.
	SERCOM_USART_INT_CTRLC_INACK_Msk = 0x10000
	// Bit INACK.
	SERCOM_USART_INT_CTRLC_INACK = 0x10000
	// Position of DSNACK field.
	SERCOM_USART_INT_CTRLC_DSNACK_Pos = 0x11
	// Bit mask of DSNACK field.
	SERCOM_USART_INT_CTRLC_DSNACK_Msk = 0x20000
	// Bit DSNACK.
	SERCOM_USART_INT_CTRLC_DSNACK = 0x20000
	// Position of MAXITER field.
	SERCOM_USART_INT_CTRLC_MAXITER_Pos = 0x14
	// Bit mask of MAXITER field.
	SERCOM_USART_INT_CTRLC_MAXITER_Msk = 0x700000
	// Position of DATA32B field.
	SERCOM_USART_INT_CTRLC_DATA32B_Pos = 0x18
	// Bit mask of DATA32B field.
	SERCOM_USART_INT_CTRLC_DATA32B_Msk = 0x3000000
	// Data reads and writes according CTRLB.CHSIZE
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE = 0x0
	// Data reads according CTRLB.CHSIZE and writes according 32-bit extension
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT = 0x1
	// Data reads according 32-bit extension and writes according CTRLB.CHSIZE
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE = 0x2
	// Data reads and writes according 32-bit extension
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT = 0x3

	// BAUD: USART_INT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_INT_BAUD_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_INT_BAUD_BAUD_Msk = 0xffff

	// BAUD_FRAC_MODE: USART_INT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_INT_BAUD_FRAC_MODE_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_INT_BAUD_FRAC_MODE_BAUD_Msk = 0x1fff
	// Position of FP field.
	SERCOM_USART_INT_BAUD_FRAC_MODE_FP_Pos = 0xd
	// Bit mask of FP field.
	SERCOM_USART_INT_BAUD_FRAC_MODE_FP_Msk = 0xe000

	// BAUD_FRACFP_MODE: USART_INT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_INT_BAUD_FRACFP_MODE_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_INT_BAUD_FRACFP_MODE_BAUD_Msk = 0x1fff
	// Position of FP field.
	SERCOM_USART_INT_BAUD_FRACFP_MODE_FP_Pos = 0xd
	// Bit mask of FP field.
	SERCOM_USART_INT_BAUD_FRACFP_MODE_FP_Msk = 0xe000

	// BAUD_USARTFP_MODE: USART_INT Baud Rate
	// Position of BAUD field.
	SERCOM_USART_INT_BAUD_USARTFP_MODE_BAUD_Pos = 0x0
	// Bit mask of BAUD field.
	SERCOM_USART_INT_BAUD_USARTFP_MODE_BAUD_Msk = 0xffff

	// RXPL: USART_INT Receive Pulse Length
	// Position of RXPL field.
	SERCOM_USART_INT_RXPL_RXPL_Pos = 0x0
	// Bit mask of RXPL field.
	SERCOM_USART_INT_RXPL_RXPL_Msk = 0xff

	// INTENCLR: USART_INT Interrupt Enable Clear
	// Position of DRE field.
	SERCOM_USART_INT_INTENCLR_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_USART_INT_INTENCLR_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_USART_INT_INTENCLR_DRE = 0x1
	// Position of TXC field.
	SERCOM_USART_INT_INTENCLR_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_USART_INT_INTENCLR_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_USART_INT_INTENCLR_TXC = 0x2
	// Position of RXC field.
	SERCOM_USART_INT_INTENCLR_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_USART_INT_INTENCLR_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_USART_INT_INTENCLR_RXC = 0x4
	// Position of RXS field.
	SERCOM_USART_INT_INTENCLR_RXS_Pos = 0x3
	// Bit mask of RXS field.
	SERCOM_USART_INT_INTENCLR_RXS_Msk = 0x8
	// Bit RXS.
	SERCOM_USART_INT_INTENCLR_RXS = 0x8
	// Position of CTSIC field.
	SERCOM_USART_INT_INTENCLR_CTSIC_Pos = 0x4
	// Bit mask of CTSIC field.
	SERCOM_USART_INT_INTENCLR_CTSIC_Msk = 0x10
	// Bit CTSIC.
	SERCOM_USART_INT_INTENCLR_CTSIC = 0x10
	// Position of RXBRK field.
	SERCOM_USART_INT_INTENCLR_RXBRK_Pos = 0x5
	// Bit mask of RXBRK field.
	SERCOM_USART_INT_INTENCLR_RXBRK_Msk = 0x20
	// Bit RXBRK.
	SERCOM_USART_INT_INTENCLR_RXBRK = 0x20
	// Position of ERROR field.
	SERCOM_USART_INT_INTENCLR_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_USART_INT_INTENCLR_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_USART_INT_INTENCLR_ERROR = 0x80

	// INTENSET: USART_INT Interrupt Enable Set
	// Position of DRE field.
	SERCOM_USART_INT_INTENSET_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_USART_INT_INTENSET_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_USART_INT_INTENSET_DRE = 0x1
	// Position of TXC field.
	SERCOM_USART_INT_INTENSET_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_USART_INT_INTENSET_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_USART_INT_INTENSET_TXC = 0x2
	// Position of RXC field.
	SERCOM_USART_INT_INTENSET_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_USART_INT_INTENSET_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_USART_INT_INTENSET_RXC = 0x4
	// Position of RXS field.
	SERCOM_USART_INT_INTENSET_RXS_Pos = 0x3
	// Bit mask of RXS field.
	SERCOM_USART_INT_INTENSET_RXS_Msk = 0x8
	// Bit RXS.
	SERCOM_USART_INT_INTENSET_RXS = 0x8
	// Position of CTSIC field.
	SERCOM_USART_INT_INTENSET_CTSIC_Pos = 0x4
	// Bit mask of CTSIC field.
	SERCOM_USART_INT_INTENSET_CTSIC_Msk = 0x10
	// Bit CTSIC.
	SERCOM_USART_INT_INTENSET_CTSIC = 0x10
	// Position of RXBRK field.
	SERCOM_USART_INT_INTENSET_RXBRK_Pos = 0x5
	// Bit mask of RXBRK field.
	SERCOM_USART_INT_INTENSET_RXBRK_Msk = 0x20
	// Bit RXBRK.
	SERCOM_USART_INT_INTENSET_RXBRK = 0x20
	// Position of ERROR field.
	SERCOM_USART_INT_INTENSET_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_USART_INT_INTENSET_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_USART_INT_INTENSET_ERROR = 0x80

	// INTFLAG: USART_INT Interrupt Flag Status and Clear
	// Position of DRE field.
	SERCOM_USART_INT_INTFLAG_DRE_Pos = 0x0
	// Bit mask of DRE field.
	SERCOM_USART_INT_INTFLAG_DRE_Msk = 0x1
	// Bit DRE.
	SERCOM_USART_INT_INTFLAG_DRE = 0x1
	// Position of TXC field.
	SERCOM_USART_INT_INTFLAG_TXC_Pos = 0x1
	// Bit mask of TXC field.
	SERCOM_USART_INT_INTFLAG_TXC_Msk = 0x2
	// Bit TXC.
	SERCOM_USART_INT_INTFLAG_TXC = 0x2
	// Position of RXC field.
	SERCOM_USART_INT_INTFLAG_RXC_Pos = 0x2
	// Bit mask of RXC field.
	SERCOM_USART_INT_INTFLAG_RXC_Msk = 0x4
	// Bit RXC.
	SERCOM_USART_INT_INTFLAG_RXC = 0x4
	// Position of RXS field.
	SERCOM_USART_INT_INTFLAG_RXS_Pos = 0x3
	// Bit mask of RXS field.
	SERCOM_USART_INT_INTFLAG_RXS_Msk = 0x8
	// Bit RXS.
	SERCOM_USART_INT_INTFLAG_RXS = 0x8
	// Position of CTSIC field.
	SERCOM_USART_INT_INTFLAG_CTSIC_Pos = 0x4
	// Bit mask of CTSIC field.
	SERCOM_USART_INT_INTFLAG_CTSIC_Msk = 0x10
	// Bit CTSIC.
	SERCOM_USART_INT_INTFLAG_CTSIC = 0x10
	// Position of RXBRK field.
	SERCOM_USART_INT_INTFLAG_RXBRK_Pos = 0x5
	// Bit mask of RXBRK field.
	SERCOM_USART_INT_INTFLAG_RXBRK_Msk = 0x20
	// Bit RXBRK.
	SERCOM_USART_INT_INTFLAG_RXBRK = 0x20
	// Position of ERROR field.
	SERCOM_USART_INT_INTFLAG_ERROR_Pos = 0x7
	// Bit mask of ERROR field.
	SERCOM_USART_INT_INTFLAG_ERROR_Msk = 0x80
	// Bit ERROR.
	SERCOM_USART_INT_INTFLAG_ERROR = 0x80

	// STATUS: USART_INT Status
	// Position of PERR field.
	SERCOM_USART_INT_STATUS_PERR_Pos = 0x0
	// Bit mask of PERR field.
	SERCOM_USART_INT_STATUS_PERR_Msk = 0x1
	// Bit PERR.
	SERCOM_USART_INT_STATUS_PERR = 0x1
	// Position of FERR field.
	SERCOM_USART_INT_STATUS_FERR_Pos = 0x1
	// Bit mask of FERR field.
	SERCOM_USART_INT_STATUS_FERR_Msk = 0x2
	// Bit FERR.
	SERCOM_USART_INT_STATUS_FERR = 0x2
	// Position of BUFOVF field.
	SERCOM_USART_INT_STATUS_BUFOVF_Pos = 0x2
	// Bit mask of BUFOVF field.
	SERCOM_USART_INT_STATUS_BUFOVF_Msk = 0x4
	// Bit BUFOVF.
	SERCOM_USART_INT_STATUS_BUFOVF = 0x4
	// Position of CTS field.
	SERCOM_USART_INT_STATUS_CTS_Pos = 0x3
	// Bit mask of CTS field.
	SERCOM_USART_INT_STATUS_CTS_Msk = 0x8
	// Bit CTS.
	SERCOM_USART_INT_STATUS_CTS = 0x8
	// Position of ISF field.
	SERCOM_USART_INT_STATUS_ISF_Pos = 0x4
	// Bit mask of ISF field.
	SERCOM_USART_INT_STATUS_ISF_Msk = 0x10
	// Bit ISF.
	SERCOM_USART_INT_STATUS_ISF = 0x10
	// Position of COLL field.
	SERCOM_USART_INT_STATUS_COLL_Pos = 0x5
	// Bit mask of COLL field.
	SERCOM_USART_INT_STATUS_COLL_Msk = 0x20
	// Bit COLL.
	SERCOM_USART_INT_STATUS_COLL = 0x20
	// Position of TXE field.
	SERCOM_USART_INT_STATUS_TXE_Pos = 0x6
	// Bit mask of TXE field.
	SERCOM_USART_INT_STATUS_TXE_Msk = 0x40
	// Bit TXE.
	SERCOM_USART_INT_STATUS_TXE = 0x40
	// Position of ITER field.
	SERCOM_USART_INT_STATUS_ITER_Pos = 0x7
	// Bit mask of ITER field.
	SERCOM_USART_INT_STATUS_ITER_Msk = 0x80
	// Bit ITER.
	SERCOM_USART_INT_STATUS_ITER = 0x80

	// SYNCBUSY: USART_INT Synchronization Busy
	// Position of SWRST field.
	SERCOM_USART_INT_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	SERCOM_USART_INT_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	SERCOM_USART_INT_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SERCOM_USART_INT_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	SERCOM_USART_INT_SYNCBUSY_CTRLB = 0x4
	// Position of RXERRCNT field.
	SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos = 0x3
	// Bit mask of RXERRCNT field.
	SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Msk = 0x8
	// Bit RXERRCNT.
	SERCOM_USART_INT_SYNCBUSY_RXERRCNT = 0x8
	// Position of LENGTH field.
	SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	SERCOM_USART_INT_SYNCBUSY_LENGTH_Msk = 0x10
	// Bit LENGTH.
	SERCOM_USART_INT_SYNCBUSY_LENGTH = 0x10

	// LENGTH: USART_INT Length
	// Position of LEN field.
	SERCOM_USART_INT_LENGTH_LEN_Pos = 0x0
	// Bit mask of LEN field.
	SERCOM_USART_INT_LENGTH_LEN_Msk = 0xff
	// Position of LENEN field.
	SERCOM_USART_INT_LENGTH_LENEN_Pos = 0x8
	// Bit mask of LENEN field.
	SERCOM_USART_INT_LENGTH_LENEN_Msk = 0x300

	// DATA: USART_INT Data
	// Position of DATA field.
	SERCOM_USART_INT_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SERCOM_USART_INT_DATA_DATA_Msk = 0xffffffff

	// DBGCTRL: USART_INT Debug Control
	// Position of DBGSTOP field.
	SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos = 0x0
	// Bit mask of DBGSTOP field.
	SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk = 0x1
	// Bit DBGSTOP.
	SERCOM_USART_INT_DBGCTRL_DBGSTOP = 0x1
)

// Bitfields for SUPC: Supply Controller
const (
	// INTENCLR: Interrupt Enable Clear
	// Position of BOD33RDY field.
	SUPC_INTENCLR_BOD33RDY_Pos = 0x0
	// Bit mask of BOD33RDY field.
	SUPC_INTENCLR_BOD33RDY_Msk = 0x1
	// Bit BOD33RDY.
	SUPC_INTENCLR_BOD33RDY = 0x1
	// Position of BOD33DET field.
	SUPC_INTENCLR_BOD33DET_Pos = 0x1
	// Bit mask of BOD33DET field.
	SUPC_INTENCLR_BOD33DET_Msk = 0x2
	// Bit BOD33DET.
	SUPC_INTENCLR_BOD33DET = 0x2
	// Position of B33SRDY field.
	SUPC_INTENCLR_B33SRDY_Pos = 0x2
	// Bit mask of B33SRDY field.
	SUPC_INTENCLR_B33SRDY_Msk = 0x4
	// Bit B33SRDY.
	SUPC_INTENCLR_B33SRDY = 0x4
	// Position of VREGRDY field.
	SUPC_INTENCLR_VREGRDY_Pos = 0x8
	// Bit mask of VREGRDY field.
	SUPC_INTENCLR_VREGRDY_Msk = 0x100
	// Bit VREGRDY.
	SUPC_INTENCLR_VREGRDY = 0x100
	// Position of VCORERDY field.
	SUPC_INTENCLR_VCORERDY_Pos = 0xa
	// Bit mask of VCORERDY field.
	SUPC_INTENCLR_VCORERDY_Msk = 0x400
	// Bit VCORERDY.
	SUPC_INTENCLR_VCORERDY = 0x400

	// INTENSET: Interrupt Enable Set
	// Position of BOD33RDY field.
	SUPC_INTENSET_BOD33RDY_Pos = 0x0
	// Bit mask of BOD33RDY field.
	SUPC_INTENSET_BOD33RDY_Msk = 0x1
	// Bit BOD33RDY.
	SUPC_INTENSET_BOD33RDY = 0x1
	// Position of BOD33DET field.
	SUPC_INTENSET_BOD33DET_Pos = 0x1
	// Bit mask of BOD33DET field.
	SUPC_INTENSET_BOD33DET_Msk = 0x2
	// Bit BOD33DET.
	SUPC_INTENSET_BOD33DET = 0x2
	// Position of B33SRDY field.
	SUPC_INTENSET_B33SRDY_Pos = 0x2
	// Bit mask of B33SRDY field.
	SUPC_INTENSET_B33SRDY_Msk = 0x4
	// Bit B33SRDY.
	SUPC_INTENSET_B33SRDY = 0x4
	// Position of VREGRDY field.
	SUPC_INTENSET_VREGRDY_Pos = 0x8
	// Bit mask of VREGRDY field.
	SUPC_INTENSET_VREGRDY_Msk = 0x100
	// Bit VREGRDY.
	SUPC_INTENSET_VREGRDY = 0x100
	// Position of VCORERDY field.
	SUPC_INTENSET_VCORERDY_Pos = 0xa
	// Bit mask of VCORERDY field.
	SUPC_INTENSET_VCORERDY_Msk = 0x400
	// Bit VCORERDY.
	SUPC_INTENSET_VCORERDY = 0x400

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of BOD33RDY field.
	SUPC_INTFLAG_BOD33RDY_Pos = 0x0
	// Bit mask of BOD33RDY field.
	SUPC_INTFLAG_BOD33RDY_Msk = 0x1
	// Bit BOD33RDY.
	SUPC_INTFLAG_BOD33RDY = 0x1
	// Position of BOD33DET field.
	SUPC_INTFLAG_BOD33DET_Pos = 0x1
	// Bit mask of BOD33DET field.
	SUPC_INTFLAG_BOD33DET_Msk = 0x2
	// Bit BOD33DET.
	SUPC_INTFLAG_BOD33DET = 0x2
	// Position of B33SRDY field.
	SUPC_INTFLAG_B33SRDY_Pos = 0x2
	// Bit mask of B33SRDY field.
	SUPC_INTFLAG_B33SRDY_Msk = 0x4
	// Bit B33SRDY.
	SUPC_INTFLAG_B33SRDY = 0x4
	// Position of VREGRDY field.
	SUPC_INTFLAG_VREGRDY_Pos = 0x8
	// Bit mask of VREGRDY field.
	SUPC_INTFLAG_VREGRDY_Msk = 0x100
	// Bit VREGRDY.
	SUPC_INTFLAG_VREGRDY = 0x100
	// Position of VCORERDY field.
	SUPC_INTFLAG_VCORERDY_Pos = 0xa
	// Bit mask of VCORERDY field.
	SUPC_INTFLAG_VCORERDY_Msk = 0x400
	// Bit VCORERDY.
	SUPC_INTFLAG_VCORERDY = 0x400

	// STATUS: Power and Clocks Status
	// Position of BOD33RDY field.
	SUPC_STATUS_BOD33RDY_Pos = 0x0
	// Bit mask of BOD33RDY field.
	SUPC_STATUS_BOD33RDY_Msk = 0x1
	// Bit BOD33RDY.
	SUPC_STATUS_BOD33RDY = 0x1
	// Position of BOD33DET field.
	SUPC_STATUS_BOD33DET_Pos = 0x1
	// Bit mask of BOD33DET field.
	SUPC_STATUS_BOD33DET_Msk = 0x2
	// Bit BOD33DET.
	SUPC_STATUS_BOD33DET = 0x2
	// Position of B33SRDY field.
	SUPC_STATUS_B33SRDY_Pos = 0x2
	// Bit mask of B33SRDY field.
	SUPC_STATUS_B33SRDY_Msk = 0x4
	// Bit B33SRDY.
	SUPC_STATUS_B33SRDY = 0x4
	// Position of VREGRDY field.
	SUPC_STATUS_VREGRDY_Pos = 0x8
	// Bit mask of VREGRDY field.
	SUPC_STATUS_VREGRDY_Msk = 0x100
	// Bit VREGRDY.
	SUPC_STATUS_VREGRDY = 0x100
	// Position of VCORERDY field.
	SUPC_STATUS_VCORERDY_Pos = 0xa
	// Bit mask of VCORERDY field.
	SUPC_STATUS_VCORERDY_Msk = 0x400
	// Bit VCORERDY.
	SUPC_STATUS_VCORERDY = 0x400

	// BOD33: BOD33 Control
	// Position of ENABLE field.
	SUPC_BOD33_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SUPC_BOD33_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SUPC_BOD33_ENABLE = 0x2
	// Position of ACTION field.
	SUPC_BOD33_ACTION_Pos = 0x2
	// Bit mask of ACTION field.
	SUPC_BOD33_ACTION_Msk = 0xc
	// No action
	SUPC_BOD33_ACTION_NONE = 0x0
	// The BOD33 generates a reset
	SUPC_BOD33_ACTION_RESET = 0x1
	// The BOD33 generates an interrupt
	SUPC_BOD33_ACTION_INT = 0x2
	// The BOD33 puts the device in backup sleep mode
	SUPC_BOD33_ACTION_BKUP = 0x3
	// Position of STDBYCFG field.
	SUPC_BOD33_STDBYCFG_Pos = 0x4
	// Bit mask of STDBYCFG field.
	SUPC_BOD33_STDBYCFG_Msk = 0x10
	// Bit STDBYCFG.
	SUPC_BOD33_STDBYCFG = 0x10
	// Position of RUNSTDBY field.
	SUPC_BOD33_RUNSTDBY_Pos = 0x5
	// Bit mask of RUNSTDBY field.
	SUPC_BOD33_RUNSTDBY_Msk = 0x20
	// Bit RUNSTDBY.
	SUPC_BOD33_RUNSTDBY = 0x20
	// Position of RUNHIB field.
	SUPC_BOD33_RUNHIB_Pos = 0x6
	// Bit mask of RUNHIB field.
	SUPC_BOD33_RUNHIB_Msk = 0x40
	// Bit RUNHIB.
	SUPC_BOD33_RUNHIB = 0x40
	// Position of RUNBKUP field.
	SUPC_BOD33_RUNBKUP_Pos = 0x7
	// Bit mask of RUNBKUP field.
	SUPC_BOD33_RUNBKUP_Msk = 0x80
	// Bit RUNBKUP.
	SUPC_BOD33_RUNBKUP = 0x80
	// Position of HYST field.
	SUPC_BOD33_HYST_Pos = 0x8
	// Bit mask of HYST field.
	SUPC_BOD33_HYST_Msk = 0xf00
	// Position of PSEL field.
	SUPC_BOD33_PSEL_Pos = 0xc
	// Bit mask of PSEL field.
	SUPC_BOD33_PSEL_Msk = 0x7000
	// Not divided
	SUPC_BOD33_PSEL_NODIV = 0x0
	// Divide clock by 4
	SUPC_BOD33_PSEL_DIV4 = 0x1
	// Divide clock by 8
	SUPC_BOD33_PSEL_DIV8 = 0x2
	// Divide clock by 16
	SUPC_BOD33_PSEL_DIV16 = 0x3
	// Divide clock by 32
	SUPC_BOD33_PSEL_DIV32 = 0x4
	// Divide clock by 64
	SUPC_BOD33_PSEL_DIV64 = 0x5
	// Divide clock by 128
	SUPC_BOD33_PSEL_DIV128 = 0x6
	// Divide clock by 256
	SUPC_BOD33_PSEL_DIV256 = 0x7
	// Position of LEVEL field.
	SUPC_BOD33_LEVEL_Pos = 0x10
	// Bit mask of LEVEL field.
	SUPC_BOD33_LEVEL_Msk = 0xff0000
	// Position of VBATLEVEL field.
	SUPC_BOD33_VBATLEVEL_Pos = 0x18
	// Bit mask of VBATLEVEL field.
	SUPC_BOD33_VBATLEVEL_Msk = 0xff000000

	// VREG: VREG Control
	// Position of ENABLE field.
	SUPC_VREG_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	SUPC_VREG_ENABLE_Msk = 0x2
	// Bit ENABLE.
	SUPC_VREG_ENABLE = 0x2
	// Position of SEL field.
	SUPC_VREG_SEL_Pos = 0x2
	// Bit mask of SEL field.
	SUPC_VREG_SEL_Msk = 0x4
	// Bit SEL.
	SUPC_VREG_SEL = 0x4
	// LDO selection
	SUPC_VREG_SEL_LDO = 0x0
	// Buck selection
	SUPC_VREG_SEL_BUCK = 0x1
	// Position of RUNBKUP field.
	SUPC_VREG_RUNBKUP_Pos = 0x7
	// Bit mask of RUNBKUP field.
	SUPC_VREG_RUNBKUP_Msk = 0x80
	// Bit RUNBKUP.
	SUPC_VREG_RUNBKUP = 0x80
	// Position of VSEN field.
	SUPC_VREG_VSEN_Pos = 0x10
	// Bit mask of VSEN field.
	SUPC_VREG_VSEN_Msk = 0x10000
	// Bit VSEN.
	SUPC_VREG_VSEN = 0x10000
	// Position of VSPER field.
	SUPC_VREG_VSPER_Pos = 0x18
	// Bit mask of VSPER field.
	SUPC_VREG_VSPER_Msk = 0x7000000

	// VREF: VREF Control
	// Position of TSEN field.
	SUPC_VREF_TSEN_Pos = 0x1
	// Bit mask of TSEN field.
	SUPC_VREF_TSEN_Msk = 0x2
	// Bit TSEN.
	SUPC_VREF_TSEN = 0x2
	// Position of VREFOE field.
	SUPC_VREF_VREFOE_Pos = 0x2
	// Bit mask of VREFOE field.
	SUPC_VREF_VREFOE_Msk = 0x4
	// Bit VREFOE.
	SUPC_VREF_VREFOE = 0x4
	// Position of TSSEL field.
	SUPC_VREF_TSSEL_Pos = 0x3
	// Bit mask of TSSEL field.
	SUPC_VREF_TSSEL_Msk = 0x8
	// Bit TSSEL.
	SUPC_VREF_TSSEL = 0x8
	// Position of RUNSTDBY field.
	SUPC_VREF_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	SUPC_VREF_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	SUPC_VREF_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	SUPC_VREF_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	SUPC_VREF_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	SUPC_VREF_ONDEMAND = 0x80
	// Position of SEL field.
	SUPC_VREF_SEL_Pos = 0x10
	// Bit mask of SEL field.
	SUPC_VREF_SEL_Msk = 0xf0000
	// 1.0V voltage reference typical value
	SUPC_VREF_SEL_1V0 = 0x0
	// 1.1V voltage reference typical value
	SUPC_VREF_SEL_1V1 = 0x1
	// 1.2V voltage reference typical value
	SUPC_VREF_SEL_1V2 = 0x2
	// 1.25V voltage reference typical value
	SUPC_VREF_SEL_1V25 = 0x3
	// 2.0V voltage reference typical value
	SUPC_VREF_SEL_2V0 = 0x4
	// 2.2V voltage reference typical value
	SUPC_VREF_SEL_2V2 = 0x5
	// 2.4V voltage reference typical value
	SUPC_VREF_SEL_2V4 = 0x6
	// 2.5V voltage reference typical value
	SUPC_VREF_SEL_2V5 = 0x7

	// BBPS: Battery Backup Power Switch
	// Position of CONF field.
	SUPC_BBPS_CONF_Pos = 0x0
	// Bit mask of CONF field.
	SUPC_BBPS_CONF_Msk = 0x1
	// Bit CONF.
	SUPC_BBPS_CONF = 0x1
	// The power switch is handled by the BOD33
	SUPC_BBPS_CONF_BOD33 = 0x0
	// In Backup Domain, the backup domain is always supplied by battery backup power
	SUPC_BBPS_CONF_FORCED = 0x1
	// Position of WAKEEN field.
	SUPC_BBPS_WAKEEN_Pos = 0x2
	// Bit mask of WAKEEN field.
	SUPC_BBPS_WAKEEN_Msk = 0x4
	// Bit WAKEEN.
	SUPC_BBPS_WAKEEN = 0x4

	// BKOUT: Backup Output Control
	// Position of ENOUT0 field.
	SUPC_BKOUT_ENOUT0_Pos = 0x0
	// Bit mask of ENOUT0 field.
	SUPC_BKOUT_ENOUT0_Msk = 0x1
	// Bit ENOUT0.
	SUPC_BKOUT_ENOUT0 = 0x1
	// Position of ENOUT1 field.
	SUPC_BKOUT_ENOUT1_Pos = 0x1
	// Bit mask of ENOUT1 field.
	SUPC_BKOUT_ENOUT1_Msk = 0x2
	// Bit ENOUT1.
	SUPC_BKOUT_ENOUT1 = 0x2
	// Position of CLROUT0 field.
	SUPC_BKOUT_CLROUT0_Pos = 0x8
	// Bit mask of CLROUT0 field.
	SUPC_BKOUT_CLROUT0_Msk = 0x100
	// Bit CLROUT0.
	SUPC_BKOUT_CLROUT0 = 0x100
	// Position of CLROUT1 field.
	SUPC_BKOUT_CLROUT1_Pos = 0x9
	// Bit mask of CLROUT1 field.
	SUPC_BKOUT_CLROUT1_Msk = 0x200
	// Bit CLROUT1.
	SUPC_BKOUT_CLROUT1 = 0x200
	// Position of SETOUT0 field.
	SUPC_BKOUT_SETOUT0_Pos = 0x10
	// Bit mask of SETOUT0 field.
	SUPC_BKOUT_SETOUT0_Msk = 0x10000
	// Bit SETOUT0.
	SUPC_BKOUT_SETOUT0 = 0x10000
	// Position of SETOUT1 field.
	SUPC_BKOUT_SETOUT1_Pos = 0x11
	// Bit mask of SETOUT1 field.
	SUPC_BKOUT_SETOUT1_Msk = 0x20000
	// Bit SETOUT1.
	SUPC_BKOUT_SETOUT1 = 0x20000
	// Position of RTCTGLOUT0 field.
	SUPC_BKOUT_RTCTGLOUT0_Pos = 0x18
	// Bit mask of RTCTGLOUT0 field.
	SUPC_BKOUT_RTCTGLOUT0_Msk = 0x1000000
	// Bit RTCTGLOUT0.
	SUPC_BKOUT_RTCTGLOUT0 = 0x1000000
	// Position of RTCTGLOUT1 field.
	SUPC_BKOUT_RTCTGLOUT1_Pos = 0x19
	// Bit mask of RTCTGLOUT1 field.
	SUPC_BKOUT_RTCTGLOUT1_Msk = 0x2000000
	// Bit RTCTGLOUT1.
	SUPC_BKOUT_RTCTGLOUT1 = 0x2000000

	// BKIN: Backup Input Control
	// Position of BKIN0 field.
	SUPC_BKIN_BKIN0_Pos = 0x0
	// Bit mask of BKIN0 field.
	SUPC_BKIN_BKIN0_Msk = 0x1
	// Bit BKIN0.
	SUPC_BKIN_BKIN0 = 0x1
	// Position of BKIN1 field.
	SUPC_BKIN_BKIN1_Pos = 0x1
	// Bit mask of BKIN1 field.
	SUPC_BKIN_BKIN1_Msk = 0x2
	// Bit BKIN1.
	SUPC_BKIN_BKIN1 = 0x2
)

// Bitfields for TC0: Basic Timer Counter
const ()

// Bitfields for TC0_COUNT8: Basic Timer Counter - COUNT8
const (
	// CTRLA: Control A
	// Position of SWRST field.
	TC_COUNT8_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TC_COUNT8_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	TC_COUNT8_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	TC_COUNT8_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TC_COUNT8_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TC_COUNT8_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	TC_COUNT8_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	TC_COUNT8_CTRLA_MODE_Msk = 0xc
	// Counter in 16-bit mode
	TC_COUNT8_CTRLA_MODE_COUNT16 = 0x0
	// Counter in 8-bit mode
	TC_COUNT8_CTRLA_MODE_COUNT8 = 0x1
	// Counter in 32-bit mode
	TC_COUNT8_CTRLA_MODE_COUNT32 = 0x2
	// Position of PRESCSYNC field.
	TC_COUNT8_CTRLA_PRESCSYNC_Pos = 0x4
	// Bit mask of PRESCSYNC field.
	TC_COUNT8_CTRLA_PRESCSYNC_Msk = 0x30
	// Reload or reset the counter on next generic clock
	TC_COUNT8_CTRLA_PRESCSYNC_GCLK = 0x0
	// Reload or reset the counter on next prescaler clock
	TC_COUNT8_CTRLA_PRESCSYNC_PRESC = 0x1
	// Reload or reset the counter on next generic clock and reset the prescaler counter
	TC_COUNT8_CTRLA_PRESCSYNC_RESYNC = 0x2
	// Position of RUNSTDBY field.
	TC_COUNT8_CTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	TC_COUNT8_CTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	TC_COUNT8_CTRLA_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	TC_COUNT8_CTRLA_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	TC_COUNT8_CTRLA_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	TC_COUNT8_CTRLA_ONDEMAND = 0x80
	// Position of PRESCALER field.
	TC_COUNT8_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	TC_COUNT8_CTRLA_PRESCALER_Msk = 0x700
	// Prescaler: GCLK_TC
	TC_COUNT8_CTRLA_PRESCALER_DIV1 = 0x0
	// Prescaler: GCLK_TC/2
	TC_COUNT8_CTRLA_PRESCALER_DIV2 = 0x1
	// Prescaler: GCLK_TC/4
	TC_COUNT8_CTRLA_PRESCALER_DIV4 = 0x2
	// Prescaler: GCLK_TC/8
	TC_COUNT8_CTRLA_PRESCALER_DIV8 = 0x3
	// Prescaler: GCLK_TC/16
	TC_COUNT8_CTRLA_PRESCALER_DIV16 = 0x4
	// Prescaler: GCLK_TC/64
	TC_COUNT8_CTRLA_PRESCALER_DIV64 = 0x5
	// Prescaler: GCLK_TC/256
	TC_COUNT8_CTRLA_PRESCALER_DIV256 = 0x6
	// Prescaler: GCLK_TC/1024
	TC_COUNT8_CTRLA_PRESCALER_DIV1024 = 0x7
	// Position of ALOCK field.
	TC_COUNT8_CTRLA_ALOCK_Pos = 0xb
	// Bit mask of ALOCK field.
	TC_COUNT8_CTRLA_ALOCK_Msk = 0x800
	// Bit ALOCK.
	TC_COUNT8_CTRLA_ALOCK = 0x800
	// Position of CAPTEN0 field.
	TC_COUNT8_CTRLA_CAPTEN0_Pos = 0x10
	// Bit mask of CAPTEN0 field.
	TC_COUNT8_CTRLA_CAPTEN0_Msk = 0x10000
	// Bit CAPTEN0.
	TC_COUNT8_CTRLA_CAPTEN0 = 0x10000
	// Position of CAPTEN1 field.
	TC_COUNT8_CTRLA_CAPTEN1_Pos = 0x11
	// Bit mask of CAPTEN1 field.
	TC_COUNT8_CTRLA_CAPTEN1_Msk = 0x20000
	// Bit CAPTEN1.
	TC_COUNT8_CTRLA_CAPTEN1 = 0x20000
	// Position of COPEN0 field.
	TC_COUNT8_CTRLA_COPEN0_Pos = 0x14
	// Bit mask of COPEN0 field.
	TC_COUNT8_CTRLA_COPEN0_Msk = 0x100000
	// Bit COPEN0.
	TC_COUNT8_CTRLA_COPEN0 = 0x100000
	// Position of COPEN1 field.
	TC_COUNT8_CTRLA_COPEN1_Pos = 0x15
	// Bit mask of COPEN1 field.
	TC_COUNT8_CTRLA_COPEN1_Msk = 0x200000
	// Bit COPEN1.
	TC_COUNT8_CTRLA_COPEN1 = 0x200000
	// Position of CAPTMODE0 field.
	TC_COUNT8_CTRLA_CAPTMODE0_Pos = 0x18
	// Bit mask of CAPTMODE0 field.
	TC_COUNT8_CTRLA_CAPTMODE0_Msk = 0x3000000
	// Default capture
	TC_COUNT8_CTRLA_CAPTMODE0_DEFAULT = 0x0
	// Minimum capture
	TC_COUNT8_CTRLA_CAPTMODE0_CAPTMIN = 0x1
	// Maximum capture
	TC_COUNT8_CTRLA_CAPTMODE0_CAPTMAX = 0x2
	// Position of CAPTMODE1 field.
	TC_COUNT8_CTRLA_CAPTMODE1_Pos = 0x1b
	// Bit mask of CAPTMODE1 field.
	TC_COUNT8_CTRLA_CAPTMODE1_Msk = 0x18000000
	// Default capture
	TC_COUNT8_CTRLA_CAPTMODE1_DEFAULT = 0x0
	// Minimum capture
	TC_COUNT8_CTRLA_CAPTMODE1_CAPTMIN = 0x1
	// Maximum capture
	TC_COUNT8_CTRLA_CAPTMODE1_CAPTMAX = 0x2

	// CTRLBCLR: Control B Clear
	// Position of DIR field.
	TC_COUNT8_CTRLBCLR_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TC_COUNT8_CTRLBCLR_DIR_Msk = 0x1
	// Bit DIR.
	TC_COUNT8_CTRLBCLR_DIR = 0x1
	// Position of LUPD field.
	TC_COUNT8_CTRLBCLR_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TC_COUNT8_CTRLBCLR_LUPD_Msk = 0x2
	// Bit LUPD.
	TC_COUNT8_CTRLBCLR_LUPD = 0x2
	// Position of ONESHOT field.
	TC_COUNT8_CTRLBCLR_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TC_COUNT8_CTRLBCLR_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TC_COUNT8_CTRLBCLR_ONESHOT = 0x4
	// Position of CMD field.
	TC_COUNT8_CTRLBCLR_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TC_COUNT8_CTRLBCLR_CMD_Msk = 0xe0
	// No action
	TC_COUNT8_CTRLBCLR_CMD_NONE = 0x0
	// Force a start, restart or retrigger
	TC_COUNT8_CTRLBCLR_CMD_RETRIGGER = 0x1
	// Force a stop
	TC_COUNT8_CTRLBCLR_CMD_STOP = 0x2
	// Force update of double-buffered register
	TC_COUNT8_CTRLBCLR_CMD_UPDATE = 0x3
	// Force a read synchronization of COUNT
	TC_COUNT8_CTRLBCLR_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TC_COUNT8_CTRLBCLR_CMD_DMAOS = 0x5

	// CTRLBSET: Control B Set
	// Position of DIR field.
	TC_COUNT8_CTRLBSET_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TC_COUNT8_CTRLBSET_DIR_Msk = 0x1
	// Bit DIR.
	TC_COUNT8_CTRLBSET_DIR = 0x1
	// Position of LUPD field.
	TC_COUNT8_CTRLBSET_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TC_COUNT8_CTRLBSET_LUPD_Msk = 0x2
	// Bit LUPD.
	TC_COUNT8_CTRLBSET_LUPD = 0x2
	// Position of ONESHOT field.
	TC_COUNT8_CTRLBSET_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TC_COUNT8_CTRLBSET_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TC_COUNT8_CTRLBSET_ONESHOT = 0x4
	// Position of CMD field.
	TC_COUNT8_CTRLBSET_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TC_COUNT8_CTRLBSET_CMD_Msk = 0xe0
	// No action
	TC_COUNT8_CTRLBSET_CMD_NONE = 0x0
	// Force a start, restart or retrigger
	TC_COUNT8_CTRLBSET_CMD_RETRIGGER = 0x1
	// Force a stop
	TC_COUNT8_CTRLBSET_CMD_STOP = 0x2
	// Force update of double-buffered register
	TC_COUNT8_CTRLBSET_CMD_UPDATE = 0x3
	// Force a read synchronization of COUNT
	TC_COUNT8_CTRLBSET_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TC_COUNT8_CTRLBSET_CMD_DMAOS = 0x5

	// EVCTRL: Event Control
	// Position of EVACT field.
	TC_COUNT8_EVCTRL_EVACT_Pos = 0x0
	// Bit mask of EVACT field.
	TC_COUNT8_EVCTRL_EVACT_Msk = 0x7
	// Event action disabled
	TC_COUNT8_EVCTRL_EVACT_OFF = 0x0
	// Start, restart or retrigger TC on event
	TC_COUNT8_EVCTRL_EVACT_RETRIGGER = 0x1
	// Count on event
	TC_COUNT8_EVCTRL_EVACT_COUNT = 0x2
	// Start TC on event
	TC_COUNT8_EVCTRL_EVACT_START = 0x3
	// Time stamp capture
	TC_COUNT8_EVCTRL_EVACT_STAMP = 0x4
	// Period catured in CC0, pulse width in CC1
	TC_COUNT8_EVCTRL_EVACT_PPW = 0x5
	// Period catured in CC1, pulse width in CC0
	TC_COUNT8_EVCTRL_EVACT_PWP = 0x6
	// Pulse width capture
	TC_COUNT8_EVCTRL_EVACT_PW = 0x7
	// Position of TCINV field.
	TC_COUNT8_EVCTRL_TCINV_Pos = 0x4
	// Bit mask of TCINV field.
	TC_COUNT8_EVCTRL_TCINV_Msk = 0x10
	// Bit TCINV.
	TC_COUNT8_EVCTRL_TCINV = 0x10
	// Position of TCEI field.
	TC_COUNT8_EVCTRL_TCEI_Pos = 0x5
	// Bit mask of TCEI field.
	TC_COUNT8_EVCTRL_TCEI_Msk = 0x20
	// Bit TCEI.
	TC_COUNT8_EVCTRL_TCEI = 0x20
	// Position of OVFEO field.
	TC_COUNT8_EVCTRL_OVFEO_Pos = 0x8
	// Bit mask of OVFEO field.
	TC_COUNT8_EVCTRL_OVFEO_Msk = 0x100
	// Bit OVFEO.
	TC_COUNT8_EVCTRL_OVFEO = 0x100
	// Position of MCEO0 field.
	TC_COUNT8_EVCTRL_MCEO0_Pos = 0xc
	// Bit mask of MCEO0 field.
	TC_COUNT8_EVCTRL_MCEO0_Msk = 0x1000
	// Bit MCEO0.
	TC_COUNT8_EVCTRL_MCEO0 = 0x1000
	// Position of MCEO1 field.
	TC_COUNT8_EVCTRL_MCEO1_Pos = 0xd
	// Bit mask of MCEO1 field.
	TC_COUNT8_EVCTRL_MCEO1_Msk = 0x2000
	// Bit MCEO1.
	TC_COUNT8_EVCTRL_MCEO1 = 0x2000

	// INTENCLR: Interrupt Enable Clear
	// Position of OVF field.
	TC_COUNT8_INTENCLR_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT8_INTENCLR_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT8_INTENCLR_OVF = 0x1
	// Position of ERR field.
	TC_COUNT8_INTENCLR_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT8_INTENCLR_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT8_INTENCLR_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT8_INTENCLR_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT8_INTENCLR_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT8_INTENCLR_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT8_INTENCLR_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT8_INTENCLR_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT8_INTENCLR_MC1 = 0x20

	// INTENSET: Interrupt Enable Set
	// Position of OVF field.
	TC_COUNT8_INTENSET_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT8_INTENSET_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT8_INTENSET_OVF = 0x1
	// Position of ERR field.
	TC_COUNT8_INTENSET_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT8_INTENSET_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT8_INTENSET_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT8_INTENSET_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT8_INTENSET_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT8_INTENSET_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT8_INTENSET_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT8_INTENSET_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT8_INTENSET_MC1 = 0x20

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of OVF field.
	TC_COUNT8_INTFLAG_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT8_INTFLAG_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT8_INTFLAG_OVF = 0x1
	// Position of ERR field.
	TC_COUNT8_INTFLAG_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT8_INTFLAG_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT8_INTFLAG_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT8_INTFLAG_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT8_INTFLAG_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT8_INTFLAG_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT8_INTFLAG_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT8_INTFLAG_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT8_INTFLAG_MC1 = 0x20

	// STATUS: Status
	// Position of STOP field.
	TC_COUNT8_STATUS_STOP_Pos = 0x0
	// Bit mask of STOP field.
	TC_COUNT8_STATUS_STOP_Msk = 0x1
	// Bit STOP.
	TC_COUNT8_STATUS_STOP = 0x1
	// Position of SLAVE field.
	TC_COUNT8_STATUS_SLAVE_Pos = 0x1
	// Bit mask of SLAVE field.
	TC_COUNT8_STATUS_SLAVE_Msk = 0x2
	// Bit SLAVE.
	TC_COUNT8_STATUS_SLAVE = 0x2
	// Position of PERBUFV field.
	TC_COUNT8_STATUS_PERBUFV_Pos = 0x3
	// Bit mask of PERBUFV field.
	TC_COUNT8_STATUS_PERBUFV_Msk = 0x8
	// Bit PERBUFV.
	TC_COUNT8_STATUS_PERBUFV = 0x8
	// Position of CCBUFV0 field.
	TC_COUNT8_STATUS_CCBUFV0_Pos = 0x4
	// Bit mask of CCBUFV0 field.
	TC_COUNT8_STATUS_CCBUFV0_Msk = 0x10
	// Bit CCBUFV0.
	TC_COUNT8_STATUS_CCBUFV0 = 0x10
	// Position of CCBUFV1 field.
	TC_COUNT8_STATUS_CCBUFV1_Pos = 0x5
	// Bit mask of CCBUFV1 field.
	TC_COUNT8_STATUS_CCBUFV1_Msk = 0x20
	// Bit CCBUFV1.
	TC_COUNT8_STATUS_CCBUFV1 = 0x20

	// WAVE: Waveform Generation Control
	// Position of WAVEGEN field.
	TC_COUNT8_WAVE_WAVEGEN_Pos = 0x0
	// Bit mask of WAVEGEN field.
	TC_COUNT8_WAVE_WAVEGEN_Msk = 0x3
	// Normal frequency
	TC_COUNT8_WAVE_WAVEGEN_NFRQ = 0x0
	// Match frequency
	TC_COUNT8_WAVE_WAVEGEN_MFRQ = 0x1
	// Normal PWM
	TC_COUNT8_WAVE_WAVEGEN_NPWM = 0x2
	// Match PWM
	TC_COUNT8_WAVE_WAVEGEN_MPWM = 0x3

	// DRVCTRL: Control C
	// Position of INVEN0 field.
	TC_COUNT8_DRVCTRL_INVEN0_Pos = 0x0
	// Bit mask of INVEN0 field.
	TC_COUNT8_DRVCTRL_INVEN0_Msk = 0x1
	// Bit INVEN0.
	TC_COUNT8_DRVCTRL_INVEN0 = 0x1
	// Position of INVEN1 field.
	TC_COUNT8_DRVCTRL_INVEN1_Pos = 0x1
	// Bit mask of INVEN1 field.
	TC_COUNT8_DRVCTRL_INVEN1_Msk = 0x2
	// Bit INVEN1.
	TC_COUNT8_DRVCTRL_INVEN1 = 0x2

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	TC_COUNT8_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	TC_COUNT8_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	TC_COUNT8_DBGCTRL_DBGRUN = 0x1

	// SYNCBUSY: Synchronization Status
	// Position of SWRST field.
	TC_COUNT8_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TC_COUNT8_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	TC_COUNT8_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	TC_COUNT8_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TC_COUNT8_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TC_COUNT8_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	TC_COUNT8_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	TC_COUNT8_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	TC_COUNT8_SYNCBUSY_CTRLB = 0x4
	// Position of STATUS field.
	TC_COUNT8_SYNCBUSY_STATUS_Pos = 0x3
	// Bit mask of STATUS field.
	TC_COUNT8_SYNCBUSY_STATUS_Msk = 0x8
	// Bit STATUS.
	TC_COUNT8_SYNCBUSY_STATUS = 0x8
	// Position of COUNT field.
	TC_COUNT8_SYNCBUSY_COUNT_Pos = 0x4
	// Bit mask of COUNT field.
	TC_COUNT8_SYNCBUSY_COUNT_Msk = 0x10
	// Bit COUNT.
	TC_COUNT8_SYNCBUSY_COUNT = 0x10
	// Position of PER field.
	TC_COUNT8_SYNCBUSY_PER_Pos = 0x5
	// Bit mask of PER field.
	TC_COUNT8_SYNCBUSY_PER_Msk = 0x20
	// Bit PER.
	TC_COUNT8_SYNCBUSY_PER = 0x20
	// Position of CC0 field.
	TC_COUNT8_SYNCBUSY_CC0_Pos = 0x6
	// Bit mask of CC0 field.
	TC_COUNT8_SYNCBUSY_CC0_Msk = 0x40
	// Bit CC0.
	TC_COUNT8_SYNCBUSY_CC0 = 0x40
	// Position of CC1 field.
	TC_COUNT8_SYNCBUSY_CC1_Pos = 0x7
	// Bit mask of CC1 field.
	TC_COUNT8_SYNCBUSY_CC1_Msk = 0x80
	// Bit CC1.
	TC_COUNT8_SYNCBUSY_CC1 = 0x80

	// COUNT: COUNT8 Count
	// Position of COUNT field.
	TC_COUNT8_COUNT_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	TC_COUNT8_COUNT_COUNT_Msk = 0xff

	// PER: COUNT8 Period
	// Position of PER field.
	TC_COUNT8_PER_PER_Pos = 0x0
	// Bit mask of PER field.
	TC_COUNT8_PER_PER_Msk = 0xff

	// CC: COUNT8 Compare and Capture
	// Position of CC field.
	TC_COUNT8_CC_CC_Pos = 0x0
	// Bit mask of CC field.
	TC_COUNT8_CC_CC_Msk = 0xff

	// PERBUF: COUNT8 Period Buffer
	// Position of PERBUF field.
	TC_COUNT8_PERBUF_PERBUF_Pos = 0x0
	// Bit mask of PERBUF field.
	TC_COUNT8_PERBUF_PERBUF_Msk = 0xff

	// CCBUF: COUNT8 Compare and Capture Buffer
	// Position of CCBUF field.
	TC_COUNT8_CCBUF_CCBUF_Pos = 0x0
	// Bit mask of CCBUF field.
	TC_COUNT8_CCBUF_CCBUF_Msk = 0xff
)

// Bitfields for TC0_COUNT16: Basic Timer Counter - COUNT16
const (
	// CTRLA: Control A
	// Position of SWRST field.
	TC_COUNT16_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TC_COUNT16_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	TC_COUNT16_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	TC_COUNT16_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TC_COUNT16_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TC_COUNT16_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	TC_COUNT16_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	TC_COUNT16_CTRLA_MODE_Msk = 0xc
	// Counter in 16-bit mode
	TC_COUNT16_CTRLA_MODE_COUNT16 = 0x0
	// Counter in 8-bit mode
	TC_COUNT16_CTRLA_MODE_COUNT8 = 0x1
	// Counter in 32-bit mode
	TC_COUNT16_CTRLA_MODE_COUNT32 = 0x2
	// Position of PRESCSYNC field.
	TC_COUNT16_CTRLA_PRESCSYNC_Pos = 0x4
	// Bit mask of PRESCSYNC field.
	TC_COUNT16_CTRLA_PRESCSYNC_Msk = 0x30
	// Reload or reset the counter on next generic clock
	TC_COUNT16_CTRLA_PRESCSYNC_GCLK = 0x0
	// Reload or reset the counter on next prescaler clock
	TC_COUNT16_CTRLA_PRESCSYNC_PRESC = 0x1
	// Reload or reset the counter on next generic clock and reset the prescaler counter
	TC_COUNT16_CTRLA_PRESCSYNC_RESYNC = 0x2
	// Position of RUNSTDBY field.
	TC_COUNT16_CTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	TC_COUNT16_CTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	TC_COUNT16_CTRLA_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	TC_COUNT16_CTRLA_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	TC_COUNT16_CTRLA_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	TC_COUNT16_CTRLA_ONDEMAND = 0x80
	// Position of PRESCALER field.
	TC_COUNT16_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	TC_COUNT16_CTRLA_PRESCALER_Msk = 0x700
	// Prescaler: GCLK_TC
	TC_COUNT16_CTRLA_PRESCALER_DIV1 = 0x0
	// Prescaler: GCLK_TC/2
	TC_COUNT16_CTRLA_PRESCALER_DIV2 = 0x1
	// Prescaler: GCLK_TC/4
	TC_COUNT16_CTRLA_PRESCALER_DIV4 = 0x2
	// Prescaler: GCLK_TC/8
	TC_COUNT16_CTRLA_PRESCALER_DIV8 = 0x3
	// Prescaler: GCLK_TC/16
	TC_COUNT16_CTRLA_PRESCALER_DIV16 = 0x4
	// Prescaler: GCLK_TC/64
	TC_COUNT16_CTRLA_PRESCALER_DIV64 = 0x5
	// Prescaler: GCLK_TC/256
	TC_COUNT16_CTRLA_PRESCALER_DIV256 = 0x6
	// Prescaler: GCLK_TC/1024
	TC_COUNT16_CTRLA_PRESCALER_DIV1024 = 0x7
	// Position of ALOCK field.
	TC_COUNT16_CTRLA_ALOCK_Pos = 0xb
	// Bit mask of ALOCK field.
	TC_COUNT16_CTRLA_ALOCK_Msk = 0x800
	// Bit ALOCK.
	TC_COUNT16_CTRLA_ALOCK = 0x800
	// Position of CAPTEN0 field.
	TC_COUNT16_CTRLA_CAPTEN0_Pos = 0x10
	// Bit mask of CAPTEN0 field.
	TC_COUNT16_CTRLA_CAPTEN0_Msk = 0x10000
	// Bit CAPTEN0.
	TC_COUNT16_CTRLA_CAPTEN0 = 0x10000
	// Position of CAPTEN1 field.
	TC_COUNT16_CTRLA_CAPTEN1_Pos = 0x11
	// Bit mask of CAPTEN1 field.
	TC_COUNT16_CTRLA_CAPTEN1_Msk = 0x20000
	// Bit CAPTEN1.
	TC_COUNT16_CTRLA_CAPTEN1 = 0x20000
	// Position of COPEN0 field.
	TC_COUNT16_CTRLA_COPEN0_Pos = 0x14
	// Bit mask of COPEN0 field.
	TC_COUNT16_CTRLA_COPEN0_Msk = 0x100000
	// Bit COPEN0.
	TC_COUNT16_CTRLA_COPEN0 = 0x100000
	// Position of COPEN1 field.
	TC_COUNT16_CTRLA_COPEN1_Pos = 0x15
	// Bit mask of COPEN1 field.
	TC_COUNT16_CTRLA_COPEN1_Msk = 0x200000
	// Bit COPEN1.
	TC_COUNT16_CTRLA_COPEN1 = 0x200000
	// Position of CAPTMODE0 field.
	TC_COUNT16_CTRLA_CAPTMODE0_Pos = 0x18
	// Bit mask of CAPTMODE0 field.
	TC_COUNT16_CTRLA_CAPTMODE0_Msk = 0x3000000
	// Default capture
	TC_COUNT16_CTRLA_CAPTMODE0_DEFAULT = 0x0
	// Minimum capture
	TC_COUNT16_CTRLA_CAPTMODE0_CAPTMIN = 0x1
	// Maximum capture
	TC_COUNT16_CTRLA_CAPTMODE0_CAPTMAX = 0x2
	// Position of CAPTMODE1 field.
	TC_COUNT16_CTRLA_CAPTMODE1_Pos = 0x1b
	// Bit mask of CAPTMODE1 field.
	TC_COUNT16_CTRLA_CAPTMODE1_Msk = 0x18000000
	// Default capture
	TC_COUNT16_CTRLA_CAPTMODE1_DEFAULT = 0x0
	// Minimum capture
	TC_COUNT16_CTRLA_CAPTMODE1_CAPTMIN = 0x1
	// Maximum capture
	TC_COUNT16_CTRLA_CAPTMODE1_CAPTMAX = 0x2

	// CTRLBCLR: Control B Clear
	// Position of DIR field.
	TC_COUNT16_CTRLBCLR_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TC_COUNT16_CTRLBCLR_DIR_Msk = 0x1
	// Bit DIR.
	TC_COUNT16_CTRLBCLR_DIR = 0x1
	// Position of LUPD field.
	TC_COUNT16_CTRLBCLR_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TC_COUNT16_CTRLBCLR_LUPD_Msk = 0x2
	// Bit LUPD.
	TC_COUNT16_CTRLBCLR_LUPD = 0x2
	// Position of ONESHOT field.
	TC_COUNT16_CTRLBCLR_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TC_COUNT16_CTRLBCLR_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TC_COUNT16_CTRLBCLR_ONESHOT = 0x4
	// Position of CMD field.
	TC_COUNT16_CTRLBCLR_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TC_COUNT16_CTRLBCLR_CMD_Msk = 0xe0
	// No action
	TC_COUNT16_CTRLBCLR_CMD_NONE = 0x0
	// Force a start, restart or retrigger
	TC_COUNT16_CTRLBCLR_CMD_RETRIGGER = 0x1
	// Force a stop
	TC_COUNT16_CTRLBCLR_CMD_STOP = 0x2
	// Force update of double-buffered register
	TC_COUNT16_CTRLBCLR_CMD_UPDATE = 0x3
	// Force a read synchronization of COUNT
	TC_COUNT16_CTRLBCLR_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TC_COUNT16_CTRLBCLR_CMD_DMAOS = 0x5

	// CTRLBSET: Control B Set
	// Position of DIR field.
	TC_COUNT16_CTRLBSET_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TC_COUNT16_CTRLBSET_DIR_Msk = 0x1
	// Bit DIR.
	TC_COUNT16_CTRLBSET_DIR = 0x1
	// Position of LUPD field.
	TC_COUNT16_CTRLBSET_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TC_COUNT16_CTRLBSET_LUPD_Msk = 0x2
	// Bit LUPD.
	TC_COUNT16_CTRLBSET_LUPD = 0x2
	// Position of ONESHOT field.
	TC_COUNT16_CTRLBSET_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TC_COUNT16_CTRLBSET_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TC_COUNT16_CTRLBSET_ONESHOT = 0x4
	// Position of CMD field.
	TC_COUNT16_CTRLBSET_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TC_COUNT16_CTRLBSET_CMD_Msk = 0xe0
	// No action
	TC_COUNT16_CTRLBSET_CMD_NONE = 0x0
	// Force a start, restart or retrigger
	TC_COUNT16_CTRLBSET_CMD_RETRIGGER = 0x1
	// Force a stop
	TC_COUNT16_CTRLBSET_CMD_STOP = 0x2
	// Force update of double-buffered register
	TC_COUNT16_CTRLBSET_CMD_UPDATE = 0x3
	// Force a read synchronization of COUNT
	TC_COUNT16_CTRLBSET_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TC_COUNT16_CTRLBSET_CMD_DMAOS = 0x5

	// EVCTRL: Event Control
	// Position of EVACT field.
	TC_COUNT16_EVCTRL_EVACT_Pos = 0x0
	// Bit mask of EVACT field.
	TC_COUNT16_EVCTRL_EVACT_Msk = 0x7
	// Event action disabled
	TC_COUNT16_EVCTRL_EVACT_OFF = 0x0
	// Start, restart or retrigger TC on event
	TC_COUNT16_EVCTRL_EVACT_RETRIGGER = 0x1
	// Count on event
	TC_COUNT16_EVCTRL_EVACT_COUNT = 0x2
	// Start TC on event
	TC_COUNT16_EVCTRL_EVACT_START = 0x3
	// Time stamp capture
	TC_COUNT16_EVCTRL_EVACT_STAMP = 0x4
	// Period catured in CC0, pulse width in CC1
	TC_COUNT16_EVCTRL_EVACT_PPW = 0x5
	// Period catured in CC1, pulse width in CC0
	TC_COUNT16_EVCTRL_EVACT_PWP = 0x6
	// Pulse width capture
	TC_COUNT16_EVCTRL_EVACT_PW = 0x7
	// Position of TCINV field.
	TC_COUNT16_EVCTRL_TCINV_Pos = 0x4
	// Bit mask of TCINV field.
	TC_COUNT16_EVCTRL_TCINV_Msk = 0x10
	// Bit TCINV.
	TC_COUNT16_EVCTRL_TCINV = 0x10
	// Position of TCEI field.
	TC_COUNT16_EVCTRL_TCEI_Pos = 0x5
	// Bit mask of TCEI field.
	TC_COUNT16_EVCTRL_TCEI_Msk = 0x20
	// Bit TCEI.
	TC_COUNT16_EVCTRL_TCEI = 0x20
	// Position of OVFEO field.
	TC_COUNT16_EVCTRL_OVFEO_Pos = 0x8
	// Bit mask of OVFEO field.
	TC_COUNT16_EVCTRL_OVFEO_Msk = 0x100
	// Bit OVFEO.
	TC_COUNT16_EVCTRL_OVFEO = 0x100
	// Position of MCEO0 field.
	TC_COUNT16_EVCTRL_MCEO0_Pos = 0xc
	// Bit mask of MCEO0 field.
	TC_COUNT16_EVCTRL_MCEO0_Msk = 0x1000
	// Bit MCEO0.
	TC_COUNT16_EVCTRL_MCEO0 = 0x1000
	// Position of MCEO1 field.
	TC_COUNT16_EVCTRL_MCEO1_Pos = 0xd
	// Bit mask of MCEO1 field.
	TC_COUNT16_EVCTRL_MCEO1_Msk = 0x2000
	// Bit MCEO1.
	TC_COUNT16_EVCTRL_MCEO1 = 0x2000

	// INTENCLR: Interrupt Enable Clear
	// Position of OVF field.
	TC_COUNT16_INTENCLR_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT16_INTENCLR_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT16_INTENCLR_OVF = 0x1
	// Position of ERR field.
	TC_COUNT16_INTENCLR_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT16_INTENCLR_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT16_INTENCLR_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT16_INTENCLR_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT16_INTENCLR_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT16_INTENCLR_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT16_INTENCLR_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT16_INTENCLR_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT16_INTENCLR_MC1 = 0x20

	// INTENSET: Interrupt Enable Set
	// Position of OVF field.
	TC_COUNT16_INTENSET_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT16_INTENSET_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT16_INTENSET_OVF = 0x1
	// Position of ERR field.
	TC_COUNT16_INTENSET_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT16_INTENSET_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT16_INTENSET_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT16_INTENSET_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT16_INTENSET_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT16_INTENSET_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT16_INTENSET_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT16_INTENSET_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT16_INTENSET_MC1 = 0x20

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of OVF field.
	TC_COUNT16_INTFLAG_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT16_INTFLAG_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT16_INTFLAG_OVF = 0x1
	// Position of ERR field.
	TC_COUNT16_INTFLAG_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT16_INTFLAG_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT16_INTFLAG_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT16_INTFLAG_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT16_INTFLAG_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT16_INTFLAG_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT16_INTFLAG_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT16_INTFLAG_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT16_INTFLAG_MC1 = 0x20

	// STATUS: Status
	// Position of STOP field.
	TC_COUNT16_STATUS_STOP_Pos = 0x0
	// Bit mask of STOP field.
	TC_COUNT16_STATUS_STOP_Msk = 0x1
	// Bit STOP.
	TC_COUNT16_STATUS_STOP = 0x1
	// Position of SLAVE field.
	TC_COUNT16_STATUS_SLAVE_Pos = 0x1
	// Bit mask of SLAVE field.
	TC_COUNT16_STATUS_SLAVE_Msk = 0x2
	// Bit SLAVE.
	TC_COUNT16_STATUS_SLAVE = 0x2
	// Position of PERBUFV field.
	TC_COUNT16_STATUS_PERBUFV_Pos = 0x3
	// Bit mask of PERBUFV field.
	TC_COUNT16_STATUS_PERBUFV_Msk = 0x8
	// Bit PERBUFV.
	TC_COUNT16_STATUS_PERBUFV = 0x8
	// Position of CCBUFV0 field.
	TC_COUNT16_STATUS_CCBUFV0_Pos = 0x4
	// Bit mask of CCBUFV0 field.
	TC_COUNT16_STATUS_CCBUFV0_Msk = 0x10
	// Bit CCBUFV0.
	TC_COUNT16_STATUS_CCBUFV0 = 0x10
	// Position of CCBUFV1 field.
	TC_COUNT16_STATUS_CCBUFV1_Pos = 0x5
	// Bit mask of CCBUFV1 field.
	TC_COUNT16_STATUS_CCBUFV1_Msk = 0x20
	// Bit CCBUFV1.
	TC_COUNT16_STATUS_CCBUFV1 = 0x20

	// WAVE: Waveform Generation Control
	// Position of WAVEGEN field.
	TC_COUNT16_WAVE_WAVEGEN_Pos = 0x0
	// Bit mask of WAVEGEN field.
	TC_COUNT16_WAVE_WAVEGEN_Msk = 0x3
	// Normal frequency
	TC_COUNT16_WAVE_WAVEGEN_NFRQ = 0x0
	// Match frequency
	TC_COUNT16_WAVE_WAVEGEN_MFRQ = 0x1
	// Normal PWM
	TC_COUNT16_WAVE_WAVEGEN_NPWM = 0x2
	// Match PWM
	TC_COUNT16_WAVE_WAVEGEN_MPWM = 0x3

	// DRVCTRL: Control C
	// Position of INVEN0 field.
	TC_COUNT16_DRVCTRL_INVEN0_Pos = 0x0
	// Bit mask of INVEN0 field.
	TC_COUNT16_DRVCTRL_INVEN0_Msk = 0x1
	// Bit INVEN0.
	TC_COUNT16_DRVCTRL_INVEN0 = 0x1
	// Position of INVEN1 field.
	TC_COUNT16_DRVCTRL_INVEN1_Pos = 0x1
	// Bit mask of INVEN1 field.
	TC_COUNT16_DRVCTRL_INVEN1_Msk = 0x2
	// Bit INVEN1.
	TC_COUNT16_DRVCTRL_INVEN1 = 0x2

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	TC_COUNT16_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	TC_COUNT16_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	TC_COUNT16_DBGCTRL_DBGRUN = 0x1

	// SYNCBUSY: Synchronization Status
	// Position of SWRST field.
	TC_COUNT16_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TC_COUNT16_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	TC_COUNT16_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	TC_COUNT16_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TC_COUNT16_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TC_COUNT16_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	TC_COUNT16_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	TC_COUNT16_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	TC_COUNT16_SYNCBUSY_CTRLB = 0x4
	// Position of STATUS field.
	TC_COUNT16_SYNCBUSY_STATUS_Pos = 0x3
	// Bit mask of STATUS field.
	TC_COUNT16_SYNCBUSY_STATUS_Msk = 0x8
	// Bit STATUS.
	TC_COUNT16_SYNCBUSY_STATUS = 0x8
	// Position of COUNT field.
	TC_COUNT16_SYNCBUSY_COUNT_Pos = 0x4
	// Bit mask of COUNT field.
	TC_COUNT16_SYNCBUSY_COUNT_Msk = 0x10
	// Bit COUNT.
	TC_COUNT16_SYNCBUSY_COUNT = 0x10
	// Position of PER field.
	TC_COUNT16_SYNCBUSY_PER_Pos = 0x5
	// Bit mask of PER field.
	TC_COUNT16_SYNCBUSY_PER_Msk = 0x20
	// Bit PER.
	TC_COUNT16_SYNCBUSY_PER = 0x20
	// Position of CC0 field.
	TC_COUNT16_SYNCBUSY_CC0_Pos = 0x6
	// Bit mask of CC0 field.
	TC_COUNT16_SYNCBUSY_CC0_Msk = 0x40
	// Bit CC0.
	TC_COUNT16_SYNCBUSY_CC0 = 0x40
	// Position of CC1 field.
	TC_COUNT16_SYNCBUSY_CC1_Pos = 0x7
	// Bit mask of CC1 field.
	TC_COUNT16_SYNCBUSY_CC1_Msk = 0x80
	// Bit CC1.
	TC_COUNT16_SYNCBUSY_CC1 = 0x80

	// COUNT: COUNT16 Count
	// Position of COUNT field.
	TC_COUNT16_COUNT_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	TC_COUNT16_COUNT_COUNT_Msk = 0xffff

	// CC: COUNT16 Compare and Capture
	// Position of CC field.
	TC_COUNT16_CC_CC_Pos = 0x0
	// Bit mask of CC field.
	TC_COUNT16_CC_CC_Msk = 0xffff

	// CCBUF: COUNT16 Compare and Capture Buffer
	// Position of CCBUF field.
	TC_COUNT16_CCBUF_CCBUF_Pos = 0x0
	// Bit mask of CCBUF field.
	TC_COUNT16_CCBUF_CCBUF_Msk = 0xffff
)

// Bitfields for TC0_COUNT32: Basic Timer Counter - COUNT32
const (
	// CTRLA: Control A
	// Position of SWRST field.
	TC_COUNT32_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TC_COUNT32_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	TC_COUNT32_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	TC_COUNT32_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TC_COUNT32_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TC_COUNT32_CTRLA_ENABLE = 0x2
	// Position of MODE field.
	TC_COUNT32_CTRLA_MODE_Pos = 0x2
	// Bit mask of MODE field.
	TC_COUNT32_CTRLA_MODE_Msk = 0xc
	// Counter in 16-bit mode
	TC_COUNT32_CTRLA_MODE_COUNT16 = 0x0
	// Counter in 8-bit mode
	TC_COUNT32_CTRLA_MODE_COUNT8 = 0x1
	// Counter in 32-bit mode
	TC_COUNT32_CTRLA_MODE_COUNT32 = 0x2
	// Position of PRESCSYNC field.
	TC_COUNT32_CTRLA_PRESCSYNC_Pos = 0x4
	// Bit mask of PRESCSYNC field.
	TC_COUNT32_CTRLA_PRESCSYNC_Msk = 0x30
	// Reload or reset the counter on next generic clock
	TC_COUNT32_CTRLA_PRESCSYNC_GCLK = 0x0
	// Reload or reset the counter on next prescaler clock
	TC_COUNT32_CTRLA_PRESCSYNC_PRESC = 0x1
	// Reload or reset the counter on next generic clock and reset the prescaler counter
	TC_COUNT32_CTRLA_PRESCSYNC_RESYNC = 0x2
	// Position of RUNSTDBY field.
	TC_COUNT32_CTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	TC_COUNT32_CTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	TC_COUNT32_CTRLA_RUNSTDBY = 0x40
	// Position of ONDEMAND field.
	TC_COUNT32_CTRLA_ONDEMAND_Pos = 0x7
	// Bit mask of ONDEMAND field.
	TC_COUNT32_CTRLA_ONDEMAND_Msk = 0x80
	// Bit ONDEMAND.
	TC_COUNT32_CTRLA_ONDEMAND = 0x80
	// Position of PRESCALER field.
	TC_COUNT32_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	TC_COUNT32_CTRLA_PRESCALER_Msk = 0x700
	// Prescaler: GCLK_TC
	TC_COUNT32_CTRLA_PRESCALER_DIV1 = 0x0
	// Prescaler: GCLK_TC/2
	TC_COUNT32_CTRLA_PRESCALER_DIV2 = 0x1
	// Prescaler: GCLK_TC/4
	TC_COUNT32_CTRLA_PRESCALER_DIV4 = 0x2
	// Prescaler: GCLK_TC/8
	TC_COUNT32_CTRLA_PRESCALER_DIV8 = 0x3
	// Prescaler: GCLK_TC/16
	TC_COUNT32_CTRLA_PRESCALER_DIV16 = 0x4
	// Prescaler: GCLK_TC/64
	TC_COUNT32_CTRLA_PRESCALER_DIV64 = 0x5
	// Prescaler: GCLK_TC/256
	TC_COUNT32_CTRLA_PRESCALER_DIV256 = 0x6
	// Prescaler: GCLK_TC/1024
	TC_COUNT32_CTRLA_PRESCALER_DIV1024 = 0x7
	// Position of ALOCK field.
	TC_COUNT32_CTRLA_ALOCK_Pos = 0xb
	// Bit mask of ALOCK field.
	TC_COUNT32_CTRLA_ALOCK_Msk = 0x800
	// Bit ALOCK.
	TC_COUNT32_CTRLA_ALOCK = 0x800
	// Position of CAPTEN0 field.
	TC_COUNT32_CTRLA_CAPTEN0_Pos = 0x10
	// Bit mask of CAPTEN0 field.
	TC_COUNT32_CTRLA_CAPTEN0_Msk = 0x10000
	// Bit CAPTEN0.
	TC_COUNT32_CTRLA_CAPTEN0 = 0x10000
	// Position of CAPTEN1 field.
	TC_COUNT32_CTRLA_CAPTEN1_Pos = 0x11
	// Bit mask of CAPTEN1 field.
	TC_COUNT32_CTRLA_CAPTEN1_Msk = 0x20000
	// Bit CAPTEN1.
	TC_COUNT32_CTRLA_CAPTEN1 = 0x20000
	// Position of COPEN0 field.
	TC_COUNT32_CTRLA_COPEN0_Pos = 0x14
	// Bit mask of COPEN0 field.
	TC_COUNT32_CTRLA_COPEN0_Msk = 0x100000
	// Bit COPEN0.
	TC_COUNT32_CTRLA_COPEN0 = 0x100000
	// Position of COPEN1 field.
	TC_COUNT32_CTRLA_COPEN1_Pos = 0x15
	// Bit mask of COPEN1 field.
	TC_COUNT32_CTRLA_COPEN1_Msk = 0x200000
	// Bit COPEN1.
	TC_COUNT32_CTRLA_COPEN1 = 0x200000
	// Position of CAPTMODE0 field.
	TC_COUNT32_CTRLA_CAPTMODE0_Pos = 0x18
	// Bit mask of CAPTMODE0 field.
	TC_COUNT32_CTRLA_CAPTMODE0_Msk = 0x3000000
	// Default capture
	TC_COUNT32_CTRLA_CAPTMODE0_DEFAULT = 0x0
	// Minimum capture
	TC_COUNT32_CTRLA_CAPTMODE0_CAPTMIN = 0x1
	// Maximum capture
	TC_COUNT32_CTRLA_CAPTMODE0_CAPTMAX = 0x2
	// Position of CAPTMODE1 field.
	TC_COUNT32_CTRLA_CAPTMODE1_Pos = 0x1b
	// Bit mask of CAPTMODE1 field.
	TC_COUNT32_CTRLA_CAPTMODE1_Msk = 0x18000000
	// Default capture
	TC_COUNT32_CTRLA_CAPTMODE1_DEFAULT = 0x0
	// Minimum capture
	TC_COUNT32_CTRLA_CAPTMODE1_CAPTMIN = 0x1
	// Maximum capture
	TC_COUNT32_CTRLA_CAPTMODE1_CAPTMAX = 0x2

	// CTRLBCLR: Control B Clear
	// Position of DIR field.
	TC_COUNT32_CTRLBCLR_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TC_COUNT32_CTRLBCLR_DIR_Msk = 0x1
	// Bit DIR.
	TC_COUNT32_CTRLBCLR_DIR = 0x1
	// Position of LUPD field.
	TC_COUNT32_CTRLBCLR_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TC_COUNT32_CTRLBCLR_LUPD_Msk = 0x2
	// Bit LUPD.
	TC_COUNT32_CTRLBCLR_LUPD = 0x2
	// Position of ONESHOT field.
	TC_COUNT32_CTRLBCLR_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TC_COUNT32_CTRLBCLR_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TC_COUNT32_CTRLBCLR_ONESHOT = 0x4
	// Position of CMD field.
	TC_COUNT32_CTRLBCLR_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TC_COUNT32_CTRLBCLR_CMD_Msk = 0xe0
	// No action
	TC_COUNT32_CTRLBCLR_CMD_NONE = 0x0
	// Force a start, restart or retrigger
	TC_COUNT32_CTRLBCLR_CMD_RETRIGGER = 0x1
	// Force a stop
	TC_COUNT32_CTRLBCLR_CMD_STOP = 0x2
	// Force update of double-buffered register
	TC_COUNT32_CTRLBCLR_CMD_UPDATE = 0x3
	// Force a read synchronization of COUNT
	TC_COUNT32_CTRLBCLR_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TC_COUNT32_CTRLBCLR_CMD_DMAOS = 0x5

	// CTRLBSET: Control B Set
	// Position of DIR field.
	TC_COUNT32_CTRLBSET_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TC_COUNT32_CTRLBSET_DIR_Msk = 0x1
	// Bit DIR.
	TC_COUNT32_CTRLBSET_DIR = 0x1
	// Position of LUPD field.
	TC_COUNT32_CTRLBSET_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TC_COUNT32_CTRLBSET_LUPD_Msk = 0x2
	// Bit LUPD.
	TC_COUNT32_CTRLBSET_LUPD = 0x2
	// Position of ONESHOT field.
	TC_COUNT32_CTRLBSET_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TC_COUNT32_CTRLBSET_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TC_COUNT32_CTRLBSET_ONESHOT = 0x4
	// Position of CMD field.
	TC_COUNT32_CTRLBSET_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TC_COUNT32_CTRLBSET_CMD_Msk = 0xe0
	// No action
	TC_COUNT32_CTRLBSET_CMD_NONE = 0x0
	// Force a start, restart or retrigger
	TC_COUNT32_CTRLBSET_CMD_RETRIGGER = 0x1
	// Force a stop
	TC_COUNT32_CTRLBSET_CMD_STOP = 0x2
	// Force update of double-buffered register
	TC_COUNT32_CTRLBSET_CMD_UPDATE = 0x3
	// Force a read synchronization of COUNT
	TC_COUNT32_CTRLBSET_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TC_COUNT32_CTRLBSET_CMD_DMAOS = 0x5

	// EVCTRL: Event Control
	// Position of EVACT field.
	TC_COUNT32_EVCTRL_EVACT_Pos = 0x0
	// Bit mask of EVACT field.
	TC_COUNT32_EVCTRL_EVACT_Msk = 0x7
	// Event action disabled
	TC_COUNT32_EVCTRL_EVACT_OFF = 0x0
	// Start, restart or retrigger TC on event
	TC_COUNT32_EVCTRL_EVACT_RETRIGGER = 0x1
	// Count on event
	TC_COUNT32_EVCTRL_EVACT_COUNT = 0x2
	// Start TC on event
	TC_COUNT32_EVCTRL_EVACT_START = 0x3
	// Time stamp capture
	TC_COUNT32_EVCTRL_EVACT_STAMP = 0x4
	// Period catured in CC0, pulse width in CC1
	TC_COUNT32_EVCTRL_EVACT_PPW = 0x5
	// Period catured in CC1, pulse width in CC0
	TC_COUNT32_EVCTRL_EVACT_PWP = 0x6
	// Pulse width capture
	TC_COUNT32_EVCTRL_EVACT_PW = 0x7
	// Position of TCINV field.
	TC_COUNT32_EVCTRL_TCINV_Pos = 0x4
	// Bit mask of TCINV field.
	TC_COUNT32_EVCTRL_TCINV_Msk = 0x10
	// Bit TCINV.
	TC_COUNT32_EVCTRL_TCINV = 0x10
	// Position of TCEI field.
	TC_COUNT32_EVCTRL_TCEI_Pos = 0x5
	// Bit mask of TCEI field.
	TC_COUNT32_EVCTRL_TCEI_Msk = 0x20
	// Bit TCEI.
	TC_COUNT32_EVCTRL_TCEI = 0x20
	// Position of OVFEO field.
	TC_COUNT32_EVCTRL_OVFEO_Pos = 0x8
	// Bit mask of OVFEO field.
	TC_COUNT32_EVCTRL_OVFEO_Msk = 0x100
	// Bit OVFEO.
	TC_COUNT32_EVCTRL_OVFEO = 0x100
	// Position of MCEO0 field.
	TC_COUNT32_EVCTRL_MCEO0_Pos = 0xc
	// Bit mask of MCEO0 field.
	TC_COUNT32_EVCTRL_MCEO0_Msk = 0x1000
	// Bit MCEO0.
	TC_COUNT32_EVCTRL_MCEO0 = 0x1000
	// Position of MCEO1 field.
	TC_COUNT32_EVCTRL_MCEO1_Pos = 0xd
	// Bit mask of MCEO1 field.
	TC_COUNT32_EVCTRL_MCEO1_Msk = 0x2000
	// Bit MCEO1.
	TC_COUNT32_EVCTRL_MCEO1 = 0x2000

	// INTENCLR: Interrupt Enable Clear
	// Position of OVF field.
	TC_COUNT32_INTENCLR_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT32_INTENCLR_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT32_INTENCLR_OVF = 0x1
	// Position of ERR field.
	TC_COUNT32_INTENCLR_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT32_INTENCLR_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT32_INTENCLR_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT32_INTENCLR_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT32_INTENCLR_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT32_INTENCLR_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT32_INTENCLR_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT32_INTENCLR_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT32_INTENCLR_MC1 = 0x20

	// INTENSET: Interrupt Enable Set
	// Position of OVF field.
	TC_COUNT32_INTENSET_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT32_INTENSET_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT32_INTENSET_OVF = 0x1
	// Position of ERR field.
	TC_COUNT32_INTENSET_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT32_INTENSET_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT32_INTENSET_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT32_INTENSET_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT32_INTENSET_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT32_INTENSET_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT32_INTENSET_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT32_INTENSET_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT32_INTENSET_MC1 = 0x20

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of OVF field.
	TC_COUNT32_INTFLAG_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TC_COUNT32_INTFLAG_OVF_Msk = 0x1
	// Bit OVF.
	TC_COUNT32_INTFLAG_OVF = 0x1
	// Position of ERR field.
	TC_COUNT32_INTFLAG_ERR_Pos = 0x1
	// Bit mask of ERR field.
	TC_COUNT32_INTFLAG_ERR_Msk = 0x2
	// Bit ERR.
	TC_COUNT32_INTFLAG_ERR = 0x2
	// Position of MC0 field.
	TC_COUNT32_INTFLAG_MC0_Pos = 0x4
	// Bit mask of MC0 field.
	TC_COUNT32_INTFLAG_MC0_Msk = 0x10
	// Bit MC0.
	TC_COUNT32_INTFLAG_MC0 = 0x10
	// Position of MC1 field.
	TC_COUNT32_INTFLAG_MC1_Pos = 0x5
	// Bit mask of MC1 field.
	TC_COUNT32_INTFLAG_MC1_Msk = 0x20
	// Bit MC1.
	TC_COUNT32_INTFLAG_MC1 = 0x20

	// STATUS: Status
	// Position of STOP field.
	TC_COUNT32_STATUS_STOP_Pos = 0x0
	// Bit mask of STOP field.
	TC_COUNT32_STATUS_STOP_Msk = 0x1
	// Bit STOP.
	TC_COUNT32_STATUS_STOP = 0x1
	// Position of SLAVE field.
	TC_COUNT32_STATUS_SLAVE_Pos = 0x1
	// Bit mask of SLAVE field.
	TC_COUNT32_STATUS_SLAVE_Msk = 0x2
	// Bit SLAVE.
	TC_COUNT32_STATUS_SLAVE = 0x2
	// Position of PERBUFV field.
	TC_COUNT32_STATUS_PERBUFV_Pos = 0x3
	// Bit mask of PERBUFV field.
	TC_COUNT32_STATUS_PERBUFV_Msk = 0x8
	// Bit PERBUFV.
	TC_COUNT32_STATUS_PERBUFV = 0x8
	// Position of CCBUFV0 field.
	TC_COUNT32_STATUS_CCBUFV0_Pos = 0x4
	// Bit mask of CCBUFV0 field.
	TC_COUNT32_STATUS_CCBUFV0_Msk = 0x10
	// Bit CCBUFV0.
	TC_COUNT32_STATUS_CCBUFV0 = 0x10
	// Position of CCBUFV1 field.
	TC_COUNT32_STATUS_CCBUFV1_Pos = 0x5
	// Bit mask of CCBUFV1 field.
	TC_COUNT32_STATUS_CCBUFV1_Msk = 0x20
	// Bit CCBUFV1.
	TC_COUNT32_STATUS_CCBUFV1 = 0x20

	// WAVE: Waveform Generation Control
	// Position of WAVEGEN field.
	TC_COUNT32_WAVE_WAVEGEN_Pos = 0x0
	// Bit mask of WAVEGEN field.
	TC_COUNT32_WAVE_WAVEGEN_Msk = 0x3
	// Normal frequency
	TC_COUNT32_WAVE_WAVEGEN_NFRQ = 0x0
	// Match frequency
	TC_COUNT32_WAVE_WAVEGEN_MFRQ = 0x1
	// Normal PWM
	TC_COUNT32_WAVE_WAVEGEN_NPWM = 0x2
	// Match PWM
	TC_COUNT32_WAVE_WAVEGEN_MPWM = 0x3

	// DRVCTRL: Control C
	// Position of INVEN0 field.
	TC_COUNT32_DRVCTRL_INVEN0_Pos = 0x0
	// Bit mask of INVEN0 field.
	TC_COUNT32_DRVCTRL_INVEN0_Msk = 0x1
	// Bit INVEN0.
	TC_COUNT32_DRVCTRL_INVEN0 = 0x1
	// Position of INVEN1 field.
	TC_COUNT32_DRVCTRL_INVEN1_Pos = 0x1
	// Bit mask of INVEN1 field.
	TC_COUNT32_DRVCTRL_INVEN1_Msk = 0x2
	// Bit INVEN1.
	TC_COUNT32_DRVCTRL_INVEN1 = 0x2

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	TC_COUNT32_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	TC_COUNT32_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	TC_COUNT32_DBGCTRL_DBGRUN = 0x1

	// SYNCBUSY: Synchronization Status
	// Position of SWRST field.
	TC_COUNT32_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TC_COUNT32_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	TC_COUNT32_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	TC_COUNT32_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TC_COUNT32_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TC_COUNT32_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	TC_COUNT32_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	TC_COUNT32_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	TC_COUNT32_SYNCBUSY_CTRLB = 0x4
	// Position of STATUS field.
	TC_COUNT32_SYNCBUSY_STATUS_Pos = 0x3
	// Bit mask of STATUS field.
	TC_COUNT32_SYNCBUSY_STATUS_Msk = 0x8
	// Bit STATUS.
	TC_COUNT32_SYNCBUSY_STATUS = 0x8
	// Position of COUNT field.
	TC_COUNT32_SYNCBUSY_COUNT_Pos = 0x4
	// Bit mask of COUNT field.
	TC_COUNT32_SYNCBUSY_COUNT_Msk = 0x10
	// Bit COUNT.
	TC_COUNT32_SYNCBUSY_COUNT = 0x10
	// Position of PER field.
	TC_COUNT32_SYNCBUSY_PER_Pos = 0x5
	// Bit mask of PER field.
	TC_COUNT32_SYNCBUSY_PER_Msk = 0x20
	// Bit PER.
	TC_COUNT32_SYNCBUSY_PER = 0x20
	// Position of CC0 field.
	TC_COUNT32_SYNCBUSY_CC0_Pos = 0x6
	// Bit mask of CC0 field.
	TC_COUNT32_SYNCBUSY_CC0_Msk = 0x40
	// Bit CC0.
	TC_COUNT32_SYNCBUSY_CC0 = 0x40
	// Position of CC1 field.
	TC_COUNT32_SYNCBUSY_CC1_Pos = 0x7
	// Bit mask of CC1 field.
	TC_COUNT32_SYNCBUSY_CC1_Msk = 0x80
	// Bit CC1.
	TC_COUNT32_SYNCBUSY_CC1 = 0x80

	// COUNT: COUNT32 Count
	// Position of COUNT field.
	TC_COUNT32_COUNT_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	TC_COUNT32_COUNT_COUNT_Msk = 0xffffffff

	// CC: COUNT32 Compare and Capture
	// Position of CC field.
	TC_COUNT32_CC_CC_Pos = 0x0
	// Bit mask of CC field.
	TC_COUNT32_CC_CC_Msk = 0xffffffff

	// CCBUF: COUNT32 Compare and Capture Buffer
	// Position of CCBUF field.
	TC_COUNT32_CCBUF_CCBUF_Pos = 0x0
	// Bit mask of CCBUF field.
	TC_COUNT32_CCBUF_CCBUF_Msk = 0xffffffff
)

// Bitfields for TCC0: Timer Counter Control
const (
	// CTRLA: Control A
	// Position of SWRST field.
	TCC_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TCC_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	TCC_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	TCC_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TCC_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TCC_CTRLA_ENABLE = 0x2
	// Position of RESOLUTION field.
	TCC_CTRLA_RESOLUTION_Pos = 0x5
	// Bit mask of RESOLUTION field.
	TCC_CTRLA_RESOLUTION_Msk = 0x60
	// Dithering is disabled
	TCC_CTRLA_RESOLUTION_NONE = 0x0
	// Dithering is done every 16 PWM frames
	TCC_CTRLA_RESOLUTION_DITH4 = 0x1
	// Dithering is done every 32 PWM frames
	TCC_CTRLA_RESOLUTION_DITH5 = 0x2
	// Dithering is done every 64 PWM frames
	TCC_CTRLA_RESOLUTION_DITH6 = 0x3
	// Position of PRESCALER field.
	TCC_CTRLA_PRESCALER_Pos = 0x8
	// Bit mask of PRESCALER field.
	TCC_CTRLA_PRESCALER_Msk = 0x700
	// No division
	TCC_CTRLA_PRESCALER_DIV1 = 0x0
	// Divide by 2
	TCC_CTRLA_PRESCALER_DIV2 = 0x1
	// Divide by 4
	TCC_CTRLA_PRESCALER_DIV4 = 0x2
	// Divide by 8
	TCC_CTRLA_PRESCALER_DIV8 = 0x3
	// Divide by 16
	TCC_CTRLA_PRESCALER_DIV16 = 0x4
	// Divide by 64
	TCC_CTRLA_PRESCALER_DIV64 = 0x5
	// Divide by 256
	TCC_CTRLA_PRESCALER_DIV256 = 0x6
	// Divide by 1024
	TCC_CTRLA_PRESCALER_DIV1024 = 0x7
	// Position of RUNSTDBY field.
	TCC_CTRLA_RUNSTDBY_Pos = 0xb
	// Bit mask of RUNSTDBY field.
	TCC_CTRLA_RUNSTDBY_Msk = 0x800
	// Bit RUNSTDBY.
	TCC_CTRLA_RUNSTDBY = 0x800
	// Position of PRESCSYNC field.
	TCC_CTRLA_PRESCSYNC_Pos = 0xc
	// Bit mask of PRESCSYNC field.
	TCC_CTRLA_PRESCSYNC_Msk = 0x3000
	// Reload or reset counter on next GCLK
	TCC_CTRLA_PRESCSYNC_GCLK = 0x0
	// Reload or reset counter on next prescaler clock
	TCC_CTRLA_PRESCSYNC_PRESC = 0x1
	// Reload or reset counter on next GCLK and reset prescaler counter
	TCC_CTRLA_PRESCSYNC_RESYNC = 0x2
	// Position of ALOCK field.
	TCC_CTRLA_ALOCK_Pos = 0xe
	// Bit mask of ALOCK field.
	TCC_CTRLA_ALOCK_Msk = 0x4000
	// Bit ALOCK.
	TCC_CTRLA_ALOCK = 0x4000
	// Position of MSYNC field.
	TCC_CTRLA_MSYNC_Pos = 0xf
	// Bit mask of MSYNC field.
	TCC_CTRLA_MSYNC_Msk = 0x8000
	// Bit MSYNC.
	TCC_CTRLA_MSYNC = 0x8000
	// Position of DMAOS field.
	TCC_CTRLA_DMAOS_Pos = 0x17
	// Bit mask of DMAOS field.
	TCC_CTRLA_DMAOS_Msk = 0x800000
	// Bit DMAOS.
	TCC_CTRLA_DMAOS = 0x800000
	// Position of CPTEN0 field.
	TCC_CTRLA_CPTEN0_Pos = 0x18
	// Bit mask of CPTEN0 field.
	TCC_CTRLA_CPTEN0_Msk = 0x1000000
	// Bit CPTEN0.
	TCC_CTRLA_CPTEN0 = 0x1000000
	// Position of CPTEN1 field.
	TCC_CTRLA_CPTEN1_Pos = 0x19
	// Bit mask of CPTEN1 field.
	TCC_CTRLA_CPTEN1_Msk = 0x2000000
	// Bit CPTEN1.
	TCC_CTRLA_CPTEN1 = 0x2000000
	// Position of CPTEN2 field.
	TCC_CTRLA_CPTEN2_Pos = 0x1a
	// Bit mask of CPTEN2 field.
	TCC_CTRLA_CPTEN2_Msk = 0x4000000
	// Bit CPTEN2.
	TCC_CTRLA_CPTEN2 = 0x4000000
	// Position of CPTEN3 field.
	TCC_CTRLA_CPTEN3_Pos = 0x1b
	// Bit mask of CPTEN3 field.
	TCC_CTRLA_CPTEN3_Msk = 0x8000000
	// Bit CPTEN3.
	TCC_CTRLA_CPTEN3 = 0x8000000
	// Position of CPTEN4 field.
	TCC_CTRLA_CPTEN4_Pos = 0x1c
	// Bit mask of CPTEN4 field.
	TCC_CTRLA_CPTEN4_Msk = 0x10000000
	// Bit CPTEN4.
	TCC_CTRLA_CPTEN4 = 0x10000000
	// Position of CPTEN5 field.
	TCC_CTRLA_CPTEN5_Pos = 0x1d
	// Bit mask of CPTEN5 field.
	TCC_CTRLA_CPTEN5_Msk = 0x20000000
	// Bit CPTEN5.
	TCC_CTRLA_CPTEN5 = 0x20000000

	// CTRLBCLR: Control B Clear
	// Position of DIR field.
	TCC_CTRLBCLR_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TCC_CTRLBCLR_DIR_Msk = 0x1
	// Bit DIR.
	TCC_CTRLBCLR_DIR = 0x1
	// Position of LUPD field.
	TCC_CTRLBCLR_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TCC_CTRLBCLR_LUPD_Msk = 0x2
	// Bit LUPD.
	TCC_CTRLBCLR_LUPD = 0x2
	// Position of ONESHOT field.
	TCC_CTRLBCLR_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TCC_CTRLBCLR_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TCC_CTRLBCLR_ONESHOT = 0x4
	// Position of IDXCMD field.
	TCC_CTRLBCLR_IDXCMD_Pos = 0x3
	// Bit mask of IDXCMD field.
	TCC_CTRLBCLR_IDXCMD_Msk = 0x18
	// Command disabled: Index toggles between cycles A and B
	TCC_CTRLBCLR_IDXCMD_DISABLE = 0x0
	// Set index: cycle B will be forced in the next cycle
	TCC_CTRLBCLR_IDXCMD_SET = 0x1
	// Clear index: cycle A will be forced in the next cycle
	TCC_CTRLBCLR_IDXCMD_CLEAR = 0x2
	// Hold index: the next cycle will be the same as the current cycle
	TCC_CTRLBCLR_IDXCMD_HOLD = 0x3
	// Position of CMD field.
	TCC_CTRLBCLR_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TCC_CTRLBCLR_CMD_Msk = 0xe0
	// No action
	TCC_CTRLBCLR_CMD_NONE = 0x0
	// Clear start, restart or retrigger
	TCC_CTRLBCLR_CMD_RETRIGGER = 0x1
	// Force stop
	TCC_CTRLBCLR_CMD_STOP = 0x2
	// Force update or double buffered registers
	TCC_CTRLBCLR_CMD_UPDATE = 0x3
	// Force COUNT read synchronization
	TCC_CTRLBCLR_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TCC_CTRLBCLR_CMD_DMAOS = 0x5

	// CTRLBSET: Control B Set
	// Position of DIR field.
	TCC_CTRLBSET_DIR_Pos = 0x0
	// Bit mask of DIR field.
	TCC_CTRLBSET_DIR_Msk = 0x1
	// Bit DIR.
	TCC_CTRLBSET_DIR = 0x1
	// Position of LUPD field.
	TCC_CTRLBSET_LUPD_Pos = 0x1
	// Bit mask of LUPD field.
	TCC_CTRLBSET_LUPD_Msk = 0x2
	// Bit LUPD.
	TCC_CTRLBSET_LUPD = 0x2
	// Position of ONESHOT field.
	TCC_CTRLBSET_ONESHOT_Pos = 0x2
	// Bit mask of ONESHOT field.
	TCC_CTRLBSET_ONESHOT_Msk = 0x4
	// Bit ONESHOT.
	TCC_CTRLBSET_ONESHOT = 0x4
	// Position of IDXCMD field.
	TCC_CTRLBSET_IDXCMD_Pos = 0x3
	// Bit mask of IDXCMD field.
	TCC_CTRLBSET_IDXCMD_Msk = 0x18
	// Command disabled: Index toggles between cycles A and B
	TCC_CTRLBSET_IDXCMD_DISABLE = 0x0
	// Set index: cycle B will be forced in the next cycle
	TCC_CTRLBSET_IDXCMD_SET = 0x1
	// Clear index: cycle A will be forced in the next cycle
	TCC_CTRLBSET_IDXCMD_CLEAR = 0x2
	// Hold index: the next cycle will be the same as the current cycle
	TCC_CTRLBSET_IDXCMD_HOLD = 0x3
	// Position of CMD field.
	TCC_CTRLBSET_CMD_Pos = 0x5
	// Bit mask of CMD field.
	TCC_CTRLBSET_CMD_Msk = 0xe0
	// No action
	TCC_CTRLBSET_CMD_NONE = 0x0
	// Clear start, restart or retrigger
	TCC_CTRLBSET_CMD_RETRIGGER = 0x1
	// Force stop
	TCC_CTRLBSET_CMD_STOP = 0x2
	// Force update or double buffered registers
	TCC_CTRLBSET_CMD_UPDATE = 0x3
	// Force COUNT read synchronization
	TCC_CTRLBSET_CMD_READSYNC = 0x4
	// One-shot DMA trigger
	TCC_CTRLBSET_CMD_DMAOS = 0x5

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	TCC_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	TCC_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	TCC_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	TCC_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TCC_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TCC_SYNCBUSY_ENABLE = 0x2
	// Position of CTRLB field.
	TCC_SYNCBUSY_CTRLB_Pos = 0x2
	// Bit mask of CTRLB field.
	TCC_SYNCBUSY_CTRLB_Msk = 0x4
	// Bit CTRLB.
	TCC_SYNCBUSY_CTRLB = 0x4
	// Position of STATUS field.
	TCC_SYNCBUSY_STATUS_Pos = 0x3
	// Bit mask of STATUS field.
	TCC_SYNCBUSY_STATUS_Msk = 0x8
	// Bit STATUS.
	TCC_SYNCBUSY_STATUS = 0x8
	// Position of COUNT field.
	TCC_SYNCBUSY_COUNT_Pos = 0x4
	// Bit mask of COUNT field.
	TCC_SYNCBUSY_COUNT_Msk = 0x10
	// Bit COUNT.
	TCC_SYNCBUSY_COUNT = 0x10
	// Position of PATT field.
	TCC_SYNCBUSY_PATT_Pos = 0x5
	// Bit mask of PATT field.
	TCC_SYNCBUSY_PATT_Msk = 0x20
	// Bit PATT.
	TCC_SYNCBUSY_PATT = 0x20
	// Position of WAVE field.
	TCC_SYNCBUSY_WAVE_Pos = 0x6
	// Bit mask of WAVE field.
	TCC_SYNCBUSY_WAVE_Msk = 0x40
	// Bit WAVE.
	TCC_SYNCBUSY_WAVE = 0x40
	// Position of PER field.
	TCC_SYNCBUSY_PER_Pos = 0x7
	// Bit mask of PER field.
	TCC_SYNCBUSY_PER_Msk = 0x80
	// Bit PER.
	TCC_SYNCBUSY_PER = 0x80
	// Position of CC0 field.
	TCC_SYNCBUSY_CC0_Pos = 0x8
	// Bit mask of CC0 field.
	TCC_SYNCBUSY_CC0_Msk = 0x100
	// Bit CC0.
	TCC_SYNCBUSY_CC0 = 0x100
	// Position of CC1 field.
	TCC_SYNCBUSY_CC1_Pos = 0x9
	// Bit mask of CC1 field.
	TCC_SYNCBUSY_CC1_Msk = 0x200
	// Bit CC1.
	TCC_SYNCBUSY_CC1 = 0x200
	// Position of CC2 field.
	TCC_SYNCBUSY_CC2_Pos = 0xa
	// Bit mask of CC2 field.
	TCC_SYNCBUSY_CC2_Msk = 0x400
	// Bit CC2.
	TCC_SYNCBUSY_CC2 = 0x400
	// Position of CC3 field.
	TCC_SYNCBUSY_CC3_Pos = 0xb
	// Bit mask of CC3 field.
	TCC_SYNCBUSY_CC3_Msk = 0x800
	// Bit CC3.
	TCC_SYNCBUSY_CC3 = 0x800
	// Position of CC4 field.
	TCC_SYNCBUSY_CC4_Pos = 0xc
	// Bit mask of CC4 field.
	TCC_SYNCBUSY_CC4_Msk = 0x1000
	// Bit CC4.
	TCC_SYNCBUSY_CC4 = 0x1000
	// Position of CC5 field.
	TCC_SYNCBUSY_CC5_Pos = 0xd
	// Bit mask of CC5 field.
	TCC_SYNCBUSY_CC5_Msk = 0x2000
	// Bit CC5.
	TCC_SYNCBUSY_CC5 = 0x2000

	// FCTRLA: Recoverable Fault A Configuration
	// Position of SRC field.
	TCC_FCTRLA_SRC_Pos = 0x0
	// Bit mask of SRC field.
	TCC_FCTRLA_SRC_Msk = 0x3
	// Fault input disabled
	TCC_FCTRLA_SRC_DISABLE = 0x0
	// MCEx (x=0,1) event input
	TCC_FCTRLA_SRC_ENABLE = 0x1
	// Inverted MCEx (x=0,1) event input
	TCC_FCTRLA_SRC_INVERT = 0x2
	// Alternate fault (A or B) state at the end of the previous period
	TCC_FCTRLA_SRC_ALTFAULT = 0x3
	// Position of KEEP field.
	TCC_FCTRLA_KEEP_Pos = 0x3
	// Bit mask of KEEP field.
	TCC_FCTRLA_KEEP_Msk = 0x8
	// Bit KEEP.
	TCC_FCTRLA_KEEP = 0x8
	// Position of QUAL field.
	TCC_FCTRLA_QUAL_Pos = 0x4
	// Bit mask of QUAL field.
	TCC_FCTRLA_QUAL_Msk = 0x10
	// Bit QUAL.
	TCC_FCTRLA_QUAL = 0x10
	// Position of BLANK field.
	TCC_FCTRLA_BLANK_Pos = 0x5
	// Bit mask of BLANK field.
	TCC_FCTRLA_BLANK_Msk = 0x60
	// Blanking applied from start of the ramp
	TCC_FCTRLA_BLANK_START = 0x0
	// Blanking applied from rising edge of the output waveform
	TCC_FCTRLA_BLANK_RISE = 0x1
	// Blanking applied from falling edge of the output waveform
	TCC_FCTRLA_BLANK_FALL = 0x2
	// Blanking applied from each toggle of the output waveform
	TCC_FCTRLA_BLANK_BOTH = 0x3
	// Position of RESTART field.
	TCC_FCTRLA_RESTART_Pos = 0x7
	// Bit mask of RESTART field.
	TCC_FCTRLA_RESTART_Msk = 0x80
	// Bit RESTART.
	TCC_FCTRLA_RESTART = 0x80
	// Position of HALT field.
	TCC_FCTRLA_HALT_Pos = 0x8
	// Bit mask of HALT field.
	TCC_FCTRLA_HALT_Msk = 0x300
	// Halt action disabled
	TCC_FCTRLA_HALT_DISABLE = 0x0
	// Hardware halt action
	TCC_FCTRLA_HALT_HW = 0x1
	// Software halt action
	TCC_FCTRLA_HALT_SW = 0x2
	// Non-recoverable fault
	TCC_FCTRLA_HALT_NR = 0x3
	// Position of CHSEL field.
	TCC_FCTRLA_CHSEL_Pos = 0xa
	// Bit mask of CHSEL field.
	TCC_FCTRLA_CHSEL_Msk = 0xc00
	// Capture value stored in channel 0
	TCC_FCTRLA_CHSEL_CC0 = 0x0
	// Capture value stored in channel 1
	TCC_FCTRLA_CHSEL_CC1 = 0x1
	// Capture value stored in channel 2
	TCC_FCTRLA_CHSEL_CC2 = 0x2
	// Capture value stored in channel 3
	TCC_FCTRLA_CHSEL_CC3 = 0x3
	// Position of CAPTURE field.
	TCC_FCTRLA_CAPTURE_Pos = 0xc
	// Bit mask of CAPTURE field.
	TCC_FCTRLA_CAPTURE_Msk = 0x7000
	// No capture
	TCC_FCTRLA_CAPTURE_DISABLE = 0x0
	// Capture on fault
	TCC_FCTRLA_CAPTURE_CAPT = 0x1
	// Minimum capture
	TCC_FCTRLA_CAPTURE_CAPTMIN = 0x2
	// Maximum capture
	TCC_FCTRLA_CAPTURE_CAPTMAX = 0x3
	// Minimum local detection
	TCC_FCTRLA_CAPTURE_LOCMIN = 0x4
	// Maximum local detection
	TCC_FCTRLA_CAPTURE_LOCMAX = 0x5
	// Minimum and maximum local detection
	TCC_FCTRLA_CAPTURE_DERIV0 = 0x6
	// Capture with ramp index as MSB value
	TCC_FCTRLA_CAPTURE_CAPTMARK = 0x7
	// Position of BLANKPRESC field.
	TCC_FCTRLA_BLANKPRESC_Pos = 0xf
	// Bit mask of BLANKPRESC field.
	TCC_FCTRLA_BLANKPRESC_Msk = 0x8000
	// Bit BLANKPRESC.
	TCC_FCTRLA_BLANKPRESC = 0x8000
	// Position of BLANKVAL field.
	TCC_FCTRLA_BLANKVAL_Pos = 0x10
	// Bit mask of BLANKVAL field.
	TCC_FCTRLA_BLANKVAL_Msk = 0xff0000
	// Position of FILTERVAL field.
	TCC_FCTRLA_FILTERVAL_Pos = 0x18
	// Bit mask of FILTERVAL field.
	TCC_FCTRLA_FILTERVAL_Msk = 0xf000000

	// FCTRLB: Recoverable Fault B Configuration
	// Position of SRC field.
	TCC_FCTRLB_SRC_Pos = 0x0
	// Bit mask of SRC field.
	TCC_FCTRLB_SRC_Msk = 0x3
	// Fault input disabled
	TCC_FCTRLB_SRC_DISABLE = 0x0
	// MCEx (x=0,1) event input
	TCC_FCTRLB_SRC_ENABLE = 0x1
	// Inverted MCEx (x=0,1) event input
	TCC_FCTRLB_SRC_INVERT = 0x2
	// Alternate fault (A or B) state at the end of the previous period
	TCC_FCTRLB_SRC_ALTFAULT = 0x3
	// Position of KEEP field.
	TCC_FCTRLB_KEEP_Pos = 0x3
	// Bit mask of KEEP field.
	TCC_FCTRLB_KEEP_Msk = 0x8
	// Bit KEEP.
	TCC_FCTRLB_KEEP = 0x8
	// Position of QUAL field.
	TCC_FCTRLB_QUAL_Pos = 0x4
	// Bit mask of QUAL field.
	TCC_FCTRLB_QUAL_Msk = 0x10
	// Bit QUAL.
	TCC_FCTRLB_QUAL = 0x10
	// Position of BLANK field.
	TCC_FCTRLB_BLANK_Pos = 0x5
	// Bit mask of BLANK field.
	TCC_FCTRLB_BLANK_Msk = 0x60
	// Blanking applied from start of the ramp
	TCC_FCTRLB_BLANK_START = 0x0
	// Blanking applied from rising edge of the output waveform
	TCC_FCTRLB_BLANK_RISE = 0x1
	// Blanking applied from falling edge of the output waveform
	TCC_FCTRLB_BLANK_FALL = 0x2
	// Blanking applied from each toggle of the output waveform
	TCC_FCTRLB_BLANK_BOTH = 0x3
	// Position of RESTART field.
	TCC_FCTRLB_RESTART_Pos = 0x7
	// Bit mask of RESTART field.
	TCC_FCTRLB_RESTART_Msk = 0x80
	// Bit RESTART.
	TCC_FCTRLB_RESTART = 0x80
	// Position of HALT field.
	TCC_FCTRLB_HALT_Pos = 0x8
	// Bit mask of HALT field.
	TCC_FCTRLB_HALT_Msk = 0x300
	// Halt action disabled
	TCC_FCTRLB_HALT_DISABLE = 0x0
	// Hardware halt action
	TCC_FCTRLB_HALT_HW = 0x1
	// Software halt action
	TCC_FCTRLB_HALT_SW = 0x2
	// Non-recoverable fault
	TCC_FCTRLB_HALT_NR = 0x3
	// Position of CHSEL field.
	TCC_FCTRLB_CHSEL_Pos = 0xa
	// Bit mask of CHSEL field.
	TCC_FCTRLB_CHSEL_Msk = 0xc00
	// Capture value stored in channel 0
	TCC_FCTRLB_CHSEL_CC0 = 0x0
	// Capture value stored in channel 1
	TCC_FCTRLB_CHSEL_CC1 = 0x1
	// Capture value stored in channel 2
	TCC_FCTRLB_CHSEL_CC2 = 0x2
	// Capture value stored in channel 3
	TCC_FCTRLB_CHSEL_CC3 = 0x3
	// Position of CAPTURE field.
	TCC_FCTRLB_CAPTURE_Pos = 0xc
	// Bit mask of CAPTURE field.
	TCC_FCTRLB_CAPTURE_Msk = 0x7000
	// No capture
	TCC_FCTRLB_CAPTURE_DISABLE = 0x0
	// Capture on fault
	TCC_FCTRLB_CAPTURE_CAPT = 0x1
	// Minimum capture
	TCC_FCTRLB_CAPTURE_CAPTMIN = 0x2
	// Maximum capture
	TCC_FCTRLB_CAPTURE_CAPTMAX = 0x3
	// Minimum local detection
	TCC_FCTRLB_CAPTURE_LOCMIN = 0x4
	// Maximum local detection
	TCC_FCTRLB_CAPTURE_LOCMAX = 0x5
	// Minimum and maximum local detection
	TCC_FCTRLB_CAPTURE_DERIV0 = 0x6
	// Capture with ramp index as MSB value
	TCC_FCTRLB_CAPTURE_CAPTMARK = 0x7
	// Position of BLANKPRESC field.
	TCC_FCTRLB_BLANKPRESC_Pos = 0xf
	// Bit mask of BLANKPRESC field.
	TCC_FCTRLB_BLANKPRESC_Msk = 0x8000
	// Bit BLANKPRESC.
	TCC_FCTRLB_BLANKPRESC = 0x8000
	// Position of BLANKVAL field.
	TCC_FCTRLB_BLANKVAL_Pos = 0x10
	// Bit mask of BLANKVAL field.
	TCC_FCTRLB_BLANKVAL_Msk = 0xff0000
	// Position of FILTERVAL field.
	TCC_FCTRLB_FILTERVAL_Pos = 0x18
	// Bit mask of FILTERVAL field.
	TCC_FCTRLB_FILTERVAL_Msk = 0xf000000

	// WEXCTRL: Waveform Extension Configuration
	// Position of OTMX field.
	TCC_WEXCTRL_OTMX_Pos = 0x0
	// Bit mask of OTMX field.
	TCC_WEXCTRL_OTMX_Msk = 0x3
	// Position of DTIEN0 field.
	TCC_WEXCTRL_DTIEN0_Pos = 0x8
	// Bit mask of DTIEN0 field.
	TCC_WEXCTRL_DTIEN0_Msk = 0x100
	// Bit DTIEN0.
	TCC_WEXCTRL_DTIEN0 = 0x100
	// Position of DTIEN1 field.
	TCC_WEXCTRL_DTIEN1_Pos = 0x9
	// Bit mask of DTIEN1 field.
	TCC_WEXCTRL_DTIEN1_Msk = 0x200
	// Bit DTIEN1.
	TCC_WEXCTRL_DTIEN1 = 0x200
	// Position of DTIEN2 field.
	TCC_WEXCTRL_DTIEN2_Pos = 0xa
	// Bit mask of DTIEN2 field.
	TCC_WEXCTRL_DTIEN2_Msk = 0x400
	// Bit DTIEN2.
	TCC_WEXCTRL_DTIEN2 = 0x400
	// Position of DTIEN3 field.
	TCC_WEXCTRL_DTIEN3_Pos = 0xb
	// Bit mask of DTIEN3 field.
	TCC_WEXCTRL_DTIEN3_Msk = 0x800
	// Bit DTIEN3.
	TCC_WEXCTRL_DTIEN3 = 0x800
	// Position of DTLS field.
	TCC_WEXCTRL_DTLS_Pos = 0x10
	// Bit mask of DTLS field.
	TCC_WEXCTRL_DTLS_Msk = 0xff0000
	// Position of DTHS field.
	TCC_WEXCTRL_DTHS_Pos = 0x18
	// Bit mask of DTHS field.
	TCC_WEXCTRL_DTHS_Msk = 0xff000000

	// DRVCTRL: Driver Control
	// Position of NRE0 field.
	TCC_DRVCTRL_NRE0_Pos = 0x0
	// Bit mask of NRE0 field.
	TCC_DRVCTRL_NRE0_Msk = 0x1
	// Bit NRE0.
	TCC_DRVCTRL_NRE0 = 0x1
	// Position of NRE1 field.
	TCC_DRVCTRL_NRE1_Pos = 0x1
	// Bit mask of NRE1 field.
	TCC_DRVCTRL_NRE1_Msk = 0x2
	// Bit NRE1.
	TCC_DRVCTRL_NRE1 = 0x2
	// Position of NRE2 field.
	TCC_DRVCTRL_NRE2_Pos = 0x2
	// Bit mask of NRE2 field.
	TCC_DRVCTRL_NRE2_Msk = 0x4
	// Bit NRE2.
	TCC_DRVCTRL_NRE2 = 0x4
	// Position of NRE3 field.
	TCC_DRVCTRL_NRE3_Pos = 0x3
	// Bit mask of NRE3 field.
	TCC_DRVCTRL_NRE3_Msk = 0x8
	// Bit NRE3.
	TCC_DRVCTRL_NRE3 = 0x8
	// Position of NRE4 field.
	TCC_DRVCTRL_NRE4_Pos = 0x4
	// Bit mask of NRE4 field.
	TCC_DRVCTRL_NRE4_Msk = 0x10
	// Bit NRE4.
	TCC_DRVCTRL_NRE4 = 0x10
	// Position of NRE5 field.
	TCC_DRVCTRL_NRE5_Pos = 0x5
	// Bit mask of NRE5 field.
	TCC_DRVCTRL_NRE5_Msk = 0x20
	// Bit NRE5.
	TCC_DRVCTRL_NRE5 = 0x20
	// Position of NRE6 field.
	TCC_DRVCTRL_NRE6_Pos = 0x6
	// Bit mask of NRE6 field.
	TCC_DRVCTRL_NRE6_Msk = 0x40
	// Bit NRE6.
	TCC_DRVCTRL_NRE6 = 0x40
	// Position of NRE7 field.
	TCC_DRVCTRL_NRE7_Pos = 0x7
	// Bit mask of NRE7 field.
	TCC_DRVCTRL_NRE7_Msk = 0x80
	// Bit NRE7.
	TCC_DRVCTRL_NRE7 = 0x80
	// Position of NRV0 field.
	TCC_DRVCTRL_NRV0_Pos = 0x8
	// Bit mask of NRV0 field.
	TCC_DRVCTRL_NRV0_Msk = 0x100
	// Bit NRV0.
	TCC_DRVCTRL_NRV0 = 0x100
	// Position of NRV1 field.
	TCC_DRVCTRL_NRV1_Pos = 0x9
	// Bit mask of NRV1 field.
	TCC_DRVCTRL_NRV1_Msk = 0x200
	// Bit NRV1.
	TCC_DRVCTRL_NRV1 = 0x200
	// Position of NRV2 field.
	TCC_DRVCTRL_NRV2_Pos = 0xa
	// Bit mask of NRV2 field.
	TCC_DRVCTRL_NRV2_Msk = 0x400
	// Bit NRV2.
	TCC_DRVCTRL_NRV2 = 0x400
	// Position of NRV3 field.
	TCC_DRVCTRL_NRV3_Pos = 0xb
	// Bit mask of NRV3 field.
	TCC_DRVCTRL_NRV3_Msk = 0x800
	// Bit NRV3.
	TCC_DRVCTRL_NRV3 = 0x800
	// Position of NRV4 field.
	TCC_DRVCTRL_NRV4_Pos = 0xc
	// Bit mask of NRV4 field.
	TCC_DRVCTRL_NRV4_Msk = 0x1000
	// Bit NRV4.
	TCC_DRVCTRL_NRV4 = 0x1000
	// Position of NRV5 field.
	TCC_DRVCTRL_NRV5_Pos = 0xd
	// Bit mask of NRV5 field.
	TCC_DRVCTRL_NRV5_Msk = 0x2000
	// Bit NRV5.
	TCC_DRVCTRL_NRV5 = 0x2000
	// Position of NRV6 field.
	TCC_DRVCTRL_NRV6_Pos = 0xe
	// Bit mask of NRV6 field.
	TCC_DRVCTRL_NRV6_Msk = 0x4000
	// Bit NRV6.
	TCC_DRVCTRL_NRV6 = 0x4000
	// Position of NRV7 field.
	TCC_DRVCTRL_NRV7_Pos = 0xf
	// Bit mask of NRV7 field.
	TCC_DRVCTRL_NRV7_Msk = 0x8000
	// Bit NRV7.
	TCC_DRVCTRL_NRV7 = 0x8000
	// Position of INVEN0 field.
	TCC_DRVCTRL_INVEN0_Pos = 0x10
	// Bit mask of INVEN0 field.
	TCC_DRVCTRL_INVEN0_Msk = 0x10000
	// Bit INVEN0.
	TCC_DRVCTRL_INVEN0 = 0x10000
	// Position of INVEN1 field.
	TCC_DRVCTRL_INVEN1_Pos = 0x11
	// Bit mask of INVEN1 field.
	TCC_DRVCTRL_INVEN1_Msk = 0x20000
	// Bit INVEN1.
	TCC_DRVCTRL_INVEN1 = 0x20000
	// Position of INVEN2 field.
	TCC_DRVCTRL_INVEN2_Pos = 0x12
	// Bit mask of INVEN2 field.
	TCC_DRVCTRL_INVEN2_Msk = 0x40000
	// Bit INVEN2.
	TCC_DRVCTRL_INVEN2 = 0x40000
	// Position of INVEN3 field.
	TCC_DRVCTRL_INVEN3_Pos = 0x13
	// Bit mask of INVEN3 field.
	TCC_DRVCTRL_INVEN3_Msk = 0x80000
	// Bit INVEN3.
	TCC_DRVCTRL_INVEN3 = 0x80000
	// Position of INVEN4 field.
	TCC_DRVCTRL_INVEN4_Pos = 0x14
	// Bit mask of INVEN4 field.
	TCC_DRVCTRL_INVEN4_Msk = 0x100000
	// Bit INVEN4.
	TCC_DRVCTRL_INVEN4 = 0x100000
	// Position of INVEN5 field.
	TCC_DRVCTRL_INVEN5_Pos = 0x15
	// Bit mask of INVEN5 field.
	TCC_DRVCTRL_INVEN5_Msk = 0x200000
	// Bit INVEN5.
	TCC_DRVCTRL_INVEN5 = 0x200000
	// Position of INVEN6 field.
	TCC_DRVCTRL_INVEN6_Pos = 0x16
	// Bit mask of INVEN6 field.
	TCC_DRVCTRL_INVEN6_Msk = 0x400000
	// Bit INVEN6.
	TCC_DRVCTRL_INVEN6 = 0x400000
	// Position of INVEN7 field.
	TCC_DRVCTRL_INVEN7_Pos = 0x17
	// Bit mask of INVEN7 field.
	TCC_DRVCTRL_INVEN7_Msk = 0x800000
	// Bit INVEN7.
	TCC_DRVCTRL_INVEN7 = 0x800000
	// Position of FILTERVAL0 field.
	TCC_DRVCTRL_FILTERVAL0_Pos = 0x18
	// Bit mask of FILTERVAL0 field.
	TCC_DRVCTRL_FILTERVAL0_Msk = 0xf000000
	// Position of FILTERVAL1 field.
	TCC_DRVCTRL_FILTERVAL1_Pos = 0x1c
	// Bit mask of FILTERVAL1 field.
	TCC_DRVCTRL_FILTERVAL1_Msk = 0xf0000000

	// DBGCTRL: Debug Control
	// Position of DBGRUN field.
	TCC_DBGCTRL_DBGRUN_Pos = 0x0
	// Bit mask of DBGRUN field.
	TCC_DBGCTRL_DBGRUN_Msk = 0x1
	// Bit DBGRUN.
	TCC_DBGCTRL_DBGRUN = 0x1
	// Position of FDDBD field.
	TCC_DBGCTRL_FDDBD_Pos = 0x2
	// Bit mask of FDDBD field.
	TCC_DBGCTRL_FDDBD_Msk = 0x4
	// Bit FDDBD.
	TCC_DBGCTRL_FDDBD = 0x4

	// EVCTRL: Event Control
	// Position of EVACT0 field.
	TCC_EVCTRL_EVACT0_Pos = 0x0
	// Bit mask of EVACT0 field.
	TCC_EVCTRL_EVACT0_Msk = 0x7
	// Event action disabled
	TCC_EVCTRL_EVACT0_OFF = 0x0
	// Start, restart or re-trigger counter on event
	TCC_EVCTRL_EVACT0_RETRIGGER = 0x1
	// Count on event
	TCC_EVCTRL_EVACT0_COUNTEV = 0x2
	// Start counter on event
	TCC_EVCTRL_EVACT0_START = 0x3
	// Increment counter on event
	TCC_EVCTRL_EVACT0_INC = 0x4
	// Count on active state of asynchronous event
	TCC_EVCTRL_EVACT0_COUNT = 0x5
	// Stamp capture
	TCC_EVCTRL_EVACT0_STAMP = 0x6
	// Non-recoverable fault
	TCC_EVCTRL_EVACT0_FAULT = 0x7
	// Position of EVACT1 field.
	TCC_EVCTRL_EVACT1_Pos = 0x3
	// Bit mask of EVACT1 field.
	TCC_EVCTRL_EVACT1_Msk = 0x38
	// Event action disabled
	TCC_EVCTRL_EVACT1_OFF = 0x0
	// Re-trigger counter on event
	TCC_EVCTRL_EVACT1_RETRIGGER = 0x1
	// Direction control
	TCC_EVCTRL_EVACT1_DIR = 0x2
	// Stop counter on event
	TCC_EVCTRL_EVACT1_STOP = 0x3
	// Decrement counter on event
	TCC_EVCTRL_EVACT1_DEC = 0x4
	// Period capture value in CC0 register, pulse width capture value in CC1 register
	TCC_EVCTRL_EVACT1_PPW = 0x5
	// Period capture value in CC1 register, pulse width capture value in CC0 register
	TCC_EVCTRL_EVACT1_PWP = 0x6
	// Non-recoverable fault
	TCC_EVCTRL_EVACT1_FAULT = 0x7
	// Position of CNTSEL field.
	TCC_EVCTRL_CNTSEL_Pos = 0x6
	// Bit mask of CNTSEL field.
	TCC_EVCTRL_CNTSEL_Msk = 0xc0
	// An interrupt/event is generated when a new counter cycle starts
	TCC_EVCTRL_CNTSEL_START = 0x0
	// An interrupt/event is generated when a counter cycle ends
	TCC_EVCTRL_CNTSEL_END = 0x1
	// An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
	TCC_EVCTRL_CNTSEL_BETWEEN = 0x2
	// An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
	TCC_EVCTRL_CNTSEL_BOUNDARY = 0x3
	// Position of OVFEO field.
	TCC_EVCTRL_OVFEO_Pos = 0x8
	// Bit mask of OVFEO field.
	TCC_EVCTRL_OVFEO_Msk = 0x100
	// Bit OVFEO.
	TCC_EVCTRL_OVFEO = 0x100
	// Position of TRGEO field.
	TCC_EVCTRL_TRGEO_Pos = 0x9
	// Bit mask of TRGEO field.
	TCC_EVCTRL_TRGEO_Msk = 0x200
	// Bit TRGEO.
	TCC_EVCTRL_TRGEO = 0x200
	// Position of CNTEO field.
	TCC_EVCTRL_CNTEO_Pos = 0xa
	// Bit mask of CNTEO field.
	TCC_EVCTRL_CNTEO_Msk = 0x400
	// Bit CNTEO.
	TCC_EVCTRL_CNTEO = 0x400
	// Position of TCINV0 field.
	TCC_EVCTRL_TCINV0_Pos = 0xc
	// Bit mask of TCINV0 field.
	TCC_EVCTRL_TCINV0_Msk = 0x1000
	// Bit TCINV0.
	TCC_EVCTRL_TCINV0 = 0x1000
	// Position of TCINV1 field.
	TCC_EVCTRL_TCINV1_Pos = 0xd
	// Bit mask of TCINV1 field.
	TCC_EVCTRL_TCINV1_Msk = 0x2000
	// Bit TCINV1.
	TCC_EVCTRL_TCINV1 = 0x2000
	// Position of TCEI0 field.
	TCC_EVCTRL_TCEI0_Pos = 0xe
	// Bit mask of TCEI0 field.
	TCC_EVCTRL_TCEI0_Msk = 0x4000
	// Bit TCEI0.
	TCC_EVCTRL_TCEI0 = 0x4000
	// Position of TCEI1 field.
	TCC_EVCTRL_TCEI1_Pos = 0xf
	// Bit mask of TCEI1 field.
	TCC_EVCTRL_TCEI1_Msk = 0x8000
	// Bit TCEI1.
	TCC_EVCTRL_TCEI1 = 0x8000
	// Position of MCEI0 field.
	TCC_EVCTRL_MCEI0_Pos = 0x10
	// Bit mask of MCEI0 field.
	TCC_EVCTRL_MCEI0_Msk = 0x10000
	// Bit MCEI0.
	TCC_EVCTRL_MCEI0 = 0x10000
	// Position of MCEI1 field.
	TCC_EVCTRL_MCEI1_Pos = 0x11
	// Bit mask of MCEI1 field.
	TCC_EVCTRL_MCEI1_Msk = 0x20000
	// Bit MCEI1.
	TCC_EVCTRL_MCEI1 = 0x20000
	// Position of MCEI2 field.
	TCC_EVCTRL_MCEI2_Pos = 0x12
	// Bit mask of MCEI2 field.
	TCC_EVCTRL_MCEI2_Msk = 0x40000
	// Bit MCEI2.
	TCC_EVCTRL_MCEI2 = 0x40000
	// Position of MCEI3 field.
	TCC_EVCTRL_MCEI3_Pos = 0x13
	// Bit mask of MCEI3 field.
	TCC_EVCTRL_MCEI3_Msk = 0x80000
	// Bit MCEI3.
	TCC_EVCTRL_MCEI3 = 0x80000
	// Position of MCEI4 field.
	TCC_EVCTRL_MCEI4_Pos = 0x14
	// Bit mask of MCEI4 field.
	TCC_EVCTRL_MCEI4_Msk = 0x100000
	// Bit MCEI4.
	TCC_EVCTRL_MCEI4 = 0x100000
	// Position of MCEI5 field.
	TCC_EVCTRL_MCEI5_Pos = 0x15
	// Bit mask of MCEI5 field.
	TCC_EVCTRL_MCEI5_Msk = 0x200000
	// Bit MCEI5.
	TCC_EVCTRL_MCEI5 = 0x200000
	// Position of MCEO0 field.
	TCC_EVCTRL_MCEO0_Pos = 0x18
	// Bit mask of MCEO0 field.
	TCC_EVCTRL_MCEO0_Msk = 0x1000000
	// Bit MCEO0.
	TCC_EVCTRL_MCEO0 = 0x1000000
	// Position of MCEO1 field.
	TCC_EVCTRL_MCEO1_Pos = 0x19
	// Bit mask of MCEO1 field.
	TCC_EVCTRL_MCEO1_Msk = 0x2000000
	// Bit MCEO1.
	TCC_EVCTRL_MCEO1 = 0x2000000
	// Position of MCEO2 field.
	TCC_EVCTRL_MCEO2_Pos = 0x1a
	// Bit mask of MCEO2 field.
	TCC_EVCTRL_MCEO2_Msk = 0x4000000
	// Bit MCEO2.
	TCC_EVCTRL_MCEO2 = 0x4000000
	// Position of MCEO3 field.
	TCC_EVCTRL_MCEO3_Pos = 0x1b
	// Bit mask of MCEO3 field.
	TCC_EVCTRL_MCEO3_Msk = 0x8000000
	// Bit MCEO3.
	TCC_EVCTRL_MCEO3 = 0x8000000
	// Position of MCEO4 field.
	TCC_EVCTRL_MCEO4_Pos = 0x1c
	// Bit mask of MCEO4 field.
	TCC_EVCTRL_MCEO4_Msk = 0x10000000
	// Bit MCEO4.
	TCC_EVCTRL_MCEO4 = 0x10000000
	// Position of MCEO5 field.
	TCC_EVCTRL_MCEO5_Pos = 0x1d
	// Bit mask of MCEO5 field.
	TCC_EVCTRL_MCEO5_Msk = 0x20000000
	// Bit MCEO5.
	TCC_EVCTRL_MCEO5 = 0x20000000

	// INTENCLR: Interrupt Enable Clear
	// Position of OVF field.
	TCC_INTENCLR_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TCC_INTENCLR_OVF_Msk = 0x1
	// Bit OVF.
	TCC_INTENCLR_OVF = 0x1
	// Position of TRG field.
	TCC_INTENCLR_TRG_Pos = 0x1
	// Bit mask of TRG field.
	TCC_INTENCLR_TRG_Msk = 0x2
	// Bit TRG.
	TCC_INTENCLR_TRG = 0x2
	// Position of CNT field.
	TCC_INTENCLR_CNT_Pos = 0x2
	// Bit mask of CNT field.
	TCC_INTENCLR_CNT_Msk = 0x4
	// Bit CNT.
	TCC_INTENCLR_CNT = 0x4
	// Position of ERR field.
	TCC_INTENCLR_ERR_Pos = 0x3
	// Bit mask of ERR field.
	TCC_INTENCLR_ERR_Msk = 0x8
	// Bit ERR.
	TCC_INTENCLR_ERR = 0x8
	// Position of UFS field.
	TCC_INTENCLR_UFS_Pos = 0xa
	// Bit mask of UFS field.
	TCC_INTENCLR_UFS_Msk = 0x400
	// Bit UFS.
	TCC_INTENCLR_UFS = 0x400
	// Position of DFS field.
	TCC_INTENCLR_DFS_Pos = 0xb
	// Bit mask of DFS field.
	TCC_INTENCLR_DFS_Msk = 0x800
	// Bit DFS.
	TCC_INTENCLR_DFS = 0x800
	// Position of FAULTA field.
	TCC_INTENCLR_FAULTA_Pos = 0xc
	// Bit mask of FAULTA field.
	TCC_INTENCLR_FAULTA_Msk = 0x1000
	// Bit FAULTA.
	TCC_INTENCLR_FAULTA = 0x1000
	// Position of FAULTB field.
	TCC_INTENCLR_FAULTB_Pos = 0xd
	// Bit mask of FAULTB field.
	TCC_INTENCLR_FAULTB_Msk = 0x2000
	// Bit FAULTB.
	TCC_INTENCLR_FAULTB = 0x2000
	// Position of FAULT0 field.
	TCC_INTENCLR_FAULT0_Pos = 0xe
	// Bit mask of FAULT0 field.
	TCC_INTENCLR_FAULT0_Msk = 0x4000
	// Bit FAULT0.
	TCC_INTENCLR_FAULT0 = 0x4000
	// Position of FAULT1 field.
	TCC_INTENCLR_FAULT1_Pos = 0xf
	// Bit mask of FAULT1 field.
	TCC_INTENCLR_FAULT1_Msk = 0x8000
	// Bit FAULT1.
	TCC_INTENCLR_FAULT1 = 0x8000
	// Position of MC0 field.
	TCC_INTENCLR_MC0_Pos = 0x10
	// Bit mask of MC0 field.
	TCC_INTENCLR_MC0_Msk = 0x10000
	// Bit MC0.
	TCC_INTENCLR_MC0 = 0x10000
	// Position of MC1 field.
	TCC_INTENCLR_MC1_Pos = 0x11
	// Bit mask of MC1 field.
	TCC_INTENCLR_MC1_Msk = 0x20000
	// Bit MC1.
	TCC_INTENCLR_MC1 = 0x20000
	// Position of MC2 field.
	TCC_INTENCLR_MC2_Pos = 0x12
	// Bit mask of MC2 field.
	TCC_INTENCLR_MC2_Msk = 0x40000
	// Bit MC2.
	TCC_INTENCLR_MC2 = 0x40000
	// Position of MC3 field.
	TCC_INTENCLR_MC3_Pos = 0x13
	// Bit mask of MC3 field.
	TCC_INTENCLR_MC3_Msk = 0x80000
	// Bit MC3.
	TCC_INTENCLR_MC3 = 0x80000
	// Position of MC4 field.
	TCC_INTENCLR_MC4_Pos = 0x14
	// Bit mask of MC4 field.
	TCC_INTENCLR_MC4_Msk = 0x100000
	// Bit MC4.
	TCC_INTENCLR_MC4 = 0x100000
	// Position of MC5 field.
	TCC_INTENCLR_MC5_Pos = 0x15
	// Bit mask of MC5 field.
	TCC_INTENCLR_MC5_Msk = 0x200000
	// Bit MC5.
	TCC_INTENCLR_MC5 = 0x200000

	// INTENSET: Interrupt Enable Set
	// Position of OVF field.
	TCC_INTENSET_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TCC_INTENSET_OVF_Msk = 0x1
	// Bit OVF.
	TCC_INTENSET_OVF = 0x1
	// Position of TRG field.
	TCC_INTENSET_TRG_Pos = 0x1
	// Bit mask of TRG field.
	TCC_INTENSET_TRG_Msk = 0x2
	// Bit TRG.
	TCC_INTENSET_TRG = 0x2
	// Position of CNT field.
	TCC_INTENSET_CNT_Pos = 0x2
	// Bit mask of CNT field.
	TCC_INTENSET_CNT_Msk = 0x4
	// Bit CNT.
	TCC_INTENSET_CNT = 0x4
	// Position of ERR field.
	TCC_INTENSET_ERR_Pos = 0x3
	// Bit mask of ERR field.
	TCC_INTENSET_ERR_Msk = 0x8
	// Bit ERR.
	TCC_INTENSET_ERR = 0x8
	// Position of UFS field.
	TCC_INTENSET_UFS_Pos = 0xa
	// Bit mask of UFS field.
	TCC_INTENSET_UFS_Msk = 0x400
	// Bit UFS.
	TCC_INTENSET_UFS = 0x400
	// Position of DFS field.
	TCC_INTENSET_DFS_Pos = 0xb
	// Bit mask of DFS field.
	TCC_INTENSET_DFS_Msk = 0x800
	// Bit DFS.
	TCC_INTENSET_DFS = 0x800
	// Position of FAULTA field.
	TCC_INTENSET_FAULTA_Pos = 0xc
	// Bit mask of FAULTA field.
	TCC_INTENSET_FAULTA_Msk = 0x1000
	// Bit FAULTA.
	TCC_INTENSET_FAULTA = 0x1000
	// Position of FAULTB field.
	TCC_INTENSET_FAULTB_Pos = 0xd
	// Bit mask of FAULTB field.
	TCC_INTENSET_FAULTB_Msk = 0x2000
	// Bit FAULTB.
	TCC_INTENSET_FAULTB = 0x2000
	// Position of FAULT0 field.
	TCC_INTENSET_FAULT0_Pos = 0xe
	// Bit mask of FAULT0 field.
	TCC_INTENSET_FAULT0_Msk = 0x4000
	// Bit FAULT0.
	TCC_INTENSET_FAULT0 = 0x4000
	// Position of FAULT1 field.
	TCC_INTENSET_FAULT1_Pos = 0xf
	// Bit mask of FAULT1 field.
	TCC_INTENSET_FAULT1_Msk = 0x8000
	// Bit FAULT1.
	TCC_INTENSET_FAULT1 = 0x8000
	// Position of MC0 field.
	TCC_INTENSET_MC0_Pos = 0x10
	// Bit mask of MC0 field.
	TCC_INTENSET_MC0_Msk = 0x10000
	// Bit MC0.
	TCC_INTENSET_MC0 = 0x10000
	// Position of MC1 field.
	TCC_INTENSET_MC1_Pos = 0x11
	// Bit mask of MC1 field.
	TCC_INTENSET_MC1_Msk = 0x20000
	// Bit MC1.
	TCC_INTENSET_MC1 = 0x20000
	// Position of MC2 field.
	TCC_INTENSET_MC2_Pos = 0x12
	// Bit mask of MC2 field.
	TCC_INTENSET_MC2_Msk = 0x40000
	// Bit MC2.
	TCC_INTENSET_MC2 = 0x40000
	// Position of MC3 field.
	TCC_INTENSET_MC3_Pos = 0x13
	// Bit mask of MC3 field.
	TCC_INTENSET_MC3_Msk = 0x80000
	// Bit MC3.
	TCC_INTENSET_MC3 = 0x80000
	// Position of MC4 field.
	TCC_INTENSET_MC4_Pos = 0x14
	// Bit mask of MC4 field.
	TCC_INTENSET_MC4_Msk = 0x100000
	// Bit MC4.
	TCC_INTENSET_MC4 = 0x100000
	// Position of MC5 field.
	TCC_INTENSET_MC5_Pos = 0x15
	// Bit mask of MC5 field.
	TCC_INTENSET_MC5_Msk = 0x200000
	// Bit MC5.
	TCC_INTENSET_MC5 = 0x200000

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of OVF field.
	TCC_INTFLAG_OVF_Pos = 0x0
	// Bit mask of OVF field.
	TCC_INTFLAG_OVF_Msk = 0x1
	// Bit OVF.
	TCC_INTFLAG_OVF = 0x1
	// Position of TRG field.
	TCC_INTFLAG_TRG_Pos = 0x1
	// Bit mask of TRG field.
	TCC_INTFLAG_TRG_Msk = 0x2
	// Bit TRG.
	TCC_INTFLAG_TRG = 0x2
	// Position of CNT field.
	TCC_INTFLAG_CNT_Pos = 0x2
	// Bit mask of CNT field.
	TCC_INTFLAG_CNT_Msk = 0x4
	// Bit CNT.
	TCC_INTFLAG_CNT = 0x4
	// Position of ERR field.
	TCC_INTFLAG_ERR_Pos = 0x3
	// Bit mask of ERR field.
	TCC_INTFLAG_ERR_Msk = 0x8
	// Bit ERR.
	TCC_INTFLAG_ERR = 0x8
	// Position of UFS field.
	TCC_INTFLAG_UFS_Pos = 0xa
	// Bit mask of UFS field.
	TCC_INTFLAG_UFS_Msk = 0x400
	// Bit UFS.
	TCC_INTFLAG_UFS = 0x400
	// Position of DFS field.
	TCC_INTFLAG_DFS_Pos = 0xb
	// Bit mask of DFS field.
	TCC_INTFLAG_DFS_Msk = 0x800
	// Bit DFS.
	TCC_INTFLAG_DFS = 0x800
	// Position of FAULTA field.
	TCC_INTFLAG_FAULTA_Pos = 0xc
	// Bit mask of FAULTA field.
	TCC_INTFLAG_FAULTA_Msk = 0x1000
	// Bit FAULTA.
	TCC_INTFLAG_FAULTA = 0x1000
	// Position of FAULTB field.
	TCC_INTFLAG_FAULTB_Pos = 0xd
	// Bit mask of FAULTB field.
	TCC_INTFLAG_FAULTB_Msk = 0x2000
	// Bit FAULTB.
	TCC_INTFLAG_FAULTB = 0x2000
	// Position of FAULT0 field.
	TCC_INTFLAG_FAULT0_Pos = 0xe
	// Bit mask of FAULT0 field.
	TCC_INTFLAG_FAULT0_Msk = 0x4000
	// Bit FAULT0.
	TCC_INTFLAG_FAULT0 = 0x4000
	// Position of FAULT1 field.
	TCC_INTFLAG_FAULT1_Pos = 0xf
	// Bit mask of FAULT1 field.
	TCC_INTFLAG_FAULT1_Msk = 0x8000
	// Bit FAULT1.
	TCC_INTFLAG_FAULT1 = 0x8000
	// Position of MC0 field.
	TCC_INTFLAG_MC0_Pos = 0x10
	// Bit mask of MC0 field.
	TCC_INTFLAG_MC0_Msk = 0x10000
	// Bit MC0.
	TCC_INTFLAG_MC0 = 0x10000
	// Position of MC1 field.
	TCC_INTFLAG_MC1_Pos = 0x11
	// Bit mask of MC1 field.
	TCC_INTFLAG_MC1_Msk = 0x20000
	// Bit MC1.
	TCC_INTFLAG_MC1 = 0x20000
	// Position of MC2 field.
	TCC_INTFLAG_MC2_Pos = 0x12
	// Bit mask of MC2 field.
	TCC_INTFLAG_MC2_Msk = 0x40000
	// Bit MC2.
	TCC_INTFLAG_MC2 = 0x40000
	// Position of MC3 field.
	TCC_INTFLAG_MC3_Pos = 0x13
	// Bit mask of MC3 field.
	TCC_INTFLAG_MC3_Msk = 0x80000
	// Bit MC3.
	TCC_INTFLAG_MC3 = 0x80000
	// Position of MC4 field.
	TCC_INTFLAG_MC4_Pos = 0x14
	// Bit mask of MC4 field.
	TCC_INTFLAG_MC4_Msk = 0x100000
	// Bit MC4.
	TCC_INTFLAG_MC4 = 0x100000
	// Position of MC5 field.
	TCC_INTFLAG_MC5_Pos = 0x15
	// Bit mask of MC5 field.
	TCC_INTFLAG_MC5_Msk = 0x200000
	// Bit MC5.
	TCC_INTFLAG_MC5 = 0x200000

	// STATUS: Status
	// Position of STOP field.
	TCC_STATUS_STOP_Pos = 0x0
	// Bit mask of STOP field.
	TCC_STATUS_STOP_Msk = 0x1
	// Bit STOP.
	TCC_STATUS_STOP = 0x1
	// Position of IDX field.
	TCC_STATUS_IDX_Pos = 0x1
	// Bit mask of IDX field.
	TCC_STATUS_IDX_Msk = 0x2
	// Bit IDX.
	TCC_STATUS_IDX = 0x2
	// Position of UFS field.
	TCC_STATUS_UFS_Pos = 0x2
	// Bit mask of UFS field.
	TCC_STATUS_UFS_Msk = 0x4
	// Bit UFS.
	TCC_STATUS_UFS = 0x4
	// Position of DFS field.
	TCC_STATUS_DFS_Pos = 0x3
	// Bit mask of DFS field.
	TCC_STATUS_DFS_Msk = 0x8
	// Bit DFS.
	TCC_STATUS_DFS = 0x8
	// Position of SLAVE field.
	TCC_STATUS_SLAVE_Pos = 0x4
	// Bit mask of SLAVE field.
	TCC_STATUS_SLAVE_Msk = 0x10
	// Bit SLAVE.
	TCC_STATUS_SLAVE = 0x10
	// Position of PATTBUFV field.
	TCC_STATUS_PATTBUFV_Pos = 0x5
	// Bit mask of PATTBUFV field.
	TCC_STATUS_PATTBUFV_Msk = 0x20
	// Bit PATTBUFV.
	TCC_STATUS_PATTBUFV = 0x20
	// Position of PERBUFV field.
	TCC_STATUS_PERBUFV_Pos = 0x7
	// Bit mask of PERBUFV field.
	TCC_STATUS_PERBUFV_Msk = 0x80
	// Bit PERBUFV.
	TCC_STATUS_PERBUFV = 0x80
	// Position of FAULTAIN field.
	TCC_STATUS_FAULTAIN_Pos = 0x8
	// Bit mask of FAULTAIN field.
	TCC_STATUS_FAULTAIN_Msk = 0x100
	// Bit FAULTAIN.
	TCC_STATUS_FAULTAIN = 0x100
	// Position of FAULTBIN field.
	TCC_STATUS_FAULTBIN_Pos = 0x9
	// Bit mask of FAULTBIN field.
	TCC_STATUS_FAULTBIN_Msk = 0x200
	// Bit FAULTBIN.
	TCC_STATUS_FAULTBIN = 0x200
	// Position of FAULT0IN field.
	TCC_STATUS_FAULT0IN_Pos = 0xa
	// Bit mask of FAULT0IN field.
	TCC_STATUS_FAULT0IN_Msk = 0x400
	// Bit FAULT0IN.
	TCC_STATUS_FAULT0IN = 0x400
	// Position of FAULT1IN field.
	TCC_STATUS_FAULT1IN_Pos = 0xb
	// Bit mask of FAULT1IN field.
	TCC_STATUS_FAULT1IN_Msk = 0x800
	// Bit FAULT1IN.
	TCC_STATUS_FAULT1IN = 0x800
	// Position of FAULTA field.
	TCC_STATUS_FAULTA_Pos = 0xc
	// Bit mask of FAULTA field.
	TCC_STATUS_FAULTA_Msk = 0x1000
	// Bit FAULTA.
	TCC_STATUS_FAULTA = 0x1000
	// Position of FAULTB field.
	TCC_STATUS_FAULTB_Pos = 0xd
	// Bit mask of FAULTB field.
	TCC_STATUS_FAULTB_Msk = 0x2000
	// Bit FAULTB.
	TCC_STATUS_FAULTB = 0x2000
	// Position of FAULT0 field.
	TCC_STATUS_FAULT0_Pos = 0xe
	// Bit mask of FAULT0 field.
	TCC_STATUS_FAULT0_Msk = 0x4000
	// Bit FAULT0.
	TCC_STATUS_FAULT0 = 0x4000
	// Position of FAULT1 field.
	TCC_STATUS_FAULT1_Pos = 0xf
	// Bit mask of FAULT1 field.
	TCC_STATUS_FAULT1_Msk = 0x8000
	// Bit FAULT1.
	TCC_STATUS_FAULT1 = 0x8000
	// Position of CCBUFV0 field.
	TCC_STATUS_CCBUFV0_Pos = 0x10
	// Bit mask of CCBUFV0 field.
	TCC_STATUS_CCBUFV0_Msk = 0x10000
	// Bit CCBUFV0.
	TCC_STATUS_CCBUFV0 = 0x10000
	// Position of CCBUFV1 field.
	TCC_STATUS_CCBUFV1_Pos = 0x11
	// Bit mask of CCBUFV1 field.
	TCC_STATUS_CCBUFV1_Msk = 0x20000
	// Bit CCBUFV1.
	TCC_STATUS_CCBUFV1 = 0x20000
	// Position of CCBUFV2 field.
	TCC_STATUS_CCBUFV2_Pos = 0x12
	// Bit mask of CCBUFV2 field.
	TCC_STATUS_CCBUFV2_Msk = 0x40000
	// Bit CCBUFV2.
	TCC_STATUS_CCBUFV2 = 0x40000
	// Position of CCBUFV3 field.
	TCC_STATUS_CCBUFV3_Pos = 0x13
	// Bit mask of CCBUFV3 field.
	TCC_STATUS_CCBUFV3_Msk = 0x80000
	// Bit CCBUFV3.
	TCC_STATUS_CCBUFV3 = 0x80000
	// Position of CCBUFV4 field.
	TCC_STATUS_CCBUFV4_Pos = 0x14
	// Bit mask of CCBUFV4 field.
	TCC_STATUS_CCBUFV4_Msk = 0x100000
	// Bit CCBUFV4.
	TCC_STATUS_CCBUFV4 = 0x100000
	// Position of CCBUFV5 field.
	TCC_STATUS_CCBUFV5_Pos = 0x15
	// Bit mask of CCBUFV5 field.
	TCC_STATUS_CCBUFV5_Msk = 0x200000
	// Bit CCBUFV5.
	TCC_STATUS_CCBUFV5 = 0x200000
	// Position of CMP0 field.
	TCC_STATUS_CMP0_Pos = 0x18
	// Bit mask of CMP0 field.
	TCC_STATUS_CMP0_Msk = 0x1000000
	// Bit CMP0.
	TCC_STATUS_CMP0 = 0x1000000
	// Position of CMP1 field.
	TCC_STATUS_CMP1_Pos = 0x19
	// Bit mask of CMP1 field.
	TCC_STATUS_CMP1_Msk = 0x2000000
	// Bit CMP1.
	TCC_STATUS_CMP1 = 0x2000000
	// Position of CMP2 field.
	TCC_STATUS_CMP2_Pos = 0x1a
	// Bit mask of CMP2 field.
	TCC_STATUS_CMP2_Msk = 0x4000000
	// Bit CMP2.
	TCC_STATUS_CMP2 = 0x4000000
	// Position of CMP3 field.
	TCC_STATUS_CMP3_Pos = 0x1b
	// Bit mask of CMP3 field.
	TCC_STATUS_CMP3_Msk = 0x8000000
	// Bit CMP3.
	TCC_STATUS_CMP3 = 0x8000000
	// Position of CMP4 field.
	TCC_STATUS_CMP4_Pos = 0x1c
	// Bit mask of CMP4 field.
	TCC_STATUS_CMP4_Msk = 0x10000000
	// Bit CMP4.
	TCC_STATUS_CMP4 = 0x10000000
	// Position of CMP5 field.
	TCC_STATUS_CMP5_Pos = 0x1d
	// Bit mask of CMP5 field.
	TCC_STATUS_CMP5_Msk = 0x20000000
	// Bit CMP5.
	TCC_STATUS_CMP5 = 0x20000000

	// COUNT: Count
	// Position of COUNT field.
	TCC_COUNT_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	TCC_COUNT_COUNT_Msk = 0xffffff

	// COUNT_DITH4_MODE: Count
	// Position of COUNT field.
	TCC_COUNT_DITH4_MODE_COUNT_Pos = 0x4
	// Bit mask of COUNT field.
	TCC_COUNT_DITH4_MODE_COUNT_Msk = 0xfffff0

	// COUNT_DITH5_MODE: Count
	// Position of COUNT field.
	TCC_COUNT_DITH5_MODE_COUNT_Pos = 0x5
	// Bit mask of COUNT field.
	TCC_COUNT_DITH5_MODE_COUNT_Msk = 0xffffe0

	// COUNT_DITH6_MODE: Count
	// Position of COUNT field.
	TCC_COUNT_DITH6_MODE_COUNT_Pos = 0x6
	// Bit mask of COUNT field.
	TCC_COUNT_DITH6_MODE_COUNT_Msk = 0xffffc0

	// PATT: Pattern
	// Position of PGE0 field.
	TCC_PATT_PGE0_Pos = 0x0
	// Bit mask of PGE0 field.
	TCC_PATT_PGE0_Msk = 0x1
	// Bit PGE0.
	TCC_PATT_PGE0 = 0x1
	// Position of PGE1 field.
	TCC_PATT_PGE1_Pos = 0x1
	// Bit mask of PGE1 field.
	TCC_PATT_PGE1_Msk = 0x2
	// Bit PGE1.
	TCC_PATT_PGE1 = 0x2
	// Position of PGE2 field.
	TCC_PATT_PGE2_Pos = 0x2
	// Bit mask of PGE2 field.
	TCC_PATT_PGE2_Msk = 0x4
	// Bit PGE2.
	TCC_PATT_PGE2 = 0x4
	// Position of PGE3 field.
	TCC_PATT_PGE3_Pos = 0x3
	// Bit mask of PGE3 field.
	TCC_PATT_PGE3_Msk = 0x8
	// Bit PGE3.
	TCC_PATT_PGE3 = 0x8
	// Position of PGE4 field.
	TCC_PATT_PGE4_Pos = 0x4
	// Bit mask of PGE4 field.
	TCC_PATT_PGE4_Msk = 0x10
	// Bit PGE4.
	TCC_PATT_PGE4 = 0x10
	// Position of PGE5 field.
	TCC_PATT_PGE5_Pos = 0x5
	// Bit mask of PGE5 field.
	TCC_PATT_PGE5_Msk = 0x20
	// Bit PGE5.
	TCC_PATT_PGE5 = 0x20
	// Position of PGE6 field.
	TCC_PATT_PGE6_Pos = 0x6
	// Bit mask of PGE6 field.
	TCC_PATT_PGE6_Msk = 0x40
	// Bit PGE6.
	TCC_PATT_PGE6 = 0x40
	// Position of PGE7 field.
	TCC_PATT_PGE7_Pos = 0x7
	// Bit mask of PGE7 field.
	TCC_PATT_PGE7_Msk = 0x80
	// Bit PGE7.
	TCC_PATT_PGE7 = 0x80
	// Position of PGV0 field.
	TCC_PATT_PGV0_Pos = 0x8
	// Bit mask of PGV0 field.
	TCC_PATT_PGV0_Msk = 0x100
	// Bit PGV0.
	TCC_PATT_PGV0 = 0x100
	// Position of PGV1 field.
	TCC_PATT_PGV1_Pos = 0x9
	// Bit mask of PGV1 field.
	TCC_PATT_PGV1_Msk = 0x200
	// Bit PGV1.
	TCC_PATT_PGV1 = 0x200
	// Position of PGV2 field.
	TCC_PATT_PGV2_Pos = 0xa
	// Bit mask of PGV2 field.
	TCC_PATT_PGV2_Msk = 0x400
	// Bit PGV2.
	TCC_PATT_PGV2 = 0x400
	// Position of PGV3 field.
	TCC_PATT_PGV3_Pos = 0xb
	// Bit mask of PGV3 field.
	TCC_PATT_PGV3_Msk = 0x800
	// Bit PGV3.
	TCC_PATT_PGV3 = 0x800
	// Position of PGV4 field.
	TCC_PATT_PGV4_Pos = 0xc
	// Bit mask of PGV4 field.
	TCC_PATT_PGV4_Msk = 0x1000
	// Bit PGV4.
	TCC_PATT_PGV4 = 0x1000
	// Position of PGV5 field.
	TCC_PATT_PGV5_Pos = 0xd
	// Bit mask of PGV5 field.
	TCC_PATT_PGV5_Msk = 0x2000
	// Bit PGV5.
	TCC_PATT_PGV5 = 0x2000
	// Position of PGV6 field.
	TCC_PATT_PGV6_Pos = 0xe
	// Bit mask of PGV6 field.
	TCC_PATT_PGV6_Msk = 0x4000
	// Bit PGV6.
	TCC_PATT_PGV6 = 0x4000
	// Position of PGV7 field.
	TCC_PATT_PGV7_Pos = 0xf
	// Bit mask of PGV7 field.
	TCC_PATT_PGV7_Msk = 0x8000
	// Bit PGV7.
	TCC_PATT_PGV7 = 0x8000

	// WAVE: Waveform Control
	// Position of WAVEGEN field.
	TCC_WAVE_WAVEGEN_Pos = 0x0
	// Bit mask of WAVEGEN field.
	TCC_WAVE_WAVEGEN_Msk = 0x7
	// Normal frequency
	TCC_WAVE_WAVEGEN_NFRQ = 0x0
	// Match frequency
	TCC_WAVE_WAVEGEN_MFRQ = 0x1
	// Normal PWM
	TCC_WAVE_WAVEGEN_NPWM = 0x2
	// Dual-slope critical
	TCC_WAVE_WAVEGEN_DSCRITICAL = 0x4
	// Dual-slope with interrupt/event condition when COUNT reaches ZERO
	TCC_WAVE_WAVEGEN_DSBOTTOM = 0x5
	// Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
	TCC_WAVE_WAVEGEN_DSBOTH = 0x6
	// Dual-slope with interrupt/event condition when COUNT reaches TOP
	TCC_WAVE_WAVEGEN_DSTOP = 0x7
	// Position of RAMP field.
	TCC_WAVE_RAMP_Pos = 0x4
	// Bit mask of RAMP field.
	TCC_WAVE_RAMP_Msk = 0x30
	// RAMP1 operation
	TCC_WAVE_RAMP_RAMP1 = 0x0
	// Alternative RAMP2 operation
	TCC_WAVE_RAMP_RAMP2A = 0x1
	// RAMP2 operation
	TCC_WAVE_RAMP_RAMP2 = 0x2
	// Critical RAMP2 operation
	TCC_WAVE_RAMP_RAMP2C = 0x3
	// Position of CIPEREN field.
	TCC_WAVE_CIPEREN_Pos = 0x7
	// Bit mask of CIPEREN field.
	TCC_WAVE_CIPEREN_Msk = 0x80
	// Bit CIPEREN.
	TCC_WAVE_CIPEREN = 0x80
	// Position of CICCEN0 field.
	TCC_WAVE_CICCEN0_Pos = 0x8
	// Bit mask of CICCEN0 field.
	TCC_WAVE_CICCEN0_Msk = 0x100
	// Bit CICCEN0.
	TCC_WAVE_CICCEN0 = 0x100
	// Position of CICCEN1 field.
	TCC_WAVE_CICCEN1_Pos = 0x9
	// Bit mask of CICCEN1 field.
	TCC_WAVE_CICCEN1_Msk = 0x200
	// Bit CICCEN1.
	TCC_WAVE_CICCEN1 = 0x200
	// Position of CICCEN2 field.
	TCC_WAVE_CICCEN2_Pos = 0xa
	// Bit mask of CICCEN2 field.
	TCC_WAVE_CICCEN2_Msk = 0x400
	// Bit CICCEN2.
	TCC_WAVE_CICCEN2 = 0x400
	// Position of CICCEN3 field.
	TCC_WAVE_CICCEN3_Pos = 0xb
	// Bit mask of CICCEN3 field.
	TCC_WAVE_CICCEN3_Msk = 0x800
	// Bit CICCEN3.
	TCC_WAVE_CICCEN3 = 0x800
	// Position of POL0 field.
	TCC_WAVE_POL0_Pos = 0x10
	// Bit mask of POL0 field.
	TCC_WAVE_POL0_Msk = 0x10000
	// Bit POL0.
	TCC_WAVE_POL0 = 0x10000
	// Position of POL1 field.
	TCC_WAVE_POL1_Pos = 0x11
	// Bit mask of POL1 field.
	TCC_WAVE_POL1_Msk = 0x20000
	// Bit POL1.
	TCC_WAVE_POL1 = 0x20000
	// Position of POL2 field.
	TCC_WAVE_POL2_Pos = 0x12
	// Bit mask of POL2 field.
	TCC_WAVE_POL2_Msk = 0x40000
	// Bit POL2.
	TCC_WAVE_POL2 = 0x40000
	// Position of POL3 field.
	TCC_WAVE_POL3_Pos = 0x13
	// Bit mask of POL3 field.
	TCC_WAVE_POL3_Msk = 0x80000
	// Bit POL3.
	TCC_WAVE_POL3 = 0x80000
	// Position of POL4 field.
	TCC_WAVE_POL4_Pos = 0x14
	// Bit mask of POL4 field.
	TCC_WAVE_POL4_Msk = 0x100000
	// Bit POL4.
	TCC_WAVE_POL4 = 0x100000
	// Position of POL5 field.
	TCC_WAVE_POL5_Pos = 0x15
	// Bit mask of POL5 field.
	TCC_WAVE_POL5_Msk = 0x200000
	// Bit POL5.
	TCC_WAVE_POL5 = 0x200000
	// Position of SWAP0 field.
	TCC_WAVE_SWAP0_Pos = 0x18
	// Bit mask of SWAP0 field.
	TCC_WAVE_SWAP0_Msk = 0x1000000
	// Bit SWAP0.
	TCC_WAVE_SWAP0 = 0x1000000
	// Position of SWAP1 field.
	TCC_WAVE_SWAP1_Pos = 0x19
	// Bit mask of SWAP1 field.
	TCC_WAVE_SWAP1_Msk = 0x2000000
	// Bit SWAP1.
	TCC_WAVE_SWAP1 = 0x2000000
	// Position of SWAP2 field.
	TCC_WAVE_SWAP2_Pos = 0x1a
	// Bit mask of SWAP2 field.
	TCC_WAVE_SWAP2_Msk = 0x4000000
	// Bit SWAP2.
	TCC_WAVE_SWAP2 = 0x4000000
	// Position of SWAP3 field.
	TCC_WAVE_SWAP3_Pos = 0x1b
	// Bit mask of SWAP3 field.
	TCC_WAVE_SWAP3_Msk = 0x8000000
	// Bit SWAP3.
	TCC_WAVE_SWAP3 = 0x8000000

	// PER: Period
	// Position of PER field.
	TCC_PER_PER_Pos = 0x0
	// Bit mask of PER field.
	TCC_PER_PER_Msk = 0xffffff

	// PER_DITH4_MODE: Period
	// Position of DITHER field.
	TCC_PER_DITH4_MODE_DITHER_Pos = 0x0
	// Bit mask of DITHER field.
	TCC_PER_DITH4_MODE_DITHER_Msk = 0xf
	// Position of PER field.
	TCC_PER_DITH4_MODE_PER_Pos = 0x4
	// Bit mask of PER field.
	TCC_PER_DITH4_MODE_PER_Msk = 0xfffff0

	// PER_DITH5_MODE: Period
	// Position of DITHER field.
	TCC_PER_DITH5_MODE_DITHER_Pos = 0x0
	// Bit mask of DITHER field.
	TCC_PER_DITH5_MODE_DITHER_Msk = 0x1f
	// Position of PER field.
	TCC_PER_DITH5_MODE_PER_Pos = 0x5
	// Bit mask of PER field.
	TCC_PER_DITH5_MODE_PER_Msk = 0xffffe0

	// PER_DITH6_MODE: Period
	// Position of DITHER field.
	TCC_PER_DITH6_MODE_DITHER_Pos = 0x0
	// Bit mask of DITHER field.
	TCC_PER_DITH6_MODE_DITHER_Msk = 0x3f
	// Position of PER field.
	TCC_PER_DITH6_MODE_PER_Pos = 0x6
	// Bit mask of PER field.
	TCC_PER_DITH6_MODE_PER_Msk = 0xffffc0

	// CC: Compare and Capture
	// Position of CC field.
	TCC_CC_CC_Pos = 0x0
	// Bit mask of CC field.
	TCC_CC_CC_Msk = 0xffffff

	// CC_DITH4_MODE: Compare and Capture
	// Position of DITHER field.
	TCC_CC_DITH4_MODE_DITHER_Pos = 0x0
	// Bit mask of DITHER field.
	TCC_CC_DITH4_MODE_DITHER_Msk = 0xf
	// Position of CC field.
	TCC_CC_DITH4_MODE_CC_Pos = 0x4
	// Bit mask of CC field.
	TCC_CC_DITH4_MODE_CC_Msk = 0xfffff0

	// CC_DITH5_MODE: Compare and Capture
	// Position of DITHER field.
	TCC_CC_DITH5_MODE_DITHER_Pos = 0x0
	// Bit mask of DITHER field.
	TCC_CC_DITH5_MODE_DITHER_Msk = 0x1f
	// Position of CC field.
	TCC_CC_DITH5_MODE_CC_Pos = 0x5
	// Bit mask of CC field.
	TCC_CC_DITH5_MODE_CC_Msk = 0xffffe0

	// CC_DITH6_MODE: Compare and Capture
	// Position of DITHER field.
	TCC_CC_DITH6_MODE_DITHER_Pos = 0x0
	// Bit mask of DITHER field.
	TCC_CC_DITH6_MODE_DITHER_Msk = 0x3f
	// Position of CC field.
	TCC_CC_DITH6_MODE_CC_Pos = 0x6
	// Bit mask of CC field.
	TCC_CC_DITH6_MODE_CC_Msk = 0xffffc0

	// PATTBUF: Pattern Buffer
	// Position of PGEB0 field.
	TCC_PATTBUF_PGEB0_Pos = 0x0
	// Bit mask of PGEB0 field.
	TCC_PATTBUF_PGEB0_Msk = 0x1
	// Bit PGEB0.
	TCC_PATTBUF_PGEB0 = 0x1
	// Position of PGEB1 field.
	TCC_PATTBUF_PGEB1_Pos = 0x1
	// Bit mask of PGEB1 field.
	TCC_PATTBUF_PGEB1_Msk = 0x2
	// Bit PGEB1.
	TCC_PATTBUF_PGEB1 = 0x2
	// Position of PGEB2 field.
	TCC_PATTBUF_PGEB2_Pos = 0x2
	// Bit mask of PGEB2 field.
	TCC_PATTBUF_PGEB2_Msk = 0x4
	// Bit PGEB2.
	TCC_PATTBUF_PGEB2 = 0x4
	// Position of PGEB3 field.
	TCC_PATTBUF_PGEB3_Pos = 0x3
	// Bit mask of PGEB3 field.
	TCC_PATTBUF_PGEB3_Msk = 0x8
	// Bit PGEB3.
	TCC_PATTBUF_PGEB3 = 0x8
	// Position of PGEB4 field.
	TCC_PATTBUF_PGEB4_Pos = 0x4
	// Bit mask of PGEB4 field.
	TCC_PATTBUF_PGEB4_Msk = 0x10
	// Bit PGEB4.
	TCC_PATTBUF_PGEB4 = 0x10
	// Position of PGEB5 field.
	TCC_PATTBUF_PGEB5_Pos = 0x5
	// Bit mask of PGEB5 field.
	TCC_PATTBUF_PGEB5_Msk = 0x20
	// Bit PGEB5.
	TCC_PATTBUF_PGEB5 = 0x20
	// Position of PGEB6 field.
	TCC_PATTBUF_PGEB6_Pos = 0x6
	// Bit mask of PGEB6 field.
	TCC_PATTBUF_PGEB6_Msk = 0x40
	// Bit PGEB6.
	TCC_PATTBUF_PGEB6 = 0x40
	// Position of PGEB7 field.
	TCC_PATTBUF_PGEB7_Pos = 0x7
	// Bit mask of PGEB7 field.
	TCC_PATTBUF_PGEB7_Msk = 0x80
	// Bit PGEB7.
	TCC_PATTBUF_PGEB7 = 0x80
	// Position of PGVB0 field.
	TCC_PATTBUF_PGVB0_Pos = 0x8
	// Bit mask of PGVB0 field.
	TCC_PATTBUF_PGVB0_Msk = 0x100
	// Bit PGVB0.
	TCC_PATTBUF_PGVB0 = 0x100
	// Position of PGVB1 field.
	TCC_PATTBUF_PGVB1_Pos = 0x9
	// Bit mask of PGVB1 field.
	TCC_PATTBUF_PGVB1_Msk = 0x200
	// Bit PGVB1.
	TCC_PATTBUF_PGVB1 = 0x200
	// Position of PGVB2 field.
	TCC_PATTBUF_PGVB2_Pos = 0xa
	// Bit mask of PGVB2 field.
	TCC_PATTBUF_PGVB2_Msk = 0x400
	// Bit PGVB2.
	TCC_PATTBUF_PGVB2 = 0x400
	// Position of PGVB3 field.
	TCC_PATTBUF_PGVB3_Pos = 0xb
	// Bit mask of PGVB3 field.
	TCC_PATTBUF_PGVB3_Msk = 0x800
	// Bit PGVB3.
	TCC_PATTBUF_PGVB3 = 0x800
	// Position of PGVB4 field.
	TCC_PATTBUF_PGVB4_Pos = 0xc
	// Bit mask of PGVB4 field.
	TCC_PATTBUF_PGVB4_Msk = 0x1000
	// Bit PGVB4.
	TCC_PATTBUF_PGVB4 = 0x1000
	// Position of PGVB5 field.
	TCC_PATTBUF_PGVB5_Pos = 0xd
	// Bit mask of PGVB5 field.
	TCC_PATTBUF_PGVB5_Msk = 0x2000
	// Bit PGVB5.
	TCC_PATTBUF_PGVB5 = 0x2000
	// Position of PGVB6 field.
	TCC_PATTBUF_PGVB6_Pos = 0xe
	// Bit mask of PGVB6 field.
	TCC_PATTBUF_PGVB6_Msk = 0x4000
	// Bit PGVB6.
	TCC_PATTBUF_PGVB6 = 0x4000
	// Position of PGVB7 field.
	TCC_PATTBUF_PGVB7_Pos = 0xf
	// Bit mask of PGVB7 field.
	TCC_PATTBUF_PGVB7_Msk = 0x8000
	// Bit PGVB7.
	TCC_PATTBUF_PGVB7 = 0x8000

	// PERBUF: Period Buffer
	// Position of PERBUF field.
	TCC_PERBUF_PERBUF_Pos = 0x0
	// Bit mask of PERBUF field.
	TCC_PERBUF_PERBUF_Msk = 0xffffff

	// PERBUF_DITH4_MODE: Period Buffer
	// Position of DITHERBUF field.
	TCC_PERBUF_DITH4_MODE_DITHERBUF_Pos = 0x0
	// Bit mask of DITHERBUF field.
	TCC_PERBUF_DITH4_MODE_DITHERBUF_Msk = 0xf
	// Position of PERBUF field.
	TCC_PERBUF_DITH4_MODE_PERBUF_Pos = 0x4
	// Bit mask of PERBUF field.
	TCC_PERBUF_DITH4_MODE_PERBUF_Msk = 0xfffff0

	// PERBUF_DITH5_MODE: Period Buffer
	// Position of DITHERBUF field.
	TCC_PERBUF_DITH5_MODE_DITHERBUF_Pos = 0x0
	// Bit mask of DITHERBUF field.
	TCC_PERBUF_DITH5_MODE_DITHERBUF_Msk = 0x1f
	// Position of PERBUF field.
	TCC_PERBUF_DITH5_MODE_PERBUF_Pos = 0x5
	// Bit mask of PERBUF field.
	TCC_PERBUF_DITH5_MODE_PERBUF_Msk = 0xffffe0

	// PERBUF_DITH6_MODE: Period Buffer
	// Position of DITHERBUF field.
	TCC_PERBUF_DITH6_MODE_DITHERBUF_Pos = 0x0
	// Bit mask of DITHERBUF field.
	TCC_PERBUF_DITH6_MODE_DITHERBUF_Msk = 0x3f
	// Position of PERBUF field.
	TCC_PERBUF_DITH6_MODE_PERBUF_Pos = 0x6
	// Bit mask of PERBUF field.
	TCC_PERBUF_DITH6_MODE_PERBUF_Msk = 0xffffc0

	// CCBUF: Compare and Capture Buffer
	// Position of CCBUF field.
	TCC_CCBUF_CCBUF_Pos = 0x0
	// Bit mask of CCBUF field.
	TCC_CCBUF_CCBUF_Msk = 0xffffff

	// CCBUF_DITH4_MODE: Compare and Capture Buffer
	// Position of CCBUF field.
	TCC_CCBUF_DITH4_MODE_CCBUF_Pos = 0x0
	// Bit mask of CCBUF field.
	TCC_CCBUF_DITH4_MODE_CCBUF_Msk = 0xf
	// Position of DITHERBUF field.
	TCC_CCBUF_DITH4_MODE_DITHERBUF_Pos = 0x4
	// Bit mask of DITHERBUF field.
	TCC_CCBUF_DITH4_MODE_DITHERBUF_Msk = 0xfffff0

	// CCBUF_DITH5_MODE: Compare and Capture Buffer
	// Position of DITHERBUF field.
	TCC_CCBUF_DITH5_MODE_DITHERBUF_Pos = 0x0
	// Bit mask of DITHERBUF field.
	TCC_CCBUF_DITH5_MODE_DITHERBUF_Msk = 0x1f
	// Position of CCBUF field.
	TCC_CCBUF_DITH5_MODE_CCBUF_Pos = 0x5
	// Bit mask of CCBUF field.
	TCC_CCBUF_DITH5_MODE_CCBUF_Msk = 0xffffe0

	// CCBUF_DITH6_MODE: Compare and Capture Buffer
	// Position of DITHERBUF field.
	TCC_CCBUF_DITH6_MODE_DITHERBUF_Pos = 0x0
	// Bit mask of DITHERBUF field.
	TCC_CCBUF_DITH6_MODE_DITHERBUF_Msk = 0x3f
	// Position of CCBUF field.
	TCC_CCBUF_DITH6_MODE_CCBUF_Pos = 0x6
	// Bit mask of CCBUF field.
	TCC_CCBUF_DITH6_MODE_CCBUF_Msk = 0xffffc0
)

// Bitfields for TRNG: True Random Generator
const (
	// CTRLA: Control A
	// Position of ENABLE field.
	TRNG_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	TRNG_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	TRNG_CTRLA_ENABLE = 0x2
	// Position of RUNSTDBY field.
	TRNG_CTRLA_RUNSTDBY_Pos = 0x6
	// Bit mask of RUNSTDBY field.
	TRNG_CTRLA_RUNSTDBY_Msk = 0x40
	// Bit RUNSTDBY.
	TRNG_CTRLA_RUNSTDBY = 0x40

	// EVCTRL: Event Control
	// Position of DATARDYEO field.
	TRNG_EVCTRL_DATARDYEO_Pos = 0x0
	// Bit mask of DATARDYEO field.
	TRNG_EVCTRL_DATARDYEO_Msk = 0x1
	// Bit DATARDYEO.
	TRNG_EVCTRL_DATARDYEO = 0x1

	// INTENCLR: Interrupt Enable Clear
	// Position of DATARDY field.
	TRNG_INTENCLR_DATARDY_Pos = 0x0
	// Bit mask of DATARDY field.
	TRNG_INTENCLR_DATARDY_Msk = 0x1
	// Bit DATARDY.
	TRNG_INTENCLR_DATARDY = 0x1

	// INTENSET: Interrupt Enable Set
	// Position of DATARDY field.
	TRNG_INTENSET_DATARDY_Pos = 0x0
	// Bit mask of DATARDY field.
	TRNG_INTENSET_DATARDY_Msk = 0x1
	// Bit DATARDY.
	TRNG_INTENSET_DATARDY = 0x1

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of DATARDY field.
	TRNG_INTFLAG_DATARDY_Pos = 0x0
	// Bit mask of DATARDY field.
	TRNG_INTFLAG_DATARDY_Msk = 0x1
	// Bit DATARDY.
	TRNG_INTFLAG_DATARDY = 0x1

	// DATA: Output Data
	// Position of DATA field.
	TRNG_DATA_DATA_Pos = 0x0
	// Bit mask of DATA field.
	TRNG_DATA_DATA_Msk = 0xffffffff
)

// Bitfields for USB: Universal Serial Bus
const ()

// Bitfields for USB_DEVICE: Universal Serial Bus - DEVICE
const (
	// CTRLA: Control A
	// Position of SWRST field.
	USB_DEVICE_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	USB_DEVICE_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	USB_DEVICE_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	USB_DEVICE_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	USB_DEVICE_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	USB_DEVICE_CTRLA_ENABLE = 0x2
	// Position of RUNSTDBY field.
	USB_DEVICE_CTRLA_RUNSTDBY_Pos = 0x2
	// Bit mask of RUNSTDBY field.
	USB_DEVICE_CTRLA_RUNSTDBY_Msk = 0x4
	// Bit RUNSTDBY.
	USB_DEVICE_CTRLA_RUNSTDBY = 0x4
	// Position of MODE field.
	USB_DEVICE_CTRLA_MODE_Pos = 0x7
	// Bit mask of MODE field.
	USB_DEVICE_CTRLA_MODE_Msk = 0x80
	// Bit MODE.
	USB_DEVICE_CTRLA_MODE = 0x80
	// Device Mode
	USB_DEVICE_CTRLA_MODE_DEVICE = 0x0
	// Host Mode
	USB_DEVICE_CTRLA_MODE_HOST = 0x1

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	USB_DEVICE_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	USB_DEVICE_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	USB_DEVICE_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	USB_DEVICE_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	USB_DEVICE_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	USB_DEVICE_SYNCBUSY_ENABLE = 0x2

	// QOSCTRL: USB Quality Of Service
	// Position of CQOS field.
	USB_DEVICE_QOSCTRL_CQOS_Pos = 0x0
	// Bit mask of CQOS field.
	USB_DEVICE_QOSCTRL_CQOS_Msk = 0x3
	// Position of DQOS field.
	USB_DEVICE_QOSCTRL_DQOS_Pos = 0x2
	// Bit mask of DQOS field.
	USB_DEVICE_QOSCTRL_DQOS_Msk = 0xc

	// CTRLB: DEVICE Control B
	// Position of DETACH field.
	USB_DEVICE_CTRLB_DETACH_Pos = 0x0
	// Bit mask of DETACH field.
	USB_DEVICE_CTRLB_DETACH_Msk = 0x1
	// Bit DETACH.
	USB_DEVICE_CTRLB_DETACH = 0x1
	// Position of UPRSM field.
	USB_DEVICE_CTRLB_UPRSM_Pos = 0x1
	// Bit mask of UPRSM field.
	USB_DEVICE_CTRLB_UPRSM_Msk = 0x2
	// Bit UPRSM.
	USB_DEVICE_CTRLB_UPRSM = 0x2
	// Position of SPDCONF field.
	USB_DEVICE_CTRLB_SPDCONF_Pos = 0x2
	// Bit mask of SPDCONF field.
	USB_DEVICE_CTRLB_SPDCONF_Msk = 0xc
	// FS : Full Speed
	USB_DEVICE_CTRLB_SPDCONF_FS = 0x0
	// LS : Low Speed
	USB_DEVICE_CTRLB_SPDCONF_LS = 0x1
	// HS : High Speed capable
	USB_DEVICE_CTRLB_SPDCONF_HS = 0x2
	// HSTM: High Speed Test Mode (force high-speed mode for test mode)
	USB_DEVICE_CTRLB_SPDCONF_HSTM = 0x3
	// Position of NREPLY field.
	USB_DEVICE_CTRLB_NREPLY_Pos = 0x4
	// Bit mask of NREPLY field.
	USB_DEVICE_CTRLB_NREPLY_Msk = 0x10
	// Bit NREPLY.
	USB_DEVICE_CTRLB_NREPLY = 0x10
	// Position of TSTJ field.
	USB_DEVICE_CTRLB_TSTJ_Pos = 0x5
	// Bit mask of TSTJ field.
	USB_DEVICE_CTRLB_TSTJ_Msk = 0x20
	// Bit TSTJ.
	USB_DEVICE_CTRLB_TSTJ = 0x20
	// Position of TSTK field.
	USB_DEVICE_CTRLB_TSTK_Pos = 0x6
	// Bit mask of TSTK field.
	USB_DEVICE_CTRLB_TSTK_Msk = 0x40
	// Bit TSTK.
	USB_DEVICE_CTRLB_TSTK = 0x40
	// Position of TSTPCKT field.
	USB_DEVICE_CTRLB_TSTPCKT_Pos = 0x7
	// Bit mask of TSTPCKT field.
	USB_DEVICE_CTRLB_TSTPCKT_Msk = 0x80
	// Bit TSTPCKT.
	USB_DEVICE_CTRLB_TSTPCKT = 0x80
	// Position of OPMODE2 field.
	USB_DEVICE_CTRLB_OPMODE2_Pos = 0x8
	// Bit mask of OPMODE2 field.
	USB_DEVICE_CTRLB_OPMODE2_Msk = 0x100
	// Bit OPMODE2.
	USB_DEVICE_CTRLB_OPMODE2 = 0x100
	// Position of GNAK field.
	USB_DEVICE_CTRLB_GNAK_Pos = 0x9
	// Bit mask of GNAK field.
	USB_DEVICE_CTRLB_GNAK_Msk = 0x200
	// Bit GNAK.
	USB_DEVICE_CTRLB_GNAK = 0x200
	// Position of LPMHDSK field.
	USB_DEVICE_CTRLB_LPMHDSK_Pos = 0xa
	// Bit mask of LPMHDSK field.
	USB_DEVICE_CTRLB_LPMHDSK_Msk = 0xc00
	// No handshake. LPM is not supported
	USB_DEVICE_CTRLB_LPMHDSK_NO = 0x0
	// ACK
	USB_DEVICE_CTRLB_LPMHDSK_ACK = 0x1
	// NYET
	USB_DEVICE_CTRLB_LPMHDSK_NYET = 0x2
	// STALL
	USB_DEVICE_CTRLB_LPMHDSK_STALL = 0x3

	// DADD: DEVICE Device Address
	// Position of DADD field.
	USB_DEVICE_DADD_DADD_Pos = 0x0
	// Bit mask of DADD field.
	USB_DEVICE_DADD_DADD_Msk = 0x7f
	// Position of ADDEN field.
	USB_DEVICE_DADD_ADDEN_Pos = 0x7
	// Bit mask of ADDEN field.
	USB_DEVICE_DADD_ADDEN_Msk = 0x80
	// Bit ADDEN.
	USB_DEVICE_DADD_ADDEN = 0x80

	// STATUS: DEVICE Status
	// Position of SPEED field.
	USB_DEVICE_STATUS_SPEED_Pos = 0x2
	// Bit mask of SPEED field.
	USB_DEVICE_STATUS_SPEED_Msk = 0xc
	// Full-speed mode
	USB_DEVICE_STATUS_SPEED_FS = 0x0
	// Low-speed mode
	USB_DEVICE_STATUS_SPEED_LS = 0x1
	// High-speed mode
	USB_DEVICE_STATUS_SPEED_HS = 0x2
	// Position of LINESTATE field.
	USB_DEVICE_STATUS_LINESTATE_Pos = 0x6
	// Bit mask of LINESTATE field.
	USB_DEVICE_STATUS_LINESTATE_Msk = 0xc0
	// SE0/RESET
	USB_DEVICE_STATUS_LINESTATE_0 = 0x0
	// FS-J or LS-K State
	USB_DEVICE_STATUS_LINESTATE_1 = 0x1
	// FS-K or LS-J State
	USB_DEVICE_STATUS_LINESTATE_2 = 0x2

	// FSMSTATUS: Finite State Machine Status
	// Position of FSMSTATE field.
	USB_DEVICE_FSMSTATUS_FSMSTATE_Pos = 0x0
	// Bit mask of FSMSTATE field.
	USB_DEVICE_FSMSTATUS_FSMSTATE_Msk = 0x7f
	// OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
	USB_DEVICE_FSMSTATUS_FSMSTATE_OFF = 0x1
	// ON (L0). It corresponds to the Idle and Active states
	USB_DEVICE_FSMSTATUS_FSMSTATE_ON = 0x2
	// SUSPEND (L2)
	USB_DEVICE_FSMSTATUS_FSMSTATE_SUSPEND = 0x4
	// SLEEP (L1)
	USB_DEVICE_FSMSTATUS_FSMSTATE_SLEEP = 0x8
	// DNRESUME. Down Stream Resume.
	USB_DEVICE_FSMSTATUS_FSMSTATE_DNRESUME = 0x10
	// UPRESUME. Up Stream Resume.
	USB_DEVICE_FSMSTATUS_FSMSTATE_UPRESUME = 0x20
	// RESET. USB lines Reset.
	USB_DEVICE_FSMSTATUS_FSMSTATE_RESET = 0x40

	// FNUM: DEVICE Device Frame Number
	// Position of MFNUM field.
	USB_DEVICE_FNUM_MFNUM_Pos = 0x0
	// Bit mask of MFNUM field.
	USB_DEVICE_FNUM_MFNUM_Msk = 0x7
	// Position of FNUM field.
	USB_DEVICE_FNUM_FNUM_Pos = 0x3
	// Bit mask of FNUM field.
	USB_DEVICE_FNUM_FNUM_Msk = 0x3ff8
	// Position of FNCERR field.
	USB_DEVICE_FNUM_FNCERR_Pos = 0xf
	// Bit mask of FNCERR field.
	USB_DEVICE_FNUM_FNCERR_Msk = 0x8000
	// Bit FNCERR.
	USB_DEVICE_FNUM_FNCERR = 0x8000

	// INTENCLR: DEVICE Device Interrupt Enable Clear
	// Position of SUSPEND field.
	USB_DEVICE_INTENCLR_SUSPEND_Pos = 0x0
	// Bit mask of SUSPEND field.
	USB_DEVICE_INTENCLR_SUSPEND_Msk = 0x1
	// Bit SUSPEND.
	USB_DEVICE_INTENCLR_SUSPEND = 0x1
	// Position of MSOF field.
	USB_DEVICE_INTENCLR_MSOF_Pos = 0x1
	// Bit mask of MSOF field.
	USB_DEVICE_INTENCLR_MSOF_Msk = 0x2
	// Bit MSOF.
	USB_DEVICE_INTENCLR_MSOF = 0x2
	// Position of SOF field.
	USB_DEVICE_INTENCLR_SOF_Pos = 0x2
	// Bit mask of SOF field.
	USB_DEVICE_INTENCLR_SOF_Msk = 0x4
	// Bit SOF.
	USB_DEVICE_INTENCLR_SOF = 0x4
	// Position of EORST field.
	USB_DEVICE_INTENCLR_EORST_Pos = 0x3
	// Bit mask of EORST field.
	USB_DEVICE_INTENCLR_EORST_Msk = 0x8
	// Bit EORST.
	USB_DEVICE_INTENCLR_EORST = 0x8
	// Position of WAKEUP field.
	USB_DEVICE_INTENCLR_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	USB_DEVICE_INTENCLR_WAKEUP_Msk = 0x10
	// Bit WAKEUP.
	USB_DEVICE_INTENCLR_WAKEUP = 0x10
	// Position of EORSM field.
	USB_DEVICE_INTENCLR_EORSM_Pos = 0x5
	// Bit mask of EORSM field.
	USB_DEVICE_INTENCLR_EORSM_Msk = 0x20
	// Bit EORSM.
	USB_DEVICE_INTENCLR_EORSM = 0x20
	// Position of UPRSM field.
	USB_DEVICE_INTENCLR_UPRSM_Pos = 0x6
	// Bit mask of UPRSM field.
	USB_DEVICE_INTENCLR_UPRSM_Msk = 0x40
	// Bit UPRSM.
	USB_DEVICE_INTENCLR_UPRSM = 0x40
	// Position of RAMACER field.
	USB_DEVICE_INTENCLR_RAMACER_Pos = 0x7
	// Bit mask of RAMACER field.
	USB_DEVICE_INTENCLR_RAMACER_Msk = 0x80
	// Bit RAMACER.
	USB_DEVICE_INTENCLR_RAMACER = 0x80
	// Position of LPMNYET field.
	USB_DEVICE_INTENCLR_LPMNYET_Pos = 0x8
	// Bit mask of LPMNYET field.
	USB_DEVICE_INTENCLR_LPMNYET_Msk = 0x100
	// Bit LPMNYET.
	USB_DEVICE_INTENCLR_LPMNYET = 0x100
	// Position of LPMSUSP field.
	USB_DEVICE_INTENCLR_LPMSUSP_Pos = 0x9
	// Bit mask of LPMSUSP field.
	USB_DEVICE_INTENCLR_LPMSUSP_Msk = 0x200
	// Bit LPMSUSP.
	USB_DEVICE_INTENCLR_LPMSUSP = 0x200

	// INTENSET: DEVICE Device Interrupt Enable Set
	// Position of SUSPEND field.
	USB_DEVICE_INTENSET_SUSPEND_Pos = 0x0
	// Bit mask of SUSPEND field.
	USB_DEVICE_INTENSET_SUSPEND_Msk = 0x1
	// Bit SUSPEND.
	USB_DEVICE_INTENSET_SUSPEND = 0x1
	// Position of MSOF field.
	USB_DEVICE_INTENSET_MSOF_Pos = 0x1
	// Bit mask of MSOF field.
	USB_DEVICE_INTENSET_MSOF_Msk = 0x2
	// Bit MSOF.
	USB_DEVICE_INTENSET_MSOF = 0x2
	// Position of SOF field.
	USB_DEVICE_INTENSET_SOF_Pos = 0x2
	// Bit mask of SOF field.
	USB_DEVICE_INTENSET_SOF_Msk = 0x4
	// Bit SOF.
	USB_DEVICE_INTENSET_SOF = 0x4
	// Position of EORST field.
	USB_DEVICE_INTENSET_EORST_Pos = 0x3
	// Bit mask of EORST field.
	USB_DEVICE_INTENSET_EORST_Msk = 0x8
	// Bit EORST.
	USB_DEVICE_INTENSET_EORST = 0x8
	// Position of WAKEUP field.
	USB_DEVICE_INTENSET_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	USB_DEVICE_INTENSET_WAKEUP_Msk = 0x10
	// Bit WAKEUP.
	USB_DEVICE_INTENSET_WAKEUP = 0x10
	// Position of EORSM field.
	USB_DEVICE_INTENSET_EORSM_Pos = 0x5
	// Bit mask of EORSM field.
	USB_DEVICE_INTENSET_EORSM_Msk = 0x20
	// Bit EORSM.
	USB_DEVICE_INTENSET_EORSM = 0x20
	// Position of UPRSM field.
	USB_DEVICE_INTENSET_UPRSM_Pos = 0x6
	// Bit mask of UPRSM field.
	USB_DEVICE_INTENSET_UPRSM_Msk = 0x40
	// Bit UPRSM.
	USB_DEVICE_INTENSET_UPRSM = 0x40
	// Position of RAMACER field.
	USB_DEVICE_INTENSET_RAMACER_Pos = 0x7
	// Bit mask of RAMACER field.
	USB_DEVICE_INTENSET_RAMACER_Msk = 0x80
	// Bit RAMACER.
	USB_DEVICE_INTENSET_RAMACER = 0x80
	// Position of LPMNYET field.
	USB_DEVICE_INTENSET_LPMNYET_Pos = 0x8
	// Bit mask of LPMNYET field.
	USB_DEVICE_INTENSET_LPMNYET_Msk = 0x100
	// Bit LPMNYET.
	USB_DEVICE_INTENSET_LPMNYET = 0x100
	// Position of LPMSUSP field.
	USB_DEVICE_INTENSET_LPMSUSP_Pos = 0x9
	// Bit mask of LPMSUSP field.
	USB_DEVICE_INTENSET_LPMSUSP_Msk = 0x200
	// Bit LPMSUSP.
	USB_DEVICE_INTENSET_LPMSUSP = 0x200

	// INTFLAG: DEVICE Device Interrupt Flag
	// Position of SUSPEND field.
	USB_DEVICE_INTFLAG_SUSPEND_Pos = 0x0
	// Bit mask of SUSPEND field.
	USB_DEVICE_INTFLAG_SUSPEND_Msk = 0x1
	// Bit SUSPEND.
	USB_DEVICE_INTFLAG_SUSPEND = 0x1
	// Position of MSOF field.
	USB_DEVICE_INTFLAG_MSOF_Pos = 0x1
	// Bit mask of MSOF field.
	USB_DEVICE_INTFLAG_MSOF_Msk = 0x2
	// Bit MSOF.
	USB_DEVICE_INTFLAG_MSOF = 0x2
	// Position of SOF field.
	USB_DEVICE_INTFLAG_SOF_Pos = 0x2
	// Bit mask of SOF field.
	USB_DEVICE_INTFLAG_SOF_Msk = 0x4
	// Bit SOF.
	USB_DEVICE_INTFLAG_SOF = 0x4
	// Position of EORST field.
	USB_DEVICE_INTFLAG_EORST_Pos = 0x3
	// Bit mask of EORST field.
	USB_DEVICE_INTFLAG_EORST_Msk = 0x8
	// Bit EORST.
	USB_DEVICE_INTFLAG_EORST = 0x8
	// Position of WAKEUP field.
	USB_DEVICE_INTFLAG_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	USB_DEVICE_INTFLAG_WAKEUP_Msk = 0x10
	// Bit WAKEUP.
	USB_DEVICE_INTFLAG_WAKEUP = 0x10
	// Position of EORSM field.
	USB_DEVICE_INTFLAG_EORSM_Pos = 0x5
	// Bit mask of EORSM field.
	USB_DEVICE_INTFLAG_EORSM_Msk = 0x20
	// Bit EORSM.
	USB_DEVICE_INTFLAG_EORSM = 0x20
	// Position of UPRSM field.
	USB_DEVICE_INTFLAG_UPRSM_Pos = 0x6
	// Bit mask of UPRSM field.
	USB_DEVICE_INTFLAG_UPRSM_Msk = 0x40
	// Bit UPRSM.
	USB_DEVICE_INTFLAG_UPRSM = 0x40
	// Position of RAMACER field.
	USB_DEVICE_INTFLAG_RAMACER_Pos = 0x7
	// Bit mask of RAMACER field.
	USB_DEVICE_INTFLAG_RAMACER_Msk = 0x80
	// Bit RAMACER.
	USB_DEVICE_INTFLAG_RAMACER = 0x80
	// Position of LPMNYET field.
	USB_DEVICE_INTFLAG_LPMNYET_Pos = 0x8
	// Bit mask of LPMNYET field.
	USB_DEVICE_INTFLAG_LPMNYET_Msk = 0x100
	// Bit LPMNYET.
	USB_DEVICE_INTFLAG_LPMNYET = 0x100
	// Position of LPMSUSP field.
	USB_DEVICE_INTFLAG_LPMSUSP_Pos = 0x9
	// Bit mask of LPMSUSP field.
	USB_DEVICE_INTFLAG_LPMSUSP_Msk = 0x200
	// Bit LPMSUSP.
	USB_DEVICE_INTFLAG_LPMSUSP = 0x200

	// EPINTSMRY: DEVICE End Point Interrupt Summary
	// Position of EPINT0 field.
	USB_DEVICE_EPINTSMRY_EPINT0_Pos = 0x0
	// Bit mask of EPINT0 field.
	USB_DEVICE_EPINTSMRY_EPINT0_Msk = 0x1
	// Bit EPINT0.
	USB_DEVICE_EPINTSMRY_EPINT0 = 0x1
	// Position of EPINT1 field.
	USB_DEVICE_EPINTSMRY_EPINT1_Pos = 0x1
	// Bit mask of EPINT1 field.
	USB_DEVICE_EPINTSMRY_EPINT1_Msk = 0x2
	// Bit EPINT1.
	USB_DEVICE_EPINTSMRY_EPINT1 = 0x2
	// Position of EPINT2 field.
	USB_DEVICE_EPINTSMRY_EPINT2_Pos = 0x2
	// Bit mask of EPINT2 field.
	USB_DEVICE_EPINTSMRY_EPINT2_Msk = 0x4
	// Bit EPINT2.
	USB_DEVICE_EPINTSMRY_EPINT2 = 0x4
	// Position of EPINT3 field.
	USB_DEVICE_EPINTSMRY_EPINT3_Pos = 0x3
	// Bit mask of EPINT3 field.
	USB_DEVICE_EPINTSMRY_EPINT3_Msk = 0x8
	// Bit EPINT3.
	USB_DEVICE_EPINTSMRY_EPINT3 = 0x8
	// Position of EPINT4 field.
	USB_DEVICE_EPINTSMRY_EPINT4_Pos = 0x4
	// Bit mask of EPINT4 field.
	USB_DEVICE_EPINTSMRY_EPINT4_Msk = 0x10
	// Bit EPINT4.
	USB_DEVICE_EPINTSMRY_EPINT4 = 0x10
	// Position of EPINT5 field.
	USB_DEVICE_EPINTSMRY_EPINT5_Pos = 0x5
	// Bit mask of EPINT5 field.
	USB_DEVICE_EPINTSMRY_EPINT5_Msk = 0x20
	// Bit EPINT5.
	USB_DEVICE_EPINTSMRY_EPINT5 = 0x20
	// Position of EPINT6 field.
	USB_DEVICE_EPINTSMRY_EPINT6_Pos = 0x6
	// Bit mask of EPINT6 field.
	USB_DEVICE_EPINTSMRY_EPINT6_Msk = 0x40
	// Bit EPINT6.
	USB_DEVICE_EPINTSMRY_EPINT6 = 0x40
	// Position of EPINT7 field.
	USB_DEVICE_EPINTSMRY_EPINT7_Pos = 0x7
	// Bit mask of EPINT7 field.
	USB_DEVICE_EPINTSMRY_EPINT7_Msk = 0x80
	// Bit EPINT7.
	USB_DEVICE_EPINTSMRY_EPINT7 = 0x80

	// DESCADD: Descriptor Address
	// Position of DESCADD field.
	USB_DEVICE_DESCADD_DESCADD_Pos = 0x0
	// Bit mask of DESCADD field.
	USB_DEVICE_DESCADD_DESCADD_Msk = 0xffffffff

	// PADCAL: USB PAD Calibration
	// Position of TRANSP field.
	USB_DEVICE_PADCAL_TRANSP_Pos = 0x0
	// Bit mask of TRANSP field.
	USB_DEVICE_PADCAL_TRANSP_Msk = 0x1f
	// Position of TRANSN field.
	USB_DEVICE_PADCAL_TRANSN_Pos = 0x6
	// Bit mask of TRANSN field.
	USB_DEVICE_PADCAL_TRANSN_Msk = 0x7c0
	// Position of TRIM field.
	USB_DEVICE_PADCAL_TRIM_Pos = 0xc
	// Bit mask of TRIM field.
	USB_DEVICE_PADCAL_TRIM_Msk = 0x7000

	// DEVICE_ENDPOINT.EPCFG: DEVICE_ENDPOINT End Point Configuration
	// Position of EPTYPE0 field.
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE0_Pos = 0x0
	// Bit mask of EPTYPE0 field.
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE0_Msk = 0x7
	// Position of EPTYPE1 field.
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE1_Pos = 0x4
	// Bit mask of EPTYPE1 field.
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE1_Msk = 0x70
	// Position of NYETDIS field.
	USB_DEVICE_ENDPOINT_EPCFG_NYETDIS_Pos = 0x7
	// Bit mask of NYETDIS field.
	USB_DEVICE_ENDPOINT_EPCFG_NYETDIS_Msk = 0x80
	// Bit NYETDIS.
	USB_DEVICE_ENDPOINT_EPCFG_NYETDIS = 0x80

	// DEVICE_ENDPOINT.EPSTATUSCLR: DEVICE_ENDPOINT End Point Pipe Status Clear
	// Position of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLOUT_Pos = 0x0
	// Bit mask of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLOUT_Msk = 0x1
	// Bit DTGLOUT.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLOUT = 0x1
	// Position of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLIN_Pos = 0x1
	// Bit mask of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLIN_Msk = 0x2
	// Bit DTGLIN.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLIN = 0x2
	// Position of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_CURBK_Pos = 0x2
	// Bit mask of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_CURBK_Msk = 0x4
	// Bit CURBK.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_CURBK = 0x4
	// Position of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ0_Pos = 0x4
	// Bit mask of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ0_Msk = 0x10
	// Bit STALLRQ0.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ0 = 0x10
	// Position of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ1_Pos = 0x5
	// Bit mask of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ1_Msk = 0x20
	// Bit STALLRQ1.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ1 = 0x20
	// Position of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY_Pos = 0x6
	// Bit mask of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY_Msk = 0x40
	// Bit BK0RDY.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY = 0x40
	// Position of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK1RDY_Pos = 0x7
	// Bit mask of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK1RDY_Msk = 0x80
	// Bit BK1RDY.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK1RDY = 0x80

	// DEVICE_ENDPOINT.EPSTATUSSET: DEVICE_ENDPOINT End Point Pipe Status Set
	// Position of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLOUT_Pos = 0x0
	// Bit mask of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLOUT_Msk = 0x1
	// Bit DTGLOUT.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLOUT = 0x1
	// Position of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLIN_Pos = 0x1
	// Bit mask of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLIN_Msk = 0x2
	// Bit DTGLIN.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLIN = 0x2
	// Position of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_CURBK_Pos = 0x2
	// Bit mask of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_CURBK_Msk = 0x4
	// Bit CURBK.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_CURBK = 0x4
	// Position of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ0_Pos = 0x4
	// Bit mask of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ0_Msk = 0x10
	// Bit STALLRQ0.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ0 = 0x10
	// Position of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ1_Pos = 0x5
	// Bit mask of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ1_Msk = 0x20
	// Bit STALLRQ1.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ1 = 0x20
	// Position of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK0RDY_Pos = 0x6
	// Bit mask of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK0RDY_Msk = 0x40
	// Bit BK0RDY.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK0RDY = 0x40
	// Position of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK1RDY_Pos = 0x7
	// Bit mask of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK1RDY_Msk = 0x80
	// Bit BK1RDY.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK1RDY = 0x80

	// DEVICE_ENDPOINT.EPSTATUS: DEVICE_ENDPOINT End Point Pipe Status
	// Position of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLOUT_Pos = 0x0
	// Bit mask of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLOUT_Msk = 0x1
	// Bit DTGLOUT.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLOUT = 0x1
	// Position of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLIN_Pos = 0x1
	// Bit mask of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLIN_Msk = 0x2
	// Bit DTGLIN.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLIN = 0x2
	// Position of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUS_CURBK_Pos = 0x2
	// Bit mask of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUS_CURBK_Msk = 0x4
	// Bit CURBK.
	USB_DEVICE_ENDPOINT_EPSTATUS_CURBK = 0x4
	// Position of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ0_Pos = 0x4
	// Bit mask of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ0_Msk = 0x10
	// Bit STALLRQ0.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ0 = 0x10
	// Position of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ1_Pos = 0x5
	// Bit mask of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ1_Msk = 0x20
	// Bit STALLRQ1.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ1 = 0x20
	// Position of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK0RDY_Pos = 0x6
	// Bit mask of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK0RDY_Msk = 0x40
	// Bit BK0RDY.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK0RDY = 0x40
	// Position of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK1RDY_Pos = 0x7
	// Bit mask of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK1RDY_Msk = 0x80
	// Bit BK1RDY.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK1RDY = 0x80

	// DEVICE_ENDPOINT.EPINTFLAG: DEVICE_ENDPOINT End Point Interrupt Flag
	// Position of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT0_Pos = 0x0
	// Bit mask of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT0_Msk = 0x1
	// Bit TRCPT0.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT0 = 0x1
	// Position of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT1_Pos = 0x1
	// Bit mask of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT1_Msk = 0x2
	// Bit TRCPT1.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT1 = 0x2
	// Position of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL0_Pos = 0x2
	// Bit mask of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL0_Msk = 0x4
	// Bit TRFAIL0.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL0 = 0x4
	// Position of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL1_Pos = 0x3
	// Bit mask of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL1_Msk = 0x8
	// Bit TRFAIL1.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL1 = 0x8
	// Position of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP_Pos = 0x4
	// Bit mask of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP_Msk = 0x10
	// Bit RXSTP.
	USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP = 0x10
	// Position of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL0_Pos = 0x5
	// Bit mask of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL0_Msk = 0x20
	// Bit STALL0.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL0 = 0x20
	// Position of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1_Pos = 0x6
	// Bit mask of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1_Msk = 0x40
	// Bit STALL1.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1 = 0x40

	// DEVICE_ENDPOINT.EPINTENCLR: DEVICE_ENDPOINT End Point Interrupt Clear Flag
	// Position of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT0_Pos = 0x0
	// Bit mask of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT0_Msk = 0x1
	// Bit TRCPT0.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT0 = 0x1
	// Position of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT1_Pos = 0x1
	// Bit mask of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT1_Msk = 0x2
	// Bit TRCPT1.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT1 = 0x2
	// Position of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL0_Pos = 0x2
	// Bit mask of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL0_Msk = 0x4
	// Bit TRFAIL0.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL0 = 0x4
	// Position of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL1_Pos = 0x3
	// Bit mask of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL1_Msk = 0x8
	// Bit TRFAIL1.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL1 = 0x8
	// Position of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_RXSTP_Pos = 0x4
	// Bit mask of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_RXSTP_Msk = 0x10
	// Bit RXSTP.
	USB_DEVICE_ENDPOINT_EPINTENCLR_RXSTP = 0x10
	// Position of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL0_Pos = 0x5
	// Bit mask of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL0_Msk = 0x20
	// Bit STALL0.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL0 = 0x20
	// Position of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL1_Pos = 0x6
	// Bit mask of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL1_Msk = 0x40
	// Bit STALL1.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL1 = 0x40

	// DEVICE_ENDPOINT.EPINTENSET: DEVICE_ENDPOINT End Point Interrupt Set Flag
	// Position of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0_Pos = 0x0
	// Bit mask of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0_Msk = 0x1
	// Bit TRCPT0.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0 = 0x1
	// Position of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1_Pos = 0x1
	// Bit mask of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1_Msk = 0x2
	// Bit TRCPT1.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1 = 0x2
	// Position of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL0_Pos = 0x2
	// Bit mask of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL0_Msk = 0x4
	// Bit TRFAIL0.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL0 = 0x4
	// Position of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL1_Pos = 0x3
	// Bit mask of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL1_Msk = 0x8
	// Bit TRFAIL1.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL1 = 0x8
	// Position of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENSET_RXSTP_Pos = 0x4
	// Bit mask of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENSET_RXSTP_Msk = 0x10
	// Bit RXSTP.
	USB_DEVICE_ENDPOINT_EPINTENSET_RXSTP = 0x10
	// Position of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL0_Pos = 0x5
	// Bit mask of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL0_Msk = 0x20
	// Bit STALL0.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL0 = 0x20
	// Position of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL1_Pos = 0x6
	// Bit mask of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL1_Msk = 0x40
	// Bit STALL1.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL1 = 0x40
)

// Bitfields for USB_HOST: Universal Serial Bus - HOST
const (
	// CTRLA: Control A
	// Position of SWRST field.
	USB_HOST_CTRLA_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	USB_HOST_CTRLA_SWRST_Msk = 0x1
	// Bit SWRST.
	USB_HOST_CTRLA_SWRST = 0x1
	// Position of ENABLE field.
	USB_HOST_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	USB_HOST_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	USB_HOST_CTRLA_ENABLE = 0x2
	// Position of RUNSTDBY field.
	USB_HOST_CTRLA_RUNSTDBY_Pos = 0x2
	// Bit mask of RUNSTDBY field.
	USB_HOST_CTRLA_RUNSTDBY_Msk = 0x4
	// Bit RUNSTDBY.
	USB_HOST_CTRLA_RUNSTDBY = 0x4
	// Position of MODE field.
	USB_HOST_CTRLA_MODE_Pos = 0x7
	// Bit mask of MODE field.
	USB_HOST_CTRLA_MODE_Msk = 0x80
	// Bit MODE.
	USB_HOST_CTRLA_MODE = 0x80
	// Device Mode
	USB_HOST_CTRLA_MODE_DEVICE = 0x0
	// Host Mode
	USB_HOST_CTRLA_MODE_HOST = 0x1

	// SYNCBUSY: Synchronization Busy
	// Position of SWRST field.
	USB_HOST_SYNCBUSY_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	USB_HOST_SYNCBUSY_SWRST_Msk = 0x1
	// Bit SWRST.
	USB_HOST_SYNCBUSY_SWRST = 0x1
	// Position of ENABLE field.
	USB_HOST_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	USB_HOST_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	USB_HOST_SYNCBUSY_ENABLE = 0x2

	// QOSCTRL: USB Quality Of Service
	// Position of CQOS field.
	USB_HOST_QOSCTRL_CQOS_Pos = 0x0
	// Bit mask of CQOS field.
	USB_HOST_QOSCTRL_CQOS_Msk = 0x3
	// Position of DQOS field.
	USB_HOST_QOSCTRL_DQOS_Pos = 0x2
	// Bit mask of DQOS field.
	USB_HOST_QOSCTRL_DQOS_Msk = 0xc

	// CTRLB: HOST Control B
	// Position of RESUME field.
	USB_HOST_CTRLB_RESUME_Pos = 0x1
	// Bit mask of RESUME field.
	USB_HOST_CTRLB_RESUME_Msk = 0x2
	// Bit RESUME.
	USB_HOST_CTRLB_RESUME = 0x2
	// Position of SPDCONF field.
	USB_HOST_CTRLB_SPDCONF_Pos = 0x2
	// Bit mask of SPDCONF field.
	USB_HOST_CTRLB_SPDCONF_Msk = 0xc
	// Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.
	USB_HOST_CTRLB_SPDCONF_NORMAL = 0x0
	// Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.
	USB_HOST_CTRLB_SPDCONF_FS = 0x3
	// Position of AUTORESUME field.
	USB_HOST_CTRLB_AUTORESUME_Pos = 0x4
	// Bit mask of AUTORESUME field.
	USB_HOST_CTRLB_AUTORESUME_Msk = 0x10
	// Bit AUTORESUME.
	USB_HOST_CTRLB_AUTORESUME = 0x10
	// Position of TSTJ field.
	USB_HOST_CTRLB_TSTJ_Pos = 0x5
	// Bit mask of TSTJ field.
	USB_HOST_CTRLB_TSTJ_Msk = 0x20
	// Bit TSTJ.
	USB_HOST_CTRLB_TSTJ = 0x20
	// Position of TSTK field.
	USB_HOST_CTRLB_TSTK_Pos = 0x6
	// Bit mask of TSTK field.
	USB_HOST_CTRLB_TSTK_Msk = 0x40
	// Bit TSTK.
	USB_HOST_CTRLB_TSTK = 0x40
	// Position of SOFE field.
	USB_HOST_CTRLB_SOFE_Pos = 0x8
	// Bit mask of SOFE field.
	USB_HOST_CTRLB_SOFE_Msk = 0x100
	// Bit SOFE.
	USB_HOST_CTRLB_SOFE = 0x100
	// Position of BUSRESET field.
	USB_HOST_CTRLB_BUSRESET_Pos = 0x9
	// Bit mask of BUSRESET field.
	USB_HOST_CTRLB_BUSRESET_Msk = 0x200
	// Bit BUSRESET.
	USB_HOST_CTRLB_BUSRESET = 0x200
	// Position of VBUSOK field.
	USB_HOST_CTRLB_VBUSOK_Pos = 0xa
	// Bit mask of VBUSOK field.
	USB_HOST_CTRLB_VBUSOK_Msk = 0x400
	// Bit VBUSOK.
	USB_HOST_CTRLB_VBUSOK = 0x400
	// Position of L1RESUME field.
	USB_HOST_CTRLB_L1RESUME_Pos = 0xb
	// Bit mask of L1RESUME field.
	USB_HOST_CTRLB_L1RESUME_Msk = 0x800
	// Bit L1RESUME.
	USB_HOST_CTRLB_L1RESUME = 0x800

	// HSOFC: HOST Host Start Of Frame Control
	// Position of FLENC field.
	USB_HOST_HSOFC_FLENC_Pos = 0x0
	// Bit mask of FLENC field.
	USB_HOST_HSOFC_FLENC_Msk = 0xf
	// Position of FLENCE field.
	USB_HOST_HSOFC_FLENCE_Pos = 0x7
	// Bit mask of FLENCE field.
	USB_HOST_HSOFC_FLENCE_Msk = 0x80
	// Bit FLENCE.
	USB_HOST_HSOFC_FLENCE = 0x80

	// STATUS: HOST Status
	// Position of SPEED field.
	USB_HOST_STATUS_SPEED_Pos = 0x2
	// Bit mask of SPEED field.
	USB_HOST_STATUS_SPEED_Msk = 0xc
	// Position of LINESTATE field.
	USB_HOST_STATUS_LINESTATE_Pos = 0x6
	// Bit mask of LINESTATE field.
	USB_HOST_STATUS_LINESTATE_Msk = 0xc0

	// FSMSTATUS: Finite State Machine Status
	// Position of FSMSTATE field.
	USB_HOST_FSMSTATUS_FSMSTATE_Pos = 0x0
	// Bit mask of FSMSTATE field.
	USB_HOST_FSMSTATUS_FSMSTATE_Msk = 0x7f
	// OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
	USB_HOST_FSMSTATUS_FSMSTATE_OFF = 0x1
	// ON (L0). It corresponds to the Idle and Active states
	USB_HOST_FSMSTATUS_FSMSTATE_ON = 0x2
	// SUSPEND (L2)
	USB_HOST_FSMSTATUS_FSMSTATE_SUSPEND = 0x4
	// SLEEP (L1)
	USB_HOST_FSMSTATUS_FSMSTATE_SLEEP = 0x8
	// DNRESUME. Down Stream Resume.
	USB_HOST_FSMSTATUS_FSMSTATE_DNRESUME = 0x10
	// UPRESUME. Up Stream Resume.
	USB_HOST_FSMSTATUS_FSMSTATE_UPRESUME = 0x20
	// RESET. USB lines Reset.
	USB_HOST_FSMSTATUS_FSMSTATE_RESET = 0x40

	// FNUM: HOST Host Frame Number
	// Position of MFNUM field.
	USB_HOST_FNUM_MFNUM_Pos = 0x0
	// Bit mask of MFNUM field.
	USB_HOST_FNUM_MFNUM_Msk = 0x7
	// Position of FNUM field.
	USB_HOST_FNUM_FNUM_Pos = 0x3
	// Bit mask of FNUM field.
	USB_HOST_FNUM_FNUM_Msk = 0x3ff8

	// FLENHIGH: HOST Host Frame Length
	// Position of FLENHIGH field.
	USB_HOST_FLENHIGH_FLENHIGH_Pos = 0x0
	// Bit mask of FLENHIGH field.
	USB_HOST_FLENHIGH_FLENHIGH_Msk = 0xff

	// INTENCLR: HOST Host Interrupt Enable Clear
	// Position of HSOF field.
	USB_HOST_INTENCLR_HSOF_Pos = 0x2
	// Bit mask of HSOF field.
	USB_HOST_INTENCLR_HSOF_Msk = 0x4
	// Bit HSOF.
	USB_HOST_INTENCLR_HSOF = 0x4
	// Position of RST field.
	USB_HOST_INTENCLR_RST_Pos = 0x3
	// Bit mask of RST field.
	USB_HOST_INTENCLR_RST_Msk = 0x8
	// Bit RST.
	USB_HOST_INTENCLR_RST = 0x8
	// Position of WAKEUP field.
	USB_HOST_INTENCLR_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	USB_HOST_INTENCLR_WAKEUP_Msk = 0x10
	// Bit WAKEUP.
	USB_HOST_INTENCLR_WAKEUP = 0x10
	// Position of DNRSM field.
	USB_HOST_INTENCLR_DNRSM_Pos = 0x5
	// Bit mask of DNRSM field.
	USB_HOST_INTENCLR_DNRSM_Msk = 0x20
	// Bit DNRSM.
	USB_HOST_INTENCLR_DNRSM = 0x20
	// Position of UPRSM field.
	USB_HOST_INTENCLR_UPRSM_Pos = 0x6
	// Bit mask of UPRSM field.
	USB_HOST_INTENCLR_UPRSM_Msk = 0x40
	// Bit UPRSM.
	USB_HOST_INTENCLR_UPRSM = 0x40
	// Position of RAMACER field.
	USB_HOST_INTENCLR_RAMACER_Pos = 0x7
	// Bit mask of RAMACER field.
	USB_HOST_INTENCLR_RAMACER_Msk = 0x80
	// Bit RAMACER.
	USB_HOST_INTENCLR_RAMACER = 0x80
	// Position of DCONN field.
	USB_HOST_INTENCLR_DCONN_Pos = 0x8
	// Bit mask of DCONN field.
	USB_HOST_INTENCLR_DCONN_Msk = 0x100
	// Bit DCONN.
	USB_HOST_INTENCLR_DCONN = 0x100
	// Position of DDISC field.
	USB_HOST_INTENCLR_DDISC_Pos = 0x9
	// Bit mask of DDISC field.
	USB_HOST_INTENCLR_DDISC_Msk = 0x200
	// Bit DDISC.
	USB_HOST_INTENCLR_DDISC = 0x200

	// INTENSET: HOST Host Interrupt Enable Set
	// Position of HSOF field.
	USB_HOST_INTENSET_HSOF_Pos = 0x2
	// Bit mask of HSOF field.
	USB_HOST_INTENSET_HSOF_Msk = 0x4
	// Bit HSOF.
	USB_HOST_INTENSET_HSOF = 0x4
	// Position of RST field.
	USB_HOST_INTENSET_RST_Pos = 0x3
	// Bit mask of RST field.
	USB_HOST_INTENSET_RST_Msk = 0x8
	// Bit RST.
	USB_HOST_INTENSET_RST = 0x8
	// Position of WAKEUP field.
	USB_HOST_INTENSET_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	USB_HOST_INTENSET_WAKEUP_Msk = 0x10
	// Bit WAKEUP.
	USB_HOST_INTENSET_WAKEUP = 0x10
	// Position of DNRSM field.
	USB_HOST_INTENSET_DNRSM_Pos = 0x5
	// Bit mask of DNRSM field.
	USB_HOST_INTENSET_DNRSM_Msk = 0x20
	// Bit DNRSM.
	USB_HOST_INTENSET_DNRSM = 0x20
	// Position of UPRSM field.
	USB_HOST_INTENSET_UPRSM_Pos = 0x6
	// Bit mask of UPRSM field.
	USB_HOST_INTENSET_UPRSM_Msk = 0x40
	// Bit UPRSM.
	USB_HOST_INTENSET_UPRSM = 0x40
	// Position of RAMACER field.
	USB_HOST_INTENSET_RAMACER_Pos = 0x7
	// Bit mask of RAMACER field.
	USB_HOST_INTENSET_RAMACER_Msk = 0x80
	// Bit RAMACER.
	USB_HOST_INTENSET_RAMACER = 0x80
	// Position of DCONN field.
	USB_HOST_INTENSET_DCONN_Pos = 0x8
	// Bit mask of DCONN field.
	USB_HOST_INTENSET_DCONN_Msk = 0x100
	// Bit DCONN.
	USB_HOST_INTENSET_DCONN = 0x100
	// Position of DDISC field.
	USB_HOST_INTENSET_DDISC_Pos = 0x9
	// Bit mask of DDISC field.
	USB_HOST_INTENSET_DDISC_Msk = 0x200
	// Bit DDISC.
	USB_HOST_INTENSET_DDISC = 0x200

	// INTFLAG: HOST Host Interrupt Flag
	// Position of HSOF field.
	USB_HOST_INTFLAG_HSOF_Pos = 0x2
	// Bit mask of HSOF field.
	USB_HOST_INTFLAG_HSOF_Msk = 0x4
	// Bit HSOF.
	USB_HOST_INTFLAG_HSOF = 0x4
	// Position of RST field.
	USB_HOST_INTFLAG_RST_Pos = 0x3
	// Bit mask of RST field.
	USB_HOST_INTFLAG_RST_Msk = 0x8
	// Bit RST.
	USB_HOST_INTFLAG_RST = 0x8
	// Position of WAKEUP field.
	USB_HOST_INTFLAG_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	USB_HOST_INTFLAG_WAKEUP_Msk = 0x10
	// Bit WAKEUP.
	USB_HOST_INTFLAG_WAKEUP = 0x10
	// Position of DNRSM field.
	USB_HOST_INTFLAG_DNRSM_Pos = 0x5
	// Bit mask of DNRSM field.
	USB_HOST_INTFLAG_DNRSM_Msk = 0x20
	// Bit DNRSM.
	USB_HOST_INTFLAG_DNRSM = 0x20
	// Position of UPRSM field.
	USB_HOST_INTFLAG_UPRSM_Pos = 0x6
	// Bit mask of UPRSM field.
	USB_HOST_INTFLAG_UPRSM_Msk = 0x40
	// Bit UPRSM.
	USB_HOST_INTFLAG_UPRSM = 0x40
	// Position of RAMACER field.
	USB_HOST_INTFLAG_RAMACER_Pos = 0x7
	// Bit mask of RAMACER field.
	USB_HOST_INTFLAG_RAMACER_Msk = 0x80
	// Bit RAMACER.
	USB_HOST_INTFLAG_RAMACER = 0x80
	// Position of DCONN field.
	USB_HOST_INTFLAG_DCONN_Pos = 0x8
	// Bit mask of DCONN field.
	USB_HOST_INTFLAG_DCONN_Msk = 0x100
	// Bit DCONN.
	USB_HOST_INTFLAG_DCONN = 0x100
	// Position of DDISC field.
	USB_HOST_INTFLAG_DDISC_Pos = 0x9
	// Bit mask of DDISC field.
	USB_HOST_INTFLAG_DDISC_Msk = 0x200
	// Bit DDISC.
	USB_HOST_INTFLAG_DDISC = 0x200

	// PINTSMRY: HOST Pipe Interrupt Summary
	// Position of EPINT0 field.
	USB_HOST_PINTSMRY_EPINT0_Pos = 0x0
	// Bit mask of EPINT0 field.
	USB_HOST_PINTSMRY_EPINT0_Msk = 0x1
	// Bit EPINT0.
	USB_HOST_PINTSMRY_EPINT0 = 0x1
	// Position of EPINT1 field.
	USB_HOST_PINTSMRY_EPINT1_Pos = 0x1
	// Bit mask of EPINT1 field.
	USB_HOST_PINTSMRY_EPINT1_Msk = 0x2
	// Bit EPINT1.
	USB_HOST_PINTSMRY_EPINT1 = 0x2
	// Position of EPINT2 field.
	USB_HOST_PINTSMRY_EPINT2_Pos = 0x2
	// Bit mask of EPINT2 field.
	USB_HOST_PINTSMRY_EPINT2_Msk = 0x4
	// Bit EPINT2.
	USB_HOST_PINTSMRY_EPINT2 = 0x4
	// Position of EPINT3 field.
	USB_HOST_PINTSMRY_EPINT3_Pos = 0x3
	// Bit mask of EPINT3 field.
	USB_HOST_PINTSMRY_EPINT3_Msk = 0x8
	// Bit EPINT3.
	USB_HOST_PINTSMRY_EPINT3 = 0x8
	// Position of EPINT4 field.
	USB_HOST_PINTSMRY_EPINT4_Pos = 0x4
	// Bit mask of EPINT4 field.
	USB_HOST_PINTSMRY_EPINT4_Msk = 0x10
	// Bit EPINT4.
	USB_HOST_PINTSMRY_EPINT4 = 0x10
	// Position of EPINT5 field.
	USB_HOST_PINTSMRY_EPINT5_Pos = 0x5
	// Bit mask of EPINT5 field.
	USB_HOST_PINTSMRY_EPINT5_Msk = 0x20
	// Bit EPINT5.
	USB_HOST_PINTSMRY_EPINT5 = 0x20
	// Position of EPINT6 field.
	USB_HOST_PINTSMRY_EPINT6_Pos = 0x6
	// Bit mask of EPINT6 field.
	USB_HOST_PINTSMRY_EPINT6_Msk = 0x40
	// Bit EPINT6.
	USB_HOST_PINTSMRY_EPINT6 = 0x40
	// Position of EPINT7 field.
	USB_HOST_PINTSMRY_EPINT7_Pos = 0x7
	// Bit mask of EPINT7 field.
	USB_HOST_PINTSMRY_EPINT7_Msk = 0x80
	// Bit EPINT7.
	USB_HOST_PINTSMRY_EPINT7 = 0x80

	// DESCADD: Descriptor Address
	// Position of DESCADD field.
	USB_HOST_DESCADD_DESCADD_Pos = 0x0
	// Bit mask of DESCADD field.
	USB_HOST_DESCADD_DESCADD_Msk = 0xffffffff

	// PADCAL: USB PAD Calibration
	// Position of TRANSP field.
	USB_HOST_PADCAL_TRANSP_Pos = 0x0
	// Bit mask of TRANSP field.
	USB_HOST_PADCAL_TRANSP_Msk = 0x1f
	// Position of TRANSN field.
	USB_HOST_PADCAL_TRANSN_Pos = 0x6
	// Bit mask of TRANSN field.
	USB_HOST_PADCAL_TRANSN_Msk = 0x7c0
	// Position of TRIM field.
	USB_HOST_PADCAL_TRIM_Pos = 0xc
	// Bit mask of TRIM field.
	USB_HOST_PADCAL_TRIM_Msk = 0x7000

	// HOST_PIPE.PCFG: HOST_PIPE End Point Configuration
	// Position of PTOKEN field.
	USB_HOST_PIPE_PCFG_PTOKEN_Pos = 0x0
	// Bit mask of PTOKEN field.
	USB_HOST_PIPE_PCFG_PTOKEN_Msk = 0x3
	// Position of BK field.
	USB_HOST_PIPE_PCFG_BK_Pos = 0x2
	// Bit mask of BK field.
	USB_HOST_PIPE_PCFG_BK_Msk = 0x4
	// Bit BK.
	USB_HOST_PIPE_PCFG_BK = 0x4
	// Position of PTYPE field.
	USB_HOST_PIPE_PCFG_PTYPE_Pos = 0x3
	// Bit mask of PTYPE field.
	USB_HOST_PIPE_PCFG_PTYPE_Msk = 0x38

	// HOST_PIPE.BINTERVAL: HOST_PIPE Bus Access Period of Pipe
	// Position of BITINTERVAL field.
	USB_HOST_PIPE_BINTERVAL_BITINTERVAL_Pos = 0x0
	// Bit mask of BITINTERVAL field.
	USB_HOST_PIPE_BINTERVAL_BITINTERVAL_Msk = 0xff

	// HOST_PIPE.PSTATUSCLR: HOST_PIPE End Point Pipe Status Clear
	// Position of DTGL field.
	USB_HOST_PIPE_PSTATUSCLR_DTGL_Pos = 0x0
	// Bit mask of DTGL field.
	USB_HOST_PIPE_PSTATUSCLR_DTGL_Msk = 0x1
	// Bit DTGL.
	USB_HOST_PIPE_PSTATUSCLR_DTGL = 0x1
	// Position of CURBK field.
	USB_HOST_PIPE_PSTATUSCLR_CURBK_Pos = 0x2
	// Bit mask of CURBK field.
	USB_HOST_PIPE_PSTATUSCLR_CURBK_Msk = 0x4
	// Bit CURBK.
	USB_HOST_PIPE_PSTATUSCLR_CURBK = 0x4
	// Position of PFREEZE field.
	USB_HOST_PIPE_PSTATUSCLR_PFREEZE_Pos = 0x4
	// Bit mask of PFREEZE field.
	USB_HOST_PIPE_PSTATUSCLR_PFREEZE_Msk = 0x10
	// Bit PFREEZE.
	USB_HOST_PIPE_PSTATUSCLR_PFREEZE = 0x10
	// Position of BK0RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK0RDY_Pos = 0x6
	// Bit mask of BK0RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK0RDY_Msk = 0x40
	// Bit BK0RDY.
	USB_HOST_PIPE_PSTATUSCLR_BK0RDY = 0x40
	// Position of BK1RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK1RDY_Pos = 0x7
	// Bit mask of BK1RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK1RDY_Msk = 0x80
	// Bit BK1RDY.
	USB_HOST_PIPE_PSTATUSCLR_BK1RDY = 0x80

	// HOST_PIPE.PSTATUSSET: HOST_PIPE End Point Pipe Status Set
	// Position of DTGL field.
	USB_HOST_PIPE_PSTATUSSET_DTGL_Pos = 0x0
	// Bit mask of DTGL field.
	USB_HOST_PIPE_PSTATUSSET_DTGL_Msk = 0x1
	// Bit DTGL.
	USB_HOST_PIPE_PSTATUSSET_DTGL = 0x1
	// Position of CURBK field.
	USB_HOST_PIPE_PSTATUSSET_CURBK_Pos = 0x2
	// Bit mask of CURBK field.
	USB_HOST_PIPE_PSTATUSSET_CURBK_Msk = 0x4
	// Bit CURBK.
	USB_HOST_PIPE_PSTATUSSET_CURBK = 0x4
	// Position of PFREEZE field.
	USB_HOST_PIPE_PSTATUSSET_PFREEZE_Pos = 0x4
	// Bit mask of PFREEZE field.
	USB_HOST_PIPE_PSTATUSSET_PFREEZE_Msk = 0x10
	// Bit PFREEZE.
	USB_HOST_PIPE_PSTATUSSET_PFREEZE = 0x10
	// Position of BK0RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK0RDY_Pos = 0x6
	// Bit mask of BK0RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK0RDY_Msk = 0x40
	// Bit BK0RDY.
	USB_HOST_PIPE_PSTATUSSET_BK0RDY = 0x40
	// Position of BK1RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK1RDY_Pos = 0x7
	// Bit mask of BK1RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK1RDY_Msk = 0x80
	// Bit BK1RDY.
	USB_HOST_PIPE_PSTATUSSET_BK1RDY = 0x80

	// HOST_PIPE.PSTATUS: HOST_PIPE End Point Pipe Status
	// Position of DTGL field.
	USB_HOST_PIPE_PSTATUS_DTGL_Pos = 0x0
	// Bit mask of DTGL field.
	USB_HOST_PIPE_PSTATUS_DTGL_Msk = 0x1
	// Bit DTGL.
	USB_HOST_PIPE_PSTATUS_DTGL = 0x1
	// Position of CURBK field.
	USB_HOST_PIPE_PSTATUS_CURBK_Pos = 0x2
	// Bit mask of CURBK field.
	USB_HOST_PIPE_PSTATUS_CURBK_Msk = 0x4
	// Bit CURBK.
	USB_HOST_PIPE_PSTATUS_CURBK = 0x4
	// Position of PFREEZE field.
	USB_HOST_PIPE_PSTATUS_PFREEZE_Pos = 0x4
	// Bit mask of PFREEZE field.
	USB_HOST_PIPE_PSTATUS_PFREEZE_Msk = 0x10
	// Bit PFREEZE.
	USB_HOST_PIPE_PSTATUS_PFREEZE = 0x10
	// Position of BK0RDY field.
	USB_HOST_PIPE_PSTATUS_BK0RDY_Pos = 0x6
	// Bit mask of BK0RDY field.
	USB_HOST_PIPE_PSTATUS_BK0RDY_Msk = 0x40
	// Bit BK0RDY.
	USB_HOST_PIPE_PSTATUS_BK0RDY = 0x40
	// Position of BK1RDY field.
	USB_HOST_PIPE_PSTATUS_BK1RDY_Pos = 0x7
	// Bit mask of BK1RDY field.
	USB_HOST_PIPE_PSTATUS_BK1RDY_Msk = 0x80
	// Bit BK1RDY.
	USB_HOST_PIPE_PSTATUS_BK1RDY = 0x80

	// HOST_PIPE.PINTFLAG: HOST_PIPE Pipe Interrupt Flag
	// Position of TRCPT0 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT0_Pos = 0x0
	// Bit mask of TRCPT0 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT0_Msk = 0x1
	// Bit TRCPT0.
	USB_HOST_PIPE_PINTFLAG_TRCPT0 = 0x1
	// Position of TRCPT1 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT1_Pos = 0x1
	// Bit mask of TRCPT1 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT1_Msk = 0x2
	// Bit TRCPT1.
	USB_HOST_PIPE_PINTFLAG_TRCPT1 = 0x2
	// Position of TRFAIL field.
	USB_HOST_PIPE_PINTFLAG_TRFAIL_Pos = 0x2
	// Bit mask of TRFAIL field.
	USB_HOST_PIPE_PINTFLAG_TRFAIL_Msk = 0x4
	// Bit TRFAIL.
	USB_HOST_PIPE_PINTFLAG_TRFAIL = 0x4
	// Position of PERR field.
	USB_HOST_PIPE_PINTFLAG_PERR_Pos = 0x3
	// Bit mask of PERR field.
	USB_HOST_PIPE_PINTFLAG_PERR_Msk = 0x8
	// Bit PERR.
	USB_HOST_PIPE_PINTFLAG_PERR = 0x8
	// Position of TXSTP field.
	USB_HOST_PIPE_PINTFLAG_TXSTP_Pos = 0x4
	// Bit mask of TXSTP field.
	USB_HOST_PIPE_PINTFLAG_TXSTP_Msk = 0x10
	// Bit TXSTP.
	USB_HOST_PIPE_PINTFLAG_TXSTP = 0x10
	// Position of STALL field.
	USB_HOST_PIPE_PINTFLAG_STALL_Pos = 0x5
	// Bit mask of STALL field.
	USB_HOST_PIPE_PINTFLAG_STALL_Msk = 0x20
	// Bit STALL.
	USB_HOST_PIPE_PINTFLAG_STALL = 0x20

	// HOST_PIPE.PINTENCLR: HOST_PIPE Pipe Interrupt Flag Clear
	// Position of TRCPT0 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT0_Pos = 0x0
	// Bit mask of TRCPT0 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT0_Msk = 0x1
	// Bit TRCPT0.
	USB_HOST_PIPE_PINTENCLR_TRCPT0 = 0x1
	// Position of TRCPT1 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT1_Pos = 0x1
	// Bit mask of TRCPT1 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT1_Msk = 0x2
	// Bit TRCPT1.
	USB_HOST_PIPE_PINTENCLR_TRCPT1 = 0x2
	// Position of TRFAIL field.
	USB_HOST_PIPE_PINTENCLR_TRFAIL_Pos = 0x2
	// Bit mask of TRFAIL field.
	USB_HOST_PIPE_PINTENCLR_TRFAIL_Msk = 0x4
	// Bit TRFAIL.
	USB_HOST_PIPE_PINTENCLR_TRFAIL = 0x4
	// Position of PERR field.
	USB_HOST_PIPE_PINTENCLR_PERR_Pos = 0x3
	// Bit mask of PERR field.
	USB_HOST_PIPE_PINTENCLR_PERR_Msk = 0x8
	// Bit PERR.
	USB_HOST_PIPE_PINTENCLR_PERR = 0x8
	// Position of TXSTP field.
	USB_HOST_PIPE_PINTENCLR_TXSTP_Pos = 0x4
	// Bit mask of TXSTP field.
	USB_HOST_PIPE_PINTENCLR_TXSTP_Msk = 0x10
	// Bit TXSTP.
	USB_HOST_PIPE_PINTENCLR_TXSTP = 0x10
	// Position of STALL field.
	USB_HOST_PIPE_PINTENCLR_STALL_Pos = 0x5
	// Bit mask of STALL field.
	USB_HOST_PIPE_PINTENCLR_STALL_Msk = 0x20
	// Bit STALL.
	USB_HOST_PIPE_PINTENCLR_STALL = 0x20

	// HOST_PIPE.PINTENSET: HOST_PIPE Pipe Interrupt Flag Set
	// Position of TRCPT0 field.
	USB_HOST_PIPE_PINTENSET_TRCPT0_Pos = 0x0
	// Bit mask of TRCPT0 field.
	USB_HOST_PIPE_PINTENSET_TRCPT0_Msk = 0x1
	// Bit TRCPT0.
	USB_HOST_PIPE_PINTENSET_TRCPT0 = 0x1
	// Position of TRCPT1 field.
	USB_HOST_PIPE_PINTENSET_TRCPT1_Pos = 0x1
	// Bit mask of TRCPT1 field.
	USB_HOST_PIPE_PINTENSET_TRCPT1_Msk = 0x2
	// Bit TRCPT1.
	USB_HOST_PIPE_PINTENSET_TRCPT1 = 0x2
	// Position of TRFAIL field.
	USB_HOST_PIPE_PINTENSET_TRFAIL_Pos = 0x2
	// Bit mask of TRFAIL field.
	USB_HOST_PIPE_PINTENSET_TRFAIL_Msk = 0x4
	// Bit TRFAIL.
	USB_HOST_PIPE_PINTENSET_TRFAIL = 0x4
	// Position of PERR field.
	USB_HOST_PIPE_PINTENSET_PERR_Pos = 0x3
	// Bit mask of PERR field.
	USB_HOST_PIPE_PINTENSET_PERR_Msk = 0x8
	// Bit PERR.
	USB_HOST_PIPE_PINTENSET_PERR = 0x8
	// Position of TXSTP field.
	USB_HOST_PIPE_PINTENSET_TXSTP_Pos = 0x4
	// Bit mask of TXSTP field.
	USB_HOST_PIPE_PINTENSET_TXSTP_Msk = 0x10
	// Bit TXSTP.
	USB_HOST_PIPE_PINTENSET_TXSTP = 0x10
	// Position of STALL field.
	USB_HOST_PIPE_PINTENSET_STALL_Pos = 0x5
	// Bit mask of STALL field.
	USB_HOST_PIPE_PINTENSET_STALL_Msk = 0x20
	// Bit STALL.
	USB_HOST_PIPE_PINTENSET_STALL = 0x20
)

// Bitfields for WDT: Watchdog Timer
const (
	// CTRLA: Control
	// Position of ENABLE field.
	WDT_CTRLA_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	WDT_CTRLA_ENABLE_Msk = 0x2
	// Bit ENABLE.
	WDT_CTRLA_ENABLE = 0x2
	// Position of WEN field.
	WDT_CTRLA_WEN_Pos = 0x2
	// Bit mask of WEN field.
	WDT_CTRLA_WEN_Msk = 0x4
	// Bit WEN.
	WDT_CTRLA_WEN = 0x4
	// Position of ALWAYSON field.
	WDT_CTRLA_ALWAYSON_Pos = 0x7
	// Bit mask of ALWAYSON field.
	WDT_CTRLA_ALWAYSON_Msk = 0x80
	// Bit ALWAYSON.
	WDT_CTRLA_ALWAYSON = 0x80

	// CONFIG: Configuration
	// Position of PER field.
	WDT_CONFIG_PER_Pos = 0x0
	// Bit mask of PER field.
	WDT_CONFIG_PER_Msk = 0xf
	// 8 clock cycles
	WDT_CONFIG_PER_CYC8 = 0x0
	// 16 clock cycles
	WDT_CONFIG_PER_CYC16 = 0x1
	// 32 clock cycles
	WDT_CONFIG_PER_CYC32 = 0x2
	// 64 clock cycles
	WDT_CONFIG_PER_CYC64 = 0x3
	// 128 clock cycles
	WDT_CONFIG_PER_CYC128 = 0x4
	// 256 clock cycles
	WDT_CONFIG_PER_CYC256 = 0x5
	// 512 clock cycles
	WDT_CONFIG_PER_CYC512 = 0x6
	// 1024 clock cycles
	WDT_CONFIG_PER_CYC1024 = 0x7
	// 2048 clock cycles
	WDT_CONFIG_PER_CYC2048 = 0x8
	// 4096 clock cycles
	WDT_CONFIG_PER_CYC4096 = 0x9
	// 8192 clock cycles
	WDT_CONFIG_PER_CYC8192 = 0xa
	// 16384 clock cycles
	WDT_CONFIG_PER_CYC16384 = 0xb
	// Position of WINDOW field.
	WDT_CONFIG_WINDOW_Pos = 0x4
	// Bit mask of WINDOW field.
	WDT_CONFIG_WINDOW_Msk = 0xf0
	// 8 clock cycles
	WDT_CONFIG_WINDOW_CYC8 = 0x0
	// 16 clock cycles
	WDT_CONFIG_WINDOW_CYC16 = 0x1
	// 32 clock cycles
	WDT_CONFIG_WINDOW_CYC32 = 0x2
	// 64 clock cycles
	WDT_CONFIG_WINDOW_CYC64 = 0x3
	// 128 clock cycles
	WDT_CONFIG_WINDOW_CYC128 = 0x4
	// 256 clock cycles
	WDT_CONFIG_WINDOW_CYC256 = 0x5
	// 512 clock cycles
	WDT_CONFIG_WINDOW_CYC512 = 0x6
	// 1024 clock cycles
	WDT_CONFIG_WINDOW_CYC1024 = 0x7
	// 2048 clock cycles
	WDT_CONFIG_WINDOW_CYC2048 = 0x8
	// 4096 clock cycles
	WDT_CONFIG_WINDOW_CYC4096 = 0x9
	// 8192 clock cycles
	WDT_CONFIG_WINDOW_CYC8192 = 0xa
	// 16384 clock cycles
	WDT_CONFIG_WINDOW_CYC16384 = 0xb

	// EWCTRL: Early Warning Interrupt Control
	// Position of EWOFFSET field.
	WDT_EWCTRL_EWOFFSET_Pos = 0x0
	// Bit mask of EWOFFSET field.
	WDT_EWCTRL_EWOFFSET_Msk = 0xf
	// 8 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC8 = 0x0
	// 16 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC16 = 0x1
	// 32 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC32 = 0x2
	// 64 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC64 = 0x3
	// 128 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC128 = 0x4
	// 256 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC256 = 0x5
	// 512 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC512 = 0x6
	// 1024 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC1024 = 0x7
	// 2048 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC2048 = 0x8
	// 4096 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC4096 = 0x9
	// 8192 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC8192 = 0xa
	// 16384 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC16384 = 0xb

	// INTENCLR: Interrupt Enable Clear
	// Position of EW field.
	WDT_INTENCLR_EW_Pos = 0x0
	// Bit mask of EW field.
	WDT_INTENCLR_EW_Msk = 0x1
	// Bit EW.
	WDT_INTENCLR_EW = 0x1

	// INTENSET: Interrupt Enable Set
	// Position of EW field.
	WDT_INTENSET_EW_Pos = 0x0
	// Bit mask of EW field.
	WDT_INTENSET_EW_Msk = 0x1
	// Bit EW.
	WDT_INTENSET_EW = 0x1

	// INTFLAG: Interrupt Flag Status and Clear
	// Position of EW field.
	WDT_INTFLAG_EW_Pos = 0x0
	// Bit mask of EW field.
	WDT_INTFLAG_EW_Msk = 0x1
	// Bit EW.
	WDT_INTFLAG_EW = 0x1

	// SYNCBUSY: Synchronization Busy
	// Position of ENABLE field.
	WDT_SYNCBUSY_ENABLE_Pos = 0x1
	// Bit mask of ENABLE field.
	WDT_SYNCBUSY_ENABLE_Msk = 0x2
	// Bit ENABLE.
	WDT_SYNCBUSY_ENABLE = 0x2
	// Position of WEN field.
	WDT_SYNCBUSY_WEN_Pos = 0x2
	// Bit mask of WEN field.
	WDT_SYNCBUSY_WEN_Msk = 0x4
	// Bit WEN.
	WDT_SYNCBUSY_WEN = 0x4
	// Position of ALWAYSON field.
	WDT_SYNCBUSY_ALWAYSON_Pos = 0x3
	// Bit mask of ALWAYSON field.
	WDT_SYNCBUSY_ALWAYSON_Msk = 0x8
	// Bit ALWAYSON.
	WDT_SYNCBUSY_ALWAYSON = 0x8
	// Position of CLEAR field.
	WDT_SYNCBUSY_CLEAR_Pos = 0x4
	// Bit mask of CLEAR field.
	WDT_SYNCBUSY_CLEAR_Msk = 0x10
	// Bit CLEAR.
	WDT_SYNCBUSY_CLEAR = 0x10

	// CLEAR: Clear
	// Position of CLEAR field.
	WDT_CLEAR_CLEAR_Pos = 0x0
	// Bit mask of CLEAR field.
	WDT_CLEAR_CLEAR_Msk = 0xff
	// Clear Key
	WDT_CLEAR_CLEAR_KEY = 0xa5
)

// Bitfields for CoreDebug: Core Debug Register
const (
	// DHCSR: Debug Halting Control and Status Register
	// Position of C_DEBUGEN field.
	CoreDebug_DHCSR_C_DEBUGEN_Pos = 0x0
	// Bit mask of C_DEBUGEN field.
	CoreDebug_DHCSR_C_DEBUGEN_Msk = 0x1
	// Bit C_DEBUGEN.
	CoreDebug_DHCSR_C_DEBUGEN = 0x1
	// Position of C_HALT field.
	CoreDebug_DHCSR_C_HALT_Pos = 0x1
	// Bit mask of C_HALT field.
	CoreDebug_DHCSR_C_HALT_Msk = 0x2
	// Bit C_HALT.
	CoreDebug_DHCSR_C_HALT = 0x2
	// Position of C_STEP field.
	CoreDebug_DHCSR_C_STEP_Pos = 0x2
	// Bit mask of C_STEP field.
	CoreDebug_DHCSR_C_STEP_Msk = 0x4
	// Bit C_STEP.
	CoreDebug_DHCSR_C_STEP = 0x4
	// Position of C_MASKINTS field.
	CoreDebug_DHCSR_C_MASKINTS_Pos = 0x3
	// Bit mask of C_MASKINTS field.
	CoreDebug_DHCSR_C_MASKINTS_Msk = 0x8
	// Bit C_MASKINTS.
	CoreDebug_DHCSR_C_MASKINTS = 0x8
	// Position of C_SNAPSTALL field.
	CoreDebug_DHCSR_C_SNAPSTALL_Pos = 0x5
	// Bit mask of C_SNAPSTALL field.
	CoreDebug_DHCSR_C_SNAPSTALL_Msk = 0x20
	// Bit C_SNAPSTALL.
	CoreDebug_DHCSR_C_SNAPSTALL = 0x20
	// Position of S_REGRDY field.
	CoreDebug_DHCSR_S_REGRDY_Pos = 0x10
	// Bit mask of S_REGRDY field.
	CoreDebug_DHCSR_S_REGRDY_Msk = 0x10000
	// Bit S_REGRDY.
	CoreDebug_DHCSR_S_REGRDY = 0x10000
	// Position of S_HALT field.
	CoreDebug_DHCSR_S_HALT_Pos = 0x11
	// Bit mask of S_HALT field.
	CoreDebug_DHCSR_S_HALT_Msk = 0x20000
	// Bit S_HALT.
	CoreDebug_DHCSR_S_HALT = 0x20000
	// Position of S_SLEEP field.
	CoreDebug_DHCSR_S_SLEEP_Pos = 0x12
	// Bit mask of S_SLEEP field.
	CoreDebug_DHCSR_S_SLEEP_Msk = 0x40000
	// Bit S_SLEEP.
	CoreDebug_DHCSR_S_SLEEP = 0x40000
	// Position of S_LOCKUP field.
	CoreDebug_DHCSR_S_LOCKUP_Pos = 0x13
	// Bit mask of S_LOCKUP field.
	CoreDebug_DHCSR_S_LOCKUP_Msk = 0x80000
	// Bit S_LOCKUP.
	CoreDebug_DHCSR_S_LOCKUP = 0x80000
	// Position of S_RETIRE_ST field.
	CoreDebug_DHCSR_S_RETIRE_ST_Pos = 0x18
	// Bit mask of S_RETIRE_ST field.
	CoreDebug_DHCSR_S_RETIRE_ST_Msk = 0x1000000
	// Bit S_RETIRE_ST.
	CoreDebug_DHCSR_S_RETIRE_ST = 0x1000000
	// Position of S_RESET_ST field.
	CoreDebug_DHCSR_S_RESET_ST_Pos = 0x19
	// Bit mask of S_RESET_ST field.
	CoreDebug_DHCSR_S_RESET_ST_Msk = 0x2000000
	// Bit S_RESET_ST.
	CoreDebug_DHCSR_S_RESET_ST = 0x2000000
	// Position of DBGKEY field.
	CoreDebug_DHCSR_DBGKEY_Pos = 0x10
	// Bit mask of DBGKEY field.
	CoreDebug_DHCSR_DBGKEY_Msk = 0xffff0000

	// DCRSR: Debug Core Register Selector Register
	// Position of REGSEL field.
	CoreDebug_DCRSR_REGSEL_Pos = 0x0
	// Bit mask of REGSEL field.
	CoreDebug_DCRSR_REGSEL_Msk = 0x1f
	// Position of REGWnR field.
	CoreDebug_DCRSR_REGWnR_Pos = 0x10
	// Bit mask of REGWnR field.
	CoreDebug_DCRSR_REGWnR_Msk = 0x10000
	// Bit REGWnR.
	CoreDebug_DCRSR_REGWnR = 0x10000

	// DEMCR: Debug Exception and Monitor Control Register
	// Position of VC_CORERESET field.
	CoreDebug_DEMCR_VC_CORERESET_Pos = 0x0
	// Bit mask of VC_CORERESET field.
	CoreDebug_DEMCR_VC_CORERESET_Msk = 0x1
	// Bit VC_CORERESET.
	CoreDebug_DEMCR_VC_CORERESET = 0x1
	// Position of VC_MMERR field.
	CoreDebug_DEMCR_VC_MMERR_Pos = 0x4
	// Bit mask of VC_MMERR field.
	CoreDebug_DEMCR_VC_MMERR_Msk = 0x10
	// Bit VC_MMERR.
	CoreDebug_DEMCR_VC_MMERR = 0x10
	// Position of VC_NOCPERR field.
	CoreDebug_DEMCR_VC_NOCPERR_Pos = 0x5
	// Bit mask of VC_NOCPERR field.
	CoreDebug_DEMCR_VC_NOCPERR_Msk = 0x20
	// Bit VC_NOCPERR.
	CoreDebug_DEMCR_VC_NOCPERR = 0x20
	// Position of VC_CHKERR field.
	CoreDebug_DEMCR_VC_CHKERR_Pos = 0x6
	// Bit mask of VC_CHKERR field.
	CoreDebug_DEMCR_VC_CHKERR_Msk = 0x40
	// Bit VC_CHKERR.
	CoreDebug_DEMCR_VC_CHKERR = 0x40
	// Position of VC_STATERR field.
	CoreDebug_DEMCR_VC_STATERR_Pos = 0x7
	// Bit mask of VC_STATERR field.
	CoreDebug_DEMCR_VC_STATERR_Msk = 0x80
	// Bit VC_STATERR.
	CoreDebug_DEMCR_VC_STATERR = 0x80
	// Position of VC_BUSERR field.
	CoreDebug_DEMCR_VC_BUSERR_Pos = 0x8
	// Bit mask of VC_BUSERR field.
	CoreDebug_DEMCR_VC_BUSERR_Msk = 0x100
	// Bit VC_BUSERR.
	CoreDebug_DEMCR_VC_BUSERR = 0x100
	// Position of VC_INTERR field.
	CoreDebug_DEMCR_VC_INTERR_Pos = 0x9
	// Bit mask of VC_INTERR field.
	CoreDebug_DEMCR_VC_INTERR_Msk = 0x200
	// Bit VC_INTERR.
	CoreDebug_DEMCR_VC_INTERR = 0x200
	// Position of VC_HARDERR field.
	CoreDebug_DEMCR_VC_HARDERR_Pos = 0xa
	// Bit mask of VC_HARDERR field.
	CoreDebug_DEMCR_VC_HARDERR_Msk = 0x400
	// Bit VC_HARDERR.
	CoreDebug_DEMCR_VC_HARDERR = 0x400
	// Position of MON_EN field.
	CoreDebug_DEMCR_MON_EN_Pos = 0x10
	// Bit mask of MON_EN field.
	CoreDebug_DEMCR_MON_EN_Msk = 0x10000
	// Bit MON_EN.
	CoreDebug_DEMCR_MON_EN = 0x10000
	// Position of MON_PEND field.
	CoreDebug_DEMCR_MON_PEND_Pos = 0x11
	// Bit mask of MON_PEND field.
	CoreDebug_DEMCR_MON_PEND_Msk = 0x20000
	// Bit MON_PEND.
	CoreDebug_DEMCR_MON_PEND = 0x20000
	// Position of MON_STEP field.
	CoreDebug_DEMCR_MON_STEP_Pos = 0x12
	// Bit mask of MON_STEP field.
	CoreDebug_DEMCR_MON_STEP_Msk = 0x40000
	// Bit MON_STEP.
	CoreDebug_DEMCR_MON_STEP = 0x40000
	// Position of MON_REQ field.
	CoreDebug_DEMCR_MON_REQ_Pos = 0x13
	// Bit mask of MON_REQ field.
	CoreDebug_DEMCR_MON_REQ_Msk = 0x80000
	// Bit MON_REQ.
	CoreDebug_DEMCR_MON_REQ = 0x80000
	// Position of TRCENA field.
	CoreDebug_DEMCR_TRCENA_Pos = 0x18
	// Bit mask of TRCENA field.
	CoreDebug_DEMCR_TRCENA_Msk = 0x1000000
	// Bit TRCENA.
	CoreDebug_DEMCR_TRCENA = 0x1000000
)

// Bitfields for DWT: Data Watchpoint and Trace Register
const (
	// CTRL: Control Register
	// Position of CYCCNTENA field.
	DWT_CTRL_CYCCNTENA_Pos = 0x0
	// Bit mask of CYCCNTENA field.
	DWT_CTRL_CYCCNTENA_Msk = 0x1
	// Bit CYCCNTENA.
	DWT_CTRL_CYCCNTENA = 0x1
	// Position of POSTPRESET field.
	DWT_CTRL_POSTPRESET_Pos = 0x1
	// Bit mask of POSTPRESET field.
	DWT_CTRL_POSTPRESET_Msk = 0x1e
	// Position of POSTINIT field.
	DWT_CTRL_POSTINIT_Pos = 0x5
	// Bit mask of POSTINIT field.
	DWT_CTRL_POSTINIT_Msk = 0x1e0
	// Position of CYCTAP field.
	DWT_CTRL_CYCTAP_Pos = 0x9
	// Bit mask of CYCTAP field.
	DWT_CTRL_CYCTAP_Msk = 0x200
	// Bit CYCTAP.
	DWT_CTRL_CYCTAP = 0x200
	// Position of SYNCTAP field.
	DWT_CTRL_SYNCTAP_Pos = 0xa
	// Bit mask of SYNCTAP field.
	DWT_CTRL_SYNCTAP_Msk = 0xc00
	// Position of PCSAMPLENA field.
	DWT_CTRL_PCSAMPLENA_Pos = 0xc
	// Bit mask of PCSAMPLENA field.
	DWT_CTRL_PCSAMPLENA_Msk = 0x1000
	// Bit PCSAMPLENA.
	DWT_CTRL_PCSAMPLENA = 0x1000
	// Position of EXCTRCENA field.
	DWT_CTRL_EXCTRCENA_Pos = 0x10
	// Bit mask of EXCTRCENA field.
	DWT_CTRL_EXCTRCENA_Msk = 0x10000
	// Bit EXCTRCENA.
	DWT_CTRL_EXCTRCENA = 0x10000
	// Position of CPIEVTENA field.
	DWT_CTRL_CPIEVTENA_Pos = 0x11
	// Bit mask of CPIEVTENA field.
	DWT_CTRL_CPIEVTENA_Msk = 0x20000
	// Bit CPIEVTENA.
	DWT_CTRL_CPIEVTENA = 0x20000
	// Position of EXCEVTENA field.
	DWT_CTRL_EXCEVTENA_Pos = 0x12
	// Bit mask of EXCEVTENA field.
	DWT_CTRL_EXCEVTENA_Msk = 0x40000
	// Bit EXCEVTENA.
	DWT_CTRL_EXCEVTENA = 0x40000
	// Position of SLEEPEVTENA field.
	DWT_CTRL_SLEEPEVTENA_Pos = 0x13
	// Bit mask of SLEEPEVTENA field.
	DWT_CTRL_SLEEPEVTENA_Msk = 0x80000
	// Bit SLEEPEVTENA.
	DWT_CTRL_SLEEPEVTENA = 0x80000
	// Position of LSUEVTENA field.
	DWT_CTRL_LSUEVTENA_Pos = 0x14
	// Bit mask of LSUEVTENA field.
	DWT_CTRL_LSUEVTENA_Msk = 0x100000
	// Bit LSUEVTENA.
	DWT_CTRL_LSUEVTENA = 0x100000
	// Position of FOLDEVTENA field.
	DWT_CTRL_FOLDEVTENA_Pos = 0x15
	// Bit mask of FOLDEVTENA field.
	DWT_CTRL_FOLDEVTENA_Msk = 0x200000
	// Bit FOLDEVTENA.
	DWT_CTRL_FOLDEVTENA = 0x200000
	// Position of CYCEVTENA field.
	DWT_CTRL_CYCEVTENA_Pos = 0x16
	// Bit mask of CYCEVTENA field.
	DWT_CTRL_CYCEVTENA_Msk = 0x400000
	// Bit CYCEVTENA.
	DWT_CTRL_CYCEVTENA = 0x400000
	// Position of NOPRFCNT field.
	DWT_CTRL_NOPRFCNT_Pos = 0x18
	// Bit mask of NOPRFCNT field.
	DWT_CTRL_NOPRFCNT_Msk = 0x1000000
	// Bit NOPRFCNT.
	DWT_CTRL_NOPRFCNT = 0x1000000
	// Position of NOCYCCNT field.
	DWT_CTRL_NOCYCCNT_Pos = 0x19
	// Bit mask of NOCYCCNT field.
	DWT_CTRL_NOCYCCNT_Msk = 0x2000000
	// Bit NOCYCCNT.
	DWT_CTRL_NOCYCCNT = 0x2000000
	// Position of NOEXTTRIG field.
	DWT_CTRL_NOEXTTRIG_Pos = 0x1a
	// Bit mask of NOEXTTRIG field.
	DWT_CTRL_NOEXTTRIG_Msk = 0x4000000
	// Bit NOEXTTRIG.
	DWT_CTRL_NOEXTTRIG = 0x4000000
	// Position of NOTRCPKT field.
	DWT_CTRL_NOTRCPKT_Pos = 0x1b
	// Bit mask of NOTRCPKT field.
	DWT_CTRL_NOTRCPKT_Msk = 0x8000000
	// Bit NOTRCPKT.
	DWT_CTRL_NOTRCPKT = 0x8000000
	// Position of NUMCOMP field.
	DWT_CTRL_NUMCOMP_Pos = 0x1c
	// Bit mask of NUMCOMP field.
	DWT_CTRL_NUMCOMP_Msk = 0xf0000000

	// CPICNT: CPI Count Register
	// Position of CPICNT field.
	DWT_CPICNT_CPICNT_Pos = 0x0
	// Bit mask of CPICNT field.
	DWT_CPICNT_CPICNT_Msk = 0xff

	// EXCCNT: Exception Overhead Count Register
	// Position of EXCCNT field.
	DWT_EXCCNT_EXCCNT_Pos = 0x0
	// Bit mask of EXCCNT field.
	DWT_EXCCNT_EXCCNT_Msk = 0xff

	// SLEEPCNT: Sleep Count Register
	// Position of SLEEPCNT field.
	DWT_SLEEPCNT_SLEEPCNT_Pos = 0x0
	// Bit mask of SLEEPCNT field.
	DWT_SLEEPCNT_SLEEPCNT_Msk = 0xff

	// LSUCNT: LSU Count Register
	// Position of LSUCNT field.
	DWT_LSUCNT_LSUCNT_Pos = 0x0
	// Bit mask of LSUCNT field.
	DWT_LSUCNT_LSUCNT_Msk = 0xff

	// FOLDCNT: Folded-instruction Count Register
	// Position of FOLDCNT field.
	DWT_FOLDCNT_FOLDCNT_Pos = 0x0
	// Bit mask of FOLDCNT field.
	DWT_FOLDCNT_FOLDCNT_Msk = 0xff

	// MASK0: Mask Register 0
	// Position of MASK field.
	DWT_MASK0_MASK_Pos = 0x0
	// Bit mask of MASK field.
	DWT_MASK0_MASK_Msk = 0x1f

	// FUNCTION0: Function Register 0
	// Position of FUNCTION field.
	DWT_FUNCTION0_FUNCTION_Pos = 0x0
	// Bit mask of FUNCTION field.
	DWT_FUNCTION0_FUNCTION_Msk = 0xf
	// Position of EMITRANGE field.
	DWT_FUNCTION0_EMITRANGE_Pos = 0x5
	// Bit mask of EMITRANGE field.
	DWT_FUNCTION0_EMITRANGE_Msk = 0x20
	// Bit EMITRANGE.
	DWT_FUNCTION0_EMITRANGE = 0x20
	// Position of CYCMATCH field.
	DWT_FUNCTION0_CYCMATCH_Pos = 0x7
	// Bit mask of CYCMATCH field.
	DWT_FUNCTION0_CYCMATCH_Msk = 0x80
	// Bit CYCMATCH.
	DWT_FUNCTION0_CYCMATCH = 0x80
	// Position of DATAVMATCH field.
	DWT_FUNCTION0_DATAVMATCH_Pos = 0x8
	// Bit mask of DATAVMATCH field.
	DWT_FUNCTION0_DATAVMATCH_Msk = 0x100
	// Bit DATAVMATCH.
	DWT_FUNCTION0_DATAVMATCH = 0x100
	// Position of LNK1ENA field.
	DWT_FUNCTION0_LNK1ENA_Pos = 0x9
	// Bit mask of LNK1ENA field.
	DWT_FUNCTION0_LNK1ENA_Msk = 0x200
	// Bit LNK1ENA.
	DWT_FUNCTION0_LNK1ENA = 0x200
	// Position of DATAVSIZE field.
	DWT_FUNCTION0_DATAVSIZE_Pos = 0xa
	// Bit mask of DATAVSIZE field.
	DWT_FUNCTION0_DATAVSIZE_Msk = 0xc00
	// Position of DATAVADDR0 field.
	DWT_FUNCTION0_DATAVADDR0_Pos = 0xc
	// Bit mask of DATAVADDR0 field.
	DWT_FUNCTION0_DATAVADDR0_Msk = 0xf000
	// Position of DATAVADDR1 field.
	DWT_FUNCTION0_DATAVADDR1_Pos = 0x10
	// Bit mask of DATAVADDR1 field.
	DWT_FUNCTION0_DATAVADDR1_Msk = 0xf0000
	// Position of MATCHED field.
	DWT_FUNCTION0_MATCHED_Pos = 0x18
	// Bit mask of MATCHED field.
	DWT_FUNCTION0_MATCHED_Msk = 0x1000000
	// Bit MATCHED.
	DWT_FUNCTION0_MATCHED = 0x1000000

	// MASK1: Mask Register 1
	// Position of MASK field.
	DWT_MASK1_MASK_Pos = 0x0
	// Bit mask of MASK field.
	DWT_MASK1_MASK_Msk = 0x1f

	// FUNCTION1: Function Register 1
	// Position of FUNCTION field.
	DWT_FUNCTION1_FUNCTION_Pos = 0x0
	// Bit mask of FUNCTION field.
	DWT_FUNCTION1_FUNCTION_Msk = 0xf
	// Position of EMITRANGE field.
	DWT_FUNCTION1_EMITRANGE_Pos = 0x5
	// Bit mask of EMITRANGE field.
	DWT_FUNCTION1_EMITRANGE_Msk = 0x20
	// Bit EMITRANGE.
	DWT_FUNCTION1_EMITRANGE = 0x20
	// Position of CYCMATCH field.
	DWT_FUNCTION1_CYCMATCH_Pos = 0x7
	// Bit mask of CYCMATCH field.
	DWT_FUNCTION1_CYCMATCH_Msk = 0x80
	// Bit CYCMATCH.
	DWT_FUNCTION1_CYCMATCH = 0x80
	// Position of DATAVMATCH field.
	DWT_FUNCTION1_DATAVMATCH_Pos = 0x8
	// Bit mask of DATAVMATCH field.
	DWT_FUNCTION1_DATAVMATCH_Msk = 0x100
	// Bit DATAVMATCH.
	DWT_FUNCTION1_DATAVMATCH = 0x100
	// Position of LNK1ENA field.
	DWT_FUNCTION1_LNK1ENA_Pos = 0x9
	// Bit mask of LNK1ENA field.
	DWT_FUNCTION1_LNK1ENA_Msk = 0x200
	// Bit LNK1ENA.
	DWT_FUNCTION1_LNK1ENA = 0x200
	// Position of DATAVSIZE field.
	DWT_FUNCTION1_DATAVSIZE_Pos = 0xa
	// Bit mask of DATAVSIZE field.
	DWT_FUNCTION1_DATAVSIZE_Msk = 0xc00
	// Position of DATAVADDR0 field.
	DWT_FUNCTION1_DATAVADDR0_Pos = 0xc
	// Bit mask of DATAVADDR0 field.
	DWT_FUNCTION1_DATAVADDR0_Msk = 0xf000
	// Position of DATAVADDR1 field.
	DWT_FUNCTION1_DATAVADDR1_Pos = 0x10
	// Bit mask of DATAVADDR1 field.
	DWT_FUNCTION1_DATAVADDR1_Msk = 0xf0000
	// Position of MATCHED field.
	DWT_FUNCTION1_MATCHED_Pos = 0x18
	// Bit mask of MATCHED field.
	DWT_FUNCTION1_MATCHED_Msk = 0x1000000
	// Bit MATCHED.
	DWT_FUNCTION1_MATCHED = 0x1000000

	// MASK2: Mask Register 2
	// Position of MASK field.
	DWT_MASK2_MASK_Pos = 0x0
	// Bit mask of MASK field.
	DWT_MASK2_MASK_Msk = 0x1f

	// FUNCTION2: Function Register 2
	// Position of FUNCTION field.
	DWT_FUNCTION2_FUNCTION_Pos = 0x0
	// Bit mask of FUNCTION field.
	DWT_FUNCTION2_FUNCTION_Msk = 0xf
	// Position of EMITRANGE field.
	DWT_FUNCTION2_EMITRANGE_Pos = 0x5
	// Bit mask of EMITRANGE field.
	DWT_FUNCTION2_EMITRANGE_Msk = 0x20
	// Bit EMITRANGE.
	DWT_FUNCTION2_EMITRANGE = 0x20
	// Position of CYCMATCH field.
	DWT_FUNCTION2_CYCMATCH_Pos = 0x7
	// Bit mask of CYCMATCH field.
	DWT_FUNCTION2_CYCMATCH_Msk = 0x80
	// Bit CYCMATCH.
	DWT_FUNCTION2_CYCMATCH = 0x80
	// Position of DATAVMATCH field.
	DWT_FUNCTION2_DATAVMATCH_Pos = 0x8
	// Bit mask of DATAVMATCH field.
	DWT_FUNCTION2_DATAVMATCH_Msk = 0x100
	// Bit DATAVMATCH.
	DWT_FUNCTION2_DATAVMATCH = 0x100
	// Position of LNK1ENA field.
	DWT_FUNCTION2_LNK1ENA_Pos = 0x9
	// Bit mask of LNK1ENA field.
	DWT_FUNCTION2_LNK1ENA_Msk = 0x200
	// Bit LNK1ENA.
	DWT_FUNCTION2_LNK1ENA = 0x200
	// Position of DATAVSIZE field.
	DWT_FUNCTION2_DATAVSIZE_Pos = 0xa
	// Bit mask of DATAVSIZE field.
	DWT_FUNCTION2_DATAVSIZE_Msk = 0xc00
	// Position of DATAVADDR0 field.
	DWT_FUNCTION2_DATAVADDR0_Pos = 0xc
	// Bit mask of DATAVADDR0 field.
	DWT_FUNCTION2_DATAVADDR0_Msk = 0xf000
	// Position of DATAVADDR1 field.
	DWT_FUNCTION2_DATAVADDR1_Pos = 0x10
	// Bit mask of DATAVADDR1 field.
	DWT_FUNCTION2_DATAVADDR1_Msk = 0xf0000
	// Position of MATCHED field.
	DWT_FUNCTION2_MATCHED_Pos = 0x18
	// Bit mask of MATCHED field.
	DWT_FUNCTION2_MATCHED_Msk = 0x1000000
	// Bit MATCHED.
	DWT_FUNCTION2_MATCHED = 0x1000000

	// MASK3: Mask Register 3
	// Position of MASK field.
	DWT_MASK3_MASK_Pos = 0x0
	// Bit mask of MASK field.
	DWT_MASK3_MASK_Msk = 0x1f

	// FUNCTION3: Function Register 3
	// Position of FUNCTION field.
	DWT_FUNCTION3_FUNCTION_Pos = 0x0
	// Bit mask of FUNCTION field.
	DWT_FUNCTION3_FUNCTION_Msk = 0xf
	// Position of EMITRANGE field.
	DWT_FUNCTION3_EMITRANGE_Pos = 0x5
	// Bit mask of EMITRANGE field.
	DWT_FUNCTION3_EMITRANGE_Msk = 0x20
	// Bit EMITRANGE.
	DWT_FUNCTION3_EMITRANGE = 0x20
	// Position of CYCMATCH field.
	DWT_FUNCTION3_CYCMATCH_Pos = 0x7
	// Bit mask of CYCMATCH field.
	DWT_FUNCTION3_CYCMATCH_Msk = 0x80
	// Bit CYCMATCH.
	DWT_FUNCTION3_CYCMATCH = 0x80
	// Position of DATAVMATCH field.
	DWT_FUNCTION3_DATAVMATCH_Pos = 0x8
	// Bit mask of DATAVMATCH field.
	DWT_FUNCTION3_DATAVMATCH_Msk = 0x100
	// Bit DATAVMATCH.
	DWT_FUNCTION3_DATAVMATCH = 0x100
	// Position of LNK1ENA field.
	DWT_FUNCTION3_LNK1ENA_Pos = 0x9
	// Bit mask of LNK1ENA field.
	DWT_FUNCTION3_LNK1ENA_Msk = 0x200
	// Bit LNK1ENA.
	DWT_FUNCTION3_LNK1ENA = 0x200
	// Position of DATAVSIZE field.
	DWT_FUNCTION3_DATAVSIZE_Pos = 0xa
	// Bit mask of DATAVSIZE field.
	DWT_FUNCTION3_DATAVSIZE_Msk = 0xc00
	// Position of DATAVADDR0 field.
	DWT_FUNCTION3_DATAVADDR0_Pos = 0xc
	// Bit mask of DATAVADDR0 field.
	DWT_FUNCTION3_DATAVADDR0_Msk = 0xf000
	// Position of DATAVADDR1 field.
	DWT_FUNCTION3_DATAVADDR1_Pos = 0x10
	// Bit mask of DATAVADDR1 field.
	DWT_FUNCTION3_DATAVADDR1_Msk = 0xf0000
	// Position of MATCHED field.
	DWT_FUNCTION3_MATCHED_Pos = 0x18
	// Bit mask of MATCHED field.
	DWT_FUNCTION3_MATCHED_Msk = 0x1000000
	// Bit MATCHED.
	DWT_FUNCTION3_MATCHED = 0x1000000
)

// Bitfields for ETM: Embedded Trace Macrocell
const (
	// CR: ETM Main Control Register
	// Position of ETMPD field.
	ETM_CR_ETMPD_Pos = 0x0
	// Bit mask of ETMPD field.
	ETM_CR_ETMPD_Msk = 0x1
	// Bit ETMPD.
	ETM_CR_ETMPD = 0x1
	// Position of PORTSIZE field.
	ETM_CR_PORTSIZE_Pos = 0x4
	// Bit mask of PORTSIZE field.
	ETM_CR_PORTSIZE_Msk = 0x70
	// Position of STALL field.
	ETM_CR_STALL_Pos = 0x7
	// Bit mask of STALL field.
	ETM_CR_STALL_Msk = 0x80
	// Bit STALL.
	ETM_CR_STALL = 0x80
	// Position of BROUT field.
	ETM_CR_BROUT_Pos = 0x8
	// Bit mask of BROUT field.
	ETM_CR_BROUT_Msk = 0x100
	// Bit BROUT.
	ETM_CR_BROUT = 0x100
	// Position of DBGRQ field.
	ETM_CR_DBGRQ_Pos = 0x9
	// Bit mask of DBGRQ field.
	ETM_CR_DBGRQ_Msk = 0x200
	// Bit DBGRQ.
	ETM_CR_DBGRQ = 0x200
	// Position of PROG field.
	ETM_CR_PROG_Pos = 0xa
	// Bit mask of PROG field.
	ETM_CR_PROG_Msk = 0x400
	// Bit PROG.
	ETM_CR_PROG = 0x400
	// Position of PORTSEL field.
	ETM_CR_PORTSEL_Pos = 0xb
	// Bit mask of PORTSEL field.
	ETM_CR_PORTSEL_Msk = 0x800
	// Bit PORTSEL.
	ETM_CR_PORTSEL = 0x800
	// Position of PORTMODE2 field.
	ETM_CR_PORTMODE2_Pos = 0xd
	// Bit mask of PORTMODE2 field.
	ETM_CR_PORTMODE2_Msk = 0x2000
	// Bit PORTMODE2.
	ETM_CR_PORTMODE2 = 0x2000
	// Position of PORTMODE field.
	ETM_CR_PORTMODE_Pos = 0x10
	// Bit mask of PORTMODE field.
	ETM_CR_PORTMODE_Msk = 0x30000
	// Position of PORTSIZE3 field.
	ETM_CR_PORTSIZE3_Pos = 0x15
	// Bit mask of PORTSIZE3 field.
	ETM_CR_PORTSIZE3_Msk = 0x200000
	// Bit PORTSIZE3.
	ETM_CR_PORTSIZE3 = 0x200000
	// Position of TSEN field.
	ETM_CR_TSEN_Pos = 0x1c
	// Bit mask of TSEN field.
	ETM_CR_TSEN_Msk = 0x10000000
	// Bit TSEN.
	ETM_CR_TSEN = 0x10000000

	// ITCTRL: ETM Integration Mode Control Register
	// Position of INTEGRATION field.
	ETM_ITCTRL_INTEGRATION_Pos = 0x0
	// Bit mask of INTEGRATION field.
	ETM_ITCTRL_INTEGRATION_Msk = 0x1
	// Bit INTEGRATION.
	ETM_ITCTRL_INTEGRATION = 0x1

	// LSR: ETM Lock Status Register
	// Position of Present field.
	ETM_LSR_Present_Pos = 0x0
	// Bit mask of Present field.
	ETM_LSR_Present_Msk = 0x1
	// Bit Present.
	ETM_LSR_Present = 0x1
	// Position of Access field.
	ETM_LSR_Access_Pos = 0x1
	// Bit mask of Access field.
	ETM_LSR_Access_Msk = 0x2
	// Bit Access.
	ETM_LSR_Access = 0x2
	// Position of ByteAcc field.
	ETM_LSR_ByteAcc_Pos = 0x2
	// Bit mask of ByteAcc field.
	ETM_LSR_ByteAcc_Msk = 0x4
	// Bit ByteAcc.
	ETM_LSR_ByteAcc = 0x4
)

// Bitfields for FPU: Floating Point Unit
const (
	// FPCCR: Floating-Point Context Control Register
	// Position of LSPACT field.
	FPU_FPCCR_LSPACT_Pos = 0x0
	// Bit mask of LSPACT field.
	FPU_FPCCR_LSPACT_Msk = 0x1
	// Bit LSPACT.
	FPU_FPCCR_LSPACT = 0x1
	// Position of USER field.
	FPU_FPCCR_USER_Pos = 0x1
	// Bit mask of USER field.
	FPU_FPCCR_USER_Msk = 0x2
	// Bit USER.
	FPU_FPCCR_USER = 0x2
	// Position of THREAD field.
	FPU_FPCCR_THREAD_Pos = 0x3
	// Bit mask of THREAD field.
	FPU_FPCCR_THREAD_Msk = 0x8
	// Bit THREAD.
	FPU_FPCCR_THREAD = 0x8
	// Position of HFRDY field.
	FPU_FPCCR_HFRDY_Pos = 0x4
	// Bit mask of HFRDY field.
	FPU_FPCCR_HFRDY_Msk = 0x10
	// Bit HFRDY.
	FPU_FPCCR_HFRDY = 0x10
	// Position of MMRDY field.
	FPU_FPCCR_MMRDY_Pos = 0x5
	// Bit mask of MMRDY field.
	FPU_FPCCR_MMRDY_Msk = 0x20
	// Bit MMRDY.
	FPU_FPCCR_MMRDY = 0x20
	// Position of BFRDY field.
	FPU_FPCCR_BFRDY_Pos = 0x6
	// Bit mask of BFRDY field.
	FPU_FPCCR_BFRDY_Msk = 0x40
	// Bit BFRDY.
	FPU_FPCCR_BFRDY = 0x40
	// Position of MONRDY field.
	FPU_FPCCR_MONRDY_Pos = 0x8
	// Bit mask of MONRDY field.
	FPU_FPCCR_MONRDY_Msk = 0x100
	// Bit MONRDY.
	FPU_FPCCR_MONRDY = 0x100
	// Position of LSPEN field.
	FPU_FPCCR_LSPEN_Pos = 0x1e
	// Bit mask of LSPEN field.
	FPU_FPCCR_LSPEN_Msk = 0x40000000
	// Bit LSPEN.
	FPU_FPCCR_LSPEN = 0x40000000
	// Position of ASPEN field.
	FPU_FPCCR_ASPEN_Pos = 0x1f
	// Bit mask of ASPEN field.
	FPU_FPCCR_ASPEN_Msk = 0x80000000
	// Bit ASPEN.
	FPU_FPCCR_ASPEN = 0x80000000

	// FPCAR: Floating-Point Context Address Register
	// Position of ADDRESS field.
	FPU_FPCAR_ADDRESS_Pos = 0x3
	// Bit mask of ADDRESS field.
	FPU_FPCAR_ADDRESS_Msk = 0xfffffff8

	// FPDSCR: Floating-Point Default Status Control Register
	// Position of RMODE field.
	FPU_FPDSCR_RMODE_Pos = 0x16
	// Bit mask of RMODE field.
	FPU_FPDSCR_RMODE_Msk = 0xc00000
	// Round to Nearest
	FPU_FPDSCR_RMODE_RN = 0x0
	// Round towards Positive Infinity
	FPU_FPDSCR_RMODE_RP = 0x1
	// Round towards Negative Infinity
	FPU_FPDSCR_RMODE_RM = 0x2
	// Round towards Zero
	FPU_FPDSCR_RMODE_RZ = 0x3
	// Position of FZ field.
	FPU_FPDSCR_FZ_Pos = 0x18
	// Bit mask of FZ field.
	FPU_FPDSCR_FZ_Msk = 0x1000000
	// Bit FZ.
	FPU_FPDSCR_FZ = 0x1000000
	// Position of DN field.
	FPU_FPDSCR_DN_Pos = 0x19
	// Bit mask of DN field.
	FPU_FPDSCR_DN_Msk = 0x2000000
	// Bit DN.
	FPU_FPDSCR_DN = 0x2000000
	// Position of AHP field.
	FPU_FPDSCR_AHP_Pos = 0x1a
	// Bit mask of AHP field.
	FPU_FPDSCR_AHP_Msk = 0x4000000
	// Bit AHP.
	FPU_FPDSCR_AHP = 0x4000000

	// MVFR0: Media and FP Feature Register 0
	// Position of A_SIMD_registers field.
	FPU_MVFR0_A_SIMD_registers_Pos = 0x0
	// Bit mask of A_SIMD_registers field.
	FPU_MVFR0_A_SIMD_registers_Msk = 0xf
	// Position of Single_precision field.
	FPU_MVFR0_Single_precision_Pos = 0x4
	// Bit mask of Single_precision field.
	FPU_MVFR0_Single_precision_Msk = 0xf0
	// Position of Double_precision field.
	FPU_MVFR0_Double_precision_Pos = 0x8
	// Bit mask of Double_precision field.
	FPU_MVFR0_Double_precision_Msk = 0xf00
	// Position of FP_excep_trapping field.
	FPU_MVFR0_FP_excep_trapping_Pos = 0xc
	// Bit mask of FP_excep_trapping field.
	FPU_MVFR0_FP_excep_trapping_Msk = 0xf000
	// Position of Divide field.
	FPU_MVFR0_Divide_Pos = 0x10
	// Bit mask of Divide field.
	FPU_MVFR0_Divide_Msk = 0xf0000
	// Position of Square_root field.
	FPU_MVFR0_Square_root_Pos = 0x14
	// Bit mask of Square_root field.
	FPU_MVFR0_Square_root_Msk = 0xf00000
	// Position of Short_vectors field.
	FPU_MVFR0_Short_vectors_Pos = 0x18
	// Bit mask of Short_vectors field.
	FPU_MVFR0_Short_vectors_Msk = 0xf000000
	// Position of FP_rounding_modes field.
	FPU_MVFR0_FP_rounding_modes_Pos = 0x1c
	// Bit mask of FP_rounding_modes field.
	FPU_MVFR0_FP_rounding_modes_Msk = 0xf0000000

	// MVFR1: Media and FP Feature Register 1
	// Position of FtZ_mode field.
	FPU_MVFR1_FtZ_mode_Pos = 0x0
	// Bit mask of FtZ_mode field.
	FPU_MVFR1_FtZ_mode_Msk = 0xf
	// Position of D_NaN_mode field.
	FPU_MVFR1_D_NaN_mode_Pos = 0x4
	// Bit mask of D_NaN_mode field.
	FPU_MVFR1_D_NaN_mode_Msk = 0xf0
	// Position of FP_HPFP field.
	FPU_MVFR1_FP_HPFP_Pos = 0x18
	// Bit mask of FP_HPFP field.
	FPU_MVFR1_FP_HPFP_Msk = 0xf000000
	// Position of FP_fused_MAC field.
	FPU_MVFR1_FP_fused_MAC_Pos = 0x1c
	// Bit mask of FP_fused_MAC field.
	FPU_MVFR1_FP_fused_MAC_Msk = 0xf0000000
)

// Bitfields for ITM: Instrumentation Trace Macrocell
const (
	// PORT_WORD_MODE: ITM Stimulus Port Registers
	// Position of PORT field.
	ITM_PORT_WORD_MODE_PORT_Pos = 0x0
	// Bit mask of PORT field.
	ITM_PORT_WORD_MODE_PORT_Msk = 0xffffffff

	// PORT_BYTE_MODE: ITM Stimulus Port Registers
	// Position of PORT field.
	ITM_PORT_BYTE_MODE_PORT_Pos = 0x0
	// Bit mask of PORT field.
	ITM_PORT_BYTE_MODE_PORT_Msk = 0xff

	// PORT_HWORD_MODE: ITM Stimulus Port Registers
	// Position of PORT field.
	ITM_PORT_HWORD_MODE_PORT_Pos = 0x0
	// Bit mask of PORT field.
	ITM_PORT_HWORD_MODE_PORT_Msk = 0xffff

	// TPR: ITM Trace Privilege Register
	// Position of PRIVMASK field.
	ITM_TPR_PRIVMASK_Pos = 0x0
	// Bit mask of PRIVMASK field.
	ITM_TPR_PRIVMASK_Msk = 0xf

	// TCR: ITM Trace Control Register
	// Position of ITMENA field.
	ITM_TCR_ITMENA_Pos = 0x0
	// Bit mask of ITMENA field.
	ITM_TCR_ITMENA_Msk = 0x1
	// Bit ITMENA.
	ITM_TCR_ITMENA = 0x1
	// Position of TSENA field.
	ITM_TCR_TSENA_Pos = 0x1
	// Bit mask of TSENA field.
	ITM_TCR_TSENA_Msk = 0x2
	// Bit TSENA.
	ITM_TCR_TSENA = 0x2
	// Position of SYNCENA field.
	ITM_TCR_SYNCENA_Pos = 0x2
	// Bit mask of SYNCENA field.
	ITM_TCR_SYNCENA_Msk = 0x4
	// Bit SYNCENA.
	ITM_TCR_SYNCENA = 0x4
	// Position of DWTENA field.
	ITM_TCR_DWTENA_Pos = 0x3
	// Bit mask of DWTENA field.
	ITM_TCR_DWTENA_Msk = 0x8
	// Bit DWTENA.
	ITM_TCR_DWTENA = 0x8
	// Position of SWOENA field.
	ITM_TCR_SWOENA_Pos = 0x4
	// Bit mask of SWOENA field.
	ITM_TCR_SWOENA_Msk = 0x10
	// Bit SWOENA.
	ITM_TCR_SWOENA = 0x10
	// Position of STALLENA field.
	ITM_TCR_STALLENA_Pos = 0x5
	// Bit mask of STALLENA field.
	ITM_TCR_STALLENA_Msk = 0x20
	// Bit STALLENA.
	ITM_TCR_STALLENA = 0x20
	// Position of TSPrescale field.
	ITM_TCR_TSPrescale_Pos = 0x8
	// Bit mask of TSPrescale field.
	ITM_TCR_TSPrescale_Msk = 0x300
	// Position of GTSFREQ field.
	ITM_TCR_GTSFREQ_Pos = 0xa
	// Bit mask of GTSFREQ field.
	ITM_TCR_GTSFREQ_Msk = 0xc00
	// Position of TraceBusID field.
	ITM_TCR_TraceBusID_Pos = 0x10
	// Bit mask of TraceBusID field.
	ITM_TCR_TraceBusID_Msk = 0x7f0000
	// Position of BUSY field.
	ITM_TCR_BUSY_Pos = 0x17
	// Bit mask of BUSY field.
	ITM_TCR_BUSY_Msk = 0x800000
	// Bit BUSY.
	ITM_TCR_BUSY = 0x800000

	// IWR: ITM Integration Write Register
	// Position of ATVALIDM field.
	ITM_IWR_ATVALIDM_Pos = 0x0
	// Bit mask of ATVALIDM field.
	ITM_IWR_ATVALIDM_Msk = 0x1
	// Bit ATVALIDM.
	ITM_IWR_ATVALIDM = 0x1

	// IRR: ITM Integration Read Register
	// Position of ATREADYM field.
	ITM_IRR_ATREADYM_Pos = 0x0
	// Bit mask of ATREADYM field.
	ITM_IRR_ATREADYM_Msk = 0x1
	// Bit ATREADYM.
	ITM_IRR_ATREADYM = 0x1
)

// Bitfields for MPU: Memory Protection Unit
const (
	// TYPE: MPU Type Register
	// Position of SEPARATE field.
	MPU_TYPE_SEPARATE_Pos = 0x0
	// Bit mask of SEPARATE field.
	MPU_TYPE_SEPARATE_Msk = 0x1
	// Bit SEPARATE.
	MPU_TYPE_SEPARATE = 0x1
	// Position of DREGION field.
	MPU_TYPE_DREGION_Pos = 0x8
	// Bit mask of DREGION field.
	MPU_TYPE_DREGION_Msk = 0xff00
	// Position of IREGION field.
	MPU_TYPE_IREGION_Pos = 0x10
	// Bit mask of IREGION field.
	MPU_TYPE_IREGION_Msk = 0xff0000

	// CTRL: MPU Control Register
	// Position of ENABLE field.
	MPU_CTRL_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	MPU_CTRL_ENABLE_Msk = 0x1
	// Bit ENABLE.
	MPU_CTRL_ENABLE = 0x1
	// Position of HFNMIENA field.
	MPU_CTRL_HFNMIENA_Pos = 0x1
	// Bit mask of HFNMIENA field.
	MPU_CTRL_HFNMIENA_Msk = 0x2
	// Bit HFNMIENA.
	MPU_CTRL_HFNMIENA = 0x2
	// Position of PRIVDEFENA field.
	MPU_CTRL_PRIVDEFENA_Pos = 0x2
	// Bit mask of PRIVDEFENA field.
	MPU_CTRL_PRIVDEFENA_Msk = 0x4
	// Bit PRIVDEFENA.
	MPU_CTRL_PRIVDEFENA = 0x4

	// RNR: MPU Region Number Register
	// Position of REGION field.
	MPU_RNR_REGION_Pos = 0x0
	// Bit mask of REGION field.
	MPU_RNR_REGION_Msk = 0xff

	// RBAR: MPU Region Base Address Register
	// Position of REGION field.
	MPU_RBAR_REGION_Pos = 0x0
	// Bit mask of REGION field.
	MPU_RBAR_REGION_Msk = 0xf
	// Position of VALID field.
	MPU_RBAR_VALID_Pos = 0x4
	// Bit mask of VALID field.
	MPU_RBAR_VALID_Msk = 0x10
	// Bit VALID.
	MPU_RBAR_VALID = 0x10
	// Position of ADDR field.
	MPU_RBAR_ADDR_Pos = 0x5
	// Bit mask of ADDR field.
	MPU_RBAR_ADDR_Msk = 0xffffffe0

	// RASR: MPU Region Attribute and Size Register
	// Position of ENABLE field.
	MPU_RASR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	MPU_RASR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	MPU_RASR_ENABLE = 0x1
	// Position of SIZE field.
	MPU_RASR_SIZE_Pos = 0x1
	// Bit mask of SIZE field.
	MPU_RASR_SIZE_Msk = 0x2
	// Bit SIZE.
	MPU_RASR_SIZE = 0x2
	// Position of SRD field.
	MPU_RASR_SRD_Pos = 0x8
	// Bit mask of SRD field.
	MPU_RASR_SRD_Msk = 0xff00
	// Position of B field.
	MPU_RASR_B_Pos = 0x10
	// Bit mask of B field.
	MPU_RASR_B_Msk = 0x10000
	// Bit B.
	MPU_RASR_B = 0x10000
	// Position of C field.
	MPU_RASR_C_Pos = 0x11
	// Bit mask of C field.
	MPU_RASR_C_Msk = 0x20000
	// Bit C.
	MPU_RASR_C = 0x20000
	// Position of S field.
	MPU_RASR_S_Pos = 0x12
	// Bit mask of S field.
	MPU_RASR_S_Msk = 0x40000
	// Bit S.
	MPU_RASR_S = 0x40000
	// Position of TEX field.
	MPU_RASR_TEX_Pos = 0x13
	// Bit mask of TEX field.
	MPU_RASR_TEX_Msk = 0x380000
	// Position of AP field.
	MPU_RASR_AP_Pos = 0x18
	// Bit mask of AP field.
	MPU_RASR_AP_Msk = 0x7000000
	// Position of XN field.
	MPU_RASR_XN_Pos = 0x1c
	// Bit mask of XN field.
	MPU_RASR_XN_Msk = 0x10000000
	// Bit XN.
	MPU_RASR_XN = 0x10000000

	// RBAR_A1: MPU Alias 1 Region Base Address Register
	// Position of REGION field.
	MPU_RBAR_A1_REGION_Pos = 0x0
	// Bit mask of REGION field.
	MPU_RBAR_A1_REGION_Msk = 0xf
	// Position of VALID field.
	MPU_RBAR_A1_VALID_Pos = 0x4
	// Bit mask of VALID field.
	MPU_RBAR_A1_VALID_Msk = 0x10
	// Bit VALID.
	MPU_RBAR_A1_VALID = 0x10
	// Position of ADDR field.
	MPU_RBAR_A1_ADDR_Pos = 0x5
	// Bit mask of ADDR field.
	MPU_RBAR_A1_ADDR_Msk = 0xffffffe0

	// RASR_A1: MPU Alias 1 Region Attribute and Size Register
	// Position of ENABLE field.
	MPU_RASR_A1_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	MPU_RASR_A1_ENABLE_Msk = 0x1
	// Bit ENABLE.
	MPU_RASR_A1_ENABLE = 0x1
	// Position of SIZE field.
	MPU_RASR_A1_SIZE_Pos = 0x1
	// Bit mask of SIZE field.
	MPU_RASR_A1_SIZE_Msk = 0x2
	// Bit SIZE.
	MPU_RASR_A1_SIZE = 0x2
	// Position of SRD field.
	MPU_RASR_A1_SRD_Pos = 0x8
	// Bit mask of SRD field.
	MPU_RASR_A1_SRD_Msk = 0xff00
	// Position of B field.
	MPU_RASR_A1_B_Pos = 0x10
	// Bit mask of B field.
	MPU_RASR_A1_B_Msk = 0x10000
	// Bit B.
	MPU_RASR_A1_B = 0x10000
	// Position of C field.
	MPU_RASR_A1_C_Pos = 0x11
	// Bit mask of C field.
	MPU_RASR_A1_C_Msk = 0x20000
	// Bit C.
	MPU_RASR_A1_C = 0x20000
	// Position of S field.
	MPU_RASR_A1_S_Pos = 0x12
	// Bit mask of S field.
	MPU_RASR_A1_S_Msk = 0x40000
	// Bit S.
	MPU_RASR_A1_S = 0x40000
	// Position of TEX field.
	MPU_RASR_A1_TEX_Pos = 0x13
	// Bit mask of TEX field.
	MPU_RASR_A1_TEX_Msk = 0x380000
	// Position of AP field.
	MPU_RASR_A1_AP_Pos = 0x18
	// Bit mask of AP field.
	MPU_RASR_A1_AP_Msk = 0x7000000
	// Position of XN field.
	MPU_RASR_A1_XN_Pos = 0x1c
	// Bit mask of XN field.
	MPU_RASR_A1_XN_Msk = 0x10000000
	// Bit XN.
	MPU_RASR_A1_XN = 0x10000000

	// RBAR_A2: MPU Alias 2 Region Base Address Register
	// Position of REGION field.
	MPU_RBAR_A2_REGION_Pos = 0x0
	// Bit mask of REGION field.
	MPU_RBAR_A2_REGION_Msk = 0xf
	// Position of VALID field.
	MPU_RBAR_A2_VALID_Pos = 0x4
	// Bit mask of VALID field.
	MPU_RBAR_A2_VALID_Msk = 0x10
	// Bit VALID.
	MPU_RBAR_A2_VALID = 0x10
	// Position of ADDR field.
	MPU_RBAR_A2_ADDR_Pos = 0x5
	// Bit mask of ADDR field.
	MPU_RBAR_A2_ADDR_Msk = 0xffffffe0

	// RASR_A2: MPU Alias 2 Region Attribute and Size Register
	// Position of ENABLE field.
	MPU_RASR_A2_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	MPU_RASR_A2_ENABLE_Msk = 0x1
	// Bit ENABLE.
	MPU_RASR_A2_ENABLE = 0x1
	// Position of SIZE field.
	MPU_RASR_A2_SIZE_Pos = 0x1
	// Bit mask of SIZE field.
	MPU_RASR_A2_SIZE_Msk = 0x2
	// Bit SIZE.
	MPU_RASR_A2_SIZE = 0x2
	// Position of SRD field.
	MPU_RASR_A2_SRD_Pos = 0x8
	// Bit mask of SRD field.
	MPU_RASR_A2_SRD_Msk = 0xff00
	// Position of B field.
	MPU_RASR_A2_B_Pos = 0x10
	// Bit mask of B field.
	MPU_RASR_A2_B_Msk = 0x10000
	// Bit B.
	MPU_RASR_A2_B = 0x10000
	// Position of C field.
	MPU_RASR_A2_C_Pos = 0x11
	// Bit mask of C field.
	MPU_RASR_A2_C_Msk = 0x20000
	// Bit C.
	MPU_RASR_A2_C = 0x20000
	// Position of S field.
	MPU_RASR_A2_S_Pos = 0x12
	// Bit mask of S field.
	MPU_RASR_A2_S_Msk = 0x40000
	// Bit S.
	MPU_RASR_A2_S = 0x40000
	// Position of TEX field.
	MPU_RASR_A2_TEX_Pos = 0x13
	// Bit mask of TEX field.
	MPU_RASR_A2_TEX_Msk = 0x380000
	// Position of AP field.
	MPU_RASR_A2_AP_Pos = 0x18
	// Bit mask of AP field.
	MPU_RASR_A2_AP_Msk = 0x7000000
	// Position of XN field.
	MPU_RASR_A2_XN_Pos = 0x1c
	// Bit mask of XN field.
	MPU_RASR_A2_XN_Msk = 0x10000000
	// Bit XN.
	MPU_RASR_A2_XN = 0x10000000

	// RBAR_A3: MPU Alias 3 Region Base Address Register
	// Position of REGION field.
	MPU_RBAR_A3_REGION_Pos = 0x0
	// Bit mask of REGION field.
	MPU_RBAR_A3_REGION_Msk = 0xf
	// Position of VALID field.
	MPU_RBAR_A3_VALID_Pos = 0x4
	// Bit mask of VALID field.
	MPU_RBAR_A3_VALID_Msk = 0x10
	// Bit VALID.
	MPU_RBAR_A3_VALID = 0x10
	// Position of ADDR field.
	MPU_RBAR_A3_ADDR_Pos = 0x5
	// Bit mask of ADDR field.
	MPU_RBAR_A3_ADDR_Msk = 0xffffffe0

	// RASR_A3: MPU Alias 3 Region Attribute and Size Register
	// Position of ENABLE field.
	MPU_RASR_A3_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	MPU_RASR_A3_ENABLE_Msk = 0x1
	// Bit ENABLE.
	MPU_RASR_A3_ENABLE = 0x1
	// Position of SIZE field.
	MPU_RASR_A3_SIZE_Pos = 0x1
	// Bit mask of SIZE field.
	MPU_RASR_A3_SIZE_Msk = 0x2
	// Bit SIZE.
	MPU_RASR_A3_SIZE = 0x2
	// Position of SRD field.
	MPU_RASR_A3_SRD_Pos = 0x8
	// Bit mask of SRD field.
	MPU_RASR_A3_SRD_Msk = 0xff00
	// Position of B field.
	MPU_RASR_A3_B_Pos = 0x10
	// Bit mask of B field.
	MPU_RASR_A3_B_Msk = 0x10000
	// Bit B.
	MPU_RASR_A3_B = 0x10000
	// Position of C field.
	MPU_RASR_A3_C_Pos = 0x11
	// Bit mask of C field.
	MPU_RASR_A3_C_Msk = 0x20000
	// Bit C.
	MPU_RASR_A3_C = 0x20000
	// Position of S field.
	MPU_RASR_A3_S_Pos = 0x12
	// Bit mask of S field.
	MPU_RASR_A3_S_Msk = 0x40000
	// Bit S.
	MPU_RASR_A3_S = 0x40000
	// Position of TEX field.
	MPU_RASR_A3_TEX_Pos = 0x13
	// Bit mask of TEX field.
	MPU_RASR_A3_TEX_Msk = 0x380000
	// Position of AP field.
	MPU_RASR_A3_AP_Pos = 0x18
	// Bit mask of AP field.
	MPU_RASR_A3_AP_Msk = 0x7000000
	// Position of XN field.
	MPU_RASR_A3_XN_Pos = 0x1c
	// Bit mask of XN field.
	MPU_RASR_A3_XN_Msk = 0x10000000
	// Bit XN.
	MPU_RASR_A3_XN = 0x10000000
)

// Bitfields for NVIC: Nested Vectored Interrupt Controller
const (
	// ISER: Interrupt Set Enable Register
	// Position of SETENA field.
	NVIC_ISER_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER_SETENA_Msk = 0xffffffff

	// ICER: Interrupt Clear Enable Register
	// Position of CLRENA field.
	NVIC_ICER_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER_CLRENA_Msk = 0xffffffff

	// ISPR: Interrupt Set Pending Register
	// Position of SETPEND field.
	NVIC_ISPR_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR_SETPEND_Msk = 0xffffffff

	// ICPR: Interrupt Clear Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR_CLRPEND_Msk = 0xffffffff

	// IABR: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR_ACTIVE_Msk = 0xffffffff

	// IP: Interrupt Priority Register n
	// Position of PRI0 field.
	NVIC_IP_PRI0_Pos = 0x0
	// Bit mask of PRI0 field.
	NVIC_IP_PRI0_Msk = 0x7

	// STIR: Software Trigger Interrupt Register
	// Position of INTID field.
	NVIC_STIR_INTID_Pos = 0x0
	// Bit mask of INTID field.
	NVIC_STIR_INTID_Msk = 0x1ff
)

// Bitfields for SysTick: System timer
const (
	// CSR: SysTick Control and Status Register
	// Position of ENABLE field.
	SysTick_CSR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	SysTick_CSR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	SysTick_CSR_ENABLE = 0x1
	// Counter disabled
	SysTick_CSR_ENABLE_VALUE_0 = 0x0
	// Counter enabled
	SysTick_CSR_ENABLE_VALUE_1 = 0x1
	// Position of TICKINT field.
	SysTick_CSR_TICKINT_Pos = 0x1
	// Bit mask of TICKINT field.
	SysTick_CSR_TICKINT_Msk = 0x2
	// Bit TICKINT.
	SysTick_CSR_TICKINT = 0x2
	// Counting down to 0 does not assert the SysTick exception request
	SysTick_CSR_TICKINT_VALUE_0 = 0x0
	// Counting down to 0 asserts the SysTick exception request
	SysTick_CSR_TICKINT_VALUE_1 = 0x1
	// Position of CLKSOURCE field.
	SysTick_CSR_CLKSOURCE_Pos = 0x2
	// Bit mask of CLKSOURCE field.
	SysTick_CSR_CLKSOURCE_Msk = 0x4
	// Bit CLKSOURCE.
	SysTick_CSR_CLKSOURCE = 0x4
	// External clock
	SysTick_CSR_CLKSOURCE_VALUE_0 = 0x0
	// Processor clock
	SysTick_CSR_CLKSOURCE_VALUE_1 = 0x1
	// Position of COUNTFLAG field.
	SysTick_CSR_COUNTFLAG_Pos = 0x10
	// Bit mask of COUNTFLAG field.
	SysTick_CSR_COUNTFLAG_Msk = 0x10000
	// Bit COUNTFLAG.
	SysTick_CSR_COUNTFLAG = 0x10000

	// RVR: SysTick Reload Value Register
	// Position of RELOAD field.
	SysTick_RVR_RELOAD_Pos = 0x0
	// Bit mask of RELOAD field.
	SysTick_RVR_RELOAD_Msk = 0xffffff

	// CVR: SysTick Current Value Register
	// Position of CURRENT field.
	SysTick_CVR_CURRENT_Pos = 0x0
	// Bit mask of CURRENT field.
	SysTick_CVR_CURRENT_Msk = 0xffffff

	// CALIB: SysTick Calibration Value Register
	// Position of TENMS field.
	SysTick_CALIB_TENMS_Pos = 0x0
	// Bit mask of TENMS field.
	SysTick_CALIB_TENMS_Msk = 0xffffff
	// Position of SKEW field.
	SysTick_CALIB_SKEW_Pos = 0x1e
	// Bit mask of SKEW field.
	SysTick_CALIB_SKEW_Msk = 0x40000000
	// Bit SKEW.
	SysTick_CALIB_SKEW = 0x40000000
	// 10ms calibration value is exact
	SysTick_CALIB_SKEW_VALUE_0 = 0x0
	// 10ms calibration value is inexact, because of the clock frequency
	SysTick_CALIB_SKEW_VALUE_1 = 0x1
	// Position of NOREF field.
	SysTick_CALIB_NOREF_Pos = 0x1f
	// Bit mask of NOREF field.
	SysTick_CALIB_NOREF_Msk = 0x80000000
	// Bit NOREF.
	SysTick_CALIB_NOREF = 0x80000000
	// The reference clock is provided
	SysTick_CALIB_NOREF_VALUE_0 = 0x0
	// The reference clock is not provided
	SysTick_CALIB_NOREF_VALUE_1 = 0x1
)

// Bitfields for SystemControl: System Control Registers
const (
	// ICTR: Interrupt Controller Type Register
	// Position of INTLINESNUM field.
	SystemControl_ICTR_INTLINESNUM_Pos = 0x0
	// Bit mask of INTLINESNUM field.
	SystemControl_ICTR_INTLINESNUM_Msk = 0xf

	// ACTLR: Auxiliary Control Register
	// Position of DISMCYCINT field.
	SystemControl_ACTLR_DISMCYCINT_Pos = 0x0
	// Bit mask of DISMCYCINT field.
	SystemControl_ACTLR_DISMCYCINT_Msk = 0x1
	// Bit DISMCYCINT.
	SystemControl_ACTLR_DISMCYCINT = 0x1
	// Position of DISDEFWBUF field.
	SystemControl_ACTLR_DISDEFWBUF_Pos = 0x1
	// Bit mask of DISDEFWBUF field.
	SystemControl_ACTLR_DISDEFWBUF_Msk = 0x2
	// Bit DISDEFWBUF.
	SystemControl_ACTLR_DISDEFWBUF = 0x2
	// Position of DISFOLD field.
	SystemControl_ACTLR_DISFOLD_Pos = 0x2
	// Bit mask of DISFOLD field.
	SystemControl_ACTLR_DISFOLD_Msk = 0x4
	// Bit DISFOLD.
	SystemControl_ACTLR_DISFOLD = 0x4
	// Position of DISFPCA field.
	SystemControl_ACTLR_DISFPCA_Pos = 0x8
	// Bit mask of DISFPCA field.
	SystemControl_ACTLR_DISFPCA_Msk = 0x100
	// Bit DISFPCA.
	SystemControl_ACTLR_DISFPCA = 0x100
	// Position of DISOOFP field.
	SystemControl_ACTLR_DISOOFP_Pos = 0x9
	// Bit mask of DISOOFP field.
	SystemControl_ACTLR_DISOOFP_Msk = 0x200
	// Bit DISOOFP.
	SystemControl_ACTLR_DISOOFP = 0x200

	// CPUID: CPUID Base Register
	// Position of REVISION field.
	SystemControl_CPUID_REVISION_Pos = 0x0
	// Bit mask of REVISION field.
	SystemControl_CPUID_REVISION_Msk = 0xf
	// Position of PARTNO field.
	SystemControl_CPUID_PARTNO_Pos = 0x4
	// Bit mask of PARTNO field.
	SystemControl_CPUID_PARTNO_Msk = 0xfff0
	// Position of CONSTANT field.
	SystemControl_CPUID_CONSTANT_Pos = 0x10
	// Bit mask of CONSTANT field.
	SystemControl_CPUID_CONSTANT_Msk = 0xf0000
	// Position of VARIANT field.
	SystemControl_CPUID_VARIANT_Pos = 0x14
	// Bit mask of VARIANT field.
	SystemControl_CPUID_VARIANT_Msk = 0xf00000
	// Position of IMPLEMENTER field.
	SystemControl_CPUID_IMPLEMENTER_Pos = 0x18
	// Bit mask of IMPLEMENTER field.
	SystemControl_CPUID_IMPLEMENTER_Msk = 0xff000000

	// ICSR: Interrupt Control and State Register
	// Position of VECTACTIVE field.
	SystemControl_ICSR_VECTACTIVE_Pos = 0x0
	// Bit mask of VECTACTIVE field.
	SystemControl_ICSR_VECTACTIVE_Msk = 0x1ff
	// Position of RETTOBASE field.
	SystemControl_ICSR_RETTOBASE_Pos = 0xb
	// Bit mask of RETTOBASE field.
	SystemControl_ICSR_RETTOBASE_Msk = 0x800
	// Bit RETTOBASE.
	SystemControl_ICSR_RETTOBASE = 0x800
	// Position of VECTPENDING field.
	SystemControl_ICSR_VECTPENDING_Pos = 0xc
	// Bit mask of VECTPENDING field.
	SystemControl_ICSR_VECTPENDING_Msk = 0x3f000
	// Position of ISRPENDING field.
	SystemControl_ICSR_ISRPENDING_Pos = 0x16
	// Bit mask of ISRPENDING field.
	SystemControl_ICSR_ISRPENDING_Msk = 0x400000
	// Bit ISRPENDING.
	SystemControl_ICSR_ISRPENDING = 0x400000
	// Position of ISRPREEMPT field.
	SystemControl_ICSR_ISRPREEMPT_Pos = 0x17
	// Bit mask of ISRPREEMPT field.
	SystemControl_ICSR_ISRPREEMPT_Msk = 0x800000
	// Bit ISRPREEMPT.
	SystemControl_ICSR_ISRPREEMPT = 0x800000
	// Position of PENDSTCLR field.
	SystemControl_ICSR_PENDSTCLR_Pos = 0x19
	// Bit mask of PENDSTCLR field.
	SystemControl_ICSR_PENDSTCLR_Msk = 0x2000000
	// Bit PENDSTCLR.
	SystemControl_ICSR_PENDSTCLR = 0x2000000
	// No effect
	SystemControl_ICSR_PENDSTCLR_VALUE_0 = 0x0
	// Removes the pending state from the SysTick exception
	SystemControl_ICSR_PENDSTCLR_VALUE_1 = 0x1
	// Position of PENDSTSET field.
	SystemControl_ICSR_PENDSTSET_Pos = 0x1a
	// Bit mask of PENDSTSET field.
	SystemControl_ICSR_PENDSTSET_Msk = 0x4000000
	// Bit PENDSTSET.
	SystemControl_ICSR_PENDSTSET = 0x4000000
	// Write: no effect; read: SysTick exception is not pending
	SystemControl_ICSR_PENDSTSET_VALUE_0 = 0x0
	// Write: changes SysTick exception state to pending; read: SysTick exception is pending
	SystemControl_ICSR_PENDSTSET_VALUE_1 = 0x1
	// Position of PENDSVCLR field.
	SystemControl_ICSR_PENDSVCLR_Pos = 0x1b
	// Bit mask of PENDSVCLR field.
	SystemControl_ICSR_PENDSVCLR_Msk = 0x8000000
	// Bit PENDSVCLR.
	SystemControl_ICSR_PENDSVCLR = 0x8000000
	// No effect
	SystemControl_ICSR_PENDSVCLR_VALUE_0 = 0x0
	// Removes the pending state from the PendSV exception
	SystemControl_ICSR_PENDSVCLR_VALUE_1 = 0x1
	// Position of PENDSVSET field.
	SystemControl_ICSR_PENDSVSET_Pos = 0x1c
	// Bit mask of PENDSVSET field.
	SystemControl_ICSR_PENDSVSET_Msk = 0x10000000
	// Bit PENDSVSET.
	SystemControl_ICSR_PENDSVSET = 0x10000000
	// Write: no effect; read: PendSV exception is not pending
	SystemControl_ICSR_PENDSVSET_VALUE_0 = 0x0
	// Write: changes PendSV exception state to pending; read: PendSV exception is pending
	SystemControl_ICSR_PENDSVSET_VALUE_1 = 0x1
	// Position of NMIPENDSET field.
	SystemControl_ICSR_NMIPENDSET_Pos = 0x1f
	// Bit mask of NMIPENDSET field.
	SystemControl_ICSR_NMIPENDSET_Msk = 0x80000000
	// Bit NMIPENDSET.
	SystemControl_ICSR_NMIPENDSET = 0x80000000
	// Write: no effect; read: NMI exception is not pending
	SystemControl_ICSR_NMIPENDSET_VALUE_0 = 0x0
	// Write: changes NMI exception state to pending; read: NMI exception is pending
	SystemControl_ICSR_NMIPENDSET_VALUE_1 = 0x1

	// VTOR: Vector Table Offset Register
	// Position of TBLOFF field.
	SystemControl_VTOR_TBLOFF_Pos = 0x7
	// Bit mask of TBLOFF field.
	SystemControl_VTOR_TBLOFF_Msk = 0xffffff80

	// AIRCR: Application Interrupt and Reset Control Register
	// Position of VECTRESET field.
	SystemControl_AIRCR_VECTRESET_Pos = 0x0
	// Bit mask of VECTRESET field.
	SystemControl_AIRCR_VECTRESET_Msk = 0x1
	// Bit VECTRESET.
	SystemControl_AIRCR_VECTRESET = 0x1
	// Position of VECTCLRACTIVE field.
	SystemControl_AIRCR_VECTCLRACTIVE_Pos = 0x1
	// Bit mask of VECTCLRACTIVE field.
	SystemControl_AIRCR_VECTCLRACTIVE_Msk = 0x2
	// Bit VECTCLRACTIVE.
	SystemControl_AIRCR_VECTCLRACTIVE = 0x2
	// Position of SYSRESETREQ field.
	SystemControl_AIRCR_SYSRESETREQ_Pos = 0x2
	// Bit mask of SYSRESETREQ field.
	SystemControl_AIRCR_SYSRESETREQ_Msk = 0x4
	// Bit SYSRESETREQ.
	SystemControl_AIRCR_SYSRESETREQ = 0x4
	// No system reset request
	SystemControl_AIRCR_SYSRESETREQ_VALUE_0 = 0x0
	// Asserts a signal to the outer system that requests a reset
	SystemControl_AIRCR_SYSRESETREQ_VALUE_1 = 0x1
	// Position of PRIGROUP field.
	SystemControl_AIRCR_PRIGROUP_Pos = 0x8
	// Bit mask of PRIGROUP field.
	SystemControl_AIRCR_PRIGROUP_Msk = 0x700
	// Position of ENDIANNESS field.
	SystemControl_AIRCR_ENDIANNESS_Pos = 0xf
	// Bit mask of ENDIANNESS field.
	SystemControl_AIRCR_ENDIANNESS_Msk = 0x8000
	// Bit ENDIANNESS.
	SystemControl_AIRCR_ENDIANNESS = 0x8000
	// Little-endian
	SystemControl_AIRCR_ENDIANNESS_VALUE_0 = 0x0
	// Big-endian
	SystemControl_AIRCR_ENDIANNESS_VALUE_1 = 0x1
	// Position of VECTKEY field.
	SystemControl_AIRCR_VECTKEY_Pos = 0x10
	// Bit mask of VECTKEY field.
	SystemControl_AIRCR_VECTKEY_Msk = 0xffff0000

	// SCR: System Control Register
	// Position of SLEEPONEXIT field.
	SystemControl_SCR_SLEEPONEXIT_Pos = 0x1
	// Bit mask of SLEEPONEXIT field.
	SystemControl_SCR_SLEEPONEXIT_Msk = 0x2
	// Bit SLEEPONEXIT.
	SystemControl_SCR_SLEEPONEXIT = 0x2
	// Do not sleep when returning to Thread mode
	SystemControl_SCR_SLEEPONEXIT_VALUE_0 = 0x0
	// Enter sleep, or deep sleep, on return from an ISR
	SystemControl_SCR_SLEEPONEXIT_VALUE_1 = 0x1
	// Position of SLEEPDEEP field.
	SystemControl_SCR_SLEEPDEEP_Pos = 0x2
	// Bit mask of SLEEPDEEP field.
	SystemControl_SCR_SLEEPDEEP_Msk = 0x4
	// Bit SLEEPDEEP.
	SystemControl_SCR_SLEEPDEEP = 0x4
	// Sleep
	SystemControl_SCR_SLEEPDEEP_VALUE_0 = 0x0
	// Deep sleep
	SystemControl_SCR_SLEEPDEEP_VALUE_1 = 0x1
	// Position of SEVONPEND field.
	SystemControl_SCR_SEVONPEND_Pos = 0x4
	// Bit mask of SEVONPEND field.
	SystemControl_SCR_SEVONPEND_Msk = 0x10
	// Bit SEVONPEND.
	SystemControl_SCR_SEVONPEND = 0x10
	// Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
	SystemControl_SCR_SEVONPEND_VALUE_0 = 0x0
	// Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
	SystemControl_SCR_SEVONPEND_VALUE_1 = 0x1

	// CCR: Configuration and Control Register
	// Position of NONBASETHRDENA field.
	SystemControl_CCR_NONBASETHRDENA_Pos = 0x0
	// Bit mask of NONBASETHRDENA field.
	SystemControl_CCR_NONBASETHRDENA_Msk = 0x1
	// Bit NONBASETHRDENA.
	SystemControl_CCR_NONBASETHRDENA = 0x1
	// Position of USERSETMPEND field.
	SystemControl_CCR_USERSETMPEND_Pos = 0x1
	// Bit mask of USERSETMPEND field.
	SystemControl_CCR_USERSETMPEND_Msk = 0x2
	// Bit USERSETMPEND.
	SystemControl_CCR_USERSETMPEND = 0x2
	// Position of UNALIGN_TRP field.
	SystemControl_CCR_UNALIGN_TRP_Pos = 0x3
	// Bit mask of UNALIGN_TRP field.
	SystemControl_CCR_UNALIGN_TRP_Msk = 0x8
	// Bit UNALIGN_TRP.
	SystemControl_CCR_UNALIGN_TRP = 0x8
	// Do not trap unaligned halfword and word accesses
	SystemControl_CCR_UNALIGN_TRP_VALUE_0 = 0x0
	// Trap unaligned halfword and word accesses
	SystemControl_CCR_UNALIGN_TRP_VALUE_1 = 0x1
	// Position of DIV_0_TRP field.
	SystemControl_CCR_DIV_0_TRP_Pos = 0x4
	// Bit mask of DIV_0_TRP field.
	SystemControl_CCR_DIV_0_TRP_Msk = 0x10
	// Bit DIV_0_TRP.
	SystemControl_CCR_DIV_0_TRP = 0x10
	// Position of BFHFNMIGN field.
	SystemControl_CCR_BFHFNMIGN_Pos = 0x8
	// Bit mask of BFHFNMIGN field.
	SystemControl_CCR_BFHFNMIGN_Msk = 0x100
	// Bit BFHFNMIGN.
	SystemControl_CCR_BFHFNMIGN = 0x100
	// Position of STKALIGN field.
	SystemControl_CCR_STKALIGN_Pos = 0x9
	// Bit mask of STKALIGN field.
	SystemControl_CCR_STKALIGN_Msk = 0x200
	// Bit STKALIGN.
	SystemControl_CCR_STKALIGN = 0x200
	// 4-byte aligned
	SystemControl_CCR_STKALIGN_VALUE_0 = 0x0
	// 8-byte aligned
	SystemControl_CCR_STKALIGN_VALUE_1 = 0x1

	// SHPR1: System Handler Priority Register 1
	// Position of PRI_4 field.
	SystemControl_SHPR1_PRI_4_Pos = 0x0
	// Bit mask of PRI_4 field.
	SystemControl_SHPR1_PRI_4_Msk = 0xff
	// Position of PRI_5 field.
	SystemControl_SHPR1_PRI_5_Pos = 0x8
	// Bit mask of PRI_5 field.
	SystemControl_SHPR1_PRI_5_Msk = 0xff00
	// Position of PRI_6 field.
	SystemControl_SHPR1_PRI_6_Pos = 0x10
	// Bit mask of PRI_6 field.
	SystemControl_SHPR1_PRI_6_Msk = 0xff0000

	// SHPR2: System Handler Priority Register 2
	// Position of PRI_11 field.
	SystemControl_SHPR2_PRI_11_Pos = 0x18
	// Bit mask of PRI_11 field.
	SystemControl_SHPR2_PRI_11_Msk = 0xff000000

	// SHPR3: System Handler Priority Register 3
	// Position of PRI_14 field.
	SystemControl_SHPR3_PRI_14_Pos = 0x10
	// Bit mask of PRI_14 field.
	SystemControl_SHPR3_PRI_14_Msk = 0xff0000
	// Position of PRI_15 field.
	SystemControl_SHPR3_PRI_15_Pos = 0x18
	// Bit mask of PRI_15 field.
	SystemControl_SHPR3_PRI_15_Msk = 0xff000000

	// SHCSR: System Handler Control and State Register
	// Position of MEMFAULTACT field.
	SystemControl_SHCSR_MEMFAULTACT_Pos = 0x0
	// Bit mask of MEMFAULTACT field.
	SystemControl_SHCSR_MEMFAULTACT_Msk = 0x1
	// Bit MEMFAULTACT.
	SystemControl_SHCSR_MEMFAULTACT = 0x1
	// Position of BUSFAULTACT field.
	SystemControl_SHCSR_BUSFAULTACT_Pos = 0x1
	// Bit mask of BUSFAULTACT field.
	SystemControl_SHCSR_BUSFAULTACT_Msk = 0x2
	// Bit BUSFAULTACT.
	SystemControl_SHCSR_BUSFAULTACT = 0x2
	// Position of USGFAULTACT field.
	SystemControl_SHCSR_USGFAULTACT_Pos = 0x3
	// Bit mask of USGFAULTACT field.
	SystemControl_SHCSR_USGFAULTACT_Msk = 0x8
	// Bit USGFAULTACT.
	SystemControl_SHCSR_USGFAULTACT = 0x8
	// Position of SVCALLACT field.
	SystemControl_SHCSR_SVCALLACT_Pos = 0x7
	// Bit mask of SVCALLACT field.
	SystemControl_SHCSR_SVCALLACT_Msk = 0x80
	// Bit SVCALLACT.
	SystemControl_SHCSR_SVCALLACT = 0x80
	// Position of MONITORACT field.
	SystemControl_SHCSR_MONITORACT_Pos = 0x8
	// Bit mask of MONITORACT field.
	SystemControl_SHCSR_MONITORACT_Msk = 0x100
	// Bit MONITORACT.
	SystemControl_SHCSR_MONITORACT = 0x100
	// Position of PENDSVACT field.
	SystemControl_SHCSR_PENDSVACT_Pos = 0xa
	// Bit mask of PENDSVACT field.
	SystemControl_SHCSR_PENDSVACT_Msk = 0x400
	// Bit PENDSVACT.
	SystemControl_SHCSR_PENDSVACT = 0x400
	// Position of SYSTICKACT field.
	SystemControl_SHCSR_SYSTICKACT_Pos = 0xb
	// Bit mask of SYSTICKACT field.
	SystemControl_SHCSR_SYSTICKACT_Msk = 0x800
	// Bit SYSTICKACT.
	SystemControl_SHCSR_SYSTICKACT = 0x800
	// Position of USGFAULTPENDED field.
	SystemControl_SHCSR_USGFAULTPENDED_Pos = 0xc
	// Bit mask of USGFAULTPENDED field.
	SystemControl_SHCSR_USGFAULTPENDED_Msk = 0x1000
	// Bit USGFAULTPENDED.
	SystemControl_SHCSR_USGFAULTPENDED = 0x1000
	// Position of MEMFAULTPENDED field.
	SystemControl_SHCSR_MEMFAULTPENDED_Pos = 0xd
	// Bit mask of MEMFAULTPENDED field.
	SystemControl_SHCSR_MEMFAULTPENDED_Msk = 0x2000
	// Bit MEMFAULTPENDED.
	SystemControl_SHCSR_MEMFAULTPENDED = 0x2000
	// Position of BUSFAULTPENDED field.
	SystemControl_SHCSR_BUSFAULTPENDED_Pos = 0xe
	// Bit mask of BUSFAULTPENDED field.
	SystemControl_SHCSR_BUSFAULTPENDED_Msk = 0x4000
	// Bit BUSFAULTPENDED.
	SystemControl_SHCSR_BUSFAULTPENDED = 0x4000
	// Position of SVCALLPENDED field.
	SystemControl_SHCSR_SVCALLPENDED_Pos = 0xf
	// Bit mask of SVCALLPENDED field.
	SystemControl_SHCSR_SVCALLPENDED_Msk = 0x8000
	// Bit SVCALLPENDED.
	SystemControl_SHCSR_SVCALLPENDED = 0x8000
	// Position of MEMFAULTENA field.
	SystemControl_SHCSR_MEMFAULTENA_Pos = 0x10
	// Bit mask of MEMFAULTENA field.
	SystemControl_SHCSR_MEMFAULTENA_Msk = 0x10000
	// Bit MEMFAULTENA.
	SystemControl_SHCSR_MEMFAULTENA = 0x10000
	// Position of BUSFAULTENA field.
	SystemControl_SHCSR_BUSFAULTENA_Pos = 0x11
	// Bit mask of BUSFAULTENA field.
	SystemControl_SHCSR_BUSFAULTENA_Msk = 0x20000
	// Bit BUSFAULTENA.
	SystemControl_SHCSR_BUSFAULTENA = 0x20000
	// Position of USGFAULTENA field.
	SystemControl_SHCSR_USGFAULTENA_Pos = 0x12
	// Bit mask of USGFAULTENA field.
	SystemControl_SHCSR_USGFAULTENA_Msk = 0x40000
	// Bit USGFAULTENA.
	SystemControl_SHCSR_USGFAULTENA = 0x40000

	// CFSR: Configurable Fault Status Register
	// Position of IACCVIOL field.
	SystemControl_CFSR_IACCVIOL_Pos = 0x0
	// Bit mask of IACCVIOL field.
	SystemControl_CFSR_IACCVIOL_Msk = 0x1
	// Bit IACCVIOL.
	SystemControl_CFSR_IACCVIOL = 0x1
	// Position of DACCVIOL field.
	SystemControl_CFSR_DACCVIOL_Pos = 0x1
	// Bit mask of DACCVIOL field.
	SystemControl_CFSR_DACCVIOL_Msk = 0x2
	// Bit DACCVIOL.
	SystemControl_CFSR_DACCVIOL = 0x2
	// Position of MUNSTKERR field.
	SystemControl_CFSR_MUNSTKERR_Pos = 0x3
	// Bit mask of MUNSTKERR field.
	SystemControl_CFSR_MUNSTKERR_Msk = 0x8
	// Bit MUNSTKERR.
	SystemControl_CFSR_MUNSTKERR = 0x8
	// Position of MSTKERR field.
	SystemControl_CFSR_MSTKERR_Pos = 0x4
	// Bit mask of MSTKERR field.
	SystemControl_CFSR_MSTKERR_Msk = 0x10
	// Bit MSTKERR.
	SystemControl_CFSR_MSTKERR = 0x10
	// Position of MLSPERR field.
	SystemControl_CFSR_MLSPERR_Pos = 0x5
	// Bit mask of MLSPERR field.
	SystemControl_CFSR_MLSPERR_Msk = 0x20
	// Bit MLSPERR.
	SystemControl_CFSR_MLSPERR = 0x20
	// Position of MMARVALID field.
	SystemControl_CFSR_MMARVALID_Pos = 0x7
	// Bit mask of MMARVALID field.
	SystemControl_CFSR_MMARVALID_Msk = 0x80
	// Bit MMARVALID.
	SystemControl_CFSR_MMARVALID = 0x80
	// Position of IBUSERR field.
	SystemControl_CFSR_IBUSERR_Pos = 0x8
	// Bit mask of IBUSERR field.
	SystemControl_CFSR_IBUSERR_Msk = 0x100
	// Bit IBUSERR.
	SystemControl_CFSR_IBUSERR = 0x100
	// Position of PRECISERR field.
	SystemControl_CFSR_PRECISERR_Pos = 0x9
	// Bit mask of PRECISERR field.
	SystemControl_CFSR_PRECISERR_Msk = 0x200
	// Bit PRECISERR.
	SystemControl_CFSR_PRECISERR = 0x200
	// Position of IMPRECISERR field.
	SystemControl_CFSR_IMPRECISERR_Pos = 0xa
	// Bit mask of IMPRECISERR field.
	SystemControl_CFSR_IMPRECISERR_Msk = 0x400
	// Bit IMPRECISERR.
	SystemControl_CFSR_IMPRECISERR = 0x400
	// Position of UNSTKERR field.
	SystemControl_CFSR_UNSTKERR_Pos = 0xb
	// Bit mask of UNSTKERR field.
	SystemControl_CFSR_UNSTKERR_Msk = 0x800
	// Bit UNSTKERR.
	SystemControl_CFSR_UNSTKERR = 0x800
	// Position of STKERR field.
	SystemControl_CFSR_STKERR_Pos = 0xc
	// Bit mask of STKERR field.
	SystemControl_CFSR_STKERR_Msk = 0x1000
	// Bit STKERR.
	SystemControl_CFSR_STKERR = 0x1000
	// Position of LSPERR field.
	SystemControl_CFSR_LSPERR_Pos = 0xd
	// Bit mask of LSPERR field.
	SystemControl_CFSR_LSPERR_Msk = 0x2000
	// Bit LSPERR.
	SystemControl_CFSR_LSPERR = 0x2000
	// Position of BFARVALID field.
	SystemControl_CFSR_BFARVALID_Pos = 0xf
	// Bit mask of BFARVALID field.
	SystemControl_CFSR_BFARVALID_Msk = 0x8000
	// Bit BFARVALID.
	SystemControl_CFSR_BFARVALID = 0x8000
	// Position of UNDEFINSTR field.
	SystemControl_CFSR_UNDEFINSTR_Pos = 0x10
	// Bit mask of UNDEFINSTR field.
	SystemControl_CFSR_UNDEFINSTR_Msk = 0x10000
	// Bit UNDEFINSTR.
	SystemControl_CFSR_UNDEFINSTR = 0x10000
	// Position of INVSTATE field.
	SystemControl_CFSR_INVSTATE_Pos = 0x11
	// Bit mask of INVSTATE field.
	SystemControl_CFSR_INVSTATE_Msk = 0x20000
	// Bit INVSTATE.
	SystemControl_CFSR_INVSTATE = 0x20000
	// Position of INVPC field.
	SystemControl_CFSR_INVPC_Pos = 0x12
	// Bit mask of INVPC field.
	SystemControl_CFSR_INVPC_Msk = 0x40000
	// Bit INVPC.
	SystemControl_CFSR_INVPC = 0x40000
	// Position of NOCP field.
	SystemControl_CFSR_NOCP_Pos = 0x13
	// Bit mask of NOCP field.
	SystemControl_CFSR_NOCP_Msk = 0x80000
	// Bit NOCP.
	SystemControl_CFSR_NOCP = 0x80000
	// Position of UNALIGNED field.
	SystemControl_CFSR_UNALIGNED_Pos = 0x18
	// Bit mask of UNALIGNED field.
	SystemControl_CFSR_UNALIGNED_Msk = 0x1000000
	// Bit UNALIGNED.
	SystemControl_CFSR_UNALIGNED = 0x1000000
	// Position of DIVBYZERO field.
	SystemControl_CFSR_DIVBYZERO_Pos = 0x19
	// Bit mask of DIVBYZERO field.
	SystemControl_CFSR_DIVBYZERO_Msk = 0x2000000
	// Bit DIVBYZERO.
	SystemControl_CFSR_DIVBYZERO = 0x2000000

	// HFSR: HardFault Status Register
	// Position of VECTTBL field.
	SystemControl_HFSR_VECTTBL_Pos = 0x1
	// Bit mask of VECTTBL field.
	SystemControl_HFSR_VECTTBL_Msk = 0x2
	// Bit VECTTBL.
	SystemControl_HFSR_VECTTBL = 0x2
	// Position of FORCED field.
	SystemControl_HFSR_FORCED_Pos = 0x1e
	// Bit mask of FORCED field.
	SystemControl_HFSR_FORCED_Msk = 0x40000000
	// Bit FORCED.
	SystemControl_HFSR_FORCED = 0x40000000
	// Position of DEBUGEVT field.
	SystemControl_HFSR_DEBUGEVT_Pos = 0x1f
	// Bit mask of DEBUGEVT field.
	SystemControl_HFSR_DEBUGEVT_Msk = 0x80000000
	// Bit DEBUGEVT.
	SystemControl_HFSR_DEBUGEVT = 0x80000000

	// DFSR: Debug Fault Status Register
	// Position of HALTED field.
	SystemControl_DFSR_HALTED_Pos = 0x0
	// Bit mask of HALTED field.
	SystemControl_DFSR_HALTED_Msk = 0x1
	// Bit HALTED.
	SystemControl_DFSR_HALTED = 0x1
	// Position of BKPT field.
	SystemControl_DFSR_BKPT_Pos = 0x1
	// Bit mask of BKPT field.
	SystemControl_DFSR_BKPT_Msk = 0x2
	// Bit BKPT.
	SystemControl_DFSR_BKPT = 0x2
	// Position of DWTTRAP field.
	SystemControl_DFSR_DWTTRAP_Pos = 0x2
	// Bit mask of DWTTRAP field.
	SystemControl_DFSR_DWTTRAP_Msk = 0x4
	// Bit DWTTRAP.
	SystemControl_DFSR_DWTTRAP = 0x4
	// Position of VCATCH field.
	SystemControl_DFSR_VCATCH_Pos = 0x3
	// Bit mask of VCATCH field.
	SystemControl_DFSR_VCATCH_Msk = 0x8
	// Bit VCATCH.
	SystemControl_DFSR_VCATCH = 0x8
	// Position of EXTERNAL field.
	SystemControl_DFSR_EXTERNAL_Pos = 0x4
	// Bit mask of EXTERNAL field.
	SystemControl_DFSR_EXTERNAL_Msk = 0x10
	// Bit EXTERNAL.
	SystemControl_DFSR_EXTERNAL = 0x10

	// MMFAR: MemManage Fault Address Register
	// Position of ADDRESS field.
	SystemControl_MMFAR_ADDRESS_Pos = 0x0
	// Bit mask of ADDRESS field.
	SystemControl_MMFAR_ADDRESS_Msk = 0xffffffff

	// BFAR: BusFault Address Register
	// Position of ADDRESS field.
	SystemControl_BFAR_ADDRESS_Pos = 0x0
	// Bit mask of ADDRESS field.
	SystemControl_BFAR_ADDRESS_Msk = 0xffffffff

	// AFSR: Auxiliary Fault Status Register
	// Position of IMPDEF field.
	SystemControl_AFSR_IMPDEF_Pos = 0x0
	// Bit mask of IMPDEF field.
	SystemControl_AFSR_IMPDEF_Msk = 0xffffffff

	// CPACR: Coprocessor Access Control Register
	// Position of CP10 field.
	SystemControl_CPACR_CP10_Pos = 0x14
	// Bit mask of CP10 field.
	SystemControl_CPACR_CP10_Msk = 0x300000
	// Access denied
	SystemControl_CPACR_CP10_DENIED = 0x0
	// Privileged access only
	SystemControl_CPACR_CP10_PRIV = 0x1
	// Full access
	SystemControl_CPACR_CP10_FULL = 0x3
	// Position of CP11 field.
	SystemControl_CPACR_CP11_Pos = 0x16
	// Bit mask of CP11 field.
	SystemControl_CPACR_CP11_Msk = 0xc00000
	// Access denied
	SystemControl_CPACR_CP11_DENIED = 0x0
	// Privileged access only
	SystemControl_CPACR_CP11_PRIV = 0x1
	// Full access
	SystemControl_CPACR_CP11_FULL = 0x3
)

// Bitfields for TPI: Trace Port Interface Register
const (
	// ACPR: Asynchronous Clock Prescaler Register
	// Position of PRESCALER field.
	TPI_ACPR_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	TPI_ACPR_PRESCALER_Msk = 0x1fff

	// SPPR: Selected Pin Protocol Register
	// Position of TXMODE field.
	TPI_SPPR_TXMODE_Pos = 0x0
	// Bit mask of TXMODE field.
	TPI_SPPR_TXMODE_Msk = 0x3

	// FFSR: Formatter and Flush Status Register
	// Position of FlInProg field.
	TPI_FFSR_FlInProg_Pos = 0x0
	// Bit mask of FlInProg field.
	TPI_FFSR_FlInProg_Msk = 0x1
	// Bit FlInProg.
	TPI_FFSR_FlInProg = 0x1
	// Position of FtStopped field.
	TPI_FFSR_FtStopped_Pos = 0x1
	// Bit mask of FtStopped field.
	TPI_FFSR_FtStopped_Msk = 0x2
	// Bit FtStopped.
	TPI_FFSR_FtStopped = 0x2
	// Position of TCPresent field.
	TPI_FFSR_TCPresent_Pos = 0x2
	// Bit mask of TCPresent field.
	TPI_FFSR_TCPresent_Msk = 0x4
	// Bit TCPresent.
	TPI_FFSR_TCPresent = 0x4
	// Position of FtNonStop field.
	TPI_FFSR_FtNonStop_Pos = 0x3
	// Bit mask of FtNonStop field.
	TPI_FFSR_FtNonStop_Msk = 0x8
	// Bit FtNonStop.
	TPI_FFSR_FtNonStop = 0x8

	// FFCR: Formatter and Flush Control Register
	// Position of EnFCont field.
	TPI_FFCR_EnFCont_Pos = 0x1
	// Bit mask of EnFCont field.
	TPI_FFCR_EnFCont_Msk = 0x2
	// Bit EnFCont.
	TPI_FFCR_EnFCont = 0x2
	// Position of TrigIn field.
	TPI_FFCR_TrigIn_Pos = 0x8
	// Bit mask of TrigIn field.
	TPI_FFCR_TrigIn_Msk = 0x100
	// Bit TrigIn.
	TPI_FFCR_TrigIn = 0x100

	// TRIGGER: TRIGGER
	// Position of TRIGGER field.
	TPI_TRIGGER_TRIGGER_Pos = 0x0
	// Bit mask of TRIGGER field.
	TPI_TRIGGER_TRIGGER_Msk = 0x1
	// Bit TRIGGER.
	TPI_TRIGGER_TRIGGER = 0x1

	// FIFO0: Integration ETM Data
	// Position of ETM0 field.
	TPI_FIFO0_ETM0_Pos = 0x0
	// Bit mask of ETM0 field.
	TPI_FIFO0_ETM0_Msk = 0xff
	// Position of ETM1 field.
	TPI_FIFO0_ETM1_Pos = 0x8
	// Bit mask of ETM1 field.
	TPI_FIFO0_ETM1_Msk = 0xff00
	// Position of ETM2 field.
	TPI_FIFO0_ETM2_Pos = 0x10
	// Bit mask of ETM2 field.
	TPI_FIFO0_ETM2_Msk = 0xff0000
	// Position of ETM_bytecount field.
	TPI_FIFO0_ETM_bytecount_Pos = 0x18
	// Bit mask of ETM_bytecount field.
	TPI_FIFO0_ETM_bytecount_Msk = 0x3000000
	// Position of ETM_ATVALID field.
	TPI_FIFO0_ETM_ATVALID_Pos = 0x1a
	// Bit mask of ETM_ATVALID field.
	TPI_FIFO0_ETM_ATVALID_Msk = 0x4000000
	// Bit ETM_ATVALID.
	TPI_FIFO0_ETM_ATVALID = 0x4000000
	// Position of ITM_bytecount field.
	TPI_FIFO0_ITM_bytecount_Pos = 0x1b
	// Bit mask of ITM_bytecount field.
	TPI_FIFO0_ITM_bytecount_Msk = 0x18000000
	// Position of ITM_ATVALID field.
	TPI_FIFO0_ITM_ATVALID_Pos = 0x1d
	// Bit mask of ITM_ATVALID field.
	TPI_FIFO0_ITM_ATVALID_Msk = 0x20000000
	// Bit ITM_ATVALID.
	TPI_FIFO0_ITM_ATVALID = 0x20000000

	// ITATBCTR2: ITATBCTR2
	// Position of ATREADY field.
	TPI_ITATBCTR2_ATREADY_Pos = 0x0
	// Bit mask of ATREADY field.
	TPI_ITATBCTR2_ATREADY_Msk = 0x1
	// Bit ATREADY.
	TPI_ITATBCTR2_ATREADY = 0x1

	// ITATBCTR0: ITATBCTR0
	// Position of ATREADY field.
	TPI_ITATBCTR0_ATREADY_Pos = 0x0
	// Bit mask of ATREADY field.
	TPI_ITATBCTR0_ATREADY_Msk = 0x1
	// Bit ATREADY.
	TPI_ITATBCTR0_ATREADY = 0x1

	// FIFO1: Integration ITM Data
	// Position of ITM0 field.
	TPI_FIFO1_ITM0_Pos = 0x0
	// Bit mask of ITM0 field.
	TPI_FIFO1_ITM0_Msk = 0xff
	// Position of ITM1 field.
	TPI_FIFO1_ITM1_Pos = 0x8
	// Bit mask of ITM1 field.
	TPI_FIFO1_ITM1_Msk = 0xff00
	// Position of ITM2 field.
	TPI_FIFO1_ITM2_Pos = 0x10
	// Bit mask of ITM2 field.
	TPI_FIFO1_ITM2_Msk = 0xff0000
	// Position of ETM_bytecount field.
	TPI_FIFO1_ETM_bytecount_Pos = 0x18
	// Bit mask of ETM_bytecount field.
	TPI_FIFO1_ETM_bytecount_Msk = 0x3000000
	// Position of ETM_ATVALID field.
	TPI_FIFO1_ETM_ATVALID_Pos = 0x1a
	// Bit mask of ETM_ATVALID field.
	TPI_FIFO1_ETM_ATVALID_Msk = 0x4000000
	// Bit ETM_ATVALID.
	TPI_FIFO1_ETM_ATVALID = 0x4000000
	// Position of ITM_bytecount field.
	TPI_FIFO1_ITM_bytecount_Pos = 0x1b
	// Bit mask of ITM_bytecount field.
	TPI_FIFO1_ITM_bytecount_Msk = 0x18000000
	// Position of ITM_ATVALID field.
	TPI_FIFO1_ITM_ATVALID_Pos = 0x1d
	// Bit mask of ITM_ATVALID field.
	TPI_FIFO1_ITM_ATVALID_Msk = 0x20000000
	// Bit ITM_ATVALID.
	TPI_FIFO1_ITM_ATVALID = 0x20000000

	// ITCTRL: Integration Mode Control
	// Position of Mode field.
	TPI_ITCTRL_Mode_Pos = 0x0
	// Bit mask of Mode field.
	TPI_ITCTRL_Mode_Msk = 0x1
	// Bit Mode.
	TPI_ITCTRL_Mode = 0x1

	// DEVID: TPIU_DEVID
	// Position of NrTraceInput field.
	TPI_DEVID_NrTraceInput_Pos = 0x0
	// Bit mask of NrTraceInput field.
	TPI_DEVID_NrTraceInput_Msk = 0x1
	// Bit NrTraceInput.
	TPI_DEVID_NrTraceInput = 0x1
	// Position of AsynClkIn field.
	TPI_DEVID_AsynClkIn_Pos = 0x5
	// Bit mask of AsynClkIn field.
	TPI_DEVID_AsynClkIn_Msk = 0x20
	// Bit AsynClkIn.
	TPI_DEVID_AsynClkIn = 0x20
	// Position of MinBufSz field.
	TPI_DEVID_MinBufSz_Pos = 0x6
	// Bit mask of MinBufSz field.
	TPI_DEVID_MinBufSz_Msk = 0x1c0
	// Position of PTINVALID field.
	TPI_DEVID_PTINVALID_Pos = 0x9
	// Bit mask of PTINVALID field.
	TPI_DEVID_PTINVALID_Msk = 0x200
	// Bit PTINVALID.
	TPI_DEVID_PTINVALID = 0x200
	// Position of MANCVALID field.
	TPI_DEVID_MANCVALID_Pos = 0xa
	// Bit mask of MANCVALID field.
	TPI_DEVID_MANCVALID_Msk = 0x400
	// Bit MANCVALID.
	TPI_DEVID_MANCVALID = 0x400
	// Position of NRZVALID field.
	TPI_DEVID_NRZVALID_Pos = 0xb
	// Bit mask of NRZVALID field.
	TPI_DEVID_NRZVALID_Msk = 0x800
	// Bit NRZVALID.
	TPI_DEVID_NRZVALID = 0x800

	// DEVTYPE: TPIU_DEVTYPE
	// Position of SubType field.
	TPI_DEVTYPE_SubType_Pos = 0x0
	// Bit mask of SubType field.
	TPI_DEVTYPE_SubType_Msk = 0xf
	// Position of MajorType field.
	TPI_DEVTYPE_MajorType_Pos = 0x4
	// Bit mask of MajorType field.
	TPI_DEVTYPE_MajorType_Msk = 0xf0
)
