// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from stm32h753v.svd, see https://github.com/tinygo-org/stm32-svd

// +build stm32,stm32h753x

// STM32H753x
//

package stm32

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "STM32H753x"
	CPU          = "CM7"
	FPUPresent   = true
	NVICPrioBits = 4
)

// Interrupt numbers.
const (
	// WWDG
	IRQ_WWDG1 = 0

	// External interrupt/event controller
	IRQ_PVD_PVM = 1

	// RTC
	IRQ_RTC_TAMP_STAMP_CSS_LSE = 2

	// RTC
	IRQ_RTC_WKUP = 3

	// Flash
	IRQ_FLASH = 4

	// Reset and clock control
	IRQ_RCC = 5

	// External interrupt/event controller
	IRQ_EXTI0 = 6

	// External interrupt/event controller
	IRQ_EXTI1 = 7

	// External interrupt/event controller
	IRQ_EXTI2 = 8

	// External interrupt/event controller
	IRQ_EXTI3 = 9

	// External interrupt/event controller
	IRQ_EXTI4 = 10

	// DMA controller
	IRQ_DMA_STR0 = 11

	// DMA controller
	IRQ_DMA1_STR0 = 11

	// DMA controller
	IRQ_DMA_STR1 = 12

	// DMA controller
	IRQ_DMA1_STR1 = 12

	// DMA controller
	IRQ_DMA1_STR2 = 13

	// DMA controller
	IRQ_DMA1_STR3 = 14

	// DMA controller
	IRQ_DMA1_STR4 = 15

	// DMA controller
	IRQ_DMA1_STR5 = 16

	// DMA controller
	IRQ_DMA1_STR6 = 17

	IRQ_ADC1_2 = 18

	// FDCAN1
	IRQ_FDCAN1_IT0 = 19

	IRQ_FDCAN2_IT0 = 20

	// FDCAN1
	IRQ_FDCAN1_IT1 = 21

	IRQ_FDCAN2_IT1 = 22

	// External interrupt/event controller
	IRQ_EXTI9_5 = 23

	// Advanced-timers
	IRQ_TIM1_BRK = 24

	// Advanced-timers
	IRQ_TIM1_UP = 25

	// Advanced-timers
	IRQ_TIM1_TRG_COM = 26

	// Advanced-timers
	IRQ_TIM_CC = 27

	// General purpose timers
	IRQ_TIM2 = 28

	// General purpose timers
	IRQ_TIM3 = 29

	IRQ_TIM4 = 30

	// I2C
	IRQ_I2C1_EV = 31

	// I2C
	IRQ_I2C1_ER = 32

	IRQ_I2C2_EV = 33

	IRQ_I2C2_ER = 34

	// Serial peripheral interface
	IRQ_SPI1 = 35

	IRQ_SPI2 = 36

	IRQ_USART1 = 37

	IRQ_USART2 = 38

	IRQ_USART3 = 39

	// External interrupt/event controller
	IRQ_EXTI15_10 = 40

	// External interrupt/event controller
	IRQ_RTC_ALARM = 41

	// General purpose timers
	IRQ_TIM8_BRK_TIM12 = 43

	// General purpose timers
	IRQ_TIM8_UP_TIM13 = 44

	// General purpose timers
	IRQ_TIM8_TRG_COM_TIM14 = 45

	IRQ_TIM8_CC = 46

	// DMA controller
	IRQ_DMA1_STR7 = 47

	// FMC
	IRQ_FMC = 48

	// SDMMC1
	IRQ_SDMMC1 = 49

	IRQ_TIM5 = 50

	IRQ_SPI3 = 51

	IRQ_UART4 = 52

	IRQ_UART5 = 53

	// Basic timers
	IRQ_TIM6_DAC = 54

	IRQ_TIM7 = 55

	IRQ_DMA2_STR0 = 56

	IRQ_DMA2_STR1 = 57

	IRQ_DMA2_STR2 = 58

	IRQ_DMA2_STR3 = 59

	IRQ_DMA2_STR4 = 60

	// Ethernet: media access control (MAC)
	IRQ_ETH = 61

	IRQ_ETH_WKUP = 62

	// FDCAN1
	IRQ_FDCAN_CAL = 63

	IRQ_DMA2_STR5 = 68

	IRQ_DMA2_STR6 = 69

	IRQ_DMA2_STR7 = 70

	IRQ_USART6 = 71

	IRQ_I2C3_EV = 72

	IRQ_I2C3_ER = 73

	IRQ_OTG_HS_EP1_OUT = 74

	IRQ_OTG_HS_EP1_IN = 75

	IRQ_OTG_HS_WKUP = 76

	IRQ_OTG_HS = 77

	// Digital camera interface
	IRQ_DCMI = 78

	// Cryptographic processor
	IRQ_CRYP = 79

	// Hash processor
	IRQ_HASH_RNG = 80

	// Floting point unit
	IRQ_FPU = 81

	IRQ_UART7 = 82

	IRQ_UART8 = 83

	IRQ_SPI4 = 84

	IRQ_SPI5 = 85

	IRQ_SPI6 = 86

	IRQ_SAI1 = 87

	// LCD-TFT Controller
	IRQ_LTDC = 88

	// LCD-TFT Controller
	IRQ_LTDC_ER = 89

	// DMA2D
	IRQ_DMA2D = 90

	IRQ_SAI2 = 91

	// QUADSPI
	IRQ_QUADSPI = 92

	// Low power timer
	IRQ_LPTIM1 = 93

	// CEC
	IRQ_CEC = 94

	IRQ_I2C4_EV = 95

	IRQ_I2C4_ER = 96

	// Receiver Interface
	IRQ_SPDIF = 97

	IRQ_OTG_FS_EP1_OUT = 98

	IRQ_OTG_FS_EP1_IN = 99

	IRQ_OTG_FS_WKUP = 100

	// USB 1 on the go high speed
	IRQ_OTG_FS = 101

	// DMAMUX
	IRQ_DMAMUX1_OV = 102

	// High Resolution Timer: TIMA
	IRQ_HRTIM1_MST = 103

	// High Resolution Timer: TIMB
	IRQ_HRTIM1_TIMA = 104

	// High Resolution Timer: TIMC
	IRQ_HRTIM_TIMB = 105

	// High Resolution Timer: TIMD
	IRQ_HRTIM1_TIMC = 106

	// High Resolution Timer: TIME
	IRQ_HRTIM1_TIMD = 107

	// High Resolution Timer: Common functions
	IRQ_HRTIM_TIME = 108

	// High Resolution Timer: TIMA
	IRQ_HRTIM1_FLT = 109

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT0 = 110

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT1 = 111

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT2 = 112

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT3 = 113

	IRQ_SAI3 = 114

	// General purpose timers
	IRQ_SWPMI1 = 115

	// General purpose timers
	IRQ_TIM15 = 116

	// General-purpose-timers
	IRQ_TIM16 = 117

	// General-purpose-timers
	IRQ_TIM17 = 118

	// Management data input/output slave
	IRQ_MDIOS_WKUP = 119

	// Management data input/output slave
	IRQ_MDIOS = 120

	// JPEG
	IRQ_JPEG = 121

	// MDMA
	IRQ_MDMA = 122

	// SDMMC1
	IRQ_SDMMC = 124

	// HSEM
	IRQ_HSEM0 = 125

	// Analog to Digital Converter
	IRQ_ADC3 = 127

	// DMAMUX
	IRQ_DMAMUX2_OVR = 128

	// BDMA
	IRQ_BDMA_CH1 = 129

	// BDMA
	IRQ_BDMA_CH2 = 130

	// BDMA
	IRQ_BDMA_CH3 = 131

	// BDMA
	IRQ_BDMA_CH4 = 132

	// BDMA
	IRQ_BDMA_CH5 = 133

	// BDMA
	IRQ_BDMA_CH6 = 134

	// BDMA
	IRQ_BDMA_CH7 = 135

	// BDMA
	IRQ_BDMA_CH8 = 136

	// COMP1
	IRQ_COMP = 137

	IRQ_LPTIM2 = 138

	// Low power timer
	IRQ_LPTIM3 = 139

	IRQ_LPTIM4 = 140

	IRQ_LPTIM5 = 141

	// LPUART1
	IRQ_LPUART = 142

	// WWDG
	IRQ_WWDG1_RST = 143

	// CRS
	IRQ_CRS = 144

	// RAM ECC monitoring
	IRQ_RAMECC = 145

	// SAI
	IRQ_SAI4 = 146

	// DELAY_Block_SDMMC1
	IRQ_WKUP = 149

	// Highest interrupt number on this device.
	IRQ_max = 149
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_WWDG1, "WWDG1_IRQHandler")
	_ = interrupt.Register(IRQ_PVD_PVM, "PVD_PVM_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_TAMP_STAMP_CSS_LSE, "RTC_TAMP_STAMP_CSS_LSE_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_WKUP, "RTC_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_FLASH, "FLASH_IRQHandler")
	_ = interrupt.Register(IRQ_RCC, "RCC_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI0, "EXTI0_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI1, "EXTI1_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI2, "EXTI2_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI3, "EXTI3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI4, "EXTI4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR0, "DMA_STR0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR0, "DMA1_STR0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR1, "DMA_STR1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR1, "DMA1_STR1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR2, "DMA1_STR2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR3, "DMA1_STR3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR4, "DMA1_STR4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR5, "DMA1_STR5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR6, "DMA1_STR6_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1_2, "ADC1_2_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN1_IT0, "FDCAN1_IT0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_IT0, "FDCAN2_IT0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN1_IT1, "FDCAN1_IT1_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_IT1, "FDCAN2_IT1_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI9_5, "EXTI9_5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_BRK, "TIM1_BRK_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_UP, "TIM1_UP_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_TRG_COM, "TIM1_TRG_COM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM_CC, "TIM_CC_IRQHandler")
	_ = interrupt.Register(IRQ_TIM2, "TIM2_IRQHandler")
	_ = interrupt.Register(IRQ_TIM3, "TIM3_IRQHandler")
	_ = interrupt.Register(IRQ_TIM4, "TIM4_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_EV, "I2C1_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_ER, "I2C1_ER_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_EV, "I2C2_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_ER, "I2C2_ER_IRQHandler")
	_ = interrupt.Register(IRQ_SPI1, "SPI1_IRQHandler")
	_ = interrupt.Register(IRQ_SPI2, "SPI2_IRQHandler")
	_ = interrupt.Register(IRQ_USART1, "USART1_IRQHandler")
	_ = interrupt.Register(IRQ_USART2, "USART2_IRQHandler")
	_ = interrupt.Register(IRQ_USART3, "USART3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI15_10, "EXTI15_10_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_ALARM, "RTC_ALARM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_BRK_TIM12, "TIM8_BRK_TIM12_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_UP_TIM13, "TIM8_UP_TIM13_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_TRG_COM_TIM14, "TIM8_TRG_COM_TIM14_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_CC, "TIM8_CC_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR7, "DMA1_STR7_IRQHandler")
	_ = interrupt.Register(IRQ_FMC, "FMC_IRQHandler")
	_ = interrupt.Register(IRQ_SDMMC1, "SDMMC1_IRQHandler")
	_ = interrupt.Register(IRQ_TIM5, "TIM5_IRQHandler")
	_ = interrupt.Register(IRQ_SPI3, "SPI3_IRQHandler")
	_ = interrupt.Register(IRQ_UART4, "UART4_IRQHandler")
	_ = interrupt.Register(IRQ_UART5, "UART5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM6_DAC, "TIM6_DAC_IRQHandler")
	_ = interrupt.Register(IRQ_TIM7, "TIM7_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR0, "DMA2_STR0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR1, "DMA2_STR1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR2, "DMA2_STR2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR3, "DMA2_STR3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR4, "DMA2_STR4_IRQHandler")
	_ = interrupt.Register(IRQ_ETH, "ETH_IRQHandler")
	_ = interrupt.Register(IRQ_ETH_WKUP, "ETH_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN_CAL, "FDCAN_CAL_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR5, "DMA2_STR5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR6, "DMA2_STR6_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR7, "DMA2_STR7_IRQHandler")
	_ = interrupt.Register(IRQ_USART6, "USART6_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_EV, "I2C3_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_ER, "I2C3_ER_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS_EP1_OUT, "OTG_HS_EP1_OUT_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS_EP1_IN, "OTG_HS_EP1_IN_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS_WKUP, "OTG_HS_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS, "OTG_HS_IRQHandler")
	_ = interrupt.Register(IRQ_DCMI, "DCMI_IRQHandler")
	_ = interrupt.Register(IRQ_CRYP, "CRYP_IRQHandler")
	_ = interrupt.Register(IRQ_HASH_RNG, "HASH_RNG_IRQHandler")
	_ = interrupt.Register(IRQ_FPU, "FPU_IRQHandler")
	_ = interrupt.Register(IRQ_UART7, "UART7_IRQHandler")
	_ = interrupt.Register(IRQ_UART8, "UART8_IRQHandler")
	_ = interrupt.Register(IRQ_SPI4, "SPI4_IRQHandler")
	_ = interrupt.Register(IRQ_SPI5, "SPI5_IRQHandler")
	_ = interrupt.Register(IRQ_SPI6, "SPI6_IRQHandler")
	_ = interrupt.Register(IRQ_SAI1, "SAI1_IRQHandler")
	_ = interrupt.Register(IRQ_LTDC, "LTDC_IRQHandler")
	_ = interrupt.Register(IRQ_LTDC_ER, "LTDC_ER_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2D, "DMA2D_IRQHandler")
	_ = interrupt.Register(IRQ_SAI2, "SAI2_IRQHandler")
	_ = interrupt.Register(IRQ_QUADSPI, "QUADSPI_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM1, "LPTIM1_IRQHandler")
	_ = interrupt.Register(IRQ_CEC, "CEC_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_EV, "I2C4_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_ER, "I2C4_ER_IRQHandler")
	_ = interrupt.Register(IRQ_SPDIF, "SPDIF_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS_EP1_OUT, "OTG_FS_EP1_OUT_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS_EP1_IN, "OTG_FS_EP1_IN_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS_WKUP, "OTG_FS_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS, "OTG_FS_IRQHandler")
	_ = interrupt.Register(IRQ_DMAMUX1_OV, "DMAMUX1_OV_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_MST, "HRTIM1_MST_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_TIMA, "HRTIM1_TIMA_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM_TIMB, "HRTIM_TIMB_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_TIMC, "HRTIM1_TIMC_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_TIMD, "HRTIM1_TIMD_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM_TIME, "HRTIM_TIME_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_FLT, "HRTIM1_FLT_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT0, "DFSDM1_FLT0_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT1, "DFSDM1_FLT1_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT2, "DFSDM1_FLT2_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT3, "DFSDM1_FLT3_IRQHandler")
	_ = interrupt.Register(IRQ_SAI3, "SAI3_IRQHandler")
	_ = interrupt.Register(IRQ_SWPMI1, "SWPMI1_IRQHandler")
	_ = interrupt.Register(IRQ_TIM15, "TIM15_IRQHandler")
	_ = interrupt.Register(IRQ_TIM16, "TIM16_IRQHandler")
	_ = interrupt.Register(IRQ_TIM17, "TIM17_IRQHandler")
	_ = interrupt.Register(IRQ_MDIOS_WKUP, "MDIOS_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_MDIOS, "MDIOS_IRQHandler")
	_ = interrupt.Register(IRQ_JPEG, "JPEG_IRQHandler")
	_ = interrupt.Register(IRQ_MDMA, "MDMA_IRQHandler")
	_ = interrupt.Register(IRQ_SDMMC, "SDMMC_IRQHandler")
	_ = interrupt.Register(IRQ_HSEM0, "HSEM0_IRQHandler")
	_ = interrupt.Register(IRQ_ADC3, "ADC3_IRQHandler")
	_ = interrupt.Register(IRQ_DMAMUX2_OVR, "DMAMUX2_OVR_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH1, "BDMA_CH1_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH2, "BDMA_CH2_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH3, "BDMA_CH3_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH4, "BDMA_CH4_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH5, "BDMA_CH5_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH6, "BDMA_CH6_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH7, "BDMA_CH7_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH8, "BDMA_CH8_IRQHandler")
	_ = interrupt.Register(IRQ_COMP, "COMP_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM2, "LPTIM2_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM3, "LPTIM3_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM4, "LPTIM4_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM5, "LPTIM5_IRQHandler")
	_ = interrupt.Register(IRQ_LPUART, "LPUART_IRQHandler")
	_ = interrupt.Register(IRQ_WWDG1_RST, "WWDG1_RST_IRQHandler")
	_ = interrupt.Register(IRQ_CRS, "CRS_IRQHandler")
	_ = interrupt.Register(IRQ_RAMECC, "RAMECC_IRQHandler")
	_ = interrupt.Register(IRQ_SAI4, "SAI4_IRQHandler")
	_ = interrupt.Register(IRQ_WKUP, "WKUP_IRQHandler")
)

// Peripherals.
var (
	// COMP1
	COMP1 = (*COMP1_Type)(unsafe.Pointer(uintptr(0x58003800)))

	// CRS
	CRS = (*CRS_Type)(unsafe.Pointer(uintptr(0x40008400)))

	// DAC
	DAC = (*DAC_Type)(unsafe.Pointer(uintptr(0x40007400)))

	// BDMA
	BDMA = (*BDMA_Type)(unsafe.Pointer(uintptr(0x58025400)))

	// DMA2D
	DMA2D = (*DMA2D_Type)(unsafe.Pointer(uintptr(0x52001000)))

	// DMAMUX
	DMAMUX2 = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x58025800)))

	// FMC
	FMC = (*FMC_Type)(unsafe.Pointer(uintptr(0x52004000)))

	// CEC
	CEC = (*CEC_Type)(unsafe.Pointer(uintptr(0x40006c00)))

	// HSEM
	HSEM = (*HSEM_Type)(unsafe.Pointer(uintptr(0x58026400)))

	// I2C
	I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005400)))

	// GPIO
	GPIOA = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020000)))

	// JPEG
	JPEG = (*JPEG_Type)(unsafe.Pointer(uintptr(0x52003000)))

	// MDMA
	MDMA = (*MDMA_Type)(unsafe.Pointer(uintptr(0x52000000)))

	// QUADSPI
	QUADSPI = (*QUADSPI_Type)(unsafe.Pointer(uintptr(0x52005000)))

	// RNG
	RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x48021800)))

	// RTC
	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x58004000)))

	// SAI
	SAI4 = (*SAI_Type)(unsafe.Pointer(uintptr(0x58005400)))

	// SDMMC1
	SDMMC1 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x52007000)))

	// VREFBUF
	VREFBUF = (*VREFBUF_Type)(unsafe.Pointer(uintptr(0x58003c00)))

	// IWDG
	IWDG = (*IWDG_Type)(unsafe.Pointer(uintptr(0x58004800)))

	// WWDG
	WWDG = (*WWDG_Type)(unsafe.Pointer(uintptr(0x50003000)))

	// PWR
	PWR = (*PWR_Type)(unsafe.Pointer(uintptr(0x58024800)))

	// Serial peripheral interface
	SPI1 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013000)))

	// LCD-TFT Controller
	LTDC = (*LTDC_Type)(unsafe.Pointer(uintptr(0x50001000)))

	// Receiver Interface
	SPDIFRX = (*SPDIFRX_Type)(unsafe.Pointer(uintptr(0x40004000)))

	// Analog to Digital Converter
	ADC3 = (*ADC_Type)(unsafe.Pointer(uintptr(0x58026000)))

	// Analog-to-Digital Converter
	ADC3_Common = (*ADC_Type)(unsafe.Pointer(uintptr(0x58026300)))

	// DMAMUX
	DMAMUX1 = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x40020800)))

	// Cryptographic processor
	CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x58024c00)))

	// Reset and clock control
	RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x58024400)))

	// Low power timer
	LPTIM1 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x40002400)))

	// Low power timer
	LPTIM3 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58002800)))

	// LPUART1
	LPUART1 = (*LPUART_Type)(unsafe.Pointer(uintptr(0x58000c00)))

	// System configuration controller
	SYSCFG = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x58000400)))

	// External interrupt/event controller
	EXTI = (*EXTI_Type)(unsafe.Pointer(uintptr(0x58000000)))

	// DELAY_Block_SDMMC1
	DELAY_Block_SDMMC1 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x52008000)))

	// Flash
	FLASH = (*Flash_Type)(unsafe.Pointer(uintptr(0x52002000)))

	// AXI interconnect registers
	AXI = (*AXI_Type)(unsafe.Pointer(uintptr(0x51000000)))

	// Hash processor
	HASH = (*HASH_Type)(unsafe.Pointer(uintptr(0x48021400)))

	// Cryptographic processor
	CRYP = (*CRYP_Type)(unsafe.Pointer(uintptr(0x48021000)))

	// Digital camera interface
	DCMI = (*DCMI_Type)(unsafe.Pointer(uintptr(0x48020000)))

	// USB 1 on the go high speed
	OTG1_HS_GLOBAL = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040000)))

	// USB 1 on the go high speed
	OTG1_HS_HOST = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040400)))

	// USB 1 on the go high speed
	OTG1_HS_DEVICE = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040800)))

	// USB 1 on the go high speed
	OTG1_HS_PWRCLK = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040e00)))

	// Ethernet: DMA mode register (DMA)
	Ethernet_DMA = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x40029000)))

	// Ethernet: MTL mode register (MTL)
	Ethernet_MTL = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x40028c00)))

	// Ethernet: media access control (MAC)
	Ethernet_MAC = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x40028000)))

	// DMA controller
	DMA1 = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020000)))

	// High Resolution Timer: Master Timers
	HRTIM_Master = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017400)))

	// High Resolution Timer: TIMA
	HRTIM_TIMA = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017480)))

	// High Resolution Timer: TIMB
	HRTIM_TIMB = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017500)))

	// High Resolution Timer: TIMC
	HRTIM_TIMC = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017580)))

	// High Resolution Timer: TIMD
	HRTIM_TIMD = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017600)))

	// High Resolution Timer: TIME
	HRTIM_TIME = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017680)))

	// High Resolution Timer: Common functions
	HRTIM_Common = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017780)))

	// Digital filter for sigma delta modulators
	DFSDM = (*DFSDM_Type)(unsafe.Pointer(uintptr(0x40017000)))

	// General-purpose-timers
	TIM16 = (*TIMs_Type)(unsafe.Pointer(uintptr(0x40014400)))

	// General-purpose-timers
	TIM17 = (*TIMs_Type)(unsafe.Pointer(uintptr(0x40014800)))

	// General purpose timers
	TIM15 = (*TIMs_Type)(unsafe.Pointer(uintptr(0x40014000)))

	// Universal synchronous asynchronous receiver transmitter
	USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x40011000)))

	// Advanced-timers
	TIM1 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40010000)))

	// FDCAN1
	FDCAN1 = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a000)))

	// CCU registers
	CAN_CCU = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a800)))

	// Management data input/output slave
	MDIOS = (*MDIOS_Type)(unsafe.Pointer(uintptr(0x40009400)))

	// Operational amplifiers
	OPAMP = (*OPAMP_Type)(unsafe.Pointer(uintptr(0x40009000)))

	// Single Wire Protocol Master Interface
	SWPMI = (*SWPMI_Type)(unsafe.Pointer(uintptr(0x40008800)))

	// General purpose timers
	TIM2 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// Basic timers
	TIM6 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001000)))

	// Nested Vectored Interrupt Controller
	NVIC = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000e100)))

	// Memory protection unit
	MPU = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90)))

	// SysTick timer
	STK = (*STK_Type)(unsafe.Pointer(uintptr(0xe000e010)))

	// Nested vectored interrupt controller
	NVIC_STIR = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000ef00)))

	// Floating point unit CPACR
	FPU_CPACR = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ed88)))

	// System control block ACTLR
	SCB_ACTRL = (*SCB_Type)(unsafe.Pointer(uintptr(0xe000e008)))

	// Floting point unit
	FPU = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ef34)))

	// System control block
	SCB = (*SCB_Type)(unsafe.Pointer(uintptr(0xe000ed00)))

	// Processor features
	PF = (*PF_Type)(unsafe.Pointer(uintptr(0xe000ed78)))

	// Access control
	AC = (*AC_Type)(unsafe.Pointer(uintptr(0xe000ef90)))

	// General purpose timers
	TIM3 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000400)))

	// General purpose timers
	TIM4 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000800)))

	// General purpose timers
	TIM12 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001800)))

	// General purpose timers
	TIM13 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001c00)))

	// General purpose timers
	TIM14 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40002000)))

	// Debug support
	DBGMCU = (*DBG_Type)(unsafe.Pointer(uintptr(0x5c001000)))

	// RAM ECC monitoring
	RAMECC1 = (*RAMECC_Type)(unsafe.Pointer(uintptr(0x52009000)))

	// RAM ECC monitoring
	RAMECC3 = (*RAMECC_Type)(unsafe.Pointer(uintptr(0x58027000)))

	// I2C
	I2C2 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005800)))

	// I2C
	I2C3 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005c00)))

	// I2C
	I2C4 = (*I2C_Type)(unsafe.Pointer(uintptr(0x58001c00)))

	// GPIO
	GPIOB = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020400)))

	// GPIO
	GPIOC = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020800)))

	// GPIO
	GPIOD = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020c00)))

	// GPIO
	GPIOE = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021000)))

	// GPIO
	GPIOF = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021400)))

	// GPIO
	GPIOG = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021800)))

	// GPIO
	GPIOH = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021c00)))

	// GPIO
	GPIOI = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58022000)))

	// GPIO
	GPIOJ = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58022400)))

	// GPIO
	GPIOK = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58022800)))

	// SAI
	SAI1 = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015800)))

	// SAI
	SAI2 = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015c00)))

	// SAI
	SAI3 = (*SAI_Type)(unsafe.Pointer(uintptr(0x40016000)))

	// SDMMC1
	SDMMC2 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x48022400)))

	// Serial peripheral interface
	SPI2 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// Serial peripheral interface
	SPI3 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003c00)))

	// Serial peripheral interface
	SPI4 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013400)))

	// Serial peripheral interface
	SPI5 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40015000)))

	// Serial peripheral interface
	SPI6 = (*SPI_Type)(unsafe.Pointer(uintptr(0x58001400)))

	// Analog to Digital Converter
	ADC1 = (*ADC_Type)(unsafe.Pointer(uintptr(0x40022000)))

	// Analog to Digital Converter
	ADC2 = (*ADC_Type)(unsafe.Pointer(uintptr(0x40022100)))

	// Analog-to-Digital Converter
	ADC12_Common = (*ADC_Type)(unsafe.Pointer(uintptr(0x40022300)))

	// Low power timer
	LPTIM2 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58002400)))

	// Low power timer
	LPTIM4 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58002c00)))

	// Low power timer
	LPTIM5 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58003000)))

	// DELAY_Block_SDMMC1
	DELAY_Block_QUADSPI = (*DLYB_Type)(unsafe.Pointer(uintptr(0x52006000)))

	// DELAY_Block_SDMMC1
	DELAY_Block_SDMMC2 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x48022800)))

	// USB 1 on the go high speed
	OTG2_HS_GLOBAL = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080000)))

	// USB 1 on the go high speed
	OTG2_HS_HOST = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080400)))

	// USB 1 on the go high speed
	OTG2_HS_DEVICE = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080800)))

	// USB 1 on the go high speed
	OTG2_HS_PWRCLK = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080e00)))

	// Universal synchronous asynchronous receiver transmitter
	USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004400)))

	// Universal synchronous asynchronous receiver transmitter
	USART3 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004800)))

	// Universal synchronous asynchronous receiver transmitter
	UART4 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004c00)))

	// Universal synchronous asynchronous receiver transmitter
	UART5 = (*USART_Type)(unsafe.Pointer(uintptr(0x40005000)))

	// Universal synchronous asynchronous receiver transmitter
	USART6 = (*USART_Type)(unsafe.Pointer(uintptr(0x40011400)))

	// Universal synchronous asynchronous receiver transmitter
	UART7 = (*USART_Type)(unsafe.Pointer(uintptr(0x40007800)))

	// Universal synchronous asynchronous receiver transmitter
	UART8 = (*USART_Type)(unsafe.Pointer(uintptr(0x40007c00)))

	// Advanced-timers
	TIM8 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40010400)))

	// FDCAN1
	FDCAN2 = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a400)))

	// General purpose timers
	TIM5 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000c00)))

	// Basic timers
	TIM7 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001400)))

	// DMA controller
	DMA2 = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020400)))

	// RAM ECC monitoring
	RAMECC2 = (*RAMECC_Type)(unsafe.Pointer(uintptr(0x48023000)))
)

// COMP1
type COMP1_Type struct {
	SR    volatile.Register32 // 0x0
	ICFR  volatile.Register32 // 0x4
	OR    volatile.Register32 // 0x8
	CFGR1 volatile.Register32 // 0xC
	CFGR2 volatile.Register32 // 0x10
}

// CRS
type CRS_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
	ISR  volatile.Register32 // 0x8
	ICR  volatile.Register32 // 0xC
}

// DAC
type DAC_Type struct {
	CR      volatile.Register32 // 0x0
	SWTRGR  volatile.Register32 // 0x4
	DHR12R1 volatile.Register32 // 0x8
	DHR12L1 volatile.Register32 // 0xC
	DHR8R1  volatile.Register32 // 0x10
	DHR12R2 volatile.Register32 // 0x14
	DHR12L2 volatile.Register32 // 0x18
	DHR8R2  volatile.Register32 // 0x1C
	DHR12RD volatile.Register32 // 0x20
	DHR12LD volatile.Register32 // 0x24
	DHR8RD  volatile.Register32 // 0x28
	DOR1    volatile.Register32 // 0x2C
	DOR2    volatile.Register32 // 0x30
	SR      volatile.Register32 // 0x34
	CCR     volatile.Register32 // 0x38
	MCR     volatile.Register32 // 0x3C
	SHSR1   volatile.Register32 // 0x40
	SHSR2   volatile.Register32 // 0x44
	SHHR    volatile.Register32 // 0x48
	SHRR    volatile.Register32 // 0x4C
}

// BDMA
type BDMA_Type struct {
	ISR  volatile.Register32 // 0x0
	IFCR volatile.Register32 // 0x4
	CH   [8]struct {
		CR   volatile.Register32
		NDTR volatile.Register32
		PAR  volatile.Register32
		M0AR volatile.Register32
		M1AR volatile.Register32
	} // 0x8
}

// DMA2D
type DMA2D_Type struct {
	CR      volatile.Register32 // 0x0
	ISR     volatile.Register32 // 0x4
	IFCR    volatile.Register32 // 0x8
	FGMAR   volatile.Register32 // 0xC
	FGOR    volatile.Register32 // 0x10
	BGMAR   volatile.Register32 // 0x14
	BGOR    volatile.Register32 // 0x18
	FGPFCCR volatile.Register32 // 0x1C
	FGCOLR  volatile.Register32 // 0x20
	BGPFCCR volatile.Register32 // 0x24
	BGCOLR  volatile.Register32 // 0x28
	FGCMAR  volatile.Register32 // 0x2C
	BGCMAR  volatile.Register32 // 0x30
	OPFCCR  volatile.Register32 // 0x34
	OCOLR   volatile.Register32 // 0x38
	OMAR    volatile.Register32 // 0x3C
	OOR     volatile.Register32 // 0x40
	NLR     volatile.Register32 // 0x44
	LWR     volatile.Register32 // 0x48
	AMTCR   volatile.Register32 // 0x4C
}

// DMAMUX
type DMAMUX_Type struct {
	CCR0  volatile.Register32 // 0x0
	CCR1  volatile.Register32 // 0x4
	CCR2  volatile.Register32 // 0x8
	CCR3  volatile.Register32 // 0xC
	CCR4  volatile.Register32 // 0x10
	CCR5  volatile.Register32 // 0x14
	CCR6  volatile.Register32 // 0x18
	CCR7  volatile.Register32 // 0x1C
	_     [96]byte
	CSR   volatile.Register32 // 0x80
	CFR   volatile.Register32 // 0x84
	_     [120]byte
	RGCR0 volatile.Register32 // 0x100
	RGCR1 volatile.Register32 // 0x104
	RGCR2 volatile.Register32 // 0x108
	RGCR3 volatile.Register32 // 0x10C
	RGCR4 volatile.Register32 // 0x110
	RGCR5 volatile.Register32 // 0x114
	RGCR6 volatile.Register32 // 0x118
	RGCR7 volatile.Register32 // 0x11C
	_     [32]byte
	RGSR  volatile.Register32 // 0x140
	RGCFR volatile.Register32 // 0x144
}

// FMC
type FMC_Type struct {
	BCR1   volatile.Register32 // 0x0
	BTR1   volatile.Register32 // 0x4
	BCR2   volatile.Register32 // 0x8
	BTR2   volatile.Register32 // 0xC
	BCR3   volatile.Register32 // 0x10
	BTR3   volatile.Register32 // 0x14
	BCR4   volatile.Register32 // 0x18
	BTR4   volatile.Register32 // 0x1C
	_      [96]byte
	PCR    volatile.Register32 // 0x80
	SR     volatile.Register32 // 0x84
	PMEM   volatile.Register32 // 0x88
	PATT   volatile.Register32 // 0x8C
	_      [4]byte
	ECCR   volatile.Register32 // 0x94
	_      [108]byte
	BWTR1  volatile.Register32 // 0x104
	_      [4]byte
	BWTR2  volatile.Register32 // 0x10C
	_      [4]byte
	BWTR3  volatile.Register32 // 0x114
	_      [4]byte
	BWTR4  volatile.Register32 // 0x11C
	_      [32]byte
	SDBANK [2]struct {
		SDCR volatile.Register32
		_    [4]byte
		SDTR volatile.Register32
		_    [18446744073709551608]byte
	} // 0x140
	_     [8]byte
	SDCMR volatile.Register32 // 0x150
	SDRTR volatile.Register32 // 0x154
	SDSR  volatile.Register32 // 0x158
}

// CEC
type CEC_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
	TXDR volatile.Register32 // 0x8
	RXDR volatile.Register32 // 0xC
	ISR  volatile.Register32 // 0x10
	IER  volatile.Register32 // 0x14
}

// HSEM
type HSEM_Type struct {
	R0    volatile.Register32 // 0x0
	R1    volatile.Register32 // 0x4
	R2    volatile.Register32 // 0x8
	R3    volatile.Register32 // 0xC
	R4    volatile.Register32 // 0x10
	R5    volatile.Register32 // 0x14
	R6    volatile.Register32 // 0x18
	R7    volatile.Register32 // 0x1C
	R8    volatile.Register32 // 0x20
	R9    volatile.Register32 // 0x24
	R10   volatile.Register32 // 0x28
	R11   volatile.Register32 // 0x2C
	R12   volatile.Register32 // 0x30
	R13   volatile.Register32 // 0x34
	R14   volatile.Register32 // 0x38
	R15   volatile.Register32 // 0x3C
	R16   volatile.Register32 // 0x40
	R17   volatile.Register32 // 0x44
	R18   volatile.Register32 // 0x48
	R19   volatile.Register32 // 0x4C
	R20   volatile.Register32 // 0x50
	R21   volatile.Register32 // 0x54
	R22   volatile.Register32 // 0x58
	R23   volatile.Register32 // 0x5C
	R24   volatile.Register32 // 0x60
	R25   volatile.Register32 // 0x64
	R26   volatile.Register32 // 0x68
	R27   volatile.Register32 // 0x6C
	R28   volatile.Register32 // 0x70
	R29   volatile.Register32 // 0x74
	R30   volatile.Register32 // 0x78
	R31   volatile.Register32 // 0x7C
	RLR0  volatile.Register32 // 0x80
	RLR1  volatile.Register32 // 0x84
	RLR2  volatile.Register32 // 0x88
	RLR3  volatile.Register32 // 0x8C
	RLR4  volatile.Register32 // 0x90
	RLR5  volatile.Register32 // 0x94
	RLR6  volatile.Register32 // 0x98
	RLR7  volatile.Register32 // 0x9C
	RLR8  volatile.Register32 // 0xA0
	RLR9  volatile.Register32 // 0xA4
	RLR10 volatile.Register32 // 0xA8
	RLR11 volatile.Register32 // 0xAC
	RLR12 volatile.Register32 // 0xB0
	RLR13 volatile.Register32 // 0xB4
	RLR14 volatile.Register32 // 0xB8
	RLR15 volatile.Register32 // 0xBC
	RLR16 volatile.Register32 // 0xC0
	RLR17 volatile.Register32 // 0xC4
	RLR18 volatile.Register32 // 0xC8
	RLR19 volatile.Register32 // 0xCC
	RLR20 volatile.Register32 // 0xD0
	RLR21 volatile.Register32 // 0xD4
	RLR22 volatile.Register32 // 0xD8
	RLR23 volatile.Register32 // 0xDC
	RLR24 volatile.Register32 // 0xE0
	RLR25 volatile.Register32 // 0xE4
	RLR26 volatile.Register32 // 0xE8
	RLR27 volatile.Register32 // 0xEC
	RLR28 volatile.Register32 // 0xF0
	RLR29 volatile.Register32 // 0xF4
	RLR30 volatile.Register32 // 0xF8
	RLR31 volatile.Register32 // 0xFC
	IER   volatile.Register32 // 0x100
	ICR   volatile.Register32 // 0x104
	ISR   volatile.Register32 // 0x108
	MISR  volatile.Register32 // 0x10C
	_     [48]byte
	CR    volatile.Register32 // 0x140
	KEYR  volatile.Register32 // 0x144
}

// I2C
type I2C_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	OAR1     volatile.Register32 // 0x8
	OAR2     volatile.Register32 // 0xC
	TIMINGR  volatile.Register32 // 0x10
	TIMEOUTR volatile.Register32 // 0x14
	ISR      volatile.Register32 // 0x18
	ICR      volatile.Register32 // 0x1C
	PECR     volatile.Register32 // 0x20
	RXDR     volatile.Register32 // 0x24
	TXDR     volatile.Register32 // 0x28
}

// GPIO
type GPIO_Type struct {
	MODER   volatile.Register32 // 0x0
	OTYPER  volatile.Register32 // 0x4
	OSPEEDR volatile.Register32 // 0x8
	PUPDR   volatile.Register32 // 0xC
	IDR     volatile.Register32 // 0x10
	ODR     volatile.Register32 // 0x14
	BSRR    volatile.Register32 // 0x18
	LCKR    volatile.Register32 // 0x1C
	AFRL    volatile.Register32 // 0x20
	AFRH    volatile.Register32 // 0x24
}

// JPEG
type JPEG_Type struct {
	CONFR0  volatile.Register32 // 0x0
	CONFR1  volatile.Register32 // 0x4
	CONFR2  volatile.Register32 // 0x8
	CONFR3  volatile.Register32 // 0xC
	CONFRN1 volatile.Register32 // 0x10
	CONFRN2 volatile.Register32 // 0x14
	CONFRN3 volatile.Register32 // 0x18
	CONFRN4 volatile.Register32 // 0x1C
	_       [16]byte
	CR      volatile.Register32 // 0x30
	SR      volatile.Register32 // 0x34
	CFR     volatile.Register32 // 0x38
	_       [4]byte
	DIR     volatile.Register32 // 0x40
	DOR     volatile.Register32 // 0x44
}

// MDMA
type MDMA_Type struct {
	GISR0 volatile.Register32 // 0x0
	_     [60]byte
	CH    [16]struct {
		ISR   volatile.Register32
		IFCR  volatile.Register32
		ESR   volatile.Register32
		CR    volatile.Register32
		TCR   volatile.Register32
		BNDTR volatile.Register32
		SAR   volatile.Register32
		DAR   volatile.Register32
		BRUR  volatile.Register32
		LAR   volatile.Register32
		TBR   volatile.Register32
		_     [4]byte
		MAR   volatile.Register32
		MDR   volatile.Register32
		_     [8]byte
	} // 0x40
}

// QUADSPI
type QUADSPI_Type struct {
	CR    volatile.Register32 // 0x0
	DCR   volatile.Register32 // 0x4
	SR    volatile.Register32 // 0x8
	FCR   volatile.Register32 // 0xC
	DLR   volatile.Register32 // 0x10
	CCR   volatile.Register32 // 0x14
	AR    volatile.Register32 // 0x18
	ABR   volatile.Register32 // 0x1C
	DR    volatile.Register32 // 0x20
	PSMKR volatile.Register32 // 0x24
	PSMAR volatile.Register32 // 0x28
	PIR   volatile.Register32 // 0x2C
	LPTR  volatile.Register32 // 0x30
}

// RNG
type RNG_Type struct {
	CR volatile.Register32 // 0x0
	SR volatile.Register32 // 0x4
	DR volatile.Register32 // 0x8
}

// RTC
type RTC_Type struct {
	TR       volatile.Register32 // 0x0
	DR       volatile.Register32 // 0x4
	CR       volatile.Register32 // 0x8
	ISR      volatile.Register32 // 0xC
	PRER     volatile.Register32 // 0x10
	WUTR     volatile.Register32 // 0x14
	_        [4]byte
	ALRMAR   volatile.Register32 // 0x1C
	ALRMBR   volatile.Register32 // 0x20
	WPR      volatile.Register32 // 0x24
	SSR      volatile.Register32 // 0x28
	SHIFTR   volatile.Register32 // 0x2C
	TSTR     volatile.Register32 // 0x30
	TSDR     volatile.Register32 // 0x34
	TSSSR    volatile.Register32 // 0x38
	CALR     volatile.Register32 // 0x3C
	TAMPCR   volatile.Register32 // 0x40
	ALRMASSR volatile.Register32 // 0x44
	ALRMBSSR volatile.Register32 // 0x48
	OR       volatile.Register32 // 0x4C
	BKP0R    volatile.Register32 // 0x50
	BKP1R    volatile.Register32 // 0x54
	BKP2R    volatile.Register32 // 0x58
	BKP3R    volatile.Register32 // 0x5C
	BKP4R    volatile.Register32 // 0x60
	BKP5R    volatile.Register32 // 0x64
	BKP6R    volatile.Register32 // 0x68
	BKP7R    volatile.Register32 // 0x6C
	BKP8R    volatile.Register32 // 0x70
	BKP9R    volatile.Register32 // 0x74
	BKP10R   volatile.Register32 // 0x78
	BKP11R   volatile.Register32 // 0x7C
	BKP12R   volatile.Register32 // 0x80
	BKP13R   volatile.Register32 // 0x84
	BKP14R   volatile.Register32 // 0x88
	BKP15R   volatile.Register32 // 0x8C
	BKP16R   volatile.Register32 // 0x90
	BKP17R   volatile.Register32 // 0x94
	BKP18R   volatile.Register32 // 0x98
	BKP19R   volatile.Register32 // 0x9C
	BKP20R   volatile.Register32 // 0xA0
	BKP21R   volatile.Register32 // 0xA4
	BKP22R   volatile.Register32 // 0xA8
	BKP23R   volatile.Register32 // 0xAC
	BKP24R   volatile.Register32 // 0xB0
	BKP25R   volatile.Register32 // 0xB4
	BKP26R   volatile.Register32 // 0xB8
	BKP27R   volatile.Register32 // 0xBC
	BKP28R   volatile.Register32 // 0xC0
	BKP29R   volatile.Register32 // 0xC4
	BKP30R   volatile.Register32 // 0xC8
	BKP31R   volatile.Register32 // 0xCC
}

// SAI
type SAI_Type struct {
	GCR volatile.Register32 // 0x0
	CH  [2]struct {
		CR1   volatile.Register32
		CR2   volatile.Register32
		FRCR  volatile.Register32
		SLOTR volatile.Register32
		IM    volatile.Register32
		SR    volatile.Register32
		CLRFR volatile.Register32
		DR    volatile.Register32
	} // 0x4
	PDMCR  volatile.Register32 // 0x44
	PDMDLY volatile.Register32 // 0x48
}

// SDMMC1
type SDMMC_Type struct {
	POWER      volatile.Register32 // 0x0
	CLKCR      volatile.Register32 // 0x4
	ARGR       volatile.Register32 // 0x8
	CMDR       volatile.Register32 // 0xC
	RESPCMDR   volatile.Register32 // 0x10
	RESP1R     volatile.Register32 // 0x14
	RESP2R     volatile.Register32 // 0x18
	RESP3R     volatile.Register32 // 0x1C
	RESP4R     volatile.Register32 // 0x20
	DTIMER     volatile.Register32 // 0x24
	DLENR      volatile.Register32 // 0x28
	DCTRL      volatile.Register32 // 0x2C
	DCNTR      volatile.Register32 // 0x30
	STAR       volatile.Register32 // 0x34
	ICR        volatile.Register32 // 0x38
	MASKR      volatile.Register32 // 0x3C
	ACKTIMER   volatile.Register32 // 0x40
	_          [12]byte
	IDMACTRLR  volatile.Register32 // 0x50
	IDMABSIZER volatile.Register32 // 0x54
	IDMABASE0R volatile.Register32 // 0x58
	IDMABASE1R volatile.Register32 // 0x5C
	_          [32]byte
	FIFOR      volatile.Register32 // 0x80
	_          [880]byte
	VER        volatile.Register32 // 0x3F4
	ID         volatile.Register32 // 0x3F8
}

// VREFBUF
type VREFBUF_Type struct {
	CSR volatile.Register32 // 0x0
	CCR volatile.Register32 // 0x4
}

// IWDG
type IWDG_Type struct {
	KR   volatile.Register32 // 0x0
	PR   volatile.Register32 // 0x4
	RLR  volatile.Register32 // 0x8
	SR   volatile.Register32 // 0xC
	WINR volatile.Register32 // 0x10
}

// WWDG
type WWDG_Type struct {
	CR  volatile.Register32 // 0x0
	CFR volatile.Register32 // 0x4
	SR  volatile.Register32 // 0x8
}

// PWR
type PWR_Type struct {
	CR1     volatile.Register32 // 0x0
	CSR1    volatile.Register32 // 0x4
	CR2     volatile.Register32 // 0x8
	CR3     volatile.Register32 // 0xC
	CPUCR   volatile.Register32 // 0x10
	_       [4]byte
	D3CR    volatile.Register32 // 0x18
	_       [4]byte
	WKUPCR  volatile.Register32 // 0x20
	WKUPFR  volatile.Register32 // 0x24
	WKUPEPR volatile.Register32 // 0x28
}

// Serial peripheral interface
type SPI_Type struct {
	CR1     volatile.Register32 // 0x0
	CR2     volatile.Register32 // 0x4
	CFG1    volatile.Register32 // 0x8
	CFG2    volatile.Register32 // 0xC
	IER     volatile.Register32 // 0x10
	SR      volatile.Register32 // 0x14
	IFCR    volatile.Register32 // 0x18
	_       [4]byte
	TXDR    volatile.Register32 // 0x20
	_       [12]byte
	RXDR    volatile.Register32 // 0x30
	_       [12]byte
	CRCPOLY volatile.Register32 // 0x40
	TXCRC   volatile.Register32 // 0x44
	RXCRC   volatile.Register32 // 0x48
	UDRDR   volatile.Register32 // 0x4C
	I2SCFGR volatile.Register32 // 0x50
}

// LCD-TFT Controller
type LTDC_Type struct {
	_     [8]byte
	SSCR  volatile.Register32 // 0x8
	BPCR  volatile.Register32 // 0xC
	AWCR  volatile.Register32 // 0x10
	TWCR  volatile.Register32 // 0x14
	GCR   volatile.Register32 // 0x18
	_     [8]byte
	SRCR  volatile.Register32 // 0x24
	_     [4]byte
	BCCR  volatile.Register32 // 0x2C
	_     [4]byte
	IER   volatile.Register32 // 0x34
	ISR   volatile.Register32 // 0x38
	ICR   volatile.Register32 // 0x3C
	LIPCR volatile.Register32 // 0x40
	CPSR  volatile.Register32 // 0x44
	CDSR  volatile.Register32 // 0x48
	_     [56]byte
	LAYER [2]struct {
		CR     volatile.Register32
		WHPCR  volatile.Register32
		WVPCR  volatile.Register32
		CKCR   volatile.Register32
		PFCR   volatile.Register32
		CACR   volatile.Register32
		DCCR   volatile.Register32
		BFCR   volatile.Register32
		_      [8]byte
		CFBAR  volatile.Register32
		CFBLR  volatile.Register32
		CFBLNR volatile.Register32
		_      [12]byte
		CLUTWR volatile.Register32
		_      [60]byte
	} // 0x84
}

// Receiver Interface
type SPDIFRX_Type struct {
	CR    volatile.Register32 // 0x0
	IMR   volatile.Register32 // 0x4
	SR    volatile.Register32 // 0x8
	IFCR  volatile.Register32 // 0xC
	DR_00 volatile.Register32 // 0x10
	CSR   volatile.Register32 // 0x14
	DIR   volatile.Register32 // 0x18
	_     [984]byte
	VERR  volatile.Register32 // 0x3F4
	IDR   volatile.Register32 // 0x3F8
	SIDR  volatile.Register32 // 0x3FC
}

// Analog to Digital Converter
type ADC_Type struct {
	ISR      volatile.Register32 // 0x0
	IER      volatile.Register32 // 0x4
	CR       volatile.Register32 // 0x8
	CFGR     volatile.Register32 // 0xC
	CFGR2    volatile.Register32 // 0x10
	SMPR1    volatile.Register32 // 0x14
	SMPR2    volatile.Register32 // 0x18
	PCSEL    volatile.Register32 // 0x1C
	LTR1     volatile.Register32 // 0x20
	HTR1     volatile.Register32 // 0x24
	_        [8]byte
	SQR1     volatile.Register32 // 0x30
	SQR2     volatile.Register32 // 0x34
	SQR3     volatile.Register32 // 0x38
	SQR4     volatile.Register32 // 0x3C
	DR       volatile.Register32 // 0x40
	_        [8]byte
	JSQR     volatile.Register32 // 0x4C
	_        [16]byte
	OFR1     volatile.Register32 // 0x60
	OFR2     volatile.Register32 // 0x64
	OFR3     volatile.Register32 // 0x68
	OFR4     volatile.Register32 // 0x6C
	_        [16]byte
	JDR1     volatile.Register32 // 0x80
	JDR2     volatile.Register32 // 0x84
	JDR3     volatile.Register32 // 0x88
	JDR4     volatile.Register32 // 0x8C
	_        [16]byte
	AWD2CR   volatile.Register32 // 0xA0
	AWD3CR   volatile.Register32 // 0xA4
	_        [8]byte
	LTR2     volatile.Register32 // 0xB0
	HTR2     volatile.Register32 // 0xB4
	LTR3     volatile.Register32 // 0xB8
	HTR3     volatile.Register32 // 0xBC
	DIFSEL   volatile.Register32 // 0xC0
	CALFACT  volatile.Register32 // 0xC4
	CALFACT2 volatile.Register32 // 0xC8
}

// Cryptographic processor
type CRC_Type struct {
	DR   volatile.Register32 // 0x0
	IDR  volatile.Register32 // 0x4
	CR   volatile.Register32 // 0x8
	_    [4]byte
	INIT volatile.Register32 // 0x10
	POL  volatile.Register32 // 0x14
}

// Reset and clock control
type RCC_Type struct {
	CR            volatile.Register32 // 0x0
	ICSCR         volatile.Register32 // 0x4
	CRRCR         volatile.Register32 // 0x8
	CSICFGR       volatile.Register32 // 0xC
	CFGR          volatile.Register32 // 0x10
	_             [4]byte
	D1CFGR        volatile.Register32 // 0x18
	D2CFGR        volatile.Register32 // 0x1C
	D3CFGR        volatile.Register32 // 0x20
	_             [4]byte
	PLLCKSELR     volatile.Register32 // 0x28
	PLLCFGR       volatile.Register32 // 0x2C
	PLL1DIVR      volatile.Register32 // 0x30
	PLL1FRACR     volatile.Register32 // 0x34
	PLL2DIVR      volatile.Register32 // 0x38
	PLL2FRACR     volatile.Register32 // 0x3C
	PLL3DIVR      volatile.Register32 // 0x40
	PLL3FRACR     volatile.Register32 // 0x44
	_             [4]byte
	D1CCIPR       volatile.Register32 // 0x4C
	D2CCIP1R      volatile.Register32 // 0x50
	D2CCIP2R      volatile.Register32 // 0x54
	D3CCIPR       volatile.Register32 // 0x58
	_             [4]byte
	CIER          volatile.Register32 // 0x60
	CIFR          volatile.Register32 // 0x64
	CICR          volatile.Register32 // 0x68
	_             [4]byte
	BDCR          volatile.Register32 // 0x70
	CSR           volatile.Register32 // 0x74
	_             [4]byte
	AHB3RSTR      volatile.Register32 // 0x7C
	AHB1RSTR      volatile.Register32 // 0x80
	AHB2RSTR      volatile.Register32 // 0x84
	AHB4RSTR      volatile.Register32 // 0x88
	APB3RSTR      volatile.Register32 // 0x8C
	APB1LRSTR     volatile.Register32 // 0x90
	APB1HRSTR     volatile.Register32 // 0x94
	APB2RSTR      volatile.Register32 // 0x98
	APB4RSTR      volatile.Register32 // 0x9C
	GCR           volatile.Register32 // 0xA0
	_             [4]byte
	D3AMR         volatile.Register32 // 0xA8
	_             [36]byte
	RSR           volatile.Register32 // 0xD0
	AHB3ENR       volatile.Register32 // 0xD4
	AHB1ENR       volatile.Register32 // 0xD8
	AHB2ENR       volatile.Register32 // 0xDC
	AHB4ENR       volatile.Register32 // 0xE0
	APB3ENR       volatile.Register32 // 0xE4
	APB1LENR      volatile.Register32 // 0xE8
	APB1HENR      volatile.Register32 // 0xEC
	APB2ENR       volatile.Register32 // 0xF0
	APB4ENR       volatile.Register32 // 0xF4
	_             [4]byte
	AHB3LPENR     volatile.Register32 // 0xFC
	AHB1LPENR     volatile.Register32 // 0x100
	AHB2LPENR     volatile.Register32 // 0x104
	AHB4LPENR     volatile.Register32 // 0x108
	APB3LPENR     volatile.Register32 // 0x10C
	APB1LLPENR    volatile.Register32 // 0x110
	APB1HLPENR    volatile.Register32 // 0x114
	APB2LPENR     volatile.Register32 // 0x118
	APB4LPENR     volatile.Register32 // 0x11C
	_             [16]byte
	C1_RSR        volatile.Register32 // 0x130
	C1_AHB3ENR    volatile.Register32 // 0x134
	C1_AHB1ENR    volatile.Register32 // 0x138
	C1_AHB2ENR    volatile.Register32 // 0x13C
	C1_AHB4ENR    volatile.Register32 // 0x140
	C1_APB3ENR    volatile.Register32 // 0x144
	C1_APB1LENR   volatile.Register32 // 0x148
	C1_APB1HENR   volatile.Register32 // 0x14C
	C1_APB2ENR    volatile.Register32 // 0x150
	C1_APB4ENR    volatile.Register32 // 0x154
	_             [4]byte
	C1_AHB3LPENR  volatile.Register32 // 0x15C
	C1_AHB1LPENR  volatile.Register32 // 0x160
	C1_AHB2LPENR  volatile.Register32 // 0x164
	C1_AHB4LPENR  volatile.Register32 // 0x168
	C1_APB3LPENR  volatile.Register32 // 0x16C
	C1_APB1LLPENR volatile.Register32 // 0x170
	C1_APB1HLPENR volatile.Register32 // 0x174
	C1_APB2LPENR  volatile.Register32 // 0x178
	C1_APB4LPENR  volatile.Register32 // 0x17C
}

// Low power timer
type LPTIM_Type struct {
	ISR   volatile.Register32 // 0x0
	ICR   volatile.Register32 // 0x4
	IER   volatile.Register32 // 0x8
	CFGR  volatile.Register32 // 0xC
	CR    volatile.Register32 // 0x10
	CMP   volatile.Register32 // 0x14
	ARR   volatile.Register32 // 0x18
	CNT   volatile.Register32 // 0x1C
	_     [4]byte
	CFGR2 volatile.Register32 // 0x24
}

// LPUART1
type LPUART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// System configuration controller
type SYSCFG_Type struct {
	_       [4]byte
	PMCR    volatile.Register32 // 0x4
	EXTICR1 volatile.Register32 // 0x8
	EXTICR2 volatile.Register32 // 0xC
	EXTICR3 volatile.Register32 // 0x10
	EXTICR4 volatile.Register32 // 0x14
	_       [8]byte
	CCCSR   volatile.Register32 // 0x20
	CCVR    volatile.Register32 // 0x24
	CCCR    volatile.Register32 // 0x28
	PWRCR   volatile.Register32 // 0x2C
	_       [244]byte
	PKGR    volatile.Register32 // 0x124
	_       [472]byte
	UR0     volatile.Register32 // 0x300
	_       [4]byte
	UR2     volatile.Register32 // 0x308
	UR3     volatile.Register32 // 0x30C
	UR4     volatile.Register32 // 0x310
	UR5     volatile.Register32 // 0x314
	UR6     volatile.Register32 // 0x318
	UR7     volatile.Register32 // 0x31C
	UR8     volatile.Register32 // 0x320
	UR9     volatile.Register32 // 0x324
	UR10    volatile.Register32 // 0x328
	UR11    volatile.Register32 // 0x32C
	UR12    volatile.Register32 // 0x330
	UR13    volatile.Register32 // 0x334
	UR14    volatile.Register32 // 0x338
	UR15    volatile.Register32 // 0x33C
	UR16    volatile.Register32 // 0x340
	UR17    volatile.Register32 // 0x344
}

// External interrupt/event controller
type EXTI_Type struct {
	RTSR1   volatile.Register32 // 0x0
	FTSR1   volatile.Register32 // 0x4
	SWIER1  volatile.Register32 // 0x8
	D3PMR1  volatile.Register32 // 0xC
	D3PCR1L volatile.Register32 // 0x10
	D3PCR1H volatile.Register32 // 0x14
	_       [8]byte
	RTSR2   volatile.Register32 // 0x20
	FTSR2   volatile.Register32 // 0x24
	SWIER2  volatile.Register32 // 0x28
	D3PMR2  volatile.Register32 // 0x2C
	D3PCR2L volatile.Register32 // 0x30
	D3PCR2H volatile.Register32 // 0x34
	_       [8]byte
	RTSR3   volatile.Register32 // 0x40
	FTSR3   volatile.Register32 // 0x44
	SWIER3  volatile.Register32 // 0x48
	D3PMR3  volatile.Register32 // 0x4C
	_       [4]byte
	D3PCR3H volatile.Register32 // 0x54
	_       [40]byte
	CPUIMR1 volatile.Register32 // 0x80
	CPUEMR1 volatile.Register32 // 0x84
	CPUPR1  volatile.Register32 // 0x88
	_       [4]byte
	CPUIMR2 volatile.Register32 // 0x90
	CPUEMR2 volatile.Register32 // 0x94
	CPUPR2  volatile.Register32 // 0x98
	_       [4]byte
	CPUIMR3 volatile.Register32 // 0xA0
	CPUEMR3 volatile.Register32 // 0xA4
	CPUPR3  volatile.Register32 // 0xA8
}

// DELAY_Block_SDMMC1
type DLYB_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
}

// Flash
type Flash_Type struct {
	ACR  volatile.Register32 // 0x0
	BANK [2]struct {
		KEYR      volatile.Register32
		_         [4]byte
		CR        volatile.Register32
		SR        volatile.Register32
		CCR       volatile.Register32
		_         [16]byte
		PRAR_CUR  volatile.Register32
		PRAR_PRG  volatile.Register32
		SCAR_CUR  volatile.Register32
		SCAR_PRG  volatile.Register32
		WPSN_CURR volatile.Register32
		WPSN_PRGR volatile.Register32
		_         [16]byte
		CRCCR     volatile.Register32
		CRCSADDR  volatile.Register32
		CRCEADDR  volatile.Register32
		_         [4]byte
		FAR       volatile.Register32
		_         [160]byte
	} // 0x4
}

// AXI interconnect registers
type AXI_Type struct {
	_                   [8144]byte
	PERIPH_ID_4         volatile.Register32 // 0x1FD0
	_                   [12]byte
	PERIPH_ID_0         volatile.Register32 // 0x1FE0
	PERIPH_ID_1         volatile.Register32 // 0x1FE4
	PERIPH_ID_2         volatile.Register32 // 0x1FE8
	PERIPH_ID_3         volatile.Register32 // 0x1FEC
	COMP_ID_0           volatile.Register32 // 0x1FF0
	COMP_ID_1           volatile.Register32 // 0x1FF4
	COMP_ID_2           volatile.Register32 // 0x1FF8
	COMP_ID_3           volatile.Register32 // 0x1FFC
	_                   [8]byte
	TARG1_FN_MOD_ISS_BM volatile.Register32 // 0x2008
	_                   [24]byte
	TARG1_FN_MOD2       volatile.Register32 // 0x2024
	_                   [4]byte
	TARG1_FN_MOD_LB     volatile.Register32 // 0x202C
	_                   [216]byte
	TARG1_FN_MOD        volatile.Register32 // 0x2108
	_                   [3836]byte
	TARG2_FN_MOD_ISS_BM volatile.Register32 // 0x3008
	_                   [24]byte
	TARG2_FN_MOD2       volatile.Register32 // 0x3024
	_                   [4]byte
	TARG2_FN_MOD_LB     volatile.Register32 // 0x302C
	_                   [216]byte
	TARG2_FN_MOD        volatile.Register32 // 0x3108
	_                   [3836]byte
	TARG3_FN_MOD_ISS_BM volatile.Register32 // 0x4008
	_                   [4092]byte
	TARG4_FN_MOD_ISS_BM volatile.Register32 // 0x5008
	_                   [4092]byte
	TARG5_FN_MOD_ISS_BM volatile.Register32 // 0x6008
	_                   [4092]byte
	TARG6_FN_MOD_ISS_BM volatile.Register32 // 0x7008
	_                   [4096]byte
	TARG7_FN_MOD_ISS_BM volatile.Register32 // 0x800C
	_                   [20]byte
	TARG7_FN_MOD2       volatile.Register32 // 0x8024
	_                   [224]byte
	TARG7_FN_MOD        volatile.Register32 // 0x8108
	_                   [237336]byte
	INI1_FN_MOD2        volatile.Register32 // 0x42024
	INI1_FN_MOD_AHB     volatile.Register32 // 0x42028
	_                   [212]byte
	INI1_READ_QOS       volatile.Register32 // 0x42100
	INI1_WRITE_QOS      volatile.Register32 // 0x42104
	INI1_FN_MOD         volatile.Register32 // 0x42108
	_                   [4084]byte
	INI2_READ_QOS       volatile.Register32 // 0x43100
	INI2_WRITE_QOS      volatile.Register32 // 0x43104
	INI2_FN_MOD         volatile.Register32 // 0x43108
	_                   [3864]byte
	INI3_FN_MOD2        volatile.Register32 // 0x44024
	INI3_FN_MOD_AHB     volatile.Register32 // 0x44028
	_                   [212]byte
	INI3_READ_QOS       volatile.Register32 // 0x44100
	INI3_WRITE_QOS      volatile.Register32 // 0x44104
	INI3_FN_MOD         volatile.Register32 // 0x44108
	_                   [4084]byte
	INI4_READ_QOS       volatile.Register32 // 0x45100
	INI4_WRITE_QOS      volatile.Register32 // 0x45104
	INI4_FN_MOD         volatile.Register32 // 0x45108
	_                   [4084]byte
	INI5_READ_QOS       volatile.Register32 // 0x46100
	INI5_WRITE_QOS      volatile.Register32 // 0x46104
	INI5_FN_MOD         volatile.Register32 // 0x46108
	_                   [4084]byte
	INI6_READ_QOS       volatile.Register32 // 0x47100
	INI6_WRITE_QOS      volatile.Register32 // 0x47104
	INI6_FN_MOD         volatile.Register32 // 0x47108
}

// Hash processor
type HASH_Type struct {
	CR       volatile.Register32 // 0x0
	DIN      volatile.Register32 // 0x4
	STR      volatile.Register32 // 0x8
	HR0      volatile.Register32 // 0xC
	HR1      volatile.Register32 // 0x10
	HR2      volatile.Register32 // 0x14
	HR3      volatile.Register32 // 0x18
	HR4      volatile.Register32 // 0x1C
	IMR      volatile.Register32 // 0x20
	SR       volatile.Register32 // 0x24
	_        [208]byte
	CSR0     volatile.Register32 // 0xF8
	CSR1     volatile.Register32 // 0xFC
	CSR2     volatile.Register32 // 0x100
	CSR3     volatile.Register32 // 0x104
	CSR4     volatile.Register32 // 0x108
	CSR5     volatile.Register32 // 0x10C
	CSR6     volatile.Register32 // 0x110
	CSR7     volatile.Register32 // 0x114
	CSR8     volatile.Register32 // 0x118
	CSR9     volatile.Register32 // 0x11C
	CSR10    volatile.Register32 // 0x120
	CSR11    volatile.Register32 // 0x124
	CSR12    volatile.Register32 // 0x128
	CSR13    volatile.Register32 // 0x12C
	CSR14    volatile.Register32 // 0x130
	CSR15    volatile.Register32 // 0x134
	CSR16    volatile.Register32 // 0x138
	CSR17    volatile.Register32 // 0x13C
	CSR18    volatile.Register32 // 0x140
	CSR19    volatile.Register32 // 0x144
	CSR20    volatile.Register32 // 0x148
	CSR21    volatile.Register32 // 0x14C
	CSR22    volatile.Register32 // 0x150
	CSR23    volatile.Register32 // 0x154
	CSR24    volatile.Register32 // 0x158
	CSR25    volatile.Register32 // 0x15C
	CSR26    volatile.Register32 // 0x160
	CSR27    volatile.Register32 // 0x164
	CSR28    volatile.Register32 // 0x168
	CSR29    volatile.Register32 // 0x16C
	CSR30    volatile.Register32 // 0x170
	CSR31    volatile.Register32 // 0x174
	CSR32    volatile.Register32 // 0x178
	CSR33    volatile.Register32 // 0x17C
	CSR34    volatile.Register32 // 0x180
	CSR35    volatile.Register32 // 0x184
	CSR36    volatile.Register32 // 0x188
	CSR37    volatile.Register32 // 0x18C
	CSR38    volatile.Register32 // 0x190
	CSR39    volatile.Register32 // 0x194
	CSR40    volatile.Register32 // 0x198
	CSR41    volatile.Register32 // 0x19C
	CSR42    volatile.Register32 // 0x1A0
	CSR43    volatile.Register32 // 0x1A4
	CSR44    volatile.Register32 // 0x1A8
	CSR45    volatile.Register32 // 0x1AC
	CSR46    volatile.Register32 // 0x1B0
	CSR47    volatile.Register32 // 0x1B4
	CSR48    volatile.Register32 // 0x1B8
	CSR49    volatile.Register32 // 0x1BC
	CSR50    volatile.Register32 // 0x1C0
	CSR51    volatile.Register32 // 0x1C4
	CSR52    volatile.Register32 // 0x1C8
	CSR53    volatile.Register32 // 0x1CC
	_        [320]byte
	HASH_HR0 volatile.Register32 // 0x310
	HASH_HR1 volatile.Register32 // 0x314
	HASH_HR2 volatile.Register32 // 0x318
	HASH_HR3 volatile.Register32 // 0x31C
	HASH_HR4 volatile.Register32 // 0x320
	HASH_HR5 volatile.Register32 // 0x324
	HASH_HR6 volatile.Register32 // 0x328
	HASH_HR7 volatile.Register32 // 0x32C
}

// Cryptographic processor
type CRYP_Type struct {
	CR         volatile.Register32 // 0x0
	SR         volatile.Register32 // 0x4
	DIN        volatile.Register32 // 0x8
	DOUT       volatile.Register32 // 0xC
	DMACR      volatile.Register32 // 0x10
	IMSCR      volatile.Register32 // 0x14
	RISR       volatile.Register32 // 0x18
	MISR       volatile.Register32 // 0x1C
	K0LR       volatile.Register32 // 0x20
	K0RR       volatile.Register32 // 0x24
	K1LR       volatile.Register32 // 0x28
	K1RR       volatile.Register32 // 0x2C
	K2LR       volatile.Register32 // 0x30
	K2RR       volatile.Register32 // 0x34
	K3LR       volatile.Register32 // 0x38
	K3RR       volatile.Register32 // 0x3C
	IV0LR      volatile.Register32 // 0x40
	IV0RR      volatile.Register32 // 0x44
	IV1LR      volatile.Register32 // 0x48
	IV1RR      volatile.Register32 // 0x4C
	CSGCMCCM0R volatile.Register32 // 0x50
	CSGCMCCM1R volatile.Register32 // 0x54
	CSGCMCCM2R volatile.Register32 // 0x58
	CSGCMCCM3R volatile.Register32 // 0x5C
	CSGCMCCM4R volatile.Register32 // 0x60
	CSGCMCCM5R volatile.Register32 // 0x64
	CSGCMCCM6R volatile.Register32 // 0x68
	CSGCMCCM7R volatile.Register32 // 0x6C
	CSGCM0R    volatile.Register32 // 0x70
	CSGCM1R    volatile.Register32 // 0x74
	CSGCM2R    volatile.Register32 // 0x78
	CSGCM3R    volatile.Register32 // 0x7C
	CSGCM4R    volatile.Register32 // 0x80
	CSGCM5R    volatile.Register32 // 0x84
	CSGCM6R    volatile.Register32 // 0x88
	CSGCM7R    volatile.Register32 // 0x8C
}

// Digital camera interface
type DCMI_Type struct {
	CR     volatile.Register32 // 0x0
	SR     volatile.Register32 // 0x4
	RIS    volatile.Register32 // 0x8
	IER    volatile.Register32 // 0xC
	MIS    volatile.Register32 // 0x10
	ICR    volatile.Register32 // 0x14
	ESCR   volatile.Register32 // 0x18
	ESUR   volatile.Register32 // 0x1C
	CWSTRT volatile.Register32 // 0x20
	CWSIZE volatile.Register32 // 0x24
	DR     volatile.Register32 // 0x28
}

// USB 1 on the go high speed
type USB_OTG_HS_Type struct {
	GOTGCTL        volatile.Register32 // 0x0
	GOTGINT        volatile.Register32 // 0x4
	GAHBCFG        volatile.Register32 // 0x8
	GUSBCFG        volatile.Register32 // 0xC
	GRSTCTL        volatile.Register32 // 0x10
	GINTSTS        volatile.Register32 // 0x14
	GINTMSK        volatile.Register32 // 0x18
	GRXSTSR_Host   volatile.Register32 // 0x1C
	GRXSTSP_Host   volatile.Register32 // 0x20
	GRXFSIZ        volatile.Register32 // 0x24
	HNPTXFSIZ_Host volatile.Register32 // 0x28
	GNPTXSTS       volatile.Register32 // 0x2C
	_              [8]byte
	GCCFG          volatile.Register32 // 0x38
	CID            volatile.Register32 // 0x3C
	_              [20]byte
	GLPMCFG        volatile.Register32 // 0x54
	_              [168]byte
	HPTXFSIZ       volatile.Register32 // 0x100
	DIEPTXF1       volatile.Register32 // 0x104
	DIEPTXF2       volatile.Register32 // 0x108
	_              [16]byte
	DIEPTXF3       volatile.Register32 // 0x11C
	DIEPTXF4       volatile.Register32 // 0x120
	DIEPTXF5       volatile.Register32 // 0x124
	DIEPTXF6       volatile.Register32 // 0x128
	DIEPTXF7       volatile.Register32 // 0x12C
}

// Ethernet: DMA mode register (DMA)
type Ethernet_Type struct {
	DMAMR      volatile.Register32 // 0x0
	DMASBMR    volatile.Register32 // 0x4
	DMAISR     volatile.Register32 // 0x8
	DMADSR     volatile.Register32 // 0xC
	_          [240]byte
	DMACCR     volatile.Register32 // 0x100
	DMACTxCR   volatile.Register32 // 0x104
	DMACRxCR   volatile.Register32 // 0x108
	_          [8]byte
	DMACTxDLAR volatile.Register32 // 0x114
	_          [4]byte
	DMACRxDLAR volatile.Register32 // 0x11C
	DMACTxDTPR volatile.Register32 // 0x120
	_          [4]byte
	DMACRxDTPR volatile.Register32 // 0x128
	DMACTxRLR  volatile.Register32 // 0x12C
	DMACRxRLR  volatile.Register32 // 0x130
	DMACIER    volatile.Register32 // 0x134
	DMACRxIWTR volatile.Register32 // 0x138
	_          [8]byte
	DMACCATxDR volatile.Register32 // 0x144
	_          [4]byte
	DMACCARxDR volatile.Register32 // 0x14C
	_          [4]byte
	DMACCATxBR volatile.Register32 // 0x154
	_          [4]byte
	DMACCARxBR volatile.Register32 // 0x15C
	DMACSR     volatile.Register32 // 0x160
	_          [8]byte
	DMACMFCR   volatile.Register32 // 0x16C
}

// DMA controller
type DMA_Type struct {
	LISR  volatile.Register32 // 0x0
	HISR  volatile.Register32 // 0x4
	LIFCR volatile.Register32 // 0x8
	HIFCR volatile.Register32 // 0xC
	ST    [8]struct {
		CR   volatile.Register32
		NDTR volatile.Register32
		PAR  volatile.Register32
		M0AR volatile.Register32
		M1AR volatile.Register32
		FCR  volatile.Register32
	} // 0x10
}

// High Resolution Timer: Master Timers
type HRTIM_Type struct {
	MCR    volatile.Register32 // 0x0
	MISR   volatile.Register32 // 0x4
	MICR   volatile.Register32 // 0x8
	MDIER4 volatile.Register32 // 0xC
	MCNTR  volatile.Register32 // 0x10
	MPER   volatile.Register32 // 0x14
	MREP   volatile.Register32 // 0x18
	MCMP1R volatile.Register32 // 0x1C
	_      [4]byte
	MCMP2R volatile.Register32 // 0x24
	MCMP3R volatile.Register32 // 0x28
	MCMP4R volatile.Register32 // 0x2C
}

// Digital filter for sigma delta modulators
type DFSDM_Type struct {
	DFSDM_CHCFG0R1  volatile.Register32 // 0x0
	DFSDM_CHCFG1R1  volatile.Register32 // 0x4
	DFSDM_CHCFG2R1  volatile.Register32 // 0x8
	DFSDM_CHCFG3R1  volatile.Register32 // 0xC
	DFSDM_CHCFG4R1  volatile.Register32 // 0x10
	DFSDM_CHCFG5R1  volatile.Register32 // 0x14
	DFSDM_CHCFG6R1  volatile.Register32 // 0x18
	DFSDM_CHCFG7R1  volatile.Register32 // 0x1C
	DFSDM_CHCFG0R2  volatile.Register32 // 0x20
	DFSDM_CHCFG1R2  volatile.Register32 // 0x24
	DFSDM_CHCFG2R2  volatile.Register32 // 0x28
	DFSDM_CHCFG3R2  volatile.Register32 // 0x2C
	DFSDM_CHCFG4R2  volatile.Register32 // 0x30
	DFSDM_CHCFG5R2  volatile.Register32 // 0x34
	DFSDM_CHCFG6R2  volatile.Register32 // 0x38
	DFSDM_CHCFG7R2  volatile.Register32 // 0x3C
	DFSDM_AWSCD0R   volatile.Register32 // 0x40
	DFSDM_AWSCD1R   volatile.Register32 // 0x44
	DFSDM_AWSCD2R   volatile.Register32 // 0x48
	DFSDM_AWSCD3R   volatile.Register32 // 0x4C
	DFSDM_AWSCD4R   volatile.Register32 // 0x50
	DFSDM_AWSCD5R   volatile.Register32 // 0x54
	DFSDM_AWSCD6R   volatile.Register32 // 0x58
	DFSDM_AWSCD7R   volatile.Register32 // 0x5C
	DFSDM_CHWDAT0R  volatile.Register32 // 0x60
	DFSDM_CHWDAT1R  volatile.Register32 // 0x64
	DFSDM_CHWDAT2R  volatile.Register32 // 0x68
	DFSDM_CHWDAT3R  volatile.Register32 // 0x6C
	DFSDM_CHWDAT4R  volatile.Register32 // 0x70
	DFSDM_CHWDAT5R  volatile.Register32 // 0x74
	DFSDM_CHWDAT6R  volatile.Register32 // 0x78
	DFSDM_CHWDAT7R  volatile.Register32 // 0x7C
	DFSDM_CHDATIN0R volatile.Register32 // 0x80
	DFSDM_CHDATIN1R volatile.Register32 // 0x84
	DFSDM_CHDATIN2R volatile.Register32 // 0x88
	DFSDM_CHDATIN3R volatile.Register32 // 0x8C
	DFSDM_CHDATIN4R volatile.Register32 // 0x90
	DFSDM_CHDATIN5R volatile.Register32 // 0x94
	DFSDM_CHDATIN6R volatile.Register32 // 0x98
	DFSDM_CHDATIN7R volatile.Register32 // 0x9C
	DFSDM0_CR1      volatile.Register32 // 0xA0
	DFSDM1_CR1      volatile.Register32 // 0xA4
	DFSDM2_CR1      volatile.Register32 // 0xA8
	DFSDM3_CR1      volatile.Register32 // 0xAC
	DFSDM0_CR2      volatile.Register32 // 0xB0
	DFSDM1_CR2      volatile.Register32 // 0xB4
	DFSDM2_CR2      volatile.Register32 // 0xB8
	DFSDM3_CR2      volatile.Register32 // 0xBC
	DFSDM0_ISR      volatile.Register32 // 0xC0
	DFSDM1_ISR      volatile.Register32 // 0xC4
	DFSDM2_ISR      volatile.Register32 // 0xC8
	DFSDM3_ISR      volatile.Register32 // 0xCC
	DFSDM0_ICR      volatile.Register32 // 0xD0
	DFSDM1_ICR      volatile.Register32 // 0xD4
	DFSDM2_ICR      volatile.Register32 // 0xD8
	DFSDM3_ICR      volatile.Register32 // 0xDC
	DFSDM0_JCHGR    volatile.Register32 // 0xE0
	DFSDM1_JCHGR    volatile.Register32 // 0xE4
	DFSDM2_JCHGR    volatile.Register32 // 0xE8
	DFSDM3_JCHGR    volatile.Register32 // 0xEC
	DFSDM0_FCR      volatile.Register32 // 0xF0
	DFSDM1_FCR      volatile.Register32 // 0xF4
	DFSDM2_FCR      volatile.Register32 // 0xF8
	DFSDM3_FCR      volatile.Register32 // 0xFC
	DFSDM0_JDATAR   volatile.Register32 // 0x100
	DFSDM1_JDATAR   volatile.Register32 // 0x104
	DFSDM2_JDATAR   volatile.Register32 // 0x108
	DFSDM3_JDATAR   volatile.Register32 // 0x10C
	DFSDM0_RDATAR   volatile.Register32 // 0x110
	DFSDM1_RDATAR   volatile.Register32 // 0x114
	DFSDM2_RDATAR   volatile.Register32 // 0x118
	DFSDM3_RDATAR   volatile.Register32 // 0x11C
	DFSDM0_AWHTR    volatile.Register32 // 0x120
	DFSDM1_AWHTR    volatile.Register32 // 0x124
	DFSDM2_AWHTR    volatile.Register32 // 0x128
	DFSDM3_AWHTR    volatile.Register32 // 0x12C
	DFSDM0_AWLTR    volatile.Register32 // 0x130
	DFSDM1_AWLTR    volatile.Register32 // 0x134
	DFSDM2_AWLTR    volatile.Register32 // 0x138
	DFSDM3_AWLTR    volatile.Register32 // 0x13C
	DFSDM0_AWSR     volatile.Register32 // 0x140
	DFSDM1_AWSR     volatile.Register32 // 0x144
	DFSDM2_AWSR     volatile.Register32 // 0x148
	DFSDM3_AWSR     volatile.Register32 // 0x14C
	DFSDM0_AWCFR    volatile.Register32 // 0x150
	DFSDM1_AWCFR    volatile.Register32 // 0x154
	DFSDM2_AWCFR    volatile.Register32 // 0x158
	DFSDM3_AWCFR    volatile.Register32 // 0x15C
	DFSDM0_EXMAX    volatile.Register32 // 0x160
	DFSDM1_EXMAX    volatile.Register32 // 0x164
	DFSDM2_EXMAX    volatile.Register32 // 0x168
	DFSDM3_EXMAX    volatile.Register32 // 0x16C
	DFSDM0_EXMIN    volatile.Register32 // 0x170
	DFSDM1_EXMIN    volatile.Register32 // 0x174
	DFSDM2_EXMIN    volatile.Register32 // 0x178
	DFSDM3_EXMIN    volatile.Register32 // 0x17C
	DFSDM0_CNVTIMR  volatile.Register32 // 0x180
	DFSDM1_CNVTIMR  volatile.Register32 // 0x184
	DFSDM2_CNVTIMR  volatile.Register32 // 0x188
	DFSDM3_CNVTIMR  volatile.Register32 // 0x18C
}

// General-purpose-timers
type TIMs_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	_            [4]byte
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	_            [4]byte
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	_            [12]byte
	BDTR         volatile.Register32 // 0x44
	DCR          volatile.Register32 // 0x48
	DMAR         volatile.Register32 // 0x4C
	_            [16]byte
	TIM16_AF1    volatile.Register32 // 0x60
	_            [4]byte
	TIM16_TISEL  volatile.Register32 // 0x68
}

// Universal synchronous asynchronous receiver transmitter
type USART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// Advanced-timers
type TIM_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	SMCR         volatile.Register32 // 0x8
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	CCMR2_Output volatile.Register32 // 0x1C
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	CCR2         volatile.Register32 // 0x38
	CCR3         volatile.Register32 // 0x3C
	CCR4         volatile.Register32 // 0x40
	BDTR         volatile.Register32 // 0x44
	DCR          volatile.Register32 // 0x48
	DMAR         volatile.Register32 // 0x4C
	_            [4]byte
	CCMR3_Output volatile.Register32 // 0x54
	CCR5         volatile.Register32 // 0x58
	CRR6         volatile.Register32 // 0x5C
	AF1          volatile.Register32 // 0x60
	AF2          volatile.Register32 // 0x64
	TISEL        volatile.Register32 // 0x68
}

// FDCAN1
type FDCAN_Type struct {
	CREL   volatile.Register32 // 0x0
	ENDN   volatile.Register32 // 0x4
	_      [4]byte
	DBTP   volatile.Register32 // 0xC
	TEST   volatile.Register32 // 0x10
	RWD    volatile.Register32 // 0x14
	CCCR   volatile.Register32 // 0x18
	NBTP   volatile.Register32 // 0x1C
	TSCC   volatile.Register32 // 0x20
	TSCV   volatile.Register32 // 0x24
	TOCC   volatile.Register32 // 0x28
	TOCV   volatile.Register32 // 0x2C
	_      [16]byte
	ECR    volatile.Register32 // 0x40
	PSR    volatile.Register32 // 0x44
	TDCR   volatile.Register32 // 0x48
	_      [4]byte
	IR     volatile.Register32 // 0x50
	IE     volatile.Register32 // 0x54
	ILS    volatile.Register32 // 0x58
	ILE    volatile.Register32 // 0x5C
	_      [32]byte
	GFC    volatile.Register32 // 0x80
	SIDFC  volatile.Register32 // 0x84
	XIDFC  volatile.Register32 // 0x88
	_      [4]byte
	XIDAM  volatile.Register32 // 0x90
	HPMS   volatile.Register32 // 0x94
	NDAT1  volatile.Register32 // 0x98
	NDAT2  volatile.Register32 // 0x9C
	RXF0C  volatile.Register32 // 0xA0
	RXF0S  volatile.Register32 // 0xA4
	RXF0A  volatile.Register32 // 0xA8
	RXBC   volatile.Register32 // 0xAC
	RXF1C  volatile.Register32 // 0xB0
	RXF1S  volatile.Register32 // 0xB4
	RXF1A  volatile.Register32 // 0xB8
	RXESC  volatile.Register32 // 0xBC
	TXBC   volatile.Register32 // 0xC0
	TXFQS  volatile.Register32 // 0xC4
	TXESC  volatile.Register32 // 0xC8
	TXBRP  volatile.Register32 // 0xCC
	TXBAR  volatile.Register32 // 0xD0
	TXBCR  volatile.Register32 // 0xD4
	TXBTO  volatile.Register32 // 0xD8
	TXBCF  volatile.Register32 // 0xDC
	TXBTIE volatile.Register32 // 0xE0
	TXBCIE volatile.Register32 // 0xE4
	_      [8]byte
	TXEFC  volatile.Register32 // 0xF0
	TXEFS  volatile.Register32 // 0xF4
	TXEFA  volatile.Register32 // 0xF8
	_      [4]byte
	TTTMC  volatile.Register32 // 0x100
	TTRMC  volatile.Register32 // 0x104
	TTOCF  volatile.Register32 // 0x108
	TTMLM  volatile.Register32 // 0x10C
	TURCF  volatile.Register32 // 0x110
	TTOCN  volatile.Register32 // 0x114
	TTGTP  volatile.Register32 // 0x118
	TTTMK  volatile.Register32 // 0x11C
	TTIR   volatile.Register32 // 0x120
	TTIE   volatile.Register32 // 0x124
	TTILS  volatile.Register32 // 0x128
	TTOST  volatile.Register32 // 0x12C
	TURNA  volatile.Register32 // 0x130
	TTLGT  volatile.Register32 // 0x134
	TTCTC  volatile.Register32 // 0x138
	TTCPT  volatile.Register32 // 0x13C
	TTCSM  volatile.Register32 // 0x140
	_      [444]byte
	TTTS   volatile.Register32 // 0x300
}

// Management data input/output slave
type MDIOS_Type struct {
	CR      volatile.Register32 // 0x0
	WRFR    volatile.Register32 // 0x4
	CWRFR   volatile.Register32 // 0x8
	RDFR    volatile.Register32 // 0xC
	CRDFR   volatile.Register32 // 0x10
	SR      volatile.Register32 // 0x14
	CLRFR   volatile.Register32 // 0x18
	DINR0   volatile.Register32 // 0x1C
	DINR1   volatile.Register32 // 0x20
	DINR2   volatile.Register32 // 0x24
	DINR3   volatile.Register32 // 0x28
	DINR4   volatile.Register32 // 0x2C
	DINR5   volatile.Register32 // 0x30
	DINR6   volatile.Register32 // 0x34
	DINR7   volatile.Register32 // 0x38
	DINR8   volatile.Register32 // 0x3C
	DINR9   volatile.Register32 // 0x40
	DINR10  volatile.Register32 // 0x44
	DINR11  volatile.Register32 // 0x48
	DINR12  volatile.Register32 // 0x4C
	DINR13  volatile.Register32 // 0x50
	DINR14  volatile.Register32 // 0x54
	DINR15  volatile.Register32 // 0x58
	DINR16  volatile.Register32 // 0x5C
	DINR17  volatile.Register32 // 0x60
	DINR18  volatile.Register32 // 0x64
	DINR19  volatile.Register32 // 0x68
	DINR20  volatile.Register32 // 0x6C
	DINR21  volatile.Register32 // 0x70
	DINR22  volatile.Register32 // 0x74
	DINR23  volatile.Register32 // 0x78
	DINR24  volatile.Register32 // 0x7C
	DINR25  volatile.Register32 // 0x80
	DINR26  volatile.Register32 // 0x84
	DINR27  volatile.Register32 // 0x88
	DINR28  volatile.Register32 // 0x8C
	DINR29  volatile.Register32 // 0x90
	DINR30  volatile.Register32 // 0x94
	DINR31  volatile.Register32 // 0x98
	DOUTR0  volatile.Register32 // 0x9C
	DOUTR1  volatile.Register32 // 0xA0
	DOUTR2  volatile.Register32 // 0xA4
	DOUTR3  volatile.Register32 // 0xA8
	DOUTR4  volatile.Register32 // 0xAC
	DOUTR5  volatile.Register32 // 0xB0
	DOUTR6  volatile.Register32 // 0xB4
	DOUTR7  volatile.Register32 // 0xB8
	DOUTR8  volatile.Register32 // 0xBC
	DOUTR9  volatile.Register32 // 0xC0
	DOUTR10 volatile.Register32 // 0xC4
	DOUTR11 volatile.Register32 // 0xC8
	DOUTR12 volatile.Register32 // 0xCC
	DOUTR13 volatile.Register32 // 0xD0
	DOUTR14 volatile.Register32 // 0xD4
	DOUTR15 volatile.Register32 // 0xD8
	DOUTR16 volatile.Register32 // 0xDC
	DOUTR17 volatile.Register32 // 0xE0
	DOUTR18 volatile.Register32 // 0xE4
	DOUTR19 volatile.Register32 // 0xE8
	DOUTR20 volatile.Register32 // 0xEC
	DOUTR21 volatile.Register32 // 0xF0
	DOUTR22 volatile.Register32 // 0xF4
	DOUTR23 volatile.Register32 // 0xF8
	DOUTR24 volatile.Register32 // 0xFC
	DOUTR25 volatile.Register32 // 0x100
	DOUTR26 volatile.Register32 // 0x104
	DOUTR27 volatile.Register32 // 0x108
	DOUTR28 volatile.Register32 // 0x10C
	DOUTR29 volatile.Register32 // 0x110
	DOUTR30 volatile.Register32 // 0x114
	DOUTR31 volatile.Register32 // 0x118
}

// Operational amplifiers
type OPAMP_Type struct {
	OPAMP1_CSR   volatile.Register32 // 0x0
	OPAMP1_OTR   volatile.Register32 // 0x4
	OPAMP1_HSOTR volatile.Register32 // 0x8
	_            [4]byte
	OPAMP2_CSR   volatile.Register32 // 0x10
	OPAMP2_OTR   volatile.Register32 // 0x14
	OPAMP2_HSOTR volatile.Register32 // 0x18
}

// Single Wire Protocol Master Interface
type SWPMI_Type struct {
	CR  volatile.Register32 // 0x0
	BRR volatile.Register32 // 0x4
	_   [4]byte
	ISR volatile.Register32 // 0xC
	ICR volatile.Register32 // 0x10
	IER volatile.Register32 // 0x14
	RFL volatile.Register32 // 0x18
	TDR volatile.Register32 // 0x1C
	RDR volatile.Register32 // 0x20
	OR  volatile.Register32 // 0x24
}

// Nested Vectored Interrupt Controller
type NVIC_Type struct {
	ISER0 volatile.Register32 // 0x0
	ISER1 volatile.Register32 // 0x4
	ISER2 volatile.Register32 // 0x8
	ISER3 volatile.Register32 // 0xC
	ISER4 volatile.Register32 // 0x10
	_     [108]byte
	ICER0 volatile.Register32 // 0x80
	ICER1 volatile.Register32 // 0x84
	ICER2 volatile.Register32 // 0x88
	ICER3 volatile.Register32 // 0x8C
	ICER4 volatile.Register32 // 0x90
	_     [108]byte
	ISPR0 volatile.Register32 // 0x100
	ISPR1 volatile.Register32 // 0x104
	ISPR2 volatile.Register32 // 0x108
	ISPR3 volatile.Register32 // 0x10C
	ISPR4 volatile.Register32 // 0x110
	_     [108]byte
	ICPR0 volatile.Register32 // 0x180
	ICPR1 volatile.Register32 // 0x184
	ICPR2 volatile.Register32 // 0x188
	_     [52]byte
	ICPR3 volatile.Register32 // 0x1C0
	ICPR4 volatile.Register32 // 0x1C4
	_     [56]byte
	IABR0 volatile.Register32 // 0x200
	IABR1 volatile.Register32 // 0x204
	IABR2 volatile.Register32 // 0x208
	IABR3 volatile.Register32 // 0x20C
	IABR4 volatile.Register32 // 0x210
	_     [236]byte
	IPR0  volatile.Register32 // 0x300
	IPR1  volatile.Register32 // 0x304
	IPR2  volatile.Register32 // 0x308
	IPR3  volatile.Register32 // 0x30C
	IPR4  volatile.Register32 // 0x310
	IPR5  volatile.Register32 // 0x314
	IPR6  volatile.Register32 // 0x318
	IPR7  volatile.Register32 // 0x31C
	IPR8  volatile.Register32 // 0x320
	IPR9  volatile.Register32 // 0x324
	IPR10 volatile.Register32 // 0x328
	IPR11 volatile.Register32 // 0x32C
	IPR12 volatile.Register32 // 0x330
	IPR13 volatile.Register32 // 0x334
	IPR14 volatile.Register32 // 0x338
	IPR15 volatile.Register32 // 0x33C
	IPR16 volatile.Register32 // 0x340
	IPR17 volatile.Register32 // 0x344
	IPR18 volatile.Register32 // 0x348
	IPR19 volatile.Register32 // 0x34C
	IPR20 volatile.Register32 // 0x350
	IPR21 volatile.Register32 // 0x354
	IPR22 volatile.Register32 // 0x358
	IPR23 volatile.Register32 // 0x35C
	IPR24 volatile.Register32 // 0x360
	IPR25 volatile.Register32 // 0x364
	IPR26 volatile.Register32 // 0x368
	IPR27 volatile.Register32 // 0x36C
	IPR28 volatile.Register32 // 0x370
	IPR29 volatile.Register32 // 0x374
	IPR30 volatile.Register32 // 0x378
	IPR31 volatile.Register32 // 0x37C
	IPR32 volatile.Register32 // 0x380
	IPR33 volatile.Register32 // 0x384
	IPR34 volatile.Register32 // 0x388
	IPR35 volatile.Register32 // 0x38C
	IPR36 volatile.Register32 // 0x390
	IPR37 volatile.Register32 // 0x394
	IPR38 volatile.Register32 // 0x398
	IPR39 volatile.Register32 // 0x39C
}

// Memory protection unit
type MPU_Type struct {
	MPU_TYPER volatile.Register32 // 0x0
	MPU_CTRL  volatile.Register32 // 0x4
	MPU_RNR   volatile.Register32 // 0x8
	MPU_RBAR  volatile.Register32 // 0xC
	MPU_RASR  volatile.Register32 // 0x10
}

// SysTick timer
type STK_Type struct {
	CSR   volatile.Register32 // 0x0
	RVR   volatile.Register32 // 0x4
	CVR   volatile.Register32 // 0x8
	CALIB volatile.Register32 // 0xC
}

// Floating point unit CPACR
type FPU_Type struct {
	CPACR volatile.Register32 // 0x0
}

// System control block ACTLR
type SCB_Type struct {
	ACTRL volatile.Register32 // 0x0
}

// Processor features
type PF_Type struct {
	CLIDR  volatile.Register32 // 0x0
	CTR    volatile.Register32 // 0x4
	CCSIDR volatile.Register32 // 0x8
}

// Access control
type AC_Type struct {
	ITCMCR volatile.Register32 // 0x0
	DTCMCR volatile.Register32 // 0x4
	AHBPCR volatile.Register32 // 0x8
	CACR   volatile.Register32 // 0xC
	AHBSCR volatile.Register32 // 0x10
	_      [4]byte
	ABFSR  volatile.Register32 // 0x18
}

// Debug support
type DBG_Type struct {
	IDC      volatile.Register32 // 0x0
	CR       volatile.Register32 // 0x4
	_        [44]byte
	APB3FZ1  volatile.Register32 // 0x34
	_        [4]byte
	APB1LFZ1 volatile.Register32 // 0x3C
	_        [12]byte
	APB2FZ1  volatile.Register32 // 0x4C
	_        [4]byte
	APB4FZ1  volatile.Register32 // 0x54
}

// RAM ECC monitoring
type RAMECC_Type struct {
	IER    volatile.Register32 // 0x0
	_      [28]byte
	M1CR   volatile.Register32 // 0x20
	M1SR   volatile.Register32 // 0x24
	M1FAR  volatile.Register32 // 0x28
	M1FDRL volatile.Register32 // 0x2C
	M1FDRH volatile.Register32 // 0x30
	M1FECR volatile.Register32 // 0x34
	_      [8]byte
	M2CR   volatile.Register32 // 0x40
	M2SR   volatile.Register32 // 0x44
	M2FAR  volatile.Register32 // 0x48
	M2FDRL volatile.Register32 // 0x4C
	M2FDRH volatile.Register32 // 0x50
	M2FECR volatile.Register32 // 0x54
	_      [8]byte
	M3CR   volatile.Register32 // 0x60
	M3SR   volatile.Register32 // 0x64
	M3FAR  volatile.Register32 // 0x68
	M3FDRL volatile.Register32 // 0x6C
	M3FDRH volatile.Register32 // 0x70
	M3FECR volatile.Register32 // 0x74
	_      [8]byte
	M4CR   volatile.Register32 // 0x80
	M4SR   volatile.Register32 // 0x84
	M4FAR  volatile.Register32 // 0x88
	M4FDRL volatile.Register32 // 0x8C
	M4FDRH volatile.Register32 // 0x90
	M4FECR volatile.Register32 // 0x94
	_      [8]byte
	M5CR   volatile.Register32 // 0xA0
	M5SR   volatile.Register32 // 0xA4
	M5FAR  volatile.Register32 // 0xA8
	M5FDRL volatile.Register32 // 0xAC
	M5FDRH volatile.Register32 // 0xB0
	M5FECR volatile.Register32 // 0xB4
}

// Bitfields for COMP1: COMP1
const (
	// SR: Comparator status register
	// Position of C1VAL field.
	COMP1_SR_C1VAL_Pos = 0x0
	// Bit mask of C1VAL field.
	COMP1_SR_C1VAL_Msk = 0x1
	// Bit C1VAL.
	COMP1_SR_C1VAL = 0x1
	// Position of C2VAL field.
	COMP1_SR_C2VAL_Pos = 0x1
	// Bit mask of C2VAL field.
	COMP1_SR_C2VAL_Msk = 0x2
	// Bit C2VAL.
	COMP1_SR_C2VAL = 0x2
	// Position of C1IF field.
	COMP1_SR_C1IF_Pos = 0x10
	// Bit mask of C1IF field.
	COMP1_SR_C1IF_Msk = 0x10000
	// Bit C1IF.
	COMP1_SR_C1IF = 0x10000
	// Position of C2IF field.
	COMP1_SR_C2IF_Pos = 0x11
	// Bit mask of C2IF field.
	COMP1_SR_C2IF_Msk = 0x20000
	// Bit C2IF.
	COMP1_SR_C2IF = 0x20000

	// ICFR: Comparator interrupt clear flag register
	// Position of CC1IF field.
	COMP1_ICFR_CC1IF_Pos = 0x10
	// Bit mask of CC1IF field.
	COMP1_ICFR_CC1IF_Msk = 0x10000
	// Bit CC1IF.
	COMP1_ICFR_CC1IF = 0x10000
	// Position of CC2IF field.
	COMP1_ICFR_CC2IF_Pos = 0x11
	// Bit mask of CC2IF field.
	COMP1_ICFR_CC2IF_Msk = 0x20000
	// Bit CC2IF.
	COMP1_ICFR_CC2IF = 0x20000

	// OR: Comparator option register
	// Position of AFOP field.
	COMP1_OR_AFOP_Pos = 0x0
	// Bit mask of AFOP field.
	COMP1_OR_AFOP_Msk = 0x7ff
	// Position of OR field.
	COMP1_OR_OR_Pos = 0xb
	// Bit mask of OR field.
	COMP1_OR_OR_Msk = 0xfffff800

	// CFGR1: Comparator configuration register 1
	// Position of EN field.
	COMP1_CFGR1_EN_Pos = 0x0
	// Bit mask of EN field.
	COMP1_CFGR1_EN_Msk = 0x1
	// Bit EN.
	COMP1_CFGR1_EN = 0x1
	// Position of BRGEN field.
	COMP1_CFGR1_BRGEN_Pos = 0x1
	// Bit mask of BRGEN field.
	COMP1_CFGR1_BRGEN_Msk = 0x2
	// Bit BRGEN.
	COMP1_CFGR1_BRGEN = 0x2
	// Position of SCALEN field.
	COMP1_CFGR1_SCALEN_Pos = 0x2
	// Bit mask of SCALEN field.
	COMP1_CFGR1_SCALEN_Msk = 0x4
	// Bit SCALEN.
	COMP1_CFGR1_SCALEN = 0x4
	// Position of POLARITY field.
	COMP1_CFGR1_POLARITY_Pos = 0x3
	// Bit mask of POLARITY field.
	COMP1_CFGR1_POLARITY_Msk = 0x8
	// Bit POLARITY.
	COMP1_CFGR1_POLARITY = 0x8
	// Position of ITEN field.
	COMP1_CFGR1_ITEN_Pos = 0x6
	// Bit mask of ITEN field.
	COMP1_CFGR1_ITEN_Msk = 0x40
	// Bit ITEN.
	COMP1_CFGR1_ITEN = 0x40
	// Position of HYST field.
	COMP1_CFGR1_HYST_Pos = 0x8
	// Bit mask of HYST field.
	COMP1_CFGR1_HYST_Msk = 0x300
	// Position of PWRMODE field.
	COMP1_CFGR1_PWRMODE_Pos = 0xc
	// Bit mask of PWRMODE field.
	COMP1_CFGR1_PWRMODE_Msk = 0x3000
	// Position of INMSEL field.
	COMP1_CFGR1_INMSEL_Pos = 0x10
	// Bit mask of INMSEL field.
	COMP1_CFGR1_INMSEL_Msk = 0x70000
	// Position of INPSEL field.
	COMP1_CFGR1_INPSEL_Pos = 0x14
	// Bit mask of INPSEL field.
	COMP1_CFGR1_INPSEL_Msk = 0x100000
	// Bit INPSEL.
	COMP1_CFGR1_INPSEL = 0x100000
	// Position of BLANKING field.
	COMP1_CFGR1_BLANKING_Pos = 0x18
	// Bit mask of BLANKING field.
	COMP1_CFGR1_BLANKING_Msk = 0xf000000
	// Position of LOCK field.
	COMP1_CFGR1_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	COMP1_CFGR1_LOCK_Msk = 0x80000000
	// Bit LOCK.
	COMP1_CFGR1_LOCK = 0x80000000

	// CFGR2: Comparator configuration register 2
	// Position of EN field.
	COMP1_CFGR2_EN_Pos = 0x0
	// Bit mask of EN field.
	COMP1_CFGR2_EN_Msk = 0x1
	// Bit EN.
	COMP1_CFGR2_EN = 0x1
	// Position of BRGEN field.
	COMP1_CFGR2_BRGEN_Pos = 0x1
	// Bit mask of BRGEN field.
	COMP1_CFGR2_BRGEN_Msk = 0x2
	// Bit BRGEN.
	COMP1_CFGR2_BRGEN = 0x2
	// Position of SCALEN field.
	COMP1_CFGR2_SCALEN_Pos = 0x2
	// Bit mask of SCALEN field.
	COMP1_CFGR2_SCALEN_Msk = 0x4
	// Bit SCALEN.
	COMP1_CFGR2_SCALEN = 0x4
	// Position of POLARITY field.
	COMP1_CFGR2_POLARITY_Pos = 0x3
	// Bit mask of POLARITY field.
	COMP1_CFGR2_POLARITY_Msk = 0x8
	// Bit POLARITY.
	COMP1_CFGR2_POLARITY = 0x8
	// Position of WINMODE field.
	COMP1_CFGR2_WINMODE_Pos = 0x4
	// Bit mask of WINMODE field.
	COMP1_CFGR2_WINMODE_Msk = 0x10
	// Bit WINMODE.
	COMP1_CFGR2_WINMODE = 0x10
	// Position of ITEN field.
	COMP1_CFGR2_ITEN_Pos = 0x6
	// Bit mask of ITEN field.
	COMP1_CFGR2_ITEN_Msk = 0x40
	// Bit ITEN.
	COMP1_CFGR2_ITEN = 0x40
	// Position of HYST field.
	COMP1_CFGR2_HYST_Pos = 0x8
	// Bit mask of HYST field.
	COMP1_CFGR2_HYST_Msk = 0x300
	// Position of PWRMODE field.
	COMP1_CFGR2_PWRMODE_Pos = 0xc
	// Bit mask of PWRMODE field.
	COMP1_CFGR2_PWRMODE_Msk = 0x3000
	// Position of INMSEL field.
	COMP1_CFGR2_INMSEL_Pos = 0x10
	// Bit mask of INMSEL field.
	COMP1_CFGR2_INMSEL_Msk = 0x70000
	// Position of INPSEL field.
	COMP1_CFGR2_INPSEL_Pos = 0x14
	// Bit mask of INPSEL field.
	COMP1_CFGR2_INPSEL_Msk = 0x100000
	// Bit INPSEL.
	COMP1_CFGR2_INPSEL = 0x100000
	// Position of BLANKING field.
	COMP1_CFGR2_BLANKING_Pos = 0x18
	// Bit mask of BLANKING field.
	COMP1_CFGR2_BLANKING_Msk = 0xf000000
	// Position of LOCK field.
	COMP1_CFGR2_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	COMP1_CFGR2_LOCK_Msk = 0x80000000
	// Bit LOCK.
	COMP1_CFGR2_LOCK = 0x80000000
)

// Bitfields for CRS: CRS
const (
	// CR: CRS control register
	// Position of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Pos = 0x0
	// Bit mask of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Msk = 0x1
	// Bit SYNCOKIE.
	CRS_CR_SYNCOKIE = 0x1
	// Position of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Pos = 0x1
	// Bit mask of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Msk = 0x2
	// Bit SYNCWARNIE.
	CRS_CR_SYNCWARNIE = 0x2
	// Position of ERRIE field.
	CRS_CR_ERRIE_Pos = 0x2
	// Bit mask of ERRIE field.
	CRS_CR_ERRIE_Msk = 0x4
	// Bit ERRIE.
	CRS_CR_ERRIE = 0x4
	// Position of ESYNCIE field.
	CRS_CR_ESYNCIE_Pos = 0x3
	// Bit mask of ESYNCIE field.
	CRS_CR_ESYNCIE_Msk = 0x8
	// Bit ESYNCIE.
	CRS_CR_ESYNCIE = 0x8
	// Position of CEN field.
	CRS_CR_CEN_Pos = 0x5
	// Bit mask of CEN field.
	CRS_CR_CEN_Msk = 0x20
	// Bit CEN.
	CRS_CR_CEN = 0x20
	// Position of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Pos = 0x6
	// Bit mask of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Msk = 0x40
	// Bit AUTOTRIMEN.
	CRS_CR_AUTOTRIMEN = 0x40
	// Position of SWSYNC field.
	CRS_CR_SWSYNC_Pos = 0x7
	// Bit mask of SWSYNC field.
	CRS_CR_SWSYNC_Msk = 0x80
	// Bit SWSYNC.
	CRS_CR_SWSYNC = 0x80
	// Position of TRIM field.
	CRS_CR_TRIM_Pos = 0x8
	// Bit mask of TRIM field.
	CRS_CR_TRIM_Msk = 0x3f00

	// CFGR: This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.
	// Position of RELOAD field.
	CRS_CFGR_RELOAD_Pos = 0x0
	// Bit mask of RELOAD field.
	CRS_CFGR_RELOAD_Msk = 0xffff
	// Position of FELIM field.
	CRS_CFGR_FELIM_Pos = 0x10
	// Bit mask of FELIM field.
	CRS_CFGR_FELIM_Msk = 0xff0000
	// Position of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Pos = 0x18
	// Bit mask of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Msk = 0x7000000
	// Position of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Pos = 0x1c
	// Bit mask of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Msk = 0x30000000
	// Position of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Pos = 0x1f
	// Bit mask of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Msk = 0x80000000
	// Bit SYNCPOL.
	CRS_CFGR_SYNCPOL = 0x80000000

	// ISR: CRS interrupt and status register
	// Position of SYNCOKF field.
	CRS_ISR_SYNCOKF_Pos = 0x0
	// Bit mask of SYNCOKF field.
	CRS_ISR_SYNCOKF_Msk = 0x1
	// Bit SYNCOKF.
	CRS_ISR_SYNCOKF = 0x1
	// Position of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Pos = 0x1
	// Bit mask of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Msk = 0x2
	// Bit SYNCWARNF.
	CRS_ISR_SYNCWARNF = 0x2
	// Position of ERRF field.
	CRS_ISR_ERRF_Pos = 0x2
	// Bit mask of ERRF field.
	CRS_ISR_ERRF_Msk = 0x4
	// Bit ERRF.
	CRS_ISR_ERRF = 0x4
	// Position of ESYNCF field.
	CRS_ISR_ESYNCF_Pos = 0x3
	// Bit mask of ESYNCF field.
	CRS_ISR_ESYNCF_Msk = 0x8
	// Bit ESYNCF.
	CRS_ISR_ESYNCF = 0x8
	// Position of SYNCERR field.
	CRS_ISR_SYNCERR_Pos = 0x8
	// Bit mask of SYNCERR field.
	CRS_ISR_SYNCERR_Msk = 0x100
	// Bit SYNCERR.
	CRS_ISR_SYNCERR = 0x100
	// Position of SYNCMISS field.
	CRS_ISR_SYNCMISS_Pos = 0x9
	// Bit mask of SYNCMISS field.
	CRS_ISR_SYNCMISS_Msk = 0x200
	// Bit SYNCMISS.
	CRS_ISR_SYNCMISS = 0x200
	// Position of TRIMOVF field.
	CRS_ISR_TRIMOVF_Pos = 0xa
	// Bit mask of TRIMOVF field.
	CRS_ISR_TRIMOVF_Msk = 0x400
	// Bit TRIMOVF.
	CRS_ISR_TRIMOVF = 0x400
	// Position of FEDIR field.
	CRS_ISR_FEDIR_Pos = 0xf
	// Bit mask of FEDIR field.
	CRS_ISR_FEDIR_Msk = 0x8000
	// Bit FEDIR.
	CRS_ISR_FEDIR = 0x8000
	// Position of FECAP field.
	CRS_ISR_FECAP_Pos = 0x10
	// Bit mask of FECAP field.
	CRS_ISR_FECAP_Msk = 0xffff0000

	// ICR: CRS interrupt flag clear register
	// Position of SYNCOKC field.
	CRS_ICR_SYNCOKC_Pos = 0x0
	// Bit mask of SYNCOKC field.
	CRS_ICR_SYNCOKC_Msk = 0x1
	// Bit SYNCOKC.
	CRS_ICR_SYNCOKC = 0x1
	// Position of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Pos = 0x1
	// Bit mask of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Msk = 0x2
	// Bit SYNCWARNC.
	CRS_ICR_SYNCWARNC = 0x2
	// Position of ERRC field.
	CRS_ICR_ERRC_Pos = 0x2
	// Bit mask of ERRC field.
	CRS_ICR_ERRC_Msk = 0x4
	// Bit ERRC.
	CRS_ICR_ERRC = 0x4
	// Position of ESYNCC field.
	CRS_ICR_ESYNCC_Pos = 0x3
	// Bit mask of ESYNCC field.
	CRS_ICR_ESYNCC_Msk = 0x8
	// Bit ESYNCC.
	CRS_ICR_ESYNCC = 0x8
)

// Bitfields for DAC: DAC
const (
	// CR: DAC control register
	// Position of EN1 field.
	DAC_CR_EN1_Pos = 0x0
	// Bit mask of EN1 field.
	DAC_CR_EN1_Msk = 0x1
	// Bit EN1.
	DAC_CR_EN1 = 0x1
	// Position of TEN1 field.
	DAC_CR_TEN1_Pos = 0x1
	// Bit mask of TEN1 field.
	DAC_CR_TEN1_Msk = 0x2
	// Bit TEN1.
	DAC_CR_TEN1 = 0x2
	// Position of TSEL1 field.
	DAC_CR_TSEL1_Pos = 0x2
	// Bit mask of TSEL1 field.
	DAC_CR_TSEL1_Msk = 0x1c
	// Position of WAVE1 field.
	DAC_CR_WAVE1_Pos = 0x6
	// Bit mask of WAVE1 field.
	DAC_CR_WAVE1_Msk = 0xc0
	// Position of MAMP1 field.
	DAC_CR_MAMP1_Pos = 0x8
	// Bit mask of MAMP1 field.
	DAC_CR_MAMP1_Msk = 0xf00
	// Position of DMAEN1 field.
	DAC_CR_DMAEN1_Pos = 0xc
	// Bit mask of DMAEN1 field.
	DAC_CR_DMAEN1_Msk = 0x1000
	// Bit DMAEN1.
	DAC_CR_DMAEN1 = 0x1000
	// Position of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1_Pos = 0xd
	// Bit mask of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1_Msk = 0x2000
	// Bit DMAUDRIE1.
	DAC_CR_DMAUDRIE1 = 0x2000
	// Position of CEN1 field.
	DAC_CR_CEN1_Pos = 0xe
	// Bit mask of CEN1 field.
	DAC_CR_CEN1_Msk = 0x4000
	// Bit CEN1.
	DAC_CR_CEN1 = 0x4000
	// Position of EN2 field.
	DAC_CR_EN2_Pos = 0x10
	// Bit mask of EN2 field.
	DAC_CR_EN2_Msk = 0x10000
	// Bit EN2.
	DAC_CR_EN2 = 0x10000
	// Position of TEN2 field.
	DAC_CR_TEN2_Pos = 0x11
	// Bit mask of TEN2 field.
	DAC_CR_TEN2_Msk = 0x20000
	// Bit TEN2.
	DAC_CR_TEN2 = 0x20000
	// Position of TSEL2 field.
	DAC_CR_TSEL2_Pos = 0x12
	// Bit mask of TSEL2 field.
	DAC_CR_TSEL2_Msk = 0x1c0000
	// Position of WAVE2 field.
	DAC_CR_WAVE2_Pos = 0x16
	// Bit mask of WAVE2 field.
	DAC_CR_WAVE2_Msk = 0xc00000
	// Position of MAMP2 field.
	DAC_CR_MAMP2_Pos = 0x18
	// Bit mask of MAMP2 field.
	DAC_CR_MAMP2_Msk = 0xf000000
	// Position of DMAEN2 field.
	DAC_CR_DMAEN2_Pos = 0x1c
	// Bit mask of DMAEN2 field.
	DAC_CR_DMAEN2_Msk = 0x10000000
	// Bit DMAEN2.
	DAC_CR_DMAEN2 = 0x10000000
	// Position of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2_Pos = 0x1d
	// Bit mask of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2_Msk = 0x20000000
	// Bit DMAUDRIE2.
	DAC_CR_DMAUDRIE2 = 0x20000000
	// Position of CEN2 field.
	DAC_CR_CEN2_Pos = 0x1e
	// Bit mask of CEN2 field.
	DAC_CR_CEN2_Msk = 0x40000000
	// Bit CEN2.
	DAC_CR_CEN2 = 0x40000000

	// SWTRGR: DAC software trigger register
	// Position of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1_Pos = 0x0
	// Bit mask of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1_Msk = 0x1
	// Bit SWTRIG1.
	DAC_SWTRGR_SWTRIG1 = 0x1
	// Position of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2_Pos = 0x1
	// Bit mask of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2_Msk = 0x2
	// Bit SWTRIG2.
	DAC_SWTRGR_SWTRIG2 = 0x2

	// DHR12R1: DAC channel1 12-bit right-aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12R1_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC_DHR12R1_DACC1DHR_Msk = 0xfff

	// DHR12L1: DAC channel1 12-bit left aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12L1_DACC1DHR_Pos = 0x4
	// Bit mask of DACC1DHR field.
	DAC_DHR12L1_DACC1DHR_Msk = 0xfff0

	// DHR8R1: DAC channel1 8-bit right aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR8R1_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC_DHR8R1_DACC1DHR_Msk = 0xff

	// DHR12R2: DAC channel2 12-bit right aligned data holding register
	// Position of DACC2DHR field.
	DAC_DHR12R2_DACC2DHR_Pos = 0x0
	// Bit mask of DACC2DHR field.
	DAC_DHR12R2_DACC2DHR_Msk = 0xfff

	// DHR12L2: DAC channel2 12-bit left aligned data holding register
	// Position of DACC2DHR field.
	DAC_DHR12L2_DACC2DHR_Pos = 0x4
	// Bit mask of DACC2DHR field.
	DAC_DHR12L2_DACC2DHR_Msk = 0xfff0

	// DHR8R2: DAC channel2 8-bit right-aligned data holding register
	// Position of DACC2DHR field.
	DAC_DHR8R2_DACC2DHR_Pos = 0x0
	// Bit mask of DACC2DHR field.
	DAC_DHR8R2_DACC2DHR_Msk = 0xff

	// DHR12RD: Dual DAC 12-bit right-aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12RD_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC_DHR12RD_DACC1DHR_Msk = 0xfff
	// Position of DACC2DHR field.
	DAC_DHR12RD_DACC2DHR_Pos = 0x10
	// Bit mask of DACC2DHR field.
	DAC_DHR12RD_DACC2DHR_Msk = 0xfff0000

	// DHR12LD: DUAL DAC 12-bit left aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12LD_DACC1DHR_Pos = 0x4
	// Bit mask of DACC1DHR field.
	DAC_DHR12LD_DACC1DHR_Msk = 0xfff0
	// Position of DACC2DHR field.
	DAC_DHR12LD_DACC2DHR_Pos = 0x14
	// Bit mask of DACC2DHR field.
	DAC_DHR12LD_DACC2DHR_Msk = 0xfff00000

	// DHR8RD: DUAL DAC 8-bit right aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR8RD_DACC1DHR_Pos = 0x0
	// Bit mask of DACC1DHR field.
	DAC_DHR8RD_DACC1DHR_Msk = 0xff
	// Position of DACC2DHR field.
	DAC_DHR8RD_DACC2DHR_Pos = 0x8
	// Bit mask of DACC2DHR field.
	DAC_DHR8RD_DACC2DHR_Msk = 0xff00

	// DOR1: DAC channel1 data output register
	// Position of DACC1DOR field.
	DAC_DOR1_DACC1DOR_Pos = 0x0
	// Bit mask of DACC1DOR field.
	DAC_DOR1_DACC1DOR_Msk = 0xfff

	// DOR2: DAC channel2 data output register
	// Position of DACC2DOR field.
	DAC_DOR2_DACC2DOR_Pos = 0x0
	// Bit mask of DACC2DOR field.
	DAC_DOR2_DACC2DOR_Msk = 0xfff

	// SR: DAC status register
	// Position of DMAUDR1 field.
	DAC_SR_DMAUDR1_Pos = 0xd
	// Bit mask of DMAUDR1 field.
	DAC_SR_DMAUDR1_Msk = 0x2000
	// Bit DMAUDR1.
	DAC_SR_DMAUDR1 = 0x2000
	// Position of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1_Pos = 0xe
	// Bit mask of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1_Msk = 0x4000
	// Bit CAL_FLAG1.
	DAC_SR_CAL_FLAG1 = 0x4000
	// Position of BWST1 field.
	DAC_SR_BWST1_Pos = 0xf
	// Bit mask of BWST1 field.
	DAC_SR_BWST1_Msk = 0x8000
	// Bit BWST1.
	DAC_SR_BWST1 = 0x8000
	// Position of DMAUDR2 field.
	DAC_SR_DMAUDR2_Pos = 0x1d
	// Bit mask of DMAUDR2 field.
	DAC_SR_DMAUDR2_Msk = 0x20000000
	// Bit DMAUDR2.
	DAC_SR_DMAUDR2 = 0x20000000
	// Position of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2_Pos = 0x1e
	// Bit mask of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2_Msk = 0x40000000
	// Bit CAL_FLAG2.
	DAC_SR_CAL_FLAG2 = 0x40000000
	// Position of BWST2 field.
	DAC_SR_BWST2_Pos = 0x1f
	// Bit mask of BWST2 field.
	DAC_SR_BWST2_Msk = 0x80000000
	// Bit BWST2.
	DAC_SR_BWST2 = 0x80000000

	// CCR: DAC calibration control register
	// Position of OTRIM1 field.
	DAC_CCR_OTRIM1_Pos = 0x0
	// Bit mask of OTRIM1 field.
	DAC_CCR_OTRIM1_Msk = 0x1f
	// Position of OTRIM2 field.
	DAC_CCR_OTRIM2_Pos = 0x10
	// Bit mask of OTRIM2 field.
	DAC_CCR_OTRIM2_Msk = 0x1f0000

	// MCR: DAC mode control register
	// Position of MODE1 field.
	DAC_MCR_MODE1_Pos = 0x0
	// Bit mask of MODE1 field.
	DAC_MCR_MODE1_Msk = 0x7
	// Position of MODE2 field.
	DAC_MCR_MODE2_Pos = 0x10
	// Bit mask of MODE2 field.
	DAC_MCR_MODE2_Msk = 0x70000

	// SHSR1: DAC Sample and Hold sample time register 1
	// Position of TSAMPLE1 field.
	DAC_SHSR1_TSAMPLE1_Pos = 0x0
	// Bit mask of TSAMPLE1 field.
	DAC_SHSR1_TSAMPLE1_Msk = 0x3ff

	// SHSR2: DAC Sample and Hold sample time register 2
	// Position of TSAMPLE2 field.
	DAC_SHSR2_TSAMPLE2_Pos = 0x0
	// Bit mask of TSAMPLE2 field.
	DAC_SHSR2_TSAMPLE2_Msk = 0x3ff

	// SHHR: DAC Sample and Hold hold time register
	// Position of THOLD1 field.
	DAC_SHHR_THOLD1_Pos = 0x0
	// Bit mask of THOLD1 field.
	DAC_SHHR_THOLD1_Msk = 0x3ff
	// Position of THOLD2 field.
	DAC_SHHR_THOLD2_Pos = 0x10
	// Bit mask of THOLD2 field.
	DAC_SHHR_THOLD2_Msk = 0x3ff0000

	// SHRR: DAC Sample and Hold refresh time register
	// Position of TREFRESH1 field.
	DAC_SHRR_TREFRESH1_Pos = 0x0
	// Bit mask of TREFRESH1 field.
	DAC_SHRR_TREFRESH1_Msk = 0xff
	// Position of TREFRESH2 field.
	DAC_SHRR_TREFRESH2_Pos = 0x10
	// Bit mask of TREFRESH2 field.
	DAC_SHRR_TREFRESH2_Msk = 0xff0000
)

// Bitfields for BDMA: BDMA
const (
	// ISR: DMA interrupt status register
	// Position of GIF1 field.
	BDMA_ISR_GIF1_Pos = 0x0
	// Bit mask of GIF1 field.
	BDMA_ISR_GIF1_Msk = 0x1
	// Bit GIF1.
	BDMA_ISR_GIF1 = 0x1
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF1_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF1_Event = 0x1
	// Position of TCIF1 field.
	BDMA_ISR_TCIF1_Pos = 0x1
	// Bit mask of TCIF1 field.
	BDMA_ISR_TCIF1_Msk = 0x2
	// Bit TCIF1.
	BDMA_ISR_TCIF1 = 0x2
	// No transfer complete event on channel x
	BDMA_ISR_TCIF1_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF1_Complete = 0x1
	// Position of HTIF1 field.
	BDMA_ISR_HTIF1_Pos = 0x2
	// Bit mask of HTIF1 field.
	BDMA_ISR_HTIF1_Msk = 0x4
	// Bit HTIF1.
	BDMA_ISR_HTIF1 = 0x4
	// No half transfer event on channel x
	BDMA_ISR_HTIF1_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF1_Half = 0x1
	// Position of TEIF1 field.
	BDMA_ISR_TEIF1_Pos = 0x3
	// Bit mask of TEIF1 field.
	BDMA_ISR_TEIF1_Msk = 0x8
	// Bit TEIF1.
	BDMA_ISR_TEIF1 = 0x8
	// No transfer error on channel x
	BDMA_ISR_TEIF1_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF1_Error = 0x1
	// Position of GIF2 field.
	BDMA_ISR_GIF2_Pos = 0x4
	// Bit mask of GIF2 field.
	BDMA_ISR_GIF2_Msk = 0x10
	// Bit GIF2.
	BDMA_ISR_GIF2 = 0x10
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF2_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF2_Event = 0x1
	// Position of TCIF2 field.
	BDMA_ISR_TCIF2_Pos = 0x5
	// Bit mask of TCIF2 field.
	BDMA_ISR_TCIF2_Msk = 0x20
	// Bit TCIF2.
	BDMA_ISR_TCIF2 = 0x20
	// No transfer complete event on channel x
	BDMA_ISR_TCIF2_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF2_Complete = 0x1
	// Position of HTIF2 field.
	BDMA_ISR_HTIF2_Pos = 0x6
	// Bit mask of HTIF2 field.
	BDMA_ISR_HTIF2_Msk = 0x40
	// Bit HTIF2.
	BDMA_ISR_HTIF2 = 0x40
	// No half transfer event on channel x
	BDMA_ISR_HTIF2_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF2_Half = 0x1
	// Position of TEIF2 field.
	BDMA_ISR_TEIF2_Pos = 0x7
	// Bit mask of TEIF2 field.
	BDMA_ISR_TEIF2_Msk = 0x80
	// Bit TEIF2.
	BDMA_ISR_TEIF2 = 0x80
	// No transfer error on channel x
	BDMA_ISR_TEIF2_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF2_Error = 0x1
	// Position of GIF3 field.
	BDMA_ISR_GIF3_Pos = 0x8
	// Bit mask of GIF3 field.
	BDMA_ISR_GIF3_Msk = 0x100
	// Bit GIF3.
	BDMA_ISR_GIF3 = 0x100
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF3_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF3_Event = 0x1
	// Position of TCIF3 field.
	BDMA_ISR_TCIF3_Pos = 0x9
	// Bit mask of TCIF3 field.
	BDMA_ISR_TCIF3_Msk = 0x200
	// Bit TCIF3.
	BDMA_ISR_TCIF3 = 0x200
	// No transfer complete event on channel x
	BDMA_ISR_TCIF3_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF3_Complete = 0x1
	// Position of HTIF3 field.
	BDMA_ISR_HTIF3_Pos = 0xa
	// Bit mask of HTIF3 field.
	BDMA_ISR_HTIF3_Msk = 0x400
	// Bit HTIF3.
	BDMA_ISR_HTIF3 = 0x400
	// No half transfer event on channel x
	BDMA_ISR_HTIF3_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF3_Half = 0x1
	// Position of TEIF3 field.
	BDMA_ISR_TEIF3_Pos = 0xb
	// Bit mask of TEIF3 field.
	BDMA_ISR_TEIF3_Msk = 0x800
	// Bit TEIF3.
	BDMA_ISR_TEIF3 = 0x800
	// No transfer error on channel x
	BDMA_ISR_TEIF3_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF3_Error = 0x1
	// Position of GIF4 field.
	BDMA_ISR_GIF4_Pos = 0xc
	// Bit mask of GIF4 field.
	BDMA_ISR_GIF4_Msk = 0x1000
	// Bit GIF4.
	BDMA_ISR_GIF4 = 0x1000
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF4_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF4_Event = 0x1
	// Position of TCIF4 field.
	BDMA_ISR_TCIF4_Pos = 0xd
	// Bit mask of TCIF4 field.
	BDMA_ISR_TCIF4_Msk = 0x2000
	// Bit TCIF4.
	BDMA_ISR_TCIF4 = 0x2000
	// No transfer complete event on channel x
	BDMA_ISR_TCIF4_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF4_Complete = 0x1
	// Position of HTIF4 field.
	BDMA_ISR_HTIF4_Pos = 0xe
	// Bit mask of HTIF4 field.
	BDMA_ISR_HTIF4_Msk = 0x4000
	// Bit HTIF4.
	BDMA_ISR_HTIF4 = 0x4000
	// No half transfer event on channel x
	BDMA_ISR_HTIF4_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF4_Half = 0x1
	// Position of TEIF4 field.
	BDMA_ISR_TEIF4_Pos = 0xf
	// Bit mask of TEIF4 field.
	BDMA_ISR_TEIF4_Msk = 0x8000
	// Bit TEIF4.
	BDMA_ISR_TEIF4 = 0x8000
	// No transfer error on channel x
	BDMA_ISR_TEIF4_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF4_Error = 0x1
	// Position of GIF5 field.
	BDMA_ISR_GIF5_Pos = 0x10
	// Bit mask of GIF5 field.
	BDMA_ISR_GIF5_Msk = 0x10000
	// Bit GIF5.
	BDMA_ISR_GIF5 = 0x10000
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF5_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF5_Event = 0x1
	// Position of TCIF5 field.
	BDMA_ISR_TCIF5_Pos = 0x11
	// Bit mask of TCIF5 field.
	BDMA_ISR_TCIF5_Msk = 0x20000
	// Bit TCIF5.
	BDMA_ISR_TCIF5 = 0x20000
	// No transfer complete event on channel x
	BDMA_ISR_TCIF5_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF5_Complete = 0x1
	// Position of HTIF5 field.
	BDMA_ISR_HTIF5_Pos = 0x12
	// Bit mask of HTIF5 field.
	BDMA_ISR_HTIF5_Msk = 0x40000
	// Bit HTIF5.
	BDMA_ISR_HTIF5 = 0x40000
	// No half transfer event on channel x
	BDMA_ISR_HTIF5_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF5_Half = 0x1
	// Position of TEIF5 field.
	BDMA_ISR_TEIF5_Pos = 0x13
	// Bit mask of TEIF5 field.
	BDMA_ISR_TEIF5_Msk = 0x80000
	// Bit TEIF5.
	BDMA_ISR_TEIF5 = 0x80000
	// No transfer error on channel x
	BDMA_ISR_TEIF5_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF5_Error = 0x1
	// Position of GIF6 field.
	BDMA_ISR_GIF6_Pos = 0x14
	// Bit mask of GIF6 field.
	BDMA_ISR_GIF6_Msk = 0x100000
	// Bit GIF6.
	BDMA_ISR_GIF6 = 0x100000
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF6_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF6_Event = 0x1
	// Position of TCIF6 field.
	BDMA_ISR_TCIF6_Pos = 0x15
	// Bit mask of TCIF6 field.
	BDMA_ISR_TCIF6_Msk = 0x200000
	// Bit TCIF6.
	BDMA_ISR_TCIF6 = 0x200000
	// No transfer complete event on channel x
	BDMA_ISR_TCIF6_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF6_Complete = 0x1
	// Position of HTIF6 field.
	BDMA_ISR_HTIF6_Pos = 0x16
	// Bit mask of HTIF6 field.
	BDMA_ISR_HTIF6_Msk = 0x400000
	// Bit HTIF6.
	BDMA_ISR_HTIF6 = 0x400000
	// No half transfer event on channel x
	BDMA_ISR_HTIF6_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF6_Half = 0x1
	// Position of TEIF6 field.
	BDMA_ISR_TEIF6_Pos = 0x17
	// Bit mask of TEIF6 field.
	BDMA_ISR_TEIF6_Msk = 0x800000
	// Bit TEIF6.
	BDMA_ISR_TEIF6 = 0x800000
	// No transfer error on channel x
	BDMA_ISR_TEIF6_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF6_Error = 0x1
	// Position of GIF7 field.
	BDMA_ISR_GIF7_Pos = 0x18
	// Bit mask of GIF7 field.
	BDMA_ISR_GIF7_Msk = 0x1000000
	// Bit GIF7.
	BDMA_ISR_GIF7 = 0x1000000
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF7_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF7_Event = 0x1
	// Position of TCIF7 field.
	BDMA_ISR_TCIF7_Pos = 0x19
	// Bit mask of TCIF7 field.
	BDMA_ISR_TCIF7_Msk = 0x2000000
	// Bit TCIF7.
	BDMA_ISR_TCIF7 = 0x2000000
	// No transfer complete event on channel x
	BDMA_ISR_TCIF7_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF7_Complete = 0x1
	// Position of HTIF7 field.
	BDMA_ISR_HTIF7_Pos = 0x1a
	// Bit mask of HTIF7 field.
	BDMA_ISR_HTIF7_Msk = 0x4000000
	// Bit HTIF7.
	BDMA_ISR_HTIF7 = 0x4000000
	// No half transfer event on channel x
	BDMA_ISR_HTIF7_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF7_Half = 0x1
	// Position of TEIF7 field.
	BDMA_ISR_TEIF7_Pos = 0x1b
	// Bit mask of TEIF7 field.
	BDMA_ISR_TEIF7_Msk = 0x8000000
	// Bit TEIF7.
	BDMA_ISR_TEIF7 = 0x8000000
	// No transfer error on channel x
	BDMA_ISR_TEIF7_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF7_Error = 0x1
	// Position of GIF8 field.
	BDMA_ISR_GIF8_Pos = 0x1c
	// Bit mask of GIF8 field.
	BDMA_ISR_GIF8_Msk = 0x10000000
	// Bit GIF8.
	BDMA_ISR_GIF8 = 0x10000000
	// No TE, HT or TC event on channel x
	BDMA_ISR_GIF8_NoEvent = 0x0
	// A TE, HT or TC event occurred on channel x
	BDMA_ISR_GIF8_Event = 0x1
	// Position of TCIF8 field.
	BDMA_ISR_TCIF8_Pos = 0x1d
	// Bit mask of TCIF8 field.
	BDMA_ISR_TCIF8_Msk = 0x20000000
	// Bit TCIF8.
	BDMA_ISR_TCIF8 = 0x20000000
	// No transfer complete event on channel x
	BDMA_ISR_TCIF8_NotComplete = 0x0
	// A transfer complete event occurred on channel x
	BDMA_ISR_TCIF8_Complete = 0x1
	// Position of HTIF8 field.
	BDMA_ISR_HTIF8_Pos = 0x1e
	// Bit mask of HTIF8 field.
	BDMA_ISR_HTIF8_Msk = 0x40000000
	// Bit HTIF8.
	BDMA_ISR_HTIF8 = 0x40000000
	// No half transfer event on channel x
	BDMA_ISR_HTIF8_NotHalf = 0x0
	// A half transfer event occurred on channel x
	BDMA_ISR_HTIF8_Half = 0x1
	// Position of TEIF8 field.
	BDMA_ISR_TEIF8_Pos = 0x1f
	// Bit mask of TEIF8 field.
	BDMA_ISR_TEIF8_Msk = 0x80000000
	// Bit TEIF8.
	BDMA_ISR_TEIF8 = 0x80000000
	// No transfer error on channel x
	BDMA_ISR_TEIF8_NoError = 0x0
	// A transfer error occurred on channel x
	BDMA_ISR_TEIF8_Error = 0x1

	// IFCR: DMA interrupt flag clear register
	// Position of CGIF1 field.
	BDMA_IFCR_CGIF1_Pos = 0x0
	// Bit mask of CGIF1 field.
	BDMA_IFCR_CGIF1_Msk = 0x1
	// Bit CGIF1.
	BDMA_IFCR_CGIF1 = 0x1
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF1_Clear = 0x1
	// Position of CTCIF1 field.
	BDMA_IFCR_CTCIF1_Pos = 0x1
	// Bit mask of CTCIF1 field.
	BDMA_IFCR_CTCIF1_Msk = 0x2
	// Bit CTCIF1.
	BDMA_IFCR_CTCIF1 = 0x2
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF1_Clear = 0x1
	// Position of CHTIF1 field.
	BDMA_IFCR_CHTIF1_Pos = 0x2
	// Bit mask of CHTIF1 field.
	BDMA_IFCR_CHTIF1_Msk = 0x4
	// Bit CHTIF1.
	BDMA_IFCR_CHTIF1 = 0x4
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF1_Clear = 0x1
	// Position of CTEIF1 field.
	BDMA_IFCR_CTEIF1_Pos = 0x3
	// Bit mask of CTEIF1 field.
	BDMA_IFCR_CTEIF1_Msk = 0x8
	// Bit CTEIF1.
	BDMA_IFCR_CTEIF1 = 0x8
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF1_Clear = 0x1
	// Position of CGIF2 field.
	BDMA_IFCR_CGIF2_Pos = 0x4
	// Bit mask of CGIF2 field.
	BDMA_IFCR_CGIF2_Msk = 0x10
	// Bit CGIF2.
	BDMA_IFCR_CGIF2 = 0x10
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF2_Clear = 0x1
	// Position of CTCIF2 field.
	BDMA_IFCR_CTCIF2_Pos = 0x5
	// Bit mask of CTCIF2 field.
	BDMA_IFCR_CTCIF2_Msk = 0x20
	// Bit CTCIF2.
	BDMA_IFCR_CTCIF2 = 0x20
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF2_Clear = 0x1
	// Position of CHTIF2 field.
	BDMA_IFCR_CHTIF2_Pos = 0x6
	// Bit mask of CHTIF2 field.
	BDMA_IFCR_CHTIF2_Msk = 0x40
	// Bit CHTIF2.
	BDMA_IFCR_CHTIF2 = 0x40
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF2_Clear = 0x1
	// Position of CTEIF2 field.
	BDMA_IFCR_CTEIF2_Pos = 0x7
	// Bit mask of CTEIF2 field.
	BDMA_IFCR_CTEIF2_Msk = 0x80
	// Bit CTEIF2.
	BDMA_IFCR_CTEIF2 = 0x80
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF2_Clear = 0x1
	// Position of CGIF3 field.
	BDMA_IFCR_CGIF3_Pos = 0x8
	// Bit mask of CGIF3 field.
	BDMA_IFCR_CGIF3_Msk = 0x100
	// Bit CGIF3.
	BDMA_IFCR_CGIF3 = 0x100
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF3_Clear = 0x1
	// Position of CTCIF3 field.
	BDMA_IFCR_CTCIF3_Pos = 0x9
	// Bit mask of CTCIF3 field.
	BDMA_IFCR_CTCIF3_Msk = 0x200
	// Bit CTCIF3.
	BDMA_IFCR_CTCIF3 = 0x200
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF3_Clear = 0x1
	// Position of CHTIF3 field.
	BDMA_IFCR_CHTIF3_Pos = 0xa
	// Bit mask of CHTIF3 field.
	BDMA_IFCR_CHTIF3_Msk = 0x400
	// Bit CHTIF3.
	BDMA_IFCR_CHTIF3 = 0x400
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF3_Clear = 0x1
	// Position of CTEIF3 field.
	BDMA_IFCR_CTEIF3_Pos = 0xb
	// Bit mask of CTEIF3 field.
	BDMA_IFCR_CTEIF3_Msk = 0x800
	// Bit CTEIF3.
	BDMA_IFCR_CTEIF3 = 0x800
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF3_Clear = 0x1
	// Position of CGIF4 field.
	BDMA_IFCR_CGIF4_Pos = 0xc
	// Bit mask of CGIF4 field.
	BDMA_IFCR_CGIF4_Msk = 0x1000
	// Bit CGIF4.
	BDMA_IFCR_CGIF4 = 0x1000
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF4_Clear = 0x1
	// Position of CTCIF4 field.
	BDMA_IFCR_CTCIF4_Pos = 0xd
	// Bit mask of CTCIF4 field.
	BDMA_IFCR_CTCIF4_Msk = 0x2000
	// Bit CTCIF4.
	BDMA_IFCR_CTCIF4 = 0x2000
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF4_Clear = 0x1
	// Position of CHTIF4 field.
	BDMA_IFCR_CHTIF4_Pos = 0xe
	// Bit mask of CHTIF4 field.
	BDMA_IFCR_CHTIF4_Msk = 0x4000
	// Bit CHTIF4.
	BDMA_IFCR_CHTIF4 = 0x4000
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF4_Clear = 0x1
	// Position of CTEIF4 field.
	BDMA_IFCR_CTEIF4_Pos = 0xf
	// Bit mask of CTEIF4 field.
	BDMA_IFCR_CTEIF4_Msk = 0x8000
	// Bit CTEIF4.
	BDMA_IFCR_CTEIF4 = 0x8000
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF4_Clear = 0x1
	// Position of CGIF5 field.
	BDMA_IFCR_CGIF5_Pos = 0x10
	// Bit mask of CGIF5 field.
	BDMA_IFCR_CGIF5_Msk = 0x10000
	// Bit CGIF5.
	BDMA_IFCR_CGIF5 = 0x10000
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF5_Clear = 0x1
	// Position of CTCIF5 field.
	BDMA_IFCR_CTCIF5_Pos = 0x11
	// Bit mask of CTCIF5 field.
	BDMA_IFCR_CTCIF5_Msk = 0x20000
	// Bit CTCIF5.
	BDMA_IFCR_CTCIF5 = 0x20000
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF5_Clear = 0x1
	// Position of CHTIF5 field.
	BDMA_IFCR_CHTIF5_Pos = 0x12
	// Bit mask of CHTIF5 field.
	BDMA_IFCR_CHTIF5_Msk = 0x40000
	// Bit CHTIF5.
	BDMA_IFCR_CHTIF5 = 0x40000
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF5_Clear = 0x1
	// Position of CTEIF5 field.
	BDMA_IFCR_CTEIF5_Pos = 0x13
	// Bit mask of CTEIF5 field.
	BDMA_IFCR_CTEIF5_Msk = 0x80000
	// Bit CTEIF5.
	BDMA_IFCR_CTEIF5 = 0x80000
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF5_Clear = 0x1
	// Position of CGIF6 field.
	BDMA_IFCR_CGIF6_Pos = 0x14
	// Bit mask of CGIF6 field.
	BDMA_IFCR_CGIF6_Msk = 0x100000
	// Bit CGIF6.
	BDMA_IFCR_CGIF6 = 0x100000
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF6_Clear = 0x1
	// Position of CTCIF6 field.
	BDMA_IFCR_CTCIF6_Pos = 0x15
	// Bit mask of CTCIF6 field.
	BDMA_IFCR_CTCIF6_Msk = 0x200000
	// Bit CTCIF6.
	BDMA_IFCR_CTCIF6 = 0x200000
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF6_Clear = 0x1
	// Position of CHTIF6 field.
	BDMA_IFCR_CHTIF6_Pos = 0x16
	// Bit mask of CHTIF6 field.
	BDMA_IFCR_CHTIF6_Msk = 0x400000
	// Bit CHTIF6.
	BDMA_IFCR_CHTIF6 = 0x400000
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF6_Clear = 0x1
	// Position of CTEIF6 field.
	BDMA_IFCR_CTEIF6_Pos = 0x17
	// Bit mask of CTEIF6 field.
	BDMA_IFCR_CTEIF6_Msk = 0x800000
	// Bit CTEIF6.
	BDMA_IFCR_CTEIF6 = 0x800000
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF6_Clear = 0x1
	// Position of CGIF7 field.
	BDMA_IFCR_CGIF7_Pos = 0x18
	// Bit mask of CGIF7 field.
	BDMA_IFCR_CGIF7_Msk = 0x1000000
	// Bit CGIF7.
	BDMA_IFCR_CGIF7 = 0x1000000
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF7_Clear = 0x1
	// Position of CTCIF7 field.
	BDMA_IFCR_CTCIF7_Pos = 0x19
	// Bit mask of CTCIF7 field.
	BDMA_IFCR_CTCIF7_Msk = 0x2000000
	// Bit CTCIF7.
	BDMA_IFCR_CTCIF7 = 0x2000000
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF7_Clear = 0x1
	// Position of CHTIF7 field.
	BDMA_IFCR_CHTIF7_Pos = 0x1a
	// Bit mask of CHTIF7 field.
	BDMA_IFCR_CHTIF7_Msk = 0x4000000
	// Bit CHTIF7.
	BDMA_IFCR_CHTIF7 = 0x4000000
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF7_Clear = 0x1
	// Position of CTEIF7 field.
	BDMA_IFCR_CTEIF7_Pos = 0x1b
	// Bit mask of CTEIF7 field.
	BDMA_IFCR_CTEIF7_Msk = 0x8000000
	// Bit CTEIF7.
	BDMA_IFCR_CTEIF7 = 0x8000000
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF7_Clear = 0x1
	// Position of CGIF8 field.
	BDMA_IFCR_CGIF8_Pos = 0x1c
	// Bit mask of CGIF8 field.
	BDMA_IFCR_CGIF8_Msk = 0x10000000
	// Bit CGIF8.
	BDMA_IFCR_CGIF8 = 0x10000000
	// Clear the corresponding CGIFx flag
	BDMA_IFCR_CGIF8_Clear = 0x1
	// Position of CTCIF8 field.
	BDMA_IFCR_CTCIF8_Pos = 0x1d
	// Bit mask of CTCIF8 field.
	BDMA_IFCR_CTCIF8_Msk = 0x20000000
	// Bit CTCIF8.
	BDMA_IFCR_CTCIF8 = 0x20000000
	// Clear the corresponding TCIFx flag
	BDMA_IFCR_CTCIF8_Clear = 0x1
	// Position of CHTIF8 field.
	BDMA_IFCR_CHTIF8_Pos = 0x1e
	// Bit mask of CHTIF8 field.
	BDMA_IFCR_CHTIF8_Msk = 0x40000000
	// Bit CHTIF8.
	BDMA_IFCR_CHTIF8 = 0x40000000
	// Clear the corresponding HTIFx flag
	BDMA_IFCR_CHTIF8_Clear = 0x1
	// Position of CTEIF8 field.
	BDMA_IFCR_CTEIF8_Pos = 0x1f
	// Bit mask of CTEIF8 field.
	BDMA_IFCR_CTEIF8_Msk = 0x80000000
	// Bit CTEIF8.
	BDMA_IFCR_CTEIF8 = 0x80000000
	// Clear the corresponding TEIFx flag
	BDMA_IFCR_CTEIF8_Clear = 0x1

	// CH.CR: DMA channel x configuration register
	// Position of EN field.
	BDMA_CH_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	BDMA_CH_CR_EN_Msk = 0x1
	// Bit EN.
	BDMA_CH_CR_EN = 0x1
	// Channel disabled
	BDMA_CH_CR_EN_Disabled = 0x0
	// Channel enabled
	BDMA_CH_CR_EN_Enabled = 0x1
	// Position of TCIE field.
	BDMA_CH_CR_TCIE_Pos = 0x1
	// Bit mask of TCIE field.
	BDMA_CH_CR_TCIE_Msk = 0x2
	// Bit TCIE.
	BDMA_CH_CR_TCIE = 0x2
	// TC interrupt disabled
	BDMA_CH_CR_TCIE_Disabled = 0x0
	// TC interrupt enabled
	BDMA_CH_CR_TCIE_Enabled = 0x1
	// Position of HTIE field.
	BDMA_CH_CR_HTIE_Pos = 0x2
	// Bit mask of HTIE field.
	BDMA_CH_CR_HTIE_Msk = 0x4
	// Bit HTIE.
	BDMA_CH_CR_HTIE = 0x4
	// HT interrupt disabled
	BDMA_CH_CR_HTIE_Disabled = 0x0
	// HT interrupt enabled
	BDMA_CH_CR_HTIE_Enabled = 0x1
	// Position of TEIE field.
	BDMA_CH_CR_TEIE_Pos = 0x3
	// Bit mask of TEIE field.
	BDMA_CH_CR_TEIE_Msk = 0x8
	// Bit TEIE.
	BDMA_CH_CR_TEIE = 0x8
	// TE interrupt disabled
	BDMA_CH_CR_TEIE_Disabled = 0x0
	// TE interrupt enabled
	BDMA_CH_CR_TEIE_Enabled = 0x1
	// Position of DIR field.
	BDMA_CH_CR_DIR_Pos = 0x4
	// Bit mask of DIR field.
	BDMA_CH_CR_DIR_Msk = 0x10
	// Bit DIR.
	BDMA_CH_CR_DIR = 0x10
	// Peripheral-to-memory
	BDMA_CH_CR_DIR_PeripheralToMemory = 0x0
	// Memory-to-peripheral
	BDMA_CH_CR_DIR_MemoryToPeripheral = 0x1
	// Position of CIRC field.
	BDMA_CH_CR_CIRC_Pos = 0x5
	// Bit mask of CIRC field.
	BDMA_CH_CR_CIRC_Msk = 0x20
	// Bit CIRC.
	BDMA_CH_CR_CIRC = 0x20
	// Circular mode disabled
	BDMA_CH_CR_CIRC_Disabled = 0x0
	// Circular mode enabled
	BDMA_CH_CR_CIRC_Enabled = 0x1
	// Position of PINC field.
	BDMA_CH_CR_PINC_Pos = 0x6
	// Bit mask of PINC field.
	BDMA_CH_CR_PINC_Msk = 0x40
	// Bit PINC.
	BDMA_CH_CR_PINC = 0x40
	// Address pointer is fixed
	BDMA_CH_CR_PINC_Fixed = 0x0
	// Address pointer is incremented after each data transfer
	BDMA_CH_CR_PINC_Incremented = 0x1
	// Position of MINC field.
	BDMA_CH_CR_MINC_Pos = 0x7
	// Bit mask of MINC field.
	BDMA_CH_CR_MINC_Msk = 0x80
	// Bit MINC.
	BDMA_CH_CR_MINC = 0x80
	// Address pointer is fixed
	BDMA_CH_CR_MINC_Fixed = 0x0
	// Address pointer is incremented after each data transfer
	BDMA_CH_CR_MINC_Incremented = 0x1
	// Position of PSIZE field.
	BDMA_CH_CR_PSIZE_Pos = 0x8
	// Bit mask of PSIZE field.
	BDMA_CH_CR_PSIZE_Msk = 0x300
	// Byte (8-bit)
	BDMA_CH_CR_PSIZE_Bits8 = 0x0
	// Half-word (16-bit)
	BDMA_CH_CR_PSIZE_Bits16 = 0x1
	// Word (32-bit)
	BDMA_CH_CR_PSIZE_Bits32 = 0x2
	// Position of MSIZE field.
	BDMA_CH_CR_MSIZE_Pos = 0xa
	// Bit mask of MSIZE field.
	BDMA_CH_CR_MSIZE_Msk = 0xc00
	// Byte (8-bit)
	BDMA_CH_CR_MSIZE_Bits8 = 0x0
	// Half-word (16-bit)
	BDMA_CH_CR_MSIZE_Bits16 = 0x1
	// Word (32-bit)
	BDMA_CH_CR_MSIZE_Bits32 = 0x2
	// Position of PL field.
	BDMA_CH_CR_PL_Pos = 0xc
	// Bit mask of PL field.
	BDMA_CH_CR_PL_Msk = 0x3000
	// Low
	BDMA_CH_CR_PL_Low = 0x0
	// Medium
	BDMA_CH_CR_PL_Medium = 0x1
	// High
	BDMA_CH_CR_PL_High = 0x2
	// Very high
	BDMA_CH_CR_PL_VeryHigh = 0x3
	// Position of MEM2MEM field.
	BDMA_CH_CR_MEM2MEM_Pos = 0xe
	// Bit mask of MEM2MEM field.
	BDMA_CH_CR_MEM2MEM_Msk = 0x4000
	// Bit MEM2MEM.
	BDMA_CH_CR_MEM2MEM = 0x4000
	// Memory-to-memory mode disabled
	BDMA_CH_CR_MEM2MEM_Disabled = 0x0
	// Memory-to-memory mode enabled
	BDMA_CH_CR_MEM2MEM_Enabled = 0x1
	// Position of CT field.
	BDMA_CH_CR_CT_Pos = 0x10
	// Bit mask of CT field.
	BDMA_CH_CR_CT_Msk = 0x10000
	// Bit CT.
	BDMA_CH_CR_CT = 0x10000
	// The current target memory is Memory 0
	BDMA_CH_CR_CT_Memory0 = 0x0
	// The current target memory is Memory 1
	BDMA_CH_CR_CT_Memory1 = 0x1
	// Position of DBM field.
	BDMA_CH_CR_DBM_Pos = 0xf
	// Bit mask of DBM field.
	BDMA_CH_CR_DBM_Msk = 0x8000
	// Bit DBM.
	BDMA_CH_CR_DBM = 0x8000
	// No buffer switching at the end of transfer
	BDMA_CH_CR_DBM_Disabled = 0x0
	// Memory target switched at the end of the DMA transfer
	BDMA_CH_CR_DBM_Enabled = 0x1

	// CH.NDTR: DMA channel x number of data register
	// Position of NDT field.
	BDMA_CH_NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	BDMA_CH_NDTR_NDT_Msk = 0xffff

	// CH.PAR: This register must not be written when the channel is enabled.
	// Position of PA field.
	BDMA_CH_PAR_PA_Pos = 0x0
	// Bit mask of PA field.
	BDMA_CH_PAR_PA_Msk = 0xffffffff

	// CH.M0AR: This register must not be written when the channel is enabled.
	// Position of MA field.
	BDMA_CH_M0AR_MA_Pos = 0x0
	// Bit mask of MA field.
	BDMA_CH_M0AR_MA_Msk = 0xffffffff

	// CH.M1AR: Channel x memory 1 address register
	// Position of MA field.
	BDMA_CH_M1AR_MA_Pos = 0x0
	// Bit mask of MA field.
	BDMA_CH_M1AR_MA_Msk = 0xffffffff
)

// Bitfields for DMA2D: DMA2D
const (
	// CR: DMA2D control register
	// Position of START field.
	DMA2D_CR_START_Pos = 0x0
	// Bit mask of START field.
	DMA2D_CR_START_Msk = 0x1
	// Bit START.
	DMA2D_CR_START = 0x1
	// Launch the DMA2D
	DMA2D_CR_START_Start = 0x1
	// Position of SUSP field.
	DMA2D_CR_SUSP_Pos = 0x1
	// Bit mask of SUSP field.
	DMA2D_CR_SUSP_Msk = 0x2
	// Bit SUSP.
	DMA2D_CR_SUSP = 0x2
	// Transfer not suspended
	DMA2D_CR_SUSP_NotSuspended = 0x0
	// Transfer suspended
	DMA2D_CR_SUSP_Suspended = 0x1
	// Position of ABORT field.
	DMA2D_CR_ABORT_Pos = 0x2
	// Bit mask of ABORT field.
	DMA2D_CR_ABORT_Msk = 0x4
	// Bit ABORT.
	DMA2D_CR_ABORT = 0x4
	// Transfer abort requested
	DMA2D_CR_ABORT_AbortRequest = 0x1
	// Position of TEIE field.
	DMA2D_CR_TEIE_Pos = 0x8
	// Bit mask of TEIE field.
	DMA2D_CR_TEIE_Msk = 0x100
	// Bit TEIE.
	DMA2D_CR_TEIE = 0x100
	// TE interrupt disabled
	DMA2D_CR_TEIE_Disabled = 0x0
	// TE interrupt enabled
	DMA2D_CR_TEIE_Enabled = 0x1
	// Position of TCIE field.
	DMA2D_CR_TCIE_Pos = 0x9
	// Bit mask of TCIE field.
	DMA2D_CR_TCIE_Msk = 0x200
	// Bit TCIE.
	DMA2D_CR_TCIE = 0x200
	// TC interrupt disabled
	DMA2D_CR_TCIE_Disabled = 0x0
	// TC interrupt enabled
	DMA2D_CR_TCIE_Enabled = 0x1
	// Position of TWIE field.
	DMA2D_CR_TWIE_Pos = 0xa
	// Bit mask of TWIE field.
	DMA2D_CR_TWIE_Msk = 0x400
	// Bit TWIE.
	DMA2D_CR_TWIE = 0x400
	// TW interrupt disabled
	DMA2D_CR_TWIE_Disabled = 0x0
	// TW interrupt enabled
	DMA2D_CR_TWIE_Enabled = 0x1
	// Position of CAEIE field.
	DMA2D_CR_CAEIE_Pos = 0xb
	// Bit mask of CAEIE field.
	DMA2D_CR_CAEIE_Msk = 0x800
	// Bit CAEIE.
	DMA2D_CR_CAEIE = 0x800
	// CAE interrupt disabled
	DMA2D_CR_CAEIE_Disabled = 0x0
	// CAE interrupt enabled
	DMA2D_CR_CAEIE_Enabled = 0x1
	// Position of CTCIE field.
	DMA2D_CR_CTCIE_Pos = 0xc
	// Bit mask of CTCIE field.
	DMA2D_CR_CTCIE_Msk = 0x1000
	// Bit CTCIE.
	DMA2D_CR_CTCIE = 0x1000
	// CTC interrupt disabled
	DMA2D_CR_CTCIE_Disabled = 0x0
	// CTC interrupt enabled
	DMA2D_CR_CTCIE_Enabled = 0x1
	// Position of CEIE field.
	DMA2D_CR_CEIE_Pos = 0xd
	// Bit mask of CEIE field.
	DMA2D_CR_CEIE_Msk = 0x2000
	// Bit CEIE.
	DMA2D_CR_CEIE = 0x2000
	// CE interrupt disabled
	DMA2D_CR_CEIE_Disabled = 0x0
	// CE interrupt enabled
	DMA2D_CR_CEIE_Enabled = 0x1
	// Position of MODE field.
	DMA2D_CR_MODE_Pos = 0x10
	// Bit mask of MODE field.
	DMA2D_CR_MODE_Msk = 0x30000
	// Memory-to-memory (FG fetch only)
	DMA2D_CR_MODE_MemoryToMemory = 0x0
	// Memory-to-memory with PFC (FG fetch only with FG PFC active)
	DMA2D_CR_MODE_MemoryToMemoryPFC = 0x1
	// Memory-to-memory with blending (FG and BG fetch with PFC and blending)
	DMA2D_CR_MODE_MemoryToMemoryPFCBlending = 0x2
	// Register-to-memory
	DMA2D_CR_MODE_RegisterToMemory = 0x3

	// ISR: DMA2D Interrupt Status Register
	// Position of TEIF field.
	DMA2D_ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	DMA2D_ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	DMA2D_ISR_TEIF = 0x1
	// Position of TCIF field.
	DMA2D_ISR_TCIF_Pos = 0x1
	// Bit mask of TCIF field.
	DMA2D_ISR_TCIF_Msk = 0x2
	// Bit TCIF.
	DMA2D_ISR_TCIF = 0x2
	// Position of TWIF field.
	DMA2D_ISR_TWIF_Pos = 0x2
	// Bit mask of TWIF field.
	DMA2D_ISR_TWIF_Msk = 0x4
	// Bit TWIF.
	DMA2D_ISR_TWIF = 0x4
	// Position of CAEIF field.
	DMA2D_ISR_CAEIF_Pos = 0x3
	// Bit mask of CAEIF field.
	DMA2D_ISR_CAEIF_Msk = 0x8
	// Bit CAEIF.
	DMA2D_ISR_CAEIF = 0x8
	// Position of CTCIF field.
	DMA2D_ISR_CTCIF_Pos = 0x4
	// Bit mask of CTCIF field.
	DMA2D_ISR_CTCIF_Msk = 0x10
	// Bit CTCIF.
	DMA2D_ISR_CTCIF = 0x10
	// Position of CEIF field.
	DMA2D_ISR_CEIF_Pos = 0x5
	// Bit mask of CEIF field.
	DMA2D_ISR_CEIF_Msk = 0x20
	// Bit CEIF.
	DMA2D_ISR_CEIF = 0x20

	// IFCR: DMA2D interrupt flag clear register
	// Position of CTEIF field.
	DMA2D_IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	DMA2D_IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	DMA2D_IFCR_CTEIF = 0x1
	// Clear the TEIF flag in the ISR register
	DMA2D_IFCR_CTEIF_Clear = 0x1
	// Position of CTCIF field.
	DMA2D_IFCR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	DMA2D_IFCR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	DMA2D_IFCR_CTCIF = 0x2
	// Clear the TCIF flag in the ISR register
	DMA2D_IFCR_CTCIF_Clear = 0x1
	// Position of CTWIF field.
	DMA2D_IFCR_CTWIF_Pos = 0x2
	// Bit mask of CTWIF field.
	DMA2D_IFCR_CTWIF_Msk = 0x4
	// Bit CTWIF.
	DMA2D_IFCR_CTWIF = 0x4
	// Clear the TWIF flag in the ISR register
	DMA2D_IFCR_CTWIF_Clear = 0x1
	// Position of CAECIF field.
	DMA2D_IFCR_CAECIF_Pos = 0x3
	// Bit mask of CAECIF field.
	DMA2D_IFCR_CAECIF_Msk = 0x8
	// Bit CAECIF.
	DMA2D_IFCR_CAECIF = 0x8
	// Clear the CAEIF flag in the ISR register
	DMA2D_IFCR_CAECIF_Clear = 0x1
	// Position of CCTCIF field.
	DMA2D_IFCR_CCTCIF_Pos = 0x4
	// Bit mask of CCTCIF field.
	DMA2D_IFCR_CCTCIF_Msk = 0x10
	// Bit CCTCIF.
	DMA2D_IFCR_CCTCIF = 0x10
	// Clear the CTCIF flag in the ISR register
	DMA2D_IFCR_CCTCIF_Clear = 0x1
	// Position of CCEIF field.
	DMA2D_IFCR_CCEIF_Pos = 0x5
	// Bit mask of CCEIF field.
	DMA2D_IFCR_CCEIF_Msk = 0x20
	// Bit CCEIF.
	DMA2D_IFCR_CCEIF = 0x20
	// Clear the CEIF flag in the ISR register
	DMA2D_IFCR_CCEIF_Clear = 0x1

	// FGMAR: DMA2D foreground memory address register
	// Position of MA field.
	DMA2D_FGMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_FGMAR_MA_Msk = 0xffffffff

	// FGOR: DMA2D foreground offset register
	// Position of LO field.
	DMA2D_FGOR_LO_Pos = 0x0
	// Bit mask of LO field.
	DMA2D_FGOR_LO_Msk = 0xffff

	// BGMAR: DMA2D background memory address register
	// Position of MA field.
	DMA2D_BGMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_BGMAR_MA_Msk = 0xffffffff

	// BGOR: DMA2D background offset register
	// Position of LO field.
	DMA2D_BGOR_LO_Pos = 0x0
	// Bit mask of LO field.
	DMA2D_BGOR_LO_Msk = 0xffff

	// FGPFCCR: DMA2D foreground PFC control register
	// Position of CM field.
	DMA2D_FGPFCCR_CM_Pos = 0x0
	// Bit mask of CM field.
	DMA2D_FGPFCCR_CM_Msk = 0xf
	// Color mode ARGB8888
	DMA2D_FGPFCCR_CM_ARGB8888 = 0x0
	// Color mode RGB888
	DMA2D_FGPFCCR_CM_RGB888 = 0x1
	// Color mode RGB565
	DMA2D_FGPFCCR_CM_RGB565 = 0x2
	// Color mode ARGB1555
	DMA2D_FGPFCCR_CM_ARGB1555 = 0x3
	// Color mode ARGB4444
	DMA2D_FGPFCCR_CM_ARGB4444 = 0x4
	// Color mode L8
	DMA2D_FGPFCCR_CM_L8 = 0x5
	// Color mode AL44
	DMA2D_FGPFCCR_CM_AL44 = 0x6
	// Color mode AL88
	DMA2D_FGPFCCR_CM_AL88 = 0x7
	// Color mode L4
	DMA2D_FGPFCCR_CM_L4 = 0x8
	// Color mode A8
	DMA2D_FGPFCCR_CM_A8 = 0x9
	// Color mode A4
	DMA2D_FGPFCCR_CM_A4 = 0xa
	// Color mode YCbCr
	DMA2D_FGPFCCR_CM_YCbCr = 0xb
	// Position of CCM field.
	DMA2D_FGPFCCR_CCM_Pos = 0x4
	// Bit mask of CCM field.
	DMA2D_FGPFCCR_CCM_Msk = 0x10
	// Bit CCM.
	DMA2D_FGPFCCR_CCM = 0x10
	// CLUT color format ARGB8888
	DMA2D_FGPFCCR_CCM_ARGB8888 = 0x0
	// CLUT color format RGB888
	DMA2D_FGPFCCR_CCM_RGB888 = 0x1
	// Position of START field.
	DMA2D_FGPFCCR_START_Pos = 0x5
	// Bit mask of START field.
	DMA2D_FGPFCCR_START_Msk = 0x20
	// Bit START.
	DMA2D_FGPFCCR_START = 0x20
	// Start the automatic loading of the CLUT
	DMA2D_FGPFCCR_START_Start = 0x1
	// Position of CS field.
	DMA2D_FGPFCCR_CS_Pos = 0x8
	// Bit mask of CS field.
	DMA2D_FGPFCCR_CS_Msk = 0xff00
	// Position of AM field.
	DMA2D_FGPFCCR_AM_Pos = 0x10
	// Bit mask of AM field.
	DMA2D_FGPFCCR_AM_Msk = 0x30000
	// No modification of alpha channel
	DMA2D_FGPFCCR_AM_NoModify = 0x0
	// Replace with value in ALPHA[7:0]
	DMA2D_FGPFCCR_AM_Replace = 0x1
	// Multiply with value in ALPHA[7:0]
	DMA2D_FGPFCCR_AM_Multiply = 0x2
	// Position of CSS field.
	DMA2D_FGPFCCR_CSS_Pos = 0x12
	// Bit mask of CSS field.
	DMA2D_FGPFCCR_CSS_Msk = 0xc0000
	// Position of AI field.
	DMA2D_FGPFCCR_AI_Pos = 0x14
	// Bit mask of AI field.
	DMA2D_FGPFCCR_AI_Msk = 0x100000
	// Bit AI.
	DMA2D_FGPFCCR_AI = 0x100000
	// Regular alpha
	DMA2D_FGPFCCR_AI_RegularAlpha = 0x0
	// Inverted alpha
	DMA2D_FGPFCCR_AI_InvertedAlpha = 0x1
	// Position of RBS field.
	DMA2D_FGPFCCR_RBS_Pos = 0x15
	// Bit mask of RBS field.
	DMA2D_FGPFCCR_RBS_Msk = 0x200000
	// Bit RBS.
	DMA2D_FGPFCCR_RBS = 0x200000
	// No Red Blue Swap (RGB or ARGB)
	DMA2D_FGPFCCR_RBS_Regular = 0x0
	// Red Blue Swap (BGR or ABGR)
	DMA2D_FGPFCCR_RBS_Swap = 0x1
	// Position of ALPHA field.
	DMA2D_FGPFCCR_ALPHA_Pos = 0x18
	// Bit mask of ALPHA field.
	DMA2D_FGPFCCR_ALPHA_Msk = 0xff000000

	// FGCOLR: DMA2D foreground color register
	// Position of BLUE field.
	DMA2D_FGCOLR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_FGCOLR_BLUE_Msk = 0xff
	// Position of GREEN field.
	DMA2D_FGCOLR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_FGCOLR_GREEN_Msk = 0xff00
	// Position of RED field.
	DMA2D_FGCOLR_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_FGCOLR_RED_Msk = 0xff0000

	// BGPFCCR: DMA2D background PFC control register
	// Position of CM field.
	DMA2D_BGPFCCR_CM_Pos = 0x0
	// Bit mask of CM field.
	DMA2D_BGPFCCR_CM_Msk = 0xf
	// Color mode ARGB8888
	DMA2D_BGPFCCR_CM_ARGB8888 = 0x0
	// Color mode RGB888
	DMA2D_BGPFCCR_CM_RGB888 = 0x1
	// Color mode RGB565
	DMA2D_BGPFCCR_CM_RGB565 = 0x2
	// Color mode ARGB1555
	DMA2D_BGPFCCR_CM_ARGB1555 = 0x3
	// Color mode ARGB4444
	DMA2D_BGPFCCR_CM_ARGB4444 = 0x4
	// Color mode L8
	DMA2D_BGPFCCR_CM_L8 = 0x5
	// Color mode AL44
	DMA2D_BGPFCCR_CM_AL44 = 0x6
	// Color mode AL88
	DMA2D_BGPFCCR_CM_AL88 = 0x7
	// Color mode L4
	DMA2D_BGPFCCR_CM_L4 = 0x8
	// Color mode A8
	DMA2D_BGPFCCR_CM_A8 = 0x9
	// Color mode A4
	DMA2D_BGPFCCR_CM_A4 = 0xa
	// Position of CCM field.
	DMA2D_BGPFCCR_CCM_Pos = 0x4
	// Bit mask of CCM field.
	DMA2D_BGPFCCR_CCM_Msk = 0x10
	// Bit CCM.
	DMA2D_BGPFCCR_CCM = 0x10
	// CLUT color format ARGB8888
	DMA2D_BGPFCCR_CCM_ARGB8888 = 0x0
	// CLUT color format RGB888
	DMA2D_BGPFCCR_CCM_RGB888 = 0x1
	// Position of START field.
	DMA2D_BGPFCCR_START_Pos = 0x5
	// Bit mask of START field.
	DMA2D_BGPFCCR_START_Msk = 0x20
	// Bit START.
	DMA2D_BGPFCCR_START = 0x20
	// Start the automatic loading of the CLUT
	DMA2D_BGPFCCR_START_Start = 0x1
	// Position of CS field.
	DMA2D_BGPFCCR_CS_Pos = 0x8
	// Bit mask of CS field.
	DMA2D_BGPFCCR_CS_Msk = 0xff00
	// Position of AM field.
	DMA2D_BGPFCCR_AM_Pos = 0x10
	// Bit mask of AM field.
	DMA2D_BGPFCCR_AM_Msk = 0x30000
	// No modification of alpha channel
	DMA2D_BGPFCCR_AM_NoModify = 0x0
	// Replace with value in ALPHA[7:0]
	DMA2D_BGPFCCR_AM_Replace = 0x1
	// Multiply with value in ALPHA[7:0]
	DMA2D_BGPFCCR_AM_Multiply = 0x2
	// Position of AI field.
	DMA2D_BGPFCCR_AI_Pos = 0x14
	// Bit mask of AI field.
	DMA2D_BGPFCCR_AI_Msk = 0x100000
	// Bit AI.
	DMA2D_BGPFCCR_AI = 0x100000
	// Regular alpha
	DMA2D_BGPFCCR_AI_RegularAlpha = 0x0
	// Inverted alpha
	DMA2D_BGPFCCR_AI_InvertedAlpha = 0x1
	// Position of RBS field.
	DMA2D_BGPFCCR_RBS_Pos = 0x15
	// Bit mask of RBS field.
	DMA2D_BGPFCCR_RBS_Msk = 0x200000
	// Bit RBS.
	DMA2D_BGPFCCR_RBS = 0x200000
	// No Red Blue Swap (RGB or ARGB)
	DMA2D_BGPFCCR_RBS_Regular = 0x0
	// Red Blue Swap (BGR or ABGR)
	DMA2D_BGPFCCR_RBS_Swap = 0x1
	// Position of ALPHA field.
	DMA2D_BGPFCCR_ALPHA_Pos = 0x18
	// Bit mask of ALPHA field.
	DMA2D_BGPFCCR_ALPHA_Msk = 0xff000000

	// BGCOLR: DMA2D background color register
	// Position of BLUE field.
	DMA2D_BGCOLR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_BGCOLR_BLUE_Msk = 0xff
	// Position of GREEN field.
	DMA2D_BGCOLR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_BGCOLR_GREEN_Msk = 0xff00
	// Position of RED field.
	DMA2D_BGCOLR_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_BGCOLR_RED_Msk = 0xff0000

	// FGCMAR: DMA2D foreground CLUT memory address register
	// Position of MA field.
	DMA2D_FGCMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_FGCMAR_MA_Msk = 0xffffffff

	// BGCMAR: DMA2D background CLUT memory address register
	// Position of MA field.
	DMA2D_BGCMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_BGCMAR_MA_Msk = 0xffffffff

	// OPFCCR: DMA2D output PFC control register
	// Position of CM field.
	DMA2D_OPFCCR_CM_Pos = 0x0
	// Bit mask of CM field.
	DMA2D_OPFCCR_CM_Msk = 0x7
	// ARGB8888
	DMA2D_OPFCCR_CM_ARGB8888 = 0x0
	// RGB888
	DMA2D_OPFCCR_CM_RGB888 = 0x1
	// RGB565
	DMA2D_OPFCCR_CM_RGB565 = 0x2
	// ARGB1555
	DMA2D_OPFCCR_CM_ARGB1555 = 0x3
	// ARGB4444
	DMA2D_OPFCCR_CM_ARGB4444 = 0x4
	// Position of AI field.
	DMA2D_OPFCCR_AI_Pos = 0x14
	// Bit mask of AI field.
	DMA2D_OPFCCR_AI_Msk = 0x100000
	// Bit AI.
	DMA2D_OPFCCR_AI = 0x100000
	// Regular alpha
	DMA2D_OPFCCR_AI_RegularAlpha = 0x0
	// Inverted alpha
	DMA2D_OPFCCR_AI_InvertedAlpha = 0x1
	// Position of RBS field.
	DMA2D_OPFCCR_RBS_Pos = 0x15
	// Bit mask of RBS field.
	DMA2D_OPFCCR_RBS_Msk = 0x200000
	// Bit RBS.
	DMA2D_OPFCCR_RBS = 0x200000
	// No Red Blue Swap (RGB or ARGB)
	DMA2D_OPFCCR_RBS_Regular = 0x0
	// Red Blue Swap (BGR or ABGR)
	DMA2D_OPFCCR_RBS_Swap = 0x1
	// Position of SB field.
	DMA2D_OPFCCR_SB_Pos = 0x8
	// Bit mask of SB field.
	DMA2D_OPFCCR_SB_Msk = 0x100
	// Bit SB.
	DMA2D_OPFCCR_SB = 0x100
	// Regular byte order
	DMA2D_OPFCCR_SB_Regular = 0x0
	// Bytes are swapped two by two
	DMA2D_OPFCCR_SB_SwapBytes = 0x1

	// OCOLR: DMA2D output color register
	// Position of BLUE field.
	DMA2D_OCOLR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_OCOLR_BLUE_Msk = 0xff
	// Position of GREEN field.
	DMA2D_OCOLR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_OCOLR_GREEN_Msk = 0xff00
	// Position of RED field.
	DMA2D_OCOLR_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_OCOLR_RED_Msk = 0xff0000
	// Position of ALPHA field.
	DMA2D_OCOLR_ALPHA_Pos = 0x18
	// Bit mask of ALPHA field.
	DMA2D_OCOLR_ALPHA_Msk = 0xff000000

	// OMAR: DMA2D output memory address register
	// Position of MA field.
	DMA2D_OMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_OMAR_MA_Msk = 0xffffffff

	// OOR: DMA2D output offset register
	// Position of LO field.
	DMA2D_OOR_LO_Pos = 0x0
	// Bit mask of LO field.
	DMA2D_OOR_LO_Msk = 0xffff

	// NLR: DMA2D number of line register
	// Position of NL field.
	DMA2D_NLR_NL_Pos = 0x0
	// Bit mask of NL field.
	DMA2D_NLR_NL_Msk = 0xffff
	// Position of PL field.
	DMA2D_NLR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA2D_NLR_PL_Msk = 0x3fff0000

	// LWR: DMA2D line watermark register
	// Position of LW field.
	DMA2D_LWR_LW_Pos = 0x0
	// Bit mask of LW field.
	DMA2D_LWR_LW_Msk = 0xffff

	// AMTCR: DMA2D AXI master timer configuration register
	// Position of EN field.
	DMA2D_AMTCR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA2D_AMTCR_EN_Msk = 0x1
	// Bit EN.
	DMA2D_AMTCR_EN = 0x1
	// Disabled AHB/AXI dead-time functionality
	DMA2D_AMTCR_EN_Disabled = 0x0
	// Enabled AHB/AXI dead-time functionality
	DMA2D_AMTCR_EN_Enabled = 0x1
	// Position of DT field.
	DMA2D_AMTCR_DT_Pos = 0x8
	// Bit mask of DT field.
	DMA2D_AMTCR_DT_Msk = 0xff00
)

// Bitfields for DMAMUX2: DMAMUX
const (
	// CCR0: DMAMux - DMA request line multiplexer channel x control register
	// Position of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Msk = 0xff
	// No signal selected as request input
	DMAMUX_CCR_DMAREQ_ID_NONE = 0x0
	// Signal `dmamux2_req_gen0` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN0 = 0x1
	// Signal `dmamux2_req_gen1` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN1 = 0x2
	// Signal `dmamux2_req_gen2` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN2 = 0x3
	// Signal `dmamux2_req_gen3` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN3 = 0x4
	// Signal `dmamux2_req_gen4` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN4 = 0x5
	// Signal `dmamux2_req_gen5` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN5 = 0x6
	// Signal `dmamux2_req_gen6` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN6 = 0x7
	// Signal `dmamux2_req_gen7` selected as request input
	DMAMUX_CCR_DMAREQ_ID_DMAMUX2_REQ_GEN7 = 0x8
	// Signal `lpuart1_rx_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_LPUART1_RX_DMA = 0x9
	// Signal `lpuart1_tx_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_LPUART1_TX_DMA = 0xa
	// Signal `spi6_rx_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_SPI6_RX_DMA = 0xb
	// Signal `spi6_tx_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_SPI6_TX_DMA = 0xc
	// Signal `i2c4_rx_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_I2C4_RX_DMA = 0xd
	// Signal `i2c4_tx_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_I2C4_TX_DMA = 0xe
	// Signal `sai4_a_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_SAI4_A_DMA = 0xf
	// Signal `sai4_b_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_SAI4_B_DMA = 0x10
	// Signal `adc3_dma` selected as request input
	DMAMUX_CCR_DMAREQ_ID_ADC3_DMA = 0x11
	// Position of SOIE field.
	DMAMUX_CCR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX_CCR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX_CCR_SOIE = 0x100
	// Synchronization overrun interrupt disabled
	DMAMUX_CCR_SOIE_Disabled = 0x0
	// Synchronization overrun interrupt enabled
	DMAMUX_CCR_SOIE_Enabled = 0x1
	// Position of EGE field.
	DMAMUX_CCR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX_CCR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX_CCR_EGE = 0x200
	// Event generation disabled
	DMAMUX_CCR_EGE_Disabled = 0x0
	// Event generation enabled
	DMAMUX_CCR_EGE_Enabled = 0x1
	// Position of SE field.
	DMAMUX_CCR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX_CCR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX_CCR_SE = 0x10000
	// Synchronization disabled
	DMAMUX_CCR_SE_Disabled = 0x0
	// Synchronization enabled
	DMAMUX_CCR_SE_Enabled = 0x1
	// Position of SPOL field.
	DMAMUX_CCR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX_CCR_SPOL_Msk = 0x60000
	// No event, i.e. no synchronization nor detection
	DMAMUX_CCR_SPOL_NoEdge = 0x0
	// Rising edge
	DMAMUX_CCR_SPOL_RisingEdge = 0x1
	// Falling edge
	DMAMUX_CCR_SPOL_FallingEdge = 0x2
	// Rising and falling edges
	DMAMUX_CCR_SPOL_BothEdges = 0x3
	// Position of NBREQ field.
	DMAMUX_CCR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX_CCR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX_CCR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX_CCR_SYNC_ID_Msk = 0x1f000000
	// Signal `dmamux2_evt0` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_DMAMUX2_EVT0 = 0x0
	// Signal `dmamux2_evt1` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_DMAMUX2_EVT1 = 0x1
	// Signal `dmamux2_evt2` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_DMAMUX2_EVT2 = 0x2
	// Signal `dmamux2_evt3` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_DMAMUX2_EVT3 = 0x3
	// Signal `dmamux2_evt4` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_DMAMUX2_EVT4 = 0x4
	// Signal `dmamux2_evt5` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_DMAMUX2_EVT5 = 0x5
	// Signal `lpuart1_rx_wkup` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_LPUART1_RX_WKUP = 0x6
	// Signal `lpuart1_tx_wkup` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_LPUART1_TX_WKUP = 0x7
	// Signal `lptim2_out` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_LPTIM2_OUT = 0x8
	// Signal `lptim3_out` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_LPTIM3_OUT = 0x9
	// Signal `i2c4_wkup` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_I2C4_WKUP = 0xa
	// Signal `spi6_wkup` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_SPI6_WKUP = 0xb
	// Signal `comp1_out` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_COMP1_OUT = 0xc
	// Signal `rtc_wkup` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_RTC_WKUP = 0xd
	// Signal `syscfg_exti0_mux` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_SYSCFG_EXTI0_MUX = 0xe
	// Signal `syscfg_exti2_mux` selected as synchronization input
	DMAMUX_CCR_SYNC_ID_SYSCFG_EXTI2_MUX = 0xf

	// CSR: DMAMUX request line multiplexer interrupt channel status register
	// Position of SOF0 field.
	DMAMUX_CSR_SOF0_Pos = 0x0
	// Bit mask of SOF0 field.
	DMAMUX_CSR_SOF0_Msk = 0x1
	// Bit SOF0.
	DMAMUX_CSR_SOF0 = 0x1
	// Position of SOF1 field.
	DMAMUX_CSR_SOF1_Pos = 0x1
	// Bit mask of SOF1 field.
	DMAMUX_CSR_SOF1_Msk = 0x2
	// Bit SOF1.
	DMAMUX_CSR_SOF1 = 0x2
	// Position of SOF2 field.
	DMAMUX_CSR_SOF2_Pos = 0x2
	// Bit mask of SOF2 field.
	DMAMUX_CSR_SOF2_Msk = 0x4
	// Bit SOF2.
	DMAMUX_CSR_SOF2 = 0x4
	// Position of SOF3 field.
	DMAMUX_CSR_SOF3_Pos = 0x3
	// Bit mask of SOF3 field.
	DMAMUX_CSR_SOF3_Msk = 0x8
	// Bit SOF3.
	DMAMUX_CSR_SOF3 = 0x8
	// Position of SOF4 field.
	DMAMUX_CSR_SOF4_Pos = 0x4
	// Bit mask of SOF4 field.
	DMAMUX_CSR_SOF4_Msk = 0x10
	// Bit SOF4.
	DMAMUX_CSR_SOF4 = 0x10
	// Position of SOF5 field.
	DMAMUX_CSR_SOF5_Pos = 0x5
	// Bit mask of SOF5 field.
	DMAMUX_CSR_SOF5_Msk = 0x20
	// Bit SOF5.
	DMAMUX_CSR_SOF5 = 0x20
	// Position of SOF6 field.
	DMAMUX_CSR_SOF6_Pos = 0x6
	// Bit mask of SOF6 field.
	DMAMUX_CSR_SOF6_Msk = 0x40
	// Bit SOF6.
	DMAMUX_CSR_SOF6 = 0x40
	// Position of SOF7 field.
	DMAMUX_CSR_SOF7_Pos = 0x7
	// Bit mask of SOF7 field.
	DMAMUX_CSR_SOF7_Msk = 0x80
	// Bit SOF7.
	DMAMUX_CSR_SOF7 = 0x80
	// Position of SOF8 field.
	DMAMUX_CSR_SOF8_Pos = 0x8
	// Bit mask of SOF8 field.
	DMAMUX_CSR_SOF8_Msk = 0x100
	// Bit SOF8.
	DMAMUX_CSR_SOF8 = 0x100
	// Position of SOF9 field.
	DMAMUX_CSR_SOF9_Pos = 0x9
	// Bit mask of SOF9 field.
	DMAMUX_CSR_SOF9_Msk = 0x200
	// Bit SOF9.
	DMAMUX_CSR_SOF9 = 0x200
	// Position of SOF10 field.
	DMAMUX_CSR_SOF10_Pos = 0xa
	// Bit mask of SOF10 field.
	DMAMUX_CSR_SOF10_Msk = 0x400
	// Bit SOF10.
	DMAMUX_CSR_SOF10 = 0x400
	// Position of SOF11 field.
	DMAMUX_CSR_SOF11_Pos = 0xb
	// Bit mask of SOF11 field.
	DMAMUX_CSR_SOF11_Msk = 0x800
	// Bit SOF11.
	DMAMUX_CSR_SOF11 = 0x800
	// Position of SOF12 field.
	DMAMUX_CSR_SOF12_Pos = 0xc
	// Bit mask of SOF12 field.
	DMAMUX_CSR_SOF12_Msk = 0x1000
	// Bit SOF12.
	DMAMUX_CSR_SOF12 = 0x1000
	// Position of SOF13 field.
	DMAMUX_CSR_SOF13_Pos = 0xd
	// Bit mask of SOF13 field.
	DMAMUX_CSR_SOF13_Msk = 0x2000
	// Bit SOF13.
	DMAMUX_CSR_SOF13 = 0x2000
	// Position of SOF14 field.
	DMAMUX_CSR_SOF14_Pos = 0xe
	// Bit mask of SOF14 field.
	DMAMUX_CSR_SOF14_Msk = 0x4000
	// Bit SOF14.
	DMAMUX_CSR_SOF14 = 0x4000
	// Position of SOF15 field.
	DMAMUX_CSR_SOF15_Pos = 0xf
	// Bit mask of SOF15 field.
	DMAMUX_CSR_SOF15_Msk = 0x8000
	// Bit SOF15.
	DMAMUX_CSR_SOF15 = 0x8000

	// CFR: DMAMUX request line multiplexer interrupt clear flag register
	// Position of CSOF0 field.
	DMAMUX_CFR_CSOF0_Pos = 0x0
	// Bit mask of CSOF0 field.
	DMAMUX_CFR_CSOF0_Msk = 0x1
	// Bit CSOF0.
	DMAMUX_CFR_CSOF0 = 0x1
	// Position of CSOF1 field.
	DMAMUX_CFR_CSOF1_Pos = 0x1
	// Bit mask of CSOF1 field.
	DMAMUX_CFR_CSOF1_Msk = 0x2
	// Bit CSOF1.
	DMAMUX_CFR_CSOF1 = 0x2
	// Position of CSOF2 field.
	DMAMUX_CFR_CSOF2_Pos = 0x2
	// Bit mask of CSOF2 field.
	DMAMUX_CFR_CSOF2_Msk = 0x4
	// Bit CSOF2.
	DMAMUX_CFR_CSOF2 = 0x4
	// Position of CSOF3 field.
	DMAMUX_CFR_CSOF3_Pos = 0x3
	// Bit mask of CSOF3 field.
	DMAMUX_CFR_CSOF3_Msk = 0x8
	// Bit CSOF3.
	DMAMUX_CFR_CSOF3 = 0x8
	// Position of CSOF4 field.
	DMAMUX_CFR_CSOF4_Pos = 0x4
	// Bit mask of CSOF4 field.
	DMAMUX_CFR_CSOF4_Msk = 0x10
	// Bit CSOF4.
	DMAMUX_CFR_CSOF4 = 0x10
	// Position of CSOF5 field.
	DMAMUX_CFR_CSOF5_Pos = 0x5
	// Bit mask of CSOF5 field.
	DMAMUX_CFR_CSOF5_Msk = 0x20
	// Bit CSOF5.
	DMAMUX_CFR_CSOF5 = 0x20
	// Position of CSOF6 field.
	DMAMUX_CFR_CSOF6_Pos = 0x6
	// Bit mask of CSOF6 field.
	DMAMUX_CFR_CSOF6_Msk = 0x40
	// Bit CSOF6.
	DMAMUX_CFR_CSOF6 = 0x40
	// Position of CSOF7 field.
	DMAMUX_CFR_CSOF7_Pos = 0x7
	// Bit mask of CSOF7 field.
	DMAMUX_CFR_CSOF7_Msk = 0x80
	// Bit CSOF7.
	DMAMUX_CFR_CSOF7 = 0x80
	// Position of CSOF8 field.
	DMAMUX_CFR_CSOF8_Pos = 0x8
	// Bit mask of CSOF8 field.
	DMAMUX_CFR_CSOF8_Msk = 0x100
	// Bit CSOF8.
	DMAMUX_CFR_CSOF8 = 0x100
	// Position of CSOF9 field.
	DMAMUX_CFR_CSOF9_Pos = 0x9
	// Bit mask of CSOF9 field.
	DMAMUX_CFR_CSOF9_Msk = 0x200
	// Bit CSOF9.
	DMAMUX_CFR_CSOF9 = 0x200
	// Position of CSOF10 field.
	DMAMUX_CFR_CSOF10_Pos = 0xa
	// Bit mask of CSOF10 field.
	DMAMUX_CFR_CSOF10_Msk = 0x400
	// Bit CSOF10.
	DMAMUX_CFR_CSOF10 = 0x400
	// Position of CSOF11 field.
	DMAMUX_CFR_CSOF11_Pos = 0xb
	// Bit mask of CSOF11 field.
	DMAMUX_CFR_CSOF11_Msk = 0x800
	// Bit CSOF11.
	DMAMUX_CFR_CSOF11 = 0x800
	// Position of CSOF12 field.
	DMAMUX_CFR_CSOF12_Pos = 0xc
	// Bit mask of CSOF12 field.
	DMAMUX_CFR_CSOF12_Msk = 0x1000
	// Bit CSOF12.
	DMAMUX_CFR_CSOF12 = 0x1000
	// Position of CSOF13 field.
	DMAMUX_CFR_CSOF13_Pos = 0xd
	// Bit mask of CSOF13 field.
	DMAMUX_CFR_CSOF13_Msk = 0x2000
	// Bit CSOF13.
	DMAMUX_CFR_CSOF13 = 0x2000
	// Position of CSOF14 field.
	DMAMUX_CFR_CSOF14_Pos = 0xe
	// Bit mask of CSOF14 field.
	DMAMUX_CFR_CSOF14_Msk = 0x4000
	// Bit CSOF14.
	DMAMUX_CFR_CSOF14 = 0x4000
	// Position of CSOF15 field.
	DMAMUX_CFR_CSOF15_Pos = 0xf
	// Bit mask of CSOF15 field.
	DMAMUX_CFR_CSOF15_Msk = 0x8000
	// Bit CSOF15.
	DMAMUX_CFR_CSOF15 = 0x8000

	// RGCR0: DMAMux - DMA request generator channel x control register
	// Position of SIG_ID field.
	DMAMUX_RGCR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX_RGCR_SIG_ID_Msk = 0x1f
	// Signal `dmamux2_evt0` selected as trigger input
	DMAMUX_RGCR_SIG_ID_DMAMUX2_EVT0 = 0x0
	// Signal `dmamux2_evt1` selected as trigger input
	DMAMUX_RGCR_SIG_ID_DMAMUX2_EVT1 = 0x1
	// Signal `dmamux2_evt2` selected as trigger input
	DMAMUX_RGCR_SIG_ID_DMAMUX2_EVT2 = 0x2
	// Signal `dmamux2_evt3` selected as trigger input
	DMAMUX_RGCR_SIG_ID_DMAMUX2_EVT3 = 0x3
	// Signal `dmamux2_evt4` selected as trigger input
	DMAMUX_RGCR_SIG_ID_DMAMUX2_EVT4 = 0x4
	// Signal `dmamux2_evt5` selected as trigger input
	DMAMUX_RGCR_SIG_ID_DMAMUX2_EVT5 = 0x5
	// Signal `dmamux2_evt6` selected as trigger input
	DMAMUX_RGCR_SIG_ID_DMAMUX2_EVT6 = 0x6
	// Signal `lpuart_rx_wkup` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPUART_RX_WKUP = 0x7
	// Signal `lpuart_tx_wkup` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPUART_TX_WKUP = 0x8
	// Signal `lptim2_wkup` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPTIM2_WKUP = 0x9
	// Signal `lptim2_out` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPTIM2_OUT = 0xa
	// Signal `lptim3_wkup` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPTIM3_WKUP = 0xb
	// Signal `lptim3_out` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPTIM3_OUT = 0xc
	// Signal `lptim4_ait` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPTIM4_AIT = 0xd
	// Signal `lptim5_ait` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPTIM5_AIT = 0xe
	// Signal `i2c4_wkup` selected as trigger input
	DMAMUX_RGCR_SIG_ID_I2C4_WKUP = 0xf
	// Signal `spi6_wkup` selected as trigger input
	DMAMUX_RGCR_SIG_ID_SPI6_WKUP = 0x10
	// Signal `comp1_out` selected as trigger input
	DMAMUX_RGCR_SIG_ID_COMP1_OUT = 0x11
	// Signal `comp2_out` selected as trigger input
	DMAMUX_RGCR_SIG_ID_COMP2_OUT = 0x12
	// Signal `rtc_wkup` selected as trigger input
	DMAMUX_RGCR_SIG_ID_RTC_WKUP = 0x13
	// Signal `syscfg_exti0_mux` selected as trigger input
	DMAMUX_RGCR_SIG_ID_SYSCFG_EXTI0_MUX = 0x14
	// Signal `syscfg_exti2_mux` selected as trigger input
	DMAMUX_RGCR_SIG_ID_SYSCFG_EXTI2_MUX = 0x15
	// Signal `i2c4_event_it` selected as trigger input
	DMAMUX_RGCR_SIG_ID_I2C4_EVENT_IT = 0x16
	// Signal `spi6_it` selected as trigger input
	DMAMUX_RGCR_SIG_ID_SPI6_IT = 0x17
	// Signal `lpuart1_it_t` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPUART1_IT_T = 0x18
	// Signal `lpuart1_it_r` selected as trigger input
	DMAMUX_RGCR_SIG_ID_LPUART1_IT_R = 0x19
	// Signal `adc3_it` selected as trigger input
	DMAMUX_RGCR_SIG_ID_ADC3_IT = 0x1a
	// Signal `adc3_awd1` selected as trigger input
	DMAMUX_RGCR_SIG_ID_ADC3_AWD1 = 0x1b
	// Signal `bdma_ch0_it` selected as trigger input
	DMAMUX_RGCR_SIG_ID_BDMA_CH0_IT = 0x1c
	// Signal `bdma_ch1_it` selected as trigger input
	DMAMUX_RGCR_SIG_ID_BDMA_CH1_IT = 0x1d
	// Position of OIE field.
	DMAMUX_RGCR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX_RGCR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX_RGCR_OIE = 0x100
	// Trigger overrun interrupt disabled
	DMAMUX_RGCR_OIE_Disabled = 0x0
	// Trigger overrun interrupt enabled
	DMAMUX_RGCR_OIE_Enabled = 0x1
	// Position of GE field.
	DMAMUX_RGCR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX_RGCR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX_RGCR_GE = 0x10000
	// DMA request generation disabled
	DMAMUX_RGCR_GE_Disabled = 0x0
	// DMA request enabled
	DMAMUX_RGCR_GE_Enabled = 0x1
	// Position of GPOL field.
	DMAMUX_RGCR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX_RGCR_GPOL_Msk = 0x60000
	// No event, i.e. no detection nor generation
	DMAMUX_RGCR_GPOL_NoEdge = 0x0
	// Rising edge
	DMAMUX_RGCR_GPOL_RisingEdge = 0x1
	// Falling edge
	DMAMUX_RGCR_GPOL_FallingEdge = 0x2
	// Rising and falling edges
	DMAMUX_RGCR_GPOL_BothEdges = 0x3
	// Position of GNBREQ field.
	DMAMUX_RGCR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX_RGCR_GNBREQ_Msk = 0xf80000

	// RGSR: DMAMux - DMA request generator status register
	// Position of OF0 field.
	DMAMUX_RGSR_OF0_Pos = 0x0
	// Bit mask of OF0 field.
	DMAMUX_RGSR_OF0_Msk = 0x1
	// Bit OF0.
	DMAMUX_RGSR_OF0 = 0x1
	// Position of OF1 field.
	DMAMUX_RGSR_OF1_Pos = 0x1
	// Bit mask of OF1 field.
	DMAMUX_RGSR_OF1_Msk = 0x2
	// Bit OF1.
	DMAMUX_RGSR_OF1 = 0x2
	// Position of OF2 field.
	DMAMUX_RGSR_OF2_Pos = 0x2
	// Bit mask of OF2 field.
	DMAMUX_RGSR_OF2_Msk = 0x4
	// Bit OF2.
	DMAMUX_RGSR_OF2 = 0x4
	// Position of OF3 field.
	DMAMUX_RGSR_OF3_Pos = 0x3
	// Bit mask of OF3 field.
	DMAMUX_RGSR_OF3_Msk = 0x8
	// Bit OF3.
	DMAMUX_RGSR_OF3 = 0x8
	// Position of OF4 field.
	DMAMUX_RGSR_OF4_Pos = 0x4
	// Bit mask of OF4 field.
	DMAMUX_RGSR_OF4_Msk = 0x10
	// Bit OF4.
	DMAMUX_RGSR_OF4 = 0x10
	// Position of OF5 field.
	DMAMUX_RGSR_OF5_Pos = 0x5
	// Bit mask of OF5 field.
	DMAMUX_RGSR_OF5_Msk = 0x20
	// Bit OF5.
	DMAMUX_RGSR_OF5 = 0x20
	// Position of OF6 field.
	DMAMUX_RGSR_OF6_Pos = 0x6
	// Bit mask of OF6 field.
	DMAMUX_RGSR_OF6_Msk = 0x40
	// Bit OF6.
	DMAMUX_RGSR_OF6 = 0x40
	// Position of OF7 field.
	DMAMUX_RGSR_OF7_Pos = 0x7
	// Bit mask of OF7 field.
	DMAMUX_RGSR_OF7_Msk = 0x80
	// Bit OF7.
	DMAMUX_RGSR_OF7 = 0x80

	// RGCFR: DMAMux - DMA request generator clear flag register
	// Position of COF0 field.
	DMAMUX_RGCFR_COF0_Pos = 0x0
	// Bit mask of COF0 field.
	DMAMUX_RGCFR_COF0_Msk = 0x1
	// Bit COF0.
	DMAMUX_RGCFR_COF0 = 0x1
	// Position of COF1 field.
	DMAMUX_RGCFR_COF1_Pos = 0x1
	// Bit mask of COF1 field.
	DMAMUX_RGCFR_COF1_Msk = 0x2
	// Bit COF1.
	DMAMUX_RGCFR_COF1 = 0x2
	// Position of COF2 field.
	DMAMUX_RGCFR_COF2_Pos = 0x2
	// Bit mask of COF2 field.
	DMAMUX_RGCFR_COF2_Msk = 0x4
	// Bit COF2.
	DMAMUX_RGCFR_COF2 = 0x4
	// Position of COF3 field.
	DMAMUX_RGCFR_COF3_Pos = 0x3
	// Bit mask of COF3 field.
	DMAMUX_RGCFR_COF3_Msk = 0x8
	// Bit COF3.
	DMAMUX_RGCFR_COF3 = 0x8
	// Position of COF4 field.
	DMAMUX_RGCFR_COF4_Pos = 0x4
	// Bit mask of COF4 field.
	DMAMUX_RGCFR_COF4_Msk = 0x10
	// Bit COF4.
	DMAMUX_RGCFR_COF4 = 0x10
	// Position of COF5 field.
	DMAMUX_RGCFR_COF5_Pos = 0x5
	// Bit mask of COF5 field.
	DMAMUX_RGCFR_COF5_Msk = 0x20
	// Bit COF5.
	DMAMUX_RGCFR_COF5 = 0x20
	// Position of COF6 field.
	DMAMUX_RGCFR_COF6_Pos = 0x6
	// Bit mask of COF6 field.
	DMAMUX_RGCFR_COF6_Msk = 0x40
	// Bit COF6.
	DMAMUX_RGCFR_COF6 = 0x40
	// Position of COF7 field.
	DMAMUX_RGCFR_COF7_Pos = 0x7
	// Bit mask of COF7 field.
	DMAMUX_RGCFR_COF7_Msk = 0x80
	// Bit COF7.
	DMAMUX_RGCFR_COF7 = 0x80
)

// Bitfields for FMC: FMC
const (
	// BCR1: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_BCR1_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR1_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR1_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_BCR1_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR1_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR1_MUXEN = 0x2
	// Position of MTYP field.
	FMC_BCR1_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR1_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_BCR1_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR1_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_BCR1_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR1_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR1_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_BCR1_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR1_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR1_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_BCR1_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR1_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR1_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_BCR1_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR1_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR1_WAITCFG = 0x800
	// Position of WREN field.
	FMC_BCR1_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR1_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR1_WREN = 0x1000
	// Position of WAITEN field.
	FMC_BCR1_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR1_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR1_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_BCR1_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR1_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR1_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR1_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_BCR1_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR1_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR1_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_BCR1_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_BCR1_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_BCR1_CCLKEN = 0x100000
	// Position of WFDIS field.
	FMC_BCR1_WFDIS_Pos = 0x15
	// Bit mask of WFDIS field.
	FMC_BCR1_WFDIS_Msk = 0x200000
	// Bit WFDIS.
	FMC_BCR1_WFDIS = 0x200000
	// Position of BMAP field.
	FMC_BCR1_BMAP_Pos = 0x18
	// Bit mask of BMAP field.
	FMC_BCR1_BMAP_Msk = 0x3000000
	// Position of FMCEN field.
	FMC_BCR1_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_BCR1_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_BCR1_FMCEN = 0x80000000

	// BTR1: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_BTR1_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BTR1_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BTR1_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BTR1_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BTR1_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BTR1_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BTR1_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BTR1_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_BTR1_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_BTR1_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_BTR1_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_BTR1_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_BTR1_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BTR1_ACCMOD_Msk = 0x30000000

	// BCR2: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_BCR2_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR2_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR2_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_BCR2_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR2_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR2_MUXEN = 0x2
	// Position of MTYP field.
	FMC_BCR2_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR2_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_BCR2_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR2_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_BCR2_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR2_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR2_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_BCR2_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR2_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR2_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_BCR2_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR2_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR2_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_BCR2_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR2_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR2_WAITCFG = 0x800
	// Position of WREN field.
	FMC_BCR2_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR2_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR2_WREN = 0x1000
	// Position of WAITEN field.
	FMC_BCR2_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR2_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR2_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_BCR2_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR2_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR2_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_BCR2_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR2_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR2_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_BCR2_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR2_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_BCR2_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR2_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR2_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_BCR2_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_BCR2_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_BCR2_CCLKEN = 0x100000
	// Position of WFDIS field.
	FMC_BCR2_WFDIS_Pos = 0x15
	// Bit mask of WFDIS field.
	FMC_BCR2_WFDIS_Msk = 0x200000
	// Bit WFDIS.
	FMC_BCR2_WFDIS = 0x200000
	// Position of BMAP field.
	FMC_BCR2_BMAP_Pos = 0x18
	// Bit mask of BMAP field.
	FMC_BCR2_BMAP_Msk = 0x3000000
	// Position of FMCEN field.
	FMC_BCR2_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_BCR2_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_BCR2_FMCEN = 0x80000000

	// BTR2: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_BTR2_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BTR2_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BTR2_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BTR2_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BTR2_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BTR2_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BTR2_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BTR2_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_BTR2_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_BTR2_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_BTR2_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_BTR2_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_BTR2_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BTR2_ACCMOD_Msk = 0x30000000

	// BCR3: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_BCR3_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR3_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR3_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_BCR3_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR3_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR3_MUXEN = 0x2
	// Position of MTYP field.
	FMC_BCR3_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR3_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_BCR3_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR3_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_BCR3_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR3_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR3_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_BCR3_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR3_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR3_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_BCR3_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR3_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR3_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_BCR3_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR3_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR3_WAITCFG = 0x800
	// Position of WREN field.
	FMC_BCR3_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR3_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR3_WREN = 0x1000
	// Position of WAITEN field.
	FMC_BCR3_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR3_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR3_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_BCR3_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR3_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR3_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_BCR3_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR3_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR3_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_BCR3_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR3_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_BCR3_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR3_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR3_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_BCR3_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_BCR3_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_BCR3_CCLKEN = 0x100000
	// Position of WFDIS field.
	FMC_BCR3_WFDIS_Pos = 0x15
	// Bit mask of WFDIS field.
	FMC_BCR3_WFDIS_Msk = 0x200000
	// Bit WFDIS.
	FMC_BCR3_WFDIS = 0x200000
	// Position of BMAP field.
	FMC_BCR3_BMAP_Pos = 0x18
	// Bit mask of BMAP field.
	FMC_BCR3_BMAP_Msk = 0x3000000
	// Position of FMCEN field.
	FMC_BCR3_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_BCR3_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_BCR3_FMCEN = 0x80000000

	// BTR3: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_BTR3_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BTR3_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BTR3_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BTR3_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BTR3_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BTR3_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BTR3_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BTR3_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_BTR3_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_BTR3_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_BTR3_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_BTR3_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_BTR3_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BTR3_ACCMOD_Msk = 0x30000000

	// BCR4: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
	// Position of MBKEN field.
	FMC_BCR4_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR4_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR4_MBKEN = 0x1
	// Position of MUXEN field.
	FMC_BCR4_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR4_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR4_MUXEN = 0x2
	// Position of MTYP field.
	FMC_BCR4_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR4_MTYP_Msk = 0xc
	// Position of MWID field.
	FMC_BCR4_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR4_MWID_Msk = 0x30
	// Position of FACCEN field.
	FMC_BCR4_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR4_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR4_FACCEN = 0x40
	// Position of BURSTEN field.
	FMC_BCR4_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR4_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR4_BURSTEN = 0x100
	// Position of WAITPOL field.
	FMC_BCR4_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR4_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR4_WAITPOL = 0x200
	// Position of WAITCFG field.
	FMC_BCR4_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR4_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR4_WAITCFG = 0x800
	// Position of WREN field.
	FMC_BCR4_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR4_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR4_WREN = 0x1000
	// Position of WAITEN field.
	FMC_BCR4_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR4_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR4_WAITEN = 0x2000
	// Position of EXTMOD field.
	FMC_BCR4_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR4_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR4_EXTMOD = 0x4000
	// Position of ASYNCWAIT field.
	FMC_BCR4_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR4_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR4_ASYNCWAIT = 0x8000
	// Position of CPSIZE field.
	FMC_BCR4_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR4_CPSIZE_Msk = 0x70000
	// Position of CBURSTRW field.
	FMC_BCR4_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR4_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR4_CBURSTRW = 0x80000
	// Position of CCLKEN field.
	FMC_BCR4_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_BCR4_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_BCR4_CCLKEN = 0x100000
	// Position of WFDIS field.
	FMC_BCR4_WFDIS_Pos = 0x15
	// Bit mask of WFDIS field.
	FMC_BCR4_WFDIS_Msk = 0x200000
	// Bit WFDIS.
	FMC_BCR4_WFDIS = 0x200000
	// Position of BMAP field.
	FMC_BCR4_BMAP_Pos = 0x18
	// Bit mask of BMAP field.
	FMC_BCR4_BMAP_Msk = 0x3000000
	// Position of FMCEN field.
	FMC_BCR4_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_BCR4_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_BCR4_FMCEN = 0x80000000

	// BTR4: This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
	// Position of ADDSET field.
	FMC_BTR4_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BTR4_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BTR4_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BTR4_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BTR4_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BTR4_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BTR4_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BTR4_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_BTR4_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_BTR4_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_BTR4_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_BTR4_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_BTR4_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BTR4_ACCMOD_Msk = 0x30000000

	// PCR: NAND Flash control registers
	// Position of PWAITEN field.
	FMC_PCR_PWAITEN_Pos = 0x1
	// Bit mask of PWAITEN field.
	FMC_PCR_PWAITEN_Msk = 0x2
	// Bit PWAITEN.
	FMC_PCR_PWAITEN = 0x2
	// Position of PBKEN field.
	FMC_PCR_PBKEN_Pos = 0x2
	// Bit mask of PBKEN field.
	FMC_PCR_PBKEN_Msk = 0x4
	// Bit PBKEN.
	FMC_PCR_PBKEN = 0x4
	// Position of PWID field.
	FMC_PCR_PWID_Pos = 0x4
	// Bit mask of PWID field.
	FMC_PCR_PWID_Msk = 0x30
	// Position of ECCEN field.
	FMC_PCR_ECCEN_Pos = 0x6
	// Bit mask of ECCEN field.
	FMC_PCR_ECCEN_Msk = 0x40
	// Bit ECCEN.
	FMC_PCR_ECCEN = 0x40
	// Position of TCLR field.
	FMC_PCR_TCLR_Pos = 0x9
	// Bit mask of TCLR field.
	FMC_PCR_TCLR_Msk = 0x1e00
	// Position of TAR field.
	FMC_PCR_TAR_Pos = 0xd
	// Bit mask of TAR field.
	FMC_PCR_TAR_Msk = 0x1e000
	// Position of ECCPS field.
	FMC_PCR_ECCPS_Pos = 0x11
	// Bit mask of ECCPS field.
	FMC_PCR_ECCPS_Msk = 0xe0000

	// SR: This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
	// Position of IRS field.
	FMC_SR_IRS_Pos = 0x0
	// Bit mask of IRS field.
	FMC_SR_IRS_Msk = 0x1
	// Bit IRS.
	FMC_SR_IRS = 0x1
	// Position of ILS field.
	FMC_SR_ILS_Pos = 0x1
	// Bit mask of ILS field.
	FMC_SR_ILS_Msk = 0x2
	// Bit ILS.
	FMC_SR_ILS = 0x2
	// Position of IFS field.
	FMC_SR_IFS_Pos = 0x2
	// Bit mask of IFS field.
	FMC_SR_IFS_Msk = 0x4
	// Bit IFS.
	FMC_SR_IFS = 0x4
	// Position of IREN field.
	FMC_SR_IREN_Pos = 0x3
	// Bit mask of IREN field.
	FMC_SR_IREN_Msk = 0x8
	// Bit IREN.
	FMC_SR_IREN = 0x8
	// Position of ILEN field.
	FMC_SR_ILEN_Pos = 0x4
	// Bit mask of ILEN field.
	FMC_SR_ILEN_Msk = 0x10
	// Bit ILEN.
	FMC_SR_ILEN = 0x10
	// Position of IFEN field.
	FMC_SR_IFEN_Pos = 0x5
	// Bit mask of IFEN field.
	FMC_SR_IFEN_Msk = 0x20
	// Bit IFEN.
	FMC_SR_IFEN = 0x20
	// Position of FEMPT field.
	FMC_SR_FEMPT_Pos = 0x6
	// Bit mask of FEMPT field.
	FMC_SR_FEMPT_Msk = 0x40
	// Bit FEMPT.
	FMC_SR_FEMPT = 0x40

	// PMEM: The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
	// Position of MEMSET field.
	FMC_PMEM_MEMSET_Pos = 0x0
	// Bit mask of MEMSET field.
	FMC_PMEM_MEMSET_Msk = 0xff
	// Position of MEMWAIT field.
	FMC_PMEM_MEMWAIT_Pos = 0x8
	// Bit mask of MEMWAIT field.
	FMC_PMEM_MEMWAIT_Msk = 0xff00
	// Position of MEMHOLD field.
	FMC_PMEM_MEMHOLD_Pos = 0x10
	// Bit mask of MEMHOLD field.
	FMC_PMEM_MEMHOLD_Msk = 0xff0000
	// Position of MEMHIZ field.
	FMC_PMEM_MEMHIZ_Pos = 0x18
	// Bit mask of MEMHIZ field.
	FMC_PMEM_MEMHIZ_Msk = 0xff000000

	// PATT: The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
	// Position of ATTSET field.
	FMC_PATT_ATTSET_Pos = 0x0
	// Bit mask of ATTSET field.
	FMC_PATT_ATTSET_Msk = 0xff
	// Position of ATTWAIT field.
	FMC_PATT_ATTWAIT_Pos = 0x8
	// Bit mask of ATTWAIT field.
	FMC_PATT_ATTWAIT_Msk = 0xff00
	// Position of ATTHOLD field.
	FMC_PATT_ATTHOLD_Pos = 0x10
	// Bit mask of ATTHOLD field.
	FMC_PATT_ATTHOLD_Msk = 0xff0000
	// Position of ATTHIZ field.
	FMC_PATT_ATTHIZ_Pos = 0x18
	// Bit mask of ATTHIZ field.
	FMC_PATT_ATTHIZ_Msk = 0xff000000

	// ECCR: This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
	// Position of ECC field.
	FMC_ECCR_ECC_Pos = 0x0
	// Bit mask of ECC field.
	FMC_ECCR_ECC_Msk = 0xffffffff

	// BWTR1: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_BWTR1_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BWTR1_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BWTR1_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BWTR1_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BWTR1_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BWTR1_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BWTR1_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BWTR1_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_BWTR1_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BWTR1_ACCMOD_Msk = 0x30000000

	// BWTR2: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_BWTR2_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BWTR2_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BWTR2_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BWTR2_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BWTR2_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BWTR2_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BWTR2_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BWTR2_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_BWTR2_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BWTR2_ACCMOD_Msk = 0x30000000

	// BWTR3: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_BWTR3_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BWTR3_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BWTR3_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BWTR3_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BWTR3_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BWTR3_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BWTR3_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BWTR3_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_BWTR3_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BWTR3_ACCMOD_Msk = 0x30000000

	// BWTR4: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_BWTR4_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BWTR4_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BWTR4_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BWTR4_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BWTR4_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BWTR4_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BWTR4_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BWTR4_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_BWTR4_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BWTR4_ACCMOD_Msk = 0x30000000

	// SDBANK.SDCR: This register contains the control parameters for each SDRAM memory bank
	// Position of NC field.
	FMC_SDBANK_SDCR_NC_Pos = 0x0
	// Bit mask of NC field.
	FMC_SDBANK_SDCR_NC_Msk = 0x3
	// Position of NR field.
	FMC_SDBANK_SDCR_NR_Pos = 0x2
	// Bit mask of NR field.
	FMC_SDBANK_SDCR_NR_Msk = 0xc
	// Position of MWID field.
	FMC_SDBANK_SDCR_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_SDBANK_SDCR_MWID_Msk = 0x30
	// Position of NB field.
	FMC_SDBANK_SDCR_NB_Pos = 0x6
	// Bit mask of NB field.
	FMC_SDBANK_SDCR_NB_Msk = 0x40
	// Bit NB.
	FMC_SDBANK_SDCR_NB = 0x40
	// Position of CAS field.
	FMC_SDBANK_SDCR_CAS_Pos = 0x7
	// Bit mask of CAS field.
	FMC_SDBANK_SDCR_CAS_Msk = 0x180
	// Position of WP field.
	FMC_SDBANK_SDCR_WP_Pos = 0x9
	// Bit mask of WP field.
	FMC_SDBANK_SDCR_WP_Msk = 0x200
	// Bit WP.
	FMC_SDBANK_SDCR_WP = 0x200
	// Position of SDCLK field.
	FMC_SDBANK_SDCR_SDCLK_Pos = 0xa
	// Bit mask of SDCLK field.
	FMC_SDBANK_SDCR_SDCLK_Msk = 0xc00
	// Position of RBURST field.
	FMC_SDBANK_SDCR_RBURST_Pos = 0xc
	// Bit mask of RBURST field.
	FMC_SDBANK_SDCR_RBURST_Msk = 0x1000
	// Bit RBURST.
	FMC_SDBANK_SDCR_RBURST = 0x1000
	// Position of RPIPE field.
	FMC_SDBANK_SDCR_RPIPE_Pos = 0xd
	// Bit mask of RPIPE field.
	FMC_SDBANK_SDCR_RPIPE_Msk = 0x6000

	// SDBANK.SDTR: This register contains the timing parameters of each SDRAM bank
	// Position of TMRD field.
	FMC_SDBANK_SDTR_TMRD_Pos = 0x0
	// Bit mask of TMRD field.
	FMC_SDBANK_SDTR_TMRD_Msk = 0xf
	// Position of TXSR field.
	FMC_SDBANK_SDTR_TXSR_Pos = 0x4
	// Bit mask of TXSR field.
	FMC_SDBANK_SDTR_TXSR_Msk = 0xf0
	// Position of TRAS field.
	FMC_SDBANK_SDTR_TRAS_Pos = 0x8
	// Bit mask of TRAS field.
	FMC_SDBANK_SDTR_TRAS_Msk = 0xf00
	// Position of TRC field.
	FMC_SDBANK_SDTR_TRC_Pos = 0xc
	// Bit mask of TRC field.
	FMC_SDBANK_SDTR_TRC_Msk = 0xf000
	// Position of TWR field.
	FMC_SDBANK_SDTR_TWR_Pos = 0x10
	// Bit mask of TWR field.
	FMC_SDBANK_SDTR_TWR_Msk = 0xf0000
	// Position of TRP field.
	FMC_SDBANK_SDTR_TRP_Pos = 0x14
	// Bit mask of TRP field.
	FMC_SDBANK_SDTR_TRP_Msk = 0xf00000
	// Position of TRCD field.
	FMC_SDBANK_SDTR_TRCD_Pos = 0x18
	// Bit mask of TRCD field.
	FMC_SDBANK_SDTR_TRCD_Msk = 0xf000000

	// SDCMR: This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks.
	// Position of MODE field.
	FMC_SDCMR_MODE_Pos = 0x0
	// Bit mask of MODE field.
	FMC_SDCMR_MODE_Msk = 0x7
	// Position of CTB2 field.
	FMC_SDCMR_CTB2_Pos = 0x3
	// Bit mask of CTB2 field.
	FMC_SDCMR_CTB2_Msk = 0x8
	// Bit CTB2.
	FMC_SDCMR_CTB2 = 0x8
	// Position of CTB1 field.
	FMC_SDCMR_CTB1_Pos = 0x4
	// Bit mask of CTB1 field.
	FMC_SDCMR_CTB1_Msk = 0x10
	// Bit CTB1.
	FMC_SDCMR_CTB1 = 0x10
	// Position of NRFS field.
	FMC_SDCMR_NRFS_Pos = 0x5
	// Bit mask of NRFS field.
	FMC_SDCMR_NRFS_Msk = 0x1e0
	// Position of MRD field.
	FMC_SDCMR_MRD_Pos = 0x9
	// Bit mask of MRD field.
	FMC_SDCMR_MRD_Msk = 0x7ffe00

	// SDRTR: This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is 0, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.This register is common to SDRAM bank 1 and bank 2.
	// Position of CRE field.
	FMC_SDRTR_CRE_Pos = 0x0
	// Bit mask of CRE field.
	FMC_SDRTR_CRE_Msk = 0x1
	// Bit CRE.
	FMC_SDRTR_CRE = 0x1
	// Position of COUNT field.
	FMC_SDRTR_COUNT_Pos = 0x1
	// Bit mask of COUNT field.
	FMC_SDRTR_COUNT_Msk = 0x3ffe
	// Position of REIE field.
	FMC_SDRTR_REIE_Pos = 0xe
	// Bit mask of REIE field.
	FMC_SDRTR_REIE_Msk = 0x4000
	// Bit REIE.
	FMC_SDRTR_REIE = 0x4000

	// SDSR: SDRAM Status register
	// Position of RE field.
	FMC_SDSR_RE_Pos = 0x0
	// Bit mask of RE field.
	FMC_SDSR_RE_Msk = 0x1
	// Bit RE.
	FMC_SDSR_RE = 0x1
	// Position of MODES1 field.
	FMC_SDSR_MODES1_Pos = 0x1
	// Bit mask of MODES1 field.
	FMC_SDSR_MODES1_Msk = 0x6
	// Position of MODES2 field.
	FMC_SDSR_MODES2_Pos = 0x3
	// Bit mask of MODES2 field.
	FMC_SDSR_MODES2_Msk = 0x18
)

// Bitfields for CEC: CEC
const (
	// CR: CEC control register
	// Position of CECEN field.
	CEC_CR_CECEN_Pos = 0x0
	// Bit mask of CECEN field.
	CEC_CR_CECEN_Msk = 0x1
	// Bit CECEN.
	CEC_CR_CECEN = 0x1
	// Position of TXSOM field.
	CEC_CR_TXSOM_Pos = 0x1
	// Bit mask of TXSOM field.
	CEC_CR_TXSOM_Msk = 0x2
	// Bit TXSOM.
	CEC_CR_TXSOM = 0x2
	// Position of TXEOM field.
	CEC_CR_TXEOM_Pos = 0x2
	// Bit mask of TXEOM field.
	CEC_CR_TXEOM_Msk = 0x4
	// Bit TXEOM.
	CEC_CR_TXEOM = 0x4

	// CFGR: This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.
	// Position of SFT field.
	CEC_CFGR_SFT_Pos = 0x0
	// Bit mask of SFT field.
	CEC_CFGR_SFT_Msk = 0x7
	// Position of RXTOL field.
	CEC_CFGR_RXTOL_Pos = 0x3
	// Bit mask of RXTOL field.
	CEC_CFGR_RXTOL_Msk = 0x8
	// Bit RXTOL.
	CEC_CFGR_RXTOL = 0x8
	// Position of BRESTP field.
	CEC_CFGR_BRESTP_Pos = 0x4
	// Bit mask of BRESTP field.
	CEC_CFGR_BRESTP_Msk = 0x10
	// Bit BRESTP.
	CEC_CFGR_BRESTP = 0x10
	// Position of BREGEN field.
	CEC_CFGR_BREGEN_Pos = 0x5
	// Bit mask of BREGEN field.
	CEC_CFGR_BREGEN_Msk = 0x20
	// Bit BREGEN.
	CEC_CFGR_BREGEN = 0x20
	// Position of LBPEGEN field.
	CEC_CFGR_LBPEGEN_Pos = 0x6
	// Bit mask of LBPEGEN field.
	CEC_CFGR_LBPEGEN_Msk = 0x40
	// Bit LBPEGEN.
	CEC_CFGR_LBPEGEN = 0x40
	// Position of BRDNOGEN field.
	CEC_CFGR_BRDNOGEN_Pos = 0x7
	// Bit mask of BRDNOGEN field.
	CEC_CFGR_BRDNOGEN_Msk = 0x80
	// Bit BRDNOGEN.
	CEC_CFGR_BRDNOGEN = 0x80
	// Position of SFTOPT field.
	CEC_CFGR_SFTOPT_Pos = 0x8
	// Bit mask of SFTOPT field.
	CEC_CFGR_SFTOPT_Msk = 0x100
	// Bit SFTOPT.
	CEC_CFGR_SFTOPT = 0x100
	// Position of OAR field.
	CEC_CFGR_OAR_Pos = 0x10
	// Bit mask of OAR field.
	CEC_CFGR_OAR_Msk = 0x7fff0000
	// Position of LSTN field.
	CEC_CFGR_LSTN_Pos = 0x1f
	// Bit mask of LSTN field.
	CEC_CFGR_LSTN_Msk = 0x80000000
	// Bit LSTN.
	CEC_CFGR_LSTN = 0x80000000

	// TXDR: CEC Tx data register
	// Position of TXD field.
	CEC_TXDR_TXD_Pos = 0x0
	// Bit mask of TXD field.
	CEC_TXDR_TXD_Msk = 0xff

	// RXDR: CEC Rx Data Register
	// Position of RXD field.
	CEC_RXDR_RXD_Pos = 0x0
	// Bit mask of RXD field.
	CEC_RXDR_RXD_Msk = 0xff

	// ISR: CEC Interrupt and Status Register
	// Position of RXBR field.
	CEC_ISR_RXBR_Pos = 0x0
	// Bit mask of RXBR field.
	CEC_ISR_RXBR_Msk = 0x1
	// Bit RXBR.
	CEC_ISR_RXBR = 0x1
	// Position of RXEND field.
	CEC_ISR_RXEND_Pos = 0x1
	// Bit mask of RXEND field.
	CEC_ISR_RXEND_Msk = 0x2
	// Bit RXEND.
	CEC_ISR_RXEND = 0x2
	// Position of RXOVR field.
	CEC_ISR_RXOVR_Pos = 0x2
	// Bit mask of RXOVR field.
	CEC_ISR_RXOVR_Msk = 0x4
	// Bit RXOVR.
	CEC_ISR_RXOVR = 0x4
	// Position of BRE field.
	CEC_ISR_BRE_Pos = 0x3
	// Bit mask of BRE field.
	CEC_ISR_BRE_Msk = 0x8
	// Bit BRE.
	CEC_ISR_BRE = 0x8
	// Position of SBPE field.
	CEC_ISR_SBPE_Pos = 0x4
	// Bit mask of SBPE field.
	CEC_ISR_SBPE_Msk = 0x10
	// Bit SBPE.
	CEC_ISR_SBPE = 0x10
	// Position of LBPE field.
	CEC_ISR_LBPE_Pos = 0x5
	// Bit mask of LBPE field.
	CEC_ISR_LBPE_Msk = 0x20
	// Bit LBPE.
	CEC_ISR_LBPE = 0x20
	// Position of RXACKE field.
	CEC_ISR_RXACKE_Pos = 0x6
	// Bit mask of RXACKE field.
	CEC_ISR_RXACKE_Msk = 0x40
	// Bit RXACKE.
	CEC_ISR_RXACKE = 0x40
	// Position of ARBLST field.
	CEC_ISR_ARBLST_Pos = 0x7
	// Bit mask of ARBLST field.
	CEC_ISR_ARBLST_Msk = 0x80
	// Bit ARBLST.
	CEC_ISR_ARBLST = 0x80
	// Position of TXBR field.
	CEC_ISR_TXBR_Pos = 0x8
	// Bit mask of TXBR field.
	CEC_ISR_TXBR_Msk = 0x100
	// Bit TXBR.
	CEC_ISR_TXBR = 0x100
	// Position of TXEND field.
	CEC_ISR_TXEND_Pos = 0x9
	// Bit mask of TXEND field.
	CEC_ISR_TXEND_Msk = 0x200
	// Bit TXEND.
	CEC_ISR_TXEND = 0x200
	// Position of TXUDR field.
	CEC_ISR_TXUDR_Pos = 0xa
	// Bit mask of TXUDR field.
	CEC_ISR_TXUDR_Msk = 0x400
	// Bit TXUDR.
	CEC_ISR_TXUDR = 0x400
	// Position of TXERR field.
	CEC_ISR_TXERR_Pos = 0xb
	// Bit mask of TXERR field.
	CEC_ISR_TXERR_Msk = 0x800
	// Bit TXERR.
	CEC_ISR_TXERR = 0x800
	// Position of TXACKE field.
	CEC_ISR_TXACKE_Pos = 0xc
	// Bit mask of TXACKE field.
	CEC_ISR_TXACKE_Msk = 0x1000
	// Bit TXACKE.
	CEC_ISR_TXACKE = 0x1000

	// IER: CEC interrupt enable register
	// Position of RXBRIE field.
	CEC_IER_RXBRIE_Pos = 0x0
	// Bit mask of RXBRIE field.
	CEC_IER_RXBRIE_Msk = 0x1
	// Bit RXBRIE.
	CEC_IER_RXBRIE = 0x1
	// Position of RXENDIE field.
	CEC_IER_RXENDIE_Pos = 0x1
	// Bit mask of RXENDIE field.
	CEC_IER_RXENDIE_Msk = 0x2
	// Bit RXENDIE.
	CEC_IER_RXENDIE = 0x2
	// Position of RXOVRIE field.
	CEC_IER_RXOVRIE_Pos = 0x2
	// Bit mask of RXOVRIE field.
	CEC_IER_RXOVRIE_Msk = 0x4
	// Bit RXOVRIE.
	CEC_IER_RXOVRIE = 0x4
	// Position of BREIE field.
	CEC_IER_BREIE_Pos = 0x3
	// Bit mask of BREIE field.
	CEC_IER_BREIE_Msk = 0x8
	// Bit BREIE.
	CEC_IER_BREIE = 0x8
	// Position of SBPEIE field.
	CEC_IER_SBPEIE_Pos = 0x4
	// Bit mask of SBPEIE field.
	CEC_IER_SBPEIE_Msk = 0x10
	// Bit SBPEIE.
	CEC_IER_SBPEIE = 0x10
	// Position of LBPEIE field.
	CEC_IER_LBPEIE_Pos = 0x5
	// Bit mask of LBPEIE field.
	CEC_IER_LBPEIE_Msk = 0x20
	// Bit LBPEIE.
	CEC_IER_LBPEIE = 0x20
	// Position of RXACKIE field.
	CEC_IER_RXACKIE_Pos = 0x6
	// Bit mask of RXACKIE field.
	CEC_IER_RXACKIE_Msk = 0x40
	// Bit RXACKIE.
	CEC_IER_RXACKIE = 0x40
	// Position of ARBLSTIE field.
	CEC_IER_ARBLSTIE_Pos = 0x7
	// Bit mask of ARBLSTIE field.
	CEC_IER_ARBLSTIE_Msk = 0x80
	// Bit ARBLSTIE.
	CEC_IER_ARBLSTIE = 0x80
	// Position of TXBRIE field.
	CEC_IER_TXBRIE_Pos = 0x8
	// Bit mask of TXBRIE field.
	CEC_IER_TXBRIE_Msk = 0x100
	// Bit TXBRIE.
	CEC_IER_TXBRIE = 0x100
	// Position of TXENDIE field.
	CEC_IER_TXENDIE_Pos = 0x9
	// Bit mask of TXENDIE field.
	CEC_IER_TXENDIE_Msk = 0x200
	// Bit TXENDIE.
	CEC_IER_TXENDIE = 0x200
	// Position of TXUDRIE field.
	CEC_IER_TXUDRIE_Pos = 0xa
	// Bit mask of TXUDRIE field.
	CEC_IER_TXUDRIE_Msk = 0x400
	// Bit TXUDRIE.
	CEC_IER_TXUDRIE = 0x400
	// Position of TXERRIE field.
	CEC_IER_TXERRIE_Pos = 0xb
	// Bit mask of TXERRIE field.
	CEC_IER_TXERRIE_Msk = 0x800
	// Bit TXERRIE.
	CEC_IER_TXERRIE = 0x800
	// Position of TXACKIE field.
	CEC_IER_TXACKIE_Pos = 0xc
	// Bit mask of TXACKIE field.
	CEC_IER_TXACKIE_Msk = 0x1000
	// Bit TXACKIE.
	CEC_IER_TXACKIE = 0x1000
)

// Bitfields for HSEM: HSEM
const (
	// R0: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R0_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R0_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R0_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R0_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R0_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R0_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R0_LOCK = 0x80000000

	// R1: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R1_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R1_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R1_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R1_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R1_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R1_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R1_LOCK = 0x80000000

	// R2: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R2_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R2_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R2_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R2_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R2_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R2_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R2_LOCK = 0x80000000

	// R3: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R3_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R3_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R3_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R3_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R3_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R3_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R3_LOCK = 0x80000000

	// R4: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R4_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R4_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R4_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R4_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R4_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R4_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R4_LOCK = 0x80000000

	// R5: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R5_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R5_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R5_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R5_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R5_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R5_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R5_LOCK = 0x80000000

	// R6: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R6_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R6_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R6_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R6_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R6_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R6_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R6_LOCK = 0x80000000

	// R7: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R7_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R7_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R7_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R7_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R7_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R7_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R7_LOCK = 0x80000000

	// R8: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R8_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R8_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R8_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R8_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R8_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R8_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R8_LOCK = 0x80000000

	// R9: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R9_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R9_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R9_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R9_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R9_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R9_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R9_LOCK = 0x80000000

	// R10: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R10_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R10_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R10_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R10_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R10_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R10_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R10_LOCK = 0x80000000

	// R11: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R11_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R11_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R11_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R11_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R11_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R11_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R11_LOCK = 0x80000000

	// R12: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R12_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R12_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R12_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R12_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R12_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R12_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R12_LOCK = 0x80000000

	// R13: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R13_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R13_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R13_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R13_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R13_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R13_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R13_LOCK = 0x80000000

	// R14: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R14_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R14_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R14_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R14_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R14_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R14_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R14_LOCK = 0x80000000

	// R15: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R15_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R15_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R15_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R15_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R15_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R15_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R15_LOCK = 0x80000000

	// R16: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R16_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R16_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R16_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R16_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R16_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R16_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R16_LOCK = 0x80000000

	// R17: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R17_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R17_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R17_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R17_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R17_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R17_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R17_LOCK = 0x80000000

	// R18: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R18_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R18_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R18_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R18_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R18_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R18_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R18_LOCK = 0x80000000

	// R19: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R19_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R19_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R19_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R19_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R19_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R19_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R19_LOCK = 0x80000000

	// R20: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R20_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R20_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R20_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R20_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R20_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R20_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R20_LOCK = 0x80000000

	// R21: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R21_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R21_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R21_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R21_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R21_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R21_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R21_LOCK = 0x80000000

	// R22: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R22_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R22_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R22_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R22_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R22_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R22_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R22_LOCK = 0x80000000

	// R23: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R23_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R23_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R23_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R23_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R23_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R23_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R23_LOCK = 0x80000000

	// R24: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R24_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R24_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R24_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R24_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R24_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R24_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R24_LOCK = 0x80000000

	// R25: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R25_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R25_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R25_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R25_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R25_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R25_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R25_LOCK = 0x80000000

	// R26: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R26_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R26_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R26_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R26_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R26_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R26_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R26_LOCK = 0x80000000

	// R27: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R27_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R27_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R27_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R27_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R27_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R27_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R27_LOCK = 0x80000000

	// R28: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R28_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R28_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R28_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R28_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R28_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R28_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R28_LOCK = 0x80000000

	// R29: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R29_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R29_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R29_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R29_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R29_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R29_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R29_LOCK = 0x80000000

	// R30: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R30_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R30_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R30_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R30_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R30_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R30_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R30_LOCK = 0x80000000

	// R31: HSEM register HSEM_R0 HSEM_R31
	// Position of PROCID field.
	HSEM_R31_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_R31_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_R31_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_R31_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_R31_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_R31_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_R31_LOCK = 0x80000000

	// RLR0: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR0_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR0_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR0_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR0_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR0_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR0_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR0_LOCK = 0x80000000

	// RLR1: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR1_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR1_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR1_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR1_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR1_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR1_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR1_LOCK = 0x80000000

	// RLR2: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR2_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR2_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR2_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR2_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR2_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR2_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR2_LOCK = 0x80000000

	// RLR3: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR3_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR3_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR3_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR3_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR3_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR3_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR3_LOCK = 0x80000000

	// RLR4: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR4_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR4_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR4_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR4_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR4_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR4_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR4_LOCK = 0x80000000

	// RLR5: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR5_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR5_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR5_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR5_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR5_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR5_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR5_LOCK = 0x80000000

	// RLR6: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR6_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR6_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR6_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR6_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR6_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR6_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR6_LOCK = 0x80000000

	// RLR7: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR7_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR7_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR7_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR7_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR7_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR7_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR7_LOCK = 0x80000000

	// RLR8: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR8_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR8_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR8_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR8_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR8_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR8_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR8_LOCK = 0x80000000

	// RLR9: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR9_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR9_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR9_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR9_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR9_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR9_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR9_LOCK = 0x80000000

	// RLR10: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR10_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR10_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR10_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR10_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR10_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR10_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR10_LOCK = 0x80000000

	// RLR11: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR11_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR11_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR11_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR11_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR11_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR11_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR11_LOCK = 0x80000000

	// RLR12: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR12_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR12_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR12_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR12_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR12_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR12_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR12_LOCK = 0x80000000

	// RLR13: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR13_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR13_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR13_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR13_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR13_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR13_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR13_LOCK = 0x80000000

	// RLR14: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR14_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR14_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR14_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR14_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR14_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR14_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR14_LOCK = 0x80000000

	// RLR15: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR15_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR15_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR15_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR15_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR15_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR15_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR15_LOCK = 0x80000000

	// RLR16: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR16_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR16_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR16_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR16_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR16_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR16_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR16_LOCK = 0x80000000

	// RLR17: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR17_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR17_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR17_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR17_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR17_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR17_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR17_LOCK = 0x80000000

	// RLR18: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR18_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR18_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR18_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR18_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR18_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR18_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR18_LOCK = 0x80000000

	// RLR19: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR19_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR19_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR19_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR19_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR19_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR19_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR19_LOCK = 0x80000000

	// RLR20: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR20_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR20_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR20_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR20_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR20_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR20_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR20_LOCK = 0x80000000

	// RLR21: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR21_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR21_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR21_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR21_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR21_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR21_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR21_LOCK = 0x80000000

	// RLR22: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR22_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR22_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR22_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR22_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR22_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR22_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR22_LOCK = 0x80000000

	// RLR23: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR23_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR23_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR23_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR23_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR23_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR23_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR23_LOCK = 0x80000000

	// RLR24: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR24_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR24_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR24_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR24_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR24_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR24_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR24_LOCK = 0x80000000

	// RLR25: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR25_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR25_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR25_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR25_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR25_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR25_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR25_LOCK = 0x80000000

	// RLR26: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR26_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR26_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR26_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR26_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR26_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR26_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR26_LOCK = 0x80000000

	// RLR27: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR27_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR27_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR27_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR27_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR27_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR27_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR27_LOCK = 0x80000000

	// RLR28: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR28_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR28_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR28_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR28_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR28_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR28_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR28_LOCK = 0x80000000

	// RLR29: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR29_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR29_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR29_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR29_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR29_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR29_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR29_LOCK = 0x80000000

	// RLR30: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR30_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR30_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR30_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR30_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR30_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR30_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR30_LOCK = 0x80000000

	// RLR31: HSEM Read lock register
	// Position of PROCID field.
	HSEM_RLR31_PROCID_Pos = 0x0
	// Bit mask of PROCID field.
	HSEM_RLR31_PROCID_Msk = 0xff
	// Position of MASTERID field.
	HSEM_RLR31_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_RLR31_MASTERID_Msk = 0xff00
	// Position of LOCK field.
	HSEM_RLR31_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	HSEM_RLR31_LOCK_Msk = 0x80000000
	// Bit LOCK.
	HSEM_RLR31_LOCK = 0x80000000

	// IER: HSEM Interrupt enable register
	// Position of ISEM0 field.
	HSEM_IER_ISEM0_Pos = 0x0
	// Bit mask of ISEM0 field.
	HSEM_IER_ISEM0_Msk = 0x1
	// Bit ISEM0.
	HSEM_IER_ISEM0 = 0x1
	// Position of ISEM1 field.
	HSEM_IER_ISEM1_Pos = 0x1
	// Bit mask of ISEM1 field.
	HSEM_IER_ISEM1_Msk = 0x2
	// Bit ISEM1.
	HSEM_IER_ISEM1 = 0x2
	// Position of ISEM2 field.
	HSEM_IER_ISEM2_Pos = 0x2
	// Bit mask of ISEM2 field.
	HSEM_IER_ISEM2_Msk = 0x4
	// Bit ISEM2.
	HSEM_IER_ISEM2 = 0x4
	// Position of ISEM3 field.
	HSEM_IER_ISEM3_Pos = 0x3
	// Bit mask of ISEM3 field.
	HSEM_IER_ISEM3_Msk = 0x8
	// Bit ISEM3.
	HSEM_IER_ISEM3 = 0x8
	// Position of ISEM4 field.
	HSEM_IER_ISEM4_Pos = 0x4
	// Bit mask of ISEM4 field.
	HSEM_IER_ISEM4_Msk = 0x10
	// Bit ISEM4.
	HSEM_IER_ISEM4 = 0x10
	// Position of ISEM5 field.
	HSEM_IER_ISEM5_Pos = 0x5
	// Bit mask of ISEM5 field.
	HSEM_IER_ISEM5_Msk = 0x20
	// Bit ISEM5.
	HSEM_IER_ISEM5 = 0x20
	// Position of ISEM6 field.
	HSEM_IER_ISEM6_Pos = 0x6
	// Bit mask of ISEM6 field.
	HSEM_IER_ISEM6_Msk = 0x40
	// Bit ISEM6.
	HSEM_IER_ISEM6 = 0x40
	// Position of ISEM7 field.
	HSEM_IER_ISEM7_Pos = 0x7
	// Bit mask of ISEM7 field.
	HSEM_IER_ISEM7_Msk = 0x80
	// Bit ISEM7.
	HSEM_IER_ISEM7 = 0x80
	// Position of ISEM8 field.
	HSEM_IER_ISEM8_Pos = 0x8
	// Bit mask of ISEM8 field.
	HSEM_IER_ISEM8_Msk = 0x100
	// Bit ISEM8.
	HSEM_IER_ISEM8 = 0x100
	// Position of ISEM9 field.
	HSEM_IER_ISEM9_Pos = 0x9
	// Bit mask of ISEM9 field.
	HSEM_IER_ISEM9_Msk = 0x200
	// Bit ISEM9.
	HSEM_IER_ISEM9 = 0x200
	// Position of ISEM10 field.
	HSEM_IER_ISEM10_Pos = 0xa
	// Bit mask of ISEM10 field.
	HSEM_IER_ISEM10_Msk = 0x400
	// Bit ISEM10.
	HSEM_IER_ISEM10 = 0x400
	// Position of ISEM11 field.
	HSEM_IER_ISEM11_Pos = 0xb
	// Bit mask of ISEM11 field.
	HSEM_IER_ISEM11_Msk = 0x800
	// Bit ISEM11.
	HSEM_IER_ISEM11 = 0x800
	// Position of ISEM12 field.
	HSEM_IER_ISEM12_Pos = 0xc
	// Bit mask of ISEM12 field.
	HSEM_IER_ISEM12_Msk = 0x1000
	// Bit ISEM12.
	HSEM_IER_ISEM12 = 0x1000
	// Position of ISEM13 field.
	HSEM_IER_ISEM13_Pos = 0xd
	// Bit mask of ISEM13 field.
	HSEM_IER_ISEM13_Msk = 0x2000
	// Bit ISEM13.
	HSEM_IER_ISEM13 = 0x2000
	// Position of ISEM14 field.
	HSEM_IER_ISEM14_Pos = 0xe
	// Bit mask of ISEM14 field.
	HSEM_IER_ISEM14_Msk = 0x4000
	// Bit ISEM14.
	HSEM_IER_ISEM14 = 0x4000
	// Position of ISEM15 field.
	HSEM_IER_ISEM15_Pos = 0xf
	// Bit mask of ISEM15 field.
	HSEM_IER_ISEM15_Msk = 0x8000
	// Bit ISEM15.
	HSEM_IER_ISEM15 = 0x8000
	// Position of ISEM16 field.
	HSEM_IER_ISEM16_Pos = 0x10
	// Bit mask of ISEM16 field.
	HSEM_IER_ISEM16_Msk = 0x10000
	// Bit ISEM16.
	HSEM_IER_ISEM16 = 0x10000
	// Position of ISEM17 field.
	HSEM_IER_ISEM17_Pos = 0x11
	// Bit mask of ISEM17 field.
	HSEM_IER_ISEM17_Msk = 0x20000
	// Bit ISEM17.
	HSEM_IER_ISEM17 = 0x20000
	// Position of ISEM18 field.
	HSEM_IER_ISEM18_Pos = 0x12
	// Bit mask of ISEM18 field.
	HSEM_IER_ISEM18_Msk = 0x40000
	// Bit ISEM18.
	HSEM_IER_ISEM18 = 0x40000
	// Position of ISEM19 field.
	HSEM_IER_ISEM19_Pos = 0x13
	// Bit mask of ISEM19 field.
	HSEM_IER_ISEM19_Msk = 0x80000
	// Bit ISEM19.
	HSEM_IER_ISEM19 = 0x80000
	// Position of ISEM20 field.
	HSEM_IER_ISEM20_Pos = 0x14
	// Bit mask of ISEM20 field.
	HSEM_IER_ISEM20_Msk = 0x100000
	// Bit ISEM20.
	HSEM_IER_ISEM20 = 0x100000
	// Position of ISEM21 field.
	HSEM_IER_ISEM21_Pos = 0x15
	// Bit mask of ISEM21 field.
	HSEM_IER_ISEM21_Msk = 0x200000
	// Bit ISEM21.
	HSEM_IER_ISEM21 = 0x200000
	// Position of ISEM22 field.
	HSEM_IER_ISEM22_Pos = 0x16
	// Bit mask of ISEM22 field.
	HSEM_IER_ISEM22_Msk = 0x400000
	// Bit ISEM22.
	HSEM_IER_ISEM22 = 0x400000
	// Position of ISEM23 field.
	HSEM_IER_ISEM23_Pos = 0x17
	// Bit mask of ISEM23 field.
	HSEM_IER_ISEM23_Msk = 0x800000
	// Bit ISEM23.
	HSEM_IER_ISEM23 = 0x800000
	// Position of ISEM24 field.
	HSEM_IER_ISEM24_Pos = 0x18
	// Bit mask of ISEM24 field.
	HSEM_IER_ISEM24_Msk = 0x1000000
	// Bit ISEM24.
	HSEM_IER_ISEM24 = 0x1000000
	// Position of ISEM25 field.
	HSEM_IER_ISEM25_Pos = 0x19
	// Bit mask of ISEM25 field.
	HSEM_IER_ISEM25_Msk = 0x2000000
	// Bit ISEM25.
	HSEM_IER_ISEM25 = 0x2000000
	// Position of ISEM26 field.
	HSEM_IER_ISEM26_Pos = 0x1a
	// Bit mask of ISEM26 field.
	HSEM_IER_ISEM26_Msk = 0x4000000
	// Bit ISEM26.
	HSEM_IER_ISEM26 = 0x4000000
	// Position of ISEM27 field.
	HSEM_IER_ISEM27_Pos = 0x1b
	// Bit mask of ISEM27 field.
	HSEM_IER_ISEM27_Msk = 0x8000000
	// Bit ISEM27.
	HSEM_IER_ISEM27 = 0x8000000
	// Position of ISEM28 field.
	HSEM_IER_ISEM28_Pos = 0x1c
	// Bit mask of ISEM28 field.
	HSEM_IER_ISEM28_Msk = 0x10000000
	// Bit ISEM28.
	HSEM_IER_ISEM28 = 0x10000000
	// Position of ISEM29 field.
	HSEM_IER_ISEM29_Pos = 0x1d
	// Bit mask of ISEM29 field.
	HSEM_IER_ISEM29_Msk = 0x20000000
	// Bit ISEM29.
	HSEM_IER_ISEM29 = 0x20000000
	// Position of ISEM30 field.
	HSEM_IER_ISEM30_Pos = 0x1e
	// Bit mask of ISEM30 field.
	HSEM_IER_ISEM30_Msk = 0x40000000
	// Bit ISEM30.
	HSEM_IER_ISEM30 = 0x40000000
	// Position of ISEM31 field.
	HSEM_IER_ISEM31_Pos = 0x1f
	// Bit mask of ISEM31 field.
	HSEM_IER_ISEM31_Msk = 0x80000000
	// Bit ISEM31.
	HSEM_IER_ISEM31 = 0x80000000

	// ICR: HSEM Interrupt clear register
	// Position of ISEM0 field.
	HSEM_ICR_ISEM0_Pos = 0x0
	// Bit mask of ISEM0 field.
	HSEM_ICR_ISEM0_Msk = 0x1
	// Bit ISEM0.
	HSEM_ICR_ISEM0 = 0x1
	// Position of ISEM1 field.
	HSEM_ICR_ISEM1_Pos = 0x1
	// Bit mask of ISEM1 field.
	HSEM_ICR_ISEM1_Msk = 0x2
	// Bit ISEM1.
	HSEM_ICR_ISEM1 = 0x2
	// Position of ISEM2 field.
	HSEM_ICR_ISEM2_Pos = 0x2
	// Bit mask of ISEM2 field.
	HSEM_ICR_ISEM2_Msk = 0x4
	// Bit ISEM2.
	HSEM_ICR_ISEM2 = 0x4
	// Position of ISEM3 field.
	HSEM_ICR_ISEM3_Pos = 0x3
	// Bit mask of ISEM3 field.
	HSEM_ICR_ISEM3_Msk = 0x8
	// Bit ISEM3.
	HSEM_ICR_ISEM3 = 0x8
	// Position of ISEM4 field.
	HSEM_ICR_ISEM4_Pos = 0x4
	// Bit mask of ISEM4 field.
	HSEM_ICR_ISEM4_Msk = 0x10
	// Bit ISEM4.
	HSEM_ICR_ISEM4 = 0x10
	// Position of ISEM5 field.
	HSEM_ICR_ISEM5_Pos = 0x5
	// Bit mask of ISEM5 field.
	HSEM_ICR_ISEM5_Msk = 0x20
	// Bit ISEM5.
	HSEM_ICR_ISEM5 = 0x20
	// Position of ISEM6 field.
	HSEM_ICR_ISEM6_Pos = 0x6
	// Bit mask of ISEM6 field.
	HSEM_ICR_ISEM6_Msk = 0x40
	// Bit ISEM6.
	HSEM_ICR_ISEM6 = 0x40
	// Position of ISEM7 field.
	HSEM_ICR_ISEM7_Pos = 0x7
	// Bit mask of ISEM7 field.
	HSEM_ICR_ISEM7_Msk = 0x80
	// Bit ISEM7.
	HSEM_ICR_ISEM7 = 0x80
	// Position of ISEM8 field.
	HSEM_ICR_ISEM8_Pos = 0x8
	// Bit mask of ISEM8 field.
	HSEM_ICR_ISEM8_Msk = 0x100
	// Bit ISEM8.
	HSEM_ICR_ISEM8 = 0x100
	// Position of ISEM9 field.
	HSEM_ICR_ISEM9_Pos = 0x9
	// Bit mask of ISEM9 field.
	HSEM_ICR_ISEM9_Msk = 0x200
	// Bit ISEM9.
	HSEM_ICR_ISEM9 = 0x200
	// Position of ISEM10 field.
	HSEM_ICR_ISEM10_Pos = 0xa
	// Bit mask of ISEM10 field.
	HSEM_ICR_ISEM10_Msk = 0x400
	// Bit ISEM10.
	HSEM_ICR_ISEM10 = 0x400
	// Position of ISEM11 field.
	HSEM_ICR_ISEM11_Pos = 0xb
	// Bit mask of ISEM11 field.
	HSEM_ICR_ISEM11_Msk = 0x800
	// Bit ISEM11.
	HSEM_ICR_ISEM11 = 0x800
	// Position of ISEM12 field.
	HSEM_ICR_ISEM12_Pos = 0xc
	// Bit mask of ISEM12 field.
	HSEM_ICR_ISEM12_Msk = 0x1000
	// Bit ISEM12.
	HSEM_ICR_ISEM12 = 0x1000
	// Position of ISEM13 field.
	HSEM_ICR_ISEM13_Pos = 0xd
	// Bit mask of ISEM13 field.
	HSEM_ICR_ISEM13_Msk = 0x2000
	// Bit ISEM13.
	HSEM_ICR_ISEM13 = 0x2000
	// Position of ISEM14 field.
	HSEM_ICR_ISEM14_Pos = 0xe
	// Bit mask of ISEM14 field.
	HSEM_ICR_ISEM14_Msk = 0x4000
	// Bit ISEM14.
	HSEM_ICR_ISEM14 = 0x4000
	// Position of ISEM15 field.
	HSEM_ICR_ISEM15_Pos = 0xf
	// Bit mask of ISEM15 field.
	HSEM_ICR_ISEM15_Msk = 0x8000
	// Bit ISEM15.
	HSEM_ICR_ISEM15 = 0x8000
	// Position of ISEM16 field.
	HSEM_ICR_ISEM16_Pos = 0x10
	// Bit mask of ISEM16 field.
	HSEM_ICR_ISEM16_Msk = 0x10000
	// Bit ISEM16.
	HSEM_ICR_ISEM16 = 0x10000
	// Position of ISEM17 field.
	HSEM_ICR_ISEM17_Pos = 0x11
	// Bit mask of ISEM17 field.
	HSEM_ICR_ISEM17_Msk = 0x20000
	// Bit ISEM17.
	HSEM_ICR_ISEM17 = 0x20000
	// Position of ISEM18 field.
	HSEM_ICR_ISEM18_Pos = 0x12
	// Bit mask of ISEM18 field.
	HSEM_ICR_ISEM18_Msk = 0x40000
	// Bit ISEM18.
	HSEM_ICR_ISEM18 = 0x40000
	// Position of ISEM19 field.
	HSEM_ICR_ISEM19_Pos = 0x13
	// Bit mask of ISEM19 field.
	HSEM_ICR_ISEM19_Msk = 0x80000
	// Bit ISEM19.
	HSEM_ICR_ISEM19 = 0x80000
	// Position of ISEM20 field.
	HSEM_ICR_ISEM20_Pos = 0x14
	// Bit mask of ISEM20 field.
	HSEM_ICR_ISEM20_Msk = 0x100000
	// Bit ISEM20.
	HSEM_ICR_ISEM20 = 0x100000
	// Position of ISEM21 field.
	HSEM_ICR_ISEM21_Pos = 0x15
	// Bit mask of ISEM21 field.
	HSEM_ICR_ISEM21_Msk = 0x200000
	// Bit ISEM21.
	HSEM_ICR_ISEM21 = 0x200000
	// Position of ISEM22 field.
	HSEM_ICR_ISEM22_Pos = 0x16
	// Bit mask of ISEM22 field.
	HSEM_ICR_ISEM22_Msk = 0x400000
	// Bit ISEM22.
	HSEM_ICR_ISEM22 = 0x400000
	// Position of ISEM23 field.
	HSEM_ICR_ISEM23_Pos = 0x17
	// Bit mask of ISEM23 field.
	HSEM_ICR_ISEM23_Msk = 0x800000
	// Bit ISEM23.
	HSEM_ICR_ISEM23 = 0x800000
	// Position of ISEM24 field.
	HSEM_ICR_ISEM24_Pos = 0x18
	// Bit mask of ISEM24 field.
	HSEM_ICR_ISEM24_Msk = 0x1000000
	// Bit ISEM24.
	HSEM_ICR_ISEM24 = 0x1000000
	// Position of ISEM25 field.
	HSEM_ICR_ISEM25_Pos = 0x19
	// Bit mask of ISEM25 field.
	HSEM_ICR_ISEM25_Msk = 0x2000000
	// Bit ISEM25.
	HSEM_ICR_ISEM25 = 0x2000000
	// Position of ISEM26 field.
	HSEM_ICR_ISEM26_Pos = 0x1a
	// Bit mask of ISEM26 field.
	HSEM_ICR_ISEM26_Msk = 0x4000000
	// Bit ISEM26.
	HSEM_ICR_ISEM26 = 0x4000000
	// Position of ISEM27 field.
	HSEM_ICR_ISEM27_Pos = 0x1b
	// Bit mask of ISEM27 field.
	HSEM_ICR_ISEM27_Msk = 0x8000000
	// Bit ISEM27.
	HSEM_ICR_ISEM27 = 0x8000000
	// Position of ISEM28 field.
	HSEM_ICR_ISEM28_Pos = 0x1c
	// Bit mask of ISEM28 field.
	HSEM_ICR_ISEM28_Msk = 0x10000000
	// Bit ISEM28.
	HSEM_ICR_ISEM28 = 0x10000000
	// Position of ISEM29 field.
	HSEM_ICR_ISEM29_Pos = 0x1d
	// Bit mask of ISEM29 field.
	HSEM_ICR_ISEM29_Msk = 0x20000000
	// Bit ISEM29.
	HSEM_ICR_ISEM29 = 0x20000000
	// Position of ISEM30 field.
	HSEM_ICR_ISEM30_Pos = 0x1e
	// Bit mask of ISEM30 field.
	HSEM_ICR_ISEM30_Msk = 0x40000000
	// Bit ISEM30.
	HSEM_ICR_ISEM30 = 0x40000000
	// Position of ISEM31 field.
	HSEM_ICR_ISEM31_Pos = 0x1f
	// Bit mask of ISEM31 field.
	HSEM_ICR_ISEM31_Msk = 0x80000000
	// Bit ISEM31.
	HSEM_ICR_ISEM31 = 0x80000000

	// ISR: HSEM Interrupt status register
	// Position of ISEM0 field.
	HSEM_ISR_ISEM0_Pos = 0x0
	// Bit mask of ISEM0 field.
	HSEM_ISR_ISEM0_Msk = 0x1
	// Bit ISEM0.
	HSEM_ISR_ISEM0 = 0x1
	// Position of ISEM1 field.
	HSEM_ISR_ISEM1_Pos = 0x1
	// Bit mask of ISEM1 field.
	HSEM_ISR_ISEM1_Msk = 0x2
	// Bit ISEM1.
	HSEM_ISR_ISEM1 = 0x2
	// Position of ISEM2 field.
	HSEM_ISR_ISEM2_Pos = 0x2
	// Bit mask of ISEM2 field.
	HSEM_ISR_ISEM2_Msk = 0x4
	// Bit ISEM2.
	HSEM_ISR_ISEM2 = 0x4
	// Position of ISEM3 field.
	HSEM_ISR_ISEM3_Pos = 0x3
	// Bit mask of ISEM3 field.
	HSEM_ISR_ISEM3_Msk = 0x8
	// Bit ISEM3.
	HSEM_ISR_ISEM3 = 0x8
	// Position of ISEM4 field.
	HSEM_ISR_ISEM4_Pos = 0x4
	// Bit mask of ISEM4 field.
	HSEM_ISR_ISEM4_Msk = 0x10
	// Bit ISEM4.
	HSEM_ISR_ISEM4 = 0x10
	// Position of ISEM5 field.
	HSEM_ISR_ISEM5_Pos = 0x5
	// Bit mask of ISEM5 field.
	HSEM_ISR_ISEM5_Msk = 0x20
	// Bit ISEM5.
	HSEM_ISR_ISEM5 = 0x20
	// Position of ISEM6 field.
	HSEM_ISR_ISEM6_Pos = 0x6
	// Bit mask of ISEM6 field.
	HSEM_ISR_ISEM6_Msk = 0x40
	// Bit ISEM6.
	HSEM_ISR_ISEM6 = 0x40
	// Position of ISEM7 field.
	HSEM_ISR_ISEM7_Pos = 0x7
	// Bit mask of ISEM7 field.
	HSEM_ISR_ISEM7_Msk = 0x80
	// Bit ISEM7.
	HSEM_ISR_ISEM7 = 0x80
	// Position of ISEM8 field.
	HSEM_ISR_ISEM8_Pos = 0x8
	// Bit mask of ISEM8 field.
	HSEM_ISR_ISEM8_Msk = 0x100
	// Bit ISEM8.
	HSEM_ISR_ISEM8 = 0x100
	// Position of ISEM9 field.
	HSEM_ISR_ISEM9_Pos = 0x9
	// Bit mask of ISEM9 field.
	HSEM_ISR_ISEM9_Msk = 0x200
	// Bit ISEM9.
	HSEM_ISR_ISEM9 = 0x200
	// Position of ISEM10 field.
	HSEM_ISR_ISEM10_Pos = 0xa
	// Bit mask of ISEM10 field.
	HSEM_ISR_ISEM10_Msk = 0x400
	// Bit ISEM10.
	HSEM_ISR_ISEM10 = 0x400
	// Position of ISEM11 field.
	HSEM_ISR_ISEM11_Pos = 0xb
	// Bit mask of ISEM11 field.
	HSEM_ISR_ISEM11_Msk = 0x800
	// Bit ISEM11.
	HSEM_ISR_ISEM11 = 0x800
	// Position of ISEM12 field.
	HSEM_ISR_ISEM12_Pos = 0xc
	// Bit mask of ISEM12 field.
	HSEM_ISR_ISEM12_Msk = 0x1000
	// Bit ISEM12.
	HSEM_ISR_ISEM12 = 0x1000
	// Position of ISEM13 field.
	HSEM_ISR_ISEM13_Pos = 0xd
	// Bit mask of ISEM13 field.
	HSEM_ISR_ISEM13_Msk = 0x2000
	// Bit ISEM13.
	HSEM_ISR_ISEM13 = 0x2000
	// Position of ISEM14 field.
	HSEM_ISR_ISEM14_Pos = 0xe
	// Bit mask of ISEM14 field.
	HSEM_ISR_ISEM14_Msk = 0x4000
	// Bit ISEM14.
	HSEM_ISR_ISEM14 = 0x4000
	// Position of ISEM15 field.
	HSEM_ISR_ISEM15_Pos = 0xf
	// Bit mask of ISEM15 field.
	HSEM_ISR_ISEM15_Msk = 0x8000
	// Bit ISEM15.
	HSEM_ISR_ISEM15 = 0x8000
	// Position of ISEM16 field.
	HSEM_ISR_ISEM16_Pos = 0x10
	// Bit mask of ISEM16 field.
	HSEM_ISR_ISEM16_Msk = 0x10000
	// Bit ISEM16.
	HSEM_ISR_ISEM16 = 0x10000
	// Position of ISEM17 field.
	HSEM_ISR_ISEM17_Pos = 0x11
	// Bit mask of ISEM17 field.
	HSEM_ISR_ISEM17_Msk = 0x20000
	// Bit ISEM17.
	HSEM_ISR_ISEM17 = 0x20000
	// Position of ISEM18 field.
	HSEM_ISR_ISEM18_Pos = 0x12
	// Bit mask of ISEM18 field.
	HSEM_ISR_ISEM18_Msk = 0x40000
	// Bit ISEM18.
	HSEM_ISR_ISEM18 = 0x40000
	// Position of ISEM19 field.
	HSEM_ISR_ISEM19_Pos = 0x13
	// Bit mask of ISEM19 field.
	HSEM_ISR_ISEM19_Msk = 0x80000
	// Bit ISEM19.
	HSEM_ISR_ISEM19 = 0x80000
	// Position of ISEM20 field.
	HSEM_ISR_ISEM20_Pos = 0x14
	// Bit mask of ISEM20 field.
	HSEM_ISR_ISEM20_Msk = 0x100000
	// Bit ISEM20.
	HSEM_ISR_ISEM20 = 0x100000
	// Position of ISEM21 field.
	HSEM_ISR_ISEM21_Pos = 0x15
	// Bit mask of ISEM21 field.
	HSEM_ISR_ISEM21_Msk = 0x200000
	// Bit ISEM21.
	HSEM_ISR_ISEM21 = 0x200000
	// Position of ISEM22 field.
	HSEM_ISR_ISEM22_Pos = 0x16
	// Bit mask of ISEM22 field.
	HSEM_ISR_ISEM22_Msk = 0x400000
	// Bit ISEM22.
	HSEM_ISR_ISEM22 = 0x400000
	// Position of ISEM23 field.
	HSEM_ISR_ISEM23_Pos = 0x17
	// Bit mask of ISEM23 field.
	HSEM_ISR_ISEM23_Msk = 0x800000
	// Bit ISEM23.
	HSEM_ISR_ISEM23 = 0x800000
	// Position of ISEM24 field.
	HSEM_ISR_ISEM24_Pos = 0x18
	// Bit mask of ISEM24 field.
	HSEM_ISR_ISEM24_Msk = 0x1000000
	// Bit ISEM24.
	HSEM_ISR_ISEM24 = 0x1000000
	// Position of ISEM25 field.
	HSEM_ISR_ISEM25_Pos = 0x19
	// Bit mask of ISEM25 field.
	HSEM_ISR_ISEM25_Msk = 0x2000000
	// Bit ISEM25.
	HSEM_ISR_ISEM25 = 0x2000000
	// Position of ISEM26 field.
	HSEM_ISR_ISEM26_Pos = 0x1a
	// Bit mask of ISEM26 field.
	HSEM_ISR_ISEM26_Msk = 0x4000000
	// Bit ISEM26.
	HSEM_ISR_ISEM26 = 0x4000000
	// Position of ISEM27 field.
	HSEM_ISR_ISEM27_Pos = 0x1b
	// Bit mask of ISEM27 field.
	HSEM_ISR_ISEM27_Msk = 0x8000000
	// Bit ISEM27.
	HSEM_ISR_ISEM27 = 0x8000000
	// Position of ISEM28 field.
	HSEM_ISR_ISEM28_Pos = 0x1c
	// Bit mask of ISEM28 field.
	HSEM_ISR_ISEM28_Msk = 0x10000000
	// Bit ISEM28.
	HSEM_ISR_ISEM28 = 0x10000000
	// Position of ISEM29 field.
	HSEM_ISR_ISEM29_Pos = 0x1d
	// Bit mask of ISEM29 field.
	HSEM_ISR_ISEM29_Msk = 0x20000000
	// Bit ISEM29.
	HSEM_ISR_ISEM29 = 0x20000000
	// Position of ISEM30 field.
	HSEM_ISR_ISEM30_Pos = 0x1e
	// Bit mask of ISEM30 field.
	HSEM_ISR_ISEM30_Msk = 0x40000000
	// Bit ISEM30.
	HSEM_ISR_ISEM30 = 0x40000000
	// Position of ISEM31 field.
	HSEM_ISR_ISEM31_Pos = 0x1f
	// Bit mask of ISEM31 field.
	HSEM_ISR_ISEM31_Msk = 0x80000000
	// Bit ISEM31.
	HSEM_ISR_ISEM31 = 0x80000000

	// MISR: HSEM Masked interrupt status register
	// Position of ISEM0 field.
	HSEM_MISR_ISEM0_Pos = 0x0
	// Bit mask of ISEM0 field.
	HSEM_MISR_ISEM0_Msk = 0x1
	// Bit ISEM0.
	HSEM_MISR_ISEM0 = 0x1
	// Position of ISEM1 field.
	HSEM_MISR_ISEM1_Pos = 0x1
	// Bit mask of ISEM1 field.
	HSEM_MISR_ISEM1_Msk = 0x2
	// Bit ISEM1.
	HSEM_MISR_ISEM1 = 0x2
	// Position of ISEM2 field.
	HSEM_MISR_ISEM2_Pos = 0x2
	// Bit mask of ISEM2 field.
	HSEM_MISR_ISEM2_Msk = 0x4
	// Bit ISEM2.
	HSEM_MISR_ISEM2 = 0x4
	// Position of ISEM3 field.
	HSEM_MISR_ISEM3_Pos = 0x3
	// Bit mask of ISEM3 field.
	HSEM_MISR_ISEM3_Msk = 0x8
	// Bit ISEM3.
	HSEM_MISR_ISEM3 = 0x8
	// Position of ISEM4 field.
	HSEM_MISR_ISEM4_Pos = 0x4
	// Bit mask of ISEM4 field.
	HSEM_MISR_ISEM4_Msk = 0x10
	// Bit ISEM4.
	HSEM_MISR_ISEM4 = 0x10
	// Position of ISEM5 field.
	HSEM_MISR_ISEM5_Pos = 0x5
	// Bit mask of ISEM5 field.
	HSEM_MISR_ISEM5_Msk = 0x20
	// Bit ISEM5.
	HSEM_MISR_ISEM5 = 0x20
	// Position of ISEM6 field.
	HSEM_MISR_ISEM6_Pos = 0x6
	// Bit mask of ISEM6 field.
	HSEM_MISR_ISEM6_Msk = 0x40
	// Bit ISEM6.
	HSEM_MISR_ISEM6 = 0x40
	// Position of ISEM7 field.
	HSEM_MISR_ISEM7_Pos = 0x7
	// Bit mask of ISEM7 field.
	HSEM_MISR_ISEM7_Msk = 0x80
	// Bit ISEM7.
	HSEM_MISR_ISEM7 = 0x80
	// Position of ISEM8 field.
	HSEM_MISR_ISEM8_Pos = 0x8
	// Bit mask of ISEM8 field.
	HSEM_MISR_ISEM8_Msk = 0x100
	// Bit ISEM8.
	HSEM_MISR_ISEM8 = 0x100
	// Position of ISEM9 field.
	HSEM_MISR_ISEM9_Pos = 0x9
	// Bit mask of ISEM9 field.
	HSEM_MISR_ISEM9_Msk = 0x200
	// Bit ISEM9.
	HSEM_MISR_ISEM9 = 0x200
	// Position of ISEM10 field.
	HSEM_MISR_ISEM10_Pos = 0xa
	// Bit mask of ISEM10 field.
	HSEM_MISR_ISEM10_Msk = 0x400
	// Bit ISEM10.
	HSEM_MISR_ISEM10 = 0x400
	// Position of ISEM11 field.
	HSEM_MISR_ISEM11_Pos = 0xb
	// Bit mask of ISEM11 field.
	HSEM_MISR_ISEM11_Msk = 0x800
	// Bit ISEM11.
	HSEM_MISR_ISEM11 = 0x800
	// Position of ISEM12 field.
	HSEM_MISR_ISEM12_Pos = 0xc
	// Bit mask of ISEM12 field.
	HSEM_MISR_ISEM12_Msk = 0x1000
	// Bit ISEM12.
	HSEM_MISR_ISEM12 = 0x1000
	// Position of ISEM13 field.
	HSEM_MISR_ISEM13_Pos = 0xd
	// Bit mask of ISEM13 field.
	HSEM_MISR_ISEM13_Msk = 0x2000
	// Bit ISEM13.
	HSEM_MISR_ISEM13 = 0x2000
	// Position of ISEM14 field.
	HSEM_MISR_ISEM14_Pos = 0xe
	// Bit mask of ISEM14 field.
	HSEM_MISR_ISEM14_Msk = 0x4000
	// Bit ISEM14.
	HSEM_MISR_ISEM14 = 0x4000
	// Position of ISEM15 field.
	HSEM_MISR_ISEM15_Pos = 0xf
	// Bit mask of ISEM15 field.
	HSEM_MISR_ISEM15_Msk = 0x8000
	// Bit ISEM15.
	HSEM_MISR_ISEM15 = 0x8000
	// Position of ISEM16 field.
	HSEM_MISR_ISEM16_Pos = 0x10
	// Bit mask of ISEM16 field.
	HSEM_MISR_ISEM16_Msk = 0x10000
	// Bit ISEM16.
	HSEM_MISR_ISEM16 = 0x10000
	// Position of ISEM17 field.
	HSEM_MISR_ISEM17_Pos = 0x11
	// Bit mask of ISEM17 field.
	HSEM_MISR_ISEM17_Msk = 0x20000
	// Bit ISEM17.
	HSEM_MISR_ISEM17 = 0x20000
	// Position of ISEM18 field.
	HSEM_MISR_ISEM18_Pos = 0x12
	// Bit mask of ISEM18 field.
	HSEM_MISR_ISEM18_Msk = 0x40000
	// Bit ISEM18.
	HSEM_MISR_ISEM18 = 0x40000
	// Position of ISEM19 field.
	HSEM_MISR_ISEM19_Pos = 0x13
	// Bit mask of ISEM19 field.
	HSEM_MISR_ISEM19_Msk = 0x80000
	// Bit ISEM19.
	HSEM_MISR_ISEM19 = 0x80000
	// Position of ISEM20 field.
	HSEM_MISR_ISEM20_Pos = 0x14
	// Bit mask of ISEM20 field.
	HSEM_MISR_ISEM20_Msk = 0x100000
	// Bit ISEM20.
	HSEM_MISR_ISEM20 = 0x100000
	// Position of ISEM21 field.
	HSEM_MISR_ISEM21_Pos = 0x15
	// Bit mask of ISEM21 field.
	HSEM_MISR_ISEM21_Msk = 0x200000
	// Bit ISEM21.
	HSEM_MISR_ISEM21 = 0x200000
	// Position of ISEM22 field.
	HSEM_MISR_ISEM22_Pos = 0x16
	// Bit mask of ISEM22 field.
	HSEM_MISR_ISEM22_Msk = 0x400000
	// Bit ISEM22.
	HSEM_MISR_ISEM22 = 0x400000
	// Position of ISEM23 field.
	HSEM_MISR_ISEM23_Pos = 0x17
	// Bit mask of ISEM23 field.
	HSEM_MISR_ISEM23_Msk = 0x800000
	// Bit ISEM23.
	HSEM_MISR_ISEM23 = 0x800000
	// Position of ISEM24 field.
	HSEM_MISR_ISEM24_Pos = 0x18
	// Bit mask of ISEM24 field.
	HSEM_MISR_ISEM24_Msk = 0x1000000
	// Bit ISEM24.
	HSEM_MISR_ISEM24 = 0x1000000
	// Position of ISEM25 field.
	HSEM_MISR_ISEM25_Pos = 0x19
	// Bit mask of ISEM25 field.
	HSEM_MISR_ISEM25_Msk = 0x2000000
	// Bit ISEM25.
	HSEM_MISR_ISEM25 = 0x2000000
	// Position of ISEM26 field.
	HSEM_MISR_ISEM26_Pos = 0x1a
	// Bit mask of ISEM26 field.
	HSEM_MISR_ISEM26_Msk = 0x4000000
	// Bit ISEM26.
	HSEM_MISR_ISEM26 = 0x4000000
	// Position of ISEM27 field.
	HSEM_MISR_ISEM27_Pos = 0x1b
	// Bit mask of ISEM27 field.
	HSEM_MISR_ISEM27_Msk = 0x8000000
	// Bit ISEM27.
	HSEM_MISR_ISEM27 = 0x8000000
	// Position of ISEM28 field.
	HSEM_MISR_ISEM28_Pos = 0x1c
	// Bit mask of ISEM28 field.
	HSEM_MISR_ISEM28_Msk = 0x10000000
	// Bit ISEM28.
	HSEM_MISR_ISEM28 = 0x10000000
	// Position of ISEM29 field.
	HSEM_MISR_ISEM29_Pos = 0x1d
	// Bit mask of ISEM29 field.
	HSEM_MISR_ISEM29_Msk = 0x20000000
	// Bit ISEM29.
	HSEM_MISR_ISEM29 = 0x20000000
	// Position of ISEM30 field.
	HSEM_MISR_ISEM30_Pos = 0x1e
	// Bit mask of ISEM30 field.
	HSEM_MISR_ISEM30_Msk = 0x40000000
	// Bit ISEM30.
	HSEM_MISR_ISEM30 = 0x40000000
	// Position of ISEM31 field.
	HSEM_MISR_ISEM31_Pos = 0x1f
	// Bit mask of ISEM31 field.
	HSEM_MISR_ISEM31_Msk = 0x80000000
	// Bit ISEM31.
	HSEM_MISR_ISEM31 = 0x80000000

	// CR: HSEM Clear register
	// Position of MASTERID field.
	HSEM_CR_MASTERID_Pos = 0x8
	// Bit mask of MASTERID field.
	HSEM_CR_MASTERID_Msk = 0xff00
	// Position of KEY field.
	HSEM_CR_KEY_Pos = 0x10
	// Bit mask of KEY field.
	HSEM_CR_KEY_Msk = 0xffff0000

	// KEYR: HSEM Interrupt clear register
	// Position of KEY field.
	HSEM_KEYR_KEY_Pos = 0x10
	// Bit mask of KEY field.
	HSEM_KEYR_KEY_Msk = 0xffff0000
)

// Bitfields for I2C1: I2C
const (
	// CR1: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
	// Position of PE field.
	I2C_CR1_PE_Pos = 0x0
	// Bit mask of PE field.
	I2C_CR1_PE_Msk = 0x1
	// Bit PE.
	I2C_CR1_PE = 0x1
	// Peripheral disabled
	I2C_CR1_PE_Disabled = 0x0
	// Peripheral enabled
	I2C_CR1_PE_Enabled = 0x1
	// Position of TXIE field.
	I2C_CR1_TXIE_Pos = 0x1
	// Bit mask of TXIE field.
	I2C_CR1_TXIE_Msk = 0x2
	// Bit TXIE.
	I2C_CR1_TXIE = 0x2
	// Transmit (TXIS) interrupt disabled
	I2C_CR1_TXIE_Disabled = 0x0
	// Transmit (TXIS) interrupt enabled
	I2C_CR1_TXIE_Enabled = 0x1
	// Position of RXIE field.
	I2C_CR1_RXIE_Pos = 0x2
	// Bit mask of RXIE field.
	I2C_CR1_RXIE_Msk = 0x4
	// Bit RXIE.
	I2C_CR1_RXIE = 0x4
	// Receive (RXNE) interrupt disabled
	I2C_CR1_RXIE_Disabled = 0x0
	// Receive (RXNE) interrupt enabled
	I2C_CR1_RXIE_Enabled = 0x1
	// Position of ADDRIE field.
	I2C_CR1_ADDRIE_Pos = 0x3
	// Bit mask of ADDRIE field.
	I2C_CR1_ADDRIE_Msk = 0x8
	// Bit ADDRIE.
	I2C_CR1_ADDRIE = 0x8
	// Address match (ADDR) interrupts disabled
	I2C_CR1_ADDRIE_Disabled = 0x0
	// Address match (ADDR) interrupts enabled
	I2C_CR1_ADDRIE_Enabled = 0x1
	// Position of NACKIE field.
	I2C_CR1_NACKIE_Pos = 0x4
	// Bit mask of NACKIE field.
	I2C_CR1_NACKIE_Msk = 0x10
	// Bit NACKIE.
	I2C_CR1_NACKIE = 0x10
	// Not acknowledge (NACKF) received interrupts disabled
	I2C_CR1_NACKIE_Disabled = 0x0
	// Not acknowledge (NACKF) received interrupts enabled
	I2C_CR1_NACKIE_Enabled = 0x1
	// Position of STOPIE field.
	I2C_CR1_STOPIE_Pos = 0x5
	// Bit mask of STOPIE field.
	I2C_CR1_STOPIE_Msk = 0x20
	// Bit STOPIE.
	I2C_CR1_STOPIE = 0x20
	// Stop detection (STOPF) interrupt disabled
	I2C_CR1_STOPIE_Disabled = 0x0
	// Stop detection (STOPF) interrupt enabled
	I2C_CR1_STOPIE_Enabled = 0x1
	// Position of TCIE field.
	I2C_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	I2C_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	I2C_CR1_TCIE = 0x40
	// Transfer Complete interrupt disabled
	I2C_CR1_TCIE_Disabled = 0x0
	// Transfer Complete interrupt enabled
	I2C_CR1_TCIE_Enabled = 0x1
	// Position of ERRIE field.
	I2C_CR1_ERRIE_Pos = 0x7
	// Bit mask of ERRIE field.
	I2C_CR1_ERRIE_Msk = 0x80
	// Bit ERRIE.
	I2C_CR1_ERRIE = 0x80
	// Error detection interrupts disabled
	I2C_CR1_ERRIE_Disabled = 0x0
	// Error detection interrupts enabled
	I2C_CR1_ERRIE_Enabled = 0x1
	// Position of DNF field.
	I2C_CR1_DNF_Pos = 0x8
	// Bit mask of DNF field.
	I2C_CR1_DNF_Msk = 0xf00
	// Digital filter disabled
	I2C_CR1_DNF_NoFilter = 0x0
	// Digital filter enabled and filtering capability up to 1 tI2CCLK
	I2C_CR1_DNF_Filter1 = 0x1
	// Digital filter enabled and filtering capability up to 2 tI2CCLK
	I2C_CR1_DNF_Filter2 = 0x2
	// Digital filter enabled and filtering capability up to 3 tI2CCLK
	I2C_CR1_DNF_Filter3 = 0x3
	// Digital filter enabled and filtering capability up to 4 tI2CCLK
	I2C_CR1_DNF_Filter4 = 0x4
	// Digital filter enabled and filtering capability up to 5 tI2CCLK
	I2C_CR1_DNF_Filter5 = 0x5
	// Digital filter enabled and filtering capability up to 6 tI2CCLK
	I2C_CR1_DNF_Filter6 = 0x6
	// Digital filter enabled and filtering capability up to 7 tI2CCLK
	I2C_CR1_DNF_Filter7 = 0x7
	// Digital filter enabled and filtering capability up to 8 tI2CCLK
	I2C_CR1_DNF_Filter8 = 0x8
	// Digital filter enabled and filtering capability up to 9 tI2CCLK
	I2C_CR1_DNF_Filter9 = 0x9
	// Digital filter enabled and filtering capability up to 10 tI2CCLK
	I2C_CR1_DNF_Filter10 = 0xa
	// Digital filter enabled and filtering capability up to 11 tI2CCLK
	I2C_CR1_DNF_Filter11 = 0xb
	// Digital filter enabled and filtering capability up to 12 tI2CCLK
	I2C_CR1_DNF_Filter12 = 0xc
	// Digital filter enabled and filtering capability up to 13 tI2CCLK
	I2C_CR1_DNF_Filter13 = 0xd
	// Digital filter enabled and filtering capability up to 14 tI2CCLK
	I2C_CR1_DNF_Filter14 = 0xe
	// Digital filter enabled and filtering capability up to 15 tI2CCLK
	I2C_CR1_DNF_Filter15 = 0xf
	// Position of ANFOFF field.
	I2C_CR1_ANFOFF_Pos = 0xc
	// Bit mask of ANFOFF field.
	I2C_CR1_ANFOFF_Msk = 0x1000
	// Bit ANFOFF.
	I2C_CR1_ANFOFF = 0x1000
	// Analog noise filter enabled
	I2C_CR1_ANFOFF_Enabled = 0x0
	// Analog noise filter disabled
	I2C_CR1_ANFOFF_Disabled = 0x1
	// Position of TXDMAEN field.
	I2C_CR1_TXDMAEN_Pos = 0xe
	// Bit mask of TXDMAEN field.
	I2C_CR1_TXDMAEN_Msk = 0x4000
	// Bit TXDMAEN.
	I2C_CR1_TXDMAEN = 0x4000
	// DMA mode disabled for transmission
	I2C_CR1_TXDMAEN_Disabled = 0x0
	// DMA mode enabled for transmission
	I2C_CR1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	I2C_CR1_RXDMAEN_Pos = 0xf
	// Bit mask of RXDMAEN field.
	I2C_CR1_RXDMAEN_Msk = 0x8000
	// Bit RXDMAEN.
	I2C_CR1_RXDMAEN = 0x8000
	// DMA mode disabled for reception
	I2C_CR1_RXDMAEN_Disabled = 0x0
	// DMA mode enabled for reception
	I2C_CR1_RXDMAEN_Enabled = 0x1
	// Position of SBC field.
	I2C_CR1_SBC_Pos = 0x10
	// Bit mask of SBC field.
	I2C_CR1_SBC_Msk = 0x10000
	// Bit SBC.
	I2C_CR1_SBC = 0x10000
	// Slave byte control disabled
	I2C_CR1_SBC_Disabled = 0x0
	// Slave byte control enabled
	I2C_CR1_SBC_Enabled = 0x1
	// Position of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Pos = 0x11
	// Bit mask of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Msk = 0x20000
	// Bit NOSTRETCH.
	I2C_CR1_NOSTRETCH = 0x20000
	// Clock stretching enabled
	I2C_CR1_NOSTRETCH_Enabled = 0x0
	// Clock stretching disabled
	I2C_CR1_NOSTRETCH_Disabled = 0x1
	// Position of WUPEN field.
	I2C_CR1_WUPEN_Pos = 0x12
	// Bit mask of WUPEN field.
	I2C_CR1_WUPEN_Msk = 0x40000
	// Bit WUPEN.
	I2C_CR1_WUPEN = 0x40000
	// Wakeup from Stop mode disabled
	I2C_CR1_WUPEN_Disabled = 0x0
	// Wakeup from Stop mode enabled
	I2C_CR1_WUPEN_Enabled = 0x1
	// Position of GCEN field.
	I2C_CR1_GCEN_Pos = 0x13
	// Bit mask of GCEN field.
	I2C_CR1_GCEN_Msk = 0x80000
	// Bit GCEN.
	I2C_CR1_GCEN = 0x80000
	// General call disabled. Address 0b00000000 is NACKed
	I2C_CR1_GCEN_Disabled = 0x0
	// General call enabled. Address 0b00000000 is ACKed
	I2C_CR1_GCEN_Enabled = 0x1
	// Position of SMBHEN field.
	I2C_CR1_SMBHEN_Pos = 0x14
	// Bit mask of SMBHEN field.
	I2C_CR1_SMBHEN_Msk = 0x100000
	// Bit SMBHEN.
	I2C_CR1_SMBHEN = 0x100000
	// Host address disabled. Address 0b0001000x is NACKed
	I2C_CR1_SMBHEN_Disabled = 0x0
	// Host address enabled. Address 0b0001000x is ACKed
	I2C_CR1_SMBHEN_Enabled = 0x1
	// Position of SMBDEN field.
	I2C_CR1_SMBDEN_Pos = 0x15
	// Bit mask of SMBDEN field.
	I2C_CR1_SMBDEN_Msk = 0x200000
	// Bit SMBDEN.
	I2C_CR1_SMBDEN = 0x200000
	// Device default address disabled. Address 0b1100001x is NACKed
	I2C_CR1_SMBDEN_Disabled = 0x0
	// Device default address enabled. Address 0b1100001x is ACKed
	I2C_CR1_SMBDEN_Enabled = 0x1
	// Position of ALERTEN field.
	I2C_CR1_ALERTEN_Pos = 0x16
	// Bit mask of ALERTEN field.
	I2C_CR1_ALERTEN_Msk = 0x400000
	// Bit ALERTEN.
	I2C_CR1_ALERTEN = 0x400000
	// In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
	I2C_CR1_ALERTEN_Disabled = 0x0
	// In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
	I2C_CR1_ALERTEN_Enabled = 0x1
	// Position of PECEN field.
	I2C_CR1_PECEN_Pos = 0x17
	// Bit mask of PECEN field.
	I2C_CR1_PECEN_Msk = 0x800000
	// Bit PECEN.
	I2C_CR1_PECEN = 0x800000
	// PEC calculation disabled
	I2C_CR1_PECEN_Disabled = 0x0
	// PEC calculation enabled
	I2C_CR1_PECEN_Enabled = 0x1

	// CR2: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
	// Position of RD_WRN field.
	I2C_CR2_RD_WRN_Pos = 0xa
	// Bit mask of RD_WRN field.
	I2C_CR2_RD_WRN_Msk = 0x400
	// Bit RD_WRN.
	I2C_CR2_RD_WRN = 0x400
	// Master requests a write transfer
	I2C_CR2_RD_WRN_Write = 0x0
	// Master requests a read transfer
	I2C_CR2_RD_WRN_Read = 0x1
	// Position of ADD10 field.
	I2C_CR2_ADD10_Pos = 0xb
	// Bit mask of ADD10 field.
	I2C_CR2_ADD10_Msk = 0x800
	// Bit ADD10.
	I2C_CR2_ADD10 = 0x800
	// The master operates in 7-bit addressing mode
	I2C_CR2_ADD10_Bit7 = 0x0
	// The master operates in 10-bit addressing mode
	I2C_CR2_ADD10_Bit10 = 0x1
	// Position of HEAD10R field.
	I2C_CR2_HEAD10R_Pos = 0xc
	// Bit mask of HEAD10R field.
	I2C_CR2_HEAD10R_Msk = 0x1000
	// Bit HEAD10R.
	I2C_CR2_HEAD10R = 0x1000
	// The master sends the complete 10 bit slave address read sequence
	I2C_CR2_HEAD10R_Complete = 0x0
	// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
	I2C_CR2_HEAD10R_Partial = 0x1
	// Position of START field.
	I2C_CR2_START_Pos = 0xd
	// Bit mask of START field.
	I2C_CR2_START_Msk = 0x2000
	// Bit START.
	I2C_CR2_START = 0x2000
	// No Start generation
	I2C_CR2_START_NoStart = 0x0
	// Restart/Start generation
	I2C_CR2_START_Start = 0x1
	// Position of STOP field.
	I2C_CR2_STOP_Pos = 0xe
	// Bit mask of STOP field.
	I2C_CR2_STOP_Msk = 0x4000
	// Bit STOP.
	I2C_CR2_STOP = 0x4000
	// No Stop generation
	I2C_CR2_STOP_NoStop = 0x0
	// Stop generation after current byte transfer
	I2C_CR2_STOP_Stop = 0x1
	// Position of NACK field.
	I2C_CR2_NACK_Pos = 0xf
	// Bit mask of NACK field.
	I2C_CR2_NACK_Msk = 0x8000
	// Bit NACK.
	I2C_CR2_NACK = 0x8000
	// an ACK is sent after current received byte
	I2C_CR2_NACK_Ack = 0x0
	// a NACK is sent after current received byte
	I2C_CR2_NACK_Nack = 0x1
	// Position of NBYTES field.
	I2C_CR2_NBYTES_Pos = 0x10
	// Bit mask of NBYTES field.
	I2C_CR2_NBYTES_Msk = 0xff0000
	// Position of RELOAD field.
	I2C_CR2_RELOAD_Pos = 0x18
	// Bit mask of RELOAD field.
	I2C_CR2_RELOAD_Msk = 0x1000000
	// Bit RELOAD.
	I2C_CR2_RELOAD = 0x1000000
	// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
	I2C_CR2_RELOAD_Completed = 0x0
	// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
	I2C_CR2_RELOAD_NotCompleted = 0x1
	// Position of AUTOEND field.
	I2C_CR2_AUTOEND_Pos = 0x19
	// Bit mask of AUTOEND field.
	I2C_CR2_AUTOEND_Msk = 0x2000000
	// Bit AUTOEND.
	I2C_CR2_AUTOEND = 0x2000000
	// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
	I2C_CR2_AUTOEND_Software = 0x0
	// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
	I2C_CR2_AUTOEND_Automatic = 0x1
	// Position of PECBYTE field.
	I2C_CR2_PECBYTE_Pos = 0x1a
	// Bit mask of PECBYTE field.
	I2C_CR2_PECBYTE_Msk = 0x4000000
	// Bit PECBYTE.
	I2C_CR2_PECBYTE = 0x4000000
	// No PEC transfer
	I2C_CR2_PECBYTE_NoPec = 0x0
	// PEC transmission/reception is requested
	I2C_CR2_PECBYTE_Pec = 0x1
	// Position of SADD field.
	I2C_CR2_SADD_Pos = 0x0
	// Bit mask of SADD field.
	I2C_CR2_SADD_Msk = 0x3ff

	// OAR1: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
	// Position of OA1 field.
	I2C_OAR1_OA1_Pos = 0x0
	// Bit mask of OA1 field.
	I2C_OAR1_OA1_Msk = 0x3ff
	// Position of OA1MODE field.
	I2C_OAR1_OA1MODE_Pos = 0xa
	// Bit mask of OA1MODE field.
	I2C_OAR1_OA1MODE_Msk = 0x400
	// Bit OA1MODE.
	I2C_OAR1_OA1MODE = 0x400
	// Own address 1 is a 7-bit address
	I2C_OAR1_OA1MODE_Bit7 = 0x0
	// Own address 1 is a 10-bit address
	I2C_OAR1_OA1MODE_Bit10 = 0x1
	// Position of OA1EN field.
	I2C_OAR1_OA1EN_Pos = 0xf
	// Bit mask of OA1EN field.
	I2C_OAR1_OA1EN_Msk = 0x8000
	// Bit OA1EN.
	I2C_OAR1_OA1EN = 0x8000
	// Own address 1 disabled. The received slave address OA1 is NACKed
	I2C_OAR1_OA1EN_Disabled = 0x0
	// Own address 1 enabled. The received slave address OA1 is ACKed
	I2C_OAR1_OA1EN_Enabled = 0x1

	// OAR2: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
	// Position of OA2 field.
	I2C_OAR2_OA2_Pos = 0x1
	// Bit mask of OA2 field.
	I2C_OAR2_OA2_Msk = 0xfe
	// Position of OA2MSK field.
	I2C_OAR2_OA2MSK_Pos = 0x8
	// Bit mask of OA2MSK field.
	I2C_OAR2_OA2MSK_Msk = 0x700
	// No mask
	I2C_OAR2_OA2MSK_NoMask = 0x0
	// OA2[1] is masked and don’t care. Only OA2[7:2] are compared
	I2C_OAR2_OA2MSK_Mask1 = 0x1
	// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
	I2C_OAR2_OA2MSK_Mask2 = 0x2
	// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
	I2C_OAR2_OA2MSK_Mask3 = 0x3
	// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
	I2C_OAR2_OA2MSK_Mask4 = 0x4
	// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
	I2C_OAR2_OA2MSK_Mask5 = 0x5
	// OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
	I2C_OAR2_OA2MSK_Mask6 = 0x6
	// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
	I2C_OAR2_OA2MSK_Mask7 = 0x7
	// Position of OA2EN field.
	I2C_OAR2_OA2EN_Pos = 0xf
	// Bit mask of OA2EN field.
	I2C_OAR2_OA2EN_Msk = 0x8000
	// Bit OA2EN.
	I2C_OAR2_OA2EN = 0x8000
	// Own address 2 disabled. The received slave address OA2 is NACKed
	I2C_OAR2_OA2EN_Disabled = 0x0
	// Own address 2 enabled. The received slave address OA2 is ACKed
	I2C_OAR2_OA2EN_Enabled = 0x1

	// TIMINGR: Access: No wait states
	// Position of SCLL field.
	I2C_TIMINGR_SCLL_Pos = 0x0
	// Bit mask of SCLL field.
	I2C_TIMINGR_SCLL_Msk = 0xff
	// Position of SCLH field.
	I2C_TIMINGR_SCLH_Pos = 0x8
	// Bit mask of SCLH field.
	I2C_TIMINGR_SCLH_Msk = 0xff00
	// Position of SDADEL field.
	I2C_TIMINGR_SDADEL_Pos = 0x10
	// Bit mask of SDADEL field.
	I2C_TIMINGR_SDADEL_Msk = 0xf0000
	// Position of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Pos = 0x14
	// Bit mask of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Msk = 0xf00000
	// Position of PRESC field.
	I2C_TIMINGR_PRESC_Pos = 0x1c
	// Bit mask of PRESC field.
	I2C_TIMINGR_PRESC_Msk = 0xf0000000

	// TIMEOUTR: Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
	// Position of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0
	// Bit mask of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff
	// Position of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Pos = 0xc
	// Bit mask of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Msk = 0x1000
	// Bit TIDLE.
	I2C_TIMEOUTR_TIDLE = 0x1000
	// TIMEOUTA is used to detect SCL low timeout
	I2C_TIMEOUTR_TIDLE_Disabled = 0x0
	// TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
	I2C_TIMEOUTR_TIDLE_Enabled = 0x1
	// Position of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf
	// Bit mask of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000
	// Bit TIMOUTEN.
	I2C_TIMEOUTR_TIMOUTEN = 0x8000
	// SCL timeout detection is disabled
	I2C_TIMEOUTR_TIMOUTEN_Disabled = 0x0
	// SCL timeout detection is enabled
	I2C_TIMEOUTR_TIMOUTEN_Enabled = 0x1
	// Position of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10
	// Bit mask of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000
	// Position of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Pos = 0x1f
	// Bit mask of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Msk = 0x80000000
	// Bit TEXTEN.
	I2C_TIMEOUTR_TEXTEN = 0x80000000
	// Extended clock timeout detection is disabled
	I2C_TIMEOUTR_TEXTEN_Disabled = 0x0
	// Extended clock timeout detection is enabled
	I2C_TIMEOUTR_TEXTEN_Enabled = 0x1

	// ISR: Access: No wait states
	// Position of TXE field.
	I2C_ISR_TXE_Pos = 0x0
	// Bit mask of TXE field.
	I2C_ISR_TXE_Msk = 0x1
	// Bit TXE.
	I2C_ISR_TXE = 0x1
	// TXDR register not empty
	I2C_ISR_TXE_NotEmpty = 0x0
	// TXDR register empty
	I2C_ISR_TXE_Empty = 0x1
	// Position of TXIS field.
	I2C_ISR_TXIS_Pos = 0x1
	// Bit mask of TXIS field.
	I2C_ISR_TXIS_Msk = 0x2
	// Bit TXIS.
	I2C_ISR_TXIS = 0x2
	// The TXDR register is not empty
	I2C_ISR_TXIS_NotEmpty = 0x0
	// The TXDR register is empty and the data to be transmitted must be written in the TXDR register
	I2C_ISR_TXIS_Empty = 0x1
	// Position of RXNE field.
	I2C_ISR_RXNE_Pos = 0x2
	// Bit mask of RXNE field.
	I2C_ISR_RXNE_Msk = 0x4
	// Bit RXNE.
	I2C_ISR_RXNE = 0x4
	// The RXDR register is empty
	I2C_ISR_RXNE_Empty = 0x0
	// Received data is copied into the RXDR register, and is ready to be read
	I2C_ISR_RXNE_NotEmpty = 0x1
	// Position of ADDR field.
	I2C_ISR_ADDR_Pos = 0x3
	// Bit mask of ADDR field.
	I2C_ISR_ADDR_Msk = 0x8
	// Bit ADDR.
	I2C_ISR_ADDR = 0x8
	// Adress mismatched or not received
	I2C_ISR_ADDR_NotMatch = 0x0
	// Received slave address matched with one of the enabled slave addresses
	I2C_ISR_ADDR_Match = 0x1
	// Position of NACKF field.
	I2C_ISR_NACKF_Pos = 0x4
	// Bit mask of NACKF field.
	I2C_ISR_NACKF_Msk = 0x10
	// Bit NACKF.
	I2C_ISR_NACKF = 0x10
	// No NACK has been received
	I2C_ISR_NACKF_NoNack = 0x0
	// NACK has been received
	I2C_ISR_NACKF_Nack = 0x1
	// Position of STOPF field.
	I2C_ISR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	I2C_ISR_STOPF_Msk = 0x20
	// Bit STOPF.
	I2C_ISR_STOPF = 0x20
	// No Stop condition detected
	I2C_ISR_STOPF_NoStop = 0x0
	// Stop condition detected
	I2C_ISR_STOPF_Stop = 0x1
	// Position of TC field.
	I2C_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	I2C_ISR_TC_Msk = 0x40
	// Bit TC.
	I2C_ISR_TC = 0x40
	// Transfer is not complete
	I2C_ISR_TC_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TC_Complete = 0x1
	// Position of TCR field.
	I2C_ISR_TCR_Pos = 0x7
	// Bit mask of TCR field.
	I2C_ISR_TCR_Msk = 0x80
	// Bit TCR.
	I2C_ISR_TCR = 0x80
	// Transfer is not complete
	I2C_ISR_TCR_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TCR_Complete = 0x1
	// Position of BERR field.
	I2C_ISR_BERR_Pos = 0x8
	// Bit mask of BERR field.
	I2C_ISR_BERR_Msk = 0x100
	// Bit BERR.
	I2C_ISR_BERR = 0x100
	// No bus error
	I2C_ISR_BERR_NoError = 0x0
	// Misplaced Start and Stop condition is detected
	I2C_ISR_BERR_Error = 0x1
	// Position of ARLO field.
	I2C_ISR_ARLO_Pos = 0x9
	// Bit mask of ARLO field.
	I2C_ISR_ARLO_Msk = 0x200
	// Bit ARLO.
	I2C_ISR_ARLO = 0x200
	// No arbitration lost
	I2C_ISR_ARLO_NotLost = 0x0
	// Arbitration lost
	I2C_ISR_ARLO_Lost = 0x1
	// Position of OVR field.
	I2C_ISR_OVR_Pos = 0xa
	// Bit mask of OVR field.
	I2C_ISR_OVR_Msk = 0x400
	// Bit OVR.
	I2C_ISR_OVR = 0x400
	// No overrun/underrun error occurs
	I2C_ISR_OVR_NoOverrun = 0x0
	// slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
	I2C_ISR_OVR_Overrun = 0x1
	// Position of PECERR field.
	I2C_ISR_PECERR_Pos = 0xb
	// Bit mask of PECERR field.
	I2C_ISR_PECERR_Msk = 0x800
	// Bit PECERR.
	I2C_ISR_PECERR = 0x800
	// Received PEC does match with PEC register
	I2C_ISR_PECERR_Match = 0x0
	// Received PEC does not match with PEC register
	I2C_ISR_PECERR_NoMatch = 0x1
	// Position of TIMEOUT field.
	I2C_ISR_TIMEOUT_Pos = 0xc
	// Bit mask of TIMEOUT field.
	I2C_ISR_TIMEOUT_Msk = 0x1000
	// Bit TIMEOUT.
	I2C_ISR_TIMEOUT = 0x1000
	// No timeout occured
	I2C_ISR_TIMEOUT_NoTimeout = 0x0
	// Timeout occured
	I2C_ISR_TIMEOUT_Timeout = 0x1
	// Position of ALERT field.
	I2C_ISR_ALERT_Pos = 0xd
	// Bit mask of ALERT field.
	I2C_ISR_ALERT_Msk = 0x2000
	// Bit ALERT.
	I2C_ISR_ALERT = 0x2000
	// SMBA alert is not detected
	I2C_ISR_ALERT_NoAlert = 0x0
	// SMBA alert event is detected on SMBA pin
	I2C_ISR_ALERT_Alert = 0x1
	// Position of BUSY field.
	I2C_ISR_BUSY_Pos = 0xf
	// Bit mask of BUSY field.
	I2C_ISR_BUSY_Msk = 0x8000
	// Bit BUSY.
	I2C_ISR_BUSY = 0x8000
	// No communication is in progress on the bus
	I2C_ISR_BUSY_NotBusy = 0x0
	// A communication is in progress on the bus
	I2C_ISR_BUSY_Busy = 0x1
	// Position of DIR field.
	I2C_ISR_DIR_Pos = 0x10
	// Bit mask of DIR field.
	I2C_ISR_DIR_Msk = 0x10000
	// Bit DIR.
	I2C_ISR_DIR = 0x10000
	// Write transfer, slave enters receiver mode
	I2C_ISR_DIR_Write = 0x0
	// Read transfer, slave enters transmitter mode
	I2C_ISR_DIR_Read = 0x1
	// Position of ADDCODE field.
	I2C_ISR_ADDCODE_Pos = 0x11
	// Bit mask of ADDCODE field.
	I2C_ISR_ADDCODE_Msk = 0xfe0000

	// ICR: Access: No wait states
	// Position of ADDRCF field.
	I2C_ICR_ADDRCF_Pos = 0x3
	// Bit mask of ADDRCF field.
	I2C_ICR_ADDRCF_Msk = 0x8
	// Bit ADDRCF.
	I2C_ICR_ADDRCF = 0x8
	// Clears the ADDR flag in ISR register
	I2C_ICR_ADDRCF_Clear = 0x1
	// Position of NACKCF field.
	I2C_ICR_NACKCF_Pos = 0x4
	// Bit mask of NACKCF field.
	I2C_ICR_NACKCF_Msk = 0x10
	// Bit NACKCF.
	I2C_ICR_NACKCF = 0x10
	// Clears the NACK flag in ISR register
	I2C_ICR_NACKCF_Clear = 0x1
	// Position of STOPCF field.
	I2C_ICR_STOPCF_Pos = 0x5
	// Bit mask of STOPCF field.
	I2C_ICR_STOPCF_Msk = 0x20
	// Bit STOPCF.
	I2C_ICR_STOPCF = 0x20
	// Clears the STOP flag in ISR register
	I2C_ICR_STOPCF_Clear = 0x1
	// Position of BERRCF field.
	I2C_ICR_BERRCF_Pos = 0x8
	// Bit mask of BERRCF field.
	I2C_ICR_BERRCF_Msk = 0x100
	// Bit BERRCF.
	I2C_ICR_BERRCF = 0x100
	// Clears the BERR flag in ISR register
	I2C_ICR_BERRCF_Clear = 0x1
	// Position of ARLOCF field.
	I2C_ICR_ARLOCF_Pos = 0x9
	// Bit mask of ARLOCF field.
	I2C_ICR_ARLOCF_Msk = 0x200
	// Bit ARLOCF.
	I2C_ICR_ARLOCF = 0x200
	// Clears the ARLO flag in ISR register
	I2C_ICR_ARLOCF_Clear = 0x1
	// Position of OVRCF field.
	I2C_ICR_OVRCF_Pos = 0xa
	// Bit mask of OVRCF field.
	I2C_ICR_OVRCF_Msk = 0x400
	// Bit OVRCF.
	I2C_ICR_OVRCF = 0x400
	// Clears the OVR flag in ISR register
	I2C_ICR_OVRCF_Clear = 0x1
	// Position of PECCF field.
	I2C_ICR_PECCF_Pos = 0xb
	// Bit mask of PECCF field.
	I2C_ICR_PECCF_Msk = 0x800
	// Bit PECCF.
	I2C_ICR_PECCF = 0x800
	// Clears the PEC flag in ISR register
	I2C_ICR_PECCF_Clear = 0x1
	// Position of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Pos = 0xc
	// Bit mask of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Msk = 0x1000
	// Bit TIMOUTCF.
	I2C_ICR_TIMOUTCF = 0x1000
	// Clears the TIMOUT flag in ISR register
	I2C_ICR_TIMOUTCF_Clear = 0x1
	// Position of ALERTCF field.
	I2C_ICR_ALERTCF_Pos = 0xd
	// Bit mask of ALERTCF field.
	I2C_ICR_ALERTCF_Msk = 0x2000
	// Bit ALERTCF.
	I2C_ICR_ALERTCF = 0x2000
	// Clears the ALERT flag in ISR register
	I2C_ICR_ALERTCF_Clear = 0x1

	// PECR: Access: No wait states
	// Position of PEC field.
	I2C_PECR_PEC_Pos = 0x0
	// Bit mask of PEC field.
	I2C_PECR_PEC_Msk = 0xff

	// RXDR: Access: No wait states
	// Position of RXDATA field.
	I2C_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	I2C_RXDR_RXDATA_Msk = 0xff

	// TXDR: Access: No wait states
	// Position of TXDATA field.
	I2C_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	I2C_TXDR_TXDATA_Msk = 0xff
)

// Bitfields for GPIOA: GPIO
const (
	// MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIO_MODER_MODER0_Pos = 0x0
	// Bit mask of MODER0 field.
	GPIO_MODER_MODER0_Msk = 0x3
	// Input mode (reset state)
	GPIO_MODER_MODER0_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER0_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER0_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER0_Analog = 0x3
	// Position of MODER1 field.
	GPIO_MODER_MODER1_Pos = 0x2
	// Bit mask of MODER1 field.
	GPIO_MODER_MODER1_Msk = 0xc
	// Input mode (reset state)
	GPIO_MODER_MODER1_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER1_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER1_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER1_Analog = 0x3
	// Position of MODER2 field.
	GPIO_MODER_MODER2_Pos = 0x4
	// Bit mask of MODER2 field.
	GPIO_MODER_MODER2_Msk = 0x30
	// Input mode (reset state)
	GPIO_MODER_MODER2_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER2_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER2_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER2_Analog = 0x3
	// Position of MODER3 field.
	GPIO_MODER_MODER3_Pos = 0x6
	// Bit mask of MODER3 field.
	GPIO_MODER_MODER3_Msk = 0xc0
	// Input mode (reset state)
	GPIO_MODER_MODER3_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER3_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER3_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER3_Analog = 0x3
	// Position of MODER4 field.
	GPIO_MODER_MODER4_Pos = 0x8
	// Bit mask of MODER4 field.
	GPIO_MODER_MODER4_Msk = 0x300
	// Input mode (reset state)
	GPIO_MODER_MODER4_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER4_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER4_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER4_Analog = 0x3
	// Position of MODER5 field.
	GPIO_MODER_MODER5_Pos = 0xa
	// Bit mask of MODER5 field.
	GPIO_MODER_MODER5_Msk = 0xc00
	// Input mode (reset state)
	GPIO_MODER_MODER5_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER5_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER5_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER5_Analog = 0x3
	// Position of MODER6 field.
	GPIO_MODER_MODER6_Pos = 0xc
	// Bit mask of MODER6 field.
	GPIO_MODER_MODER6_Msk = 0x3000
	// Input mode (reset state)
	GPIO_MODER_MODER6_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER6_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER6_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER6_Analog = 0x3
	// Position of MODER7 field.
	GPIO_MODER_MODER7_Pos = 0xe
	// Bit mask of MODER7 field.
	GPIO_MODER_MODER7_Msk = 0xc000
	// Input mode (reset state)
	GPIO_MODER_MODER7_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER7_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER7_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER7_Analog = 0x3
	// Position of MODER8 field.
	GPIO_MODER_MODER8_Pos = 0x10
	// Bit mask of MODER8 field.
	GPIO_MODER_MODER8_Msk = 0x30000
	// Input mode (reset state)
	GPIO_MODER_MODER8_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER8_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER8_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER8_Analog = 0x3
	// Position of MODER9 field.
	GPIO_MODER_MODER9_Pos = 0x12
	// Bit mask of MODER9 field.
	GPIO_MODER_MODER9_Msk = 0xc0000
	// Input mode (reset state)
	GPIO_MODER_MODER9_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER9_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER9_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER9_Analog = 0x3
	// Position of MODER10 field.
	GPIO_MODER_MODER10_Pos = 0x14
	// Bit mask of MODER10 field.
	GPIO_MODER_MODER10_Msk = 0x300000
	// Input mode (reset state)
	GPIO_MODER_MODER10_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER10_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER10_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER10_Analog = 0x3
	// Position of MODER11 field.
	GPIO_MODER_MODER11_Pos = 0x16
	// Bit mask of MODER11 field.
	GPIO_MODER_MODER11_Msk = 0xc00000
	// Input mode (reset state)
	GPIO_MODER_MODER11_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER11_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER11_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER11_Analog = 0x3
	// Position of MODER12 field.
	GPIO_MODER_MODER12_Pos = 0x18
	// Bit mask of MODER12 field.
	GPIO_MODER_MODER12_Msk = 0x3000000
	// Input mode (reset state)
	GPIO_MODER_MODER12_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER12_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER12_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER12_Analog = 0x3
	// Position of MODER13 field.
	GPIO_MODER_MODER13_Pos = 0x1a
	// Bit mask of MODER13 field.
	GPIO_MODER_MODER13_Msk = 0xc000000
	// Input mode (reset state)
	GPIO_MODER_MODER13_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER13_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER13_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER13_Analog = 0x3
	// Position of MODER14 field.
	GPIO_MODER_MODER14_Pos = 0x1c
	// Bit mask of MODER14 field.
	GPIO_MODER_MODER14_Msk = 0x30000000
	// Input mode (reset state)
	GPIO_MODER_MODER14_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER14_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER14_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER14_Analog = 0x3
	// Position of MODER15 field.
	GPIO_MODER_MODER15_Pos = 0x1e
	// Bit mask of MODER15 field.
	GPIO_MODER_MODER15_Msk = 0xc0000000
	// Input mode (reset state)
	GPIO_MODER_MODER15_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER15_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER15_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER15_Analog = 0x3

	// OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIO_OTYPER_OT0_Pos = 0x0
	// Bit mask of OT0 field.
	GPIO_OTYPER_OT0_Msk = 0x1
	// Bit OT0.
	GPIO_OTYPER_OT0 = 0x1
	// Output push-pull (reset state)
	GPIO_OTYPER_OT0_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT0_OpenDrain = 0x1
	// Position of OT1 field.
	GPIO_OTYPER_OT1_Pos = 0x1
	// Bit mask of OT1 field.
	GPIO_OTYPER_OT1_Msk = 0x2
	// Bit OT1.
	GPIO_OTYPER_OT1 = 0x2
	// Output push-pull (reset state)
	GPIO_OTYPER_OT1_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT1_OpenDrain = 0x1
	// Position of OT2 field.
	GPIO_OTYPER_OT2_Pos = 0x2
	// Bit mask of OT2 field.
	GPIO_OTYPER_OT2_Msk = 0x4
	// Bit OT2.
	GPIO_OTYPER_OT2 = 0x4
	// Output push-pull (reset state)
	GPIO_OTYPER_OT2_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT2_OpenDrain = 0x1
	// Position of OT3 field.
	GPIO_OTYPER_OT3_Pos = 0x3
	// Bit mask of OT3 field.
	GPIO_OTYPER_OT3_Msk = 0x8
	// Bit OT3.
	GPIO_OTYPER_OT3 = 0x8
	// Output push-pull (reset state)
	GPIO_OTYPER_OT3_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT3_OpenDrain = 0x1
	// Position of OT4 field.
	GPIO_OTYPER_OT4_Pos = 0x4
	// Bit mask of OT4 field.
	GPIO_OTYPER_OT4_Msk = 0x10
	// Bit OT4.
	GPIO_OTYPER_OT4 = 0x10
	// Output push-pull (reset state)
	GPIO_OTYPER_OT4_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT4_OpenDrain = 0x1
	// Position of OT5 field.
	GPIO_OTYPER_OT5_Pos = 0x5
	// Bit mask of OT5 field.
	GPIO_OTYPER_OT5_Msk = 0x20
	// Bit OT5.
	GPIO_OTYPER_OT5 = 0x20
	// Output push-pull (reset state)
	GPIO_OTYPER_OT5_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT5_OpenDrain = 0x1
	// Position of OT6 field.
	GPIO_OTYPER_OT6_Pos = 0x6
	// Bit mask of OT6 field.
	GPIO_OTYPER_OT6_Msk = 0x40
	// Bit OT6.
	GPIO_OTYPER_OT6 = 0x40
	// Output push-pull (reset state)
	GPIO_OTYPER_OT6_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT6_OpenDrain = 0x1
	// Position of OT7 field.
	GPIO_OTYPER_OT7_Pos = 0x7
	// Bit mask of OT7 field.
	GPIO_OTYPER_OT7_Msk = 0x80
	// Bit OT7.
	GPIO_OTYPER_OT7 = 0x80
	// Output push-pull (reset state)
	GPIO_OTYPER_OT7_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT7_OpenDrain = 0x1
	// Position of OT8 field.
	GPIO_OTYPER_OT8_Pos = 0x8
	// Bit mask of OT8 field.
	GPIO_OTYPER_OT8_Msk = 0x100
	// Bit OT8.
	GPIO_OTYPER_OT8 = 0x100
	// Output push-pull (reset state)
	GPIO_OTYPER_OT8_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT8_OpenDrain = 0x1
	// Position of OT9 field.
	GPIO_OTYPER_OT9_Pos = 0x9
	// Bit mask of OT9 field.
	GPIO_OTYPER_OT9_Msk = 0x200
	// Bit OT9.
	GPIO_OTYPER_OT9 = 0x200
	// Output push-pull (reset state)
	GPIO_OTYPER_OT9_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT9_OpenDrain = 0x1
	// Position of OT10 field.
	GPIO_OTYPER_OT10_Pos = 0xa
	// Bit mask of OT10 field.
	GPIO_OTYPER_OT10_Msk = 0x400
	// Bit OT10.
	GPIO_OTYPER_OT10 = 0x400
	// Output push-pull (reset state)
	GPIO_OTYPER_OT10_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT10_OpenDrain = 0x1
	// Position of OT11 field.
	GPIO_OTYPER_OT11_Pos = 0xb
	// Bit mask of OT11 field.
	GPIO_OTYPER_OT11_Msk = 0x800
	// Bit OT11.
	GPIO_OTYPER_OT11 = 0x800
	// Output push-pull (reset state)
	GPIO_OTYPER_OT11_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT11_OpenDrain = 0x1
	// Position of OT12 field.
	GPIO_OTYPER_OT12_Pos = 0xc
	// Bit mask of OT12 field.
	GPIO_OTYPER_OT12_Msk = 0x1000
	// Bit OT12.
	GPIO_OTYPER_OT12 = 0x1000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT12_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT12_OpenDrain = 0x1
	// Position of OT13 field.
	GPIO_OTYPER_OT13_Pos = 0xd
	// Bit mask of OT13 field.
	GPIO_OTYPER_OT13_Msk = 0x2000
	// Bit OT13.
	GPIO_OTYPER_OT13 = 0x2000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT13_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT13_OpenDrain = 0x1
	// Position of OT14 field.
	GPIO_OTYPER_OT14_Pos = 0xe
	// Bit mask of OT14 field.
	GPIO_OTYPER_OT14_Msk = 0x4000
	// Bit OT14.
	GPIO_OTYPER_OT14 = 0x4000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT14_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT14_OpenDrain = 0x1
	// Position of OT15 field.
	GPIO_OTYPER_OT15_Pos = 0xf
	// Bit mask of OT15 field.
	GPIO_OTYPER_OT15_Msk = 0x8000
	// Bit OT15.
	GPIO_OTYPER_OT15 = 0x8000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT15_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT15_OpenDrain = 0x1

	// OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIO_OSPEEDR_OSPEEDR0_Pos = 0x0
	// Bit mask of OSPEEDR0 field.
	GPIO_OSPEEDR_OSPEEDR0_Msk = 0x3
	// Low speed
	GPIO_OSPEEDR_OSPEEDR0_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR0_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR0_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR0_VeryHighSpeed = 0x3
	// Position of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR1_Pos = 0x2
	// Bit mask of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR1_Msk = 0xc
	// Low speed
	GPIO_OSPEEDR_OSPEEDR1_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR1_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR1_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR1_VeryHighSpeed = 0x3
	// Position of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR2_Pos = 0x4
	// Bit mask of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR2_Msk = 0x30
	// Low speed
	GPIO_OSPEEDR_OSPEEDR2_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR2_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR2_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR2_VeryHighSpeed = 0x3
	// Position of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR3_Pos = 0x6
	// Bit mask of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR3_Msk = 0xc0
	// Low speed
	GPIO_OSPEEDR_OSPEEDR3_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR3_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR3_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR3_VeryHighSpeed = 0x3
	// Position of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR4_Pos = 0x8
	// Bit mask of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR4_Msk = 0x300
	// Low speed
	GPIO_OSPEEDR_OSPEEDR4_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR4_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR4_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR4_VeryHighSpeed = 0x3
	// Position of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR5_Pos = 0xa
	// Bit mask of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR5_Msk = 0xc00
	// Low speed
	GPIO_OSPEEDR_OSPEEDR5_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR5_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR5_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR5_VeryHighSpeed = 0x3
	// Position of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR6_Pos = 0xc
	// Bit mask of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR6_Msk = 0x3000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR6_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR6_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR6_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR6_VeryHighSpeed = 0x3
	// Position of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR7_Pos = 0xe
	// Bit mask of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR7_Msk = 0xc000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR7_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR7_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR7_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR7_VeryHighSpeed = 0x3
	// Position of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR8_Pos = 0x10
	// Bit mask of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR8_Msk = 0x30000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR8_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR8_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR8_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR8_VeryHighSpeed = 0x3
	// Position of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR9_Pos = 0x12
	// Bit mask of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR9_Msk = 0xc0000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR9_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR9_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR9_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR9_VeryHighSpeed = 0x3
	// Position of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR10_Pos = 0x14
	// Bit mask of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR10_Msk = 0x300000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR10_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR10_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR10_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR10_VeryHighSpeed = 0x3
	// Position of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR11_Pos = 0x16
	// Bit mask of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR11_Msk = 0xc00000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR11_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR11_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR11_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR11_VeryHighSpeed = 0x3
	// Position of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR12_Pos = 0x18
	// Bit mask of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR12_Msk = 0x3000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR12_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR12_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR12_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR12_VeryHighSpeed = 0x3
	// Position of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR13_Pos = 0x1a
	// Bit mask of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR13_Msk = 0xc000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR13_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR13_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR13_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR13_VeryHighSpeed = 0x3
	// Position of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR14_Pos = 0x1c
	// Bit mask of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR14_Msk = 0x30000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR14_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR14_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR14_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR14_VeryHighSpeed = 0x3
	// Position of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR15_Pos = 0x1e
	// Bit mask of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR15_Msk = 0xc0000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR15_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR15_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR15_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR15_VeryHighSpeed = 0x3

	// PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIO_PUPDR_PUPDR0_Pos = 0x0
	// Bit mask of PUPDR0 field.
	GPIO_PUPDR_PUPDR0_Msk = 0x3
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR0_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR0_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR0_PullDown = 0x2
	// Position of PUPDR1 field.
	GPIO_PUPDR_PUPDR1_Pos = 0x2
	// Bit mask of PUPDR1 field.
	GPIO_PUPDR_PUPDR1_Msk = 0xc
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR1_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR1_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR1_PullDown = 0x2
	// Position of PUPDR2 field.
	GPIO_PUPDR_PUPDR2_Pos = 0x4
	// Bit mask of PUPDR2 field.
	GPIO_PUPDR_PUPDR2_Msk = 0x30
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR2_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR2_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR2_PullDown = 0x2
	// Position of PUPDR3 field.
	GPIO_PUPDR_PUPDR3_Pos = 0x6
	// Bit mask of PUPDR3 field.
	GPIO_PUPDR_PUPDR3_Msk = 0xc0
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR3_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR3_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR3_PullDown = 0x2
	// Position of PUPDR4 field.
	GPIO_PUPDR_PUPDR4_Pos = 0x8
	// Bit mask of PUPDR4 field.
	GPIO_PUPDR_PUPDR4_Msk = 0x300
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR4_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR4_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR4_PullDown = 0x2
	// Position of PUPDR5 field.
	GPIO_PUPDR_PUPDR5_Pos = 0xa
	// Bit mask of PUPDR5 field.
	GPIO_PUPDR_PUPDR5_Msk = 0xc00
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR5_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR5_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR5_PullDown = 0x2
	// Position of PUPDR6 field.
	GPIO_PUPDR_PUPDR6_Pos = 0xc
	// Bit mask of PUPDR6 field.
	GPIO_PUPDR_PUPDR6_Msk = 0x3000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR6_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR6_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR6_PullDown = 0x2
	// Position of PUPDR7 field.
	GPIO_PUPDR_PUPDR7_Pos = 0xe
	// Bit mask of PUPDR7 field.
	GPIO_PUPDR_PUPDR7_Msk = 0xc000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR7_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR7_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR7_PullDown = 0x2
	// Position of PUPDR8 field.
	GPIO_PUPDR_PUPDR8_Pos = 0x10
	// Bit mask of PUPDR8 field.
	GPIO_PUPDR_PUPDR8_Msk = 0x30000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR8_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR8_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR8_PullDown = 0x2
	// Position of PUPDR9 field.
	GPIO_PUPDR_PUPDR9_Pos = 0x12
	// Bit mask of PUPDR9 field.
	GPIO_PUPDR_PUPDR9_Msk = 0xc0000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR9_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR9_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR9_PullDown = 0x2
	// Position of PUPDR10 field.
	GPIO_PUPDR_PUPDR10_Pos = 0x14
	// Bit mask of PUPDR10 field.
	GPIO_PUPDR_PUPDR10_Msk = 0x300000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR10_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR10_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR10_PullDown = 0x2
	// Position of PUPDR11 field.
	GPIO_PUPDR_PUPDR11_Pos = 0x16
	// Bit mask of PUPDR11 field.
	GPIO_PUPDR_PUPDR11_Msk = 0xc00000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR11_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR11_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR11_PullDown = 0x2
	// Position of PUPDR12 field.
	GPIO_PUPDR_PUPDR12_Pos = 0x18
	// Bit mask of PUPDR12 field.
	GPIO_PUPDR_PUPDR12_Msk = 0x3000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR12_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR12_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR12_PullDown = 0x2
	// Position of PUPDR13 field.
	GPIO_PUPDR_PUPDR13_Pos = 0x1a
	// Bit mask of PUPDR13 field.
	GPIO_PUPDR_PUPDR13_Msk = 0xc000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR13_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR13_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR13_PullDown = 0x2
	// Position of PUPDR14 field.
	GPIO_PUPDR_PUPDR14_Pos = 0x1c
	// Bit mask of PUPDR14 field.
	GPIO_PUPDR_PUPDR14_Msk = 0x30000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR14_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR14_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR14_PullDown = 0x2
	// Position of PUPDR15 field.
	GPIO_PUPDR_PUPDR15_Pos = 0x1e
	// Bit mask of PUPDR15 field.
	GPIO_PUPDR_PUPDR15_Msk = 0xc0000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR15_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR15_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR15_PullDown = 0x2

	// IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIO_IDR_IDR0_Pos = 0x0
	// Bit mask of IDR0 field.
	GPIO_IDR_IDR0_Msk = 0x1
	// Bit IDR0.
	GPIO_IDR_IDR0 = 0x1
	// Input is logic high
	GPIO_IDR_IDR0_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR0_Low = 0x0
	// Position of IDR1 field.
	GPIO_IDR_IDR1_Pos = 0x1
	// Bit mask of IDR1 field.
	GPIO_IDR_IDR1_Msk = 0x2
	// Bit IDR1.
	GPIO_IDR_IDR1 = 0x2
	// Input is logic high
	GPIO_IDR_IDR1_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR1_Low = 0x0
	// Position of IDR2 field.
	GPIO_IDR_IDR2_Pos = 0x2
	// Bit mask of IDR2 field.
	GPIO_IDR_IDR2_Msk = 0x4
	// Bit IDR2.
	GPIO_IDR_IDR2 = 0x4
	// Input is logic high
	GPIO_IDR_IDR2_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR2_Low = 0x0
	// Position of IDR3 field.
	GPIO_IDR_IDR3_Pos = 0x3
	// Bit mask of IDR3 field.
	GPIO_IDR_IDR3_Msk = 0x8
	// Bit IDR3.
	GPIO_IDR_IDR3 = 0x8
	// Input is logic high
	GPIO_IDR_IDR3_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR3_Low = 0x0
	// Position of IDR4 field.
	GPIO_IDR_IDR4_Pos = 0x4
	// Bit mask of IDR4 field.
	GPIO_IDR_IDR4_Msk = 0x10
	// Bit IDR4.
	GPIO_IDR_IDR4 = 0x10
	// Input is logic high
	GPIO_IDR_IDR4_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR4_Low = 0x0
	// Position of IDR5 field.
	GPIO_IDR_IDR5_Pos = 0x5
	// Bit mask of IDR5 field.
	GPIO_IDR_IDR5_Msk = 0x20
	// Bit IDR5.
	GPIO_IDR_IDR5 = 0x20
	// Input is logic high
	GPIO_IDR_IDR5_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR5_Low = 0x0
	// Position of IDR6 field.
	GPIO_IDR_IDR6_Pos = 0x6
	// Bit mask of IDR6 field.
	GPIO_IDR_IDR6_Msk = 0x40
	// Bit IDR6.
	GPIO_IDR_IDR6 = 0x40
	// Input is logic high
	GPIO_IDR_IDR6_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR6_Low = 0x0
	// Position of IDR7 field.
	GPIO_IDR_IDR7_Pos = 0x7
	// Bit mask of IDR7 field.
	GPIO_IDR_IDR7_Msk = 0x80
	// Bit IDR7.
	GPIO_IDR_IDR7 = 0x80
	// Input is logic high
	GPIO_IDR_IDR7_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR7_Low = 0x0
	// Position of IDR8 field.
	GPIO_IDR_IDR8_Pos = 0x8
	// Bit mask of IDR8 field.
	GPIO_IDR_IDR8_Msk = 0x100
	// Bit IDR8.
	GPIO_IDR_IDR8 = 0x100
	// Input is logic high
	GPIO_IDR_IDR8_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR8_Low = 0x0
	// Position of IDR9 field.
	GPIO_IDR_IDR9_Pos = 0x9
	// Bit mask of IDR9 field.
	GPIO_IDR_IDR9_Msk = 0x200
	// Bit IDR9.
	GPIO_IDR_IDR9 = 0x200
	// Input is logic high
	GPIO_IDR_IDR9_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR9_Low = 0x0
	// Position of IDR10 field.
	GPIO_IDR_IDR10_Pos = 0xa
	// Bit mask of IDR10 field.
	GPIO_IDR_IDR10_Msk = 0x400
	// Bit IDR10.
	GPIO_IDR_IDR10 = 0x400
	// Input is logic high
	GPIO_IDR_IDR10_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR10_Low = 0x0
	// Position of IDR11 field.
	GPIO_IDR_IDR11_Pos = 0xb
	// Bit mask of IDR11 field.
	GPIO_IDR_IDR11_Msk = 0x800
	// Bit IDR11.
	GPIO_IDR_IDR11 = 0x800
	// Input is logic high
	GPIO_IDR_IDR11_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR11_Low = 0x0
	// Position of IDR12 field.
	GPIO_IDR_IDR12_Pos = 0xc
	// Bit mask of IDR12 field.
	GPIO_IDR_IDR12_Msk = 0x1000
	// Bit IDR12.
	GPIO_IDR_IDR12 = 0x1000
	// Input is logic high
	GPIO_IDR_IDR12_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR12_Low = 0x0
	// Position of IDR13 field.
	GPIO_IDR_IDR13_Pos = 0xd
	// Bit mask of IDR13 field.
	GPIO_IDR_IDR13_Msk = 0x2000
	// Bit IDR13.
	GPIO_IDR_IDR13 = 0x2000
	// Input is logic high
	GPIO_IDR_IDR13_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR13_Low = 0x0
	// Position of IDR14 field.
	GPIO_IDR_IDR14_Pos = 0xe
	// Bit mask of IDR14 field.
	GPIO_IDR_IDR14_Msk = 0x4000
	// Bit IDR14.
	GPIO_IDR_IDR14 = 0x4000
	// Input is logic high
	GPIO_IDR_IDR14_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR14_Low = 0x0
	// Position of IDR15 field.
	GPIO_IDR_IDR15_Pos = 0xf
	// Bit mask of IDR15 field.
	GPIO_IDR_IDR15_Msk = 0x8000
	// Bit IDR15.
	GPIO_IDR_IDR15 = 0x8000
	// Input is logic high
	GPIO_IDR_IDR15_High = 0x1
	// Input is logic low
	GPIO_IDR_IDR15_Low = 0x0

	// ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIO_ODR_ODR0_Pos = 0x0
	// Bit mask of ODR0 field.
	GPIO_ODR_ODR0_Msk = 0x1
	// Bit ODR0.
	GPIO_ODR_ODR0 = 0x1
	// Set output to logic high
	GPIO_ODR_ODR0_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR0_Low = 0x0
	// Position of ODR1 field.
	GPIO_ODR_ODR1_Pos = 0x1
	// Bit mask of ODR1 field.
	GPIO_ODR_ODR1_Msk = 0x2
	// Bit ODR1.
	GPIO_ODR_ODR1 = 0x2
	// Set output to logic high
	GPIO_ODR_ODR1_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR1_Low = 0x0
	// Position of ODR2 field.
	GPIO_ODR_ODR2_Pos = 0x2
	// Bit mask of ODR2 field.
	GPIO_ODR_ODR2_Msk = 0x4
	// Bit ODR2.
	GPIO_ODR_ODR2 = 0x4
	// Set output to logic high
	GPIO_ODR_ODR2_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR2_Low = 0x0
	// Position of ODR3 field.
	GPIO_ODR_ODR3_Pos = 0x3
	// Bit mask of ODR3 field.
	GPIO_ODR_ODR3_Msk = 0x8
	// Bit ODR3.
	GPIO_ODR_ODR3 = 0x8
	// Set output to logic high
	GPIO_ODR_ODR3_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR3_Low = 0x0
	// Position of ODR4 field.
	GPIO_ODR_ODR4_Pos = 0x4
	// Bit mask of ODR4 field.
	GPIO_ODR_ODR4_Msk = 0x10
	// Bit ODR4.
	GPIO_ODR_ODR4 = 0x10
	// Set output to logic high
	GPIO_ODR_ODR4_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR4_Low = 0x0
	// Position of ODR5 field.
	GPIO_ODR_ODR5_Pos = 0x5
	// Bit mask of ODR5 field.
	GPIO_ODR_ODR5_Msk = 0x20
	// Bit ODR5.
	GPIO_ODR_ODR5 = 0x20
	// Set output to logic high
	GPIO_ODR_ODR5_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR5_Low = 0x0
	// Position of ODR6 field.
	GPIO_ODR_ODR6_Pos = 0x6
	// Bit mask of ODR6 field.
	GPIO_ODR_ODR6_Msk = 0x40
	// Bit ODR6.
	GPIO_ODR_ODR6 = 0x40
	// Set output to logic high
	GPIO_ODR_ODR6_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR6_Low = 0x0
	// Position of ODR7 field.
	GPIO_ODR_ODR7_Pos = 0x7
	// Bit mask of ODR7 field.
	GPIO_ODR_ODR7_Msk = 0x80
	// Bit ODR7.
	GPIO_ODR_ODR7 = 0x80
	// Set output to logic high
	GPIO_ODR_ODR7_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR7_Low = 0x0
	// Position of ODR8 field.
	GPIO_ODR_ODR8_Pos = 0x8
	// Bit mask of ODR8 field.
	GPIO_ODR_ODR8_Msk = 0x100
	// Bit ODR8.
	GPIO_ODR_ODR8 = 0x100
	// Set output to logic high
	GPIO_ODR_ODR8_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR8_Low = 0x0
	// Position of ODR9 field.
	GPIO_ODR_ODR9_Pos = 0x9
	// Bit mask of ODR9 field.
	GPIO_ODR_ODR9_Msk = 0x200
	// Bit ODR9.
	GPIO_ODR_ODR9 = 0x200
	// Set output to logic high
	GPIO_ODR_ODR9_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR9_Low = 0x0
	// Position of ODR10 field.
	GPIO_ODR_ODR10_Pos = 0xa
	// Bit mask of ODR10 field.
	GPIO_ODR_ODR10_Msk = 0x400
	// Bit ODR10.
	GPIO_ODR_ODR10 = 0x400
	// Set output to logic high
	GPIO_ODR_ODR10_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR10_Low = 0x0
	// Position of ODR11 field.
	GPIO_ODR_ODR11_Pos = 0xb
	// Bit mask of ODR11 field.
	GPIO_ODR_ODR11_Msk = 0x800
	// Bit ODR11.
	GPIO_ODR_ODR11 = 0x800
	// Set output to logic high
	GPIO_ODR_ODR11_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR11_Low = 0x0
	// Position of ODR12 field.
	GPIO_ODR_ODR12_Pos = 0xc
	// Bit mask of ODR12 field.
	GPIO_ODR_ODR12_Msk = 0x1000
	// Bit ODR12.
	GPIO_ODR_ODR12 = 0x1000
	// Set output to logic high
	GPIO_ODR_ODR12_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR12_Low = 0x0
	// Position of ODR13 field.
	GPIO_ODR_ODR13_Pos = 0xd
	// Bit mask of ODR13 field.
	GPIO_ODR_ODR13_Msk = 0x2000
	// Bit ODR13.
	GPIO_ODR_ODR13 = 0x2000
	// Set output to logic high
	GPIO_ODR_ODR13_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR13_Low = 0x0
	// Position of ODR14 field.
	GPIO_ODR_ODR14_Pos = 0xe
	// Bit mask of ODR14 field.
	GPIO_ODR_ODR14_Msk = 0x4000
	// Bit ODR14.
	GPIO_ODR_ODR14 = 0x4000
	// Set output to logic high
	GPIO_ODR_ODR14_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR14_Low = 0x0
	// Position of ODR15 field.
	GPIO_ODR_ODR15_Pos = 0xf
	// Bit mask of ODR15 field.
	GPIO_ODR_ODR15_Msk = 0x8000
	// Bit ODR15.
	GPIO_ODR_ODR15 = 0x8000
	// Set output to logic high
	GPIO_ODR_ODR15_High = 0x1
	// Set output to logic low
	GPIO_ODR_ODR15_Low = 0x0

	// BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIO_BSRR_BS0_Pos = 0x0
	// Bit mask of BS0 field.
	GPIO_BSRR_BS0_Msk = 0x1
	// Bit BS0.
	GPIO_BSRR_BS0 = 0x1
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS0_Set = 0x1
	// Position of BS1 field.
	GPIO_BSRR_BS1_Pos = 0x1
	// Bit mask of BS1 field.
	GPIO_BSRR_BS1_Msk = 0x2
	// Bit BS1.
	GPIO_BSRR_BS1 = 0x2
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS1_Set = 0x1
	// Position of BS2 field.
	GPIO_BSRR_BS2_Pos = 0x2
	// Bit mask of BS2 field.
	GPIO_BSRR_BS2_Msk = 0x4
	// Bit BS2.
	GPIO_BSRR_BS2 = 0x4
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS2_Set = 0x1
	// Position of BS3 field.
	GPIO_BSRR_BS3_Pos = 0x3
	// Bit mask of BS3 field.
	GPIO_BSRR_BS3_Msk = 0x8
	// Bit BS3.
	GPIO_BSRR_BS3 = 0x8
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS3_Set = 0x1
	// Position of BS4 field.
	GPIO_BSRR_BS4_Pos = 0x4
	// Bit mask of BS4 field.
	GPIO_BSRR_BS4_Msk = 0x10
	// Bit BS4.
	GPIO_BSRR_BS4 = 0x10
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS4_Set = 0x1
	// Position of BS5 field.
	GPIO_BSRR_BS5_Pos = 0x5
	// Bit mask of BS5 field.
	GPIO_BSRR_BS5_Msk = 0x20
	// Bit BS5.
	GPIO_BSRR_BS5 = 0x20
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS5_Set = 0x1
	// Position of BS6 field.
	GPIO_BSRR_BS6_Pos = 0x6
	// Bit mask of BS6 field.
	GPIO_BSRR_BS6_Msk = 0x40
	// Bit BS6.
	GPIO_BSRR_BS6 = 0x40
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS6_Set = 0x1
	// Position of BS7 field.
	GPIO_BSRR_BS7_Pos = 0x7
	// Bit mask of BS7 field.
	GPIO_BSRR_BS7_Msk = 0x80
	// Bit BS7.
	GPIO_BSRR_BS7 = 0x80
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS7_Set = 0x1
	// Position of BS8 field.
	GPIO_BSRR_BS8_Pos = 0x8
	// Bit mask of BS8 field.
	GPIO_BSRR_BS8_Msk = 0x100
	// Bit BS8.
	GPIO_BSRR_BS8 = 0x100
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS8_Set = 0x1
	// Position of BS9 field.
	GPIO_BSRR_BS9_Pos = 0x9
	// Bit mask of BS9 field.
	GPIO_BSRR_BS9_Msk = 0x200
	// Bit BS9.
	GPIO_BSRR_BS9 = 0x200
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS9_Set = 0x1
	// Position of BS10 field.
	GPIO_BSRR_BS10_Pos = 0xa
	// Bit mask of BS10 field.
	GPIO_BSRR_BS10_Msk = 0x400
	// Bit BS10.
	GPIO_BSRR_BS10 = 0x400
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS10_Set = 0x1
	// Position of BS11 field.
	GPIO_BSRR_BS11_Pos = 0xb
	// Bit mask of BS11 field.
	GPIO_BSRR_BS11_Msk = 0x800
	// Bit BS11.
	GPIO_BSRR_BS11 = 0x800
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS11_Set = 0x1
	// Position of BS12 field.
	GPIO_BSRR_BS12_Pos = 0xc
	// Bit mask of BS12 field.
	GPIO_BSRR_BS12_Msk = 0x1000
	// Bit BS12.
	GPIO_BSRR_BS12 = 0x1000
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS12_Set = 0x1
	// Position of BS13 field.
	GPIO_BSRR_BS13_Pos = 0xd
	// Bit mask of BS13 field.
	GPIO_BSRR_BS13_Msk = 0x2000
	// Bit BS13.
	GPIO_BSRR_BS13 = 0x2000
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS13_Set = 0x1
	// Position of BS14 field.
	GPIO_BSRR_BS14_Pos = 0xe
	// Bit mask of BS14 field.
	GPIO_BSRR_BS14_Msk = 0x4000
	// Bit BS14.
	GPIO_BSRR_BS14 = 0x4000
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS14_Set = 0x1
	// Position of BS15 field.
	GPIO_BSRR_BS15_Pos = 0xf
	// Bit mask of BS15 field.
	GPIO_BSRR_BS15_Msk = 0x8000
	// Bit BS15.
	GPIO_BSRR_BS15 = 0x8000
	// Sets the corresponding ODRx bit
	GPIO_BSRR_BS15_Set = 0x1
	// Position of BR0 field.
	GPIO_BSRR_BR0_Pos = 0x10
	// Bit mask of BR0 field.
	GPIO_BSRR_BR0_Msk = 0x10000
	// Bit BR0.
	GPIO_BSRR_BR0 = 0x10000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BSRR_BR1_Pos = 0x11
	// Bit mask of BR1 field.
	GPIO_BSRR_BR1_Msk = 0x20000
	// Bit BR1.
	GPIO_BSRR_BR1 = 0x20000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BSRR_BR2_Pos = 0x12
	// Bit mask of BR2 field.
	GPIO_BSRR_BR2_Msk = 0x40000
	// Bit BR2.
	GPIO_BSRR_BR2 = 0x40000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BSRR_BR3_Pos = 0x13
	// Bit mask of BR3 field.
	GPIO_BSRR_BR3_Msk = 0x80000
	// Bit BR3.
	GPIO_BSRR_BR3 = 0x80000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BSRR_BR4_Pos = 0x14
	// Bit mask of BR4 field.
	GPIO_BSRR_BR4_Msk = 0x100000
	// Bit BR4.
	GPIO_BSRR_BR4 = 0x100000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BSRR_BR5_Pos = 0x15
	// Bit mask of BR5 field.
	GPIO_BSRR_BR5_Msk = 0x200000
	// Bit BR5.
	GPIO_BSRR_BR5 = 0x200000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BSRR_BR6_Pos = 0x16
	// Bit mask of BR6 field.
	GPIO_BSRR_BR6_Msk = 0x400000
	// Bit BR6.
	GPIO_BSRR_BR6 = 0x400000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BSRR_BR7_Pos = 0x17
	// Bit mask of BR7 field.
	GPIO_BSRR_BR7_Msk = 0x800000
	// Bit BR7.
	GPIO_BSRR_BR7 = 0x800000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BSRR_BR8_Pos = 0x18
	// Bit mask of BR8 field.
	GPIO_BSRR_BR8_Msk = 0x1000000
	// Bit BR8.
	GPIO_BSRR_BR8 = 0x1000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BSRR_BR9_Pos = 0x19
	// Bit mask of BR9 field.
	GPIO_BSRR_BR9_Msk = 0x2000000
	// Bit BR9.
	GPIO_BSRR_BR9 = 0x2000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BSRR_BR10_Pos = 0x1a
	// Bit mask of BR10 field.
	GPIO_BSRR_BR10_Msk = 0x4000000
	// Bit BR10.
	GPIO_BSRR_BR10 = 0x4000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BSRR_BR11_Pos = 0x1b
	// Bit mask of BR11 field.
	GPIO_BSRR_BR11_Msk = 0x8000000
	// Bit BR11.
	GPIO_BSRR_BR11 = 0x8000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR11_Reset = 0x1
	// Position of BR12 field.
	GPIO_BSRR_BR12_Pos = 0x1c
	// Bit mask of BR12 field.
	GPIO_BSRR_BR12_Msk = 0x10000000
	// Bit BR12.
	GPIO_BSRR_BR12 = 0x10000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR12_Reset = 0x1
	// Position of BR13 field.
	GPIO_BSRR_BR13_Pos = 0x1d
	// Bit mask of BR13 field.
	GPIO_BSRR_BR13_Msk = 0x20000000
	// Bit BR13.
	GPIO_BSRR_BR13 = 0x20000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR13_Reset = 0x1
	// Position of BR14 field.
	GPIO_BSRR_BR14_Pos = 0x1e
	// Bit mask of BR14 field.
	GPIO_BSRR_BR14_Msk = 0x40000000
	// Bit BR14.
	GPIO_BSRR_BR14 = 0x40000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR14_Reset = 0x1
	// Position of BR15 field.
	GPIO_BSRR_BR15_Pos = 0x1f
	// Bit mask of BR15 field.
	GPIO_BSRR_BR15_Msk = 0x80000000
	// Bit BR15.
	GPIO_BSRR_BR15 = 0x80000000
	// Resets the corresponding ODRx bit
	GPIO_BSRR_BR15_Reset = 0x1

	// LCKR: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).
	// Position of LCK0 field.
	GPIO_LCKR_LCK0_Pos = 0x0
	// Bit mask of LCK0 field.
	GPIO_LCKR_LCK0_Msk = 0x1
	// Bit LCK0.
	GPIO_LCKR_LCK0 = 0x1
	// Port configuration not locked
	GPIO_LCKR_LCK0_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK0_Locked = 0x1
	// Position of LCK1 field.
	GPIO_LCKR_LCK1_Pos = 0x1
	// Bit mask of LCK1 field.
	GPIO_LCKR_LCK1_Msk = 0x2
	// Bit LCK1.
	GPIO_LCKR_LCK1 = 0x2
	// Port configuration not locked
	GPIO_LCKR_LCK1_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK1_Locked = 0x1
	// Position of LCK2 field.
	GPIO_LCKR_LCK2_Pos = 0x2
	// Bit mask of LCK2 field.
	GPIO_LCKR_LCK2_Msk = 0x4
	// Bit LCK2.
	GPIO_LCKR_LCK2 = 0x4
	// Port configuration not locked
	GPIO_LCKR_LCK2_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK2_Locked = 0x1
	// Position of LCK3 field.
	GPIO_LCKR_LCK3_Pos = 0x3
	// Bit mask of LCK3 field.
	GPIO_LCKR_LCK3_Msk = 0x8
	// Bit LCK3.
	GPIO_LCKR_LCK3 = 0x8
	// Port configuration not locked
	GPIO_LCKR_LCK3_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK3_Locked = 0x1
	// Position of LCK4 field.
	GPIO_LCKR_LCK4_Pos = 0x4
	// Bit mask of LCK4 field.
	GPIO_LCKR_LCK4_Msk = 0x10
	// Bit LCK4.
	GPIO_LCKR_LCK4 = 0x10
	// Port configuration not locked
	GPIO_LCKR_LCK4_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK4_Locked = 0x1
	// Position of LCK5 field.
	GPIO_LCKR_LCK5_Pos = 0x5
	// Bit mask of LCK5 field.
	GPIO_LCKR_LCK5_Msk = 0x20
	// Bit LCK5.
	GPIO_LCKR_LCK5 = 0x20
	// Port configuration not locked
	GPIO_LCKR_LCK5_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK5_Locked = 0x1
	// Position of LCK6 field.
	GPIO_LCKR_LCK6_Pos = 0x6
	// Bit mask of LCK6 field.
	GPIO_LCKR_LCK6_Msk = 0x40
	// Bit LCK6.
	GPIO_LCKR_LCK6 = 0x40
	// Port configuration not locked
	GPIO_LCKR_LCK6_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK6_Locked = 0x1
	// Position of LCK7 field.
	GPIO_LCKR_LCK7_Pos = 0x7
	// Bit mask of LCK7 field.
	GPIO_LCKR_LCK7_Msk = 0x80
	// Bit LCK7.
	GPIO_LCKR_LCK7 = 0x80
	// Port configuration not locked
	GPIO_LCKR_LCK7_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK7_Locked = 0x1
	// Position of LCK8 field.
	GPIO_LCKR_LCK8_Pos = 0x8
	// Bit mask of LCK8 field.
	GPIO_LCKR_LCK8_Msk = 0x100
	// Bit LCK8.
	GPIO_LCKR_LCK8 = 0x100
	// Port configuration not locked
	GPIO_LCKR_LCK8_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK8_Locked = 0x1
	// Position of LCK9 field.
	GPIO_LCKR_LCK9_Pos = 0x9
	// Bit mask of LCK9 field.
	GPIO_LCKR_LCK9_Msk = 0x200
	// Bit LCK9.
	GPIO_LCKR_LCK9 = 0x200
	// Port configuration not locked
	GPIO_LCKR_LCK9_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK9_Locked = 0x1
	// Position of LCK10 field.
	GPIO_LCKR_LCK10_Pos = 0xa
	// Bit mask of LCK10 field.
	GPIO_LCKR_LCK10_Msk = 0x400
	// Bit LCK10.
	GPIO_LCKR_LCK10 = 0x400
	// Port configuration not locked
	GPIO_LCKR_LCK10_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK10_Locked = 0x1
	// Position of LCK11 field.
	GPIO_LCKR_LCK11_Pos = 0xb
	// Bit mask of LCK11 field.
	GPIO_LCKR_LCK11_Msk = 0x800
	// Bit LCK11.
	GPIO_LCKR_LCK11 = 0x800
	// Port configuration not locked
	GPIO_LCKR_LCK11_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK11_Locked = 0x1
	// Position of LCK12 field.
	GPIO_LCKR_LCK12_Pos = 0xc
	// Bit mask of LCK12 field.
	GPIO_LCKR_LCK12_Msk = 0x1000
	// Bit LCK12.
	GPIO_LCKR_LCK12 = 0x1000
	// Port configuration not locked
	GPIO_LCKR_LCK12_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK12_Locked = 0x1
	// Position of LCK13 field.
	GPIO_LCKR_LCK13_Pos = 0xd
	// Bit mask of LCK13 field.
	GPIO_LCKR_LCK13_Msk = 0x2000
	// Bit LCK13.
	GPIO_LCKR_LCK13 = 0x2000
	// Port configuration not locked
	GPIO_LCKR_LCK13_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK13_Locked = 0x1
	// Position of LCK14 field.
	GPIO_LCKR_LCK14_Pos = 0xe
	// Bit mask of LCK14 field.
	GPIO_LCKR_LCK14_Msk = 0x4000
	// Bit LCK14.
	GPIO_LCKR_LCK14 = 0x4000
	// Port configuration not locked
	GPIO_LCKR_LCK14_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK14_Locked = 0x1
	// Position of LCK15 field.
	GPIO_LCKR_LCK15_Pos = 0xf
	// Bit mask of LCK15 field.
	GPIO_LCKR_LCK15_Msk = 0x8000
	// Bit LCK15.
	GPIO_LCKR_LCK15 = 0x8000
	// Port configuration not locked
	GPIO_LCKR_LCK15_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK15_Locked = 0x1
	// Position of LCKK field.
	GPIO_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIO_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIO_LCKR_LCKK = 0x10000
	// Port configuration lock key not active
	GPIO_LCKR_LCKK_NotActive = 0x0
	// Port configuration lock key active
	GPIO_LCKR_LCKK_Active = 0x1

	// AFRL: GPIO alternate function low register
	// Position of AFR0 field.
	GPIO_AFRL_AFR0_Pos = 0x0
	// Bit mask of AFR0 field.
	GPIO_AFRL_AFR0_Msk = 0xf
	// AF0
	GPIO_AFRL_AFR0_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR0_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR0_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR0_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR0_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR0_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR0_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR0_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR0_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR0_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR0_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR0_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR0_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR0_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR0_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR0_AF15 = 0xf
	// Position of AFR1 field.
	GPIO_AFRL_AFR1_Pos = 0x4
	// Bit mask of AFR1 field.
	GPIO_AFRL_AFR1_Msk = 0xf0
	// AF0
	GPIO_AFRL_AFR1_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR1_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR1_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR1_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR1_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR1_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR1_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR1_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR1_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR1_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR1_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR1_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR1_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR1_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR1_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR1_AF15 = 0xf
	// Position of AFR2 field.
	GPIO_AFRL_AFR2_Pos = 0x8
	// Bit mask of AFR2 field.
	GPIO_AFRL_AFR2_Msk = 0xf00
	// AF0
	GPIO_AFRL_AFR2_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR2_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR2_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR2_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR2_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR2_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR2_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR2_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR2_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR2_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR2_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR2_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR2_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR2_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR2_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR2_AF15 = 0xf
	// Position of AFR3 field.
	GPIO_AFRL_AFR3_Pos = 0xc
	// Bit mask of AFR3 field.
	GPIO_AFRL_AFR3_Msk = 0xf000
	// AF0
	GPIO_AFRL_AFR3_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR3_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR3_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR3_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR3_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR3_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR3_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR3_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR3_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR3_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR3_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR3_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR3_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR3_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR3_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR3_AF15 = 0xf
	// Position of AFR4 field.
	GPIO_AFRL_AFR4_Pos = 0x10
	// Bit mask of AFR4 field.
	GPIO_AFRL_AFR4_Msk = 0xf0000
	// AF0
	GPIO_AFRL_AFR4_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR4_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR4_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR4_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR4_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR4_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR4_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR4_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR4_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR4_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR4_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR4_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR4_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR4_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR4_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR4_AF15 = 0xf
	// Position of AFR5 field.
	GPIO_AFRL_AFR5_Pos = 0x14
	// Bit mask of AFR5 field.
	GPIO_AFRL_AFR5_Msk = 0xf00000
	// AF0
	GPIO_AFRL_AFR5_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR5_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR5_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR5_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR5_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR5_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR5_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR5_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR5_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR5_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR5_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR5_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR5_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR5_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR5_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR5_AF15 = 0xf
	// Position of AFR6 field.
	GPIO_AFRL_AFR6_Pos = 0x18
	// Bit mask of AFR6 field.
	GPIO_AFRL_AFR6_Msk = 0xf000000
	// AF0
	GPIO_AFRL_AFR6_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR6_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR6_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR6_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR6_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR6_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR6_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR6_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR6_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR6_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR6_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR6_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR6_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR6_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR6_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR6_AF15 = 0xf
	// Position of AFR7 field.
	GPIO_AFRL_AFR7_Pos = 0x1c
	// Bit mask of AFR7 field.
	GPIO_AFRL_AFR7_Msk = 0xf0000000
	// AF0
	GPIO_AFRL_AFR7_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFR7_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFR7_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFR7_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFR7_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFR7_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFR7_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFR7_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFR7_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFR7_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFR7_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFR7_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFR7_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFR7_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFR7_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFR7_AF15 = 0xf

	// AFRH: GPIO alternate function high register
	// Position of AFR8 field.
	GPIO_AFRH_AFR8_Pos = 0x0
	// Bit mask of AFR8 field.
	GPIO_AFRH_AFR8_Msk = 0xf
	// AF0
	GPIO_AFRH_AFR8_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR8_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR8_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR8_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR8_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR8_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR8_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR8_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR8_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR8_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR8_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR8_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR8_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR8_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR8_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR8_AF15 = 0xf
	// Position of AFR9 field.
	GPIO_AFRH_AFR9_Pos = 0x4
	// Bit mask of AFR9 field.
	GPIO_AFRH_AFR9_Msk = 0xf0
	// AF0
	GPIO_AFRH_AFR9_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR9_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR9_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR9_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR9_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR9_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR9_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR9_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR9_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR9_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR9_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR9_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR9_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR9_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR9_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR9_AF15 = 0xf
	// Position of AFR10 field.
	GPIO_AFRH_AFR10_Pos = 0x8
	// Bit mask of AFR10 field.
	GPIO_AFRH_AFR10_Msk = 0xf00
	// AF0
	GPIO_AFRH_AFR10_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR10_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR10_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR10_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR10_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR10_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR10_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR10_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR10_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR10_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR10_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR10_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR10_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR10_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR10_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR10_AF15 = 0xf
	// Position of AFR11 field.
	GPIO_AFRH_AFR11_Pos = 0xc
	// Bit mask of AFR11 field.
	GPIO_AFRH_AFR11_Msk = 0xf000
	// AF0
	GPIO_AFRH_AFR11_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR11_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR11_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR11_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR11_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR11_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR11_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR11_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR11_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR11_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR11_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR11_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR11_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR11_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR11_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR11_AF15 = 0xf
	// Position of AFR12 field.
	GPIO_AFRH_AFR12_Pos = 0x10
	// Bit mask of AFR12 field.
	GPIO_AFRH_AFR12_Msk = 0xf0000
	// AF0
	GPIO_AFRH_AFR12_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR12_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR12_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR12_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR12_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR12_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR12_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR12_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR12_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR12_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR12_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR12_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR12_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR12_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR12_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR12_AF15 = 0xf
	// Position of AFR13 field.
	GPIO_AFRH_AFR13_Pos = 0x14
	// Bit mask of AFR13 field.
	GPIO_AFRH_AFR13_Msk = 0xf00000
	// AF0
	GPIO_AFRH_AFR13_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR13_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR13_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR13_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR13_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR13_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR13_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR13_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR13_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR13_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR13_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR13_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR13_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR13_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR13_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR13_AF15 = 0xf
	// Position of AFR14 field.
	GPIO_AFRH_AFR14_Pos = 0x18
	// Bit mask of AFR14 field.
	GPIO_AFRH_AFR14_Msk = 0xf000000
	// AF0
	GPIO_AFRH_AFR14_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR14_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR14_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR14_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR14_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR14_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR14_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR14_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR14_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR14_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR14_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR14_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR14_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR14_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR14_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR14_AF15 = 0xf
	// Position of AFR15 field.
	GPIO_AFRH_AFR15_Pos = 0x1c
	// Bit mask of AFR15 field.
	GPIO_AFRH_AFR15_Msk = 0xf0000000
	// AF0
	GPIO_AFRH_AFR15_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFR15_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFR15_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFR15_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFR15_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFR15_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFR15_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFR15_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFR15_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFR15_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFR15_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFR15_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFR15_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFR15_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFR15_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFR15_AF15 = 0xf
)

// Bitfields for JPEG: JPEG
const (
	// CONFR0: JPEG codec control register
	// Position of START field.
	JPEG_CONFR0_START_Pos = 0x0
	// Bit mask of START field.
	JPEG_CONFR0_START_Msk = 0x1
	// Bit START.
	JPEG_CONFR0_START = 0x1

	// CONFR1: JPEG codec configuration register 1
	// Position of NF field.
	JPEG_CONFR1_NF_Pos = 0x0
	// Bit mask of NF field.
	JPEG_CONFR1_NF_Msk = 0x3
	// Position of DE field.
	JPEG_CONFR1_DE_Pos = 0x3
	// Bit mask of DE field.
	JPEG_CONFR1_DE_Msk = 0x8
	// Bit DE.
	JPEG_CONFR1_DE = 0x8
	// Position of COLORSPACE field.
	JPEG_CONFR1_COLORSPACE_Pos = 0x4
	// Bit mask of COLORSPACE field.
	JPEG_CONFR1_COLORSPACE_Msk = 0x30
	// Position of NS field.
	JPEG_CONFR1_NS_Pos = 0x6
	// Bit mask of NS field.
	JPEG_CONFR1_NS_Msk = 0xc0
	// Position of HDR field.
	JPEG_CONFR1_HDR_Pos = 0x8
	// Bit mask of HDR field.
	JPEG_CONFR1_HDR_Msk = 0x100
	// Bit HDR.
	JPEG_CONFR1_HDR = 0x100
	// Position of YSIZE field.
	JPEG_CONFR1_YSIZE_Pos = 0x10
	// Bit mask of YSIZE field.
	JPEG_CONFR1_YSIZE_Msk = 0xffff0000

	// CONFR2: JPEG codec configuration register 2
	// Position of NMCU field.
	JPEG_CONFR2_NMCU_Pos = 0x0
	// Bit mask of NMCU field.
	JPEG_CONFR2_NMCU_Msk = 0x3ffffff

	// CONFR3: JPEG codec configuration register 3
	// Position of XSIZE field.
	JPEG_CONFR3_XSIZE_Pos = 0x10
	// Bit mask of XSIZE field.
	JPEG_CONFR3_XSIZE_Msk = 0xffff0000

	// CONFRN1: JPEG codec configuration register 4-7
	// Position of HD field.
	JPEG_CONFRN1_HD_Pos = 0x0
	// Bit mask of HD field.
	JPEG_CONFRN1_HD_Msk = 0x1
	// Bit HD.
	JPEG_CONFRN1_HD = 0x1
	// Position of HA field.
	JPEG_CONFRN1_HA_Pos = 0x1
	// Bit mask of HA field.
	JPEG_CONFRN1_HA_Msk = 0x2
	// Bit HA.
	JPEG_CONFRN1_HA = 0x2
	// Position of QT field.
	JPEG_CONFRN1_QT_Pos = 0x2
	// Bit mask of QT field.
	JPEG_CONFRN1_QT_Msk = 0xc
	// Position of NB field.
	JPEG_CONFRN1_NB_Pos = 0x4
	// Bit mask of NB field.
	JPEG_CONFRN1_NB_Msk = 0xf0
	// Position of VSF field.
	JPEG_CONFRN1_VSF_Pos = 0x8
	// Bit mask of VSF field.
	JPEG_CONFRN1_VSF_Msk = 0xf00
	// Position of HSF field.
	JPEG_CONFRN1_HSF_Pos = 0xc
	// Bit mask of HSF field.
	JPEG_CONFRN1_HSF_Msk = 0xf000

	// CONFRN2: JPEG codec configuration register 4-7
	// Position of HD field.
	JPEG_CONFRN2_HD_Pos = 0x0
	// Bit mask of HD field.
	JPEG_CONFRN2_HD_Msk = 0x1
	// Bit HD.
	JPEG_CONFRN2_HD = 0x1
	// Position of HA field.
	JPEG_CONFRN2_HA_Pos = 0x1
	// Bit mask of HA field.
	JPEG_CONFRN2_HA_Msk = 0x2
	// Bit HA.
	JPEG_CONFRN2_HA = 0x2
	// Position of QT field.
	JPEG_CONFRN2_QT_Pos = 0x2
	// Bit mask of QT field.
	JPEG_CONFRN2_QT_Msk = 0xc
	// Position of NB field.
	JPEG_CONFRN2_NB_Pos = 0x4
	// Bit mask of NB field.
	JPEG_CONFRN2_NB_Msk = 0xf0
	// Position of VSF field.
	JPEG_CONFRN2_VSF_Pos = 0x8
	// Bit mask of VSF field.
	JPEG_CONFRN2_VSF_Msk = 0xf00
	// Position of HSF field.
	JPEG_CONFRN2_HSF_Pos = 0xc
	// Bit mask of HSF field.
	JPEG_CONFRN2_HSF_Msk = 0xf000

	// CONFRN3: JPEG codec configuration register 4-7
	// Position of HD field.
	JPEG_CONFRN3_HD_Pos = 0x0
	// Bit mask of HD field.
	JPEG_CONFRN3_HD_Msk = 0x1
	// Bit HD.
	JPEG_CONFRN3_HD = 0x1
	// Position of HA field.
	JPEG_CONFRN3_HA_Pos = 0x1
	// Bit mask of HA field.
	JPEG_CONFRN3_HA_Msk = 0x2
	// Bit HA.
	JPEG_CONFRN3_HA = 0x2
	// Position of QT field.
	JPEG_CONFRN3_QT_Pos = 0x2
	// Bit mask of QT field.
	JPEG_CONFRN3_QT_Msk = 0xc
	// Position of NB field.
	JPEG_CONFRN3_NB_Pos = 0x4
	// Bit mask of NB field.
	JPEG_CONFRN3_NB_Msk = 0xf0
	// Position of VSF field.
	JPEG_CONFRN3_VSF_Pos = 0x8
	// Bit mask of VSF field.
	JPEG_CONFRN3_VSF_Msk = 0xf00
	// Position of HSF field.
	JPEG_CONFRN3_HSF_Pos = 0xc
	// Bit mask of HSF field.
	JPEG_CONFRN3_HSF_Msk = 0xf000

	// CONFRN4: JPEG codec configuration register 4-7
	// Position of HD field.
	JPEG_CONFRN4_HD_Pos = 0x0
	// Bit mask of HD field.
	JPEG_CONFRN4_HD_Msk = 0x1
	// Bit HD.
	JPEG_CONFRN4_HD = 0x1
	// Position of HA field.
	JPEG_CONFRN4_HA_Pos = 0x1
	// Bit mask of HA field.
	JPEG_CONFRN4_HA_Msk = 0x2
	// Bit HA.
	JPEG_CONFRN4_HA = 0x2
	// Position of QT field.
	JPEG_CONFRN4_QT_Pos = 0x2
	// Bit mask of QT field.
	JPEG_CONFRN4_QT_Msk = 0xc
	// Position of NB field.
	JPEG_CONFRN4_NB_Pos = 0x4
	// Bit mask of NB field.
	JPEG_CONFRN4_NB_Msk = 0xf0
	// Position of VSF field.
	JPEG_CONFRN4_VSF_Pos = 0x8
	// Bit mask of VSF field.
	JPEG_CONFRN4_VSF_Msk = 0xf00
	// Position of HSF field.
	JPEG_CONFRN4_HSF_Pos = 0xc
	// Bit mask of HSF field.
	JPEG_CONFRN4_HSF_Msk = 0xf000

	// CR: JPEG control register
	// Position of JCEN field.
	JPEG_CR_JCEN_Pos = 0x0
	// Bit mask of JCEN field.
	JPEG_CR_JCEN_Msk = 0x1
	// Bit JCEN.
	JPEG_CR_JCEN = 0x1
	// Position of IFTIE field.
	JPEG_CR_IFTIE_Pos = 0x1
	// Bit mask of IFTIE field.
	JPEG_CR_IFTIE_Msk = 0x2
	// Bit IFTIE.
	JPEG_CR_IFTIE = 0x2
	// Position of IFNFIE field.
	JPEG_CR_IFNFIE_Pos = 0x2
	// Bit mask of IFNFIE field.
	JPEG_CR_IFNFIE_Msk = 0x4
	// Bit IFNFIE.
	JPEG_CR_IFNFIE = 0x4
	// Position of OFTIE field.
	JPEG_CR_OFTIE_Pos = 0x3
	// Bit mask of OFTIE field.
	JPEG_CR_OFTIE_Msk = 0x8
	// Bit OFTIE.
	JPEG_CR_OFTIE = 0x8
	// Position of OFNEIE field.
	JPEG_CR_OFNEIE_Pos = 0x4
	// Bit mask of OFNEIE field.
	JPEG_CR_OFNEIE_Msk = 0x10
	// Bit OFNEIE.
	JPEG_CR_OFNEIE = 0x10
	// Position of EOCIE field.
	JPEG_CR_EOCIE_Pos = 0x5
	// Bit mask of EOCIE field.
	JPEG_CR_EOCIE_Msk = 0x20
	// Bit EOCIE.
	JPEG_CR_EOCIE = 0x20
	// Position of HPDIE field.
	JPEG_CR_HPDIE_Pos = 0x6
	// Bit mask of HPDIE field.
	JPEG_CR_HPDIE_Msk = 0x40
	// Bit HPDIE.
	JPEG_CR_HPDIE = 0x40
	// Position of IDMAEN field.
	JPEG_CR_IDMAEN_Pos = 0xb
	// Bit mask of IDMAEN field.
	JPEG_CR_IDMAEN_Msk = 0x800
	// Bit IDMAEN.
	JPEG_CR_IDMAEN = 0x800
	// Position of ODMAEN field.
	JPEG_CR_ODMAEN_Pos = 0xc
	// Bit mask of ODMAEN field.
	JPEG_CR_ODMAEN_Msk = 0x1000
	// Bit ODMAEN.
	JPEG_CR_ODMAEN = 0x1000
	// Position of IFF field.
	JPEG_CR_IFF_Pos = 0xd
	// Bit mask of IFF field.
	JPEG_CR_IFF_Msk = 0x2000
	// Bit IFF.
	JPEG_CR_IFF = 0x2000
	// Position of OFF field.
	JPEG_CR_OFF_Pos = 0xe
	// Bit mask of OFF field.
	JPEG_CR_OFF_Msk = 0x4000
	// Bit OFF.
	JPEG_CR_OFF = 0x4000

	// SR: JPEG status register
	// Position of IFTF field.
	JPEG_SR_IFTF_Pos = 0x1
	// Bit mask of IFTF field.
	JPEG_SR_IFTF_Msk = 0x2
	// Bit IFTF.
	JPEG_SR_IFTF = 0x2
	// Position of IFNFF field.
	JPEG_SR_IFNFF_Pos = 0x2
	// Bit mask of IFNFF field.
	JPEG_SR_IFNFF_Msk = 0x4
	// Bit IFNFF.
	JPEG_SR_IFNFF = 0x4
	// Position of OFTF field.
	JPEG_SR_OFTF_Pos = 0x3
	// Bit mask of OFTF field.
	JPEG_SR_OFTF_Msk = 0x8
	// Bit OFTF.
	JPEG_SR_OFTF = 0x8
	// Position of OFNEF field.
	JPEG_SR_OFNEF_Pos = 0x4
	// Bit mask of OFNEF field.
	JPEG_SR_OFNEF_Msk = 0x10
	// Bit OFNEF.
	JPEG_SR_OFNEF = 0x10
	// Position of EOCF field.
	JPEG_SR_EOCF_Pos = 0x5
	// Bit mask of EOCF field.
	JPEG_SR_EOCF_Msk = 0x20
	// Bit EOCF.
	JPEG_SR_EOCF = 0x20
	// Position of HPDF field.
	JPEG_SR_HPDF_Pos = 0x6
	// Bit mask of HPDF field.
	JPEG_SR_HPDF_Msk = 0x40
	// Bit HPDF.
	JPEG_SR_HPDF = 0x40
	// Position of COF field.
	JPEG_SR_COF_Pos = 0x7
	// Bit mask of COF field.
	JPEG_SR_COF_Msk = 0x80
	// Bit COF.
	JPEG_SR_COF = 0x80

	// CFR: JPEG clear flag register
	// Position of CEOCF field.
	JPEG_CFR_CEOCF_Pos = 0x5
	// Bit mask of CEOCF field.
	JPEG_CFR_CEOCF_Msk = 0x20
	// Bit CEOCF.
	JPEG_CFR_CEOCF = 0x20
	// Position of CHPDF field.
	JPEG_CFR_CHPDF_Pos = 0x6
	// Bit mask of CHPDF field.
	JPEG_CFR_CHPDF_Msk = 0x40
	// Bit CHPDF.
	JPEG_CFR_CHPDF = 0x40

	// DIR: JPEG data input register
	// Position of DATAIN field.
	JPEG_DIR_DATAIN_Pos = 0x0
	// Bit mask of DATAIN field.
	JPEG_DIR_DATAIN_Msk = 0xffffffff

	// DOR: JPEG data output register
	// Position of DATAOUT field.
	JPEG_DOR_DATAOUT_Pos = 0x0
	// Bit mask of DATAOUT field.
	JPEG_DOR_DATAOUT_Msk = 0xffffffff
)

// Bitfields for MDMA: MDMA
const (
	// GISR0: MDMA Global Interrupt/Status Register
	// Position of GIF0 field.
	MDMA_GISR0_GIF0_Pos = 0x0
	// Bit mask of GIF0 field.
	MDMA_GISR0_GIF0_Msk = 0x1
	// Bit GIF0.
	MDMA_GISR0_GIF0 = 0x1
	// Position of GIF1 field.
	MDMA_GISR0_GIF1_Pos = 0x1
	// Bit mask of GIF1 field.
	MDMA_GISR0_GIF1_Msk = 0x2
	// Bit GIF1.
	MDMA_GISR0_GIF1 = 0x2
	// Position of GIF2 field.
	MDMA_GISR0_GIF2_Pos = 0x2
	// Bit mask of GIF2 field.
	MDMA_GISR0_GIF2_Msk = 0x4
	// Bit GIF2.
	MDMA_GISR0_GIF2 = 0x4
	// Position of GIF3 field.
	MDMA_GISR0_GIF3_Pos = 0x3
	// Bit mask of GIF3 field.
	MDMA_GISR0_GIF3_Msk = 0x8
	// Bit GIF3.
	MDMA_GISR0_GIF3 = 0x8
	// Position of GIF4 field.
	MDMA_GISR0_GIF4_Pos = 0x4
	// Bit mask of GIF4 field.
	MDMA_GISR0_GIF4_Msk = 0x10
	// Bit GIF4.
	MDMA_GISR0_GIF4 = 0x10
	// Position of GIF5 field.
	MDMA_GISR0_GIF5_Pos = 0x5
	// Bit mask of GIF5 field.
	MDMA_GISR0_GIF5_Msk = 0x20
	// Bit GIF5.
	MDMA_GISR0_GIF5 = 0x20
	// Position of GIF6 field.
	MDMA_GISR0_GIF6_Pos = 0x6
	// Bit mask of GIF6 field.
	MDMA_GISR0_GIF6_Msk = 0x40
	// Bit GIF6.
	MDMA_GISR0_GIF6 = 0x40
	// Position of GIF7 field.
	MDMA_GISR0_GIF7_Pos = 0x7
	// Bit mask of GIF7 field.
	MDMA_GISR0_GIF7_Msk = 0x80
	// Bit GIF7.
	MDMA_GISR0_GIF7 = 0x80
	// Position of GIF8 field.
	MDMA_GISR0_GIF8_Pos = 0x8
	// Bit mask of GIF8 field.
	MDMA_GISR0_GIF8_Msk = 0x100
	// Bit GIF8.
	MDMA_GISR0_GIF8 = 0x100
	// Position of GIF9 field.
	MDMA_GISR0_GIF9_Pos = 0x9
	// Bit mask of GIF9 field.
	MDMA_GISR0_GIF9_Msk = 0x200
	// Bit GIF9.
	MDMA_GISR0_GIF9 = 0x200
	// Position of GIF10 field.
	MDMA_GISR0_GIF10_Pos = 0xa
	// Bit mask of GIF10 field.
	MDMA_GISR0_GIF10_Msk = 0x400
	// Bit GIF10.
	MDMA_GISR0_GIF10 = 0x400
	// Position of GIF11 field.
	MDMA_GISR0_GIF11_Pos = 0xb
	// Bit mask of GIF11 field.
	MDMA_GISR0_GIF11_Msk = 0x800
	// Bit GIF11.
	MDMA_GISR0_GIF11 = 0x800
	// Position of GIF12 field.
	MDMA_GISR0_GIF12_Pos = 0xc
	// Bit mask of GIF12 field.
	MDMA_GISR0_GIF12_Msk = 0x1000
	// Bit GIF12.
	MDMA_GISR0_GIF12 = 0x1000
	// Position of GIF13 field.
	MDMA_GISR0_GIF13_Pos = 0xd
	// Bit mask of GIF13 field.
	MDMA_GISR0_GIF13_Msk = 0x2000
	// Bit GIF13.
	MDMA_GISR0_GIF13 = 0x2000
	// Position of GIF14 field.
	MDMA_GISR0_GIF14_Pos = 0xe
	// Bit mask of GIF14 field.
	MDMA_GISR0_GIF14_Msk = 0x4000
	// Bit GIF14.
	MDMA_GISR0_GIF14 = 0x4000
	// Position of GIF15 field.
	MDMA_GISR0_GIF15_Pos = 0xf
	// Bit mask of GIF15 field.
	MDMA_GISR0_GIF15_Msk = 0x8000
	// Bit GIF15.
	MDMA_GISR0_GIF15 = 0x8000

	// CH.ISR: MDMA channel x interrupt/status register
	// Position of TEIF field.
	MDMA_CH_ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	MDMA_CH_ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	MDMA_CH_ISR_TEIF = 0x1
	// Position of CTCIF field.
	MDMA_CH_ISR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	MDMA_CH_ISR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	MDMA_CH_ISR_CTCIF = 0x2
	// Position of BRTIF field.
	MDMA_CH_ISR_BRTIF_Pos = 0x2
	// Bit mask of BRTIF field.
	MDMA_CH_ISR_BRTIF_Msk = 0x4
	// Bit BRTIF.
	MDMA_CH_ISR_BRTIF = 0x4
	// Position of BTIF field.
	MDMA_CH_ISR_BTIF_Pos = 0x3
	// Bit mask of BTIF field.
	MDMA_CH_ISR_BTIF_Msk = 0x8
	// Bit BTIF.
	MDMA_CH_ISR_BTIF = 0x8
	// Position of TCIF field.
	MDMA_CH_ISR_TCIF_Pos = 0x4
	// Bit mask of TCIF field.
	MDMA_CH_ISR_TCIF_Msk = 0x10
	// Bit TCIF.
	MDMA_CH_ISR_TCIF = 0x10
	// Position of CRQA field.
	MDMA_CH_ISR_CRQA_Pos = 0x10
	// Bit mask of CRQA field.
	MDMA_CH_ISR_CRQA_Msk = 0x10000
	// Bit CRQA.
	MDMA_CH_ISR_CRQA = 0x10000

	// CH.IFCR: MDMA channel x interrupt flag clear register
	// Position of CTEIF field.
	MDMA_CH_IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	MDMA_CH_IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	MDMA_CH_IFCR_CTEIF = 0x1
	// Position of CCTCIF field.
	MDMA_CH_IFCR_CCTCIF_Pos = 0x1
	// Bit mask of CCTCIF field.
	MDMA_CH_IFCR_CCTCIF_Msk = 0x2
	// Bit CCTCIF.
	MDMA_CH_IFCR_CCTCIF = 0x2
	// Position of CBRTIF field.
	MDMA_CH_IFCR_CBRTIF_Pos = 0x2
	// Bit mask of CBRTIF field.
	MDMA_CH_IFCR_CBRTIF_Msk = 0x4
	// Bit CBRTIF.
	MDMA_CH_IFCR_CBRTIF = 0x4
	// Position of CBTIF field.
	MDMA_CH_IFCR_CBTIF_Pos = 0x3
	// Bit mask of CBTIF field.
	MDMA_CH_IFCR_CBTIF_Msk = 0x8
	// Bit CBTIF.
	MDMA_CH_IFCR_CBTIF = 0x8
	// Position of CLTCIF field.
	MDMA_CH_IFCR_CLTCIF_Pos = 0x4
	// Bit mask of CLTCIF field.
	MDMA_CH_IFCR_CLTCIF_Msk = 0x10
	// Bit CLTCIF.
	MDMA_CH_IFCR_CLTCIF = 0x10

	// CH.ESR: MDMA Channel x error status register
	// Position of TEA field.
	MDMA_CH_ESR_TEA_Pos = 0x0
	// Bit mask of TEA field.
	MDMA_CH_ESR_TEA_Msk = 0x7f
	// Position of TED field.
	MDMA_CH_ESR_TED_Pos = 0x7
	// Bit mask of TED field.
	MDMA_CH_ESR_TED_Msk = 0x80
	// Bit TED.
	MDMA_CH_ESR_TED = 0x80
	// Position of TELD field.
	MDMA_CH_ESR_TELD_Pos = 0x8
	// Bit mask of TELD field.
	MDMA_CH_ESR_TELD_Msk = 0x100
	// Bit TELD.
	MDMA_CH_ESR_TELD = 0x100
	// Position of TEMD field.
	MDMA_CH_ESR_TEMD_Pos = 0x9
	// Bit mask of TEMD field.
	MDMA_CH_ESR_TEMD_Msk = 0x200
	// Bit TEMD.
	MDMA_CH_ESR_TEMD = 0x200
	// Position of ASE field.
	MDMA_CH_ESR_ASE_Pos = 0xa
	// Bit mask of ASE field.
	MDMA_CH_ESR_ASE_Msk = 0x400
	// Bit ASE.
	MDMA_CH_ESR_ASE = 0x400
	// Position of BSE field.
	MDMA_CH_ESR_BSE_Pos = 0xb
	// Bit mask of BSE field.
	MDMA_CH_ESR_BSE_Msk = 0x800
	// Bit BSE.
	MDMA_CH_ESR_BSE = 0x800

	// CH.CR: This register is used to control the concerned channel.
	// Position of EN field.
	MDMA_CH_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDMA_CH_CR_EN_Msk = 0x1
	// Bit EN.
	MDMA_CH_CR_EN = 0x1
	// Position of TEIE field.
	MDMA_CH_CR_TEIE_Pos = 0x1
	// Bit mask of TEIE field.
	MDMA_CH_CR_TEIE_Msk = 0x2
	// Bit TEIE.
	MDMA_CH_CR_TEIE = 0x2
	// Position of CTCIE field.
	MDMA_CH_CR_CTCIE_Pos = 0x2
	// Bit mask of CTCIE field.
	MDMA_CH_CR_CTCIE_Msk = 0x4
	// Bit CTCIE.
	MDMA_CH_CR_CTCIE = 0x4
	// Position of BRTIE field.
	MDMA_CH_CR_BRTIE_Pos = 0x3
	// Bit mask of BRTIE field.
	MDMA_CH_CR_BRTIE_Msk = 0x8
	// Bit BRTIE.
	MDMA_CH_CR_BRTIE = 0x8
	// Position of BTIE field.
	MDMA_CH_CR_BTIE_Pos = 0x4
	// Bit mask of BTIE field.
	MDMA_CH_CR_BTIE_Msk = 0x10
	// Bit BTIE.
	MDMA_CH_CR_BTIE = 0x10
	// Position of TCIE field.
	MDMA_CH_CR_TCIE_Pos = 0x5
	// Bit mask of TCIE field.
	MDMA_CH_CR_TCIE_Msk = 0x20
	// Bit TCIE.
	MDMA_CH_CR_TCIE = 0x20
	// Position of PL field.
	MDMA_CH_CR_PL_Pos = 0x6
	// Bit mask of PL field.
	MDMA_CH_CR_PL_Msk = 0xc0
	// Position of BEX field.
	MDMA_CH_CR_BEX_Pos = 0xc
	// Bit mask of BEX field.
	MDMA_CH_CR_BEX_Msk = 0x1000
	// Bit BEX.
	MDMA_CH_CR_BEX = 0x1000
	// Position of HEX field.
	MDMA_CH_CR_HEX_Pos = 0xd
	// Bit mask of HEX field.
	MDMA_CH_CR_HEX_Msk = 0x2000
	// Bit HEX.
	MDMA_CH_CR_HEX = 0x2000
	// Position of WEX field.
	MDMA_CH_CR_WEX_Pos = 0xe
	// Bit mask of WEX field.
	MDMA_CH_CR_WEX_Msk = 0x4000
	// Bit WEX.
	MDMA_CH_CR_WEX = 0x4000
	// Position of SWRQ field.
	MDMA_CH_CR_SWRQ_Pos = 0x10
	// Bit mask of SWRQ field.
	MDMA_CH_CR_SWRQ_Msk = 0x10000
	// Bit SWRQ.
	MDMA_CH_CR_SWRQ = 0x10000

	// CH.TCR: This register is used to configure the concerned channel.
	// Position of SINC field.
	MDMA_CH_TCR_SINC_Pos = 0x0
	// Bit mask of SINC field.
	MDMA_CH_TCR_SINC_Msk = 0x3
	// Position of DINC field.
	MDMA_CH_TCR_DINC_Pos = 0x2
	// Bit mask of DINC field.
	MDMA_CH_TCR_DINC_Msk = 0xc
	// Position of SSIZE field.
	MDMA_CH_TCR_SSIZE_Pos = 0x4
	// Bit mask of SSIZE field.
	MDMA_CH_TCR_SSIZE_Msk = 0x30
	// Position of DSIZE field.
	MDMA_CH_TCR_DSIZE_Pos = 0x6
	// Bit mask of DSIZE field.
	MDMA_CH_TCR_DSIZE_Msk = 0xc0
	// Position of SINCOS field.
	MDMA_CH_TCR_SINCOS_Pos = 0x8
	// Bit mask of SINCOS field.
	MDMA_CH_TCR_SINCOS_Msk = 0x300
	// Position of DINCOS field.
	MDMA_CH_TCR_DINCOS_Pos = 0xa
	// Bit mask of DINCOS field.
	MDMA_CH_TCR_DINCOS_Msk = 0xc00
	// Position of SBURST field.
	MDMA_CH_TCR_SBURST_Pos = 0xc
	// Bit mask of SBURST field.
	MDMA_CH_TCR_SBURST_Msk = 0x7000
	// Position of DBURST field.
	MDMA_CH_TCR_DBURST_Pos = 0xf
	// Bit mask of DBURST field.
	MDMA_CH_TCR_DBURST_Msk = 0x38000
	// Position of TLEN field.
	MDMA_CH_TCR_TLEN_Pos = 0x12
	// Bit mask of TLEN field.
	MDMA_CH_TCR_TLEN_Msk = 0x1fc0000
	// Position of PKE field.
	MDMA_CH_TCR_PKE_Pos = 0x19
	// Bit mask of PKE field.
	MDMA_CH_TCR_PKE_Msk = 0x2000000
	// Bit PKE.
	MDMA_CH_TCR_PKE = 0x2000000
	// Position of PAM field.
	MDMA_CH_TCR_PAM_Pos = 0x1a
	// Bit mask of PAM field.
	MDMA_CH_TCR_PAM_Msk = 0xc000000
	// Position of TRGM field.
	MDMA_CH_TCR_TRGM_Pos = 0x1c
	// Bit mask of TRGM field.
	MDMA_CH_TCR_TRGM_Msk = 0x30000000
	// Position of SWRM field.
	MDMA_CH_TCR_SWRM_Pos = 0x1e
	// Bit mask of SWRM field.
	MDMA_CH_TCR_SWRM_Msk = 0x40000000
	// Bit SWRM.
	MDMA_CH_TCR_SWRM = 0x40000000
	// Position of BWM field.
	MDMA_CH_TCR_BWM_Pos = 0x1f
	// Bit mask of BWM field.
	MDMA_CH_TCR_BWM_Msk = 0x80000000
	// Bit BWM.
	MDMA_CH_TCR_BWM = 0x80000000

	// CH.BNDTR: MDMA Channel x block number of data register
	// Position of BNDT field.
	MDMA_CH_BNDTR_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	MDMA_CH_BNDTR_BNDT_Msk = 0x1ffff
	// Position of BRSUM field.
	MDMA_CH_BNDTR_BRSUM_Pos = 0x12
	// Bit mask of BRSUM field.
	MDMA_CH_BNDTR_BRSUM_Msk = 0x40000
	// Bit BRSUM.
	MDMA_CH_BNDTR_BRSUM = 0x40000
	// Position of BRDUM field.
	MDMA_CH_BNDTR_BRDUM_Pos = 0x13
	// Bit mask of BRDUM field.
	MDMA_CH_BNDTR_BRDUM_Msk = 0x80000
	// Bit BRDUM.
	MDMA_CH_BNDTR_BRDUM = 0x80000
	// Position of BRC field.
	MDMA_CH_BNDTR_BRC_Pos = 0x14
	// Bit mask of BRC field.
	MDMA_CH_BNDTR_BRC_Msk = 0xfff00000

	// CH.SAR: MDMA channel x source address register
	// Position of SAR field.
	MDMA_CH_SAR_SAR_Pos = 0x0
	// Bit mask of SAR field.
	MDMA_CH_SAR_SAR_Msk = 0xffffffff

	// CH.DAR: MDMA channel x destination address register
	// Position of DAR field.
	MDMA_CH_DAR_DAR_Pos = 0x0
	// Bit mask of DAR field.
	MDMA_CH_DAR_DAR_Msk = 0xffffffff

	// CH.BRUR: MDMA channel x Block Repeat address Update register
	// Position of SUV field.
	MDMA_CH_BRUR_SUV_Pos = 0x0
	// Bit mask of SUV field.
	MDMA_CH_BRUR_SUV_Msk = 0xffff
	// Position of DUV field.
	MDMA_CH_BRUR_DUV_Pos = 0x10
	// Bit mask of DUV field.
	MDMA_CH_BRUR_DUV_Msk = 0xffff0000

	// CH.LAR: MDMA channel x Link Address register
	// Position of LAR field.
	MDMA_CH_LAR_LAR_Pos = 0x0
	// Bit mask of LAR field.
	MDMA_CH_LAR_LAR_Msk = 0xffffffff

	// CH.TBR: MDMA channel x Trigger and Bus selection Register
	// Position of TSEL field.
	MDMA_CH_TBR_TSEL_Pos = 0x0
	// Bit mask of TSEL field.
	MDMA_CH_TBR_TSEL_Msk = 0x3f
	// Position of SBUS field.
	MDMA_CH_TBR_SBUS_Pos = 0x10
	// Bit mask of SBUS field.
	MDMA_CH_TBR_SBUS_Msk = 0x10000
	// Bit SBUS.
	MDMA_CH_TBR_SBUS = 0x10000
	// Position of DBUS field.
	MDMA_CH_TBR_DBUS_Pos = 0x11
	// Bit mask of DBUS field.
	MDMA_CH_TBR_DBUS_Msk = 0x20000
	// Bit DBUS.
	MDMA_CH_TBR_DBUS = 0x20000

	// CH.MAR: MDMA channel x Mask address register
	// Position of MAR field.
	MDMA_CH_MAR_MAR_Pos = 0x0
	// Bit mask of MAR field.
	MDMA_CH_MAR_MAR_Msk = 0xffffffff

	// CH.MDR: MDMA channel x Mask Data register
	// Position of MDR field.
	MDMA_CH_MDR_MDR_Pos = 0x0
	// Bit mask of MDR field.
	MDMA_CH_MDR_MDR_Msk = 0xffffffff
)

// Bitfields for QUADSPI: QUADSPI
const (
	// CR: QUADSPI control register
	// Position of EN field.
	QUADSPI_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	QUADSPI_CR_EN_Msk = 0x1
	// Bit EN.
	QUADSPI_CR_EN = 0x1
	// Position of ABORT field.
	QUADSPI_CR_ABORT_Pos = 0x1
	// Bit mask of ABORT field.
	QUADSPI_CR_ABORT_Msk = 0x2
	// Bit ABORT.
	QUADSPI_CR_ABORT = 0x2
	// Position of DMAEN field.
	QUADSPI_CR_DMAEN_Pos = 0x2
	// Bit mask of DMAEN field.
	QUADSPI_CR_DMAEN_Msk = 0x4
	// Bit DMAEN.
	QUADSPI_CR_DMAEN = 0x4
	// Position of TCEN field.
	QUADSPI_CR_TCEN_Pos = 0x3
	// Bit mask of TCEN field.
	QUADSPI_CR_TCEN_Msk = 0x8
	// Bit TCEN.
	QUADSPI_CR_TCEN = 0x8
	// Position of SSHIFT field.
	QUADSPI_CR_SSHIFT_Pos = 0x4
	// Bit mask of SSHIFT field.
	QUADSPI_CR_SSHIFT_Msk = 0x10
	// Bit SSHIFT.
	QUADSPI_CR_SSHIFT = 0x10
	// Position of DFM field.
	QUADSPI_CR_DFM_Pos = 0x6
	// Bit mask of DFM field.
	QUADSPI_CR_DFM_Msk = 0x40
	// Bit DFM.
	QUADSPI_CR_DFM = 0x40
	// Position of FSEL field.
	QUADSPI_CR_FSEL_Pos = 0x7
	// Bit mask of FSEL field.
	QUADSPI_CR_FSEL_Msk = 0x80
	// Bit FSEL.
	QUADSPI_CR_FSEL = 0x80
	// Position of FTHRES field.
	QUADSPI_CR_FTHRES_Pos = 0x8
	// Bit mask of FTHRES field.
	QUADSPI_CR_FTHRES_Msk = 0x1f00
	// Position of TEIE field.
	QUADSPI_CR_TEIE_Pos = 0x10
	// Bit mask of TEIE field.
	QUADSPI_CR_TEIE_Msk = 0x10000
	// Bit TEIE.
	QUADSPI_CR_TEIE = 0x10000
	// Position of TCIE field.
	QUADSPI_CR_TCIE_Pos = 0x11
	// Bit mask of TCIE field.
	QUADSPI_CR_TCIE_Msk = 0x20000
	// Bit TCIE.
	QUADSPI_CR_TCIE = 0x20000
	// Position of FTIE field.
	QUADSPI_CR_FTIE_Pos = 0x12
	// Bit mask of FTIE field.
	QUADSPI_CR_FTIE_Msk = 0x40000
	// Bit FTIE.
	QUADSPI_CR_FTIE = 0x40000
	// Position of SMIE field.
	QUADSPI_CR_SMIE_Pos = 0x13
	// Bit mask of SMIE field.
	QUADSPI_CR_SMIE_Msk = 0x80000
	// Bit SMIE.
	QUADSPI_CR_SMIE = 0x80000
	// Position of TOIE field.
	QUADSPI_CR_TOIE_Pos = 0x14
	// Bit mask of TOIE field.
	QUADSPI_CR_TOIE_Msk = 0x100000
	// Bit TOIE.
	QUADSPI_CR_TOIE = 0x100000
	// Position of APMS field.
	QUADSPI_CR_APMS_Pos = 0x16
	// Bit mask of APMS field.
	QUADSPI_CR_APMS_Msk = 0x400000
	// Bit APMS.
	QUADSPI_CR_APMS = 0x400000
	// Position of PMM field.
	QUADSPI_CR_PMM_Pos = 0x17
	// Bit mask of PMM field.
	QUADSPI_CR_PMM_Msk = 0x800000
	// Bit PMM.
	QUADSPI_CR_PMM = 0x800000
	// Position of PRESCALER field.
	QUADSPI_CR_PRESCALER_Pos = 0x18
	// Bit mask of PRESCALER field.
	QUADSPI_CR_PRESCALER_Msk = 0xff000000

	// DCR: QUADSPI device configuration register
	// Position of CKMODE field.
	QUADSPI_DCR_CKMODE_Pos = 0x0
	// Bit mask of CKMODE field.
	QUADSPI_DCR_CKMODE_Msk = 0x1
	// Bit CKMODE.
	QUADSPI_DCR_CKMODE = 0x1
	// Position of CSHT field.
	QUADSPI_DCR_CSHT_Pos = 0x8
	// Bit mask of CSHT field.
	QUADSPI_DCR_CSHT_Msk = 0x700
	// Position of FSIZE field.
	QUADSPI_DCR_FSIZE_Pos = 0x10
	// Bit mask of FSIZE field.
	QUADSPI_DCR_FSIZE_Msk = 0x1f0000

	// SR: QUADSPI status register
	// Position of TEF field.
	QUADSPI_SR_TEF_Pos = 0x0
	// Bit mask of TEF field.
	QUADSPI_SR_TEF_Msk = 0x1
	// Bit TEF.
	QUADSPI_SR_TEF = 0x1
	// Position of TCF field.
	QUADSPI_SR_TCF_Pos = 0x1
	// Bit mask of TCF field.
	QUADSPI_SR_TCF_Msk = 0x2
	// Bit TCF.
	QUADSPI_SR_TCF = 0x2
	// Position of FTF field.
	QUADSPI_SR_FTF_Pos = 0x2
	// Bit mask of FTF field.
	QUADSPI_SR_FTF_Msk = 0x4
	// Bit FTF.
	QUADSPI_SR_FTF = 0x4
	// Position of SMF field.
	QUADSPI_SR_SMF_Pos = 0x3
	// Bit mask of SMF field.
	QUADSPI_SR_SMF_Msk = 0x8
	// Bit SMF.
	QUADSPI_SR_SMF = 0x8
	// Position of TOF field.
	QUADSPI_SR_TOF_Pos = 0x4
	// Bit mask of TOF field.
	QUADSPI_SR_TOF_Msk = 0x10
	// Bit TOF.
	QUADSPI_SR_TOF = 0x10
	// Position of BUSY field.
	QUADSPI_SR_BUSY_Pos = 0x5
	// Bit mask of BUSY field.
	QUADSPI_SR_BUSY_Msk = 0x20
	// Bit BUSY.
	QUADSPI_SR_BUSY = 0x20
	// Position of FLEVEL field.
	QUADSPI_SR_FLEVEL_Pos = 0x8
	// Bit mask of FLEVEL field.
	QUADSPI_SR_FLEVEL_Msk = 0x3f00

	// FCR: QUADSPI flag clear register
	// Position of CTEF field.
	QUADSPI_FCR_CTEF_Pos = 0x0
	// Bit mask of CTEF field.
	QUADSPI_FCR_CTEF_Msk = 0x1
	// Bit CTEF.
	QUADSPI_FCR_CTEF = 0x1
	// Position of CTCF field.
	QUADSPI_FCR_CTCF_Pos = 0x1
	// Bit mask of CTCF field.
	QUADSPI_FCR_CTCF_Msk = 0x2
	// Bit CTCF.
	QUADSPI_FCR_CTCF = 0x2
	// Position of CSMF field.
	QUADSPI_FCR_CSMF_Pos = 0x3
	// Bit mask of CSMF field.
	QUADSPI_FCR_CSMF_Msk = 0x8
	// Bit CSMF.
	QUADSPI_FCR_CSMF = 0x8
	// Position of CTOF field.
	QUADSPI_FCR_CTOF_Pos = 0x4
	// Bit mask of CTOF field.
	QUADSPI_FCR_CTOF_Msk = 0x10
	// Bit CTOF.
	QUADSPI_FCR_CTOF = 0x10

	// DLR: QUADSPI data length register
	// Position of DL field.
	QUADSPI_DLR_DL_Pos = 0x0
	// Bit mask of DL field.
	QUADSPI_DLR_DL_Msk = 0xffffffff

	// CCR: QUADSPI communication configuration register
	// Position of INSTRUCTION field.
	QUADSPI_CCR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	QUADSPI_CCR_INSTRUCTION_Msk = 0xff
	// Position of IMODE field.
	QUADSPI_CCR_IMODE_Pos = 0x8
	// Bit mask of IMODE field.
	QUADSPI_CCR_IMODE_Msk = 0x300
	// Position of ADMODE field.
	QUADSPI_CCR_ADMODE_Pos = 0xa
	// Bit mask of ADMODE field.
	QUADSPI_CCR_ADMODE_Msk = 0xc00
	// Position of ADSIZE field.
	QUADSPI_CCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	QUADSPI_CCR_ADSIZE_Msk = 0x3000
	// Position of ABMODE field.
	QUADSPI_CCR_ABMODE_Pos = 0xe
	// Bit mask of ABMODE field.
	QUADSPI_CCR_ABMODE_Msk = 0xc000
	// Position of ABSIZE field.
	QUADSPI_CCR_ABSIZE_Pos = 0x10
	// Bit mask of ABSIZE field.
	QUADSPI_CCR_ABSIZE_Msk = 0x30000
	// Position of DCYC field.
	QUADSPI_CCR_DCYC_Pos = 0x12
	// Bit mask of DCYC field.
	QUADSPI_CCR_DCYC_Msk = 0x7c0000
	// Position of DMODE field.
	QUADSPI_CCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	QUADSPI_CCR_DMODE_Msk = 0x3000000
	// Position of FMODE field.
	QUADSPI_CCR_FMODE_Pos = 0x1a
	// Bit mask of FMODE field.
	QUADSPI_CCR_FMODE_Msk = 0xc000000
	// Position of SIOO field.
	QUADSPI_CCR_SIOO_Pos = 0x1c
	// Bit mask of SIOO field.
	QUADSPI_CCR_SIOO_Msk = 0x10000000
	// Bit SIOO.
	QUADSPI_CCR_SIOO = 0x10000000
	// Position of DHHC field.
	QUADSPI_CCR_DHHC_Pos = 0x1e
	// Bit mask of DHHC field.
	QUADSPI_CCR_DHHC_Msk = 0x40000000
	// Bit DHHC.
	QUADSPI_CCR_DHHC = 0x40000000
	// Position of DDRM field.
	QUADSPI_CCR_DDRM_Pos = 0x1f
	// Bit mask of DDRM field.
	QUADSPI_CCR_DDRM_Msk = 0x80000000
	// Bit DDRM.
	QUADSPI_CCR_DDRM = 0x80000000

	// AR: QUADSPI address register
	// Position of ADDRESS field.
	QUADSPI_AR_ADDRESS_Pos = 0x0
	// Bit mask of ADDRESS field.
	QUADSPI_AR_ADDRESS_Msk = 0xffffffff

	// ABR: QUADSPI alternate bytes registers
	// Position of ALTERNATE field.
	QUADSPI_ABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	QUADSPI_ABR_ALTERNATE_Msk = 0xffffffff

	// DR: QUADSPI data register
	// Position of DATA field.
	QUADSPI_DR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	QUADSPI_DR_DATA_Msk = 0xffffffff

	// PSMKR: QUADSPI polling status mask register
	// Position of MASK field.
	QUADSPI_PSMKR_MASK_Pos = 0x0
	// Bit mask of MASK field.
	QUADSPI_PSMKR_MASK_Msk = 0xffffffff

	// PSMAR: QUADSPI polling status match register
	// Position of MATCH field.
	QUADSPI_PSMAR_MATCH_Pos = 0x0
	// Bit mask of MATCH field.
	QUADSPI_PSMAR_MATCH_Msk = 0xffffffff

	// PIR: QUADSPI polling interval register
	// Position of INTERVAL field.
	QUADSPI_PIR_INTERVAL_Pos = 0x0
	// Bit mask of INTERVAL field.
	QUADSPI_PIR_INTERVAL_Msk = 0xffff

	// LPTR: QUADSPI low-power timeout register
	// Position of TIMEOUT field.
	QUADSPI_LPTR_TIMEOUT_Pos = 0x0
	// Bit mask of TIMEOUT field.
	QUADSPI_LPTR_TIMEOUT_Msk = 0xffff
)

// Bitfields for RNG: RNG
const (
	// CR: RNG control register
	// Position of RNGEN field.
	RNG_CR_RNGEN_Pos = 0x2
	// Bit mask of RNGEN field.
	RNG_CR_RNGEN_Msk = 0x4
	// Bit RNGEN.
	RNG_CR_RNGEN = 0x4
	// Random number generator is disabled
	RNG_CR_RNGEN_Disabled = 0x0
	// Random number generator is enabled
	RNG_CR_RNGEN_Enabled = 0x1
	// Position of IE field.
	RNG_CR_IE_Pos = 0x3
	// Bit mask of IE field.
	RNG_CR_IE_Msk = 0x8
	// Bit IE.
	RNG_CR_IE = 0x8
	// RNG interrupt is disabled
	RNG_CR_IE_Disabled = 0x0
	// RNG interrupt is enabled
	RNG_CR_IE_Enabled = 0x1
	// Position of CED field.
	RNG_CR_CED_Pos = 0x5
	// Bit mask of CED field.
	RNG_CR_CED_Msk = 0x20
	// Bit CED.
	RNG_CR_CED = 0x20
	// Clock error detection is enabled
	RNG_CR_CED_Enabled = 0x0
	// Clock error detection is disabled
	RNG_CR_CED_Disabled = 0x1

	// SR: RNG status register
	// Position of DRDY field.
	RNG_SR_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	RNG_SR_DRDY_Msk = 0x1
	// Bit DRDY.
	RNG_SR_DRDY = 0x1
	// Position of CECS field.
	RNG_SR_CECS_Pos = 0x1
	// Bit mask of CECS field.
	RNG_SR_CECS_Msk = 0x2
	// Bit CECS.
	RNG_SR_CECS = 0x2
	// Position of SECS field.
	RNG_SR_SECS_Pos = 0x2
	// Bit mask of SECS field.
	RNG_SR_SECS_Msk = 0x4
	// Bit SECS.
	RNG_SR_SECS = 0x4
	// Position of CEIS field.
	RNG_SR_CEIS_Pos = 0x5
	// Bit mask of CEIS field.
	RNG_SR_CEIS_Msk = 0x20
	// Bit CEIS.
	RNG_SR_CEIS = 0x20
	// Position of SEIS field.
	RNG_SR_SEIS_Pos = 0x6
	// Bit mask of SEIS field.
	RNG_SR_SEIS_Msk = 0x40
	// Bit SEIS.
	RNG_SR_SEIS = 0x40

	// DR: The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.
	// Position of RNDATA field.
	RNG_DR_RNDATA_Pos = 0x0
	// Bit mask of RNDATA field.
	RNG_DR_RNDATA_Msk = 0xffffffff
)

// Bitfields for RTC: RTC
const (
	// TR: The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of SU field.
	RTC_TR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_TR_SU_Msk = 0xf
	// Position of ST field.
	RTC_TR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_TR_ST_Msk = 0x70
	// Position of MNU field.
	RTC_TR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_TR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_TR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_TR_MNT_Msk = 0x7000
	// Position of HU field.
	RTC_TR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_TR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_TR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_TR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_TR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_TR_PM_Msk = 0x400000
	// Bit PM.
	RTC_TR_PM = 0x400000
	// AM or 24-hour format
	RTC_TR_PM_AM = 0x0
	// PM
	RTC_TR_PM_PM = 0x1

	// DR: The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of DU field.
	RTC_DR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_DR_DU_Msk = 0xf
	// Position of DT field.
	RTC_DR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_DR_DT_Msk = 0x30
	// Position of MU field.
	RTC_DR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_DR_MU_Msk = 0xf00
	// Position of MT field.
	RTC_DR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_DR_MT_Msk = 0x1000
	// Bit MT.
	RTC_DR_MT = 0x1000
	// Position of WDU field.
	RTC_DR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_DR_WDU_Msk = 0xe000
	// Position of YU field.
	RTC_DR_YU_Pos = 0x10
	// Bit mask of YU field.
	RTC_DR_YU_Msk = 0xf0000
	// Position of YT field.
	RTC_DR_YT_Pos = 0x14
	// Bit mask of YT field.
	RTC_DR_YT_Msk = 0xf00000

	// CR: RTC control register
	// Position of WUCKSEL field.
	RTC_CR_WUCKSEL_Pos = 0x0
	// Bit mask of WUCKSEL field.
	RTC_CR_WUCKSEL_Msk = 0x7
	// RTC/16 clock is selected
	RTC_CR_WUCKSEL_Div16 = 0x0
	// RTC/8 clock is selected
	RTC_CR_WUCKSEL_Div8 = 0x1
	// RTC/4 clock is selected
	RTC_CR_WUCKSEL_Div4 = 0x2
	// RTC/2 clock is selected
	RTC_CR_WUCKSEL_Div2 = 0x3
	// ck_spre (usually 1 Hz) clock is selected
	RTC_CR_WUCKSEL_ClockSpare = 0x4
	// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
	RTC_CR_WUCKSEL_ClockSpareWithOffset = 0x6
	// Position of TSEDGE field.
	RTC_CR_TSEDGE_Pos = 0x3
	// Bit mask of TSEDGE field.
	RTC_CR_TSEDGE_Msk = 0x8
	// Bit TSEDGE.
	RTC_CR_TSEDGE = 0x8
	// RTC_TS input rising edge generates a time-stamp event
	RTC_CR_TSEDGE_RisingEdge = 0x0
	// RTC_TS input falling edge generates a time-stamp event
	RTC_CR_TSEDGE_FallingEdge = 0x1
	// Position of REFCKON field.
	RTC_CR_REFCKON_Pos = 0x4
	// Bit mask of REFCKON field.
	RTC_CR_REFCKON_Msk = 0x10
	// Bit REFCKON.
	RTC_CR_REFCKON = 0x10
	// RTC_REFIN detection disabled
	RTC_CR_REFCKON_Disabled = 0x0
	// RTC_REFIN detection enabled
	RTC_CR_REFCKON_Enabled = 0x1
	// Position of BYPSHAD field.
	RTC_CR_BYPSHAD_Pos = 0x5
	// Bit mask of BYPSHAD field.
	RTC_CR_BYPSHAD_Msk = 0x20
	// Bit BYPSHAD.
	RTC_CR_BYPSHAD = 0x20
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
	RTC_CR_BYPSHAD_ShadowReg = 0x0
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
	RTC_CR_BYPSHAD_BypassShadowReg = 0x1
	// Position of FMT field.
	RTC_CR_FMT_Pos = 0x6
	// Bit mask of FMT field.
	RTC_CR_FMT_Msk = 0x40
	// Bit FMT.
	RTC_CR_FMT = 0x40
	// 24 hour/day format
	RTC_CR_FMT_Twenty_Four_Hour = 0x0
	// AM/PM hour format
	RTC_CR_FMT_AM_PM = 0x1
	// Position of ALRAE field.
	RTC_CR_ALRAE_Pos = 0x8
	// Bit mask of ALRAE field.
	RTC_CR_ALRAE_Msk = 0x100
	// Bit ALRAE.
	RTC_CR_ALRAE = 0x100
	// Alarm A disabled
	RTC_CR_ALRAE_Disabled = 0x0
	// Alarm A enabled
	RTC_CR_ALRAE_Enabled = 0x1
	// Position of ALRBE field.
	RTC_CR_ALRBE_Pos = 0x9
	// Bit mask of ALRBE field.
	RTC_CR_ALRBE_Msk = 0x200
	// Bit ALRBE.
	RTC_CR_ALRBE = 0x200
	// Alarm B disabled
	RTC_CR_ALRBE_Disabled = 0x0
	// Alarm B enabled
	RTC_CR_ALRBE_Enabled = 0x1
	// Position of WUTE field.
	RTC_CR_WUTE_Pos = 0xa
	// Bit mask of WUTE field.
	RTC_CR_WUTE_Msk = 0x400
	// Bit WUTE.
	RTC_CR_WUTE = 0x400
	// Wakeup timer disabled
	RTC_CR_WUTE_Disabled = 0x0
	// Wakeup timer enabled
	RTC_CR_WUTE_Enabled = 0x1
	// Position of TSE field.
	RTC_CR_TSE_Pos = 0xb
	// Bit mask of TSE field.
	RTC_CR_TSE_Msk = 0x800
	// Bit TSE.
	RTC_CR_TSE = 0x800
	// Timestamp disabled
	RTC_CR_TSE_Disabled = 0x0
	// Timestamp enabled
	RTC_CR_TSE_Enabled = 0x1
	// Position of ALRAIE field.
	RTC_CR_ALRAIE_Pos = 0xc
	// Bit mask of ALRAIE field.
	RTC_CR_ALRAIE_Msk = 0x1000
	// Bit ALRAIE.
	RTC_CR_ALRAIE = 0x1000
	// Alarm A interrupt disabled
	RTC_CR_ALRAIE_Disabled = 0x0
	// Alarm A interrupt enabled
	RTC_CR_ALRAIE_Enabled = 0x1
	// Position of ALRBIE field.
	RTC_CR_ALRBIE_Pos = 0xd
	// Bit mask of ALRBIE field.
	RTC_CR_ALRBIE_Msk = 0x2000
	// Bit ALRBIE.
	RTC_CR_ALRBIE = 0x2000
	// Alarm B Interrupt disabled
	RTC_CR_ALRBIE_Disabled = 0x0
	// Alarm B Interrupt enabled
	RTC_CR_ALRBIE_Enabled = 0x1
	// Position of WUTIE field.
	RTC_CR_WUTIE_Pos = 0xe
	// Bit mask of WUTIE field.
	RTC_CR_WUTIE_Msk = 0x4000
	// Bit WUTIE.
	RTC_CR_WUTIE = 0x4000
	// Wakeup timer interrupt disabled
	RTC_CR_WUTIE_Disabled = 0x0
	// Wakeup timer interrupt enabled
	RTC_CR_WUTIE_Enabled = 0x1
	// Position of TSIE field.
	RTC_CR_TSIE_Pos = 0xf
	// Bit mask of TSIE field.
	RTC_CR_TSIE_Msk = 0x8000
	// Bit TSIE.
	RTC_CR_TSIE = 0x8000
	// Time-stamp Interrupt disabled
	RTC_CR_TSIE_Disabled = 0x0
	// Time-stamp Interrupt enabled
	RTC_CR_TSIE_Enabled = 0x1
	// Position of ADD1H field.
	RTC_CR_ADD1H_Pos = 0x10
	// Bit mask of ADD1H field.
	RTC_CR_ADD1H_Msk = 0x10000
	// Bit ADD1H.
	RTC_CR_ADD1H = 0x10000
	// Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
	RTC_CR_ADD1H_Add1 = 0x1
	// Position of SUB1H field.
	RTC_CR_SUB1H_Pos = 0x11
	// Bit mask of SUB1H field.
	RTC_CR_SUB1H_Msk = 0x20000
	// Bit SUB1H.
	RTC_CR_SUB1H = 0x20000
	// Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
	RTC_CR_SUB1H_Sub1 = 0x1
	// Position of BKP field.
	RTC_CR_BKP_Pos = 0x12
	// Bit mask of BKP field.
	RTC_CR_BKP_Msk = 0x40000
	// Bit BKP.
	RTC_CR_BKP = 0x40000
	// Daylight Saving Time change has not been performed
	RTC_CR_BKP_DST_Not_Changed = 0x0
	// Daylight Saving Time change has been performed
	RTC_CR_BKP_DST_Changed = 0x1
	// Position of COSEL field.
	RTC_CR_COSEL_Pos = 0x13
	// Bit mask of COSEL field.
	RTC_CR_COSEL_Msk = 0x80000
	// Bit COSEL.
	RTC_CR_COSEL = 0x80000
	// Calibration output is 512 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_512Hz = 0x0
	// Calibration output is 1 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_1Hz = 0x1
	// Position of POL field.
	RTC_CR_POL_Pos = 0x14
	// Bit mask of POL field.
	RTC_CR_POL_Msk = 0x100000
	// Bit POL.
	RTC_CR_POL = 0x100000
	// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_High = 0x0
	// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_Low = 0x1
	// Position of OSEL field.
	RTC_CR_OSEL_Pos = 0x15
	// Bit mask of OSEL field.
	RTC_CR_OSEL_Msk = 0x600000
	// Output disabled
	RTC_CR_OSEL_Disabled = 0x0
	// Alarm A output enabled
	RTC_CR_OSEL_AlarmA = 0x1
	// Alarm B output enabled
	RTC_CR_OSEL_AlarmB = 0x2
	// Wakeup output enabled
	RTC_CR_OSEL_Wakeup = 0x3
	// Position of COE field.
	RTC_CR_COE_Pos = 0x17
	// Bit mask of COE field.
	RTC_CR_COE_Msk = 0x800000
	// Bit COE.
	RTC_CR_COE = 0x800000
	// Calibration output disabled
	RTC_CR_COE_Disabled = 0x0
	// Calibration output enabled
	RTC_CR_COE_Enabled = 0x1
	// Position of ITSE field.
	RTC_CR_ITSE_Pos = 0x18
	// Bit mask of ITSE field.
	RTC_CR_ITSE_Msk = 0x1000000
	// Bit ITSE.
	RTC_CR_ITSE = 0x1000000
	// Internal event timestamp is disabled
	RTC_CR_ITSE_Disabled = 0x0
	// Internal event timestamp is enabled
	RTC_CR_ITSE_Enabled = 0x1

	// ISR: This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9.
	// Position of ALRAWF field.
	RTC_ISR_ALRAWF_Pos = 0x0
	// Bit mask of ALRAWF field.
	RTC_ISR_ALRAWF_Msk = 0x1
	// Bit ALRAWF.
	RTC_ISR_ALRAWF = 0x1
	// Alarm update not allowed
	RTC_ISR_ALRAWF_UpdateNotAllowed = 0x0
	// Alarm update allowed
	RTC_ISR_ALRAWF_UpdateAllowed = 0x1
	// Position of ALRBWF field.
	RTC_ISR_ALRBWF_Pos = 0x1
	// Bit mask of ALRBWF field.
	RTC_ISR_ALRBWF_Msk = 0x2
	// Bit ALRBWF.
	RTC_ISR_ALRBWF = 0x2
	// Alarm update not allowed
	RTC_ISR_ALRBWF_UpdateNotAllowed = 0x0
	// Alarm update allowed
	RTC_ISR_ALRBWF_UpdateAllowed = 0x1
	// Position of WUTWF field.
	RTC_ISR_WUTWF_Pos = 0x2
	// Bit mask of WUTWF field.
	RTC_ISR_WUTWF_Msk = 0x4
	// Bit WUTWF.
	RTC_ISR_WUTWF = 0x4
	// Wakeup timer configuration update not allowed
	RTC_ISR_WUTWF_UpdateNotAllowed = 0x0
	// Wakeup timer configuration update allowed
	RTC_ISR_WUTWF_UpdateAllowed = 0x1
	// Position of SHPF field.
	RTC_ISR_SHPF_Pos = 0x3
	// Bit mask of SHPF field.
	RTC_ISR_SHPF_Msk = 0x8
	// Bit SHPF.
	RTC_ISR_SHPF = 0x8
	// No shift operation is pending
	RTC_ISR_SHPF_NoShiftPending = 0x0
	// A shift operation is pending
	RTC_ISR_SHPF_ShiftPending = 0x1
	// Position of INITS field.
	RTC_ISR_INITS_Pos = 0x4
	// Bit mask of INITS field.
	RTC_ISR_INITS_Msk = 0x10
	// Bit INITS.
	RTC_ISR_INITS = 0x10
	// Calendar has not been initialized
	RTC_ISR_INITS_NotInitalized = 0x0
	// Calendar has been initialized
	RTC_ISR_INITS_Initalized = 0x1
	// Position of RSF field.
	RTC_ISR_RSF_Pos = 0x5
	// Bit mask of RSF field.
	RTC_ISR_RSF_Msk = 0x20
	// Bit RSF.
	RTC_ISR_RSF = 0x20
	// Calendar shadow registers not yet synchronized
	RTC_ISR_RSF_NotSynced = 0x0
	// Calendar shadow registers synchronized
	RTC_ISR_RSF_Synced = 0x1
	// This flag is cleared by software by writing 0
	RTC_ISR_RSF_Clear = 0x0
	// Position of INITF field.
	RTC_ISR_INITF_Pos = 0x6
	// Bit mask of INITF field.
	RTC_ISR_INITF_Msk = 0x40
	// Bit INITF.
	RTC_ISR_INITF = 0x40
	// Calendar registers update is not allowed
	RTC_ISR_INITF_NotAllowed = 0x0
	// Calendar registers update is allowed
	RTC_ISR_INITF_Allowed = 0x1
	// Position of INIT field.
	RTC_ISR_INIT_Pos = 0x7
	// Bit mask of INIT field.
	RTC_ISR_INIT_Msk = 0x80
	// Bit INIT.
	RTC_ISR_INIT = 0x80
	// Free running mode
	RTC_ISR_INIT_FreeRunningMode = 0x0
	// Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
	RTC_ISR_INIT_InitMode = 0x1
	// Position of ALRAF field.
	RTC_ISR_ALRAF_Pos = 0x8
	// Bit mask of ALRAF field.
	RTC_ISR_ALRAF_Msk = 0x100
	// Bit ALRAF.
	RTC_ISR_ALRAF = 0x100
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
	RTC_ISR_ALRAF_Match = 0x1
	// This flag is cleared by software by writing 0
	RTC_ISR_ALRAF_Clear = 0x0
	// Position of ALRBF field.
	RTC_ISR_ALRBF_Pos = 0x9
	// Bit mask of ALRBF field.
	RTC_ISR_ALRBF_Msk = 0x200
	// Bit ALRBF.
	RTC_ISR_ALRBF = 0x200
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)
	RTC_ISR_ALRBF_Match = 0x1
	// This flag is cleared by software by writing 0
	RTC_ISR_ALRBF_Clear = 0x0
	// Position of WUTF field.
	RTC_ISR_WUTF_Pos = 0xa
	// Bit mask of WUTF field.
	RTC_ISR_WUTF_Msk = 0x400
	// Bit WUTF.
	RTC_ISR_WUTF = 0x400
	// This flag is set by hardware when the wakeup auto-reload counter reaches 0
	RTC_ISR_WUTF_Zero = 0x1
	// This flag is cleared by software by writing 0
	RTC_ISR_WUTF_Clear = 0x0
	// Position of TSF field.
	RTC_ISR_TSF_Pos = 0xb
	// Bit mask of TSF field.
	RTC_ISR_TSF_Msk = 0x800
	// Bit TSF.
	RTC_ISR_TSF = 0x800
	// This flag is set by hardware when a time-stamp event occurs
	RTC_ISR_TSF_TimestampEvent = 0x1
	// This flag is cleared by software by writing 0
	RTC_ISR_TSF_Clear = 0x0
	// Position of TSOVF field.
	RTC_ISR_TSOVF_Pos = 0xc
	// Bit mask of TSOVF field.
	RTC_ISR_TSOVF_Msk = 0x1000
	// Bit TSOVF.
	RTC_ISR_TSOVF = 0x1000
	// This flag is set by hardware when a time-stamp event occurs while TSF is already set
	RTC_ISR_TSOVF_Overflow = 0x1
	// This flag is cleared by software by writing 0
	RTC_ISR_TSOVF_Clear = 0x0
	// Position of TAMP1F field.
	RTC_ISR_TAMP1F_Pos = 0xd
	// Bit mask of TAMP1F field.
	RTC_ISR_TAMP1F_Msk = 0x2000
	// Bit TAMP1F.
	RTC_ISR_TAMP1F = 0x2000
	// This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
	RTC_ISR_TAMP1F_Tampered = 0x1
	// Flag cleared by software writing 0
	RTC_ISR_TAMP1F_Clear = 0x0
	// Position of TAMP2F field.
	RTC_ISR_TAMP2F_Pos = 0xe
	// Bit mask of TAMP2F field.
	RTC_ISR_TAMP2F_Msk = 0x4000
	// Bit TAMP2F.
	RTC_ISR_TAMP2F = 0x4000
	// This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
	RTC_ISR_TAMP2F_Tampered = 0x1
	// Flag cleared by software writing 0
	RTC_ISR_TAMP2F_Clear = 0x0
	// Position of TAMP3F field.
	RTC_ISR_TAMP3F_Pos = 0xf
	// Bit mask of TAMP3F field.
	RTC_ISR_TAMP3F_Msk = 0x8000
	// Bit TAMP3F.
	RTC_ISR_TAMP3F = 0x8000
	// This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
	RTC_ISR_TAMP3F_Tampered = 0x1
	// Flag cleared by software writing 0
	RTC_ISR_TAMP3F_Clear = 0x0
	// Position of RECALPF field.
	RTC_ISR_RECALPF_Pos = 0x10
	// Bit mask of RECALPF field.
	RTC_ISR_RECALPF_Msk = 0x10000
	// Bit RECALPF.
	RTC_ISR_RECALPF = 0x10000
	// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
	RTC_ISR_RECALPF_Pending = 0x1
	// Position of ITSF field.
	RTC_ISR_ITSF_Pos = 0x11
	// Bit mask of ITSF field.
	RTC_ISR_ITSF_Msk = 0x20000
	// Bit ITSF.
	RTC_ISR_ITSF = 0x20000
	// This flag is set by hardware when a time-stamp on the internal event occurs
	RTC_ISR_ITSF_Match = 0x1
	// This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits
	RTC_ISR_ITSF_Clear = 0x0

	// PRER: This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of PREDIV_S field.
	RTC_PRER_PREDIV_S_Pos = 0x0
	// Bit mask of PREDIV_S field.
	RTC_PRER_PREDIV_S_Msk = 0x7fff
	// Position of PREDIV_A field.
	RTC_PRER_PREDIV_A_Pos = 0x10
	// Bit mask of PREDIV_A field.
	RTC_PRER_PREDIV_A_Msk = 0x7f0000

	// WUTR: This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of WUT field.
	RTC_WUTR_WUT_Pos = 0x0
	// Bit mask of WUT field.
	RTC_WUTR_WUT_Msk = 0xffff

	// ALRMAR: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of SU field.
	RTC_ALRMAR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_ALRMAR_SU_Msk = 0xf
	// Position of ST field.
	RTC_ALRMAR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_ALRMAR_ST_Msk = 0x70
	// Position of MSK1 field.
	RTC_ALRMAR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_ALRMAR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_ALRMAR_MSK1 = 0x80
	// Alarm set if the date/day match
	RTC_ALRMAR_MSK1_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMAR_MSK1_NotMask = 0x1
	// Position of MNU field.
	RTC_ALRMAR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_ALRMAR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_ALRMAR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_ALRMAR_MNT_Msk = 0x7000
	// Position of MSK2 field.
	RTC_ALRMAR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_ALRMAR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_ALRMAR_MSK2 = 0x8000
	// Alarm set if the date/day match
	RTC_ALRMAR_MSK2_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMAR_MSK2_NotMask = 0x1
	// Position of HU field.
	RTC_ALRMAR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_ALRMAR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_ALRMAR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_ALRMAR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_ALRMAR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_ALRMAR_PM_Msk = 0x400000
	// Bit PM.
	RTC_ALRMAR_PM = 0x400000
	// AM or 24-hour format
	RTC_ALRMAR_PM_AM = 0x0
	// PM
	RTC_ALRMAR_PM_PM = 0x1
	// Position of MSK3 field.
	RTC_ALRMAR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_ALRMAR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_ALRMAR_MSK3 = 0x800000
	// Alarm set if the date/day match
	RTC_ALRMAR_MSK3_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMAR_MSK3_NotMask = 0x1
	// Position of DU field.
	RTC_ALRMAR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_ALRMAR_DU_Msk = 0xf000000
	// Position of DT field.
	RTC_ALRMAR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_ALRMAR_DT_Msk = 0x30000000
	// Position of WDSEL field.
	RTC_ALRMAR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_ALRMAR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_ALRMAR_WDSEL = 0x40000000
	// DU[3:0] represents the date units
	RTC_ALRMAR_WDSEL_DateUnits = 0x0
	// DU[3:0] represents the week day. DT[1:0] is don’t care.
	RTC_ALRMAR_WDSEL_WeekDay = 0x1
	// Position of MSK4 field.
	RTC_ALRMAR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_ALRMAR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_ALRMAR_MSK4 = 0x80000000
	// Alarm set if the date/day match
	RTC_ALRMAR_MSK4_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMAR_MSK4_NotMask = 0x1

	// ALRMBR: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of SU field.
	RTC_ALRMBR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_ALRMBR_SU_Msk = 0xf
	// Position of ST field.
	RTC_ALRMBR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_ALRMBR_ST_Msk = 0x70
	// Position of MSK1 field.
	RTC_ALRMBR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_ALRMBR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_ALRMBR_MSK1 = 0x80
	// Alarm set if the date/day match
	RTC_ALRMBR_MSK1_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMBR_MSK1_NotMask = 0x1
	// Position of MNU field.
	RTC_ALRMBR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_ALRMBR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_ALRMBR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_ALRMBR_MNT_Msk = 0x7000
	// Position of MSK2 field.
	RTC_ALRMBR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_ALRMBR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_ALRMBR_MSK2 = 0x8000
	// Alarm set if the date/day match
	RTC_ALRMBR_MSK2_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMBR_MSK2_NotMask = 0x1
	// Position of HU field.
	RTC_ALRMBR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_ALRMBR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_ALRMBR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_ALRMBR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_ALRMBR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_ALRMBR_PM_Msk = 0x400000
	// Bit PM.
	RTC_ALRMBR_PM = 0x400000
	// AM or 24-hour format
	RTC_ALRMBR_PM_AM = 0x0
	// PM
	RTC_ALRMBR_PM_PM = 0x1
	// Position of MSK3 field.
	RTC_ALRMBR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_ALRMBR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_ALRMBR_MSK3 = 0x800000
	// Alarm set if the date/day match
	RTC_ALRMBR_MSK3_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMBR_MSK3_NotMask = 0x1
	// Position of DU field.
	RTC_ALRMBR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_ALRMBR_DU_Msk = 0xf000000
	// Position of DT field.
	RTC_ALRMBR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_ALRMBR_DT_Msk = 0x30000000
	// Position of WDSEL field.
	RTC_ALRMBR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_ALRMBR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_ALRMBR_WDSEL = 0x40000000
	// DU[3:0] represents the date units
	RTC_ALRMBR_WDSEL_DateUnits = 0x0
	// DU[3:0] represents the week day. DT[1:0] is don’t care.
	RTC_ALRMBR_WDSEL_WeekDay = 0x1
	// Position of MSK4 field.
	RTC_ALRMBR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_ALRMBR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_ALRMBR_MSK4 = 0x80000000
	// Alarm set if the date/day match
	RTC_ALRMBR_MSK4_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMBR_MSK4_NotMask = 0x1

	// WPR: RTC write protection register
	// Position of KEY field.
	RTC_WPR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	RTC_WPR_KEY_Msk = 0xff

	// SSR: RTC sub second register
	// Position of SS field.
	RTC_SSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_SSR_SS_Msk = 0xffff

	// SHIFTR: This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of SUBFS field.
	RTC_SHIFTR_SUBFS_Pos = 0x0
	// Bit mask of SUBFS field.
	RTC_SHIFTR_SUBFS_Msk = 0x7fff
	// Position of ADD1S field.
	RTC_SHIFTR_ADD1S_Pos = 0x1f
	// Bit mask of ADD1S field.
	RTC_SHIFTR_ADD1S_Msk = 0x80000000
	// Bit ADD1S.
	RTC_SHIFTR_ADD1S = 0x80000000
	// Add one second to the clock/calendar
	RTC_SHIFTR_ADD1S_Add1 = 0x1

	// TSTR: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
	// Position of SU field.
	RTC_TSTR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_TSTR_SU_Msk = 0xf
	// Position of ST field.
	RTC_TSTR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_TSTR_ST_Msk = 0x70
	// Position of MNU field.
	RTC_TSTR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_TSTR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_TSTR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_TSTR_MNT_Msk = 0x7000
	// Position of HU field.
	RTC_TSTR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_TSTR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_TSTR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_TSTR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_TSTR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_TSTR_PM_Msk = 0x400000
	// Bit PM.
	RTC_TSTR_PM = 0x400000

	// TSDR: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
	// Position of DU field.
	RTC_TSDR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_TSDR_DU_Msk = 0xf
	// Position of DT field.
	RTC_TSDR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_TSDR_DT_Msk = 0x30
	// Position of MU field.
	RTC_TSDR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_TSDR_MU_Msk = 0xf00
	// Position of MT field.
	RTC_TSDR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_TSDR_MT_Msk = 0x1000
	// Bit MT.
	RTC_TSDR_MT = 0x1000
	// Position of WDU field.
	RTC_TSDR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_TSDR_WDU_Msk = 0xe000

	// TSSSR: The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset.
	// Position of SS field.
	RTC_TSSSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_TSSSR_SS_Msk = 0xffff

	// CALR: This register is write protected. The write access procedure is described in RTC register write protection on page9.
	// Position of CALM field.
	RTC_CALR_CALM_Pos = 0x0
	// Bit mask of CALM field.
	RTC_CALR_CALM_Msk = 0x1ff
	// Position of CALW16 field.
	RTC_CALR_CALW16_Pos = 0xd
	// Bit mask of CALW16 field.
	RTC_CALR_CALW16_Msk = 0x2000
	// Bit CALW16.
	RTC_CALR_CALW16 = 0x2000
	// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
	RTC_CALR_CALW16_Sixteen_Second = 0x1
	// Position of CALW8 field.
	RTC_CALR_CALW8_Pos = 0xe
	// Bit mask of CALW8 field.
	RTC_CALR_CALW8_Msk = 0x4000
	// Bit CALW8.
	RTC_CALR_CALW8 = 0x4000
	// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
	RTC_CALR_CALW8_Eight_Second = 0x1
	// Position of CALP field.
	RTC_CALR_CALP_Pos = 0xf
	// Bit mask of CALP field.
	RTC_CALR_CALP_Msk = 0x8000
	// Bit CALP.
	RTC_CALR_CALP = 0x8000
	// No RTCCLK pulses are added
	RTC_CALR_CALP_NoChange = 0x0
	// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
	RTC_CALR_CALP_IncreaseFreq = 0x1

	// TAMPCR: RTC tamper and alternate function configuration register
	// Position of TAMP1E field.
	RTC_TAMPCR_TAMP1E_Pos = 0x0
	// Bit mask of TAMP1E field.
	RTC_TAMPCR_TAMP1E_Msk = 0x1
	// Bit TAMP1E.
	RTC_TAMPCR_TAMP1E = 0x1
	// Position of TAMP1TRG field.
	RTC_TAMPCR_TAMP1TRG_Pos = 0x1
	// Bit mask of TAMP1TRG field.
	RTC_TAMPCR_TAMP1TRG_Msk = 0x2
	// Bit TAMP1TRG.
	RTC_TAMPCR_TAMP1TRG = 0x2
	// Position of TAMPIE field.
	RTC_TAMPCR_TAMPIE_Pos = 0x2
	// Bit mask of TAMPIE field.
	RTC_TAMPCR_TAMPIE_Msk = 0x4
	// Bit TAMPIE.
	RTC_TAMPCR_TAMPIE = 0x4
	// Position of TAMP2E field.
	RTC_TAMPCR_TAMP2E_Pos = 0x3
	// Bit mask of TAMP2E field.
	RTC_TAMPCR_TAMP2E_Msk = 0x8
	// Bit TAMP2E.
	RTC_TAMPCR_TAMP2E = 0x8
	// Position of TAMP2TRG field.
	RTC_TAMPCR_TAMP2TRG_Pos = 0x4
	// Bit mask of TAMP2TRG field.
	RTC_TAMPCR_TAMP2TRG_Msk = 0x10
	// Bit TAMP2TRG.
	RTC_TAMPCR_TAMP2TRG = 0x10
	// Position of TAMP3E field.
	RTC_TAMPCR_TAMP3E_Pos = 0x5
	// Bit mask of TAMP3E field.
	RTC_TAMPCR_TAMP3E_Msk = 0x20
	// Bit TAMP3E.
	RTC_TAMPCR_TAMP3E = 0x20
	// Position of TAMP3TRG field.
	RTC_TAMPCR_TAMP3TRG_Pos = 0x6
	// Bit mask of TAMP3TRG field.
	RTC_TAMPCR_TAMP3TRG_Msk = 0x40
	// Bit TAMP3TRG.
	RTC_TAMPCR_TAMP3TRG = 0x40
	// Position of TAMPTS field.
	RTC_TAMPCR_TAMPTS_Pos = 0x7
	// Bit mask of TAMPTS field.
	RTC_TAMPCR_TAMPTS_Msk = 0x80
	// Bit TAMPTS.
	RTC_TAMPCR_TAMPTS = 0x80
	// Position of TAMPFREQ field.
	RTC_TAMPCR_TAMPFREQ_Pos = 0x8
	// Bit mask of TAMPFREQ field.
	RTC_TAMPCR_TAMPFREQ_Msk = 0x700
	// Position of TAMPFLT field.
	RTC_TAMPCR_TAMPFLT_Pos = 0xb
	// Bit mask of TAMPFLT field.
	RTC_TAMPCR_TAMPFLT_Msk = 0x1800
	// Position of TAMPPRCH field.
	RTC_TAMPCR_TAMPPRCH_Pos = 0xd
	// Bit mask of TAMPPRCH field.
	RTC_TAMPCR_TAMPPRCH_Msk = 0x6000
	// Position of TAMPPUDIS field.
	RTC_TAMPCR_TAMPPUDIS_Pos = 0xf
	// Bit mask of TAMPPUDIS field.
	RTC_TAMPCR_TAMPPUDIS_Msk = 0x8000
	// Bit TAMPPUDIS.
	RTC_TAMPCR_TAMPPUDIS = 0x8000
	// Position of TAMP1IE field.
	RTC_TAMPCR_TAMP1IE_Pos = 0x10
	// Bit mask of TAMP1IE field.
	RTC_TAMPCR_TAMP1IE_Msk = 0x10000
	// Bit TAMP1IE.
	RTC_TAMPCR_TAMP1IE = 0x10000
	// Position of TAMP1NOERASE field.
	RTC_TAMPCR_TAMP1NOERASE_Pos = 0x11
	// Bit mask of TAMP1NOERASE field.
	RTC_TAMPCR_TAMP1NOERASE_Msk = 0x20000
	// Bit TAMP1NOERASE.
	RTC_TAMPCR_TAMP1NOERASE = 0x20000
	// Position of TAMP1MF field.
	RTC_TAMPCR_TAMP1MF_Pos = 0x12
	// Bit mask of TAMP1MF field.
	RTC_TAMPCR_TAMP1MF_Msk = 0x40000
	// Bit TAMP1MF.
	RTC_TAMPCR_TAMP1MF = 0x40000
	// Position of TAMP2IE field.
	RTC_TAMPCR_TAMP2IE_Pos = 0x13
	// Bit mask of TAMP2IE field.
	RTC_TAMPCR_TAMP2IE_Msk = 0x80000
	// Bit TAMP2IE.
	RTC_TAMPCR_TAMP2IE = 0x80000
	// Position of TAMP2NOERASE field.
	RTC_TAMPCR_TAMP2NOERASE_Pos = 0x14
	// Bit mask of TAMP2NOERASE field.
	RTC_TAMPCR_TAMP2NOERASE_Msk = 0x100000
	// Bit TAMP2NOERASE.
	RTC_TAMPCR_TAMP2NOERASE = 0x100000
	// Position of TAMP2MF field.
	RTC_TAMPCR_TAMP2MF_Pos = 0x15
	// Bit mask of TAMP2MF field.
	RTC_TAMPCR_TAMP2MF_Msk = 0x200000
	// Bit TAMP2MF.
	RTC_TAMPCR_TAMP2MF = 0x200000
	// Position of TAMP3IE field.
	RTC_TAMPCR_TAMP3IE_Pos = 0x16
	// Bit mask of TAMP3IE field.
	RTC_TAMPCR_TAMP3IE_Msk = 0x400000
	// Bit TAMP3IE.
	RTC_TAMPCR_TAMP3IE = 0x400000
	// Position of TAMP3NOERASE field.
	RTC_TAMPCR_TAMP3NOERASE_Pos = 0x17
	// Bit mask of TAMP3NOERASE field.
	RTC_TAMPCR_TAMP3NOERASE_Msk = 0x800000
	// Bit TAMP3NOERASE.
	RTC_TAMPCR_TAMP3NOERASE = 0x800000
	// Position of TAMP3MF field.
	RTC_TAMPCR_TAMP3MF_Pos = 0x18
	// Bit mask of TAMP3MF field.
	RTC_TAMPCR_TAMP3MF_Msk = 0x1000000
	// Bit TAMP3MF.
	RTC_TAMPCR_TAMP3MF = 0x1000000

	// ALRMASSR: This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9
	// Position of SS field.
	RTC_ALRMASSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_ALRMASSR_SS_Msk = 0x7fff
	// Position of MASKSS field.
	RTC_ALRMASSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_ALRMASSR_MASKSS_Msk = 0xf000000

	// ALRMBSSR: This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection.
	// Position of SS field.
	RTC_ALRMBSSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_ALRMBSSR_SS_Msk = 0x7fff
	// Position of MASKSS field.
	RTC_ALRMBSSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_ALRMBSSR_MASKSS_Msk = 0xf000000

	// OR: RTC option register
	// Position of RTC_ALARM_TYPE field.
	RTC_OR_RTC_ALARM_TYPE_Pos = 0x0
	// Bit mask of RTC_ALARM_TYPE field.
	RTC_OR_RTC_ALARM_TYPE_Msk = 0x1
	// Bit RTC_ALARM_TYPE.
	RTC_OR_RTC_ALARM_TYPE = 0x1
	// Position of RTC_OUT_RMP field.
	RTC_OR_RTC_OUT_RMP_Pos = 0x1
	// Bit mask of RTC_OUT_RMP field.
	RTC_OR_RTC_OUT_RMP_Msk = 0x2
	// Bit RTC_OUT_RMP.
	RTC_OR_RTC_OUT_RMP = 0x2

	// BKP0R: RTC backup registers
	// Position of BKP field.
	RTC_BKPR_BKP_Pos = 0x0
	// Bit mask of BKP field.
	RTC_BKPR_BKP_Msk = 0xffffffff
)

// Bitfields for SAI4: SAI
const (
	// GCR: Global configuration register
	// Position of SYNCOUT field.
	SAI_GCR_SYNCOUT_Pos = 0x4
	// Bit mask of SYNCOUT field.
	SAI_GCR_SYNCOUT_Msk = 0x30
	// Position of SYNCIN field.
	SAI_GCR_SYNCIN_Pos = 0x0
	// Bit mask of SYNCIN field.
	SAI_GCR_SYNCIN_Msk = 0x3

	// CH.CR1: Configuration register 1
	// Position of MODE field.
	SAI_CH_CR1_MODE_Pos = 0x0
	// Bit mask of MODE field.
	SAI_CH_CR1_MODE_Msk = 0x3
	// Master transmitter
	SAI_CH_CR1_MODE_MasterTx = 0x0
	// Master receiver
	SAI_CH_CR1_MODE_MasterRx = 0x1
	// Slave transmitter
	SAI_CH_CR1_MODE_SlaveTx = 0x2
	// Slave receiver
	SAI_CH_CR1_MODE_SlaveRx = 0x3
	// Position of PRTCFG field.
	SAI_CH_CR1_PRTCFG_Pos = 0x2
	// Bit mask of PRTCFG field.
	SAI_CH_CR1_PRTCFG_Msk = 0xc
	// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
	SAI_CH_CR1_PRTCFG_Free = 0x0
	// SPDIF protocol
	SAI_CH_CR1_PRTCFG_Spdif = 0x1
	// AC’97 protocol
	SAI_CH_CR1_PRTCFG_Ac97 = 0x2
	// Position of DS field.
	SAI_CH_CR1_DS_Pos = 0x5
	// Bit mask of DS field.
	SAI_CH_CR1_DS_Msk = 0xe0
	// 8 bits
	SAI_CH_CR1_DS_Bit8 = 0x2
	// 10 bits
	SAI_CH_CR1_DS_Bit10 = 0x3
	// 16 bits
	SAI_CH_CR1_DS_Bit16 = 0x4
	// 20 bits
	SAI_CH_CR1_DS_Bit20 = 0x5
	// 24 bits
	SAI_CH_CR1_DS_Bit24 = 0x6
	// 32 bits
	SAI_CH_CR1_DS_Bit32 = 0x7
	// Position of LSBFIRST field.
	SAI_CH_CR1_LSBFIRST_Pos = 0x8
	// Bit mask of LSBFIRST field.
	SAI_CH_CR1_LSBFIRST_Msk = 0x100
	// Bit LSBFIRST.
	SAI_CH_CR1_LSBFIRST = 0x100
	// Data are transferred with MSB first
	SAI_CH_CR1_LSBFIRST_MsbFirst = 0x0
	// Data are transferred with LSB first
	SAI_CH_CR1_LSBFIRST_LsbFirst = 0x1
	// Position of CKSTR field.
	SAI_CH_CR1_CKSTR_Pos = 0x9
	// Bit mask of CKSTR field.
	SAI_CH_CR1_CKSTR_Msk = 0x200
	// Bit CKSTR.
	SAI_CH_CR1_CKSTR = 0x200
	// Data strobing edge is falling edge of SCK
	SAI_CH_CR1_CKSTR_FallingEdge = 0x0
	// Data strobing edge is rising edge of SCK
	SAI_CH_CR1_CKSTR_RisingEdge = 0x1
	// Position of SYNCEN field.
	SAI_CH_CR1_SYNCEN_Pos = 0xa
	// Bit mask of SYNCEN field.
	SAI_CH_CR1_SYNCEN_Msk = 0xc00
	// audio sub-block in asynchronous mode
	SAI_CH_CR1_SYNCEN_Asynchronous = 0x0
	// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
	SAI_CH_CR1_SYNCEN_Internal = 0x1
	// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
	SAI_CH_CR1_SYNCEN_External = 0x2
	// Position of MONO field.
	SAI_CH_CR1_MONO_Pos = 0xc
	// Bit mask of MONO field.
	SAI_CH_CR1_MONO_Msk = 0x1000
	// Bit MONO.
	SAI_CH_CR1_MONO = 0x1000
	// Stereo mode
	SAI_CH_CR1_MONO_Stereo = 0x0
	// Mono mode
	SAI_CH_CR1_MONO_Mono = 0x1
	// Position of OUTDRIV field.
	SAI_CH_CR1_OUTDRIV_Pos = 0xd
	// Bit mask of OUTDRIV field.
	SAI_CH_CR1_OUTDRIV_Msk = 0x2000
	// Bit OUTDRIV.
	SAI_CH_CR1_OUTDRIV = 0x2000
	// Audio block output driven when SAIEN is set
	SAI_CH_CR1_OUTDRIV_OnStart = 0x0
	// Audio block output driven immediately after the setting of this bit
	SAI_CH_CR1_OUTDRIV_Immediately = 0x1
	// Position of SAIEN field.
	SAI_CH_CR1_SAIEN_Pos = 0x10
	// Bit mask of SAIEN field.
	SAI_CH_CR1_SAIEN_Msk = 0x10000
	// Bit SAIEN.
	SAI_CH_CR1_SAIEN = 0x10000
	// SAI audio block disabled
	SAI_CH_CR1_SAIEN_Disabled = 0x0
	// SAI audio block enabled
	SAI_CH_CR1_SAIEN_Enabled = 0x1
	// Position of DMAEN field.
	SAI_CH_CR1_DMAEN_Pos = 0x11
	// Bit mask of DMAEN field.
	SAI_CH_CR1_DMAEN_Msk = 0x20000
	// Bit DMAEN.
	SAI_CH_CR1_DMAEN = 0x20000
	// DMA disabled
	SAI_CH_CR1_DMAEN_Disabled = 0x0
	// DMA enabled
	SAI_CH_CR1_DMAEN_Enabled = 0x1
	// Position of NODIV field.
	SAI_CH_CR1_NODIV_Pos = 0x13
	// Bit mask of NODIV field.
	SAI_CH_CR1_NODIV_Msk = 0x80000
	// Bit NODIV.
	SAI_CH_CR1_NODIV = 0x80000
	// Master clock generator is enabled
	SAI_CH_CR1_NODIV_MasterClock = 0x0
	// No divider used in the clock generator (in this case Master Clock Divider bit has no effect)
	SAI_CH_CR1_NODIV_NoDiv = 0x1
	// Position of MCKDIV field.
	SAI_CH_CR1_MCKDIV_Pos = 0x14
	// Bit mask of MCKDIV field.
	SAI_CH_CR1_MCKDIV_Msk = 0x3f00000
	// Position of OSR field.
	SAI_CH_CR1_OSR_Pos = 0x1a
	// Bit mask of OSR field.
	SAI_CH_CR1_OSR_Msk = 0x4000000
	// Bit OSR.
	SAI_CH_CR1_OSR = 0x4000000
	// Position of MCKEN field.
	SAI_CH_CR1_MCKEN_Pos = 0x1b
	// Bit mask of MCKEN field.
	SAI_CH_CR1_MCKEN_Msk = 0x8000000
	// Bit MCKEN.
	SAI_CH_CR1_MCKEN = 0x8000000

	// CH.CR2: Configuration register 2
	// Position of FTH field.
	SAI_CH_CR2_FTH_Pos = 0x0
	// Bit mask of FTH field.
	SAI_CH_CR2_FTH_Msk = 0x7
	// FIFO empty
	SAI_CH_CR2_FTH_Empty = 0x0
	// 1⁄4 FIFO
	SAI_CH_CR2_FTH_Quarter1 = 0x1
	// 1⁄2 FIFO
	SAI_CH_CR2_FTH_Quarter2 = 0x2
	// 3⁄4 FIFO
	SAI_CH_CR2_FTH_Quarter3 = 0x3
	// FIFO full
	SAI_CH_CR2_FTH_Full = 0x4
	// Position of FFLUSH field.
	SAI_CH_CR2_FFLUSH_Pos = 0x3
	// Bit mask of FFLUSH field.
	SAI_CH_CR2_FFLUSH_Msk = 0x8
	// Bit FFLUSH.
	SAI_CH_CR2_FFLUSH = 0x8
	// No FIFO flush
	SAI_CH_CR2_FFLUSH_NoFlush = 0x0
	// FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
	SAI_CH_CR2_FFLUSH_Flush = 0x1
	// Position of TRIS field.
	SAI_CH_CR2_TRIS_Pos = 0x4
	// Bit mask of TRIS field.
	SAI_CH_CR2_TRIS_Msk = 0x10
	// Bit TRIS.
	SAI_CH_CR2_TRIS = 0x10
	// Position of MUTE field.
	SAI_CH_CR2_MUTE_Pos = 0x5
	// Bit mask of MUTE field.
	SAI_CH_CR2_MUTE_Msk = 0x20
	// Bit MUTE.
	SAI_CH_CR2_MUTE = 0x20
	// No mute mode
	SAI_CH_CR2_MUTE_Disabled = 0x0
	// Mute mode enabled
	SAI_CH_CR2_MUTE_Enabled = 0x1
	// Position of MUTEVAL field.
	SAI_CH_CR2_MUTEVAL_Pos = 0x6
	// Bit mask of MUTEVAL field.
	SAI_CH_CR2_MUTEVAL_Msk = 0x40
	// Bit MUTEVAL.
	SAI_CH_CR2_MUTEVAL = 0x40
	// Bit value 0 is sent during the mute mode
	SAI_CH_CR2_MUTEVAL_SendZero = 0x0
	// Last values are sent during the mute mode
	SAI_CH_CR2_MUTEVAL_SendLast = 0x1
	// Position of MUTECNT field.
	SAI_CH_CR2_MUTECNT_Pos = 0x7
	// Bit mask of MUTECNT field.
	SAI_CH_CR2_MUTECNT_Msk = 0x1f80
	// Position of CPL field.
	SAI_CH_CR2_CPL_Pos = 0xd
	// Bit mask of CPL field.
	SAI_CH_CR2_CPL_Msk = 0x2000
	// Bit CPL.
	SAI_CH_CR2_CPL = 0x2000
	// 1’s complement representation
	SAI_CH_CR2_CPL_OnesComplement = 0x0
	// 2’s complement representation
	SAI_CH_CR2_CPL_TwosComplement = 0x1
	// Position of COMP field.
	SAI_CH_CR2_COMP_Pos = 0xe
	// Bit mask of COMP field.
	SAI_CH_CR2_COMP_Msk = 0xc000
	// No companding algorithm
	SAI_CH_CR2_COMP_NoCompanding = 0x0
	// μ-Law algorithm
	SAI_CH_CR2_COMP_MuLaw = 0x2
	// A-Law algorithm
	SAI_CH_CR2_COMP_ALaw = 0x3

	// CH.FRCR: This register has no meaning in AC97 and SPDIF audio protocol
	// Position of FRL field.
	SAI_CH_FRCR_FRL_Pos = 0x0
	// Bit mask of FRL field.
	SAI_CH_FRCR_FRL_Msk = 0xff
	// Position of FSALL field.
	SAI_CH_FRCR_FSALL_Pos = 0x8
	// Bit mask of FSALL field.
	SAI_CH_FRCR_FSALL_Msk = 0x7f00
	// Position of FSDEF field.
	SAI_CH_FRCR_FSDEF_Pos = 0x10
	// Bit mask of FSDEF field.
	SAI_CH_FRCR_FSDEF_Msk = 0x10000
	// Bit FSDEF.
	SAI_CH_FRCR_FSDEF = 0x10000
	// Position of FSPOL field.
	SAI_CH_FRCR_FSPOL_Pos = 0x11
	// Bit mask of FSPOL field.
	SAI_CH_FRCR_FSPOL_Msk = 0x20000
	// Bit FSPOL.
	SAI_CH_FRCR_FSPOL = 0x20000
	// FS is active low (falling edge)
	SAI_CH_FRCR_FSPOL_FallingEdge = 0x0
	// FS is active high (rising edge)
	SAI_CH_FRCR_FSPOL_RisingEdge = 0x1
	// Position of FSOFF field.
	SAI_CH_FRCR_FSOFF_Pos = 0x12
	// Bit mask of FSOFF field.
	SAI_CH_FRCR_FSOFF_Msk = 0x40000
	// Bit FSOFF.
	SAI_CH_FRCR_FSOFF = 0x40000
	// FS is asserted on the first bit of the slot 0
	SAI_CH_FRCR_FSOFF_OnFirst = 0x0
	// FS is asserted one bit before the first bit of the slot 0
	SAI_CH_FRCR_FSOFF_BeforeFirst = 0x1

	// CH.SLOTR: This register has no meaning in AC97 and SPDIF audio protocol
	// Position of FBOFF field.
	SAI_CH_SLOTR_FBOFF_Pos = 0x0
	// Bit mask of FBOFF field.
	SAI_CH_SLOTR_FBOFF_Msk = 0x1f
	// Position of SLOTSZ field.
	SAI_CH_SLOTR_SLOTSZ_Pos = 0x6
	// Bit mask of SLOTSZ field.
	SAI_CH_SLOTR_SLOTSZ_Msk = 0xc0
	// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
	SAI_CH_SLOTR_SLOTSZ_DataSize = 0x0
	// 16-bit
	SAI_CH_SLOTR_SLOTSZ_Bit16 = 0x1
	// 32-bit
	SAI_CH_SLOTR_SLOTSZ_Bit32 = 0x2
	// Position of NBSLOT field.
	SAI_CH_SLOTR_NBSLOT_Pos = 0x8
	// Bit mask of NBSLOT field.
	SAI_CH_SLOTR_NBSLOT_Msk = 0xf00
	// Position of SLOTEN field.
	SAI_CH_SLOTR_SLOTEN_Pos = 0x10
	// Bit mask of SLOTEN field.
	SAI_CH_SLOTR_SLOTEN_Msk = 0xffff0000
	// Inactive slot
	SAI_CH_SLOTR_SLOTEN_Inactive = 0x0
	// Active slot
	SAI_CH_SLOTR_SLOTEN_Active = 0x1

	// CH.IM: Interrupt mask register 2
	// Position of OVRUDRIE field.
	SAI_CH_IM_OVRUDRIE_Pos = 0x0
	// Bit mask of OVRUDRIE field.
	SAI_CH_IM_OVRUDRIE_Msk = 0x1
	// Bit OVRUDRIE.
	SAI_CH_IM_OVRUDRIE = 0x1
	// Interrupt is disabled
	SAI_CH_IM_OVRUDRIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_OVRUDRIE_Enabled = 0x1
	// Position of MUTEDETIE field.
	SAI_CH_IM_MUTEDETIE_Pos = 0x1
	// Bit mask of MUTEDETIE field.
	SAI_CH_IM_MUTEDETIE_Msk = 0x2
	// Bit MUTEDETIE.
	SAI_CH_IM_MUTEDETIE = 0x2
	// Interrupt is disabled
	SAI_CH_IM_MUTEDETIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_MUTEDETIE_Enabled = 0x1
	// Position of WCKCFGIE field.
	SAI_CH_IM_WCKCFGIE_Pos = 0x2
	// Bit mask of WCKCFGIE field.
	SAI_CH_IM_WCKCFGIE_Msk = 0x4
	// Bit WCKCFGIE.
	SAI_CH_IM_WCKCFGIE = 0x4
	// Interrupt is disabled
	SAI_CH_IM_WCKCFGIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_WCKCFGIE_Enabled = 0x1
	// Position of FREQIE field.
	SAI_CH_IM_FREQIE_Pos = 0x3
	// Bit mask of FREQIE field.
	SAI_CH_IM_FREQIE_Msk = 0x8
	// Bit FREQIE.
	SAI_CH_IM_FREQIE = 0x8
	// Interrupt is disabled
	SAI_CH_IM_FREQIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_FREQIE_Enabled = 0x1
	// Position of CNRDYIE field.
	SAI_CH_IM_CNRDYIE_Pos = 0x4
	// Bit mask of CNRDYIE field.
	SAI_CH_IM_CNRDYIE_Msk = 0x10
	// Bit CNRDYIE.
	SAI_CH_IM_CNRDYIE = 0x10
	// Interrupt is disabled
	SAI_CH_IM_CNRDYIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_CNRDYIE_Enabled = 0x1
	// Position of AFSDETIE field.
	SAI_CH_IM_AFSDETIE_Pos = 0x5
	// Bit mask of AFSDETIE field.
	SAI_CH_IM_AFSDETIE_Msk = 0x20
	// Bit AFSDETIE.
	SAI_CH_IM_AFSDETIE = 0x20
	// Interrupt is disabled
	SAI_CH_IM_AFSDETIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_AFSDETIE_Enabled = 0x1
	// Position of LFSDETIE field.
	SAI_CH_IM_LFSDETIE_Pos = 0x6
	// Bit mask of LFSDETIE field.
	SAI_CH_IM_LFSDETIE_Msk = 0x40
	// Bit LFSDETIE.
	SAI_CH_IM_LFSDETIE = 0x40
	// Interrupt is disabled
	SAI_CH_IM_LFSDETIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_LFSDETIE_Enabled = 0x1

	// CH.SR: Status register
	// Position of OVRUDR field.
	SAI_CH_SR_OVRUDR_Pos = 0x0
	// Bit mask of OVRUDR field.
	SAI_CH_SR_OVRUDR_Msk = 0x1
	// Bit OVRUDR.
	SAI_CH_SR_OVRUDR = 0x1
	// No overrun/underrun error
	SAI_CH_SR_OVRUDR_NoError = 0x0
	// Overrun/underrun error detection
	SAI_CH_SR_OVRUDR_Overrun = 0x1
	// Position of MUTEDET field.
	SAI_CH_SR_MUTEDET_Pos = 0x1
	// Bit mask of MUTEDET field.
	SAI_CH_SR_MUTEDET_Msk = 0x2
	// Bit MUTEDET.
	SAI_CH_SR_MUTEDET = 0x2
	// No MUTE detection on the SD input line
	SAI_CH_SR_MUTEDET_NoMute = 0x0
	// MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
	SAI_CH_SR_MUTEDET_Mute = 0x1
	// Position of WCKCFG field.
	SAI_CH_SR_WCKCFG_Pos = 0x2
	// Bit mask of WCKCFG field.
	SAI_CH_SR_WCKCFG_Msk = 0x4
	// Bit WCKCFG.
	SAI_CH_SR_WCKCFG = 0x4
	// Clock configuration is correct
	SAI_CH_SR_WCKCFG_Correct = 0x0
	// Clock configuration does not respect the rule concerning the frame length specification
	SAI_CH_SR_WCKCFG_Wrong = 0x1
	// Position of FREQ field.
	SAI_CH_SR_FREQ_Pos = 0x3
	// Bit mask of FREQ field.
	SAI_CH_SR_FREQ_Msk = 0x8
	// Bit FREQ.
	SAI_CH_SR_FREQ = 0x8
	// No FIFO request
	SAI_CH_SR_FREQ_NoRequest = 0x0
	// FIFO request to read or to write the SAI_xDR
	SAI_CH_SR_FREQ_Request = 0x1
	// Position of CNRDY field.
	SAI_CH_SR_CNRDY_Pos = 0x4
	// Bit mask of CNRDY field.
	SAI_CH_SR_CNRDY_Msk = 0x10
	// Bit CNRDY.
	SAI_CH_SR_CNRDY = 0x10
	// External AC’97 Codec is ready
	SAI_CH_SR_CNRDY_Ready = 0x0
	// External AC’97 Codec is not ready
	SAI_CH_SR_CNRDY_NotReady = 0x1
	// Position of AFSDET field.
	SAI_CH_SR_AFSDET_Pos = 0x5
	// Bit mask of AFSDET field.
	SAI_CH_SR_AFSDET_Msk = 0x20
	// Bit AFSDET.
	SAI_CH_SR_AFSDET = 0x20
	// No error
	SAI_CH_SR_AFSDET_NoError = 0x0
	// Frame synchronization signal is detected earlier than expected
	SAI_CH_SR_AFSDET_EarlySync = 0x1
	// Position of LFSDET field.
	SAI_CH_SR_LFSDET_Pos = 0x6
	// Bit mask of LFSDET field.
	SAI_CH_SR_LFSDET_Msk = 0x40
	// Bit LFSDET.
	SAI_CH_SR_LFSDET = 0x40
	// No error
	SAI_CH_SR_LFSDET_NoError = 0x0
	// Frame synchronization signal is not present at the right time
	SAI_CH_SR_LFSDET_NoSync = 0x1
	// Position of FLVL field.
	SAI_CH_SR_FLVL_Pos = 0x10
	// Bit mask of FLVL field.
	SAI_CH_SR_FLVL_Msk = 0x70000
	// FIFO empty
	SAI_CH_SR_FLVL_Empty = 0x0
	// FIFO <= 1⁄4 but not empty
	SAI_CH_SR_FLVL_Quarter1 = 0x1
	// 1⁄4 < FIFO <= 1⁄2
	SAI_CH_SR_FLVL_Quarter2 = 0x2
	// 1⁄2 < FIFO <= 3⁄4
	SAI_CH_SR_FLVL_Quarter3 = 0x3
	// 3⁄4 < FIFO but not full
	SAI_CH_SR_FLVL_Quarter4 = 0x4
	// FIFO full
	SAI_CH_SR_FLVL_Full = 0x5

	// CH.CLRFR: Clear flag register
	// Position of COVRUDR field.
	SAI_CH_CLRFR_COVRUDR_Pos = 0x0
	// Bit mask of COVRUDR field.
	SAI_CH_CLRFR_COVRUDR_Msk = 0x1
	// Bit COVRUDR.
	SAI_CH_CLRFR_COVRUDR = 0x1
	// Clears the OVRUDR flag
	SAI_CH_CLRFR_COVRUDR_Clear = 0x1
	// Position of CMUTEDET field.
	SAI_CH_CLRFR_CMUTEDET_Pos = 0x1
	// Bit mask of CMUTEDET field.
	SAI_CH_CLRFR_CMUTEDET_Msk = 0x2
	// Bit CMUTEDET.
	SAI_CH_CLRFR_CMUTEDET = 0x2
	// Clears the MUTEDET flag
	SAI_CH_CLRFR_CMUTEDET_Clear = 0x1
	// Position of CWCKCFG field.
	SAI_CH_CLRFR_CWCKCFG_Pos = 0x2
	// Bit mask of CWCKCFG field.
	SAI_CH_CLRFR_CWCKCFG_Msk = 0x4
	// Bit CWCKCFG.
	SAI_CH_CLRFR_CWCKCFG = 0x4
	// Clears the WCKCFG flag
	SAI_CH_CLRFR_CWCKCFG_Clear = 0x1
	// Position of CCNRDY field.
	SAI_CH_CLRFR_CCNRDY_Pos = 0x4
	// Bit mask of CCNRDY field.
	SAI_CH_CLRFR_CCNRDY_Msk = 0x10
	// Bit CCNRDY.
	SAI_CH_CLRFR_CCNRDY = 0x10
	// Clears the CNRDY flag
	SAI_CH_CLRFR_CCNRDY_Clear = 0x1
	// Position of CAFSDET field.
	SAI_CH_CLRFR_CAFSDET_Pos = 0x5
	// Bit mask of CAFSDET field.
	SAI_CH_CLRFR_CAFSDET_Msk = 0x20
	// Bit CAFSDET.
	SAI_CH_CLRFR_CAFSDET = 0x20
	// Clears the AFSDET flag
	SAI_CH_CLRFR_CAFSDET_Clear = 0x1
	// Position of CLFSDET field.
	SAI_CH_CLRFR_CLFSDET_Pos = 0x6
	// Bit mask of CLFSDET field.
	SAI_CH_CLRFR_CLFSDET_Msk = 0x40
	// Bit CLFSDET.
	SAI_CH_CLRFR_CLFSDET = 0x40
	// Clears the LFSDET flag
	SAI_CH_CLRFR_CLFSDET_Clear = 0x1

	// CH.DR: Data register
	// Position of DATA field.
	SAI_CH_DR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SAI_CH_DR_DATA_Msk = 0xffffffff

	// PDMCR: PDM control register
	// Position of PDMEN field.
	SAI_PDMCR_PDMEN_Pos = 0x0
	// Bit mask of PDMEN field.
	SAI_PDMCR_PDMEN_Msk = 0x1
	// Bit PDMEN.
	SAI_PDMCR_PDMEN = 0x1
	// Position of MICNBR field.
	SAI_PDMCR_MICNBR_Pos = 0x4
	// Bit mask of MICNBR field.
	SAI_PDMCR_MICNBR_Msk = 0x30
	// Position of CKEN1 field.
	SAI_PDMCR_CKEN1_Pos = 0x8
	// Bit mask of CKEN1 field.
	SAI_PDMCR_CKEN1_Msk = 0x100
	// Bit CKEN1.
	SAI_PDMCR_CKEN1 = 0x100
	// Position of CKEN2 field.
	SAI_PDMCR_CKEN2_Pos = 0x9
	// Bit mask of CKEN2 field.
	SAI_PDMCR_CKEN2_Msk = 0x200
	// Bit CKEN2.
	SAI_PDMCR_CKEN2 = 0x200
	// Position of CKEN3 field.
	SAI_PDMCR_CKEN3_Pos = 0xa
	// Bit mask of CKEN3 field.
	SAI_PDMCR_CKEN3_Msk = 0x400
	// Bit CKEN3.
	SAI_PDMCR_CKEN3 = 0x400
	// Position of CKEN4 field.
	SAI_PDMCR_CKEN4_Pos = 0xb
	// Bit mask of CKEN4 field.
	SAI_PDMCR_CKEN4_Msk = 0x800
	// Bit CKEN4.
	SAI_PDMCR_CKEN4 = 0x800

	// PDMDLY: PDM delay register
	// Position of DLYM1L field.
	SAI_PDMDLY_DLYM1L_Pos = 0x0
	// Bit mask of DLYM1L field.
	SAI_PDMDLY_DLYM1L_Msk = 0x7
	// Position of DLYM1R field.
	SAI_PDMDLY_DLYM1R_Pos = 0x4
	// Bit mask of DLYM1R field.
	SAI_PDMDLY_DLYM1R_Msk = 0x70
	// Position of DLYM2L field.
	SAI_PDMDLY_DLYM2L_Pos = 0x8
	// Bit mask of DLYM2L field.
	SAI_PDMDLY_DLYM2L_Msk = 0x700
	// Position of DLYM2R field.
	SAI_PDMDLY_DLYM2R_Pos = 0xc
	// Bit mask of DLYM2R field.
	SAI_PDMDLY_DLYM2R_Msk = 0x7000
	// Position of DLYM3L field.
	SAI_PDMDLY_DLYM3L_Pos = 0x10
	// Bit mask of DLYM3L field.
	SAI_PDMDLY_DLYM3L_Msk = 0x70000
	// Position of DLYM3R field.
	SAI_PDMDLY_DLYM3R_Pos = 0x14
	// Bit mask of DLYM3R field.
	SAI_PDMDLY_DLYM3R_Msk = 0x700000
	// Position of DLYM4L field.
	SAI_PDMDLY_DLYM4L_Pos = 0x18
	// Bit mask of DLYM4L field.
	SAI_PDMDLY_DLYM4L_Msk = 0x7000000
	// Position of DLYM4R field.
	SAI_PDMDLY_DLYM4R_Pos = 0x1c
	// Bit mask of DLYM4R field.
	SAI_PDMDLY_DLYM4R_Msk = 0x70000000
)

// Bitfields for SDMMC1: SDMMC1
const (
	// POWER: SDMMC power control register
	// Position of PWRCTRL field.
	SDMMC_POWER_PWRCTRL_Pos = 0x0
	// Bit mask of PWRCTRL field.
	SDMMC_POWER_PWRCTRL_Msk = 0x3
	// Position of VSWITCH field.
	SDMMC_POWER_VSWITCH_Pos = 0x2
	// Bit mask of VSWITCH field.
	SDMMC_POWER_VSWITCH_Msk = 0x4
	// Bit VSWITCH.
	SDMMC_POWER_VSWITCH = 0x4
	// Position of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN_Pos = 0x3
	// Bit mask of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN_Msk = 0x8
	// Bit VSWITCHEN.
	SDMMC_POWER_VSWITCHEN = 0x8
	// Position of DIRPOL field.
	SDMMC_POWER_DIRPOL_Pos = 0x4
	// Bit mask of DIRPOL field.
	SDMMC_POWER_DIRPOL_Msk = 0x10
	// Bit DIRPOL.
	SDMMC_POWER_DIRPOL = 0x10

	// CLKCR: The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.
	// Position of CLKDIV field.
	SDMMC_CLKCR_CLKDIV_Pos = 0x0
	// Bit mask of CLKDIV field.
	SDMMC_CLKCR_CLKDIV_Msk = 0x3ff
	// Position of PWRSAV field.
	SDMMC_CLKCR_PWRSAV_Pos = 0xc
	// Bit mask of PWRSAV field.
	SDMMC_CLKCR_PWRSAV_Msk = 0x1000
	// Bit PWRSAV.
	SDMMC_CLKCR_PWRSAV = 0x1000
	// Position of WIDBUS field.
	SDMMC_CLKCR_WIDBUS_Pos = 0xe
	// Bit mask of WIDBUS field.
	SDMMC_CLKCR_WIDBUS_Msk = 0xc000
	// Position of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE_Pos = 0x10
	// Bit mask of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE_Msk = 0x10000
	// Bit NEGEDGE.
	SDMMC_CLKCR_NEGEDGE = 0x10000
	// Position of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN_Pos = 0x11
	// Bit mask of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN_Msk = 0x20000
	// Bit HWFC_EN.
	SDMMC_CLKCR_HWFC_EN = 0x20000
	// Position of DDR field.
	SDMMC_CLKCR_DDR_Pos = 0x12
	// Bit mask of DDR field.
	SDMMC_CLKCR_DDR_Msk = 0x40000
	// Bit DDR.
	SDMMC_CLKCR_DDR = 0x40000
	// Position of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED_Pos = 0x13
	// Bit mask of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED_Msk = 0x80000
	// Bit BUSSPEED.
	SDMMC_CLKCR_BUSSPEED = 0x80000
	// Position of SELCLKRX field.
	SDMMC_CLKCR_SELCLKRX_Pos = 0x14
	// Bit mask of SELCLKRX field.
	SDMMC_CLKCR_SELCLKRX_Msk = 0x300000

	// ARGR: The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.
	// Position of CMDARG field.
	SDMMC_ARGR_CMDARG_Pos = 0x0
	// Bit mask of CMDARG field.
	SDMMC_ARGR_CMDARG_Msk = 0xffffffff

	// CMDR: The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
	// Position of CMDINDEX field.
	SDMMC_CMDR_CMDINDEX_Pos = 0x0
	// Bit mask of CMDINDEX field.
	SDMMC_CMDR_CMDINDEX_Msk = 0x3f
	// Position of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS_Pos = 0x6
	// Bit mask of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS_Msk = 0x40
	// Bit CMDTRANS.
	SDMMC_CMDR_CMDTRANS = 0x40
	// Position of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP_Pos = 0x7
	// Bit mask of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP_Msk = 0x80
	// Bit CMDSTOP.
	SDMMC_CMDR_CMDSTOP = 0x80
	// Position of WAITRESP field.
	SDMMC_CMDR_WAITRESP_Pos = 0x8
	// Bit mask of WAITRESP field.
	SDMMC_CMDR_WAITRESP_Msk = 0x300
	// Position of WAITINT field.
	SDMMC_CMDR_WAITINT_Pos = 0xa
	// Bit mask of WAITINT field.
	SDMMC_CMDR_WAITINT_Msk = 0x400
	// Bit WAITINT.
	SDMMC_CMDR_WAITINT = 0x400
	// Position of WAITPEND field.
	SDMMC_CMDR_WAITPEND_Pos = 0xb
	// Bit mask of WAITPEND field.
	SDMMC_CMDR_WAITPEND_Msk = 0x800
	// Bit WAITPEND.
	SDMMC_CMDR_WAITPEND = 0x800
	// Position of CPSMEN field.
	SDMMC_CMDR_CPSMEN_Pos = 0xc
	// Bit mask of CPSMEN field.
	SDMMC_CMDR_CPSMEN_Msk = 0x1000
	// Bit CPSMEN.
	SDMMC_CMDR_CPSMEN = 0x1000
	// Position of DTHOLD field.
	SDMMC_CMDR_DTHOLD_Pos = 0xd
	// Bit mask of DTHOLD field.
	SDMMC_CMDR_DTHOLD_Msk = 0x2000
	// Bit DTHOLD.
	SDMMC_CMDR_DTHOLD = 0x2000
	// Position of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE_Pos = 0xe
	// Bit mask of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE_Msk = 0x4000
	// Bit BOOTMODE.
	SDMMC_CMDR_BOOTMODE = 0x4000
	// Position of BOOTEN field.
	SDMMC_CMDR_BOOTEN_Pos = 0xf
	// Bit mask of BOOTEN field.
	SDMMC_CMDR_BOOTEN_Msk = 0x8000
	// Bit BOOTEN.
	SDMMC_CMDR_BOOTEN = 0x8000
	// Position of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND_Pos = 0x10
	// Bit mask of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND_Msk = 0x10000
	// Bit CMDSUSPEND.
	SDMMC_CMDR_CMDSUSPEND = 0x10000

	// RESPCMDR: SDMMC command response register
	// Position of RESPCMD field.
	SDMMC_RESPCMDR_RESPCMD_Pos = 0x0
	// Bit mask of RESPCMD field.
	SDMMC_RESPCMDR_RESPCMD_Msk = 0x3f

	// RESP1R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS1 field.
	SDMMC_RESP1R_CARDSTATUS1_Pos = 0x0
	// Bit mask of CARDSTATUS1 field.
	SDMMC_RESP1R_CARDSTATUS1_Msk = 0xffffffff

	// RESP2R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS2 field.
	SDMMC_RESP2R_CARDSTATUS2_Pos = 0x0
	// Bit mask of CARDSTATUS2 field.
	SDMMC_RESP2R_CARDSTATUS2_Msk = 0xffffffff

	// RESP3R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS3 field.
	SDMMC_RESP3R_CARDSTATUS3_Pos = 0x0
	// Bit mask of CARDSTATUS3 field.
	SDMMC_RESP3R_CARDSTATUS3_Msk = 0xffffffff

	// RESP4R: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
	// Position of CARDSTATUS4 field.
	SDMMC_RESP4R_CARDSTATUS4_Pos = 0x0
	// Bit mask of CARDSTATUS4 field.
	SDMMC_RESP4R_CARDSTATUS4_Msk = 0xffffffff

	// DTIMER: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
	// Position of DATATIME field.
	SDMMC_DTIMER_DATATIME_Pos = 0x0
	// Bit mask of DATATIME field.
	SDMMC_DTIMER_DATATIME_Msk = 0xffffffff

	// DLENR: The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.
	// Position of DATALENGTH field.
	SDMMC_DLENR_DATALENGTH_Pos = 0x0
	// Bit mask of DATALENGTH field.
	SDMMC_DLENR_DATALENGTH_Msk = 0x1ffffff

	// DCTRL: The SDMMC_DCTRL register control the data path state machine (DPSM).
	// Position of DTEN field.
	SDMMC_DCTRL_DTEN_Pos = 0x0
	// Bit mask of DTEN field.
	SDMMC_DCTRL_DTEN_Msk = 0x1
	// Bit DTEN.
	SDMMC_DCTRL_DTEN = 0x1
	// Position of DTDIR field.
	SDMMC_DCTRL_DTDIR_Pos = 0x1
	// Bit mask of DTDIR field.
	SDMMC_DCTRL_DTDIR_Msk = 0x2
	// Bit DTDIR.
	SDMMC_DCTRL_DTDIR = 0x2
	// Position of DTMODE field.
	SDMMC_DCTRL_DTMODE_Pos = 0x2
	// Bit mask of DTMODE field.
	SDMMC_DCTRL_DTMODE_Msk = 0xc
	// Position of DBLOCKSIZE field.
	SDMMC_DCTRL_DBLOCKSIZE_Pos = 0x4
	// Bit mask of DBLOCKSIZE field.
	SDMMC_DCTRL_DBLOCKSIZE_Msk = 0xf0
	// Position of RWSTART field.
	SDMMC_DCTRL_RWSTART_Pos = 0x8
	// Bit mask of RWSTART field.
	SDMMC_DCTRL_RWSTART_Msk = 0x100
	// Bit RWSTART.
	SDMMC_DCTRL_RWSTART = 0x100
	// Position of RWSTOP field.
	SDMMC_DCTRL_RWSTOP_Pos = 0x9
	// Bit mask of RWSTOP field.
	SDMMC_DCTRL_RWSTOP_Msk = 0x200
	// Bit RWSTOP.
	SDMMC_DCTRL_RWSTOP = 0x200
	// Position of RWMOD field.
	SDMMC_DCTRL_RWMOD_Pos = 0xa
	// Bit mask of RWMOD field.
	SDMMC_DCTRL_RWMOD_Msk = 0x400
	// Bit RWMOD.
	SDMMC_DCTRL_RWMOD = 0x400
	// Position of SDIOEN field.
	SDMMC_DCTRL_SDIOEN_Pos = 0xb
	// Bit mask of SDIOEN field.
	SDMMC_DCTRL_SDIOEN_Msk = 0x800
	// Bit SDIOEN.
	SDMMC_DCTRL_SDIOEN = 0x800
	// Position of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN_Pos = 0xc
	// Bit mask of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN_Msk = 0x1000
	// Bit BOOTACKEN.
	SDMMC_DCTRL_BOOTACKEN = 0x1000
	// Position of FIFORST field.
	SDMMC_DCTRL_FIFORST_Pos = 0xd
	// Bit mask of FIFORST field.
	SDMMC_DCTRL_FIFORST_Msk = 0x2000
	// Bit FIFORST.
	SDMMC_DCTRL_FIFORST = 0x2000

	// DCNTR: The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.
	// Position of DATACOUNT field.
	SDMMC_DCNTR_DATACOUNT_Pos = 0x0
	// Bit mask of DATACOUNT field.
	SDMMC_DCNTR_DATACOUNT_Msk = 0x1ffffff

	// STAR: The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)
	// Position of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL_Pos = 0x0
	// Bit mask of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL_Msk = 0x1
	// Bit CCRCFAIL.
	SDMMC_STAR_CCRCFAIL = 0x1
	// Position of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL_Pos = 0x1
	// Bit mask of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL_Msk = 0x2
	// Bit DCRCFAIL.
	SDMMC_STAR_DCRCFAIL = 0x2
	// Position of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT_Pos = 0x2
	// Bit mask of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT_Msk = 0x4
	// Bit CTIMEOUT.
	SDMMC_STAR_CTIMEOUT = 0x4
	// Position of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT_Pos = 0x3
	// Bit mask of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT_Msk = 0x8
	// Bit DTIMEOUT.
	SDMMC_STAR_DTIMEOUT = 0x8
	// Position of TXUNDERR field.
	SDMMC_STAR_TXUNDERR_Pos = 0x4
	// Bit mask of TXUNDERR field.
	SDMMC_STAR_TXUNDERR_Msk = 0x10
	// Bit TXUNDERR.
	SDMMC_STAR_TXUNDERR = 0x10
	// Position of RXOVERR field.
	SDMMC_STAR_RXOVERR_Pos = 0x5
	// Bit mask of RXOVERR field.
	SDMMC_STAR_RXOVERR_Msk = 0x20
	// Bit RXOVERR.
	SDMMC_STAR_RXOVERR = 0x20
	// Position of CMDREND field.
	SDMMC_STAR_CMDREND_Pos = 0x6
	// Bit mask of CMDREND field.
	SDMMC_STAR_CMDREND_Msk = 0x40
	// Bit CMDREND.
	SDMMC_STAR_CMDREND = 0x40
	// Position of CMDSENT field.
	SDMMC_STAR_CMDSENT_Pos = 0x7
	// Bit mask of CMDSENT field.
	SDMMC_STAR_CMDSENT_Msk = 0x80
	// Bit CMDSENT.
	SDMMC_STAR_CMDSENT = 0x80
	// Position of DATAEND field.
	SDMMC_STAR_DATAEND_Pos = 0x8
	// Bit mask of DATAEND field.
	SDMMC_STAR_DATAEND_Msk = 0x100
	// Bit DATAEND.
	SDMMC_STAR_DATAEND = 0x100
	// Position of DHOLD field.
	SDMMC_STAR_DHOLD_Pos = 0x9
	// Bit mask of DHOLD field.
	SDMMC_STAR_DHOLD_Msk = 0x200
	// Bit DHOLD.
	SDMMC_STAR_DHOLD = 0x200
	// Position of DBCKEND field.
	SDMMC_STAR_DBCKEND_Pos = 0xa
	// Bit mask of DBCKEND field.
	SDMMC_STAR_DBCKEND_Msk = 0x400
	// Bit DBCKEND.
	SDMMC_STAR_DBCKEND = 0x400
	// Position of DABORT field.
	SDMMC_STAR_DABORT_Pos = 0xb
	// Bit mask of DABORT field.
	SDMMC_STAR_DABORT_Msk = 0x800
	// Bit DABORT.
	SDMMC_STAR_DABORT = 0x800
	// Position of DPSMACT field.
	SDMMC_STAR_DPSMACT_Pos = 0xc
	// Bit mask of DPSMACT field.
	SDMMC_STAR_DPSMACT_Msk = 0x1000
	// Bit DPSMACT.
	SDMMC_STAR_DPSMACT = 0x1000
	// Position of CPSMACT field.
	SDMMC_STAR_CPSMACT_Pos = 0xd
	// Bit mask of CPSMACT field.
	SDMMC_STAR_CPSMACT_Msk = 0x2000
	// Bit CPSMACT.
	SDMMC_STAR_CPSMACT = 0x2000
	// Position of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE_Pos = 0xe
	// Bit mask of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE_Msk = 0x4000
	// Bit TXFIFOHE.
	SDMMC_STAR_TXFIFOHE = 0x4000
	// Position of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF_Pos = 0xf
	// Bit mask of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF_Msk = 0x8000
	// Bit RXFIFOHF.
	SDMMC_STAR_RXFIFOHF = 0x8000
	// Position of TXFIFOF field.
	SDMMC_STAR_TXFIFOF_Pos = 0x10
	// Bit mask of TXFIFOF field.
	SDMMC_STAR_TXFIFOF_Msk = 0x10000
	// Bit TXFIFOF.
	SDMMC_STAR_TXFIFOF = 0x10000
	// Position of RXFIFOF field.
	SDMMC_STAR_RXFIFOF_Pos = 0x11
	// Bit mask of RXFIFOF field.
	SDMMC_STAR_RXFIFOF_Msk = 0x20000
	// Bit RXFIFOF.
	SDMMC_STAR_RXFIFOF = 0x20000
	// Position of TXFIFOE field.
	SDMMC_STAR_TXFIFOE_Pos = 0x12
	// Bit mask of TXFIFOE field.
	SDMMC_STAR_TXFIFOE_Msk = 0x40000
	// Bit TXFIFOE.
	SDMMC_STAR_TXFIFOE = 0x40000
	// Position of RXFIFOE field.
	SDMMC_STAR_RXFIFOE_Pos = 0x13
	// Bit mask of RXFIFOE field.
	SDMMC_STAR_RXFIFOE_Msk = 0x80000
	// Bit RXFIFOE.
	SDMMC_STAR_RXFIFOE = 0x80000
	// Position of BUSYD0 field.
	SDMMC_STAR_BUSYD0_Pos = 0x14
	// Bit mask of BUSYD0 field.
	SDMMC_STAR_BUSYD0_Msk = 0x100000
	// Bit BUSYD0.
	SDMMC_STAR_BUSYD0 = 0x100000
	// Position of BUSYD0END field.
	SDMMC_STAR_BUSYD0END_Pos = 0x15
	// Bit mask of BUSYD0END field.
	SDMMC_STAR_BUSYD0END_Msk = 0x200000
	// Bit BUSYD0END.
	SDMMC_STAR_BUSYD0END = 0x200000
	// Position of SDIOIT field.
	SDMMC_STAR_SDIOIT_Pos = 0x16
	// Bit mask of SDIOIT field.
	SDMMC_STAR_SDIOIT_Msk = 0x400000
	// Bit SDIOIT.
	SDMMC_STAR_SDIOIT = 0x400000
	// Position of ACKFAIL field.
	SDMMC_STAR_ACKFAIL_Pos = 0x17
	// Bit mask of ACKFAIL field.
	SDMMC_STAR_ACKFAIL_Msk = 0x800000
	// Bit ACKFAIL.
	SDMMC_STAR_ACKFAIL = 0x800000
	// Position of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT_Pos = 0x18
	// Bit mask of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT_Msk = 0x1000000
	// Bit ACKTIMEOUT.
	SDMMC_STAR_ACKTIMEOUT = 0x1000000
	// Position of VSWEND field.
	SDMMC_STAR_VSWEND_Pos = 0x19
	// Bit mask of VSWEND field.
	SDMMC_STAR_VSWEND_Msk = 0x2000000
	// Bit VSWEND.
	SDMMC_STAR_VSWEND = 0x2000000
	// Position of CKSTOP field.
	SDMMC_STAR_CKSTOP_Pos = 0x1a
	// Bit mask of CKSTOP field.
	SDMMC_STAR_CKSTOP_Msk = 0x4000000
	// Bit CKSTOP.
	SDMMC_STAR_CKSTOP = 0x4000000
	// Position of IDMATE field.
	SDMMC_STAR_IDMATE_Pos = 0x1b
	// Bit mask of IDMATE field.
	SDMMC_STAR_IDMATE_Msk = 0x8000000
	// Bit IDMATE.
	SDMMC_STAR_IDMATE = 0x8000000
	// Position of IDMABTC field.
	SDMMC_STAR_IDMABTC_Pos = 0x1c
	// Bit mask of IDMABTC field.
	SDMMC_STAR_IDMABTC_Msk = 0x10000000
	// Bit IDMABTC.
	SDMMC_STAR_IDMABTC = 0x10000000

	// ICR: The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.
	// Position of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC_Pos = 0x0
	// Bit mask of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC_Msk = 0x1
	// Bit CCRCFAILC.
	SDMMC_ICR_CCRCFAILC = 0x1
	// Position of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC_Pos = 0x1
	// Bit mask of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC_Msk = 0x2
	// Bit DCRCFAILC.
	SDMMC_ICR_DCRCFAILC = 0x2
	// Position of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC_Pos = 0x2
	// Bit mask of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC_Msk = 0x4
	// Bit CTIMEOUTC.
	SDMMC_ICR_CTIMEOUTC = 0x4
	// Position of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC_Pos = 0x3
	// Bit mask of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC_Msk = 0x8
	// Bit DTIMEOUTC.
	SDMMC_ICR_DTIMEOUTC = 0x8
	// Position of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC_Pos = 0x4
	// Bit mask of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC_Msk = 0x10
	// Bit TXUNDERRC.
	SDMMC_ICR_TXUNDERRC = 0x10
	// Position of RXOVERRC field.
	SDMMC_ICR_RXOVERRC_Pos = 0x5
	// Bit mask of RXOVERRC field.
	SDMMC_ICR_RXOVERRC_Msk = 0x20
	// Bit RXOVERRC.
	SDMMC_ICR_RXOVERRC = 0x20
	// Position of CMDRENDC field.
	SDMMC_ICR_CMDRENDC_Pos = 0x6
	// Bit mask of CMDRENDC field.
	SDMMC_ICR_CMDRENDC_Msk = 0x40
	// Bit CMDRENDC.
	SDMMC_ICR_CMDRENDC = 0x40
	// Position of CMDSENTC field.
	SDMMC_ICR_CMDSENTC_Pos = 0x7
	// Bit mask of CMDSENTC field.
	SDMMC_ICR_CMDSENTC_Msk = 0x80
	// Bit CMDSENTC.
	SDMMC_ICR_CMDSENTC = 0x80
	// Position of DATAENDC field.
	SDMMC_ICR_DATAENDC_Pos = 0x8
	// Bit mask of DATAENDC field.
	SDMMC_ICR_DATAENDC_Msk = 0x100
	// Bit DATAENDC.
	SDMMC_ICR_DATAENDC = 0x100
	// Position of DHOLDC field.
	SDMMC_ICR_DHOLDC_Pos = 0x9
	// Bit mask of DHOLDC field.
	SDMMC_ICR_DHOLDC_Msk = 0x200
	// Bit DHOLDC.
	SDMMC_ICR_DHOLDC = 0x200
	// Position of DBCKENDC field.
	SDMMC_ICR_DBCKENDC_Pos = 0xa
	// Bit mask of DBCKENDC field.
	SDMMC_ICR_DBCKENDC_Msk = 0x400
	// Bit DBCKENDC.
	SDMMC_ICR_DBCKENDC = 0x400
	// Position of DABORTC field.
	SDMMC_ICR_DABORTC_Pos = 0xb
	// Bit mask of DABORTC field.
	SDMMC_ICR_DABORTC_Msk = 0x800
	// Bit DABORTC.
	SDMMC_ICR_DABORTC = 0x800
	// Position of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC_Pos = 0x15
	// Bit mask of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC_Msk = 0x200000
	// Bit BUSYD0ENDC.
	SDMMC_ICR_BUSYD0ENDC = 0x200000
	// Position of SDIOITC field.
	SDMMC_ICR_SDIOITC_Pos = 0x16
	// Bit mask of SDIOITC field.
	SDMMC_ICR_SDIOITC_Msk = 0x400000
	// Bit SDIOITC.
	SDMMC_ICR_SDIOITC = 0x400000
	// Position of ACKFAILC field.
	SDMMC_ICR_ACKFAILC_Pos = 0x17
	// Bit mask of ACKFAILC field.
	SDMMC_ICR_ACKFAILC_Msk = 0x800000
	// Bit ACKFAILC.
	SDMMC_ICR_ACKFAILC = 0x800000
	// Position of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC_Pos = 0x18
	// Bit mask of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC_Msk = 0x1000000
	// Bit ACKTIMEOUTC.
	SDMMC_ICR_ACKTIMEOUTC = 0x1000000
	// Position of VSWENDC field.
	SDMMC_ICR_VSWENDC_Pos = 0x19
	// Bit mask of VSWENDC field.
	SDMMC_ICR_VSWENDC_Msk = 0x2000000
	// Bit VSWENDC.
	SDMMC_ICR_VSWENDC = 0x2000000
	// Position of CKSTOPC field.
	SDMMC_ICR_CKSTOPC_Pos = 0x1a
	// Bit mask of CKSTOPC field.
	SDMMC_ICR_CKSTOPC_Msk = 0x4000000
	// Bit CKSTOPC.
	SDMMC_ICR_CKSTOPC = 0x4000000
	// Position of IDMATEC field.
	SDMMC_ICR_IDMATEC_Pos = 0x1b
	// Bit mask of IDMATEC field.
	SDMMC_ICR_IDMATEC_Msk = 0x8000000
	// Bit IDMATEC.
	SDMMC_ICR_IDMATEC = 0x8000000
	// Position of IDMABTCC field.
	SDMMC_ICR_IDMABTCC_Pos = 0x1c
	// Bit mask of IDMABTCC field.
	SDMMC_ICR_IDMABTCC_Msk = 0x10000000
	// Bit IDMABTCC.
	SDMMC_ICR_IDMABTCC = 0x10000000

	// MASKR: The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
	// Position of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE_Pos = 0x0
	// Bit mask of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE_Msk = 0x1
	// Bit CCRCFAILIE.
	SDMMC_MASKR_CCRCFAILIE = 0x1
	// Position of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE_Pos = 0x1
	// Bit mask of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE_Msk = 0x2
	// Bit DCRCFAILIE.
	SDMMC_MASKR_DCRCFAILIE = 0x2
	// Position of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE_Pos = 0x2
	// Bit mask of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE_Msk = 0x4
	// Bit CTIMEOUTIE.
	SDMMC_MASKR_CTIMEOUTIE = 0x4
	// Position of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE_Pos = 0x3
	// Bit mask of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE_Msk = 0x8
	// Bit DTIMEOUTIE.
	SDMMC_MASKR_DTIMEOUTIE = 0x8
	// Position of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE_Pos = 0x4
	// Bit mask of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE_Msk = 0x10
	// Bit TXUNDERRIE.
	SDMMC_MASKR_TXUNDERRIE = 0x10
	// Position of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE_Pos = 0x5
	// Bit mask of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE_Msk = 0x20
	// Bit RXOVERRIE.
	SDMMC_MASKR_RXOVERRIE = 0x20
	// Position of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE_Pos = 0x6
	// Bit mask of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE_Msk = 0x40
	// Bit CMDRENDIE.
	SDMMC_MASKR_CMDRENDIE = 0x40
	// Position of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE_Pos = 0x7
	// Bit mask of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE_Msk = 0x80
	// Bit CMDSENTIE.
	SDMMC_MASKR_CMDSENTIE = 0x80
	// Position of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE_Pos = 0x8
	// Bit mask of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE_Msk = 0x100
	// Bit DATAENDIE.
	SDMMC_MASKR_DATAENDIE = 0x100
	// Position of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE_Pos = 0x9
	// Bit mask of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE_Msk = 0x200
	// Bit DHOLDIE.
	SDMMC_MASKR_DHOLDIE = 0x200
	// Position of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE_Pos = 0xa
	// Bit mask of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE_Msk = 0x400
	// Bit DBCKENDIE.
	SDMMC_MASKR_DBCKENDIE = 0x400
	// Position of DABORTIE field.
	SDMMC_MASKR_DABORTIE_Pos = 0xb
	// Bit mask of DABORTIE field.
	SDMMC_MASKR_DABORTIE_Msk = 0x800
	// Bit DABORTIE.
	SDMMC_MASKR_DABORTIE = 0x800
	// Position of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE_Pos = 0xe
	// Bit mask of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE_Msk = 0x4000
	// Bit TXFIFOHEIE.
	SDMMC_MASKR_TXFIFOHEIE = 0x4000
	// Position of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE_Pos = 0xf
	// Bit mask of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE_Msk = 0x8000
	// Bit RXFIFOHFIE.
	SDMMC_MASKR_RXFIFOHFIE = 0x8000
	// Position of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE_Pos = 0x11
	// Bit mask of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE_Msk = 0x20000
	// Bit RXFIFOFIE.
	SDMMC_MASKR_RXFIFOFIE = 0x20000
	// Position of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE_Pos = 0x12
	// Bit mask of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE_Msk = 0x40000
	// Bit TXFIFOEIE.
	SDMMC_MASKR_TXFIFOEIE = 0x40000
	// Position of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE_Pos = 0x15
	// Bit mask of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE_Msk = 0x200000
	// Bit BUSYD0ENDIE.
	SDMMC_MASKR_BUSYD0ENDIE = 0x200000
	// Position of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE_Pos = 0x16
	// Bit mask of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE_Msk = 0x400000
	// Bit SDIOITIE.
	SDMMC_MASKR_SDIOITIE = 0x400000
	// Position of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE_Pos = 0x17
	// Bit mask of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE_Msk = 0x800000
	// Bit ACKFAILIE.
	SDMMC_MASKR_ACKFAILIE = 0x800000
	// Position of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE_Pos = 0x18
	// Bit mask of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE_Msk = 0x1000000
	// Bit ACKTIMEOUTIE.
	SDMMC_MASKR_ACKTIMEOUTIE = 0x1000000
	// Position of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE_Pos = 0x19
	// Bit mask of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE_Msk = 0x2000000
	// Bit VSWENDIE.
	SDMMC_MASKR_VSWENDIE = 0x2000000
	// Position of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE_Pos = 0x1a
	// Bit mask of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE_Msk = 0x4000000
	// Bit CKSTOPIE.
	SDMMC_MASKR_CKSTOPIE = 0x4000000
	// Position of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE_Pos = 0x1c
	// Bit mask of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE_Msk = 0x10000000
	// Bit IDMABTCIE.
	SDMMC_MASKR_IDMABTCIE = 0x10000000

	// ACKTIMER: The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.
	// Position of ACKTIME field.
	SDMMC_ACKTIMER_ACKTIME_Pos = 0x0
	// Bit mask of ACKTIME field.
	SDMMC_ACKTIMER_ACKTIME_Msk = 0x1ffffff

	// IDMACTRLR: The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
	// Position of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN_Pos = 0x0
	// Bit mask of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN_Msk = 0x1
	// Bit IDMAEN.
	SDMMC_IDMACTRLR_IDMAEN = 0x1
	// Position of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE_Pos = 0x1
	// Bit mask of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE_Msk = 0x2
	// Bit IDMABMODE.
	SDMMC_IDMACTRLR_IDMABMODE = 0x2
	// Position of IDMABACT field.
	SDMMC_IDMACTRLR_IDMABACT_Pos = 0x2
	// Bit mask of IDMABACT field.
	SDMMC_IDMACTRLR_IDMABACT_Msk = 0x4
	// Bit IDMABACT.
	SDMMC_IDMACTRLR_IDMABACT = 0x4

	// IDMABSIZER: The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.
	// Position of IDMABNDT field.
	SDMMC_IDMABSIZER_IDMABNDT_Pos = 0x5
	// Bit mask of IDMABNDT field.
	SDMMC_IDMABSIZER_IDMABNDT_Msk = 0x1fe0

	// IDMABASE0R: The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.
	// Position of IDMABASE0 field.
	SDMMC_IDMABASE0R_IDMABASE0_Pos = 0x0
	// Bit mask of IDMABASE0 field.
	SDMMC_IDMABASE0R_IDMABASE0_Msk = 0xffffffff

	// IDMABASE1R: The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.
	// Position of IDMABASE1 field.
	SDMMC_IDMABASE1R_IDMABASE1_Pos = 0x0
	// Bit mask of IDMABASE1 field.
	SDMMC_IDMABASE1R_IDMABASE1_Msk = 0xffffffff

	// FIFOR: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC_FIFOR_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC_FIFOR_FIFODATA_Msk = 0xffffffff

	// VER: SDMMC IP version register
	// Position of MINREV field.
	SDMMC_VER_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	SDMMC_VER_MINREV_Msk = 0xf
	// Position of MAJREV field.
	SDMMC_VER_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	SDMMC_VER_MAJREV_Msk = 0xf0

	// ID: SDMMC IP identification register
	// Position of IP_ID field.
	SDMMC_ID_IP_ID_Pos = 0x0
	// Bit mask of IP_ID field.
	SDMMC_ID_IP_ID_Msk = 0xffffffff
)

// Bitfields for VREFBUF: VREFBUF
const (
	// CSR: VREFBUF control and status register
	// Position of ENVR field.
	VREFBUF_CSR_ENVR_Pos = 0x0
	// Bit mask of ENVR field.
	VREFBUF_CSR_ENVR_Msk = 0x1
	// Bit ENVR.
	VREFBUF_CSR_ENVR = 0x1
	// Position of HIZ field.
	VREFBUF_CSR_HIZ_Pos = 0x1
	// Bit mask of HIZ field.
	VREFBUF_CSR_HIZ_Msk = 0x2
	// Bit HIZ.
	VREFBUF_CSR_HIZ = 0x2
	// Position of VRR field.
	VREFBUF_CSR_VRR_Pos = 0x3
	// Bit mask of VRR field.
	VREFBUF_CSR_VRR_Msk = 0x8
	// Bit VRR.
	VREFBUF_CSR_VRR = 0x8
	// Position of VRS field.
	VREFBUF_CSR_VRS_Pos = 0x4
	// Bit mask of VRS field.
	VREFBUF_CSR_VRS_Msk = 0x70

	// CCR: VREFBUF calibration control register
	// Position of TRIM field.
	VREFBUF_CCR_TRIM_Pos = 0x0
	// Bit mask of TRIM field.
	VREFBUF_CCR_TRIM_Msk = 0x3f
)

// Bitfields for IWDG: IWDG
const (
	// KR: Key register
	// Position of KEY field.
	IWDG_KR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	IWDG_KR_KEY_Msk = 0xffff
	// Enable access to PR, RLR and WINR registers (0x5555)
	IWDG_KR_KEY_Enable = 0x5555
	// Reset the watchdog value (0xAAAA)
	IWDG_KR_KEY_Reset = 0xaaaa
	// Start the watchdog (0xCCCC)
	IWDG_KR_KEY_Start = 0xcccc

	// PR: Prescaler register
	// Position of PR field.
	IWDG_PR_PR_Pos = 0x0
	// Bit mask of PR field.
	IWDG_PR_PR_Msk = 0x7
	// Divider /4
	IWDG_PR_PR_DivideBy4 = 0x0
	// Divider /8
	IWDG_PR_PR_DivideBy8 = 0x1
	// Divider /16
	IWDG_PR_PR_DivideBy16 = 0x2
	// Divider /32
	IWDG_PR_PR_DivideBy32 = 0x3
	// Divider /64
	IWDG_PR_PR_DivideBy64 = 0x4
	// Divider /128
	IWDG_PR_PR_DivideBy128 = 0x5
	// Divider /256
	IWDG_PR_PR_DivideBy256 = 0x6
	// Divider /256
	IWDG_PR_PR_DivideBy256bis = 0x7

	// RLR: Reload register
	// Position of RL field.
	IWDG_RLR_RL_Pos = 0x0
	// Bit mask of RL field.
	IWDG_RLR_RL_Msk = 0xfff

	// SR: Status register
	// Position of PVU field.
	IWDG_SR_PVU_Pos = 0x0
	// Bit mask of PVU field.
	IWDG_SR_PVU_Msk = 0x1
	// Bit PVU.
	IWDG_SR_PVU = 0x1
	// Position of RVU field.
	IWDG_SR_RVU_Pos = 0x1
	// Bit mask of RVU field.
	IWDG_SR_RVU_Msk = 0x2
	// Bit RVU.
	IWDG_SR_RVU = 0x2
	// Position of WVU field.
	IWDG_SR_WVU_Pos = 0x2
	// Bit mask of WVU field.
	IWDG_SR_WVU_Msk = 0x4
	// Bit WVU.
	IWDG_SR_WVU = 0x4

	// WINR: Window register
	// Position of WIN field.
	IWDG_WINR_WIN_Pos = 0x0
	// Bit mask of WIN field.
	IWDG_WINR_WIN_Msk = 0xfff
)

// Bitfields for WWDG: WWDG
const (
	// CR: Control register
	// Position of T field.
	WWDG_CR_T_Pos = 0x0
	// Bit mask of T field.
	WWDG_CR_T_Msk = 0x7f
	// Position of WDGA field.
	WWDG_CR_WDGA_Pos = 0x7
	// Bit mask of WDGA field.
	WWDG_CR_WDGA_Msk = 0x80
	// Bit WDGA.
	WWDG_CR_WDGA = 0x80
	// Watchdog disabled
	WWDG_CR_WDGA_Disabled = 0x0
	// Watchdog enabled
	WWDG_CR_WDGA_Enabled = 0x1

	// CFR: Configuration register
	// Position of W field.
	WWDG_CFR_W_Pos = 0x0
	// Bit mask of W field.
	WWDG_CFR_W_Msk = 0x7f
	// Position of EWI field.
	WWDG_CFR_EWI_Pos = 0x9
	// Bit mask of EWI field.
	WWDG_CFR_EWI_Msk = 0x200
	// Bit EWI.
	WWDG_CFR_EWI = 0x200
	// interrupt occurs whenever the counter reaches the value 0x40
	WWDG_CFR_EWI_Enable = 0x1
	// Position of WDGTB field.
	WWDG_CFR_WDGTB_Pos = 0xb
	// Bit mask of WDGTB field.
	WWDG_CFR_WDGTB_Msk = 0x3800
	// Counter clock (PCLK1 div 4096) div 16
	WWDG_CFR_WDGTB_Div16 = 0x4
	// Counter clock (PCLK1 div 4096) div 32
	WWDG_CFR_WDGTB_Div32 = 0x5
	// Counter clock (PCLK1 div 4096) div 64
	WWDG_CFR_WDGTB_Div64 = 0x6
	// Counter clock (PCLK1 div 4096) div 128
	WWDG_CFR_WDGTB_Div128 = 0x7
	// Counter clock (PCLK1 div 4096) div 1
	WWDG_CFR_WDGTB_Div1 = 0x0
	// Counter clock (PCLK1 div 4096) div 2
	WWDG_CFR_WDGTB_Div2 = 0x1
	// Counter clock (PCLK1 div 4096) div 4
	WWDG_CFR_WDGTB_Div4 = 0x2
	// Counter clock (PCLK1 div 4096) div 8
	WWDG_CFR_WDGTB_Div8 = 0x3

	// SR: Status register
	// Position of EWIF field.
	WWDG_SR_EWIF_Pos = 0x0
	// Bit mask of EWIF field.
	WWDG_SR_EWIF_Msk = 0x1
	// Bit EWIF.
	WWDG_SR_EWIF = 0x1
	// The EWI Interrupt Service Routine has been triggered
	WWDG_SR_EWIF_Pending = 0x1
	// The EWI Interrupt Service Routine has been serviced
	WWDG_SR_EWIF_Finished = 0x0
)

// Bitfields for PWR: PWR
const (
	// CR1: PWR control register 1
	// Position of LPDS field.
	PWR_CR1_LPDS_Pos = 0x0
	// Bit mask of LPDS field.
	PWR_CR1_LPDS_Msk = 0x1
	// Bit LPDS.
	PWR_CR1_LPDS = 0x1
	// Position of PVDE field.
	PWR_CR1_PVDE_Pos = 0x4
	// Bit mask of PVDE field.
	PWR_CR1_PVDE_Msk = 0x10
	// Bit PVDE.
	PWR_CR1_PVDE = 0x10
	// Position of PLS field.
	PWR_CR1_PLS_Pos = 0x5
	// Bit mask of PLS field.
	PWR_CR1_PLS_Msk = 0xe0
	// Position of DBP field.
	PWR_CR1_DBP_Pos = 0x8
	// Bit mask of DBP field.
	PWR_CR1_DBP_Msk = 0x100
	// Bit DBP.
	PWR_CR1_DBP = 0x100
	// Position of FLPS field.
	PWR_CR1_FLPS_Pos = 0x9
	// Bit mask of FLPS field.
	PWR_CR1_FLPS_Msk = 0x200
	// Bit FLPS.
	PWR_CR1_FLPS = 0x200
	// Position of SVOS field.
	PWR_CR1_SVOS_Pos = 0xe
	// Bit mask of SVOS field.
	PWR_CR1_SVOS_Msk = 0xc000
	// Position of AVDEN field.
	PWR_CR1_AVDEN_Pos = 0x10
	// Bit mask of AVDEN field.
	PWR_CR1_AVDEN_Msk = 0x10000
	// Bit AVDEN.
	PWR_CR1_AVDEN = 0x10000
	// Position of ALS field.
	PWR_CR1_ALS_Pos = 0x11
	// Bit mask of ALS field.
	PWR_CR1_ALS_Msk = 0x60000

	// CSR1: PWR control status register 1
	// Position of PVDO field.
	PWR_CSR1_PVDO_Pos = 0x4
	// Bit mask of PVDO field.
	PWR_CSR1_PVDO_Msk = 0x10
	// Bit PVDO.
	PWR_CSR1_PVDO = 0x10
	// Position of ACTVOSRDY field.
	PWR_CSR1_ACTVOSRDY_Pos = 0xd
	// Bit mask of ACTVOSRDY field.
	PWR_CSR1_ACTVOSRDY_Msk = 0x2000
	// Bit ACTVOSRDY.
	PWR_CSR1_ACTVOSRDY = 0x2000
	// Position of ACTVOS field.
	PWR_CSR1_ACTVOS_Pos = 0xe
	// Bit mask of ACTVOS field.
	PWR_CSR1_ACTVOS_Msk = 0xc000
	// Position of AVDO field.
	PWR_CSR1_AVDO_Pos = 0x10
	// Bit mask of AVDO field.
	PWR_CSR1_AVDO_Msk = 0x10000
	// Bit AVDO.
	PWR_CSR1_AVDO = 0x10000

	// CR2: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
	// Position of BREN field.
	PWR_CR2_BREN_Pos = 0x0
	// Bit mask of BREN field.
	PWR_CR2_BREN_Msk = 0x1
	// Bit BREN.
	PWR_CR2_BREN = 0x1
	// Position of MONEN field.
	PWR_CR2_MONEN_Pos = 0x4
	// Bit mask of MONEN field.
	PWR_CR2_MONEN_Msk = 0x10
	// Bit MONEN.
	PWR_CR2_MONEN = 0x10
	// Position of BRRDY field.
	PWR_CR2_BRRDY_Pos = 0x10
	// Bit mask of BRRDY field.
	PWR_CR2_BRRDY_Msk = 0x10000
	// Bit BRRDY.
	PWR_CR2_BRRDY = 0x10000
	// Position of VBATL field.
	PWR_CR2_VBATL_Pos = 0x14
	// Bit mask of VBATL field.
	PWR_CR2_VBATL_Msk = 0x100000
	// Bit VBATL.
	PWR_CR2_VBATL = 0x100000
	// Position of VBATH field.
	PWR_CR2_VBATH_Pos = 0x15
	// Bit mask of VBATH field.
	PWR_CR2_VBATH_Msk = 0x200000
	// Bit VBATH.
	PWR_CR2_VBATH = 0x200000
	// Position of TEMPL field.
	PWR_CR2_TEMPL_Pos = 0x16
	// Bit mask of TEMPL field.
	PWR_CR2_TEMPL_Msk = 0x400000
	// Bit TEMPL.
	PWR_CR2_TEMPL = 0x400000
	// Position of TEMPH field.
	PWR_CR2_TEMPH_Pos = 0x17
	// Bit mask of TEMPH field.
	PWR_CR2_TEMPH_Msk = 0x800000
	// Bit TEMPH.
	PWR_CR2_TEMPH = 0x800000

	// CR3: Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.
	// Position of BYPASS field.
	PWR_CR3_BYPASS_Pos = 0x0
	// Bit mask of BYPASS field.
	PWR_CR3_BYPASS_Msk = 0x1
	// Bit BYPASS.
	PWR_CR3_BYPASS = 0x1
	// Position of LDOEN field.
	PWR_CR3_LDOEN_Pos = 0x1
	// Bit mask of LDOEN field.
	PWR_CR3_LDOEN_Msk = 0x2
	// Bit LDOEN.
	PWR_CR3_LDOEN = 0x2
	// Position of SCUEN field.
	PWR_CR3_SCUEN_Pos = 0x2
	// Bit mask of SCUEN field.
	PWR_CR3_SCUEN_Msk = 0x4
	// Bit SCUEN.
	PWR_CR3_SCUEN = 0x4
	// Position of VBE field.
	PWR_CR3_VBE_Pos = 0x8
	// Bit mask of VBE field.
	PWR_CR3_VBE_Msk = 0x100
	// Bit VBE.
	PWR_CR3_VBE = 0x100
	// Position of VBRS field.
	PWR_CR3_VBRS_Pos = 0x9
	// Bit mask of VBRS field.
	PWR_CR3_VBRS_Msk = 0x200
	// Bit VBRS.
	PWR_CR3_VBRS = 0x200
	// Position of USB33DEN field.
	PWR_CR3_USB33DEN_Pos = 0x18
	// Bit mask of USB33DEN field.
	PWR_CR3_USB33DEN_Msk = 0x1000000
	// Bit USB33DEN.
	PWR_CR3_USB33DEN = 0x1000000
	// Position of USBREGEN field.
	PWR_CR3_USBREGEN_Pos = 0x19
	// Bit mask of USBREGEN field.
	PWR_CR3_USBREGEN_Msk = 0x2000000
	// Bit USBREGEN.
	PWR_CR3_USBREGEN = 0x2000000
	// Position of USB33RDY field.
	PWR_CR3_USB33RDY_Pos = 0x1a
	// Bit mask of USB33RDY field.
	PWR_CR3_USB33RDY_Msk = 0x4000000
	// Bit USB33RDY.
	PWR_CR3_USB33RDY = 0x4000000

	// CPUCR: This register allows controlling CPU1 power.
	// Position of PDDS_D1 field.
	PWR_CPUCR_PDDS_D1_Pos = 0x0
	// Bit mask of PDDS_D1 field.
	PWR_CPUCR_PDDS_D1_Msk = 0x1
	// Bit PDDS_D1.
	PWR_CPUCR_PDDS_D1 = 0x1
	// Position of PDDS_D2 field.
	PWR_CPUCR_PDDS_D2_Pos = 0x1
	// Bit mask of PDDS_D2 field.
	PWR_CPUCR_PDDS_D2_Msk = 0x2
	// Bit PDDS_D2.
	PWR_CPUCR_PDDS_D2 = 0x2
	// Position of PDDS_D3 field.
	PWR_CPUCR_PDDS_D3_Pos = 0x2
	// Bit mask of PDDS_D3 field.
	PWR_CPUCR_PDDS_D3_Msk = 0x4
	// Bit PDDS_D3.
	PWR_CPUCR_PDDS_D3 = 0x4
	// Position of STOPF field.
	PWR_CPUCR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	PWR_CPUCR_STOPF_Msk = 0x20
	// Bit STOPF.
	PWR_CPUCR_STOPF = 0x20
	// Position of SBF field.
	PWR_CPUCR_SBF_Pos = 0x6
	// Bit mask of SBF field.
	PWR_CPUCR_SBF_Msk = 0x40
	// Bit SBF.
	PWR_CPUCR_SBF = 0x40
	// Position of SBF_D1 field.
	PWR_CPUCR_SBF_D1_Pos = 0x7
	// Bit mask of SBF_D1 field.
	PWR_CPUCR_SBF_D1_Msk = 0x80
	// Bit SBF_D1.
	PWR_CPUCR_SBF_D1 = 0x80
	// Position of SBF_D2 field.
	PWR_CPUCR_SBF_D2_Pos = 0x8
	// Bit mask of SBF_D2 field.
	PWR_CPUCR_SBF_D2_Msk = 0x100
	// Bit SBF_D2.
	PWR_CPUCR_SBF_D2 = 0x100
	// Position of CSSF field.
	PWR_CPUCR_CSSF_Pos = 0x9
	// Bit mask of CSSF field.
	PWR_CPUCR_CSSF_Msk = 0x200
	// Bit CSSF.
	PWR_CPUCR_CSSF = 0x200
	// Position of RUN_D3 field.
	PWR_CPUCR_RUN_D3_Pos = 0xb
	// Bit mask of RUN_D3 field.
	PWR_CPUCR_RUN_D3_Msk = 0x800
	// Bit RUN_D3.
	PWR_CPUCR_RUN_D3 = 0x800

	// D3CR: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
	// Position of VOSRDY field.
	PWR_D3CR_VOSRDY_Pos = 0xd
	// Bit mask of VOSRDY field.
	PWR_D3CR_VOSRDY_Msk = 0x2000
	// Bit VOSRDY.
	PWR_D3CR_VOSRDY = 0x2000
	// Position of VOS field.
	PWR_D3CR_VOS_Pos = 0xe
	// Bit mask of VOS field.
	PWR_D3CR_VOS_Msk = 0xc000

	// WKUPCR: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
	// Position of WKUPC field.
	PWR_WKUPCR_WKUPC_Pos = 0x0
	// Bit mask of WKUPC field.
	PWR_WKUPCR_WKUPC_Msk = 0x3f

	// WKUPFR: reset only by system reset, not reset by wakeup from Standby mode
	// Position of WKUPF1 field.
	PWR_WKUPFR_WKUPF1_Pos = 0x0
	// Bit mask of WKUPF1 field.
	PWR_WKUPFR_WKUPF1_Msk = 0x1
	// Bit WKUPF1.
	PWR_WKUPFR_WKUPF1 = 0x1
	// Position of WKUPF2 field.
	PWR_WKUPFR_WKUPF2_Pos = 0x1
	// Bit mask of WKUPF2 field.
	PWR_WKUPFR_WKUPF2_Msk = 0x2
	// Bit WKUPF2.
	PWR_WKUPFR_WKUPF2 = 0x2
	// Position of WKUPF3 field.
	PWR_WKUPFR_WKUPF3_Pos = 0x2
	// Bit mask of WKUPF3 field.
	PWR_WKUPFR_WKUPF3_Msk = 0x4
	// Bit WKUPF3.
	PWR_WKUPFR_WKUPF3 = 0x4
	// Position of WKUPF4 field.
	PWR_WKUPFR_WKUPF4_Pos = 0x3
	// Bit mask of WKUPF4 field.
	PWR_WKUPFR_WKUPF4_Msk = 0x8
	// Bit WKUPF4.
	PWR_WKUPFR_WKUPF4 = 0x8
	// Position of WKUPF5 field.
	PWR_WKUPFR_WKUPF5_Pos = 0x4
	// Bit mask of WKUPF5 field.
	PWR_WKUPFR_WKUPF5_Msk = 0x10
	// Bit WKUPF5.
	PWR_WKUPFR_WKUPF5 = 0x10
	// Position of WKUPF6 field.
	PWR_WKUPFR_WKUPF6_Pos = 0x5
	// Bit mask of WKUPF6 field.
	PWR_WKUPFR_WKUPF6_Msk = 0x20
	// Bit WKUPF6.
	PWR_WKUPFR_WKUPF6 = 0x20

	// WKUPEPR: Reset only by system reset, not reset by wakeup from Standby mode
	// Position of WKUPEN1 field.
	PWR_WKUPEPR_WKUPEN1_Pos = 0x0
	// Bit mask of WKUPEN1 field.
	PWR_WKUPEPR_WKUPEN1_Msk = 0x1
	// Bit WKUPEN1.
	PWR_WKUPEPR_WKUPEN1 = 0x1
	// Position of WKUPEN2 field.
	PWR_WKUPEPR_WKUPEN2_Pos = 0x1
	// Bit mask of WKUPEN2 field.
	PWR_WKUPEPR_WKUPEN2_Msk = 0x2
	// Bit WKUPEN2.
	PWR_WKUPEPR_WKUPEN2 = 0x2
	// Position of WKUPEN3 field.
	PWR_WKUPEPR_WKUPEN3_Pos = 0x2
	// Bit mask of WKUPEN3 field.
	PWR_WKUPEPR_WKUPEN3_Msk = 0x4
	// Bit WKUPEN3.
	PWR_WKUPEPR_WKUPEN3 = 0x4
	// Position of WKUPEN4 field.
	PWR_WKUPEPR_WKUPEN4_Pos = 0x3
	// Bit mask of WKUPEN4 field.
	PWR_WKUPEPR_WKUPEN4_Msk = 0x8
	// Bit WKUPEN4.
	PWR_WKUPEPR_WKUPEN4 = 0x8
	// Position of WKUPEN5 field.
	PWR_WKUPEPR_WKUPEN5_Pos = 0x4
	// Bit mask of WKUPEN5 field.
	PWR_WKUPEPR_WKUPEN5_Msk = 0x10
	// Bit WKUPEN5.
	PWR_WKUPEPR_WKUPEN5 = 0x10
	// Position of WKUPEN6 field.
	PWR_WKUPEPR_WKUPEN6_Pos = 0x5
	// Bit mask of WKUPEN6 field.
	PWR_WKUPEPR_WKUPEN6_Msk = 0x20
	// Bit WKUPEN6.
	PWR_WKUPEPR_WKUPEN6 = 0x20
	// Position of WKUPP1 field.
	PWR_WKUPEPR_WKUPP1_Pos = 0x8
	// Bit mask of WKUPP1 field.
	PWR_WKUPEPR_WKUPP1_Msk = 0x100
	// Bit WKUPP1.
	PWR_WKUPEPR_WKUPP1 = 0x100
	// Position of WKUPP2 field.
	PWR_WKUPEPR_WKUPP2_Pos = 0x9
	// Bit mask of WKUPP2 field.
	PWR_WKUPEPR_WKUPP2_Msk = 0x200
	// Bit WKUPP2.
	PWR_WKUPEPR_WKUPP2 = 0x200
	// Position of WKUPP3 field.
	PWR_WKUPEPR_WKUPP3_Pos = 0xa
	// Bit mask of WKUPP3 field.
	PWR_WKUPEPR_WKUPP3_Msk = 0x400
	// Bit WKUPP3.
	PWR_WKUPEPR_WKUPP3 = 0x400
	// Position of WKUPP4 field.
	PWR_WKUPEPR_WKUPP4_Pos = 0xb
	// Bit mask of WKUPP4 field.
	PWR_WKUPEPR_WKUPP4_Msk = 0x800
	// Bit WKUPP4.
	PWR_WKUPEPR_WKUPP4 = 0x800
	// Position of WKUPP5 field.
	PWR_WKUPEPR_WKUPP5_Pos = 0xc
	// Bit mask of WKUPP5 field.
	PWR_WKUPEPR_WKUPP5_Msk = 0x1000
	// Bit WKUPP5.
	PWR_WKUPEPR_WKUPP5 = 0x1000
	// Position of WKUPP6 field.
	PWR_WKUPEPR_WKUPP6_Pos = 0xd
	// Bit mask of WKUPP6 field.
	PWR_WKUPEPR_WKUPP6_Msk = 0x2000
	// Bit WKUPP6.
	PWR_WKUPEPR_WKUPP6 = 0x2000
	// Position of WKUPPUPD1 field.
	PWR_WKUPEPR_WKUPPUPD1_Pos = 0x10
	// Bit mask of WKUPPUPD1 field.
	PWR_WKUPEPR_WKUPPUPD1_Msk = 0x30000
	// Position of WKUPPUPD2 field.
	PWR_WKUPEPR_WKUPPUPD2_Pos = 0x12
	// Bit mask of WKUPPUPD2 field.
	PWR_WKUPEPR_WKUPPUPD2_Msk = 0xc0000
	// Position of WKUPPUPD3 field.
	PWR_WKUPEPR_WKUPPUPD3_Pos = 0x14
	// Bit mask of WKUPPUPD3 field.
	PWR_WKUPEPR_WKUPPUPD3_Msk = 0x300000
	// Position of WKUPPUPD4 field.
	PWR_WKUPEPR_WKUPPUPD4_Pos = 0x16
	// Bit mask of WKUPPUPD4 field.
	PWR_WKUPEPR_WKUPPUPD4_Msk = 0xc00000
	// Position of WKUPPUPD5 field.
	PWR_WKUPEPR_WKUPPUPD5_Pos = 0x18
	// Bit mask of WKUPPUPD5 field.
	PWR_WKUPEPR_WKUPPUPD5_Msk = 0x3000000
	// Position of WKUPPUPD6 field.
	PWR_WKUPEPR_WKUPPUPD6_Pos = 0x1a
	// Bit mask of WKUPPUPD6 field.
	PWR_WKUPEPR_WKUPPUPD6_Msk = 0xc000000
)

// Bitfields for SPI1: Serial peripheral interface
const (
	// CR1: control register 1
	// Position of IOLOCK field.
	SPI_CR1_IOLOCK_Pos = 0x10
	// Bit mask of IOLOCK field.
	SPI_CR1_IOLOCK_Msk = 0x10000
	// Bit IOLOCK.
	SPI_CR1_IOLOCK = 0x10000
	// IO configuration unlocked
	SPI_CR1_IOLOCK_Unlocked = 0x0
	// IO configuration locked
	SPI_CR1_IOLOCK_Locked = 0x1
	// Position of TCRCINI field.
	SPI_CR1_TCRCINI_Pos = 0xf
	// Bit mask of TCRCINI field.
	SPI_CR1_TCRCINI_Msk = 0x8000
	// Bit TCRCINI.
	SPI_CR1_TCRCINI = 0x8000
	// All zeros TX CRC initialization pattern
	SPI_CR1_TCRCINI_AllZeros = 0x0
	// All ones TX CRC initialization pattern
	SPI_CR1_TCRCINI_AllOnes = 0x1
	// Position of RCRCINI field.
	SPI_CR1_RCRCINI_Pos = 0xe
	// Bit mask of RCRCINI field.
	SPI_CR1_RCRCINI_Msk = 0x4000
	// Bit RCRCINI.
	SPI_CR1_RCRCINI = 0x4000
	// All zeros RX CRC initialization pattern
	SPI_CR1_RCRCINI_AllZeros = 0x0
	// All ones RX CRC initialization pattern
	SPI_CR1_RCRCINI_AllOnes = 0x1
	// Position of CRC33_17 field.
	SPI_CR1_CRC33_17_Pos = 0xd
	// Bit mask of CRC33_17 field.
	SPI_CR1_CRC33_17_Msk = 0x2000
	// Bit CRC33_17.
	SPI_CR1_CRC33_17 = 0x2000
	// Full size (33/17 bit) CRC polynomial is not used
	SPI_CR1_CRC33_17_Disabled = 0x0
	// Full size (33/17 bit) CRC polynomial is used
	SPI_CR1_CRC33_17_Enabled = 0x1
	// Position of SSI field.
	SPI_CR1_SSI_Pos = 0xc
	// Bit mask of SSI field.
	SPI_CR1_SSI_Msk = 0x1000
	// Bit SSI.
	SPI_CR1_SSI = 0x1000
	// 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
	SPI_CR1_SSI_SlaveSelected = 0x0
	// 1 is forced onto the SS signal and the I/O value of the SS pin is ignored
	SPI_CR1_SSI_SlaveNotSelected = 0x1
	// Position of HDDIR field.
	SPI_CR1_HDDIR_Pos = 0xb
	// Bit mask of HDDIR field.
	SPI_CR1_HDDIR_Msk = 0x800
	// Bit HDDIR.
	SPI_CR1_HDDIR = 0x800
	// Receiver in half duplex mode
	SPI_CR1_HDDIR_Receiver = 0x0
	// Transmitter in half duplex mode
	SPI_CR1_HDDIR_Transmitter = 0x1
	// Position of CSUSP field.
	SPI_CR1_CSUSP_Pos = 0xa
	// Bit mask of CSUSP field.
	SPI_CR1_CSUSP_Msk = 0x400
	// Bit CSUSP.
	SPI_CR1_CSUSP = 0x400
	// Do not request master suspend
	SPI_CR1_CSUSP_NotRequested = 0x0
	// Request master suspend
	SPI_CR1_CSUSP_Requested = 0x1
	// Position of CSTART field.
	SPI_CR1_CSTART_Pos = 0x9
	// Bit mask of CSTART field.
	SPI_CR1_CSTART_Msk = 0x200
	// Bit CSTART.
	SPI_CR1_CSTART = 0x200
	// Do not start master transfer
	SPI_CR1_CSTART_NotStarted = 0x0
	// Start master transfer
	SPI_CR1_CSTART_Started = 0x1
	// Position of MASRX field.
	SPI_CR1_MASRX_Pos = 0x8
	// Bit mask of MASRX field.
	SPI_CR1_MASRX_Msk = 0x100
	// Bit MASRX.
	SPI_CR1_MASRX = 0x100
	// Automatic suspend in master receive-only mode disabled
	SPI_CR1_MASRX_Disabled = 0x0
	// Automatic suspend in master receive-only mode enabled
	SPI_CR1_MASRX_Enabled = 0x1
	// Position of SPE field.
	SPI_CR1_SPE_Pos = 0x0
	// Bit mask of SPE field.
	SPI_CR1_SPE_Msk = 0x1
	// Bit SPE.
	SPI_CR1_SPE = 0x1
	// Peripheral disabled
	SPI_CR1_SPE_Disabled = 0x0
	// Peripheral enabled
	SPI_CR1_SPE_Enabled = 0x1

	// CR2: control register 2
	// Position of TSER field.
	SPI_CR2_TSER_Pos = 0x10
	// Bit mask of TSER field.
	SPI_CR2_TSER_Msk = 0xffff0000
	// Position of TSIZE field.
	SPI_CR2_TSIZE_Pos = 0x0
	// Bit mask of TSIZE field.
	SPI_CR2_TSIZE_Msk = 0xffff

	// CFG1: configuration register 1
	// Position of MBR field.
	SPI_CFG1_MBR_Pos = 0x1c
	// Bit mask of MBR field.
	SPI_CFG1_MBR_Msk = 0x70000000
	// f_spi_ker_ck / 2
	SPI_CFG1_MBR_Div2 = 0x0
	// f_spi_ker_ck / 4
	SPI_CFG1_MBR_Div4 = 0x1
	// f_spi_ker_ck / 8
	SPI_CFG1_MBR_Div8 = 0x2
	// f_spi_ker_ck / 16
	SPI_CFG1_MBR_Div16 = 0x3
	// f_spi_ker_ck / 32
	SPI_CFG1_MBR_Div32 = 0x4
	// f_spi_ker_ck / 64
	SPI_CFG1_MBR_Div64 = 0x5
	// f_spi_ker_ck / 128
	SPI_CFG1_MBR_Div128 = 0x6
	// f_spi_ker_ck / 256
	SPI_CFG1_MBR_Div256 = 0x7
	// Position of CRCEN field.
	SPI_CFG1_CRCEN_Pos = 0x16
	// Bit mask of CRCEN field.
	SPI_CFG1_CRCEN_Msk = 0x400000
	// Bit CRCEN.
	SPI_CFG1_CRCEN = 0x400000
	// CRC calculation disabled
	SPI_CFG1_CRCEN_Disabled = 0x0
	// CRC calculation enabled
	SPI_CFG1_CRCEN_Enabled = 0x1
	// Position of CRCSIZE field.
	SPI_CFG1_CRCSIZE_Pos = 0x10
	// Bit mask of CRCSIZE field.
	SPI_CFG1_CRCSIZE_Msk = 0x1f0000
	// Position of TXDMAEN field.
	SPI_CFG1_TXDMAEN_Pos = 0xf
	// Bit mask of TXDMAEN field.
	SPI_CFG1_TXDMAEN_Msk = 0x8000
	// Bit TXDMAEN.
	SPI_CFG1_TXDMAEN = 0x8000
	// Tx buffer DMA disabled
	SPI_CFG1_TXDMAEN_Disabled = 0x0
	// Tx buffer DMA enabled
	SPI_CFG1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	SPI_CFG1_RXDMAEN_Pos = 0xe
	// Bit mask of RXDMAEN field.
	SPI_CFG1_RXDMAEN_Msk = 0x4000
	// Bit RXDMAEN.
	SPI_CFG1_RXDMAEN = 0x4000
	// Rx buffer DMA disabled
	SPI_CFG1_RXDMAEN_Disabled = 0x0
	// Rx buffer DMA enabled
	SPI_CFG1_RXDMAEN_Enabled = 0x1
	// Position of UDRDET field.
	SPI_CFG1_UDRDET_Pos = 0xb
	// Bit mask of UDRDET field.
	SPI_CFG1_UDRDET_Msk = 0x1800
	// Underrun is detected at begin of data frame
	SPI_CFG1_UDRDET_StartOfFrame = 0x0
	// Underrun is detected at end of last data frame
	SPI_CFG1_UDRDET_EndOfFrame = 0x1
	// Underrun is detected at begin of active SS signal
	SPI_CFG1_UDRDET_StartOfSlaveSelect = 0x2
	// Position of UDRCFG field.
	SPI_CFG1_UDRCFG_Pos = 0x9
	// Bit mask of UDRCFG field.
	SPI_CFG1_UDRCFG_Msk = 0x600
	// Slave sends a constant underrun pattern
	SPI_CFG1_UDRCFG_Constant = 0x0
	// Slave repeats last received data frame from master
	SPI_CFG1_UDRCFG_RepeatReceived = 0x1
	// Slave repeats last transmitted data frame
	SPI_CFG1_UDRCFG_RepeatTransmitted = 0x2
	// Position of FTHLV field.
	SPI_CFG1_FTHLV_Pos = 0x5
	// Bit mask of FTHLV field.
	SPI_CFG1_FTHLV_Msk = 0x1e0
	// 1 frame
	SPI_CFG1_FTHLV_OneFrame = 0x0
	// 2 frames
	SPI_CFG1_FTHLV_TwoFrames = 0x1
	// 3 frames
	SPI_CFG1_FTHLV_ThreeFrames = 0x2
	// 4 frames
	SPI_CFG1_FTHLV_FourFrames = 0x3
	// 5 frames
	SPI_CFG1_FTHLV_FiveFrames = 0x4
	// 6 frames
	SPI_CFG1_FTHLV_SixFrames = 0x5
	// 7 frames
	SPI_CFG1_FTHLV_SevenFrames = 0x6
	// 8 frames
	SPI_CFG1_FTHLV_EightFrames = 0x7
	// 9 frames
	SPI_CFG1_FTHLV_NineFrames = 0x8
	// 10 frames
	SPI_CFG1_FTHLV_TenFrames = 0x9
	// 11 frames
	SPI_CFG1_FTHLV_ElevenFrames = 0xa
	// 12 frames
	SPI_CFG1_FTHLV_TwelveFrames = 0xb
	// 13 frames
	SPI_CFG1_FTHLV_ThirteenFrames = 0xc
	// 14 frames
	SPI_CFG1_FTHLV_FourteenFrames = 0xd
	// 15 frames
	SPI_CFG1_FTHLV_FifteenFrames = 0xe
	// 16 frames
	SPI_CFG1_FTHLV_SixteenFrames = 0xf
	// Position of DSIZE field.
	SPI_CFG1_DSIZE_Pos = 0x0
	// Bit mask of DSIZE field.
	SPI_CFG1_DSIZE_Msk = 0x1f

	// CFG2: configuration register 2
	// Position of AFCNTR field.
	SPI_CFG2_AFCNTR_Pos = 0x1f
	// Bit mask of AFCNTR field.
	SPI_CFG2_AFCNTR_Msk = 0x80000000
	// Bit AFCNTR.
	SPI_CFG2_AFCNTR = 0x80000000
	// Peripheral takes no control of GPIOs while disabled
	SPI_CFG2_AFCNTR_NotControlled = 0x0
	// Peripheral controls GPIOs while disabled
	SPI_CFG2_AFCNTR_Controlled = 0x1
	// Position of SSOM field.
	SPI_CFG2_SSOM_Pos = 0x1e
	// Bit mask of SSOM field.
	SPI_CFG2_SSOM_Msk = 0x40000000
	// Bit SSOM.
	SPI_CFG2_SSOM = 0x40000000
	// SS is asserted until data transfer complete
	SPI_CFG2_SSOM_Asserted = 0x0
	// Data frames interleaved with SS not asserted during MIDI
	SPI_CFG2_SSOM_NotAsserted = 0x1
	// Position of SSOE field.
	SPI_CFG2_SSOE_Pos = 0x1d
	// Bit mask of SSOE field.
	SPI_CFG2_SSOE_Msk = 0x20000000
	// Bit SSOE.
	SPI_CFG2_SSOE = 0x20000000
	// SS output is disabled in master mode
	SPI_CFG2_SSOE_Disabled = 0x0
	// SS output is enabled in master mode
	SPI_CFG2_SSOE_Enabled = 0x1
	// Position of SSIOP field.
	SPI_CFG2_SSIOP_Pos = 0x1c
	// Bit mask of SSIOP field.
	SPI_CFG2_SSIOP_Msk = 0x10000000
	// Bit SSIOP.
	SPI_CFG2_SSIOP = 0x10000000
	// Low level is active for SS signal
	SPI_CFG2_SSIOP_ActiveLow = 0x0
	// High level is active for SS signal
	SPI_CFG2_SSIOP_ActiveHigh = 0x1
	// Position of SSM field.
	SPI_CFG2_SSM_Pos = 0x1a
	// Bit mask of SSM field.
	SPI_CFG2_SSM_Msk = 0x4000000
	// Bit SSM.
	SPI_CFG2_SSM = 0x4000000
	// Software slave management disabled
	SPI_CFG2_SSM_Disabled = 0x0
	// Software slave management enabled
	SPI_CFG2_SSM_Enabled = 0x1
	// Position of CPOL field.
	SPI_CFG2_CPOL_Pos = 0x19
	// Bit mask of CPOL field.
	SPI_CFG2_CPOL_Msk = 0x2000000
	// Bit CPOL.
	SPI_CFG2_CPOL = 0x2000000
	// CK to 0 when idle
	SPI_CFG2_CPOL_IdleLow = 0x0
	// CK to 1 when idle
	SPI_CFG2_CPOL_IdleHigh = 0x1
	// Position of CPHA field.
	SPI_CFG2_CPHA_Pos = 0x18
	// Bit mask of CPHA field.
	SPI_CFG2_CPHA_Msk = 0x1000000
	// Bit CPHA.
	SPI_CFG2_CPHA = 0x1000000
	// The first clock transition is the first data capture edge
	SPI_CFG2_CPHA_FirstEdge = 0x0
	// The second clock transition is the first data capture edge
	SPI_CFG2_CPHA_SecondEdge = 0x1
	// Position of LSBFRST field.
	SPI_CFG2_LSBFRST_Pos = 0x17
	// Bit mask of LSBFRST field.
	SPI_CFG2_LSBFRST_Msk = 0x800000
	// Bit LSBFRST.
	SPI_CFG2_LSBFRST = 0x800000
	// Data is transmitted/received with the MSB first
	SPI_CFG2_LSBFRST_MSBFirst = 0x0
	// Data is transmitted/received with the LSB first
	SPI_CFG2_LSBFRST_LSBFirst = 0x1
	// Position of MASTER field.
	SPI_CFG2_MASTER_Pos = 0x16
	// Bit mask of MASTER field.
	SPI_CFG2_MASTER_Msk = 0x400000
	// Bit MASTER.
	SPI_CFG2_MASTER = 0x400000
	// Slave configuration
	SPI_CFG2_MASTER_Slave = 0x0
	// Master configuration
	SPI_CFG2_MASTER_Master = 0x1
	// Position of SP field.
	SPI_CFG2_SP_Pos = 0x13
	// Bit mask of SP field.
	SPI_CFG2_SP_Msk = 0x380000
	// Motorola SPI protocol
	SPI_CFG2_SP_Motorola = 0x0
	// TI SPI protocol
	SPI_CFG2_SP_TI = 0x1
	// Position of COMM field.
	SPI_CFG2_COMM_Pos = 0x11
	// Bit mask of COMM field.
	SPI_CFG2_COMM_Msk = 0x60000
	// Full duplex
	SPI_CFG2_COMM_FullDuplex = 0x0
	// Simplex transmitter only
	SPI_CFG2_COMM_Transmitter = 0x1
	// Simplex receiver only
	SPI_CFG2_COMM_Receiver = 0x2
	// Half duplex
	SPI_CFG2_COMM_HalfDuplex = 0x3
	// Position of IOSWP field.
	SPI_CFG2_IOSWP_Pos = 0xf
	// Bit mask of IOSWP field.
	SPI_CFG2_IOSWP_Msk = 0x8000
	// Bit IOSWP.
	SPI_CFG2_IOSWP = 0x8000
	// MISO and MOSI not swapped
	SPI_CFG2_IOSWP_Disabled = 0x0
	// MISO and MOSI swapped
	SPI_CFG2_IOSWP_Enabled = 0x1
	// Position of MIDI field.
	SPI_CFG2_MIDI_Pos = 0x4
	// Bit mask of MIDI field.
	SPI_CFG2_MIDI_Msk = 0xf0
	// Position of MSSI field.
	SPI_CFG2_MSSI_Pos = 0x0
	// Bit mask of MSSI field.
	SPI_CFG2_MSSI_Msk = 0xf

	// IER: Interrupt Enable Register
	// Position of TSERFIE field.
	SPI_IER_TSERFIE_Pos = 0xa
	// Bit mask of TSERFIE field.
	SPI_IER_TSERFIE_Msk = 0x400
	// Bit TSERFIE.
	SPI_IER_TSERFIE = 0x400
	// TSER loaded interrupt masked
	SPI_IER_TSERFIE_Masked = 0x0
	// TSER loaded interrupt not masked
	SPI_IER_TSERFIE_NotMasked = 0x1
	// Position of MODFIE field.
	SPI_IER_MODFIE_Pos = 0x9
	// Bit mask of MODFIE field.
	SPI_IER_MODFIE_Msk = 0x200
	// Bit MODFIE.
	SPI_IER_MODFIE = 0x200
	// Mode fault interrupt masked
	SPI_IER_MODFIE_Masked = 0x0
	// Mode fault interrupt not masked
	SPI_IER_MODFIE_NotMasked = 0x1
	// Position of TIFREIE field.
	SPI_IER_TIFREIE_Pos = 0x8
	// Bit mask of TIFREIE field.
	SPI_IER_TIFREIE_Msk = 0x100
	// Bit TIFREIE.
	SPI_IER_TIFREIE = 0x100
	// TI frame format error interrupt masked
	SPI_IER_TIFREIE_Masked = 0x0
	// TI frame format error interrupt not masked
	SPI_IER_TIFREIE_NotMasked = 0x1
	// Position of CRCEIE field.
	SPI_IER_CRCEIE_Pos = 0x7
	// Bit mask of CRCEIE field.
	SPI_IER_CRCEIE_Msk = 0x80
	// Bit CRCEIE.
	SPI_IER_CRCEIE = 0x80
	// CRC error interrupt masked
	SPI_IER_CRCEIE_Masked = 0x0
	// CRC error interrupt not masked
	SPI_IER_CRCEIE_NotMasked = 0x1
	// Position of OVRIE field.
	SPI_IER_OVRIE_Pos = 0x6
	// Bit mask of OVRIE field.
	SPI_IER_OVRIE_Msk = 0x40
	// Bit OVRIE.
	SPI_IER_OVRIE = 0x40
	// Overrun interrupt masked
	SPI_IER_OVRIE_Masked = 0x0
	// Overrun interrupt not masked
	SPI_IER_OVRIE_NotMasked = 0x1
	// Position of UDRIE field.
	SPI_IER_UDRIE_Pos = 0x5
	// Bit mask of UDRIE field.
	SPI_IER_UDRIE_Msk = 0x20
	// Bit UDRIE.
	SPI_IER_UDRIE = 0x20
	// Underrun interrupt masked
	SPI_IER_UDRIE_Masked = 0x0
	// Underrun interrupt not masked
	SPI_IER_UDRIE_NotMasked = 0x1
	// Position of TXTFIE field.
	SPI_IER_TXTFIE_Pos = 0x4
	// Bit mask of TXTFIE field.
	SPI_IER_TXTFIE_Msk = 0x10
	// Bit TXTFIE.
	SPI_IER_TXTFIE = 0x10
	// Transmission transfer filled interrupt masked
	SPI_IER_TXTFIE_Masked = 0x0
	// Transmission transfer filled interrupt not masked
	SPI_IER_TXTFIE_NotMasked = 0x1
	// Position of EOTIE field.
	SPI_IER_EOTIE_Pos = 0x3
	// Bit mask of EOTIE field.
	SPI_IER_EOTIE_Msk = 0x8
	// Bit EOTIE.
	SPI_IER_EOTIE = 0x8
	// End-of-transfer interrupt masked
	SPI_IER_EOTIE_Masked = 0x0
	// End-of-transfer interrupt not masked
	SPI_IER_EOTIE_NotMasked = 0x1
	// Position of DXPIE field.
	SPI_IER_DXPIE_Pos = 0x2
	// Bit mask of DXPIE field.
	SPI_IER_DXPIE_Msk = 0x4
	// Bit DXPIE.
	SPI_IER_DXPIE = 0x4
	// Duplex transfer complete interrupt masked
	SPI_IER_DXPIE_Masked = 0x0
	// Duplex transfer complete interrupt not masked
	SPI_IER_DXPIE_NotMasked = 0x1
	// Position of TXPIE field.
	SPI_IER_TXPIE_Pos = 0x1
	// Bit mask of TXPIE field.
	SPI_IER_TXPIE_Msk = 0x2
	// Bit TXPIE.
	SPI_IER_TXPIE = 0x2
	// TX space available interrupt masked
	SPI_IER_TXPIE_Masked = 0x0
	// TX space available interrupt not masked
	SPI_IER_TXPIE_NotMasked = 0x1
	// Position of RXPIE field.
	SPI_IER_RXPIE_Pos = 0x0
	// Bit mask of RXPIE field.
	SPI_IER_RXPIE_Msk = 0x1
	// Bit RXPIE.
	SPI_IER_RXPIE = 0x1
	// RX data available interrupt masked
	SPI_IER_RXPIE_Masked = 0x0
	// RX data available interrupt not masked
	SPI_IER_RXPIE_NotMasked = 0x1

	// SR: Status Register
	// Position of CTSIZE field.
	SPI_SR_CTSIZE_Pos = 0x10
	// Bit mask of CTSIZE field.
	SPI_SR_CTSIZE_Msk = 0xffff0000
	// Position of RXWNE field.
	SPI_SR_RXWNE_Pos = 0xf
	// Bit mask of RXWNE field.
	SPI_SR_RXWNE_Msk = 0x8000
	// Bit RXWNE.
	SPI_SR_RXWNE = 0x8000
	// Less than 32-bit data frame received
	SPI_SR_RXWNE_LessThan32 = 0x0
	// At least 32-bit data frame received
	SPI_SR_RXWNE_AtLeast32 = 0x1
	// Position of RXPLVL field.
	SPI_SR_RXPLVL_Pos = 0xd
	// Bit mask of RXPLVL field.
	SPI_SR_RXPLVL_Msk = 0x6000
	// Zero frames beyond packing ratio available
	SPI_SR_RXPLVL_ZeroFrames = 0x0
	// One frame beyond packing ratio available
	SPI_SR_RXPLVL_OneFrame = 0x1
	// Two frame beyond packing ratio available
	SPI_SR_RXPLVL_TwoFrames = 0x2
	// Three frame beyond packing ratio available
	SPI_SR_RXPLVL_ThreeFrames = 0x3
	// Position of TXC field.
	SPI_SR_TXC_Pos = 0xc
	// Bit mask of TXC field.
	SPI_SR_TXC_Msk = 0x1000
	// Bit TXC.
	SPI_SR_TXC = 0x1000
	// Transmission ongoing
	SPI_SR_TXC_Ongoing = 0x0
	// Transmission completed
	SPI_SR_TXC_Completed = 0x1
	// Position of SUSP field.
	SPI_SR_SUSP_Pos = 0xb
	// Bit mask of SUSP field.
	SPI_SR_SUSP_Msk = 0x800
	// Bit SUSP.
	SPI_SR_SUSP = 0x800
	// Master not suspended
	SPI_SR_SUSP_NotSuspended = 0x0
	// Master suspended
	SPI_SR_SUSP_Suspended = 0x1
	// Position of TSERF field.
	SPI_SR_TSERF_Pos = 0xa
	// Bit mask of TSERF field.
	SPI_SR_TSERF_Msk = 0x400
	// Bit TSERF.
	SPI_SR_TSERF = 0x400
	// Additional number of SPI data to be transacted not yet loaded
	SPI_SR_TSERF_NotLoaded = 0x0
	// Additional number of SPI data to be transacted was reloaded
	SPI_SR_TSERF_Loaded = 0x1
	// Position of MODF field.
	SPI_SR_MODF_Pos = 0x9
	// Bit mask of MODF field.
	SPI_SR_MODF_Msk = 0x200
	// Bit MODF.
	SPI_SR_MODF = 0x200
	// No mode fault detected
	SPI_SR_MODF_NoFault = 0x0
	// Mode fault detected
	SPI_SR_MODF_Fault = 0x1
	// Position of TIFRE field.
	SPI_SR_TIFRE_Pos = 0x8
	// Bit mask of TIFRE field.
	SPI_SR_TIFRE_Msk = 0x100
	// Bit TIFRE.
	SPI_SR_TIFRE = 0x100
	// TI frame format error detected
	SPI_SR_TIFRE_NoError = 0x0
	// TI frame format error detected
	SPI_SR_TIFRE_Error = 0x1
	// Position of CRCE field.
	SPI_SR_CRCE_Pos = 0x7
	// Bit mask of CRCE field.
	SPI_SR_CRCE_Msk = 0x80
	// Bit CRCE.
	SPI_SR_CRCE = 0x80
	// No CRC error detected
	SPI_SR_CRCE_NoError = 0x0
	// CRC error detected
	SPI_SR_CRCE_Error = 0x1
	// Position of OVR field.
	SPI_SR_OVR_Pos = 0x6
	// Bit mask of OVR field.
	SPI_SR_OVR_Msk = 0x40
	// Bit OVR.
	SPI_SR_OVR = 0x40
	// No overrun occurred
	SPI_SR_OVR_NoOverrun = 0x0
	// Overrun occurred
	SPI_SR_OVR_Overrun = 0x1
	// Position of UDR field.
	SPI_SR_UDR_Pos = 0x5
	// Bit mask of UDR field.
	SPI_SR_UDR_Msk = 0x20
	// Bit UDR.
	SPI_SR_UDR = 0x20
	// No underrun occurred
	SPI_SR_UDR_NoUnderrun = 0x0
	// Underrun occurred
	SPI_SR_UDR_Underrun = 0x1
	// Position of TXTF field.
	SPI_SR_TXTF_Pos = 0x4
	// Bit mask of TXTF field.
	SPI_SR_TXTF_Msk = 0x10
	// Bit TXTF.
	SPI_SR_TXTF = 0x10
	// Transmission buffer incomplete
	SPI_SR_TXTF_NotCompleted = 0x0
	// Transmission buffer filled with at least one transfer
	SPI_SR_TXTF_Completed = 0x1
	// Position of EOT field.
	SPI_SR_EOT_Pos = 0x3
	// Bit mask of EOT field.
	SPI_SR_EOT_Msk = 0x8
	// Bit EOT.
	SPI_SR_EOT = 0x8
	// Transfer ongoing or not started
	SPI_SR_EOT_NotCompleted = 0x0
	// Transfer complete
	SPI_SR_EOT_Completed = 0x1
	// Position of DXP field.
	SPI_SR_DXP_Pos = 0x2
	// Bit mask of DXP field.
	SPI_SR_DXP_Msk = 0x4
	// Bit DXP.
	SPI_SR_DXP = 0x4
	// Duplex packet unavailable: no space for transmission and/or no data received
	SPI_SR_DXP_Unavailable = 0x0
	// Duplex packet available: space for transmission and data received
	SPI_SR_DXP_Available = 0x1
	// Position of TXP field.
	SPI_SR_TXP_Pos = 0x1
	// Bit mask of TXP field.
	SPI_SR_TXP_Msk = 0x2
	// Bit TXP.
	SPI_SR_TXP = 0x2
	// Tx buffer full
	SPI_SR_TXP_Full = 0x0
	// Tx buffer not full
	SPI_SR_TXP_NotFull = 0x1
	// Position of RXP field.
	SPI_SR_RXP_Pos = 0x0
	// Bit mask of RXP field.
	SPI_SR_RXP_Msk = 0x1
	// Bit RXP.
	SPI_SR_RXP = 0x1
	// Rx buffer empty
	SPI_SR_RXP_Empty = 0x0
	// Rx buffer not empty
	SPI_SR_RXP_NotEmpty = 0x1

	// IFCR: Interrupt/Status Flags Clear Register
	// Position of SUSPC field.
	SPI_IFCR_SUSPC_Pos = 0xb
	// Bit mask of SUSPC field.
	SPI_IFCR_SUSPC_Msk = 0x800
	// Bit SUSPC.
	SPI_IFCR_SUSPC = 0x800
	// Clear interrupt flag
	SPI_IFCR_SUSPC_Clear = 0x1
	// Position of TSERFC field.
	SPI_IFCR_TSERFC_Pos = 0xa
	// Bit mask of TSERFC field.
	SPI_IFCR_TSERFC_Msk = 0x400
	// Bit TSERFC.
	SPI_IFCR_TSERFC = 0x400
	// Clear interrupt flag
	SPI_IFCR_TSERFC_Clear = 0x1
	// Position of MODFC field.
	SPI_IFCR_MODFC_Pos = 0x9
	// Bit mask of MODFC field.
	SPI_IFCR_MODFC_Msk = 0x200
	// Bit MODFC.
	SPI_IFCR_MODFC = 0x200
	// Clear interrupt flag
	SPI_IFCR_MODFC_Clear = 0x1
	// Position of TIFREC field.
	SPI_IFCR_TIFREC_Pos = 0x8
	// Bit mask of TIFREC field.
	SPI_IFCR_TIFREC_Msk = 0x100
	// Bit TIFREC.
	SPI_IFCR_TIFREC = 0x100
	// Clear interrupt flag
	SPI_IFCR_TIFREC_Clear = 0x1
	// Position of CRCEC field.
	SPI_IFCR_CRCEC_Pos = 0x7
	// Bit mask of CRCEC field.
	SPI_IFCR_CRCEC_Msk = 0x80
	// Bit CRCEC.
	SPI_IFCR_CRCEC = 0x80
	// Clear interrupt flag
	SPI_IFCR_CRCEC_Clear = 0x1
	// Position of OVRC field.
	SPI_IFCR_OVRC_Pos = 0x6
	// Bit mask of OVRC field.
	SPI_IFCR_OVRC_Msk = 0x40
	// Bit OVRC.
	SPI_IFCR_OVRC = 0x40
	// Clear interrupt flag
	SPI_IFCR_OVRC_Clear = 0x1
	// Position of UDRC field.
	SPI_IFCR_UDRC_Pos = 0x5
	// Bit mask of UDRC field.
	SPI_IFCR_UDRC_Msk = 0x20
	// Bit UDRC.
	SPI_IFCR_UDRC = 0x20
	// Clear interrupt flag
	SPI_IFCR_UDRC_Clear = 0x1
	// Position of TXTFC field.
	SPI_IFCR_TXTFC_Pos = 0x4
	// Bit mask of TXTFC field.
	SPI_IFCR_TXTFC_Msk = 0x10
	// Bit TXTFC.
	SPI_IFCR_TXTFC = 0x10
	// Clear interrupt flag
	SPI_IFCR_TXTFC_Clear = 0x1
	// Position of EOTC field.
	SPI_IFCR_EOTC_Pos = 0x3
	// Bit mask of EOTC field.
	SPI_IFCR_EOTC_Msk = 0x8
	// Bit EOTC.
	SPI_IFCR_EOTC = 0x8
	// Clear interrupt flag
	SPI_IFCR_EOTC_Clear = 0x1

	// TXDR: Transmit Data Register
	// Position of TXDR field.
	SPI_TXDR_TXDR_Pos = 0x0
	// Bit mask of TXDR field.
	SPI_TXDR_TXDR_Msk = 0xffffffff

	// RXDR: Receive Data Register
	// Position of RXDR field.
	SPI_RXDR_RXDR_Pos = 0x0
	// Bit mask of RXDR field.
	SPI_RXDR_RXDR_Msk = 0xffffffff

	// CRCPOLY: Polynomial Register
	// Position of CRCPOLY field.
	SPI_CRCPOLY_CRCPOLY_Pos = 0x0
	// Bit mask of CRCPOLY field.
	SPI_CRCPOLY_CRCPOLY_Msk = 0xffffffff

	// TXCRC: Transmitter CRC Register
	// Position of TXCRC field.
	SPI_TXCRC_TXCRC_Pos = 0x0
	// Bit mask of TXCRC field.
	SPI_TXCRC_TXCRC_Msk = 0xffffffff

	// RXCRC: Receiver CRC Register
	// Position of RXCRC field.
	SPI_RXCRC_RXCRC_Pos = 0x0
	// Bit mask of RXCRC field.
	SPI_RXCRC_RXCRC_Msk = 0xffffffff

	// UDRDR: Underrun Data Register
	// Position of UDRDR field.
	SPI_UDRDR_UDRDR_Pos = 0x0
	// Bit mask of UDRDR field.
	SPI_UDRDR_UDRDR_Msk = 0xffffffff

	// I2SCFGR: configuration register
	// Position of MCKOE field.
	SPI_I2SCFGR_MCKOE_Pos = 0x19
	// Bit mask of MCKOE field.
	SPI_I2SCFGR_MCKOE_Msk = 0x2000000
	// Bit MCKOE.
	SPI_I2SCFGR_MCKOE = 0x2000000
	// Master clock output disabled
	SPI_I2SCFGR_MCKOE_Disabled = 0x0
	// Master clock output enabled
	SPI_I2SCFGR_MCKOE_Enabled = 0x1
	// Position of ODD field.
	SPI_I2SCFGR_ODD_Pos = 0x18
	// Bit mask of ODD field.
	SPI_I2SCFGR_ODD_Msk = 0x1000000
	// Bit ODD.
	SPI_I2SCFGR_ODD = 0x1000000
	// Real divider value is I2SDIV*2
	SPI_I2SCFGR_ODD_Even = 0x0
	// Real divider value is I2SDIV*2 + 1
	SPI_I2SCFGR_ODD_Odd = 0x1
	// Position of I2SDIV field.
	SPI_I2SCFGR_I2SDIV_Pos = 0x10
	// Bit mask of I2SDIV field.
	SPI_I2SCFGR_I2SDIV_Msk = 0xff0000
	// Position of DATFMT field.
	SPI_I2SCFGR_DATFMT_Pos = 0xe
	// Bit mask of DATFMT field.
	SPI_I2SCFGR_DATFMT_Msk = 0x4000
	// Bit DATFMT.
	SPI_I2SCFGR_DATFMT = 0x4000
	// The data inside RXDR and TXDR are right aligned
	SPI_I2SCFGR_DATFMT_RightAligned = 0x0
	// The data inside RXDR and TXDR are left aligned
	SPI_I2SCFGR_DATFMT_LeftAligned = 0x1
	// Position of WSINV field.
	SPI_I2SCFGR_WSINV_Pos = 0xd
	// Bit mask of WSINV field.
	SPI_I2SCFGR_WSINV_Msk = 0x2000
	// Bit WSINV.
	SPI_I2SCFGR_WSINV = 0x2000
	// Word select inversion disabled
	SPI_I2SCFGR_WSINV_Disabled = 0x0
	// Word select inversion enabled
	SPI_I2SCFGR_WSINV_Enabled = 0x1
	// Position of FIXCH field.
	SPI_I2SCFGR_FIXCH_Pos = 0xc
	// Bit mask of FIXCH field.
	SPI_I2SCFGR_FIXCH_Msk = 0x1000
	// Bit FIXCH.
	SPI_I2SCFGR_FIXCH = 0x1000
	// The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
	SPI_I2SCFGR_FIXCH_NotFixed = 0x0
	// The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)
	SPI_I2SCFGR_FIXCH_Fixed = 0x1
	// Position of CKPOL field.
	SPI_I2SCFGR_CKPOL_Pos = 0xb
	// Bit mask of CKPOL field.
	SPI_I2SCFGR_CKPOL_Msk = 0x800
	// Bit CKPOL.
	SPI_I2SCFGR_CKPOL = 0x800
	// Signals are sampled on rising and changed on falling clock edges
	SPI_I2SCFGR_CKPOL_SampleOnRising = 0x0
	// Signals are sampled on falling and changed on rising clock edges
	SPI_I2SCFGR_CKPOL_SampleOnFalling = 0x1
	// Position of CHLEN field.
	SPI_I2SCFGR_CHLEN_Pos = 0xa
	// Bit mask of CHLEN field.
	SPI_I2SCFGR_CHLEN_Msk = 0x400
	// Bit CHLEN.
	SPI_I2SCFGR_CHLEN = 0x400
	// 16 bit per channel
	SPI_I2SCFGR_CHLEN_Bits16 = 0x0
	// 32 bit per channel
	SPI_I2SCFGR_CHLEN_Bits32 = 0x1
	// Position of DATLEN field.
	SPI_I2SCFGR_DATLEN_Pos = 0x8
	// Bit mask of DATLEN field.
	SPI_I2SCFGR_DATLEN_Msk = 0x300
	// 16 bit data length
	SPI_I2SCFGR_DATLEN_Bits16 = 0x0
	// 24 bit data length
	SPI_I2SCFGR_DATLEN_Bits24 = 0x1
	// 32 bit data length
	SPI_I2SCFGR_DATLEN_Bits32 = 0x2
	// Position of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC_Pos = 0x7
	// Bit mask of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC_Msk = 0x80
	// Bit PCMSYNC.
	SPI_I2SCFGR_PCMSYNC = 0x80
	// Short PCM frame synchronization
	SPI_I2SCFGR_PCMSYNC_Short = 0x0
	// Long PCM frame synchronization
	SPI_I2SCFGR_PCMSYNC_Long = 0x1
	// Position of I2SSTD field.
	SPI_I2SCFGR_I2SSTD_Pos = 0x4
	// Bit mask of I2SSTD field.
	SPI_I2SCFGR_I2SSTD_Msk = 0x30
	// I2S Philips standard
	SPI_I2SCFGR_I2SSTD_Philips = 0x0
	// MSB/left justified standard
	SPI_I2SCFGR_I2SSTD_LeftAligned = 0x1
	// LSB/right justified standard
	SPI_I2SCFGR_I2SSTD_RightAligned = 0x2
	// PCM standard
	SPI_I2SCFGR_I2SSTD_PCM = 0x3
	// Position of I2SCFG field.
	SPI_I2SCFGR_I2SCFG_Pos = 0x1
	// Bit mask of I2SCFG field.
	SPI_I2SCFGR_I2SCFG_Msk = 0xe
	// Slave, transmit
	SPI_I2SCFGR_I2SCFG_SlaveTransmit = 0x0
	// Slave, recteive
	SPI_I2SCFGR_I2SCFG_SlaveReceive = 0x1
	// Master, transmit
	SPI_I2SCFGR_I2SCFG_MasterTransmit = 0x2
	// Master, receive
	SPI_I2SCFGR_I2SCFG_MasterReceive = 0x3
	// Slave, full duplex
	SPI_I2SCFGR_I2SCFG_SlaveFullDuplex = 0x4
	// Master, full duplex
	SPI_I2SCFGR_I2SCFG_MasterFullDuplex = 0x5
	// Position of I2SMOD field.
	SPI_I2SCFGR_I2SMOD_Pos = 0x0
	// Bit mask of I2SMOD field.
	SPI_I2SCFGR_I2SMOD_Msk = 0x1
	// Bit I2SMOD.
	SPI_I2SCFGR_I2SMOD = 0x1
	// SPI mode selected
	SPI_I2SCFGR_I2SMOD_SPI = 0x0
	// I2S/PCM mode selected
	SPI_I2SCFGR_I2SMOD_I2S = 0x1
)

// Bitfields for LTDC: LCD-TFT Controller
const (
	// SSCR: Synchronization Size Configuration Register
	// Position of HSW field.
	LTDC_SSCR_HSW_Pos = 0x10
	// Bit mask of HSW field.
	LTDC_SSCR_HSW_Msk = 0xfff0000
	// Position of VSH field.
	LTDC_SSCR_VSH_Pos = 0x0
	// Bit mask of VSH field.
	LTDC_SSCR_VSH_Msk = 0x7ff

	// BPCR: Back Porch Configuration Register
	// Position of AHBP field.
	LTDC_BPCR_AHBP_Pos = 0x10
	// Bit mask of AHBP field.
	LTDC_BPCR_AHBP_Msk = 0xfff0000
	// Position of AVBP field.
	LTDC_BPCR_AVBP_Pos = 0x0
	// Bit mask of AVBP field.
	LTDC_BPCR_AVBP_Msk = 0x7ff

	// AWCR: Active Width Configuration Register
	// Position of AAW field.
	LTDC_AWCR_AAW_Pos = 0x10
	// Bit mask of AAW field.
	LTDC_AWCR_AAW_Msk = 0xfff0000
	// Position of AAH field.
	LTDC_AWCR_AAH_Pos = 0x0
	// Bit mask of AAH field.
	LTDC_AWCR_AAH_Msk = 0x7ff

	// TWCR: Total Width Configuration Register
	// Position of TOTALW field.
	LTDC_TWCR_TOTALW_Pos = 0x10
	// Bit mask of TOTALW field.
	LTDC_TWCR_TOTALW_Msk = 0xfff0000
	// Position of TOTALH field.
	LTDC_TWCR_TOTALH_Pos = 0x0
	// Bit mask of TOTALH field.
	LTDC_TWCR_TOTALH_Msk = 0x7ff

	// GCR: Global Control Register
	// Position of HSPOL field.
	LTDC_GCR_HSPOL_Pos = 0x1f
	// Bit mask of HSPOL field.
	LTDC_GCR_HSPOL_Msk = 0x80000000
	// Bit HSPOL.
	LTDC_GCR_HSPOL = 0x80000000
	// Horizontal synchronization polarity is active low
	LTDC_GCR_HSPOL_ActiveLow = 0x0
	// Horizontal synchronization polarity is active high
	LTDC_GCR_HSPOL_ActiveHigh = 0x1
	// Position of VSPOL field.
	LTDC_GCR_VSPOL_Pos = 0x1e
	// Bit mask of VSPOL field.
	LTDC_GCR_VSPOL_Msk = 0x40000000
	// Bit VSPOL.
	LTDC_GCR_VSPOL = 0x40000000
	// Vertical synchronization polarity is active low
	LTDC_GCR_VSPOL_ActiveLow = 0x0
	// Vertical synchronization polarity is active high
	LTDC_GCR_VSPOL_ActiveHigh = 0x1
	// Position of DEPOL field.
	LTDC_GCR_DEPOL_Pos = 0x1d
	// Bit mask of DEPOL field.
	LTDC_GCR_DEPOL_Msk = 0x20000000
	// Bit DEPOL.
	LTDC_GCR_DEPOL = 0x20000000
	// Data enable polarity is active low
	LTDC_GCR_DEPOL_ActiveLow = 0x0
	// Data enable polarity is active high
	LTDC_GCR_DEPOL_ActiveHigh = 0x1
	// Position of PCPOL field.
	LTDC_GCR_PCPOL_Pos = 0x1c
	// Bit mask of PCPOL field.
	LTDC_GCR_PCPOL_Msk = 0x10000000
	// Bit PCPOL.
	LTDC_GCR_PCPOL = 0x10000000
	// Pixel clock on rising edge
	LTDC_GCR_PCPOL_RisingEdge = 0x0
	// Pixel clock on falling edge
	LTDC_GCR_PCPOL_FallingEdge = 0x1
	// Position of DEN field.
	LTDC_GCR_DEN_Pos = 0x10
	// Bit mask of DEN field.
	LTDC_GCR_DEN_Msk = 0x10000
	// Bit DEN.
	LTDC_GCR_DEN = 0x10000
	// Dither disabled
	LTDC_GCR_DEN_Disabled = 0x0
	// Dither enabled
	LTDC_GCR_DEN_Enabled = 0x1
	// Position of DRW field.
	LTDC_GCR_DRW_Pos = 0xc
	// Bit mask of DRW field.
	LTDC_GCR_DRW_Msk = 0x7000
	// Position of DGW field.
	LTDC_GCR_DGW_Pos = 0x8
	// Bit mask of DGW field.
	LTDC_GCR_DGW_Msk = 0x700
	// Position of DBW field.
	LTDC_GCR_DBW_Pos = 0x4
	// Bit mask of DBW field.
	LTDC_GCR_DBW_Msk = 0x70
	// Position of LTDCEN field.
	LTDC_GCR_LTDCEN_Pos = 0x0
	// Bit mask of LTDCEN field.
	LTDC_GCR_LTDCEN_Msk = 0x1
	// Bit LTDCEN.
	LTDC_GCR_LTDCEN = 0x1
	// LCD-TFT controller disabled
	LTDC_GCR_LTDCEN_Disabled = 0x0
	// LCD-TFT controller enabled
	LTDC_GCR_LTDCEN_Enabled = 0x1

	// SRCR: Shadow Reload Configuration Register
	// Position of VBR field.
	LTDC_SRCR_VBR_Pos = 0x1
	// Bit mask of VBR field.
	LTDC_SRCR_VBR_Msk = 0x2
	// Bit VBR.
	LTDC_SRCR_VBR = 0x2
	// The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).
	LTDC_SRCR_VBR_Reload = 0x1
	// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
	LTDC_SRCR_VBR_NoEffect = 0x0
	// Position of IMR field.
	LTDC_SRCR_IMR_Pos = 0x0
	// Bit mask of IMR field.
	LTDC_SRCR_IMR_Msk = 0x1
	// Bit IMR.
	LTDC_SRCR_IMR = 0x1
	// The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload
	LTDC_SRCR_IMR_Reload = 0x1
	// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
	LTDC_SRCR_IMR_NoEffect = 0x0

	// BCCR: Background Color Configuration Register
	// Position of BCBLUE field.
	LTDC_BCCR_BCBLUE_Pos = 0x0
	// Bit mask of BCBLUE field.
	LTDC_BCCR_BCBLUE_Msk = 0xff
	// Position of BCGREEN field.
	LTDC_BCCR_BCGREEN_Pos = 0x8
	// Bit mask of BCGREEN field.
	LTDC_BCCR_BCGREEN_Msk = 0xff00
	// Position of BCRED field.
	LTDC_BCCR_BCRED_Pos = 0x10
	// Bit mask of BCRED field.
	LTDC_BCCR_BCRED_Msk = 0xff0000

	// IER: Interrupt Enable Register
	// Position of RRIE field.
	LTDC_IER_RRIE_Pos = 0x3
	// Bit mask of RRIE field.
	LTDC_IER_RRIE_Msk = 0x8
	// Bit RRIE.
	LTDC_IER_RRIE = 0x8
	// Register reload interrupt disabled
	LTDC_IER_RRIE_Disabled = 0x0
	// Register reload interrupt enabled
	LTDC_IER_RRIE_Enabled = 0x1
	// Position of TERRIE field.
	LTDC_IER_TERRIE_Pos = 0x2
	// Bit mask of TERRIE field.
	LTDC_IER_TERRIE_Msk = 0x4
	// Bit TERRIE.
	LTDC_IER_TERRIE = 0x4
	// Transfer error interrupt disabled
	LTDC_IER_TERRIE_Disabled = 0x0
	// Transfer error interrupt enabled
	LTDC_IER_TERRIE_Enabled = 0x1
	// Position of FUIE field.
	LTDC_IER_FUIE_Pos = 0x1
	// Bit mask of FUIE field.
	LTDC_IER_FUIE_Msk = 0x2
	// Bit FUIE.
	LTDC_IER_FUIE = 0x2
	// FIFO underrun interrupt disabled
	LTDC_IER_FUIE_Disabled = 0x0
	// FIFO underrun interrupt enabled
	LTDC_IER_FUIE_Enabled = 0x1
	// Position of LIE field.
	LTDC_IER_LIE_Pos = 0x0
	// Bit mask of LIE field.
	LTDC_IER_LIE_Msk = 0x1
	// Bit LIE.
	LTDC_IER_LIE = 0x1
	// Line interrupt disabled
	LTDC_IER_LIE_Disabled = 0x0
	// Line interrupt enabled
	LTDC_IER_LIE_Enabled = 0x1

	// ISR: Interrupt Status Register
	// Position of RRIF field.
	LTDC_ISR_RRIF_Pos = 0x3
	// Bit mask of RRIF field.
	LTDC_ISR_RRIF_Msk = 0x8
	// Bit RRIF.
	LTDC_ISR_RRIF = 0x8
	// No register reload
	LTDC_ISR_RRIF_NoReload = 0x0
	// Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)
	LTDC_ISR_RRIF_Reload = 0x1
	// Position of TERRIF field.
	LTDC_ISR_TERRIF_Pos = 0x2
	// Bit mask of TERRIF field.
	LTDC_ISR_TERRIF_Msk = 0x4
	// Bit TERRIF.
	LTDC_ISR_TERRIF = 0x4
	// No transfer error
	LTDC_ISR_TERRIF_NoError = 0x0
	// Transfer error interrupt generated when a bus error occurs
	LTDC_ISR_TERRIF_Error = 0x1
	// Position of FUIF field.
	LTDC_ISR_FUIF_Pos = 0x1
	// Bit mask of FUIF field.
	LTDC_ISR_FUIF_Msk = 0x2
	// Bit FUIF.
	LTDC_ISR_FUIF = 0x2
	// No FIFO underrun
	LTDC_ISR_FUIF_NoUnderrun = 0x0
	// FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO
	LTDC_ISR_FUIF_Underrun = 0x1
	// Position of LIF field.
	LTDC_ISR_LIF_Pos = 0x0
	// Bit mask of LIF field.
	LTDC_ISR_LIF_Msk = 0x1
	// Bit LIF.
	LTDC_ISR_LIF = 0x1
	// Programmed line not reached
	LTDC_ISR_LIF_NotReached = 0x0
	// Line interrupt generated when a programmed line is reached
	LTDC_ISR_LIF_Reached = 0x1

	// ICR: Interrupt Clear Register
	// Position of CRRIF field.
	LTDC_ICR_CRRIF_Pos = 0x3
	// Bit mask of CRRIF field.
	LTDC_ICR_CRRIF_Msk = 0x8
	// Bit CRRIF.
	LTDC_ICR_CRRIF = 0x8
	// Clears the RRIF flag in the ISR register
	LTDC_ICR_CRRIF_Clear = 0x1
	// Position of CTERRIF field.
	LTDC_ICR_CTERRIF_Pos = 0x2
	// Bit mask of CTERRIF field.
	LTDC_ICR_CTERRIF_Msk = 0x4
	// Bit CTERRIF.
	LTDC_ICR_CTERRIF = 0x4
	// Clears the TERRIF flag in the ISR register
	LTDC_ICR_CTERRIF_Clear = 0x1
	// Position of CFUIF field.
	LTDC_ICR_CFUIF_Pos = 0x1
	// Bit mask of CFUIF field.
	LTDC_ICR_CFUIF_Msk = 0x2
	// Bit CFUIF.
	LTDC_ICR_CFUIF = 0x2
	// Clears the FUIF flag in the ISR register
	LTDC_ICR_CFUIF_Clear = 0x1
	// Position of CLIF field.
	LTDC_ICR_CLIF_Pos = 0x0
	// Bit mask of CLIF field.
	LTDC_ICR_CLIF_Msk = 0x1
	// Bit CLIF.
	LTDC_ICR_CLIF = 0x1
	// Clears the LIF flag in the ISR register
	LTDC_ICR_CLIF_Clear = 0x1

	// LIPCR: Line Interrupt Position Configuration Register
	// Position of LIPOS field.
	LTDC_LIPCR_LIPOS_Pos = 0x0
	// Bit mask of LIPOS field.
	LTDC_LIPCR_LIPOS_Msk = 0x7ff

	// CPSR: Current Position Status Register
	// Position of CXPOS field.
	LTDC_CPSR_CXPOS_Pos = 0x10
	// Bit mask of CXPOS field.
	LTDC_CPSR_CXPOS_Msk = 0xffff0000
	// Position of CYPOS field.
	LTDC_CPSR_CYPOS_Pos = 0x0
	// Bit mask of CYPOS field.
	LTDC_CPSR_CYPOS_Msk = 0xffff

	// CDSR: Current Display Status Register
	// Position of HSYNCS field.
	LTDC_CDSR_HSYNCS_Pos = 0x3
	// Bit mask of HSYNCS field.
	LTDC_CDSR_HSYNCS_Msk = 0x8
	// Bit HSYNCS.
	LTDC_CDSR_HSYNCS = 0x8
	// Currently not in HSYNC phase
	LTDC_CDSR_HSYNCS_NotActive = 0x0
	// Currently in HSYNC phase
	LTDC_CDSR_HSYNCS_Active = 0x1
	// Position of VSYNCS field.
	LTDC_CDSR_VSYNCS_Pos = 0x2
	// Bit mask of VSYNCS field.
	LTDC_CDSR_VSYNCS_Msk = 0x4
	// Bit VSYNCS.
	LTDC_CDSR_VSYNCS = 0x4
	// Currently not in VSYNC phase
	LTDC_CDSR_VSYNCS_NotActive = 0x0
	// Currently in VSYNC phase
	LTDC_CDSR_VSYNCS_Active = 0x1
	// Position of HDES field.
	LTDC_CDSR_HDES_Pos = 0x1
	// Bit mask of HDES field.
	LTDC_CDSR_HDES_Msk = 0x2
	// Bit HDES.
	LTDC_CDSR_HDES = 0x2
	// Currently not in horizontal Data Enable phase
	LTDC_CDSR_HDES_NotActive = 0x0
	// Currently in horizontal Data Enable phase
	LTDC_CDSR_HDES_Active = 0x1
	// Position of VDES field.
	LTDC_CDSR_VDES_Pos = 0x0
	// Bit mask of VDES field.
	LTDC_CDSR_VDES_Msk = 0x1
	// Bit VDES.
	LTDC_CDSR_VDES = 0x1
	// Currently not in vertical Data Enable phase
	LTDC_CDSR_VDES_NotActive = 0x0
	// Currently in vertical Data Enable phase
	LTDC_CDSR_VDES_Active = 0x1

	// LAYER.CR: Layerx Control Register
	// Position of CLUTEN field.
	LTDC_LAYER_CR_CLUTEN_Pos = 0x4
	// Bit mask of CLUTEN field.
	LTDC_LAYER_CR_CLUTEN_Msk = 0x10
	// Bit CLUTEN.
	LTDC_LAYER_CR_CLUTEN = 0x10
	// Color look-up table disabled
	LTDC_LAYER_CR_CLUTEN_Disabled = 0x0
	// Color look-up table enabled
	LTDC_LAYER_CR_CLUTEN_Enabled = 0x1
	// Position of COLKEN field.
	LTDC_LAYER_CR_COLKEN_Pos = 0x1
	// Bit mask of COLKEN field.
	LTDC_LAYER_CR_COLKEN_Msk = 0x2
	// Bit COLKEN.
	LTDC_LAYER_CR_COLKEN = 0x2
	// Color keying disabled
	LTDC_LAYER_CR_COLKEN_Disabled = 0x0
	// Color keying enabled
	LTDC_LAYER_CR_COLKEN_Enabled = 0x1
	// Position of LEN field.
	LTDC_LAYER_CR_LEN_Pos = 0x0
	// Bit mask of LEN field.
	LTDC_LAYER_CR_LEN_Msk = 0x1
	// Bit LEN.
	LTDC_LAYER_CR_LEN = 0x1
	// Layer disabled
	LTDC_LAYER_CR_LEN_Disabled = 0x0
	// Layer enabled
	LTDC_LAYER_CR_LEN_Enabled = 0x1

	// LAYER.WHPCR: Layerx Window Horizontal Position Configuration Register
	// Position of WHSPPOS field.
	LTDC_LAYER_WHPCR_WHSPPOS_Pos = 0x10
	// Bit mask of WHSPPOS field.
	LTDC_LAYER_WHPCR_WHSPPOS_Msk = 0xfff0000
	// Position of WHSTPOS field.
	LTDC_LAYER_WHPCR_WHSTPOS_Pos = 0x0
	// Bit mask of WHSTPOS field.
	LTDC_LAYER_WHPCR_WHSTPOS_Msk = 0xfff

	// LAYER.WVPCR: Layerx Window Vertical Position Configuration Register
	// Position of WVSPPOS field.
	LTDC_LAYER_WVPCR_WVSPPOS_Pos = 0x10
	// Bit mask of WVSPPOS field.
	LTDC_LAYER_WVPCR_WVSPPOS_Msk = 0x7ff0000
	// Position of WVSTPOS field.
	LTDC_LAYER_WVPCR_WVSTPOS_Pos = 0x0
	// Bit mask of WVSTPOS field.
	LTDC_LAYER_WVPCR_WVSTPOS_Msk = 0x7ff

	// LAYER.CKCR: Layerx Color Keying Configuration Register
	// Position of CKRED field.
	LTDC_LAYER_CKCR_CKRED_Pos = 0x10
	// Bit mask of CKRED field.
	LTDC_LAYER_CKCR_CKRED_Msk = 0xff0000
	// Position of CKGREEN field.
	LTDC_LAYER_CKCR_CKGREEN_Pos = 0x8
	// Bit mask of CKGREEN field.
	LTDC_LAYER_CKCR_CKGREEN_Msk = 0xff00
	// Position of CKBLUE field.
	LTDC_LAYER_CKCR_CKBLUE_Pos = 0x0
	// Bit mask of CKBLUE field.
	LTDC_LAYER_CKCR_CKBLUE_Msk = 0xff

	// LAYER.PFCR: Layerx Pixel Format Configuration Register
	// Position of PF field.
	LTDC_LAYER_PFCR_PF_Pos = 0x0
	// Bit mask of PF field.
	LTDC_LAYER_PFCR_PF_Msk = 0x7
	// ARGB8888
	LTDC_LAYER_PFCR_PF_ARGB8888 = 0x0
	// RGB888
	LTDC_LAYER_PFCR_PF_RGB888 = 0x1
	// RGB565
	LTDC_LAYER_PFCR_PF_RGB565 = 0x2
	// ARGB1555
	LTDC_LAYER_PFCR_PF_ARGB1555 = 0x3
	// ARGB4444
	LTDC_LAYER_PFCR_PF_ARGB4444 = 0x4
	// L8 (8-bit luminance)
	LTDC_LAYER_PFCR_PF_L8 = 0x5
	// AL44 (4-bit alpha, 4-bit luminance)
	LTDC_LAYER_PFCR_PF_AL44 = 0x6
	// AL88 (8-bit alpha, 8-bit luminance)
	LTDC_LAYER_PFCR_PF_AL88 = 0x7

	// LAYER.CACR: Layerx Constant Alpha Configuration Register
	// Position of CONSTA field.
	LTDC_LAYER_CACR_CONSTA_Pos = 0x0
	// Bit mask of CONSTA field.
	LTDC_LAYER_CACR_CONSTA_Msk = 0xff

	// LAYER.DCCR: Layerx Default Color Configuration Register
	// Position of DCALPHA field.
	LTDC_LAYER_DCCR_DCALPHA_Pos = 0x18
	// Bit mask of DCALPHA field.
	LTDC_LAYER_DCCR_DCALPHA_Msk = 0xff000000
	// Position of DCRED field.
	LTDC_LAYER_DCCR_DCRED_Pos = 0x10
	// Bit mask of DCRED field.
	LTDC_LAYER_DCCR_DCRED_Msk = 0xff0000
	// Position of DCGREEN field.
	LTDC_LAYER_DCCR_DCGREEN_Pos = 0x8
	// Bit mask of DCGREEN field.
	LTDC_LAYER_DCCR_DCGREEN_Msk = 0xff00
	// Position of DCBLUE field.
	LTDC_LAYER_DCCR_DCBLUE_Pos = 0x0
	// Bit mask of DCBLUE field.
	LTDC_LAYER_DCCR_DCBLUE_Msk = 0xff

	// LAYER.BFCR: Layerx Blending Factors Configuration Register
	// Position of BF1 field.
	LTDC_LAYER_BFCR_BF1_Pos = 0x8
	// Bit mask of BF1 field.
	LTDC_LAYER_BFCR_BF1_Msk = 0x700
	// BF1 = constant alpha
	LTDC_LAYER_BFCR_BF1_Constant = 0x4
	// BF1 = pixel alpha * constant alpha
	LTDC_LAYER_BFCR_BF1_Pixel = 0x6
	// Position of BF2 field.
	LTDC_LAYER_BFCR_BF2_Pos = 0x0
	// Bit mask of BF2 field.
	LTDC_LAYER_BFCR_BF2_Msk = 0x7
	// BF2 = 1 - constant alpha
	LTDC_LAYER_BFCR_BF2_Constant = 0x5
	// BF2 = 1 - pixel alpha * constant alpha
	LTDC_LAYER_BFCR_BF2_Pixel = 0x7

	// LAYER.CFBAR: Layerx Color Frame Buffer Address Register
	// Position of CFBADD field.
	LTDC_LAYER_CFBAR_CFBADD_Pos = 0x0
	// Bit mask of CFBADD field.
	LTDC_LAYER_CFBAR_CFBADD_Msk = 0xffffffff

	// LAYER.CFBLR: Layerx Color Frame Buffer Length Register
	// Position of CFBP field.
	LTDC_LAYER_CFBLR_CFBP_Pos = 0x10
	// Bit mask of CFBP field.
	LTDC_LAYER_CFBLR_CFBP_Msk = 0x1fff0000
	// Position of CFBLL field.
	LTDC_LAYER_CFBLR_CFBLL_Pos = 0x0
	// Bit mask of CFBLL field.
	LTDC_LAYER_CFBLR_CFBLL_Msk = 0x1fff

	// LAYER.CFBLNR: Layerx ColorFrame Buffer Line Number Register
	// Position of CFBLNBR field.
	LTDC_LAYER_CFBLNR_CFBLNBR_Pos = 0x0
	// Bit mask of CFBLNBR field.
	LTDC_LAYER_CFBLNR_CFBLNBR_Msk = 0x7ff

	// LAYER.CLUTWR: Layerx CLUT Write Register
	// Position of CLUTADD field.
	LTDC_LAYER_CLUTWR_CLUTADD_Pos = 0x18
	// Bit mask of CLUTADD field.
	LTDC_LAYER_CLUTWR_CLUTADD_Msk = 0xff000000
	// Position of RED field.
	LTDC_LAYER_CLUTWR_RED_Pos = 0x10
	// Bit mask of RED field.
	LTDC_LAYER_CLUTWR_RED_Msk = 0xff0000
	// Position of GREEN field.
	LTDC_LAYER_CLUTWR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	LTDC_LAYER_CLUTWR_GREEN_Msk = 0xff00
	// Position of BLUE field.
	LTDC_LAYER_CLUTWR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	LTDC_LAYER_CLUTWR_BLUE_Msk = 0xff
)

// Bitfields for SPDIFRX: Receiver Interface
const (
	// CR: Control register
	// Position of SPDIFRXEN field.
	SPDIFRX_CR_SPDIFRXEN_Pos = 0x0
	// Bit mask of SPDIFRXEN field.
	SPDIFRX_CR_SPDIFRXEN_Msk = 0x3
	// Position of RXDMAEN field.
	SPDIFRX_CR_RXDMAEN_Pos = 0x2
	// Bit mask of RXDMAEN field.
	SPDIFRX_CR_RXDMAEN_Msk = 0x4
	// Bit RXDMAEN.
	SPDIFRX_CR_RXDMAEN = 0x4
	// Position of RXSTEO field.
	SPDIFRX_CR_RXSTEO_Pos = 0x3
	// Bit mask of RXSTEO field.
	SPDIFRX_CR_RXSTEO_Msk = 0x8
	// Bit RXSTEO.
	SPDIFRX_CR_RXSTEO = 0x8
	// Position of DRFMT field.
	SPDIFRX_CR_DRFMT_Pos = 0x4
	// Bit mask of DRFMT field.
	SPDIFRX_CR_DRFMT_Msk = 0x30
	// Position of PMSK field.
	SPDIFRX_CR_PMSK_Pos = 0x6
	// Bit mask of PMSK field.
	SPDIFRX_CR_PMSK_Msk = 0x40
	// Bit PMSK.
	SPDIFRX_CR_PMSK = 0x40
	// Position of VMSK field.
	SPDIFRX_CR_VMSK_Pos = 0x7
	// Bit mask of VMSK field.
	SPDIFRX_CR_VMSK_Msk = 0x80
	// Bit VMSK.
	SPDIFRX_CR_VMSK = 0x80
	// Position of CUMSK field.
	SPDIFRX_CR_CUMSK_Pos = 0x8
	// Bit mask of CUMSK field.
	SPDIFRX_CR_CUMSK_Msk = 0x100
	// Bit CUMSK.
	SPDIFRX_CR_CUMSK = 0x100
	// Position of PTMSK field.
	SPDIFRX_CR_PTMSK_Pos = 0x9
	// Bit mask of PTMSK field.
	SPDIFRX_CR_PTMSK_Msk = 0x200
	// Bit PTMSK.
	SPDIFRX_CR_PTMSK = 0x200
	// Position of CBDMAEN field.
	SPDIFRX_CR_CBDMAEN_Pos = 0xa
	// Bit mask of CBDMAEN field.
	SPDIFRX_CR_CBDMAEN_Msk = 0x400
	// Bit CBDMAEN.
	SPDIFRX_CR_CBDMAEN = 0x400
	// Position of CHSEL field.
	SPDIFRX_CR_CHSEL_Pos = 0xb
	// Bit mask of CHSEL field.
	SPDIFRX_CR_CHSEL_Msk = 0x800
	// Bit CHSEL.
	SPDIFRX_CR_CHSEL = 0x800
	// Position of NBTR field.
	SPDIFRX_CR_NBTR_Pos = 0xc
	// Bit mask of NBTR field.
	SPDIFRX_CR_NBTR_Msk = 0x3000
	// Position of WFA field.
	SPDIFRX_CR_WFA_Pos = 0xe
	// Bit mask of WFA field.
	SPDIFRX_CR_WFA_Msk = 0x4000
	// Bit WFA.
	SPDIFRX_CR_WFA = 0x4000
	// Position of INSEL field.
	SPDIFRX_CR_INSEL_Pos = 0x10
	// Bit mask of INSEL field.
	SPDIFRX_CR_INSEL_Msk = 0x70000
	// Position of CKSEN field.
	SPDIFRX_CR_CKSEN_Pos = 0x14
	// Bit mask of CKSEN field.
	SPDIFRX_CR_CKSEN_Msk = 0x100000
	// Bit CKSEN.
	SPDIFRX_CR_CKSEN = 0x100000
	// Position of CKSBKPEN field.
	SPDIFRX_CR_CKSBKPEN_Pos = 0x15
	// Bit mask of CKSBKPEN field.
	SPDIFRX_CR_CKSBKPEN_Msk = 0x200000
	// Bit CKSBKPEN.
	SPDIFRX_CR_CKSBKPEN = 0x200000

	// IMR: Interrupt mask register
	// Position of RXNEIE field.
	SPDIFRX_IMR_RXNEIE_Pos = 0x0
	// Bit mask of RXNEIE field.
	SPDIFRX_IMR_RXNEIE_Msk = 0x1
	// Bit RXNEIE.
	SPDIFRX_IMR_RXNEIE = 0x1
	// Position of CSRNEIE field.
	SPDIFRX_IMR_CSRNEIE_Pos = 0x1
	// Bit mask of CSRNEIE field.
	SPDIFRX_IMR_CSRNEIE_Msk = 0x2
	// Bit CSRNEIE.
	SPDIFRX_IMR_CSRNEIE = 0x2
	// Position of PERRIE field.
	SPDIFRX_IMR_PERRIE_Pos = 0x2
	// Bit mask of PERRIE field.
	SPDIFRX_IMR_PERRIE_Msk = 0x4
	// Bit PERRIE.
	SPDIFRX_IMR_PERRIE = 0x4
	// Position of OVRIE field.
	SPDIFRX_IMR_OVRIE_Pos = 0x3
	// Bit mask of OVRIE field.
	SPDIFRX_IMR_OVRIE_Msk = 0x8
	// Bit OVRIE.
	SPDIFRX_IMR_OVRIE = 0x8
	// Position of SBLKIE field.
	SPDIFRX_IMR_SBLKIE_Pos = 0x4
	// Bit mask of SBLKIE field.
	SPDIFRX_IMR_SBLKIE_Msk = 0x10
	// Bit SBLKIE.
	SPDIFRX_IMR_SBLKIE = 0x10
	// Position of SYNCDIE field.
	SPDIFRX_IMR_SYNCDIE_Pos = 0x5
	// Bit mask of SYNCDIE field.
	SPDIFRX_IMR_SYNCDIE_Msk = 0x20
	// Bit SYNCDIE.
	SPDIFRX_IMR_SYNCDIE = 0x20
	// Position of IFEIE field.
	SPDIFRX_IMR_IFEIE_Pos = 0x6
	// Bit mask of IFEIE field.
	SPDIFRX_IMR_IFEIE_Msk = 0x40
	// Bit IFEIE.
	SPDIFRX_IMR_IFEIE = 0x40

	// SR: Status register
	// Position of RXNE field.
	SPDIFRX_SR_RXNE_Pos = 0x0
	// Bit mask of RXNE field.
	SPDIFRX_SR_RXNE_Msk = 0x1
	// Bit RXNE.
	SPDIFRX_SR_RXNE = 0x1
	// Position of CSRNE field.
	SPDIFRX_SR_CSRNE_Pos = 0x1
	// Bit mask of CSRNE field.
	SPDIFRX_SR_CSRNE_Msk = 0x2
	// Bit CSRNE.
	SPDIFRX_SR_CSRNE = 0x2
	// Position of PERR field.
	SPDIFRX_SR_PERR_Pos = 0x2
	// Bit mask of PERR field.
	SPDIFRX_SR_PERR_Msk = 0x4
	// Bit PERR.
	SPDIFRX_SR_PERR = 0x4
	// Position of OVR field.
	SPDIFRX_SR_OVR_Pos = 0x3
	// Bit mask of OVR field.
	SPDIFRX_SR_OVR_Msk = 0x8
	// Bit OVR.
	SPDIFRX_SR_OVR = 0x8
	// Position of SBD field.
	SPDIFRX_SR_SBD_Pos = 0x4
	// Bit mask of SBD field.
	SPDIFRX_SR_SBD_Msk = 0x10
	// Bit SBD.
	SPDIFRX_SR_SBD = 0x10
	// Position of SYNCD field.
	SPDIFRX_SR_SYNCD_Pos = 0x5
	// Bit mask of SYNCD field.
	SPDIFRX_SR_SYNCD_Msk = 0x20
	// Bit SYNCD.
	SPDIFRX_SR_SYNCD = 0x20
	// Position of FERR field.
	SPDIFRX_SR_FERR_Pos = 0x6
	// Bit mask of FERR field.
	SPDIFRX_SR_FERR_Msk = 0x40
	// Bit FERR.
	SPDIFRX_SR_FERR = 0x40
	// Position of SERR field.
	SPDIFRX_SR_SERR_Pos = 0x7
	// Bit mask of SERR field.
	SPDIFRX_SR_SERR_Msk = 0x80
	// Bit SERR.
	SPDIFRX_SR_SERR = 0x80
	// Position of TERR field.
	SPDIFRX_SR_TERR_Pos = 0x8
	// Bit mask of TERR field.
	SPDIFRX_SR_TERR_Msk = 0x100
	// Bit TERR.
	SPDIFRX_SR_TERR = 0x100
	// Position of WIDTH5 field.
	SPDIFRX_SR_WIDTH5_Pos = 0x10
	// Bit mask of WIDTH5 field.
	SPDIFRX_SR_WIDTH5_Msk = 0x7fff0000

	// IFCR: Interrupt Flag Clear register
	// Position of PERRCF field.
	SPDIFRX_IFCR_PERRCF_Pos = 0x2
	// Bit mask of PERRCF field.
	SPDIFRX_IFCR_PERRCF_Msk = 0x4
	// Bit PERRCF.
	SPDIFRX_IFCR_PERRCF = 0x4
	// Position of OVRCF field.
	SPDIFRX_IFCR_OVRCF_Pos = 0x3
	// Bit mask of OVRCF field.
	SPDIFRX_IFCR_OVRCF_Msk = 0x8
	// Bit OVRCF.
	SPDIFRX_IFCR_OVRCF = 0x8
	// Position of SBDCF field.
	SPDIFRX_IFCR_SBDCF_Pos = 0x4
	// Bit mask of SBDCF field.
	SPDIFRX_IFCR_SBDCF_Msk = 0x10
	// Bit SBDCF.
	SPDIFRX_IFCR_SBDCF = 0x10
	// Position of SYNCDCF field.
	SPDIFRX_IFCR_SYNCDCF_Pos = 0x5
	// Bit mask of SYNCDCF field.
	SPDIFRX_IFCR_SYNCDCF_Msk = 0x20
	// Bit SYNCDCF.
	SPDIFRX_IFCR_SYNCDCF = 0x20

	// DR_00: Data input register
	// Position of DR field.
	SPDIFRX_DR_00_DR_Pos = 0x0
	// Bit mask of DR field.
	SPDIFRX_DR_00_DR_Msk = 0xffffff
	// Position of PE field.
	SPDIFRX_DR_00_PE_Pos = 0x18
	// Bit mask of PE field.
	SPDIFRX_DR_00_PE_Msk = 0x1000000
	// Bit PE.
	SPDIFRX_DR_00_PE = 0x1000000
	// Position of V field.
	SPDIFRX_DR_00_V_Pos = 0x19
	// Bit mask of V field.
	SPDIFRX_DR_00_V_Msk = 0x2000000
	// Bit V.
	SPDIFRX_DR_00_V = 0x2000000
	// Position of U field.
	SPDIFRX_DR_00_U_Pos = 0x1a
	// Bit mask of U field.
	SPDIFRX_DR_00_U_Msk = 0x4000000
	// Bit U.
	SPDIFRX_DR_00_U = 0x4000000
	// Position of C field.
	SPDIFRX_DR_00_C_Pos = 0x1b
	// Bit mask of C field.
	SPDIFRX_DR_00_C_Msk = 0x8000000
	// Bit C.
	SPDIFRX_DR_00_C = 0x8000000
	// Position of PT field.
	SPDIFRX_DR_00_PT_Pos = 0x1c
	// Bit mask of PT field.
	SPDIFRX_DR_00_PT_Msk = 0x30000000

	// DR_01: Data input register
	// Position of PE field.
	SPDIFRX_DR_01_PE_Pos = 0x0
	// Bit mask of PE field.
	SPDIFRX_DR_01_PE_Msk = 0x1
	// Bit PE.
	SPDIFRX_DR_01_PE = 0x1
	// Position of V field.
	SPDIFRX_DR_01_V_Pos = 0x1
	// Bit mask of V field.
	SPDIFRX_DR_01_V_Msk = 0x2
	// Bit V.
	SPDIFRX_DR_01_V = 0x2
	// Position of U field.
	SPDIFRX_DR_01_U_Pos = 0x2
	// Bit mask of U field.
	SPDIFRX_DR_01_U_Msk = 0x4
	// Bit U.
	SPDIFRX_DR_01_U = 0x4
	// Position of C field.
	SPDIFRX_DR_01_C_Pos = 0x3
	// Bit mask of C field.
	SPDIFRX_DR_01_C_Msk = 0x8
	// Bit C.
	SPDIFRX_DR_01_C = 0x8
	// Position of PT field.
	SPDIFRX_DR_01_PT_Pos = 0x4
	// Bit mask of PT field.
	SPDIFRX_DR_01_PT_Msk = 0x30
	// Position of DR field.
	SPDIFRX_DR_01_DR_Pos = 0x8
	// Bit mask of DR field.
	SPDIFRX_DR_01_DR_Msk = 0xffffff00

	// DR_10: Data input register
	// Position of DRNL1 field.
	SPDIFRX_DR_10_DRNL1_Pos = 0x0
	// Bit mask of DRNL1 field.
	SPDIFRX_DR_10_DRNL1_Msk = 0xffff
	// Position of DRNL2 field.
	SPDIFRX_DR_10_DRNL2_Pos = 0x10
	// Bit mask of DRNL2 field.
	SPDIFRX_DR_10_DRNL2_Msk = 0xffff0000

	// CSR: Channel Status register
	// Position of USR field.
	SPDIFRX_CSR_USR_Pos = 0x0
	// Bit mask of USR field.
	SPDIFRX_CSR_USR_Msk = 0xffff
	// Position of CS field.
	SPDIFRX_CSR_CS_Pos = 0x10
	// Bit mask of CS field.
	SPDIFRX_CSR_CS_Msk = 0xff0000
	// Position of SOB field.
	SPDIFRX_CSR_SOB_Pos = 0x18
	// Bit mask of SOB field.
	SPDIFRX_CSR_SOB_Msk = 0x1000000
	// Bit SOB.
	SPDIFRX_CSR_SOB = 0x1000000

	// DIR: Debug Information register
	// Position of THI field.
	SPDIFRX_DIR_THI_Pos = 0x0
	// Bit mask of THI field.
	SPDIFRX_DIR_THI_Msk = 0x1fff
	// Position of TLO field.
	SPDIFRX_DIR_TLO_Pos = 0x10
	// Bit mask of TLO field.
	SPDIFRX_DIR_TLO_Msk = 0x1fff0000

	// VERR: SPDIFRX version register
	// Position of MINREV field.
	SPDIFRX_VERR_MINREV_Pos = 0x0
	// Bit mask of MINREV field.
	SPDIFRX_VERR_MINREV_Msk = 0xf
	// Position of MAJREV field.
	SPDIFRX_VERR_MAJREV_Pos = 0x4
	// Bit mask of MAJREV field.
	SPDIFRX_VERR_MAJREV_Msk = 0xf0

	// IDR: SPDIFRX identification register
	// Position of ID field.
	SPDIFRX_IDR_ID_Pos = 0x0
	// Bit mask of ID field.
	SPDIFRX_IDR_ID_Msk = 0xffffffff

	// SIDR: SPDIFRX size identification register
	// Position of SID field.
	SPDIFRX_SIDR_SID_Pos = 0x0
	// Bit mask of SID field.
	SPDIFRX_SIDR_SID_Msk = 0xffffffff
)

// Bitfields for ADC3: Analog to Digital Converter
const (
	// ISR: ADC interrupt and status register
	// Position of JQOVF field.
	ADC_ISR_JQOVF_Pos = 0xa
	// Bit mask of JQOVF field.
	ADC_ISR_JQOVF_Msk = 0x400
	// Bit JQOVF.
	ADC_ISR_JQOVF = 0x400
	// No injected context queue overflow has occurred
	ADC_ISR_JQOVF_NoOverflow = 0x0
	// Injected context queue overflow has occurred
	ADC_ISR_JQOVF_Overflow = 0x1
	// Clear injected context queue overflow flag
	ADC_ISR_JQOVF_Clear = 0x1
	// Position of AWD3 field.
	ADC_ISR_AWD3_Pos = 0x9
	// Bit mask of AWD3 field.
	ADC_ISR_AWD3_Msk = 0x200
	// Bit AWD3.
	ADC_ISR_AWD3 = 0x200
	// No analog watchdog event occurred
	ADC_ISR_AWD3_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD3_Event = 0x1
	// Clear analog watchdog event occurred flag
	ADC_ISR_AWD3_Clear = 0x1
	// Position of AWD2 field.
	ADC_ISR_AWD2_Pos = 0x8
	// Bit mask of AWD2 field.
	ADC_ISR_AWD2_Msk = 0x100
	// Bit AWD2.
	ADC_ISR_AWD2 = 0x100
	// No analog watchdog event occurred
	ADC_ISR_AWD2_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD2_Event = 0x1
	// Clear analog watchdog event occurred flag
	ADC_ISR_AWD2_Clear = 0x1
	// Position of AWD1 field.
	ADC_ISR_AWD1_Pos = 0x7
	// Bit mask of AWD1 field.
	ADC_ISR_AWD1_Msk = 0x80
	// Bit AWD1.
	ADC_ISR_AWD1 = 0x80
	// No analog watchdog event occurred
	ADC_ISR_AWD1_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD1_Event = 0x1
	// Clear analog watchdog event occurred flag
	ADC_ISR_AWD1_Clear = 0x1
	// Position of JEOS field.
	ADC_ISR_JEOS_Pos = 0x6
	// Bit mask of JEOS field.
	ADC_ISR_JEOS_Msk = 0x40
	// Bit JEOS.
	ADC_ISR_JEOS = 0x40
	// Injected sequence is not complete
	ADC_ISR_JEOS_NotComplete = 0x0
	// Injected sequence complete
	ADC_ISR_JEOS_Complete = 0x1
	// Clear Injected sequence complete flag
	ADC_ISR_JEOS_Clear = 0x1
	// Position of JEOC field.
	ADC_ISR_JEOC_Pos = 0x5
	// Bit mask of JEOC field.
	ADC_ISR_JEOC_Msk = 0x20
	// Bit JEOC.
	ADC_ISR_JEOC = 0x20
	// Injected conversion is not complete
	ADC_ISR_JEOC_NotComplete = 0x0
	// Injected conversion complete
	ADC_ISR_JEOC_Complete = 0x1
	// Clear injected conversion complete flag
	ADC_ISR_JEOC_Clear = 0x1
	// Position of OVR field.
	ADC_ISR_OVR_Pos = 0x4
	// Bit mask of OVR field.
	ADC_ISR_OVR_Msk = 0x10
	// Bit OVR.
	ADC_ISR_OVR = 0x10
	// No overrun occurred
	ADC_ISR_OVR_NoOverrun = 0x0
	// Overrun occurred
	ADC_ISR_OVR_Overrun = 0x1
	// Clear overrun occurred flag
	ADC_ISR_OVR_Clear = 0x1
	// Position of EOS field.
	ADC_ISR_EOS_Pos = 0x3
	// Bit mask of EOS field.
	ADC_ISR_EOS_Msk = 0x8
	// Bit EOS.
	ADC_ISR_EOS = 0x8
	// Regular sequence is not complete
	ADC_ISR_EOS_NotComplete = 0x0
	// Regular sequence complete
	ADC_ISR_EOS_Complete = 0x1
	// Clear regular sequence complete flag
	ADC_ISR_EOS_Clear = 0x1
	// Position of EOC field.
	ADC_ISR_EOC_Pos = 0x2
	// Bit mask of EOC field.
	ADC_ISR_EOC_Msk = 0x4
	// Bit EOC.
	ADC_ISR_EOC = 0x4
	// Regular conversion is not complete
	ADC_ISR_EOC_NotComplete = 0x0
	// Regular conversion complete
	ADC_ISR_EOC_Complete = 0x1
	// Clear regular conversion complete flag
	ADC_ISR_EOC_Clear = 0x1
	// Position of EOSMP field.
	ADC_ISR_EOSMP_Pos = 0x1
	// Bit mask of EOSMP field.
	ADC_ISR_EOSMP_Msk = 0x2
	// Bit EOSMP.
	ADC_ISR_EOSMP = 0x2
	// End of sampling phase no yet reached
	ADC_ISR_EOSMP_NotEnded = 0x0
	// End of sampling phase reached
	ADC_ISR_EOSMP_Ended = 0x1
	// Clear end of sampling phase reached flag
	ADC_ISR_EOSMP_Clear = 0x1
	// Position of ADRDY field.
	ADC_ISR_ADRDY_Pos = 0x0
	// Bit mask of ADRDY field.
	ADC_ISR_ADRDY_Msk = 0x1
	// Bit ADRDY.
	ADC_ISR_ADRDY = 0x1
	// ADC is not ready to start conversion
	ADC_ISR_ADRDY_NotReady = 0x0
	// ADC is ready to start conversion
	ADC_ISR_ADRDY_Ready = 0x1
	// Clear ADC is ready to start conversion flag
	ADC_ISR_ADRDY_Clear = 0x1

	// IER: ADC interrupt enable register
	// Position of JQOVFIE field.
	ADC_IER_JQOVFIE_Pos = 0xa
	// Bit mask of JQOVFIE field.
	ADC_IER_JQOVFIE_Msk = 0x400
	// Bit JQOVFIE.
	ADC_IER_JQOVFIE = 0x400
	// Injected context queue overflow interrupt disabled
	ADC_IER_JQOVFIE_Disabled = 0x0
	// Injected context queue overflow interrupt enabled
	ADC_IER_JQOVFIE_Enabled = 0x1
	// Position of AWD3IE field.
	ADC_IER_AWD3IE_Pos = 0x9
	// Bit mask of AWD3IE field.
	ADC_IER_AWD3IE_Msk = 0x200
	// Bit AWD3IE.
	ADC_IER_AWD3IE = 0x200
	// Analog watchdog interrupt disabled
	ADC_IER_AWD3IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD3IE_Enabled = 0x1
	// Position of AWD2IE field.
	ADC_IER_AWD2IE_Pos = 0x8
	// Bit mask of AWD2IE field.
	ADC_IER_AWD2IE_Msk = 0x100
	// Bit AWD2IE.
	ADC_IER_AWD2IE = 0x100
	// Analog watchdog interrupt disabled
	ADC_IER_AWD2IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD2IE_Enabled = 0x1
	// Position of AWD1IE field.
	ADC_IER_AWD1IE_Pos = 0x7
	// Bit mask of AWD1IE field.
	ADC_IER_AWD1IE_Msk = 0x80
	// Bit AWD1IE.
	ADC_IER_AWD1IE = 0x80
	// Analog watchdog interrupt disabled
	ADC_IER_AWD1IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD1IE_Enabled = 0x1
	// Position of JEOSIE field.
	ADC_IER_JEOSIE_Pos = 0x6
	// Bit mask of JEOSIE field.
	ADC_IER_JEOSIE_Msk = 0x40
	// Bit JEOSIE.
	ADC_IER_JEOSIE = 0x40
	// End of injected sequence interrupt disabled
	ADC_IER_JEOSIE_Disabled = 0x0
	// End of injected sequence interrupt enabled
	ADC_IER_JEOSIE_Enabled = 0x1
	// Position of JEOCIE field.
	ADC_IER_JEOCIE_Pos = 0x5
	// Bit mask of JEOCIE field.
	ADC_IER_JEOCIE_Msk = 0x20
	// Bit JEOCIE.
	ADC_IER_JEOCIE = 0x20
	// End of injected conversion interrupt disabled
	ADC_IER_JEOCIE_Disabled = 0x0
	// End of injected conversion interrupt enabled
	ADC_IER_JEOCIE_Enabled = 0x1
	// Position of OVRIE field.
	ADC_IER_OVRIE_Pos = 0x4
	// Bit mask of OVRIE field.
	ADC_IER_OVRIE_Msk = 0x10
	// Bit OVRIE.
	ADC_IER_OVRIE = 0x10
	// Overrun interrupt disabled
	ADC_IER_OVRIE_Disabled = 0x0
	// Overrun interrupt enabled
	ADC_IER_OVRIE_Enabled = 0x1
	// Position of EOSIE field.
	ADC_IER_EOSIE_Pos = 0x3
	// Bit mask of EOSIE field.
	ADC_IER_EOSIE_Msk = 0x8
	// Bit EOSIE.
	ADC_IER_EOSIE = 0x8
	// End of regular sequence interrupt disabled
	ADC_IER_EOSIE_Disabled = 0x0
	// End of regular sequence interrupt enabled
	ADC_IER_EOSIE_Enabled = 0x1
	// Position of EOCIE field.
	ADC_IER_EOCIE_Pos = 0x2
	// Bit mask of EOCIE field.
	ADC_IER_EOCIE_Msk = 0x4
	// Bit EOCIE.
	ADC_IER_EOCIE = 0x4
	// End of regular conversion interrupt disabled
	ADC_IER_EOCIE_Disabled = 0x0
	// End of regular conversion interrupt enabled
	ADC_IER_EOCIE_Enabled = 0x1
	// Position of EOSMPIE field.
	ADC_IER_EOSMPIE_Pos = 0x1
	// Bit mask of EOSMPIE field.
	ADC_IER_EOSMPIE_Msk = 0x2
	// Bit EOSMPIE.
	ADC_IER_EOSMPIE = 0x2
	// End of regular conversion sampling phase interrupt disabled
	ADC_IER_EOSMPIE_Disabled = 0x0
	// End of regular conversion sampling phase interrupt enabled
	ADC_IER_EOSMPIE_Enabled = 0x1
	// Position of ADRDYIE field.
	ADC_IER_ADRDYIE_Pos = 0x0
	// Bit mask of ADRDYIE field.
	ADC_IER_ADRDYIE_Msk = 0x1
	// Bit ADRDYIE.
	ADC_IER_ADRDYIE = 0x1
	// ADC ready interrupt disabled
	ADC_IER_ADRDYIE_Disabled = 0x0
	// ADC ready interrupt enabled
	ADC_IER_ADRDYIE_Enabled = 0x1

	// CR: ADC control register
	// Position of ADCAL field.
	ADC_CR_ADCAL_Pos = 0x1f
	// Bit mask of ADCAL field.
	ADC_CR_ADCAL_Msk = 0x80000000
	// Bit ADCAL.
	ADC_CR_ADCAL = 0x80000000
	// Calibration complete
	ADC_CR_ADCAL_Complete = 0x0
	// Start the calibration of the ADC
	ADC_CR_ADCAL_Calibration = 0x1
	// Position of ADCALDIF field.
	ADC_CR_ADCALDIF_Pos = 0x1e
	// Bit mask of ADCALDIF field.
	ADC_CR_ADCALDIF_Msk = 0x40000000
	// Bit ADCALDIF.
	ADC_CR_ADCALDIF = 0x40000000
	// Calibration for single-ended mode
	ADC_CR_ADCALDIF_SingleEnded = 0x0
	// Calibration for differential mode
	ADC_CR_ADCALDIF_Differential = 0x1
	// Position of DEEPPWD field.
	ADC_CR_DEEPPWD_Pos = 0x1d
	// Bit mask of DEEPPWD field.
	ADC_CR_DEEPPWD_Msk = 0x20000000
	// Bit DEEPPWD.
	ADC_CR_DEEPPWD = 0x20000000
	// ADC not in deep power down
	ADC_CR_DEEPPWD_PowerUp = 0x0
	// ADC in deep power down
	ADC_CR_DEEPPWD_PowerDown = 0x1
	// Position of ADVREGEN field.
	ADC_CR_ADVREGEN_Pos = 0x1c
	// Bit mask of ADVREGEN field.
	ADC_CR_ADVREGEN_Msk = 0x10000000
	// Bit ADVREGEN.
	ADC_CR_ADVREGEN = 0x10000000
	// ADC voltage regulator disabled
	ADC_CR_ADVREGEN_Disabled = 0x0
	// ADC voltage regulator enabled
	ADC_CR_ADVREGEN_Enabled = 0x1
	// Position of LINCALRDYW6 field.
	ADC_CR_LINCALRDYW6_Pos = 0x1b
	// Bit mask of LINCALRDYW6 field.
	ADC_CR_LINCALRDYW6_Msk = 0x8000000
	// Bit LINCALRDYW6.
	ADC_CR_LINCALRDYW6 = 0x8000000
	// LINCALFACT Word Read
	ADC_CR_LINCALRDYW6_Reset = 0x0
	// LINCALFACT Word Write
	ADC_CR_LINCALRDYW6_Set = 0x1
	// Position of LINCALRDYW5 field.
	ADC_CR_LINCALRDYW5_Pos = 0x1a
	// Bit mask of LINCALRDYW5 field.
	ADC_CR_LINCALRDYW5_Msk = 0x4000000
	// Bit LINCALRDYW5.
	ADC_CR_LINCALRDYW5 = 0x4000000
	// LINCALFACT Word Read
	ADC_CR_LINCALRDYW5_Reset = 0x0
	// LINCALFACT Word Write
	ADC_CR_LINCALRDYW5_Set = 0x1
	// Position of LINCALRDYW4 field.
	ADC_CR_LINCALRDYW4_Pos = 0x19
	// Bit mask of LINCALRDYW4 field.
	ADC_CR_LINCALRDYW4_Msk = 0x2000000
	// Bit LINCALRDYW4.
	ADC_CR_LINCALRDYW4 = 0x2000000
	// LINCALFACT Word Read
	ADC_CR_LINCALRDYW4_Reset = 0x0
	// LINCALFACT Word Write
	ADC_CR_LINCALRDYW4_Set = 0x1
	// Position of LINCALRDYW3 field.
	ADC_CR_LINCALRDYW3_Pos = 0x18
	// Bit mask of LINCALRDYW3 field.
	ADC_CR_LINCALRDYW3_Msk = 0x1000000
	// Bit LINCALRDYW3.
	ADC_CR_LINCALRDYW3 = 0x1000000
	// LINCALFACT Word Read
	ADC_CR_LINCALRDYW3_Reset = 0x0
	// LINCALFACT Word Write
	ADC_CR_LINCALRDYW3_Set = 0x1
	// Position of LINCALRDYW2 field.
	ADC_CR_LINCALRDYW2_Pos = 0x17
	// Bit mask of LINCALRDYW2 field.
	ADC_CR_LINCALRDYW2_Msk = 0x800000
	// Bit LINCALRDYW2.
	ADC_CR_LINCALRDYW2 = 0x800000
	// LINCALFACT Word Read
	ADC_CR_LINCALRDYW2_Reset = 0x0
	// LINCALFACT Word Write
	ADC_CR_LINCALRDYW2_Set = 0x1
	// Position of LINCALRDYW1 field.
	ADC_CR_LINCALRDYW1_Pos = 0x16
	// Bit mask of LINCALRDYW1 field.
	ADC_CR_LINCALRDYW1_Msk = 0x400000
	// Bit LINCALRDYW1.
	ADC_CR_LINCALRDYW1 = 0x400000
	// LINCALFACT Word Read
	ADC_CR_LINCALRDYW1_Reset = 0x0
	// LINCALFACT Word Write
	ADC_CR_LINCALRDYW1_Set = 0x1
	// Position of ADCALLIN field.
	ADC_CR_ADCALLIN_Pos = 0x10
	// Bit mask of ADCALLIN field.
	ADC_CR_ADCALLIN_Msk = 0x10000
	// Bit ADCALLIN.
	ADC_CR_ADCALLIN = 0x10000
	// ADC calibration without linearaity calibration
	ADC_CR_ADCALLIN_NoLinearity = 0x0
	// ADC calibration with linearaity calibration
	ADC_CR_ADCALLIN_Linearity = 0x1
	// Position of BOOST field.
	ADC_CR_BOOST_Pos = 0x8
	// Bit mask of BOOST field.
	ADC_CR_BOOST_Msk = 0x300
	// Boost mode used when ADC clock ≤ 6.25 MHz
	ADC_CR_BOOST_LT6_25 = 0x0
	// Boost mode used when 6.25 MHz < ADC clock ≤ 12.5 MHz
	ADC_CR_BOOST_LT12_5 = 0x1
	// Boost mode used when 12.5 MHz < ADC clock ≤ 25.0 MHz
	ADC_CR_BOOST_LT25 = 0x2
	// Boost mode used when 25.0 MHz < ADC clock ≤ 50.0 MHz
	ADC_CR_BOOST_LT50 = 0x3
	// Position of JADSTP field.
	ADC_CR_JADSTP_Pos = 0x5
	// Bit mask of JADSTP field.
	ADC_CR_JADSTP_Msk = 0x20
	// Bit JADSTP.
	ADC_CR_JADSTP = 0x20
	// Stop conversion of channel
	ADC_CR_JADSTP_Stop = 0x1
	// Position of ADSTP field.
	ADC_CR_ADSTP_Pos = 0x4
	// Bit mask of ADSTP field.
	ADC_CR_ADSTP_Msk = 0x10
	// Bit ADSTP.
	ADC_CR_ADSTP = 0x10
	// Stop conversion of channel
	ADC_CR_ADSTP_Stop = 0x1
	// Position of JADSTART field.
	ADC_CR_JADSTART_Pos = 0x3
	// Bit mask of JADSTART field.
	ADC_CR_JADSTART_Msk = 0x8
	// Bit JADSTART.
	ADC_CR_JADSTART = 0x8
	// Starts conversion of channel
	ADC_CR_JADSTART_Start = 0x1
	// Position of ADSTART field.
	ADC_CR_ADSTART_Pos = 0x2
	// Bit mask of ADSTART field.
	ADC_CR_ADSTART_Msk = 0x4
	// Bit ADSTART.
	ADC_CR_ADSTART = 0x4
	// Starts conversion of channel
	ADC_CR_ADSTART_Start = 0x1
	// Position of ADDIS field.
	ADC_CR_ADDIS_Pos = 0x1
	// Bit mask of ADDIS field.
	ADC_CR_ADDIS_Msk = 0x2
	// Bit ADDIS.
	ADC_CR_ADDIS = 0x2
	// Disable ADC conversion and go to power down mode
	ADC_CR_ADDIS_Disable = 0x0
	// Position of ADEN field.
	ADC_CR_ADEN_Pos = 0x0
	// Bit mask of ADEN field.
	ADC_CR_ADEN_Msk = 0x1
	// Bit ADEN.
	ADC_CR_ADEN = 0x1
	// Enable ADC
	ADC_CR_ADEN_Enable = 0x1

	// CFGR: ADC configuration register 1
	// Position of JQDIS field.
	ADC_CFGR_JQDIS_Pos = 0x1f
	// Bit mask of JQDIS field.
	ADC_CFGR_JQDIS_Msk = 0x80000000
	// Bit JQDIS.
	ADC_CFGR_JQDIS = 0x80000000
	// Injected Queue enabled
	ADC_CFGR_JQDIS_Enabled = 0x0
	// Injected Queue disabled
	ADC_CFGR_JQDIS_Disabled = 0x1
	// Position of AWD1CH field.
	ADC_CFGR_AWD1CH_Pos = 0x1a
	// Bit mask of AWD1CH field.
	ADC_CFGR_AWD1CH_Msk = 0x7c000000
	// Position of JAUTO field.
	ADC_CFGR_JAUTO_Pos = 0x19
	// Bit mask of JAUTO field.
	ADC_CFGR_JAUTO_Msk = 0x2000000
	// Bit JAUTO.
	ADC_CFGR_JAUTO = 0x2000000
	// Automatic injected group conversion disabled
	ADC_CFGR_JAUTO_Disabled = 0x0
	// Automatic injected group conversion enabled
	ADC_CFGR_JAUTO_Enabled = 0x1
	// Position of JAWD1EN field.
	ADC_CFGR_JAWD1EN_Pos = 0x18
	// Bit mask of JAWD1EN field.
	ADC_CFGR_JAWD1EN_Msk = 0x1000000
	// Bit JAWD1EN.
	ADC_CFGR_JAWD1EN = 0x1000000
	// Analog watchdog 1 disabled on injected channels
	ADC_CFGR_JAWD1EN_Disabled = 0x0
	// Analog watchdog 1 enabled on injected channels
	ADC_CFGR_JAWD1EN_Enabled = 0x1
	// Position of AWD1EN field.
	ADC_CFGR_AWD1EN_Pos = 0x17
	// Bit mask of AWD1EN field.
	ADC_CFGR_AWD1EN_Msk = 0x800000
	// Bit AWD1EN.
	ADC_CFGR_AWD1EN = 0x800000
	// Analog watchdog 1 disabled on regular channels
	ADC_CFGR_AWD1EN_Disabled = 0x0
	// Analog watchdog 1 enabled on regular channels
	ADC_CFGR_AWD1EN_Enabled = 0x1
	// Position of AWD1SGL field.
	ADC_CFGR_AWD1SGL_Pos = 0x16
	// Bit mask of AWD1SGL field.
	ADC_CFGR_AWD1SGL_Msk = 0x400000
	// Bit AWD1SGL.
	ADC_CFGR_AWD1SGL = 0x400000
	// Analog watchdog 1 enabled on all channels
	ADC_CFGR_AWD1SGL_All = 0x0
	// Analog watchdog 1 enabled on single channel selected in AWD1CH
	ADC_CFGR_AWD1SGL_Single = 0x1
	// Position of JQM field.
	ADC_CFGR_JQM_Pos = 0x15
	// Bit mask of JQM field.
	ADC_CFGR_JQM_Msk = 0x200000
	// Bit JQM.
	ADC_CFGR_JQM = 0x200000
	// JSQR Mode 0: Queue maintains the last written configuration into JSQR
	ADC_CFGR_JQM_Mode0 = 0x0
	// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence
	ADC_CFGR_JQM_Mode1 = 0x1
	// Position of JDISCEN field.
	ADC_CFGR_JDISCEN_Pos = 0x14
	// Bit mask of JDISCEN field.
	ADC_CFGR_JDISCEN_Msk = 0x100000
	// Bit JDISCEN.
	ADC_CFGR_JDISCEN = 0x100000
	// Discontinuous mode on injected channels disabled
	ADC_CFGR_JDISCEN_Disabled = 0x0
	// Discontinuous mode on injected channels enabled
	ADC_CFGR_JDISCEN_Enabled = 0x1
	// Position of DISCNUM field.
	ADC_CFGR_DISCNUM_Pos = 0x11
	// Bit mask of DISCNUM field.
	ADC_CFGR_DISCNUM_Msk = 0xe0000
	// Position of DISCEN field.
	ADC_CFGR_DISCEN_Pos = 0x10
	// Bit mask of DISCEN field.
	ADC_CFGR_DISCEN_Msk = 0x10000
	// Bit DISCEN.
	ADC_CFGR_DISCEN = 0x10000
	// Discontinuous mode on regular channels disabled
	ADC_CFGR_DISCEN_Disabled = 0x0
	// Discontinuous mode on regular channels enabled
	ADC_CFGR_DISCEN_Enabled = 0x1
	// Position of AUTDLY field.
	ADC_CFGR_AUTDLY_Pos = 0xe
	// Bit mask of AUTDLY field.
	ADC_CFGR_AUTDLY_Msk = 0x4000
	// Bit AUTDLY.
	ADC_CFGR_AUTDLY = 0x4000
	// Auto delayed conversion mode off
	ADC_CFGR_AUTDLY_Off = 0x0
	// Auto delayed conversion mode on
	ADC_CFGR_AUTDLY_On = 0x1
	// Position of CONT field.
	ADC_CFGR_CONT_Pos = 0xd
	// Bit mask of CONT field.
	ADC_CFGR_CONT_Msk = 0x2000
	// Bit CONT.
	ADC_CFGR_CONT = 0x2000
	// Single conversion mode
	ADC_CFGR_CONT_Single = 0x0
	// Continuous conversion mode
	ADC_CFGR_CONT_Continuous = 0x1
	// Position of OVRMOD field.
	ADC_CFGR_OVRMOD_Pos = 0xc
	// Bit mask of OVRMOD field.
	ADC_CFGR_OVRMOD_Msk = 0x1000
	// Bit OVRMOD.
	ADC_CFGR_OVRMOD = 0x1000
	// Preserve DR register when an overrun is detected
	ADC_CFGR_OVRMOD_Preserve = 0x0
	// Overwrite DR register when an overrun is detected
	ADC_CFGR_OVRMOD_Overwrite = 0x1
	// Position of EXTEN field.
	ADC_CFGR_EXTEN_Pos = 0xa
	// Bit mask of EXTEN field.
	ADC_CFGR_EXTEN_Msk = 0xc00
	// Trigger detection disabled
	ADC_CFGR_EXTEN_Disabled = 0x0
	// Trigger detection on the rising edge
	ADC_CFGR_EXTEN_RisingEdge = 0x1
	// Trigger detection on the falling edge
	ADC_CFGR_EXTEN_FallingEdge = 0x2
	// Trigger detection on both the rising and falling edges
	ADC_CFGR_EXTEN_BothEdges = 0x3
	// Position of EXTSEL field.
	ADC_CFGR_EXTSEL_Pos = 0x5
	// Bit mask of EXTSEL field.
	ADC_CFGR_EXTSEL_Msk = 0x3e0
	// Timer 4 CC4 event
	ADC_CFGR_EXTSEL_TIM4_CC4 = 0x5
	// Timer 8 TRGO event
	ADC_CFGR_EXTSEL_TIM8_TRGO = 0x7
	// Timer 8 TRGO2 event
	ADC_CFGR_EXTSEL_TIM8_TRGO2 = 0x8
	// Timer 4 TRGO event
	ADC_CFGR_EXTSEL_TIM4_TRGO = 0xc
	// HRTIM1_ADCTRG1 event
	ADC_CFGR_EXTSEL_HRTIM1_ADCTRG1 = 0x10
	// HRTIM1_ADCTRG3 event
	ADC_CFGR_EXTSEL_HRTIM1_ADCTRG3 = 0x11
	// LPTIM1_OUT event
	ADC_CFGR_EXTSEL_LPTIM1_OUT = 0x12
	// LPTIM2_OUT event
	ADC_CFGR_EXTSEL_LPTIM2_OUT = 0x13
	// LPTIM3_OUT event
	ADC_CFGR_EXTSEL_LPTIM3_OUT = 0x14
	// Timer 1 CC1 event
	ADC_CFGR_EXTSEL_TIM1_CC1 = 0x0
	// Timer 1 CC2 event
	ADC_CFGR_EXTSEL_TIM1_CC2 = 0x1
	// Timer 1 CC3 event
	ADC_CFGR_EXTSEL_TIM1_CC3 = 0x2
	// Timer 2 CC2 event
	ADC_CFGR_EXTSEL_TIM2_CC2 = 0x3
	// Timer 3 TRGO event
	ADC_CFGR_EXTSEL_TIM3_TRGO = 0x4
	// EXTI line 11
	ADC_CFGR_EXTSEL_EXTI11 = 0x6
	// Timer 1 TRGO event
	ADC_CFGR_EXTSEL_TIM1_TRGO = 0x9
	// Timer 1 TRGO2 event
	ADC_CFGR_EXTSEL_TIM1_TRGO2 = 0xa
	// Timer 2 TRGO event
	ADC_CFGR_EXTSEL_TIM2_TRGO = 0xb
	// Timer 6 TRGO event
	ADC_CFGR_EXTSEL_TIM6_TRGO = 0xd
	// Timer 15 TRGO event
	ADC_CFGR_EXTSEL_TIM15_TRGO = 0xe
	// Timer 3 CC4 event
	ADC_CFGR_EXTSEL_TIM3_CC4 = 0xf
	// Position of RES field.
	ADC_CFGR_RES_Pos = 0x2
	// Bit mask of RES field.
	ADC_CFGR_RES_Msk = 0x1c
	// 16-bit resolution
	ADC_CFGR_RES_SixteenBit = 0x0
	// 14-bit resolution
	ADC_CFGR_RES_FourteenBit = 0x1
	// 12-bit resolution
	ADC_CFGR_RES_TwelveBit = 0x2
	// 10-bit resolution
	ADC_CFGR_RES_TenBit = 0x3
	// 8-bit resolution
	ADC_CFGR_RES_EightBit = 0x7
	// Position of DMNGT field.
	ADC_CFGR_DMNGT_Pos = 0x0
	// Bit mask of DMNGT field.
	ADC_CFGR_DMNGT_Msk = 0x3
	// Store output data in DR only
	ADC_CFGR_DMNGT_DR = 0x0
	// DMA One Shot Mode selected
	ADC_CFGR_DMNGT_DMA_OneShot = 0x1
	// DFSDM mode selected
	ADC_CFGR_DMNGT_DFSDM = 0x2
	// DMA Circular Mode selected
	ADC_CFGR_DMNGT_DMA_Circular = 0x3

	// CFGR2: ADC configuration register 2
	// Position of ROVSE field.
	ADC_CFGR2_ROVSE_Pos = 0x0
	// Bit mask of ROVSE field.
	ADC_CFGR2_ROVSE_Msk = 0x1
	// Bit ROVSE.
	ADC_CFGR2_ROVSE = 0x1
	// Regular oversampling disabled
	ADC_CFGR2_ROVSE_Disabled = 0x0
	// Regular oversampling enabled
	ADC_CFGR2_ROVSE_Enabled = 0x1
	// Position of JOVSE field.
	ADC_CFGR2_JOVSE_Pos = 0x1
	// Bit mask of JOVSE field.
	ADC_CFGR2_JOVSE_Msk = 0x2
	// Bit JOVSE.
	ADC_CFGR2_JOVSE = 0x2
	// Injected oversampling disabled
	ADC_CFGR2_JOVSE_Disabled = 0x0
	// Injected oversampling enabled
	ADC_CFGR2_JOVSE_Enabled = 0x1
	// Position of OVSS field.
	ADC_CFGR2_OVSS_Pos = 0x5
	// Bit mask of OVSS field.
	ADC_CFGR2_OVSS_Msk = 0x1e0
	// Position of TROVS field.
	ADC_CFGR2_TROVS_Pos = 0x9
	// Bit mask of TROVS field.
	ADC_CFGR2_TROVS_Msk = 0x200
	// Bit TROVS.
	ADC_CFGR2_TROVS = 0x200
	// All oversampled conversions for a channel are run following a trigger
	ADC_CFGR2_TROVS_Automatic = 0x0
	// Each oversampled conversion for a channel needs a new trigger
	ADC_CFGR2_TROVS_Triggered = 0x1
	// Position of ROVSM field.
	ADC_CFGR2_ROVSM_Pos = 0xa
	// Bit mask of ROVSM field.
	ADC_CFGR2_ROVSM_Msk = 0x400
	// Bit ROVSM.
	ADC_CFGR2_ROVSM = 0x400
	// Oversampling is temporary stopped and continued after injection sequence
	ADC_CFGR2_ROVSM_Continued = 0x0
	// Oversampling is aborted and resumed from start after injection sequence
	ADC_CFGR2_ROVSM_Resumed = 0x1
	// Position of RSHIFT1 field.
	ADC_CFGR2_RSHIFT1_Pos = 0xb
	// Bit mask of RSHIFT1 field.
	ADC_CFGR2_RSHIFT1_Msk = 0x800
	// Bit RSHIFT1.
	ADC_CFGR2_RSHIFT1 = 0x800
	// Right-shifting disabled
	ADC_CFGR2_RSHIFT1_Disabled = 0x0
	// Data is right-shifted 1-bit
	ADC_CFGR2_RSHIFT1_Enabled = 0x1
	// Position of RSHIFT2 field.
	ADC_CFGR2_RSHIFT2_Pos = 0xc
	// Bit mask of RSHIFT2 field.
	ADC_CFGR2_RSHIFT2_Msk = 0x1000
	// Bit RSHIFT2.
	ADC_CFGR2_RSHIFT2 = 0x1000
	// Right-shifting disabled
	ADC_CFGR2_RSHIFT2_Disabled = 0x0
	// Data is right-shifted 1-bit
	ADC_CFGR2_RSHIFT2_Enabled = 0x1
	// Position of RSHIFT3 field.
	ADC_CFGR2_RSHIFT3_Pos = 0xd
	// Bit mask of RSHIFT3 field.
	ADC_CFGR2_RSHIFT3_Msk = 0x2000
	// Bit RSHIFT3.
	ADC_CFGR2_RSHIFT3 = 0x2000
	// Right-shifting disabled
	ADC_CFGR2_RSHIFT3_Disabled = 0x0
	// Data is right-shifted 1-bit
	ADC_CFGR2_RSHIFT3_Enabled = 0x1
	// Position of RSHIFT4 field.
	ADC_CFGR2_RSHIFT4_Pos = 0xe
	// Bit mask of RSHIFT4 field.
	ADC_CFGR2_RSHIFT4_Msk = 0x4000
	// Bit RSHIFT4.
	ADC_CFGR2_RSHIFT4 = 0x4000
	// Right-shifting disabled
	ADC_CFGR2_RSHIFT4_Disabled = 0x0
	// Data is right-shifted 1-bit
	ADC_CFGR2_RSHIFT4_Enabled = 0x1
	// Position of OSVR field.
	ADC_CFGR2_OSVR_Pos = 0x10
	// Bit mask of OSVR field.
	ADC_CFGR2_OSVR_Msk = 0x3ff0000
	// Position of LSHIFT field.
	ADC_CFGR2_LSHIFT_Pos = 0x1c
	// Bit mask of LSHIFT field.
	ADC_CFGR2_LSHIFT_Msk = 0xf0000000

	// SMPR1: ADC sampling time register 1
	// Position of SMP9 field.
	ADC_SMPR1_SMP9_Pos = 0x1b
	// Bit mask of SMP9 field.
	ADC_SMPR1_SMP9_Msk = 0x38000000
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles810_5 = 0x7
	// Position of SMP8 field.
	ADC_SMPR1_SMP8_Pos = 0x18
	// Bit mask of SMP8 field.
	ADC_SMPR1_SMP8_Msk = 0x7000000
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles810_5 = 0x7
	// Position of SMP7 field.
	ADC_SMPR1_SMP7_Pos = 0x15
	// Bit mask of SMP7 field.
	ADC_SMPR1_SMP7_Msk = 0xe00000
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles810_5 = 0x7
	// Position of SMP6 field.
	ADC_SMPR1_SMP6_Pos = 0x12
	// Bit mask of SMP6 field.
	ADC_SMPR1_SMP6_Msk = 0x1c0000
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles810_5 = 0x7
	// Position of SMP5 field.
	ADC_SMPR1_SMP5_Pos = 0xf
	// Bit mask of SMP5 field.
	ADC_SMPR1_SMP5_Msk = 0x38000
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles810_5 = 0x7
	// Position of SMP4 field.
	ADC_SMPR1_SMP4_Pos = 0xc
	// Bit mask of SMP4 field.
	ADC_SMPR1_SMP4_Msk = 0x7000
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles810_5 = 0x7
	// Position of SMP3 field.
	ADC_SMPR1_SMP3_Pos = 0x9
	// Bit mask of SMP3 field.
	ADC_SMPR1_SMP3_Msk = 0xe00
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles810_5 = 0x7
	// Position of SMP2 field.
	ADC_SMPR1_SMP2_Pos = 0x6
	// Bit mask of SMP2 field.
	ADC_SMPR1_SMP2_Msk = 0x1c0
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles810_5 = 0x7
	// Position of SMP1 field.
	ADC_SMPR1_SMP1_Pos = 0x3
	// Bit mask of SMP1 field.
	ADC_SMPR1_SMP1_Msk = 0x38
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles810_5 = 0x7
	// Position of SMP0 field.
	ADC_SMPR1_SMP0_Pos = 0x0
	// Bit mask of SMP0 field.
	ADC_SMPR1_SMP0_Msk = 0x7
	// 1.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles810_5 = 0x7

	// SMPR2: ADC sampling time register 2
	// Position of SMP19 field.
	ADC_SMPR2_SMP19_Pos = 0x1b
	// Bit mask of SMP19 field.
	ADC_SMPR2_SMP19_Msk = 0x38000000
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles810_5 = 0x7
	// Position of SMP18 field.
	ADC_SMPR2_SMP18_Pos = 0x18
	// Bit mask of SMP18 field.
	ADC_SMPR2_SMP18_Msk = 0x7000000
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles810_5 = 0x7
	// Position of SMP17 field.
	ADC_SMPR2_SMP17_Pos = 0x15
	// Bit mask of SMP17 field.
	ADC_SMPR2_SMP17_Msk = 0xe00000
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles810_5 = 0x7
	// Position of SMP16 field.
	ADC_SMPR2_SMP16_Pos = 0x12
	// Bit mask of SMP16 field.
	ADC_SMPR2_SMP16_Msk = 0x1c0000
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles810_5 = 0x7
	// Position of SMP15 field.
	ADC_SMPR2_SMP15_Pos = 0xf
	// Bit mask of SMP15 field.
	ADC_SMPR2_SMP15_Msk = 0x38000
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles810_5 = 0x7
	// Position of SMP14 field.
	ADC_SMPR2_SMP14_Pos = 0xc
	// Bit mask of SMP14 field.
	ADC_SMPR2_SMP14_Msk = 0x7000
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles810_5 = 0x7
	// Position of SMP13 field.
	ADC_SMPR2_SMP13_Pos = 0x9
	// Bit mask of SMP13 field.
	ADC_SMPR2_SMP13_Msk = 0xe00
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles810_5 = 0x7
	// Position of SMP12 field.
	ADC_SMPR2_SMP12_Pos = 0x6
	// Bit mask of SMP12 field.
	ADC_SMPR2_SMP12_Msk = 0x1c0
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles810_5 = 0x7
	// Position of SMP11 field.
	ADC_SMPR2_SMP11_Pos = 0x3
	// Bit mask of SMP11 field.
	ADC_SMPR2_SMP11_Msk = 0x38
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles810_5 = 0x7
	// Position of SMP10 field.
	ADC_SMPR2_SMP10_Pos = 0x0
	// Bit mask of SMP10 field.
	ADC_SMPR2_SMP10_Msk = 0x7
	// 1.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles1_5 = 0x0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles2_5 = 0x1
	// 8.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles8_5 = 0x2
	// 16.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles16_5 = 0x3
	// 32.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles32_5 = 0x4
	// 64.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles64_5 = 0x5
	// 387.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles387_5 = 0x6
	// 810.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles810_5 = 0x7

	// PCSEL: ADC pre channel selection register
	// Position of PCSEL field.
	ADC_PCSEL_PCSEL_Pos = 0x0
	// Bit mask of PCSEL field.
	ADC_PCSEL_PCSEL_Msk = 0xfffff
	// Input channel x is not pre-selected
	ADC_PCSEL_PCSEL_NotPreselected = 0x0
	// Pre-select input channel x
	ADC_PCSEL_PCSEL_Preselected = 0x1

	// LTR1: ADC analog watchdog 1 threshold register
	// Position of LTR1 field.
	ADC_LTR1_LTR1_Pos = 0x0
	// Bit mask of LTR1 field.
	ADC_LTR1_LTR1_Msk = 0x3ffffff

	// HTR1: ADC analog watchdog 2 threshold register
	// Position of HTR1 field.
	ADC_HTR1_HTR1_Pos = 0x0
	// Bit mask of HTR1 field.
	ADC_HTR1_HTR1_Msk = 0x3ffffff

	// SQR1: ADC group regular sequencer ranks register 1
	// Position of SQ4 field.
	ADC_SQR1_SQ4_Pos = 0x18
	// Bit mask of SQ4 field.
	ADC_SQR1_SQ4_Msk = 0x1f000000
	// Position of SQ3 field.
	ADC_SQR1_SQ3_Pos = 0x12
	// Bit mask of SQ3 field.
	ADC_SQR1_SQ3_Msk = 0x7c0000
	// Position of SQ2 field.
	ADC_SQR1_SQ2_Pos = 0xc
	// Bit mask of SQ2 field.
	ADC_SQR1_SQ2_Msk = 0x1f000
	// Position of SQ1 field.
	ADC_SQR1_SQ1_Pos = 0x6
	// Bit mask of SQ1 field.
	ADC_SQR1_SQ1_Msk = 0x7c0
	// Position of L field.
	ADC_SQR1_L_Pos = 0x0
	// Bit mask of L field.
	ADC_SQR1_L_Msk = 0xf

	// SQR2: ADC group regular sequencer ranks register 2
	// Position of SQ9 field.
	ADC_SQR2_SQ9_Pos = 0x18
	// Bit mask of SQ9 field.
	ADC_SQR2_SQ9_Msk = 0x1f000000
	// Position of SQ8 field.
	ADC_SQR2_SQ8_Pos = 0x12
	// Bit mask of SQ8 field.
	ADC_SQR2_SQ8_Msk = 0x7c0000
	// Position of SQ7 field.
	ADC_SQR2_SQ7_Pos = 0xc
	// Bit mask of SQ7 field.
	ADC_SQR2_SQ7_Msk = 0x1f000
	// Position of SQ6 field.
	ADC_SQR2_SQ6_Pos = 0x6
	// Bit mask of SQ6 field.
	ADC_SQR2_SQ6_Msk = 0x7c0
	// Position of SQ5 field.
	ADC_SQR2_SQ5_Pos = 0x0
	// Bit mask of SQ5 field.
	ADC_SQR2_SQ5_Msk = 0x1f

	// SQR3: ADC group regular sequencer ranks register 3
	// Position of SQ14 field.
	ADC_SQR3_SQ14_Pos = 0x18
	// Bit mask of SQ14 field.
	ADC_SQR3_SQ14_Msk = 0x1f000000
	// Position of SQ13 field.
	ADC_SQR3_SQ13_Pos = 0x12
	// Bit mask of SQ13 field.
	ADC_SQR3_SQ13_Msk = 0x7c0000
	// Position of SQ12 field.
	ADC_SQR3_SQ12_Pos = 0xc
	// Bit mask of SQ12 field.
	ADC_SQR3_SQ12_Msk = 0x1f000
	// Position of SQ11 field.
	ADC_SQR3_SQ11_Pos = 0x6
	// Bit mask of SQ11 field.
	ADC_SQR3_SQ11_Msk = 0x7c0
	// Position of SQ10 field.
	ADC_SQR3_SQ10_Pos = 0x0
	// Bit mask of SQ10 field.
	ADC_SQR3_SQ10_Msk = 0x1f

	// SQR4: ADC group regular sequencer ranks register 4
	// Position of SQ16 field.
	ADC_SQR4_SQ16_Pos = 0x6
	// Bit mask of SQ16 field.
	ADC_SQR4_SQ16_Msk = 0x7c0
	// Position of SQ15 field.
	ADC_SQR4_SQ15_Pos = 0x0
	// Bit mask of SQ15 field.
	ADC_SQR4_SQ15_Msk = 0x1f

	// DR: ADC group regular conversion data register
	// Position of RDATA field.
	ADC_DR_RDATA_Pos = 0x0
	// Bit mask of RDATA field.
	ADC_DR_RDATA_Msk = 0xffff

	// JSQR: ADC group injected sequencer register
	// Position of JSQ4 field.
	ADC_JSQR_JSQ4_Pos = 0x1b
	// Bit mask of JSQ4 field.
	ADC_JSQR_JSQ4_Msk = 0xf8000000
	// Position of JSQ3 field.
	ADC_JSQR_JSQ3_Pos = 0x15
	// Bit mask of JSQ3 field.
	ADC_JSQR_JSQ3_Msk = 0x3e00000
	// Position of JSQ2 field.
	ADC_JSQR_JSQ2_Pos = 0xf
	// Bit mask of JSQ2 field.
	ADC_JSQR_JSQ2_Msk = 0xf8000
	// Position of JSQ1 field.
	ADC_JSQR_JSQ1_Pos = 0x9
	// Bit mask of JSQ1 field.
	ADC_JSQR_JSQ1_Msk = 0x3e00
	// Position of JEXTEN field.
	ADC_JSQR_JEXTEN_Pos = 0x7
	// Bit mask of JEXTEN field.
	ADC_JSQR_JEXTEN_Msk = 0x180
	// Trigger detection disabled
	ADC_JSQR_JEXTEN_Disabled = 0x0
	// Trigger detection on the rising edge
	ADC_JSQR_JEXTEN_RisingEdge = 0x1
	// Trigger detection on the falling edge
	ADC_JSQR_JEXTEN_FallingEdge = 0x2
	// Trigger detection on both the rising and falling edges
	ADC_JSQR_JEXTEN_BothEdges = 0x3
	// Position of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Pos = 0x2
	// Bit mask of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Msk = 0x7c
	// Timer 4 TRGO event
	ADC_JSQR_JEXTSEL_TIM4_TRGO = 0x5
	// Timer 8 CC4 event
	ADC_JSQR_JEXTSEL_TIM8_CC4 = 0x7
	// Timer 8 TRGO event
	ADC_JSQR_JEXTSEL_TIM8_TRGO = 0x9
	// Timer 8 TRGO2 event
	ADC_JSQR_JEXTSEL_TIM8_TRGO2 = 0xa
	// HRTIM1_ADCTRG2 event
	ADC_JSQR_JEXTSEL_HRTIM1_ADCTRG2 = 0x10
	// HRTIM1_ADCTRG4 event
	ADC_JSQR_JEXTSEL_HRTIM1_ADCTRG4 = 0x11
	// LPTIM1_OUT event
	ADC_JSQR_JEXTSEL_LPTIM1_OUT = 0x12
	// LPTIM2_OUT event
	ADC_JSQR_JEXTSEL_LPTIM2_OUT = 0x13
	// LPTIM3_OUT event
	ADC_JSQR_JEXTSEL_LPTIM3_OUT = 0x14
	// Position of JL field.
	ADC_JSQR_JL_Pos = 0x0
	// Bit mask of JL field.
	ADC_JSQR_JL_Msk = 0x3

	// OFR1: ADC offset number 1 register
	// Position of SSATE field.
	ADC_OFR1_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_OFR1_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_OFR1_SSATE = 0x80000000
	// Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
	ADC_OFR1_SSATE_Disabled = 0x0
	// Offset is subtracted and result is saturated to maintain result size
	ADC_OFR1_SSATE_Enabled = 0x1
	// Position of OFFSET1_CH field.
	ADC_OFR1_OFFSET1_CH_Pos = 0x1a
	// Bit mask of OFFSET1_CH field.
	ADC_OFR1_OFFSET1_CH_Msk = 0x7c000000
	// Position of OFFSET1 field.
	ADC_OFR1_OFFSET1_Pos = 0x0
	// Bit mask of OFFSET1 field.
	ADC_OFR1_OFFSET1_Msk = 0x3ffffff

	// OFR2: ADC offset number 2 register
	// Position of SSATE field.
	ADC_OFR2_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_OFR2_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_OFR2_SSATE = 0x80000000
	// Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
	ADC_OFR2_SSATE_Disabled = 0x0
	// Offset is subtracted and result is saturated to maintain result size
	ADC_OFR2_SSATE_Enabled = 0x1
	// Position of OFFSET2_CH field.
	ADC_OFR2_OFFSET2_CH_Pos = 0x1a
	// Bit mask of OFFSET2_CH field.
	ADC_OFR2_OFFSET2_CH_Msk = 0x7c000000
	// Position of OFFSET2 field.
	ADC_OFR2_OFFSET2_Pos = 0x0
	// Bit mask of OFFSET2 field.
	ADC_OFR2_OFFSET2_Msk = 0x3ffffff

	// OFR3: ADC offset number 3 register
	// Position of SSATE field.
	ADC_OFR3_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_OFR3_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_OFR3_SSATE = 0x80000000
	// Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
	ADC_OFR3_SSATE_Disabled = 0x0
	// Offset is subtracted and result is saturated to maintain result size
	ADC_OFR3_SSATE_Enabled = 0x1
	// Position of OFFSET3_CH field.
	ADC_OFR3_OFFSET3_CH_Pos = 0x1a
	// Bit mask of OFFSET3_CH field.
	ADC_OFR3_OFFSET3_CH_Msk = 0x7c000000
	// Position of OFFSET3 field.
	ADC_OFR3_OFFSET3_Pos = 0x0
	// Bit mask of OFFSET3 field.
	ADC_OFR3_OFFSET3_Msk = 0x3ffffff

	// OFR4: ADC offset number 4 register
	// Position of SSATE field.
	ADC_OFR4_SSATE_Pos = 0x1f
	// Bit mask of SSATE field.
	ADC_OFR4_SSATE_Msk = 0x80000000
	// Bit SSATE.
	ADC_OFR4_SSATE = 0x80000000
	// Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
	ADC_OFR4_SSATE_Disabled = 0x0
	// Offset is subtracted and result is saturated to maintain result size
	ADC_OFR4_SSATE_Enabled = 0x1
	// Position of OFFSET4_CH field.
	ADC_OFR4_OFFSET4_CH_Pos = 0x1a
	// Bit mask of OFFSET4_CH field.
	ADC_OFR4_OFFSET4_CH_Msk = 0x7c000000
	// Position of OFFSET4 field.
	ADC_OFR4_OFFSET4_Pos = 0x0
	// Bit mask of OFFSET4 field.
	ADC_OFR4_OFFSET4_Msk = 0x3ffffff

	// JDR1: ADC group injected sequencer rank 1 register
	// Position of JDATA1 field.
	ADC_JDR1_JDATA1_Pos = 0x0
	// Bit mask of JDATA1 field.
	ADC_JDR1_JDATA1_Msk = 0xffffffff

	// JDR2: ADC group injected sequencer rank 2 register
	// Position of JDATA2 field.
	ADC_JDR2_JDATA2_Pos = 0x0
	// Bit mask of JDATA2 field.
	ADC_JDR2_JDATA2_Msk = 0xffffffff

	// JDR3: ADC group injected sequencer rank 3 register
	// Position of JDATA3 field.
	ADC_JDR3_JDATA3_Pos = 0x0
	// Bit mask of JDATA3 field.
	ADC_JDR3_JDATA3_Msk = 0xffffffff

	// JDR4: ADC group injected sequencer rank 4 register
	// Position of JDATA4 field.
	ADC_JDR4_JDATA4_Pos = 0x0
	// Bit mask of JDATA4 field.
	ADC_JDR4_JDATA4_Msk = 0xffffffff

	// AWD2CR: ADC analog watchdog 2 configuration register
	// Position of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Pos = 0x0
	// Bit mask of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Msk = 0x1
	// Bit AWD2CH0.
	ADC_AWD2CR_AWD2CH0 = 0x1
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH0_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH0_Monitored = 0x1
	// Position of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Pos = 0x1
	// Bit mask of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Msk = 0x2
	// Bit AWD2CH1.
	ADC_AWD2CR_AWD2CH1 = 0x2
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH1_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH1_Monitored = 0x1
	// Position of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Pos = 0x2
	// Bit mask of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Msk = 0x4
	// Bit AWD2CH2.
	ADC_AWD2CR_AWD2CH2 = 0x4
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH2_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH2_Monitored = 0x1
	// Position of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Pos = 0x3
	// Bit mask of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Msk = 0x8
	// Bit AWD2CH3.
	ADC_AWD2CR_AWD2CH3 = 0x8
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH3_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH3_Monitored = 0x1
	// Position of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Pos = 0x4
	// Bit mask of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Msk = 0x10
	// Bit AWD2CH4.
	ADC_AWD2CR_AWD2CH4 = 0x10
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH4_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH4_Monitored = 0x1
	// Position of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Pos = 0x5
	// Bit mask of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Msk = 0x20
	// Bit AWD2CH5.
	ADC_AWD2CR_AWD2CH5 = 0x20
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH5_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH5_Monitored = 0x1
	// Position of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Pos = 0x6
	// Bit mask of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Msk = 0x40
	// Bit AWD2CH6.
	ADC_AWD2CR_AWD2CH6 = 0x40
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH6_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH6_Monitored = 0x1
	// Position of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Pos = 0x7
	// Bit mask of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Msk = 0x80
	// Bit AWD2CH7.
	ADC_AWD2CR_AWD2CH7 = 0x80
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH7_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH7_Monitored = 0x1
	// Position of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Pos = 0x8
	// Bit mask of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Msk = 0x100
	// Bit AWD2CH8.
	ADC_AWD2CR_AWD2CH8 = 0x100
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH8_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH8_Monitored = 0x1
	// Position of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Pos = 0x9
	// Bit mask of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Msk = 0x200
	// Bit AWD2CH9.
	ADC_AWD2CR_AWD2CH9 = 0x200
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH9_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH9_Monitored = 0x1
	// Position of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Pos = 0xa
	// Bit mask of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Msk = 0x400
	// Bit AWD2CH10.
	ADC_AWD2CR_AWD2CH10 = 0x400
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH10_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH10_Monitored = 0x1
	// Position of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Pos = 0xb
	// Bit mask of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Msk = 0x800
	// Bit AWD2CH11.
	ADC_AWD2CR_AWD2CH11 = 0x800
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH11_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH11_Monitored = 0x1
	// Position of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Pos = 0xc
	// Bit mask of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Msk = 0x1000
	// Bit AWD2CH12.
	ADC_AWD2CR_AWD2CH12 = 0x1000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH12_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH12_Monitored = 0x1
	// Position of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Pos = 0xd
	// Bit mask of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Msk = 0x2000
	// Bit AWD2CH13.
	ADC_AWD2CR_AWD2CH13 = 0x2000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH13_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH13_Monitored = 0x1
	// Position of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Pos = 0xe
	// Bit mask of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Msk = 0x4000
	// Bit AWD2CH14.
	ADC_AWD2CR_AWD2CH14 = 0x4000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH14_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH14_Monitored = 0x1
	// Position of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Pos = 0xf
	// Bit mask of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Msk = 0x8000
	// Bit AWD2CH15.
	ADC_AWD2CR_AWD2CH15 = 0x8000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH15_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH15_Monitored = 0x1
	// Position of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Pos = 0x10
	// Bit mask of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Msk = 0x10000
	// Bit AWD2CH16.
	ADC_AWD2CR_AWD2CH16 = 0x10000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH16_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH16_Monitored = 0x1
	// Position of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Pos = 0x11
	// Bit mask of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Msk = 0x20000
	// Bit AWD2CH17.
	ADC_AWD2CR_AWD2CH17 = 0x20000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH17_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH17_Monitored = 0x1
	// Position of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Pos = 0x12
	// Bit mask of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Msk = 0x40000
	// Bit AWD2CH18.
	ADC_AWD2CR_AWD2CH18 = 0x40000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH18_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH18_Monitored = 0x1
	// Position of AWD2CH19 field.
	ADC_AWD2CR_AWD2CH19_Pos = 0x13
	// Bit mask of AWD2CH19 field.
	ADC_AWD2CR_AWD2CH19_Msk = 0x80000
	// Bit AWD2CH19.
	ADC_AWD2CR_AWD2CH19 = 0x80000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH19_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH19_Monitored = 0x1

	// AWD3CR: ADC analog watchdog 3 configuration register
	// Position of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Pos = 0x0
	// Bit mask of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Msk = 0x1
	// Bit AWD3CH0.
	ADC_AWD3CR_AWD3CH0 = 0x1
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH0_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH0_Monitored = 0x1
	// Position of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Pos = 0x1
	// Bit mask of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Msk = 0x2
	// Bit AWD3CH1.
	ADC_AWD3CR_AWD3CH1 = 0x2
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH1_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH1_Monitored = 0x1
	// Position of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Pos = 0x2
	// Bit mask of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Msk = 0x4
	// Bit AWD3CH2.
	ADC_AWD3CR_AWD3CH2 = 0x4
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH2_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH2_Monitored = 0x1
	// Position of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Pos = 0x3
	// Bit mask of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Msk = 0x8
	// Bit AWD3CH3.
	ADC_AWD3CR_AWD3CH3 = 0x8
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH3_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH3_Monitored = 0x1
	// Position of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Pos = 0x4
	// Bit mask of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Msk = 0x10
	// Bit AWD3CH4.
	ADC_AWD3CR_AWD3CH4 = 0x10
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH4_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH4_Monitored = 0x1
	// Position of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Pos = 0x5
	// Bit mask of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Msk = 0x20
	// Bit AWD3CH5.
	ADC_AWD3CR_AWD3CH5 = 0x20
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH5_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH5_Monitored = 0x1
	// Position of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Pos = 0x6
	// Bit mask of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Msk = 0x40
	// Bit AWD3CH6.
	ADC_AWD3CR_AWD3CH6 = 0x40
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH6_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH6_Monitored = 0x1
	// Position of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Pos = 0x7
	// Bit mask of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Msk = 0x80
	// Bit AWD3CH7.
	ADC_AWD3CR_AWD3CH7 = 0x80
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH7_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH7_Monitored = 0x1
	// Position of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Pos = 0x8
	// Bit mask of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Msk = 0x100
	// Bit AWD3CH8.
	ADC_AWD3CR_AWD3CH8 = 0x100
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH8_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH8_Monitored = 0x1
	// Position of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Pos = 0x9
	// Bit mask of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Msk = 0x200
	// Bit AWD3CH9.
	ADC_AWD3CR_AWD3CH9 = 0x200
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH9_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH9_Monitored = 0x1
	// Position of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Pos = 0xa
	// Bit mask of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Msk = 0x400
	// Bit AWD3CH10.
	ADC_AWD3CR_AWD3CH10 = 0x400
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH10_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH10_Monitored = 0x1
	// Position of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Pos = 0xb
	// Bit mask of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Msk = 0x800
	// Bit AWD3CH11.
	ADC_AWD3CR_AWD3CH11 = 0x800
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH11_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH11_Monitored = 0x1
	// Position of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Pos = 0xc
	// Bit mask of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Msk = 0x1000
	// Bit AWD3CH12.
	ADC_AWD3CR_AWD3CH12 = 0x1000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH12_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH12_Monitored = 0x1
	// Position of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Pos = 0xd
	// Bit mask of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Msk = 0x2000
	// Bit AWD3CH13.
	ADC_AWD3CR_AWD3CH13 = 0x2000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH13_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH13_Monitored = 0x1
	// Position of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Pos = 0xe
	// Bit mask of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Msk = 0x4000
	// Bit AWD3CH14.
	ADC_AWD3CR_AWD3CH14 = 0x4000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH14_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH14_Monitored = 0x1
	// Position of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Pos = 0xf
	// Bit mask of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Msk = 0x8000
	// Bit AWD3CH15.
	ADC_AWD3CR_AWD3CH15 = 0x8000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH15_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH15_Monitored = 0x1
	// Position of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Pos = 0x10
	// Bit mask of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Msk = 0x10000
	// Bit AWD3CH16.
	ADC_AWD3CR_AWD3CH16 = 0x10000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH16_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH16_Monitored = 0x1
	// Position of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Pos = 0x11
	// Bit mask of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Msk = 0x20000
	// Bit AWD3CH17.
	ADC_AWD3CR_AWD3CH17 = 0x20000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH17_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH17_Monitored = 0x1
	// Position of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Pos = 0x12
	// Bit mask of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Msk = 0x40000
	// Bit AWD3CH18.
	ADC_AWD3CR_AWD3CH18 = 0x40000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH18_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH18_Monitored = 0x1
	// Position of AWD3CH19 field.
	ADC_AWD3CR_AWD3CH19_Pos = 0x13
	// Bit mask of AWD3CH19 field.
	ADC_AWD3CR_AWD3CH19_Msk = 0x80000
	// Bit AWD3CH19.
	ADC_AWD3CR_AWD3CH19 = 0x80000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH19_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH19_Monitored = 0x1

	// LTR2: ADC watchdog lower threshold register 2
	// Position of LTR2 field.
	ADC_LTR2_LTR2_Pos = 0x0
	// Bit mask of LTR2 field.
	ADC_LTR2_LTR2_Msk = 0x3ffffff

	// HTR2: ADC watchdog higher threshold register 2
	// Position of HTR2 field.
	ADC_HTR2_HTR2_Pos = 0x0
	// Bit mask of HTR2 field.
	ADC_HTR2_HTR2_Msk = 0x3ffffff

	// LTR3: ADC watchdog lower threshold register 3
	// Position of LTR3 field.
	ADC_LTR3_LTR3_Pos = 0x0
	// Bit mask of LTR3 field.
	ADC_LTR3_LTR3_Msk = 0x3ffffff

	// HTR3: ADC watchdog higher threshold register 3
	// Position of HTR3 field.
	ADC_HTR3_HTR3_Pos = 0x0
	// Bit mask of HTR3 field.
	ADC_HTR3_HTR3_Msk = 0x3ffffff

	// DIFSEL: ADC channel differential or single-ended mode selection register
	// Position of DIFSEL0 field.
	ADC_DIFSEL_DIFSEL0_Pos = 0x0
	// Bit mask of DIFSEL0 field.
	ADC_DIFSEL_DIFSEL0_Msk = 0x1
	// Bit DIFSEL0.
	ADC_DIFSEL_DIFSEL0 = 0x1
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL0_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL0_Differential = 0x1
	// Position of DIFSEL1 field.
	ADC_DIFSEL_DIFSEL1_Pos = 0x1
	// Bit mask of DIFSEL1 field.
	ADC_DIFSEL_DIFSEL1_Msk = 0x2
	// Bit DIFSEL1.
	ADC_DIFSEL_DIFSEL1 = 0x2
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL1_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL1_Differential = 0x1
	// Position of DIFSEL2 field.
	ADC_DIFSEL_DIFSEL2_Pos = 0x2
	// Bit mask of DIFSEL2 field.
	ADC_DIFSEL_DIFSEL2_Msk = 0x4
	// Bit DIFSEL2.
	ADC_DIFSEL_DIFSEL2 = 0x4
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL2_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL2_Differential = 0x1
	// Position of DIFSEL3 field.
	ADC_DIFSEL_DIFSEL3_Pos = 0x3
	// Bit mask of DIFSEL3 field.
	ADC_DIFSEL_DIFSEL3_Msk = 0x8
	// Bit DIFSEL3.
	ADC_DIFSEL_DIFSEL3 = 0x8
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL3_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL3_Differential = 0x1
	// Position of DIFSEL4 field.
	ADC_DIFSEL_DIFSEL4_Pos = 0x4
	// Bit mask of DIFSEL4 field.
	ADC_DIFSEL_DIFSEL4_Msk = 0x10
	// Bit DIFSEL4.
	ADC_DIFSEL_DIFSEL4 = 0x10
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL4_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL4_Differential = 0x1
	// Position of DIFSEL5 field.
	ADC_DIFSEL_DIFSEL5_Pos = 0x5
	// Bit mask of DIFSEL5 field.
	ADC_DIFSEL_DIFSEL5_Msk = 0x20
	// Bit DIFSEL5.
	ADC_DIFSEL_DIFSEL5 = 0x20
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL5_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL5_Differential = 0x1
	// Position of DIFSEL6 field.
	ADC_DIFSEL_DIFSEL6_Pos = 0x6
	// Bit mask of DIFSEL6 field.
	ADC_DIFSEL_DIFSEL6_Msk = 0x40
	// Bit DIFSEL6.
	ADC_DIFSEL_DIFSEL6 = 0x40
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL6_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL6_Differential = 0x1
	// Position of DIFSEL7 field.
	ADC_DIFSEL_DIFSEL7_Pos = 0x7
	// Bit mask of DIFSEL7 field.
	ADC_DIFSEL_DIFSEL7_Msk = 0x80
	// Bit DIFSEL7.
	ADC_DIFSEL_DIFSEL7 = 0x80
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL7_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL7_Differential = 0x1
	// Position of DIFSEL8 field.
	ADC_DIFSEL_DIFSEL8_Pos = 0x8
	// Bit mask of DIFSEL8 field.
	ADC_DIFSEL_DIFSEL8_Msk = 0x100
	// Bit DIFSEL8.
	ADC_DIFSEL_DIFSEL8 = 0x100
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL8_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL8_Differential = 0x1
	// Position of DIFSEL9 field.
	ADC_DIFSEL_DIFSEL9_Pos = 0x9
	// Bit mask of DIFSEL9 field.
	ADC_DIFSEL_DIFSEL9_Msk = 0x200
	// Bit DIFSEL9.
	ADC_DIFSEL_DIFSEL9 = 0x200
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL9_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL9_Differential = 0x1
	// Position of DIFSEL10 field.
	ADC_DIFSEL_DIFSEL10_Pos = 0xa
	// Bit mask of DIFSEL10 field.
	ADC_DIFSEL_DIFSEL10_Msk = 0x400
	// Bit DIFSEL10.
	ADC_DIFSEL_DIFSEL10 = 0x400
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL10_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL10_Differential = 0x1
	// Position of DIFSEL11 field.
	ADC_DIFSEL_DIFSEL11_Pos = 0xb
	// Bit mask of DIFSEL11 field.
	ADC_DIFSEL_DIFSEL11_Msk = 0x800
	// Bit DIFSEL11.
	ADC_DIFSEL_DIFSEL11 = 0x800
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL11_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL11_Differential = 0x1
	// Position of DIFSEL12 field.
	ADC_DIFSEL_DIFSEL12_Pos = 0xc
	// Bit mask of DIFSEL12 field.
	ADC_DIFSEL_DIFSEL12_Msk = 0x1000
	// Bit DIFSEL12.
	ADC_DIFSEL_DIFSEL12 = 0x1000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL12_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL12_Differential = 0x1
	// Position of DIFSEL13 field.
	ADC_DIFSEL_DIFSEL13_Pos = 0xd
	// Bit mask of DIFSEL13 field.
	ADC_DIFSEL_DIFSEL13_Msk = 0x2000
	// Bit DIFSEL13.
	ADC_DIFSEL_DIFSEL13 = 0x2000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL13_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL13_Differential = 0x1
	// Position of DIFSEL14 field.
	ADC_DIFSEL_DIFSEL14_Pos = 0xe
	// Bit mask of DIFSEL14 field.
	ADC_DIFSEL_DIFSEL14_Msk = 0x4000
	// Bit DIFSEL14.
	ADC_DIFSEL_DIFSEL14 = 0x4000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL14_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL14_Differential = 0x1
	// Position of DIFSEL15 field.
	ADC_DIFSEL_DIFSEL15_Pos = 0xf
	// Bit mask of DIFSEL15 field.
	ADC_DIFSEL_DIFSEL15_Msk = 0x8000
	// Bit DIFSEL15.
	ADC_DIFSEL_DIFSEL15 = 0x8000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL15_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL15_Differential = 0x1
	// Position of DIFSEL16 field.
	ADC_DIFSEL_DIFSEL16_Pos = 0x10
	// Bit mask of DIFSEL16 field.
	ADC_DIFSEL_DIFSEL16_Msk = 0x10000
	// Bit DIFSEL16.
	ADC_DIFSEL_DIFSEL16 = 0x10000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL16_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL16_Differential = 0x1
	// Position of DIFSEL17 field.
	ADC_DIFSEL_DIFSEL17_Pos = 0x11
	// Bit mask of DIFSEL17 field.
	ADC_DIFSEL_DIFSEL17_Msk = 0x20000
	// Bit DIFSEL17.
	ADC_DIFSEL_DIFSEL17 = 0x20000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL17_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL17_Differential = 0x1
	// Position of DIFSEL18 field.
	ADC_DIFSEL_DIFSEL18_Pos = 0x12
	// Bit mask of DIFSEL18 field.
	ADC_DIFSEL_DIFSEL18_Msk = 0x40000
	// Bit DIFSEL18.
	ADC_DIFSEL_DIFSEL18 = 0x40000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL18_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL18_Differential = 0x1
	// Position of DIFSEL19 field.
	ADC_DIFSEL_DIFSEL19_Pos = 0x13
	// Bit mask of DIFSEL19 field.
	ADC_DIFSEL_DIFSEL19_Msk = 0x80000
	// Bit DIFSEL19.
	ADC_DIFSEL_DIFSEL19 = 0x80000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL19_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL19_Differential = 0x1

	// CALFACT: ADC calibration factors register
	// Position of CALFACT_D field.
	ADC_CALFACT_CALFACT_D_Pos = 0x10
	// Bit mask of CALFACT_D field.
	ADC_CALFACT_CALFACT_D_Msk = 0x7ff0000
	// Position of CALFACT_S field.
	ADC_CALFACT_CALFACT_S_Pos = 0x0
	// Bit mask of CALFACT_S field.
	ADC_CALFACT_CALFACT_S_Msk = 0x7ff

	// CALFACT2: ADC Calibration Factor register 2
	// Position of LINCALFACT field.
	ADC_CALFACT2_LINCALFACT_Pos = 0x0
	// Bit mask of LINCALFACT field.
	ADC_CALFACT2_LINCALFACT_Msk = 0x3fffffff
)

// Bitfields for CRC: Cryptographic processor
const (
	// DR: Data register
	// Position of DR field.
	CRC_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	CRC_DR_DR_Msk = 0xffffffff

	// DR8: Data register - byte sized
	// Position of DR8 field.
	CRC_DR8_DR8_Pos = 0x0
	// Bit mask of DR8 field.
	CRC_DR8_DR8_Msk = 0xff

	// DR16: Data register - half-word sized
	// Position of DR16 field.
	CRC_DR16_DR16_Pos = 0x0
	// Bit mask of DR16 field.
	CRC_DR16_DR16_Msk = 0xffff

	// IDR: Independent Data register
	// Position of IDR field.
	CRC_IDR_IDR_Pos = 0x0
	// Bit mask of IDR field.
	CRC_IDR_IDR_Msk = 0xffffffff

	// CR: Control register
	// Position of RESET field.
	CRC_CR_RESET_Pos = 0x0
	// Bit mask of RESET field.
	CRC_CR_RESET_Msk = 0x1
	// Bit RESET.
	CRC_CR_RESET = 0x1
	// Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
	CRC_CR_RESET_Reset = 0x1
	// Position of POLYSIZE field.
	CRC_CR_POLYSIZE_Pos = 0x3
	// Bit mask of POLYSIZE field.
	CRC_CR_POLYSIZE_Msk = 0x18
	// 32-bit polynomial
	CRC_CR_POLYSIZE_Polysize32 = 0x0
	// 16-bit polynomial
	CRC_CR_POLYSIZE_Polysize16 = 0x1
	// 8-bit polynomial
	CRC_CR_POLYSIZE_Polysize8 = 0x2
	// 7-bit polynomial
	CRC_CR_POLYSIZE_Polysize7 = 0x3
	// Position of REV_IN field.
	CRC_CR_REV_IN_Pos = 0x5
	// Bit mask of REV_IN field.
	CRC_CR_REV_IN_Msk = 0x60
	// Bit order not affected
	CRC_CR_REV_IN_Normal = 0x0
	// Bit reversal done by byte
	CRC_CR_REV_IN_Byte = 0x1
	// Bit reversal done by half-word
	CRC_CR_REV_IN_HalfWord = 0x2
	// Bit reversal done by word
	CRC_CR_REV_IN_Word = 0x3
	// Position of REV_OUT field.
	CRC_CR_REV_OUT_Pos = 0x7
	// Bit mask of REV_OUT field.
	CRC_CR_REV_OUT_Msk = 0x80
	// Bit REV_OUT.
	CRC_CR_REV_OUT = 0x80
	// Bit order not affected
	CRC_CR_REV_OUT_Normal = 0x0
	// Bit reversed output
	CRC_CR_REV_OUT_Reversed = 0x1

	// INIT: Initial CRC value
	// Position of INIT field.
	CRC_INIT_INIT_Pos = 0x0
	// Bit mask of INIT field.
	CRC_INIT_INIT_Msk = 0xffffffff

	// POL: CRC polynomial
	// Position of POL field.
	CRC_POL_POL_Pos = 0x0
	// Bit mask of POL field.
	CRC_POL_POL_Msk = 0xffffffff
)

// Bitfields for RCC: Reset and clock control
const (
	// CR: clock control register
	// Position of HSION field.
	RCC_CR_HSION_Pos = 0x0
	// Bit mask of HSION field.
	RCC_CR_HSION_Msk = 0x1
	// Bit HSION.
	RCC_CR_HSION = 0x1
	// Clock Off
	RCC_CR_HSION_Off = 0x0
	// Clock On
	RCC_CR_HSION_On = 0x1
	// Position of HSIKERON field.
	RCC_CR_HSIKERON_Pos = 0x1
	// Bit mask of HSIKERON field.
	RCC_CR_HSIKERON_Msk = 0x2
	// Bit HSIKERON.
	RCC_CR_HSIKERON = 0x2
	// Clock Off
	RCC_CR_HSIKERON_Off = 0x0
	// Clock On
	RCC_CR_HSIKERON_On = 0x1
	// Position of HSIRDY field.
	RCC_CR_HSIRDY_Pos = 0x2
	// Bit mask of HSIRDY field.
	RCC_CR_HSIRDY_Msk = 0x4
	// Bit HSIRDY.
	RCC_CR_HSIRDY = 0x4
	// Clock not ready
	RCC_CR_HSIRDY_NotReady = 0x0
	// Clock ready
	RCC_CR_HSIRDY_Ready = 0x1
	// Position of HSIDIV field.
	RCC_CR_HSIDIV_Pos = 0x3
	// Bit mask of HSIDIV field.
	RCC_CR_HSIDIV_Msk = 0x18
	// No division
	RCC_CR_HSIDIV_Div1 = 0x0
	// Division by 2
	RCC_CR_HSIDIV_Div2 = 0x1
	// Division by 4
	RCC_CR_HSIDIV_Div4 = 0x2
	// Division by 8
	RCC_CR_HSIDIV_Div8 = 0x3
	// Position of HSIDIVF field.
	RCC_CR_HSIDIVF_Pos = 0x5
	// Bit mask of HSIDIVF field.
	RCC_CR_HSIDIVF_Msk = 0x20
	// Bit HSIDIVF.
	RCC_CR_HSIDIVF = 0x20
	// New HSIDIV ratio has not yet propagated to hsi_ck
	RCC_CR_HSIDIVF_NotPropagated = 0x0
	// HSIDIV ratio has propagated to hsi_ck
	RCC_CR_HSIDIVF_Propagated = 0x1
	// Position of CSION field.
	RCC_CR_CSION_Pos = 0x7
	// Bit mask of CSION field.
	RCC_CR_CSION_Msk = 0x80
	// Bit CSION.
	RCC_CR_CSION = 0x80
	// Clock Off
	RCC_CR_CSION_Off = 0x0
	// Clock On
	RCC_CR_CSION_On = 0x1
	// Position of CSIRDY field.
	RCC_CR_CSIRDY_Pos = 0x8
	// Bit mask of CSIRDY field.
	RCC_CR_CSIRDY_Msk = 0x100
	// Bit CSIRDY.
	RCC_CR_CSIRDY = 0x100
	// Clock not ready
	RCC_CR_CSIRDY_NotReady = 0x0
	// Clock ready
	RCC_CR_CSIRDY_Ready = 0x1
	// Position of CSIKERON field.
	RCC_CR_CSIKERON_Pos = 0x9
	// Bit mask of CSIKERON field.
	RCC_CR_CSIKERON_Msk = 0x200
	// Bit CSIKERON.
	RCC_CR_CSIKERON = 0x200
	// Clock Off
	RCC_CR_CSIKERON_Off = 0x0
	// Clock On
	RCC_CR_CSIKERON_On = 0x1
	// Position of HSI48ON field.
	RCC_CR_HSI48ON_Pos = 0xc
	// Bit mask of HSI48ON field.
	RCC_CR_HSI48ON_Msk = 0x1000
	// Bit HSI48ON.
	RCC_CR_HSI48ON = 0x1000
	// Clock Off
	RCC_CR_HSI48ON_Off = 0x0
	// Clock On
	RCC_CR_HSI48ON_On = 0x1
	// Position of HSI48RDY field.
	RCC_CR_HSI48RDY_Pos = 0xd
	// Bit mask of HSI48RDY field.
	RCC_CR_HSI48RDY_Msk = 0x2000
	// Bit HSI48RDY.
	RCC_CR_HSI48RDY = 0x2000
	// Clock not ready
	RCC_CR_HSI48RDY_NotReady = 0x0
	// Clock ready
	RCC_CR_HSI48RDY_Ready = 0x1
	// Position of D1CKRDY field.
	RCC_CR_D1CKRDY_Pos = 0xe
	// Bit mask of D1CKRDY field.
	RCC_CR_D1CKRDY_Msk = 0x4000
	// Bit D1CKRDY.
	RCC_CR_D1CKRDY = 0x4000
	// Clock not ready
	RCC_CR_D1CKRDY_NotReady = 0x0
	// Clock ready
	RCC_CR_D1CKRDY_Ready = 0x1
	// Position of D2CKRDY field.
	RCC_CR_D2CKRDY_Pos = 0xf
	// Bit mask of D2CKRDY field.
	RCC_CR_D2CKRDY_Msk = 0x8000
	// Bit D2CKRDY.
	RCC_CR_D2CKRDY = 0x8000
	// Clock not ready
	RCC_CR_D2CKRDY_NotReady = 0x0
	// Clock ready
	RCC_CR_D2CKRDY_Ready = 0x1
	// Position of HSEON field.
	RCC_CR_HSEON_Pos = 0x10
	// Bit mask of HSEON field.
	RCC_CR_HSEON_Msk = 0x10000
	// Bit HSEON.
	RCC_CR_HSEON = 0x10000
	// Clock Off
	RCC_CR_HSEON_Off = 0x0
	// Clock On
	RCC_CR_HSEON_On = 0x1
	// Position of HSERDY field.
	RCC_CR_HSERDY_Pos = 0x11
	// Bit mask of HSERDY field.
	RCC_CR_HSERDY_Msk = 0x20000
	// Bit HSERDY.
	RCC_CR_HSERDY = 0x20000
	// Clock not ready
	RCC_CR_HSERDY_NotReady = 0x0
	// Clock ready
	RCC_CR_HSERDY_Ready = 0x1
	// Position of HSEBYP field.
	RCC_CR_HSEBYP_Pos = 0x12
	// Bit mask of HSEBYP field.
	RCC_CR_HSEBYP_Msk = 0x40000
	// Bit HSEBYP.
	RCC_CR_HSEBYP = 0x40000
	// HSE crystal oscillator not bypassed
	RCC_CR_HSEBYP_NotBypassed = 0x0
	// HSE crystal oscillator bypassed with external clock
	RCC_CR_HSEBYP_Bypassed = 0x1
	// Position of HSECSSON field.
	RCC_CR_HSECSSON_Pos = 0x13
	// Bit mask of HSECSSON field.
	RCC_CR_HSECSSON_Msk = 0x80000
	// Bit HSECSSON.
	RCC_CR_HSECSSON = 0x80000
	// Clock Off
	RCC_CR_HSECSSON_Off = 0x0
	// Clock On
	RCC_CR_HSECSSON_On = 0x1
	// Position of PLL1ON field.
	RCC_CR_PLL1ON_Pos = 0x18
	// Bit mask of PLL1ON field.
	RCC_CR_PLL1ON_Msk = 0x1000000
	// Bit PLL1ON.
	RCC_CR_PLL1ON = 0x1000000
	// Clock Off
	RCC_CR_PLL1ON_Off = 0x0
	// Clock On
	RCC_CR_PLL1ON_On = 0x1
	// Position of PLL1RDY field.
	RCC_CR_PLL1RDY_Pos = 0x19
	// Bit mask of PLL1RDY field.
	RCC_CR_PLL1RDY_Msk = 0x2000000
	// Bit PLL1RDY.
	RCC_CR_PLL1RDY = 0x2000000
	// Clock not ready
	RCC_CR_PLL1RDY_NotReady = 0x0
	// Clock ready
	RCC_CR_PLL1RDY_Ready = 0x1
	// Position of PLL2ON field.
	RCC_CR_PLL2ON_Pos = 0x1a
	// Bit mask of PLL2ON field.
	RCC_CR_PLL2ON_Msk = 0x4000000
	// Bit PLL2ON.
	RCC_CR_PLL2ON = 0x4000000
	// Clock Off
	RCC_CR_PLL2ON_Off = 0x0
	// Clock On
	RCC_CR_PLL2ON_On = 0x1
	// Position of PLL2RDY field.
	RCC_CR_PLL2RDY_Pos = 0x1b
	// Bit mask of PLL2RDY field.
	RCC_CR_PLL2RDY_Msk = 0x8000000
	// Bit PLL2RDY.
	RCC_CR_PLL2RDY = 0x8000000
	// Clock not ready
	RCC_CR_PLL2RDY_NotReady = 0x0
	// Clock ready
	RCC_CR_PLL2RDY_Ready = 0x1
	// Position of PLL3ON field.
	RCC_CR_PLL3ON_Pos = 0x1c
	// Bit mask of PLL3ON field.
	RCC_CR_PLL3ON_Msk = 0x10000000
	// Bit PLL3ON.
	RCC_CR_PLL3ON = 0x10000000
	// Clock Off
	RCC_CR_PLL3ON_Off = 0x0
	// Clock On
	RCC_CR_PLL3ON_On = 0x1
	// Position of PLL3RDY field.
	RCC_CR_PLL3RDY_Pos = 0x1d
	// Bit mask of PLL3RDY field.
	RCC_CR_PLL3RDY_Msk = 0x20000000
	// Bit PLL3RDY.
	RCC_CR_PLL3RDY = 0x20000000
	// Clock not ready
	RCC_CR_PLL3RDY_NotReady = 0x0
	// Clock ready
	RCC_CR_PLL3RDY_Ready = 0x1

	// ICSCR: RCC Internal Clock Source Calibration Register
	// Position of HSICAL field.
	RCC_ICSCR_HSICAL_Pos = 0x0
	// Bit mask of HSICAL field.
	RCC_ICSCR_HSICAL_Msk = 0xfff
	// Position of HSITRIM field.
	RCC_ICSCR_HSITRIM_Pos = 0xc
	// Bit mask of HSITRIM field.
	RCC_ICSCR_HSITRIM_Msk = 0x3f000
	// Position of CSICAL field.
	RCC_ICSCR_CSICAL_Pos = 0x12
	// Bit mask of CSICAL field.
	RCC_ICSCR_CSICAL_Msk = 0x3fc0000
	// Position of CSITRIM field.
	RCC_ICSCR_CSITRIM_Pos = 0x1a
	// Bit mask of CSITRIM field.
	RCC_ICSCR_CSITRIM_Msk = 0x7c000000

	// HSICFGR: RCC HSI configuration register
	// Position of HSITRIM field.
	RCC_HSICFGR_HSITRIM_Pos = 0x18
	// Bit mask of HSITRIM field.
	RCC_HSICFGR_HSITRIM_Msk = 0x7f000000
	// Position of HSICAL field.
	RCC_HSICFGR_HSICAL_Pos = 0x0
	// Bit mask of HSICAL field.
	RCC_HSICFGR_HSICAL_Msk = 0xfff

	// CRRCR: RCC Clock Recovery RC Register
	// Position of HSI48CAL field.
	RCC_CRRCR_HSI48CAL_Pos = 0x0
	// Bit mask of HSI48CAL field.
	RCC_CRRCR_HSI48CAL_Msk = 0x3ff

	// CSICFGR: RCC CSI configuration register
	// Position of CSITRIM field.
	RCC_CSICFGR_CSITRIM_Pos = 0x18
	// Bit mask of CSITRIM field.
	RCC_CSICFGR_CSITRIM_Msk = 0x3f000000
	// Position of CSICAL field.
	RCC_CSICFGR_CSICAL_Pos = 0x0
	// Bit mask of CSICAL field.
	RCC_CSICFGR_CSICAL_Msk = 0x1ff

	// CFGR: RCC Clock Configuration Register
	// Position of SW field.
	RCC_CFGR_SW_Pos = 0x0
	// Bit mask of SW field.
	RCC_CFGR_SW_Msk = 0x7
	// HSI selected as system clock
	RCC_CFGR_SW_HSI = 0x0
	// CSI selected as system clock
	RCC_CFGR_SW_CSI = 0x1
	// HSE selected as system clock
	RCC_CFGR_SW_HSE = 0x2
	// PLL1 selected as system clock
	RCC_CFGR_SW_PLL1 = 0x3
	// Position of SWS field.
	RCC_CFGR_SWS_Pos = 0x3
	// Bit mask of SWS field.
	RCC_CFGR_SWS_Msk = 0x38
	// HSI oscillator used as system clock
	RCC_CFGR_SWS_HSI = 0x0
	// CSI oscillator used as system clock
	RCC_CFGR_SWS_CSI = 0x1
	// HSE oscillator used as system clock
	RCC_CFGR_SWS_HSE = 0x2
	// PLL1 used as system clock
	RCC_CFGR_SWS_PLL1 = 0x3
	// Position of STOPWUCK field.
	RCC_CFGR_STOPWUCK_Pos = 0x6
	// Bit mask of STOPWUCK field.
	RCC_CFGR_STOPWUCK_Msk = 0x40
	// Bit STOPWUCK.
	RCC_CFGR_STOPWUCK = 0x40
	// HSI selected as wake up clock from system Stop
	RCC_CFGR_STOPWUCK_HSI = 0x0
	// CSI selected as wake up clock from system Stop
	RCC_CFGR_STOPWUCK_CSI = 0x1
	// Position of STOPKERWUCK field.
	RCC_CFGR_STOPKERWUCK_Pos = 0x7
	// Bit mask of STOPKERWUCK field.
	RCC_CFGR_STOPKERWUCK_Msk = 0x80
	// Bit STOPKERWUCK.
	RCC_CFGR_STOPKERWUCK = 0x80
	// HSI selected as wake up clock from system Stop
	RCC_CFGR_STOPKERWUCK_HSI = 0x0
	// CSI selected as wake up clock from system Stop
	RCC_CFGR_STOPKERWUCK_CSI = 0x1
	// Position of RTCPRE field.
	RCC_CFGR_RTCPRE_Pos = 0x8
	// Bit mask of RTCPRE field.
	RCC_CFGR_RTCPRE_Msk = 0x3f00
	// Position of HRTIMSEL field.
	RCC_CFGR_HRTIMSEL_Pos = 0xe
	// Bit mask of HRTIMSEL field.
	RCC_CFGR_HRTIMSEL_Msk = 0x4000
	// Bit HRTIMSEL.
	RCC_CFGR_HRTIMSEL = 0x4000
	// The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)
	RCC_CFGR_HRTIMSEL_TIMY_KER = 0x0
	// The HRTIM prescaler clock source is the CPU clock (c_ck)
	RCC_CFGR_HRTIMSEL_C_CK = 0x1
	// Position of TIMPRE field.
	RCC_CFGR_TIMPRE_Pos = 0xf
	// Bit mask of TIMPRE field.
	RCC_CFGR_TIMPRE_Msk = 0x8000
	// Bit TIMPRE.
	RCC_CFGR_TIMPRE = 0x8000
	// Timer kernel clock equal to 2x pclk by default
	RCC_CFGR_TIMPRE_DefaultX2 = 0x0
	// Timer kernel clock equal to 4x pclk by default
	RCC_CFGR_TIMPRE_DefaultX4 = 0x1
	// Position of MCO1PRE field.
	RCC_CFGR_MCO1PRE_Pos = 0x12
	// Bit mask of MCO1PRE field.
	RCC_CFGR_MCO1PRE_Msk = 0x3c0000
	// Position of MCO1 field.
	RCC_CFGR_MCO1_Pos = 0x16
	// Bit mask of MCO1 field.
	RCC_CFGR_MCO1_Msk = 0x1c00000
	// HSI selected for micro-controller clock output
	RCC_CFGR_MCO1_HSI = 0x0
	// LSE selected for micro-controller clock output
	RCC_CFGR_MCO1_LSE = 0x1
	// HSE selected for micro-controller clock output
	RCC_CFGR_MCO1_HSE = 0x2
	// pll1_q selected for micro-controller clock output
	RCC_CFGR_MCO1_PLL1_Q = 0x3
	// HSI48 selected for micro-controller clock output
	RCC_CFGR_MCO1_HSI48 = 0x4
	// Position of MCO2PRE field.
	RCC_CFGR_MCO2PRE_Pos = 0x19
	// Bit mask of MCO2PRE field.
	RCC_CFGR_MCO2PRE_Msk = 0x1e000000
	// Position of MCO2 field.
	RCC_CFGR_MCO2_Pos = 0x1d
	// Bit mask of MCO2 field.
	RCC_CFGR_MCO2_Msk = 0xe0000000
	// System clock selected for micro-controller clock output
	RCC_CFGR_MCO2_SYSCLK = 0x0
	// pll2_p selected for micro-controller clock output
	RCC_CFGR_MCO2_PLL2_P = 0x1
	// HSE selected for micro-controller clock output
	RCC_CFGR_MCO2_HSE = 0x2
	// pll1_p selected for micro-controller clock output
	RCC_CFGR_MCO2_PLL1_P = 0x3
	// CSI selected for micro-controller clock output
	RCC_CFGR_MCO2_CSI = 0x4
	// LSI selected for micro-controller clock output
	RCC_CFGR_MCO2_LSI = 0x5

	// D1CFGR: RCC Domain 1 Clock Configuration Register
	// Position of HPRE field.
	RCC_D1CFGR_HPRE_Pos = 0x0
	// Bit mask of HPRE field.
	RCC_D1CFGR_HPRE_Msk = 0xf
	// sys_ck not divided
	RCC_D1CFGR_HPRE_Div1 = 0x0
	// sys_ck divided by 2
	RCC_D1CFGR_HPRE_Div2 = 0x8
	// sys_ck divided by 4
	RCC_D1CFGR_HPRE_Div4 = 0x9
	// sys_ck divided by 8
	RCC_D1CFGR_HPRE_Div8 = 0xa
	// sys_ck divided by 16
	RCC_D1CFGR_HPRE_Div16 = 0xb
	// sys_ck divided by 64
	RCC_D1CFGR_HPRE_Div64 = 0xc
	// sys_ck divided by 128
	RCC_D1CFGR_HPRE_Div128 = 0xd
	// sys_ck divided by 256
	RCC_D1CFGR_HPRE_Div256 = 0xe
	// sys_ck divided by 512
	RCC_D1CFGR_HPRE_Div512 = 0xf
	// Position of D1PPRE field.
	RCC_D1CFGR_D1PPRE_Pos = 0x4
	// Bit mask of D1PPRE field.
	RCC_D1CFGR_D1PPRE_Msk = 0x70
	// rcc_hclk not divided
	RCC_D1CFGR_D1PPRE_Div1 = 0x0
	// rcc_hclk divided by 2
	RCC_D1CFGR_D1PPRE_Div2 = 0x4
	// rcc_hclk divided by 4
	RCC_D1CFGR_D1PPRE_Div4 = 0x5
	// rcc_hclk divided by 8
	RCC_D1CFGR_D1PPRE_Div8 = 0x6
	// rcc_hclk divided by 16
	RCC_D1CFGR_D1PPRE_Div16 = 0x7
	// Position of D1CPRE field.
	RCC_D1CFGR_D1CPRE_Pos = 0x8
	// Bit mask of D1CPRE field.
	RCC_D1CFGR_D1CPRE_Msk = 0xf00
	// sys_ck not divided
	RCC_D1CFGR_D1CPRE_Div1 = 0x0
	// sys_ck divided by 2
	RCC_D1CFGR_D1CPRE_Div2 = 0x8
	// sys_ck divided by 4
	RCC_D1CFGR_D1CPRE_Div4 = 0x9
	// sys_ck divided by 8
	RCC_D1CFGR_D1CPRE_Div8 = 0xa
	// sys_ck divided by 16
	RCC_D1CFGR_D1CPRE_Div16 = 0xb
	// sys_ck divided by 64
	RCC_D1CFGR_D1CPRE_Div64 = 0xc
	// sys_ck divided by 128
	RCC_D1CFGR_D1CPRE_Div128 = 0xd
	// sys_ck divided by 256
	RCC_D1CFGR_D1CPRE_Div256 = 0xe
	// sys_ck divided by 512
	RCC_D1CFGR_D1CPRE_Div512 = 0xf

	// D2CFGR: RCC Domain 2 Clock Configuration Register
	// Position of D2PPRE1 field.
	RCC_D2CFGR_D2PPRE1_Pos = 0x4
	// Bit mask of D2PPRE1 field.
	RCC_D2CFGR_D2PPRE1_Msk = 0x70
	// rcc_hclk not divided
	RCC_D2CFGR_D2PPRE1_Div1 = 0x0
	// rcc_hclk divided by 2
	RCC_D2CFGR_D2PPRE1_Div2 = 0x4
	// rcc_hclk divided by 4
	RCC_D2CFGR_D2PPRE1_Div4 = 0x5
	// rcc_hclk divided by 8
	RCC_D2CFGR_D2PPRE1_Div8 = 0x6
	// rcc_hclk divided by 16
	RCC_D2CFGR_D2PPRE1_Div16 = 0x7
	// Position of D2PPRE2 field.
	RCC_D2CFGR_D2PPRE2_Pos = 0x8
	// Bit mask of D2PPRE2 field.
	RCC_D2CFGR_D2PPRE2_Msk = 0x700
	// rcc_hclk not divided
	RCC_D2CFGR_D2PPRE2_Div1 = 0x0
	// rcc_hclk divided by 2
	RCC_D2CFGR_D2PPRE2_Div2 = 0x4
	// rcc_hclk divided by 4
	RCC_D2CFGR_D2PPRE2_Div4 = 0x5
	// rcc_hclk divided by 8
	RCC_D2CFGR_D2PPRE2_Div8 = 0x6
	// rcc_hclk divided by 16
	RCC_D2CFGR_D2PPRE2_Div16 = 0x7

	// D3CFGR: RCC Domain 3 Clock Configuration Register
	// Position of D3PPRE field.
	RCC_D3CFGR_D3PPRE_Pos = 0x4
	// Bit mask of D3PPRE field.
	RCC_D3CFGR_D3PPRE_Msk = 0x70
	// rcc_hclk not divided
	RCC_D3CFGR_D3PPRE_Div1 = 0x0
	// rcc_hclk divided by 2
	RCC_D3CFGR_D3PPRE_Div2 = 0x4
	// rcc_hclk divided by 4
	RCC_D3CFGR_D3PPRE_Div4 = 0x5
	// rcc_hclk divided by 8
	RCC_D3CFGR_D3PPRE_Div8 = 0x6
	// rcc_hclk divided by 16
	RCC_D3CFGR_D3PPRE_Div16 = 0x7

	// PLLCKSELR: RCC PLLs Clock Source Selection Register
	// Position of PLLSRC field.
	RCC_PLLCKSELR_PLLSRC_Pos = 0x0
	// Bit mask of PLLSRC field.
	RCC_PLLCKSELR_PLLSRC_Msk = 0x3
	// HSI selected as PLL clock
	RCC_PLLCKSELR_PLLSRC_HSI = 0x0
	// CSI selected as PLL clock
	RCC_PLLCKSELR_PLLSRC_CSI = 0x1
	// HSE selected as PLL clock
	RCC_PLLCKSELR_PLLSRC_HSE = 0x2
	// No clock sent to DIVMx dividers and PLLs
	RCC_PLLCKSELR_PLLSRC_None = 0x3
	// Position of DIVM1 field.
	RCC_PLLCKSELR_DIVM1_Pos = 0x4
	// Bit mask of DIVM1 field.
	RCC_PLLCKSELR_DIVM1_Msk = 0x3f0
	// Position of DIVM2 field.
	RCC_PLLCKSELR_DIVM2_Pos = 0xc
	// Bit mask of DIVM2 field.
	RCC_PLLCKSELR_DIVM2_Msk = 0x3f000
	// Position of DIVM3 field.
	RCC_PLLCKSELR_DIVM3_Pos = 0x14
	// Bit mask of DIVM3 field.
	RCC_PLLCKSELR_DIVM3_Msk = 0x3f00000

	// PLLCFGR: RCC PLLs Configuration Register
	// Position of PLL1FRACEN field.
	RCC_PLLCFGR_PLL1FRACEN_Pos = 0x0
	// Bit mask of PLL1FRACEN field.
	RCC_PLLCFGR_PLL1FRACEN_Msk = 0x1
	// Bit PLL1FRACEN.
	RCC_PLLCFGR_PLL1FRACEN = 0x1
	// Reset latch to tranfer FRACN to the Sigma-Delta modulator
	RCC_PLLCFGR_PLL1FRACEN_Reset = 0x0
	// Set latch to tranfer FRACN to the Sigma-Delta modulator
	RCC_PLLCFGR_PLL1FRACEN_Set = 0x1
	// Position of PLL1VCOSEL field.
	RCC_PLLCFGR_PLL1VCOSEL_Pos = 0x1
	// Bit mask of PLL1VCOSEL field.
	RCC_PLLCFGR_PLL1VCOSEL_Msk = 0x2
	// Bit PLL1VCOSEL.
	RCC_PLLCFGR_PLL1VCOSEL = 0x2
	// VCO frequency range 192 to 836 MHz
	RCC_PLLCFGR_PLL1VCOSEL_WideVCO = 0x0
	// VCO frequency range 150 to 420 MHz
	RCC_PLLCFGR_PLL1VCOSEL_MediumVCO = 0x1
	// Position of PLL1RGE field.
	RCC_PLLCFGR_PLL1RGE_Pos = 0x2
	// Bit mask of PLL1RGE field.
	RCC_PLLCFGR_PLL1RGE_Msk = 0xc
	// Frequency is between 1 and 2 MHz
	RCC_PLLCFGR_PLL1RGE_Range1 = 0x0
	// Frequency is between 2 and 4 MHz
	RCC_PLLCFGR_PLL1RGE_Range2 = 0x1
	// Frequency is between 4 and 8 MHz
	RCC_PLLCFGR_PLL1RGE_Range4 = 0x2
	// Frequency is between 8 and 16 MHz
	RCC_PLLCFGR_PLL1RGE_Range8 = 0x3
	// Position of PLL2FRACEN field.
	RCC_PLLCFGR_PLL2FRACEN_Pos = 0x4
	// Bit mask of PLL2FRACEN field.
	RCC_PLLCFGR_PLL2FRACEN_Msk = 0x10
	// Bit PLL2FRACEN.
	RCC_PLLCFGR_PLL2FRACEN = 0x10
	// Reset latch to tranfer FRACN to the Sigma-Delta modulator
	RCC_PLLCFGR_PLL2FRACEN_Reset = 0x0
	// Set latch to tranfer FRACN to the Sigma-Delta modulator
	RCC_PLLCFGR_PLL2FRACEN_Set = 0x1
	// Position of PLL2VCOSEL field.
	RCC_PLLCFGR_PLL2VCOSEL_Pos = 0x5
	// Bit mask of PLL2VCOSEL field.
	RCC_PLLCFGR_PLL2VCOSEL_Msk = 0x20
	// Bit PLL2VCOSEL.
	RCC_PLLCFGR_PLL2VCOSEL = 0x20
	// VCO frequency range 192 to 836 MHz
	RCC_PLLCFGR_PLL2VCOSEL_WideVCO = 0x0
	// VCO frequency range 150 to 420 MHz
	RCC_PLLCFGR_PLL2VCOSEL_MediumVCO = 0x1
	// Position of PLL2RGE field.
	RCC_PLLCFGR_PLL2RGE_Pos = 0x6
	// Bit mask of PLL2RGE field.
	RCC_PLLCFGR_PLL2RGE_Msk = 0xc0
	// Frequency is between 1 and 2 MHz
	RCC_PLLCFGR_PLL2RGE_Range1 = 0x0
	// Frequency is between 2 and 4 MHz
	RCC_PLLCFGR_PLL2RGE_Range2 = 0x1
	// Frequency is between 4 and 8 MHz
	RCC_PLLCFGR_PLL2RGE_Range4 = 0x2
	// Frequency is between 8 and 16 MHz
	RCC_PLLCFGR_PLL2RGE_Range8 = 0x3
	// Position of PLL3FRACEN field.
	RCC_PLLCFGR_PLL3FRACEN_Pos = 0x8
	// Bit mask of PLL3FRACEN field.
	RCC_PLLCFGR_PLL3FRACEN_Msk = 0x100
	// Bit PLL3FRACEN.
	RCC_PLLCFGR_PLL3FRACEN = 0x100
	// Reset latch to tranfer FRACN to the Sigma-Delta modulator
	RCC_PLLCFGR_PLL3FRACEN_Reset = 0x0
	// Set latch to tranfer FRACN to the Sigma-Delta modulator
	RCC_PLLCFGR_PLL3FRACEN_Set = 0x1
	// Position of PLL3VCOSEL field.
	RCC_PLLCFGR_PLL3VCOSEL_Pos = 0x9
	// Bit mask of PLL3VCOSEL field.
	RCC_PLLCFGR_PLL3VCOSEL_Msk = 0x200
	// Bit PLL3VCOSEL.
	RCC_PLLCFGR_PLL3VCOSEL = 0x200
	// VCO frequency range 192 to 836 MHz
	RCC_PLLCFGR_PLL3VCOSEL_WideVCO = 0x0
	// VCO frequency range 150 to 420 MHz
	RCC_PLLCFGR_PLL3VCOSEL_MediumVCO = 0x1
	// Position of PLL3RGE field.
	RCC_PLLCFGR_PLL3RGE_Pos = 0xa
	// Bit mask of PLL3RGE field.
	RCC_PLLCFGR_PLL3RGE_Msk = 0xc00
	// Frequency is between 1 and 2 MHz
	RCC_PLLCFGR_PLL3RGE_Range1 = 0x0
	// Frequency is between 2 and 4 MHz
	RCC_PLLCFGR_PLL3RGE_Range2 = 0x1
	// Frequency is between 4 and 8 MHz
	RCC_PLLCFGR_PLL3RGE_Range4 = 0x2
	// Frequency is between 8 and 16 MHz
	RCC_PLLCFGR_PLL3RGE_Range8 = 0x3
	// Position of DIVP1EN field.
	RCC_PLLCFGR_DIVP1EN_Pos = 0x10
	// Bit mask of DIVP1EN field.
	RCC_PLLCFGR_DIVP1EN_Msk = 0x10000
	// Bit DIVP1EN.
	RCC_PLLCFGR_DIVP1EN = 0x10000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVP1EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVP1EN_Enabled = 0x1
	// Position of DIVQ1EN field.
	RCC_PLLCFGR_DIVQ1EN_Pos = 0x11
	// Bit mask of DIVQ1EN field.
	RCC_PLLCFGR_DIVQ1EN_Msk = 0x20000
	// Bit DIVQ1EN.
	RCC_PLLCFGR_DIVQ1EN = 0x20000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVQ1EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVQ1EN_Enabled = 0x1
	// Position of DIVR1EN field.
	RCC_PLLCFGR_DIVR1EN_Pos = 0x12
	// Bit mask of DIVR1EN field.
	RCC_PLLCFGR_DIVR1EN_Msk = 0x40000
	// Bit DIVR1EN.
	RCC_PLLCFGR_DIVR1EN = 0x40000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVR1EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVR1EN_Enabled = 0x1
	// Position of DIVP2EN field.
	RCC_PLLCFGR_DIVP2EN_Pos = 0x13
	// Bit mask of DIVP2EN field.
	RCC_PLLCFGR_DIVP2EN_Msk = 0x80000
	// Bit DIVP2EN.
	RCC_PLLCFGR_DIVP2EN = 0x80000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVP2EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVP2EN_Enabled = 0x1
	// Position of DIVQ2EN field.
	RCC_PLLCFGR_DIVQ2EN_Pos = 0x14
	// Bit mask of DIVQ2EN field.
	RCC_PLLCFGR_DIVQ2EN_Msk = 0x100000
	// Bit DIVQ2EN.
	RCC_PLLCFGR_DIVQ2EN = 0x100000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVQ2EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVQ2EN_Enabled = 0x1
	// Position of DIVR2EN field.
	RCC_PLLCFGR_DIVR2EN_Pos = 0x15
	// Bit mask of DIVR2EN field.
	RCC_PLLCFGR_DIVR2EN_Msk = 0x200000
	// Bit DIVR2EN.
	RCC_PLLCFGR_DIVR2EN = 0x200000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVR2EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVR2EN_Enabled = 0x1
	// Position of DIVP3EN field.
	RCC_PLLCFGR_DIVP3EN_Pos = 0x16
	// Bit mask of DIVP3EN field.
	RCC_PLLCFGR_DIVP3EN_Msk = 0x400000
	// Bit DIVP3EN.
	RCC_PLLCFGR_DIVP3EN = 0x400000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVP3EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVP3EN_Enabled = 0x1
	// Position of DIVQ3EN field.
	RCC_PLLCFGR_DIVQ3EN_Pos = 0x17
	// Bit mask of DIVQ3EN field.
	RCC_PLLCFGR_DIVQ3EN_Msk = 0x800000
	// Bit DIVQ3EN.
	RCC_PLLCFGR_DIVQ3EN = 0x800000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVQ3EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVQ3EN_Enabled = 0x1
	// Position of DIVR3EN field.
	RCC_PLLCFGR_DIVR3EN_Pos = 0x18
	// Bit mask of DIVR3EN field.
	RCC_PLLCFGR_DIVR3EN_Msk = 0x1000000
	// Bit DIVR3EN.
	RCC_PLLCFGR_DIVR3EN = 0x1000000
	// Clock ouput is disabled
	RCC_PLLCFGR_DIVR3EN_Disabled = 0x0
	// Clock output is enabled
	RCC_PLLCFGR_DIVR3EN_Enabled = 0x1

	// PLL1DIVR: RCC PLL1 Dividers Configuration Register
	// Position of DIVN1 field.
	RCC_PLL1DIVR_DIVN1_Pos = 0x0
	// Bit mask of DIVN1 field.
	RCC_PLL1DIVR_DIVN1_Msk = 0x1ff
	// Position of DIVP1 field.
	RCC_PLL1DIVR_DIVP1_Pos = 0x9
	// Bit mask of DIVP1 field.
	RCC_PLL1DIVR_DIVP1_Msk = 0xfe00
	// pll_p_ck = vco_ck
	RCC_PLL1DIVR_DIVP1_Div1 = 0x0
	// pll_p_ck = vco_ck / 2
	RCC_PLL1DIVR_DIVP1_Div2 = 0x1
	// pll_p_ck = vco_ck / 4
	RCC_PLL1DIVR_DIVP1_Div4 = 0x3
	// pll_p_ck = vco_ck / 6
	RCC_PLL1DIVR_DIVP1_Div6 = 0x5
	// pll_p_ck = vco_ck / 8
	RCC_PLL1DIVR_DIVP1_Div8 = 0x7
	// pll_p_ck = vco_ck / 10
	RCC_PLL1DIVR_DIVP1_Div10 = 0x9
	// pll_p_ck = vco_ck / 12
	RCC_PLL1DIVR_DIVP1_Div12 = 0xb
	// pll_p_ck = vco_ck / 14
	RCC_PLL1DIVR_DIVP1_Div14 = 0xd
	// pll_p_ck = vco_ck / 16
	RCC_PLL1DIVR_DIVP1_Div16 = 0xf
	// pll_p_ck = vco_ck / 18
	RCC_PLL1DIVR_DIVP1_Div18 = 0x11
	// pll_p_ck = vco_ck / 20
	RCC_PLL1DIVR_DIVP1_Div20 = 0x13
	// pll_p_ck = vco_ck / 22
	RCC_PLL1DIVR_DIVP1_Div22 = 0x15
	// pll_p_ck = vco_ck / 24
	RCC_PLL1DIVR_DIVP1_Div24 = 0x17
	// pll_p_ck = vco_ck / 26
	RCC_PLL1DIVR_DIVP1_Div26 = 0x19
	// pll_p_ck = vco_ck / 28
	RCC_PLL1DIVR_DIVP1_Div28 = 0x1b
	// pll_p_ck = vco_ck / 30
	RCC_PLL1DIVR_DIVP1_Div30 = 0x1d
	// pll_p_ck = vco_ck / 32
	RCC_PLL1DIVR_DIVP1_Div32 = 0x1f
	// pll_p_ck = vco_ck / 34
	RCC_PLL1DIVR_DIVP1_Div34 = 0x21
	// pll_p_ck = vco_ck / 36
	RCC_PLL1DIVR_DIVP1_Div36 = 0x23
	// pll_p_ck = vco_ck / 38
	RCC_PLL1DIVR_DIVP1_Div38 = 0x25
	// pll_p_ck = vco_ck / 40
	RCC_PLL1DIVR_DIVP1_Div40 = 0x27
	// pll_p_ck = vco_ck / 42
	RCC_PLL1DIVR_DIVP1_Div42 = 0x29
	// pll_p_ck = vco_ck / 44
	RCC_PLL1DIVR_DIVP1_Div44 = 0x2b
	// pll_p_ck = vco_ck / 46
	RCC_PLL1DIVR_DIVP1_Div46 = 0x2d
	// pll_p_ck = vco_ck / 48
	RCC_PLL1DIVR_DIVP1_Div48 = 0x2f
	// pll_p_ck = vco_ck / 50
	RCC_PLL1DIVR_DIVP1_Div50 = 0x31
	// pll_p_ck = vco_ck / 52
	RCC_PLL1DIVR_DIVP1_Div52 = 0x33
	// pll_p_ck = vco_ck / 54
	RCC_PLL1DIVR_DIVP1_Div54 = 0x35
	// pll_p_ck = vco_ck / 56
	RCC_PLL1DIVR_DIVP1_Div56 = 0x37
	// pll_p_ck = vco_ck / 58
	RCC_PLL1DIVR_DIVP1_Div58 = 0x39
	// pll_p_ck = vco_ck / 60
	RCC_PLL1DIVR_DIVP1_Div60 = 0x3b
	// pll_p_ck = vco_ck / 62
	RCC_PLL1DIVR_DIVP1_Div62 = 0x3d
	// pll_p_ck = vco_ck / 64
	RCC_PLL1DIVR_DIVP1_Div64 = 0x3f
	// pll_p_ck = vco_ck / 66
	RCC_PLL1DIVR_DIVP1_Div66 = 0x41
	// pll_p_ck = vco_ck / 68
	RCC_PLL1DIVR_DIVP1_Div68 = 0x43
	// pll_p_ck = vco_ck / 70
	RCC_PLL1DIVR_DIVP1_Div70 = 0x45
	// pll_p_ck = vco_ck / 72
	RCC_PLL1DIVR_DIVP1_Div72 = 0x47
	// pll_p_ck = vco_ck / 74
	RCC_PLL1DIVR_DIVP1_Div74 = 0x49
	// pll_p_ck = vco_ck / 76
	RCC_PLL1DIVR_DIVP1_Div76 = 0x4b
	// pll_p_ck = vco_ck / 78
	RCC_PLL1DIVR_DIVP1_Div78 = 0x4d
	// pll_p_ck = vco_ck / 80
	RCC_PLL1DIVR_DIVP1_Div80 = 0x4f
	// pll_p_ck = vco_ck / 82
	RCC_PLL1DIVR_DIVP1_Div82 = 0x51
	// pll_p_ck = vco_ck / 84
	RCC_PLL1DIVR_DIVP1_Div84 = 0x53
	// pll_p_ck = vco_ck / 86
	RCC_PLL1DIVR_DIVP1_Div86 = 0x55
	// pll_p_ck = vco_ck / 88
	RCC_PLL1DIVR_DIVP1_Div88 = 0x57
	// pll_p_ck = vco_ck / 90
	RCC_PLL1DIVR_DIVP1_Div90 = 0x59
	// pll_p_ck = vco_ck / 92
	RCC_PLL1DIVR_DIVP1_Div92 = 0x5b
	// pll_p_ck = vco_ck / 94
	RCC_PLL1DIVR_DIVP1_Div94 = 0x5d
	// pll_p_ck = vco_ck / 96
	RCC_PLL1DIVR_DIVP1_Div96 = 0x5f
	// pll_p_ck = vco_ck / 98
	RCC_PLL1DIVR_DIVP1_Div98 = 0x61
	// pll_p_ck = vco_ck / 100
	RCC_PLL1DIVR_DIVP1_Div100 = 0x63
	// pll_p_ck = vco_ck / 102
	RCC_PLL1DIVR_DIVP1_Div102 = 0x65
	// pll_p_ck = vco_ck / 104
	RCC_PLL1DIVR_DIVP1_Div104 = 0x67
	// pll_p_ck = vco_ck / 106
	RCC_PLL1DIVR_DIVP1_Div106 = 0x69
	// pll_p_ck = vco_ck / 108
	RCC_PLL1DIVR_DIVP1_Div108 = 0x6b
	// pll_p_ck = vco_ck / 110
	RCC_PLL1DIVR_DIVP1_Div110 = 0x6d
	// pll_p_ck = vco_ck / 112
	RCC_PLL1DIVR_DIVP1_Div112 = 0x6f
	// pll_p_ck = vco_ck / 114
	RCC_PLL1DIVR_DIVP1_Div114 = 0x71
	// pll_p_ck = vco_ck / 116
	RCC_PLL1DIVR_DIVP1_Div116 = 0x73
	// pll_p_ck = vco_ck / 118
	RCC_PLL1DIVR_DIVP1_Div118 = 0x75
	// pll_p_ck = vco_ck / 120
	RCC_PLL1DIVR_DIVP1_Div120 = 0x77
	// pll_p_ck = vco_ck / 122
	RCC_PLL1DIVR_DIVP1_Div122 = 0x79
	// pll_p_ck = vco_ck / 124
	RCC_PLL1DIVR_DIVP1_Div124 = 0x7b
	// pll_p_ck = vco_ck / 126
	RCC_PLL1DIVR_DIVP1_Div126 = 0x7d
	// pll_p_ck = vco_ck / 128
	RCC_PLL1DIVR_DIVP1_Div128 = 0x7f
	// Position of DIVQ1 field.
	RCC_PLL1DIVR_DIVQ1_Pos = 0x10
	// Bit mask of DIVQ1 field.
	RCC_PLL1DIVR_DIVQ1_Msk = 0x7f0000
	// Position of DIVR1 field.
	RCC_PLL1DIVR_DIVR1_Pos = 0x18
	// Bit mask of DIVR1 field.
	RCC_PLL1DIVR_DIVR1_Msk = 0x7f000000

	// PLL1FRACR: RCC PLL1 Fractional Divider Register
	// Position of FRACN1 field.
	RCC_PLL1FRACR_FRACN1_Pos = 0x3
	// Bit mask of FRACN1 field.
	RCC_PLL1FRACR_FRACN1_Msk = 0xfff8

	// PLL2DIVR: RCC PLL2 Dividers Configuration Register
	// Position of DIVN2 field.
	RCC_PLL2DIVR_DIVN2_Pos = 0x0
	// Bit mask of DIVN2 field.
	RCC_PLL2DIVR_DIVN2_Msk = 0x1ff
	// Position of DIVP2 field.
	RCC_PLL2DIVR_DIVP2_Pos = 0x9
	// Bit mask of DIVP2 field.
	RCC_PLL2DIVR_DIVP2_Msk = 0xfe00
	// Position of DIVQ2 field.
	RCC_PLL2DIVR_DIVQ2_Pos = 0x10
	// Bit mask of DIVQ2 field.
	RCC_PLL2DIVR_DIVQ2_Msk = 0x7f0000
	// Position of DIVR2 field.
	RCC_PLL2DIVR_DIVR2_Pos = 0x18
	// Bit mask of DIVR2 field.
	RCC_PLL2DIVR_DIVR2_Msk = 0x7f000000

	// PLL2FRACR: RCC PLL2 Fractional Divider Register
	// Position of FRACN2 field.
	RCC_PLL2FRACR_FRACN2_Pos = 0x3
	// Bit mask of FRACN2 field.
	RCC_PLL2FRACR_FRACN2_Msk = 0xfff8

	// PLL3DIVR: RCC PLL3 Dividers Configuration Register
	// Position of DIVN3 field.
	RCC_PLL3DIVR_DIVN3_Pos = 0x0
	// Bit mask of DIVN3 field.
	RCC_PLL3DIVR_DIVN3_Msk = 0x1ff
	// Position of DIVP3 field.
	RCC_PLL3DIVR_DIVP3_Pos = 0x9
	// Bit mask of DIVP3 field.
	RCC_PLL3DIVR_DIVP3_Msk = 0xfe00
	// Position of DIVQ3 field.
	RCC_PLL3DIVR_DIVQ3_Pos = 0x10
	// Bit mask of DIVQ3 field.
	RCC_PLL3DIVR_DIVQ3_Msk = 0x7f0000
	// Position of DIVR3 field.
	RCC_PLL3DIVR_DIVR3_Pos = 0x18
	// Bit mask of DIVR3 field.
	RCC_PLL3DIVR_DIVR3_Msk = 0x7f000000

	// PLL3FRACR: RCC PLL3 Fractional Divider Register
	// Position of FRACN3 field.
	RCC_PLL3FRACR_FRACN3_Pos = 0x3
	// Bit mask of FRACN3 field.
	RCC_PLL3FRACR_FRACN3_Msk = 0xfff8

	// D1CCIPR: RCC Domain 1 Kernel Clock Configuration Register
	// Position of FMCSEL field.
	RCC_D1CCIPR_FMCSEL_Pos = 0x0
	// Bit mask of FMCSEL field.
	RCC_D1CCIPR_FMCSEL_Msk = 0x3
	// rcc_hclk3 selected as peripheral clock
	RCC_D1CCIPR_FMCSEL_RCC_HCLK3 = 0x0
	// pll1_q selected as peripheral clock
	RCC_D1CCIPR_FMCSEL_PLL1_Q = 0x1
	// pll2_r selected as peripheral clock
	RCC_D1CCIPR_FMCSEL_PLL2_R = 0x2
	// PER selected as peripheral clock
	RCC_D1CCIPR_FMCSEL_PER = 0x3
	// Position of QSPISEL field.
	RCC_D1CCIPR_QSPISEL_Pos = 0x4
	// Bit mask of QSPISEL field.
	RCC_D1CCIPR_QSPISEL_Msk = 0x30
	// rcc_hclk3 selected as peripheral clock
	RCC_D1CCIPR_QSPISEL_RCC_HCLK3 = 0x0
	// pll1_q selected as peripheral clock
	RCC_D1CCIPR_QSPISEL_PLL1_Q = 0x1
	// pll2_r selected as peripheral clock
	RCC_D1CCIPR_QSPISEL_PLL2_R = 0x2
	// PER selected as peripheral clock
	RCC_D1CCIPR_QSPISEL_PER = 0x3
	// Position of SDMMCSEL field.
	RCC_D1CCIPR_SDMMCSEL_Pos = 0x10
	// Bit mask of SDMMCSEL field.
	RCC_D1CCIPR_SDMMCSEL_Msk = 0x10000
	// Bit SDMMCSEL.
	RCC_D1CCIPR_SDMMCSEL = 0x10000
	// pll1_q selected as peripheral clock
	RCC_D1CCIPR_SDMMCSEL_PLL1_Q = 0x0
	// pll2_r selected as peripheral clock
	RCC_D1CCIPR_SDMMCSEL_PLL2_R = 0x1
	// Position of CKPERSEL field.
	RCC_D1CCIPR_CKPERSEL_Pos = 0x1c
	// Bit mask of CKPERSEL field.
	RCC_D1CCIPR_CKPERSEL_Msk = 0x30000000
	// HSI selected as peripheral clock
	RCC_D1CCIPR_CKPERSEL_HSI = 0x0
	// CSI selected as peripheral clock
	RCC_D1CCIPR_CKPERSEL_CSI = 0x1
	// HSE selected as peripheral clock
	RCC_D1CCIPR_CKPERSEL_HSE = 0x2

	// D2CCIP1R: RCC Domain 2 Kernel Clock Configuration Register
	// Position of SAI1SEL field.
	RCC_D2CCIP1R_SAI1SEL_Pos = 0x0
	// Bit mask of SAI1SEL field.
	RCC_D2CCIP1R_SAI1SEL_Msk = 0x7
	// pll1_q selected as peripheral clock
	RCC_D2CCIP1R_SAI1SEL_PLL1_Q = 0x0
	// pll2_p selected as peripheral clock
	RCC_D2CCIP1R_SAI1SEL_PLL2_P = 0x1
	// pll3_p selected as peripheral clock
	RCC_D2CCIP1R_SAI1SEL_PLL3_P = 0x2
	// I2S_CKIN selected as peripheral clock
	RCC_D2CCIP1R_SAI1SEL_I2S_CKIN = 0x3
	// PER selected as peripheral clock
	RCC_D2CCIP1R_SAI1SEL_PER = 0x4
	// Position of SAI23SEL field.
	RCC_D2CCIP1R_SAI23SEL_Pos = 0x6
	// Bit mask of SAI23SEL field.
	RCC_D2CCIP1R_SAI23SEL_Msk = 0x1c0
	// pll1_q selected as peripheral clock
	RCC_D2CCIP1R_SAI23SEL_PLL1_Q = 0x0
	// pll2_p selected as peripheral clock
	RCC_D2CCIP1R_SAI23SEL_PLL2_P = 0x1
	// pll3_p selected as peripheral clock
	RCC_D2CCIP1R_SAI23SEL_PLL3_P = 0x2
	// I2S_CKIN selected as peripheral clock
	RCC_D2CCIP1R_SAI23SEL_I2S_CKIN = 0x3
	// PER selected as peripheral clock
	RCC_D2CCIP1R_SAI23SEL_PER = 0x4
	// Position of SPI123SEL field.
	RCC_D2CCIP1R_SPI123SEL_Pos = 0xc
	// Bit mask of SPI123SEL field.
	RCC_D2CCIP1R_SPI123SEL_Msk = 0x7000
	// pll1_q selected as peripheral clock
	RCC_D2CCIP1R_SPI123SEL_PLL1_Q = 0x0
	// pll2_p selected as peripheral clock
	RCC_D2CCIP1R_SPI123SEL_PLL2_P = 0x1
	// pll3_p selected as peripheral clock
	RCC_D2CCIP1R_SPI123SEL_PLL3_P = 0x2
	// I2S_CKIN selected as peripheral clock
	RCC_D2CCIP1R_SPI123SEL_I2S_CKIN = 0x3
	// PER selected as peripheral clock
	RCC_D2CCIP1R_SPI123SEL_PER = 0x4
	// Position of SPI45SEL field.
	RCC_D2CCIP1R_SPI45SEL_Pos = 0x10
	// Bit mask of SPI45SEL field.
	RCC_D2CCIP1R_SPI45SEL_Msk = 0x70000
	// APB clock selected as peripheral clock
	RCC_D2CCIP1R_SPI45SEL_APB = 0x0
	// pll2_q selected as peripheral clock
	RCC_D2CCIP1R_SPI45SEL_PLL2_Q = 0x1
	// pll3_q selected as peripheral clock
	RCC_D2CCIP1R_SPI45SEL_PLL3_Q = 0x2
	// hsi_ker selected as peripheral clock
	RCC_D2CCIP1R_SPI45SEL_HSI_KER = 0x3
	// csi_ker selected as peripheral clock
	RCC_D2CCIP1R_SPI45SEL_CSI_KER = 0x4
	// HSE selected as peripheral clock
	RCC_D2CCIP1R_SPI45SEL_HSE = 0x5
	// Position of SPDIFSEL field.
	RCC_D2CCIP1R_SPDIFSEL_Pos = 0x14
	// Bit mask of SPDIFSEL field.
	RCC_D2CCIP1R_SPDIFSEL_Msk = 0x300000
	// pll1_q selected as peripheral clock
	RCC_D2CCIP1R_SPDIFSEL_PLL1_Q = 0x0
	// pll2_r selected as peripheral clock
	RCC_D2CCIP1R_SPDIFSEL_PLL2_R = 0x1
	// pll3_r selected as peripheral clock
	RCC_D2CCIP1R_SPDIFSEL_PLL3_R = 0x2
	// hsi_ker selected as peripheral clock
	RCC_D2CCIP1R_SPDIFSEL_HSI_KER = 0x3
	// Position of DFSDM1SEL field.
	RCC_D2CCIP1R_DFSDM1SEL_Pos = 0x18
	// Bit mask of DFSDM1SEL field.
	RCC_D2CCIP1R_DFSDM1SEL_Msk = 0x1000000
	// Bit DFSDM1SEL.
	RCC_D2CCIP1R_DFSDM1SEL = 0x1000000
	// rcc_pclk2 selected as peripheral clock
	RCC_D2CCIP1R_DFSDM1SEL_RCC_PCLK2 = 0x0
	// System clock selected as peripheral clock
	RCC_D2CCIP1R_DFSDM1SEL_SYS = 0x1
	// Position of FDCANSEL field.
	RCC_D2CCIP1R_FDCANSEL_Pos = 0x1c
	// Bit mask of FDCANSEL field.
	RCC_D2CCIP1R_FDCANSEL_Msk = 0x30000000
	// HSE selected as peripheral clock
	RCC_D2CCIP1R_FDCANSEL_HSE = 0x0
	// pll1_q selected as peripheral clock
	RCC_D2CCIP1R_FDCANSEL_PLL1_Q = 0x1
	// pll2_q selected as peripheral clock
	RCC_D2CCIP1R_FDCANSEL_PLL2_Q = 0x2
	// Position of SWPSEL field.
	RCC_D2CCIP1R_SWPSEL_Pos = 0x1f
	// Bit mask of SWPSEL field.
	RCC_D2CCIP1R_SWPSEL_Msk = 0x80000000
	// Bit SWPSEL.
	RCC_D2CCIP1R_SWPSEL = 0x80000000
	// pclk selected as peripheral clock
	RCC_D2CCIP1R_SWPSEL_PCLK = 0x0
	// hsi_ker selected as peripheral clock
	RCC_D2CCIP1R_SWPSEL_HSI_KER = 0x1

	// D2CCIP2R: RCC Domain 2 Kernel Clock Configuration Register
	// Position of USART234578SEL field.
	RCC_D2CCIP2R_USART234578SEL_Pos = 0x0
	// Bit mask of USART234578SEL field.
	RCC_D2CCIP2R_USART234578SEL_Msk = 0x7
	// rcc_pclk1 selected as peripheral clock
	RCC_D2CCIP2R_USART234578SEL_RCC_PCLK1 = 0x0
	// pll2_q selected as peripheral clock
	RCC_D2CCIP2R_USART234578SEL_PLL2_Q = 0x1
	// pll3_q selected as peripheral clock
	RCC_D2CCIP2R_USART234578SEL_PLL3_Q = 0x2
	// hsi_ker selected as peripheral clock
	RCC_D2CCIP2R_USART234578SEL_HSI_KER = 0x3
	// csi_ker selected as peripheral clock
	RCC_D2CCIP2R_USART234578SEL_CSI_KER = 0x4
	// LSE selected as peripheral clock
	RCC_D2CCIP2R_USART234578SEL_LSE = 0x5
	// Position of USART16SEL field.
	RCC_D2CCIP2R_USART16SEL_Pos = 0x3
	// Bit mask of USART16SEL field.
	RCC_D2CCIP2R_USART16SEL_Msk = 0x38
	// rcc_pclk2 selected as peripheral clock
	RCC_D2CCIP2R_USART16SEL_RCC_PCLK2 = 0x0
	// pll2_q selected as peripheral clock
	RCC_D2CCIP2R_USART16SEL_PLL2_Q = 0x1
	// pll3_q selected as peripheral clock
	RCC_D2CCIP2R_USART16SEL_PLL3_Q = 0x2
	// hsi_ker selected as peripheral clock
	RCC_D2CCIP2R_USART16SEL_HSI_KER = 0x3
	// csi_ker selected as peripheral clock
	RCC_D2CCIP2R_USART16SEL_CSI_KER = 0x4
	// LSE selected as peripheral clock
	RCC_D2CCIP2R_USART16SEL_LSE = 0x5
	// Position of RNGSEL field.
	RCC_D2CCIP2R_RNGSEL_Pos = 0x8
	// Bit mask of RNGSEL field.
	RCC_D2CCIP2R_RNGSEL_Msk = 0x300
	// HSI48 selected as peripheral clock
	RCC_D2CCIP2R_RNGSEL_HSI48 = 0x0
	// pll1_q selected as peripheral clock
	RCC_D2CCIP2R_RNGSEL_PLL1_Q = 0x1
	// LSE selected as peripheral clock
	RCC_D2CCIP2R_RNGSEL_LSE = 0x2
	// LSI selected as peripheral clock
	RCC_D2CCIP2R_RNGSEL_LSI = 0x3
	// Position of I2C123SEL field.
	RCC_D2CCIP2R_I2C123SEL_Pos = 0xc
	// Bit mask of I2C123SEL field.
	RCC_D2CCIP2R_I2C123SEL_Msk = 0x3000
	// rcc_pclk1 selected as peripheral clock
	RCC_D2CCIP2R_I2C123SEL_RCC_PCLK1 = 0x0
	// pll3_r selected as peripheral clock
	RCC_D2CCIP2R_I2C123SEL_PLL3_R = 0x1
	// hsi_ker selected as peripheral clock
	RCC_D2CCIP2R_I2C123SEL_HSI_KER = 0x2
	// csi_ker selected as peripheral clock
	RCC_D2CCIP2R_I2C123SEL_CSI_KER = 0x3
	// Position of USBSEL field.
	RCC_D2CCIP2R_USBSEL_Pos = 0x14
	// Bit mask of USBSEL field.
	RCC_D2CCIP2R_USBSEL_Msk = 0x300000
	// Disable the kernel clock
	RCC_D2CCIP2R_USBSEL_DISABLE = 0x0
	// pll1_q selected as peripheral clock
	RCC_D2CCIP2R_USBSEL_PLL1_Q = 0x1
	// pll3_q selected as peripheral clock
	RCC_D2CCIP2R_USBSEL_PLL3_Q = 0x2
	// HSI48 selected as peripheral clock
	RCC_D2CCIP2R_USBSEL_HSI48 = 0x3
	// Position of CECSEL field.
	RCC_D2CCIP2R_CECSEL_Pos = 0x16
	// Bit mask of CECSEL field.
	RCC_D2CCIP2R_CECSEL_Msk = 0xc00000
	// LSE selected as peripheral clock
	RCC_D2CCIP2R_CECSEL_LSE = 0x0
	// LSI selected as peripheral clock
	RCC_D2CCIP2R_CECSEL_LSI = 0x1
	// csi_ker selected as peripheral clock
	RCC_D2CCIP2R_CECSEL_CSI_KER = 0x2
	// Position of LPTIM1SEL field.
	RCC_D2CCIP2R_LPTIM1SEL_Pos = 0x1c
	// Bit mask of LPTIM1SEL field.
	RCC_D2CCIP2R_LPTIM1SEL_Msk = 0x70000000
	// rcc_pclk1 selected as peripheral clock
	RCC_D2CCIP2R_LPTIM1SEL_RCC_PCLK1 = 0x0
	// pll2_p selected as peripheral clock
	RCC_D2CCIP2R_LPTIM1SEL_PLL2_P = 0x1
	// pll3_r selected as peripheral clock
	RCC_D2CCIP2R_LPTIM1SEL_PLL3_R = 0x2
	// LSE selected as peripheral clock
	RCC_D2CCIP2R_LPTIM1SEL_LSE = 0x3
	// LSI selected as peripheral clock
	RCC_D2CCIP2R_LPTIM1SEL_LSI = 0x4
	// PER selected as peripheral clock
	RCC_D2CCIP2R_LPTIM1SEL_PER = 0x5

	// D3CCIPR: RCC Domain 3 Kernel Clock Configuration Register
	// Position of LPUART1SEL field.
	RCC_D3CCIPR_LPUART1SEL_Pos = 0x0
	// Bit mask of LPUART1SEL field.
	RCC_D3CCIPR_LPUART1SEL_Msk = 0x7
	// rcc_pclk_d3 selected as peripheral clock
	RCC_D3CCIPR_LPUART1SEL_RCC_PCLK_D3 = 0x0
	// pll2_q selected as peripheral clock
	RCC_D3CCIPR_LPUART1SEL_PLL2_Q = 0x1
	// pll3_q selected as peripheral clock
	RCC_D3CCIPR_LPUART1SEL_PLL3_Q = 0x2
	// hsi_ker selected as peripheral clock
	RCC_D3CCIPR_LPUART1SEL_HSI_KER = 0x3
	// csi_ker selected as peripheral clock
	RCC_D3CCIPR_LPUART1SEL_CSI_KER = 0x4
	// LSE selected as peripheral clock
	RCC_D3CCIPR_LPUART1SEL_LSE = 0x5
	// Position of I2C4SEL field.
	RCC_D3CCIPR_I2C4SEL_Pos = 0x8
	// Bit mask of I2C4SEL field.
	RCC_D3CCIPR_I2C4SEL_Msk = 0x300
	// rcc_pclk4 selected as peripheral clock
	RCC_D3CCIPR_I2C4SEL_RCC_PCLK4 = 0x0
	// pll3_r selected as peripheral clock
	RCC_D3CCIPR_I2C4SEL_PLL3_R = 0x1
	// hsi_ker selected as peripheral clock
	RCC_D3CCIPR_I2C4SEL_HSI_KER = 0x2
	// csi_ker selected as peripheral clock
	RCC_D3CCIPR_I2C4SEL_CSI_KER = 0x3
	// Position of LPTIM2SEL field.
	RCC_D3CCIPR_LPTIM2SEL_Pos = 0xa
	// Bit mask of LPTIM2SEL field.
	RCC_D3CCIPR_LPTIM2SEL_Msk = 0x1c00
	// rcc_pclk4 selected as peripheral clock
	RCC_D3CCIPR_LPTIM2SEL_RCC_PCLK4 = 0x0
	// pll2_p selected as peripheral clock
	RCC_D3CCIPR_LPTIM2SEL_PLL2_P = 0x1
	// pll3_r selected as peripheral clock
	RCC_D3CCIPR_LPTIM2SEL_PLL3_R = 0x2
	// LSE selected as peripheral clock
	RCC_D3CCIPR_LPTIM2SEL_LSE = 0x3
	// LSI selected as peripheral clock
	RCC_D3CCIPR_LPTIM2SEL_LSI = 0x4
	// PER selected as peripheral clock
	RCC_D3CCIPR_LPTIM2SEL_PER = 0x5
	// Position of LPTIM345SEL field.
	RCC_D3CCIPR_LPTIM345SEL_Pos = 0xd
	// Bit mask of LPTIM345SEL field.
	RCC_D3CCIPR_LPTIM345SEL_Msk = 0xe000
	// rcc_pclk4 selected as peripheral clock
	RCC_D3CCIPR_LPTIM345SEL_RCC_PCLK4 = 0x0
	// pll2_p selected as peripheral clock
	RCC_D3CCIPR_LPTIM345SEL_PLL2_P = 0x1
	// pll3_r selected as peripheral clock
	RCC_D3CCIPR_LPTIM345SEL_PLL3_R = 0x2
	// LSE selected as peripheral clock
	RCC_D3CCIPR_LPTIM345SEL_LSE = 0x3
	// LSI selected as peripheral clock
	RCC_D3CCIPR_LPTIM345SEL_LSI = 0x4
	// PER selected as peripheral clock
	RCC_D3CCIPR_LPTIM345SEL_PER = 0x5
	// Position of ADCSEL field.
	RCC_D3CCIPR_ADCSEL_Pos = 0x10
	// Bit mask of ADCSEL field.
	RCC_D3CCIPR_ADCSEL_Msk = 0x30000
	// pll2_p selected as peripheral clock
	RCC_D3CCIPR_ADCSEL_PLL2_P = 0x0
	// pll3_r selected as peripheral clock
	RCC_D3CCIPR_ADCSEL_PLL3_R = 0x1
	// PER selected as peripheral clock
	RCC_D3CCIPR_ADCSEL_PER = 0x2
	// Position of SAI4ASEL field.
	RCC_D3CCIPR_SAI4ASEL_Pos = 0x15
	// Bit mask of SAI4ASEL field.
	RCC_D3CCIPR_SAI4ASEL_Msk = 0xe00000
	// pll1_q selected as peripheral clock
	RCC_D3CCIPR_SAI4ASEL_PLL1_Q = 0x0
	// pll2_p selected as peripheral clock
	RCC_D3CCIPR_SAI4ASEL_PLL2_P = 0x1
	// pll3_p selected as peripheral clock
	RCC_D3CCIPR_SAI4ASEL_PLL3_P = 0x2
	// i2s_ckin selected as peripheral clock
	RCC_D3CCIPR_SAI4ASEL_I2S_CKIN = 0x3
	// PER selected as peripheral clock
	RCC_D3CCIPR_SAI4ASEL_PER = 0x4
	// Position of SAI4BSEL field.
	RCC_D3CCIPR_SAI4BSEL_Pos = 0x18
	// Bit mask of SAI4BSEL field.
	RCC_D3CCIPR_SAI4BSEL_Msk = 0x7000000
	// pll1_q selected as peripheral clock
	RCC_D3CCIPR_SAI4BSEL_PLL1_Q = 0x0
	// pll2_p selected as peripheral clock
	RCC_D3CCIPR_SAI4BSEL_PLL2_P = 0x1
	// pll3_p selected as peripheral clock
	RCC_D3CCIPR_SAI4BSEL_PLL3_P = 0x2
	// i2s_ckin selected as peripheral clock
	RCC_D3CCIPR_SAI4BSEL_I2S_CKIN = 0x3
	// PER selected as peripheral clock
	RCC_D3CCIPR_SAI4BSEL_PER = 0x4
	// Position of SPI6SEL field.
	RCC_D3CCIPR_SPI6SEL_Pos = 0x1c
	// Bit mask of SPI6SEL field.
	RCC_D3CCIPR_SPI6SEL_Msk = 0x70000000
	// rcc_pclk4 selected as peripheral clock
	RCC_D3CCIPR_SPI6SEL_RCC_PCLK4 = 0x0
	// pll2_q selected as peripheral clock
	RCC_D3CCIPR_SPI6SEL_PLL2_Q = 0x1
	// pll3_q selected as peripheral clock
	RCC_D3CCIPR_SPI6SEL_PLL3_Q = 0x2
	// hsi_ker selected as peripheral clock
	RCC_D3CCIPR_SPI6SEL_HSI_KER = 0x3
	// csi_ker selected as peripheral clock
	RCC_D3CCIPR_SPI6SEL_CSI_KER = 0x4
	// HSE selected as peripheral clock
	RCC_D3CCIPR_SPI6SEL_HSE = 0x5

	// CIER: RCC Clock Source Interrupt Enable Register
	// Position of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Pos = 0x0
	// Bit mask of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Msk = 0x1
	// Bit LSIRDYIE.
	RCC_CIER_LSIRDYIE = 0x1
	// Interrupt disabled
	RCC_CIER_LSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_LSIRDYIE_Enabled = 0x1
	// Position of LSERDYIE field.
	RCC_CIER_LSERDYIE_Pos = 0x1
	// Bit mask of LSERDYIE field.
	RCC_CIER_LSERDYIE_Msk = 0x2
	// Bit LSERDYIE.
	RCC_CIER_LSERDYIE = 0x2
	// Interrupt disabled
	RCC_CIER_LSERDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_LSERDYIE_Enabled = 0x1
	// Position of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Pos = 0x2
	// Bit mask of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Msk = 0x4
	// Bit HSIRDYIE.
	RCC_CIER_HSIRDYIE = 0x4
	// Interrupt disabled
	RCC_CIER_HSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSIRDYIE_Enabled = 0x1
	// Position of HSERDYIE field.
	RCC_CIER_HSERDYIE_Pos = 0x3
	// Bit mask of HSERDYIE field.
	RCC_CIER_HSERDYIE_Msk = 0x8
	// Bit HSERDYIE.
	RCC_CIER_HSERDYIE = 0x8
	// Interrupt disabled
	RCC_CIER_HSERDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSERDYIE_Enabled = 0x1
	// Position of CSIRDYIE field.
	RCC_CIER_CSIRDYIE_Pos = 0x4
	// Bit mask of CSIRDYIE field.
	RCC_CIER_CSIRDYIE_Msk = 0x10
	// Bit CSIRDYIE.
	RCC_CIER_CSIRDYIE = 0x10
	// Interrupt disabled
	RCC_CIER_CSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_CSIRDYIE_Enabled = 0x1
	// Position of HSI48RDYIE field.
	RCC_CIER_HSI48RDYIE_Pos = 0x5
	// Bit mask of HSI48RDYIE field.
	RCC_CIER_HSI48RDYIE_Msk = 0x20
	// Bit HSI48RDYIE.
	RCC_CIER_HSI48RDYIE = 0x20
	// Interrupt disabled
	RCC_CIER_HSI48RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSI48RDYIE_Enabled = 0x1
	// Position of PLL1RDYIE field.
	RCC_CIER_PLL1RDYIE_Pos = 0x6
	// Bit mask of PLL1RDYIE field.
	RCC_CIER_PLL1RDYIE_Msk = 0x40
	// Bit PLL1RDYIE.
	RCC_CIER_PLL1RDYIE = 0x40
	// Interrupt disabled
	RCC_CIER_PLL1RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_PLL1RDYIE_Enabled = 0x1
	// Position of PLL2RDYIE field.
	RCC_CIER_PLL2RDYIE_Pos = 0x7
	// Bit mask of PLL2RDYIE field.
	RCC_CIER_PLL2RDYIE_Msk = 0x80
	// Bit PLL2RDYIE.
	RCC_CIER_PLL2RDYIE = 0x80
	// Interrupt disabled
	RCC_CIER_PLL2RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_PLL2RDYIE_Enabled = 0x1
	// Position of PLL3RDYIE field.
	RCC_CIER_PLL3RDYIE_Pos = 0x8
	// Bit mask of PLL3RDYIE field.
	RCC_CIER_PLL3RDYIE_Msk = 0x100
	// Bit PLL3RDYIE.
	RCC_CIER_PLL3RDYIE = 0x100
	// Interrupt disabled
	RCC_CIER_PLL3RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_PLL3RDYIE_Enabled = 0x1
	// Position of LSECSSIE field.
	RCC_CIER_LSECSSIE_Pos = 0x9
	// Bit mask of LSECSSIE field.
	RCC_CIER_LSECSSIE_Msk = 0x200
	// Bit LSECSSIE.
	RCC_CIER_LSECSSIE = 0x200
	// Interrupt disabled
	RCC_CIER_LSECSSIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_LSECSSIE_Enabled = 0x1

	// CIFR: RCC Clock Source Interrupt Flag Register
	// Position of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Pos = 0x0
	// Bit mask of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Msk = 0x1
	// Bit LSIRDYF.
	RCC_CIFR_LSIRDYF = 0x1
	// Position of LSERDYF field.
	RCC_CIFR_LSERDYF_Pos = 0x1
	// Bit mask of LSERDYF field.
	RCC_CIFR_LSERDYF_Msk = 0x2
	// Bit LSERDYF.
	RCC_CIFR_LSERDYF = 0x2
	// Position of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Pos = 0x2
	// Bit mask of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Msk = 0x4
	// Bit HSIRDYF.
	RCC_CIFR_HSIRDYF = 0x4
	// Position of HSERDYF field.
	RCC_CIFR_HSERDYF_Pos = 0x3
	// Bit mask of HSERDYF field.
	RCC_CIFR_HSERDYF_Msk = 0x8
	// Bit HSERDYF.
	RCC_CIFR_HSERDYF = 0x8
	// Position of CSIRDY field.
	RCC_CIFR_CSIRDY_Pos = 0x4
	// Bit mask of CSIRDY field.
	RCC_CIFR_CSIRDY_Msk = 0x10
	// Bit CSIRDY.
	RCC_CIFR_CSIRDY = 0x10
	// Position of HSI48RDYF field.
	RCC_CIFR_HSI48RDYF_Pos = 0x5
	// Bit mask of HSI48RDYF field.
	RCC_CIFR_HSI48RDYF_Msk = 0x20
	// Bit HSI48RDYF.
	RCC_CIFR_HSI48RDYF = 0x20
	// Position of PLL1RDYF field.
	RCC_CIFR_PLL1RDYF_Pos = 0x6
	// Bit mask of PLL1RDYF field.
	RCC_CIFR_PLL1RDYF_Msk = 0x40
	// Bit PLL1RDYF.
	RCC_CIFR_PLL1RDYF = 0x40
	// Position of PLL2RDYF field.
	RCC_CIFR_PLL2RDYF_Pos = 0x7
	// Bit mask of PLL2RDYF field.
	RCC_CIFR_PLL2RDYF_Msk = 0x80
	// Bit PLL2RDYF.
	RCC_CIFR_PLL2RDYF = 0x80
	// Position of PLL3RDYF field.
	RCC_CIFR_PLL3RDYF_Pos = 0x8
	// Bit mask of PLL3RDYF field.
	RCC_CIFR_PLL3RDYF_Msk = 0x100
	// Bit PLL3RDYF.
	RCC_CIFR_PLL3RDYF = 0x100
	// Position of LSECSSF field.
	RCC_CIFR_LSECSSF_Pos = 0x9
	// Bit mask of LSECSSF field.
	RCC_CIFR_LSECSSF_Msk = 0x200
	// Bit LSECSSF.
	RCC_CIFR_LSECSSF = 0x200
	// Position of HSECSSF field.
	RCC_CIFR_HSECSSF_Pos = 0xa
	// Bit mask of HSECSSF field.
	RCC_CIFR_HSECSSF_Msk = 0x400
	// Bit HSECSSF.
	RCC_CIFR_HSECSSF = 0x400

	// CICR: RCC Clock Source Interrupt Clear Register
	// Position of LSIRDYC field.
	RCC_CICR_LSIRDYC_Pos = 0x0
	// Bit mask of LSIRDYC field.
	RCC_CICR_LSIRDYC_Msk = 0x1
	// Bit LSIRDYC.
	RCC_CICR_LSIRDYC = 0x1
	// Clear interrupt flag
	RCC_CICR_LSIRDYC_Clear = 0x1
	// Position of LSERDYC field.
	RCC_CICR_LSERDYC_Pos = 0x1
	// Bit mask of LSERDYC field.
	RCC_CICR_LSERDYC_Msk = 0x2
	// Bit LSERDYC.
	RCC_CICR_LSERDYC = 0x2
	// Clear interrupt flag
	RCC_CICR_LSERDYC_Clear = 0x1
	// Position of HSIRDYC field.
	RCC_CICR_HSIRDYC_Pos = 0x2
	// Bit mask of HSIRDYC field.
	RCC_CICR_HSIRDYC_Msk = 0x4
	// Bit HSIRDYC.
	RCC_CICR_HSIRDYC = 0x4
	// Clear interrupt flag
	RCC_CICR_HSIRDYC_Clear = 0x1
	// Position of HSERDYC field.
	RCC_CICR_HSERDYC_Pos = 0x3
	// Bit mask of HSERDYC field.
	RCC_CICR_HSERDYC_Msk = 0x8
	// Bit HSERDYC.
	RCC_CICR_HSERDYC = 0x8
	// Clear interrupt flag
	RCC_CICR_HSERDYC_Clear = 0x1
	// Position of HSE_ready_Interrupt_Clear field.
	RCC_CICR_HSE_ready_Interrupt_Clear_Pos = 0x4
	// Bit mask of HSE_ready_Interrupt_Clear field.
	RCC_CICR_HSE_ready_Interrupt_Clear_Msk = 0x10
	// Bit HSE_ready_Interrupt_Clear.
	RCC_CICR_HSE_ready_Interrupt_Clear = 0x10
	// Position of HSI48RDYC field.
	RCC_CICR_HSI48RDYC_Pos = 0x5
	// Bit mask of HSI48RDYC field.
	RCC_CICR_HSI48RDYC_Msk = 0x20
	// Bit HSI48RDYC.
	RCC_CICR_HSI48RDYC = 0x20
	// Clear interrupt flag
	RCC_CICR_HSI48RDYC_Clear = 0x1
	// Position of PLL1RDYC field.
	RCC_CICR_PLL1RDYC_Pos = 0x6
	// Bit mask of PLL1RDYC field.
	RCC_CICR_PLL1RDYC_Msk = 0x40
	// Bit PLL1RDYC.
	RCC_CICR_PLL1RDYC = 0x40
	// Clear interrupt flag
	RCC_CICR_PLL1RDYC_Clear = 0x1
	// Position of PLL2RDYC field.
	RCC_CICR_PLL2RDYC_Pos = 0x7
	// Bit mask of PLL2RDYC field.
	RCC_CICR_PLL2RDYC_Msk = 0x80
	// Bit PLL2RDYC.
	RCC_CICR_PLL2RDYC = 0x80
	// Clear interrupt flag
	RCC_CICR_PLL2RDYC_Clear = 0x1
	// Position of PLL3RDYC field.
	RCC_CICR_PLL3RDYC_Pos = 0x8
	// Bit mask of PLL3RDYC field.
	RCC_CICR_PLL3RDYC_Msk = 0x100
	// Bit PLL3RDYC.
	RCC_CICR_PLL3RDYC = 0x100
	// Clear interrupt flag
	RCC_CICR_PLL3RDYC_Clear = 0x1
	// Position of LSECSSC field.
	RCC_CICR_LSECSSC_Pos = 0x9
	// Bit mask of LSECSSC field.
	RCC_CICR_LSECSSC_Msk = 0x200
	// Bit LSECSSC.
	RCC_CICR_LSECSSC = 0x200
	// Clear interrupt flag
	RCC_CICR_LSECSSC_Clear = 0x1
	// Position of HSECSSC field.
	RCC_CICR_HSECSSC_Pos = 0xa
	// Bit mask of HSECSSC field.
	RCC_CICR_HSECSSC_Msk = 0x400
	// Bit HSECSSC.
	RCC_CICR_HSECSSC = 0x400
	// Clear interrupt flag
	RCC_CICR_HSECSSC_Clear = 0x1

	// BDCR: RCC Backup Domain Control Register
	// Position of LSEON field.
	RCC_BDCR_LSEON_Pos = 0x0
	// Bit mask of LSEON field.
	RCC_BDCR_LSEON_Msk = 0x1
	// Bit LSEON.
	RCC_BDCR_LSEON = 0x1
	// LSE oscillator Off
	RCC_BDCR_LSEON_Off = 0x0
	// LSE oscillator On
	RCC_BDCR_LSEON_On = 0x1
	// Position of LSERDY field.
	RCC_BDCR_LSERDY_Pos = 0x1
	// Bit mask of LSERDY field.
	RCC_BDCR_LSERDY_Msk = 0x2
	// Bit LSERDY.
	RCC_BDCR_LSERDY = 0x2
	// LSE oscillator not ready
	RCC_BDCR_LSERDY_NotReady = 0x0
	// LSE oscillator ready
	RCC_BDCR_LSERDY_Ready = 0x1
	// Position of LSEBYP field.
	RCC_BDCR_LSEBYP_Pos = 0x2
	// Bit mask of LSEBYP field.
	RCC_BDCR_LSEBYP_Msk = 0x4
	// Bit LSEBYP.
	RCC_BDCR_LSEBYP = 0x4
	// LSE crystal oscillator not bypassed
	RCC_BDCR_LSEBYP_NotBypassed = 0x0
	// LSE crystal oscillator bypassed with external clock
	RCC_BDCR_LSEBYP_Bypassed = 0x1
	// Position of LSEDRV field.
	RCC_BDCR_LSEDRV_Pos = 0x3
	// Bit mask of LSEDRV field.
	RCC_BDCR_LSEDRV_Msk = 0x18
	// Lowest LSE oscillator driving capability
	RCC_BDCR_LSEDRV_Lowest = 0x0
	// Medium low LSE oscillator driving capability
	RCC_BDCR_LSEDRV_MediumLow = 0x1
	// Medium high LSE oscillator driving capability
	RCC_BDCR_LSEDRV_MediumHigh = 0x2
	// Highest LSE oscillator driving capability
	RCC_BDCR_LSEDRV_Highest = 0x3
	// Position of LSECSSON field.
	RCC_BDCR_LSECSSON_Pos = 0x5
	// Bit mask of LSECSSON field.
	RCC_BDCR_LSECSSON_Msk = 0x20
	// Bit LSECSSON.
	RCC_BDCR_LSECSSON = 0x20
	// Clock security system on 32 kHz oscillator off
	RCC_BDCR_LSECSSON_SecurityOff = 0x0
	// Clock security system on 32 kHz oscillator on
	RCC_BDCR_LSECSSON_SecurityOn = 0x1
	// Position of LSECSSD field.
	RCC_BDCR_LSECSSD_Pos = 0x6
	// Bit mask of LSECSSD field.
	RCC_BDCR_LSECSSD_Msk = 0x40
	// Bit LSECSSD.
	RCC_BDCR_LSECSSD = 0x40
	// No failure detected on 32 kHz oscillator
	RCC_BDCR_LSECSSD_NoFailure = 0x0
	// Failure detected on 32 kHz oscillator
	RCC_BDCR_LSECSSD_Failure = 0x1
	// Position of RTCSEL field.
	RCC_BDCR_RTCSEL_Pos = 0x8
	// Bit mask of RTCSEL field.
	RCC_BDCR_RTCSEL_Msk = 0x300
	// No clock
	RCC_BDCR_RTCSEL_NoClock = 0x0
	// LSE oscillator clock used as RTC clock
	RCC_BDCR_RTCSEL_LSE = 0x1
	// LSI oscillator clock used as RTC clock
	RCC_BDCR_RTCSEL_LSI = 0x2
	// HSE oscillator clock divided by a prescaler used as RTC clock
	RCC_BDCR_RTCSEL_HSE = 0x3
	// Position of RTCEN field.
	RCC_BDCR_RTCEN_Pos = 0xf
	// Bit mask of RTCEN field.
	RCC_BDCR_RTCEN_Msk = 0x8000
	// Bit RTCEN.
	RCC_BDCR_RTCEN = 0x8000
	// RTC clock disabled
	RCC_BDCR_RTCEN_Disabled = 0x0
	// RTC clock enabled
	RCC_BDCR_RTCEN_Enabled = 0x1
	// Position of BDRST field.
	RCC_BDCR_BDRST_Pos = 0x10
	// Bit mask of BDRST field.
	RCC_BDCR_BDRST_Msk = 0x10000
	// Bit BDRST.
	RCC_BDCR_BDRST = 0x10000
	// Resets the entire VSW domain
	RCC_BDCR_BDRST_Reset = 0x1

	// CSR: RCC Clock Control and Status Register
	// Position of LSION field.
	RCC_CSR_LSION_Pos = 0x0
	// Bit mask of LSION field.
	RCC_CSR_LSION_Msk = 0x1
	// Bit LSION.
	RCC_CSR_LSION = 0x1
	// LSI oscillator Off
	RCC_CSR_LSION_Off = 0x0
	// LSI oscillator On
	RCC_CSR_LSION_On = 0x1
	// Position of LSIRDY field.
	RCC_CSR_LSIRDY_Pos = 0x1
	// Bit mask of LSIRDY field.
	RCC_CSR_LSIRDY_Msk = 0x2
	// Bit LSIRDY.
	RCC_CSR_LSIRDY = 0x2
	// LSI oscillator not ready
	RCC_CSR_LSIRDY_NotReady = 0x0
	// LSI oscillator ready
	RCC_CSR_LSIRDY_Ready = 0x1

	// AHB3RSTR: RCC AHB3 Reset Register
	// Position of MDMARST field.
	RCC_AHB3RSTR_MDMARST_Pos = 0x0
	// Bit mask of MDMARST field.
	RCC_AHB3RSTR_MDMARST_Msk = 0x1
	// Bit MDMARST.
	RCC_AHB3RSTR_MDMARST = 0x1
	// Reset the selected module
	RCC_AHB3RSTR_MDMARST_Reset = 0x1
	// Position of DMA2DRST field.
	RCC_AHB3RSTR_DMA2DRST_Pos = 0x4
	// Bit mask of DMA2DRST field.
	RCC_AHB3RSTR_DMA2DRST_Msk = 0x10
	// Bit DMA2DRST.
	RCC_AHB3RSTR_DMA2DRST = 0x10
	// Reset the selected module
	RCC_AHB3RSTR_DMA2DRST_Reset = 0x1
	// Position of JPGDECRST field.
	RCC_AHB3RSTR_JPGDECRST_Pos = 0x5
	// Bit mask of JPGDECRST field.
	RCC_AHB3RSTR_JPGDECRST_Msk = 0x20
	// Bit JPGDECRST.
	RCC_AHB3RSTR_JPGDECRST = 0x20
	// Reset the selected module
	RCC_AHB3RSTR_JPGDECRST_Reset = 0x1
	// Position of FMCRST field.
	RCC_AHB3RSTR_FMCRST_Pos = 0xc
	// Bit mask of FMCRST field.
	RCC_AHB3RSTR_FMCRST_Msk = 0x1000
	// Bit FMCRST.
	RCC_AHB3RSTR_FMCRST = 0x1000
	// Reset the selected module
	RCC_AHB3RSTR_FMCRST_Reset = 0x1
	// Position of QSPIRST field.
	RCC_AHB3RSTR_QSPIRST_Pos = 0xe
	// Bit mask of QSPIRST field.
	RCC_AHB3RSTR_QSPIRST_Msk = 0x4000
	// Bit QSPIRST.
	RCC_AHB3RSTR_QSPIRST = 0x4000
	// Reset the selected module
	RCC_AHB3RSTR_QSPIRST_Reset = 0x1
	// Position of SDMMC1RST field.
	RCC_AHB3RSTR_SDMMC1RST_Pos = 0x10
	// Bit mask of SDMMC1RST field.
	RCC_AHB3RSTR_SDMMC1RST_Msk = 0x10000
	// Bit SDMMC1RST.
	RCC_AHB3RSTR_SDMMC1RST = 0x10000
	// Reset the selected module
	RCC_AHB3RSTR_SDMMC1RST_Reset = 0x1
	// Position of CPURST field.
	RCC_AHB3RSTR_CPURST_Pos = 0x1f
	// Bit mask of CPURST field.
	RCC_AHB3RSTR_CPURST_Msk = 0x80000000
	// Bit CPURST.
	RCC_AHB3RSTR_CPURST = 0x80000000
	// Reset the selected module
	RCC_AHB3RSTR_CPURST_Reset = 0x1

	// AHB1RSTR: RCC AHB1 Peripheral Reset Register
	// Position of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST_Pos = 0x0
	// Bit mask of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST_Msk = 0x1
	// Bit DMA1RST.
	RCC_AHB1RSTR_DMA1RST = 0x1
	// Reset the selected module
	RCC_AHB1RSTR_DMA1RST_Reset = 0x1
	// Position of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST_Pos = 0x1
	// Bit mask of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST_Msk = 0x2
	// Bit DMA2RST.
	RCC_AHB1RSTR_DMA2RST = 0x2
	// Reset the selected module
	RCC_AHB1RSTR_DMA2RST_Reset = 0x1
	// Position of ADC12RST field.
	RCC_AHB1RSTR_ADC12RST_Pos = 0x5
	// Bit mask of ADC12RST field.
	RCC_AHB1RSTR_ADC12RST_Msk = 0x20
	// Bit ADC12RST.
	RCC_AHB1RSTR_ADC12RST = 0x20
	// Reset the selected module
	RCC_AHB1RSTR_ADC12RST_Reset = 0x1
	// Position of ETH1MACRST field.
	RCC_AHB1RSTR_ETH1MACRST_Pos = 0xf
	// Bit mask of ETH1MACRST field.
	RCC_AHB1RSTR_ETH1MACRST_Msk = 0x8000
	// Bit ETH1MACRST.
	RCC_AHB1RSTR_ETH1MACRST = 0x8000
	// Reset the selected module
	RCC_AHB1RSTR_ETH1MACRST_Reset = 0x1
	// Position of USB1OTGRST field.
	RCC_AHB1RSTR_USB1OTGRST_Pos = 0x19
	// Bit mask of USB1OTGRST field.
	RCC_AHB1RSTR_USB1OTGRST_Msk = 0x2000000
	// Bit USB1OTGRST.
	RCC_AHB1RSTR_USB1OTGRST = 0x2000000
	// Reset the selected module
	RCC_AHB1RSTR_USB1OTGRST_Reset = 0x1
	// Position of USB2OTGRST field.
	RCC_AHB1RSTR_USB2OTGRST_Pos = 0x1b
	// Bit mask of USB2OTGRST field.
	RCC_AHB1RSTR_USB2OTGRST_Msk = 0x8000000
	// Bit USB2OTGRST.
	RCC_AHB1RSTR_USB2OTGRST = 0x8000000
	// Reset the selected module
	RCC_AHB1RSTR_USB2OTGRST_Reset = 0x1

	// AHB2RSTR: RCC AHB2 Peripheral Reset Register
	// Position of CAMITFRST field.
	RCC_AHB2RSTR_CAMITFRST_Pos = 0x0
	// Bit mask of CAMITFRST field.
	RCC_AHB2RSTR_CAMITFRST_Msk = 0x1
	// Bit CAMITFRST.
	RCC_AHB2RSTR_CAMITFRST = 0x1
	// Reset the selected module
	RCC_AHB2RSTR_CAMITFRST_Reset = 0x1
	// Position of CRYPTRST field.
	RCC_AHB2RSTR_CRYPTRST_Pos = 0x4
	// Bit mask of CRYPTRST field.
	RCC_AHB2RSTR_CRYPTRST_Msk = 0x10
	// Bit CRYPTRST.
	RCC_AHB2RSTR_CRYPTRST = 0x10
	// Reset the selected module
	RCC_AHB2RSTR_CRYPTRST_Reset = 0x1
	// Position of HASHRST field.
	RCC_AHB2RSTR_HASHRST_Pos = 0x5
	// Bit mask of HASHRST field.
	RCC_AHB2RSTR_HASHRST_Msk = 0x20
	// Bit HASHRST.
	RCC_AHB2RSTR_HASHRST = 0x20
	// Reset the selected module
	RCC_AHB2RSTR_HASHRST_Reset = 0x1
	// Position of RNGRST field.
	RCC_AHB2RSTR_RNGRST_Pos = 0x6
	// Bit mask of RNGRST field.
	RCC_AHB2RSTR_RNGRST_Msk = 0x40
	// Bit RNGRST.
	RCC_AHB2RSTR_RNGRST = 0x40
	// Reset the selected module
	RCC_AHB2RSTR_RNGRST_Reset = 0x1
	// Position of SDMMC2RST field.
	RCC_AHB2RSTR_SDMMC2RST_Pos = 0x9
	// Bit mask of SDMMC2RST field.
	RCC_AHB2RSTR_SDMMC2RST_Msk = 0x200
	// Bit SDMMC2RST.
	RCC_AHB2RSTR_SDMMC2RST = 0x200
	// Reset the selected module
	RCC_AHB2RSTR_SDMMC2RST_Reset = 0x1

	// AHB4RSTR: RCC AHB4 Peripheral Reset Register
	// Position of GPIOARST field.
	RCC_AHB4RSTR_GPIOARST_Pos = 0x0
	// Bit mask of GPIOARST field.
	RCC_AHB4RSTR_GPIOARST_Msk = 0x1
	// Bit GPIOARST.
	RCC_AHB4RSTR_GPIOARST = 0x1
	// Reset the selected module
	RCC_AHB4RSTR_GPIOARST_Reset = 0x1
	// Position of GPIOBRST field.
	RCC_AHB4RSTR_GPIOBRST_Pos = 0x1
	// Bit mask of GPIOBRST field.
	RCC_AHB4RSTR_GPIOBRST_Msk = 0x2
	// Bit GPIOBRST.
	RCC_AHB4RSTR_GPIOBRST = 0x2
	// Reset the selected module
	RCC_AHB4RSTR_GPIOBRST_Reset = 0x1
	// Position of GPIOCRST field.
	RCC_AHB4RSTR_GPIOCRST_Pos = 0x2
	// Bit mask of GPIOCRST field.
	RCC_AHB4RSTR_GPIOCRST_Msk = 0x4
	// Bit GPIOCRST.
	RCC_AHB4RSTR_GPIOCRST = 0x4
	// Reset the selected module
	RCC_AHB4RSTR_GPIOCRST_Reset = 0x1
	// Position of GPIODRST field.
	RCC_AHB4RSTR_GPIODRST_Pos = 0x3
	// Bit mask of GPIODRST field.
	RCC_AHB4RSTR_GPIODRST_Msk = 0x8
	// Bit GPIODRST.
	RCC_AHB4RSTR_GPIODRST = 0x8
	// Reset the selected module
	RCC_AHB4RSTR_GPIODRST_Reset = 0x1
	// Position of GPIOERST field.
	RCC_AHB4RSTR_GPIOERST_Pos = 0x4
	// Bit mask of GPIOERST field.
	RCC_AHB4RSTR_GPIOERST_Msk = 0x10
	// Bit GPIOERST.
	RCC_AHB4RSTR_GPIOERST = 0x10
	// Reset the selected module
	RCC_AHB4RSTR_GPIOERST_Reset = 0x1
	// Position of GPIOFRST field.
	RCC_AHB4RSTR_GPIOFRST_Pos = 0x5
	// Bit mask of GPIOFRST field.
	RCC_AHB4RSTR_GPIOFRST_Msk = 0x20
	// Bit GPIOFRST.
	RCC_AHB4RSTR_GPIOFRST = 0x20
	// Reset the selected module
	RCC_AHB4RSTR_GPIOFRST_Reset = 0x1
	// Position of GPIOGRST field.
	RCC_AHB4RSTR_GPIOGRST_Pos = 0x6
	// Bit mask of GPIOGRST field.
	RCC_AHB4RSTR_GPIOGRST_Msk = 0x40
	// Bit GPIOGRST.
	RCC_AHB4RSTR_GPIOGRST = 0x40
	// Reset the selected module
	RCC_AHB4RSTR_GPIOGRST_Reset = 0x1
	// Position of GPIOHRST field.
	RCC_AHB4RSTR_GPIOHRST_Pos = 0x7
	// Bit mask of GPIOHRST field.
	RCC_AHB4RSTR_GPIOHRST_Msk = 0x80
	// Bit GPIOHRST.
	RCC_AHB4RSTR_GPIOHRST = 0x80
	// Reset the selected module
	RCC_AHB4RSTR_GPIOHRST_Reset = 0x1
	// Position of GPIOIRST field.
	RCC_AHB4RSTR_GPIOIRST_Pos = 0x8
	// Bit mask of GPIOIRST field.
	RCC_AHB4RSTR_GPIOIRST_Msk = 0x100
	// Bit GPIOIRST.
	RCC_AHB4RSTR_GPIOIRST = 0x100
	// Reset the selected module
	RCC_AHB4RSTR_GPIOIRST_Reset = 0x1
	// Position of GPIOJRST field.
	RCC_AHB4RSTR_GPIOJRST_Pos = 0x9
	// Bit mask of GPIOJRST field.
	RCC_AHB4RSTR_GPIOJRST_Msk = 0x200
	// Bit GPIOJRST.
	RCC_AHB4RSTR_GPIOJRST = 0x200
	// Reset the selected module
	RCC_AHB4RSTR_GPIOJRST_Reset = 0x1
	// Position of GPIOKRST field.
	RCC_AHB4RSTR_GPIOKRST_Pos = 0xa
	// Bit mask of GPIOKRST field.
	RCC_AHB4RSTR_GPIOKRST_Msk = 0x400
	// Bit GPIOKRST.
	RCC_AHB4RSTR_GPIOKRST = 0x400
	// Reset the selected module
	RCC_AHB4RSTR_GPIOKRST_Reset = 0x1
	// Position of CRCRST field.
	RCC_AHB4RSTR_CRCRST_Pos = 0x13
	// Bit mask of CRCRST field.
	RCC_AHB4RSTR_CRCRST_Msk = 0x80000
	// Bit CRCRST.
	RCC_AHB4RSTR_CRCRST = 0x80000
	// Reset the selected module
	RCC_AHB4RSTR_CRCRST_Reset = 0x1
	// Position of BDMARST field.
	RCC_AHB4RSTR_BDMARST_Pos = 0x15
	// Bit mask of BDMARST field.
	RCC_AHB4RSTR_BDMARST_Msk = 0x200000
	// Bit BDMARST.
	RCC_AHB4RSTR_BDMARST = 0x200000
	// Reset the selected module
	RCC_AHB4RSTR_BDMARST_Reset = 0x1
	// Position of ADC3RST field.
	RCC_AHB4RSTR_ADC3RST_Pos = 0x18
	// Bit mask of ADC3RST field.
	RCC_AHB4RSTR_ADC3RST_Msk = 0x1000000
	// Bit ADC3RST.
	RCC_AHB4RSTR_ADC3RST = 0x1000000
	// Reset the selected module
	RCC_AHB4RSTR_ADC3RST_Reset = 0x1
	// Position of HSEMRST field.
	RCC_AHB4RSTR_HSEMRST_Pos = 0x19
	// Bit mask of HSEMRST field.
	RCC_AHB4RSTR_HSEMRST_Msk = 0x2000000
	// Bit HSEMRST.
	RCC_AHB4RSTR_HSEMRST = 0x2000000
	// Reset the selected module
	RCC_AHB4RSTR_HSEMRST_Reset = 0x1

	// APB3RSTR: RCC APB3 Peripheral Reset Register
	// Position of LTDCRST field.
	RCC_APB3RSTR_LTDCRST_Pos = 0x3
	// Bit mask of LTDCRST field.
	RCC_APB3RSTR_LTDCRST_Msk = 0x8
	// Bit LTDCRST.
	RCC_APB3RSTR_LTDCRST = 0x8
	// Reset the selected module
	RCC_APB3RSTR_LTDCRST_Reset = 0x1

	// APB1LRSTR: RCC APB1 Peripheral Reset Register
	// Position of TIM2RST field.
	RCC_APB1LRSTR_TIM2RST_Pos = 0x0
	// Bit mask of TIM2RST field.
	RCC_APB1LRSTR_TIM2RST_Msk = 0x1
	// Bit TIM2RST.
	RCC_APB1LRSTR_TIM2RST = 0x1
	// Reset the selected module
	RCC_APB1LRSTR_TIM2RST_Reset = 0x1
	// Position of TIM3RST field.
	RCC_APB1LRSTR_TIM3RST_Pos = 0x1
	// Bit mask of TIM3RST field.
	RCC_APB1LRSTR_TIM3RST_Msk = 0x2
	// Bit TIM3RST.
	RCC_APB1LRSTR_TIM3RST = 0x2
	// Reset the selected module
	RCC_APB1LRSTR_TIM3RST_Reset = 0x1
	// Position of TIM4RST field.
	RCC_APB1LRSTR_TIM4RST_Pos = 0x2
	// Bit mask of TIM4RST field.
	RCC_APB1LRSTR_TIM4RST_Msk = 0x4
	// Bit TIM4RST.
	RCC_APB1LRSTR_TIM4RST = 0x4
	// Reset the selected module
	RCC_APB1LRSTR_TIM4RST_Reset = 0x1
	// Position of TIM5RST field.
	RCC_APB1LRSTR_TIM5RST_Pos = 0x3
	// Bit mask of TIM5RST field.
	RCC_APB1LRSTR_TIM5RST_Msk = 0x8
	// Bit TIM5RST.
	RCC_APB1LRSTR_TIM5RST = 0x8
	// Reset the selected module
	RCC_APB1LRSTR_TIM5RST_Reset = 0x1
	// Position of TIM6RST field.
	RCC_APB1LRSTR_TIM6RST_Pos = 0x4
	// Bit mask of TIM6RST field.
	RCC_APB1LRSTR_TIM6RST_Msk = 0x10
	// Bit TIM6RST.
	RCC_APB1LRSTR_TIM6RST = 0x10
	// Reset the selected module
	RCC_APB1LRSTR_TIM6RST_Reset = 0x1
	// Position of TIM7RST field.
	RCC_APB1LRSTR_TIM7RST_Pos = 0x5
	// Bit mask of TIM7RST field.
	RCC_APB1LRSTR_TIM7RST_Msk = 0x20
	// Bit TIM7RST.
	RCC_APB1LRSTR_TIM7RST = 0x20
	// Reset the selected module
	RCC_APB1LRSTR_TIM7RST_Reset = 0x1
	// Position of TIM12RST field.
	RCC_APB1LRSTR_TIM12RST_Pos = 0x6
	// Bit mask of TIM12RST field.
	RCC_APB1LRSTR_TIM12RST_Msk = 0x40
	// Bit TIM12RST.
	RCC_APB1LRSTR_TIM12RST = 0x40
	// Reset the selected module
	RCC_APB1LRSTR_TIM12RST_Reset = 0x1
	// Position of TIM13RST field.
	RCC_APB1LRSTR_TIM13RST_Pos = 0x7
	// Bit mask of TIM13RST field.
	RCC_APB1LRSTR_TIM13RST_Msk = 0x80
	// Bit TIM13RST.
	RCC_APB1LRSTR_TIM13RST = 0x80
	// Reset the selected module
	RCC_APB1LRSTR_TIM13RST_Reset = 0x1
	// Position of TIM14RST field.
	RCC_APB1LRSTR_TIM14RST_Pos = 0x8
	// Bit mask of TIM14RST field.
	RCC_APB1LRSTR_TIM14RST_Msk = 0x100
	// Bit TIM14RST.
	RCC_APB1LRSTR_TIM14RST = 0x100
	// Reset the selected module
	RCC_APB1LRSTR_TIM14RST_Reset = 0x1
	// Position of LPTIM1RST field.
	RCC_APB1LRSTR_LPTIM1RST_Pos = 0x9
	// Bit mask of LPTIM1RST field.
	RCC_APB1LRSTR_LPTIM1RST_Msk = 0x200
	// Bit LPTIM1RST.
	RCC_APB1LRSTR_LPTIM1RST = 0x200
	// Reset the selected module
	RCC_APB1LRSTR_LPTIM1RST_Reset = 0x1
	// Position of SPI2RST field.
	RCC_APB1LRSTR_SPI2RST_Pos = 0xe
	// Bit mask of SPI2RST field.
	RCC_APB1LRSTR_SPI2RST_Msk = 0x4000
	// Bit SPI2RST.
	RCC_APB1LRSTR_SPI2RST = 0x4000
	// Reset the selected module
	RCC_APB1LRSTR_SPI2RST_Reset = 0x1
	// Position of SPI3RST field.
	RCC_APB1LRSTR_SPI3RST_Pos = 0xf
	// Bit mask of SPI3RST field.
	RCC_APB1LRSTR_SPI3RST_Msk = 0x8000
	// Bit SPI3RST.
	RCC_APB1LRSTR_SPI3RST = 0x8000
	// Reset the selected module
	RCC_APB1LRSTR_SPI3RST_Reset = 0x1
	// Position of SPDIFRXRST field.
	RCC_APB1LRSTR_SPDIFRXRST_Pos = 0x10
	// Bit mask of SPDIFRXRST field.
	RCC_APB1LRSTR_SPDIFRXRST_Msk = 0x10000
	// Bit SPDIFRXRST.
	RCC_APB1LRSTR_SPDIFRXRST = 0x10000
	// Reset the selected module
	RCC_APB1LRSTR_SPDIFRXRST_Reset = 0x1
	// Position of USART2RST field.
	RCC_APB1LRSTR_USART2RST_Pos = 0x11
	// Bit mask of USART2RST field.
	RCC_APB1LRSTR_USART2RST_Msk = 0x20000
	// Bit USART2RST.
	RCC_APB1LRSTR_USART2RST = 0x20000
	// Reset the selected module
	RCC_APB1LRSTR_USART2RST_Reset = 0x1
	// Position of USART3RST field.
	RCC_APB1LRSTR_USART3RST_Pos = 0x12
	// Bit mask of USART3RST field.
	RCC_APB1LRSTR_USART3RST_Msk = 0x40000
	// Bit USART3RST.
	RCC_APB1LRSTR_USART3RST = 0x40000
	// Reset the selected module
	RCC_APB1LRSTR_USART3RST_Reset = 0x1
	// Position of UART4RST field.
	RCC_APB1LRSTR_UART4RST_Pos = 0x13
	// Bit mask of UART4RST field.
	RCC_APB1LRSTR_UART4RST_Msk = 0x80000
	// Bit UART4RST.
	RCC_APB1LRSTR_UART4RST = 0x80000
	// Reset the selected module
	RCC_APB1LRSTR_UART4RST_Reset = 0x1
	// Position of UART5RST field.
	RCC_APB1LRSTR_UART5RST_Pos = 0x14
	// Bit mask of UART5RST field.
	RCC_APB1LRSTR_UART5RST_Msk = 0x100000
	// Bit UART5RST.
	RCC_APB1LRSTR_UART5RST = 0x100000
	// Reset the selected module
	RCC_APB1LRSTR_UART5RST_Reset = 0x1
	// Position of I2C1RST field.
	RCC_APB1LRSTR_I2C1RST_Pos = 0x15
	// Bit mask of I2C1RST field.
	RCC_APB1LRSTR_I2C1RST_Msk = 0x200000
	// Bit I2C1RST.
	RCC_APB1LRSTR_I2C1RST = 0x200000
	// Reset the selected module
	RCC_APB1LRSTR_I2C1RST_Reset = 0x1
	// Position of I2C2RST field.
	RCC_APB1LRSTR_I2C2RST_Pos = 0x16
	// Bit mask of I2C2RST field.
	RCC_APB1LRSTR_I2C2RST_Msk = 0x400000
	// Bit I2C2RST.
	RCC_APB1LRSTR_I2C2RST = 0x400000
	// Reset the selected module
	RCC_APB1LRSTR_I2C2RST_Reset = 0x1
	// Position of I2C3RST field.
	RCC_APB1LRSTR_I2C3RST_Pos = 0x17
	// Bit mask of I2C3RST field.
	RCC_APB1LRSTR_I2C3RST_Msk = 0x800000
	// Bit I2C3RST.
	RCC_APB1LRSTR_I2C3RST = 0x800000
	// Reset the selected module
	RCC_APB1LRSTR_I2C3RST_Reset = 0x1
	// Position of CECRST field.
	RCC_APB1LRSTR_CECRST_Pos = 0x1b
	// Bit mask of CECRST field.
	RCC_APB1LRSTR_CECRST_Msk = 0x8000000
	// Bit CECRST.
	RCC_APB1LRSTR_CECRST = 0x8000000
	// Reset the selected module
	RCC_APB1LRSTR_CECRST_Reset = 0x1
	// Position of DAC12RST field.
	RCC_APB1LRSTR_DAC12RST_Pos = 0x1d
	// Bit mask of DAC12RST field.
	RCC_APB1LRSTR_DAC12RST_Msk = 0x20000000
	// Bit DAC12RST.
	RCC_APB1LRSTR_DAC12RST = 0x20000000
	// Reset the selected module
	RCC_APB1LRSTR_DAC12RST_Reset = 0x1
	// Position of UART7RST field.
	RCC_APB1LRSTR_UART7RST_Pos = 0x1e
	// Bit mask of UART7RST field.
	RCC_APB1LRSTR_UART7RST_Msk = 0x40000000
	// Bit UART7RST.
	RCC_APB1LRSTR_UART7RST = 0x40000000
	// Reset the selected module
	RCC_APB1LRSTR_UART7RST_Reset = 0x1
	// Position of UART8RST field.
	RCC_APB1LRSTR_UART8RST_Pos = 0x1f
	// Bit mask of UART8RST field.
	RCC_APB1LRSTR_UART8RST_Msk = 0x80000000
	// Bit UART8RST.
	RCC_APB1LRSTR_UART8RST = 0x80000000
	// Reset the selected module
	RCC_APB1LRSTR_UART8RST_Reset = 0x1

	// APB1HRSTR: RCC APB1 Peripheral Reset Register
	// Position of CRSRST field.
	RCC_APB1HRSTR_CRSRST_Pos = 0x1
	// Bit mask of CRSRST field.
	RCC_APB1HRSTR_CRSRST_Msk = 0x2
	// Bit CRSRST.
	RCC_APB1HRSTR_CRSRST = 0x2
	// Reset the selected module
	RCC_APB1HRSTR_CRSRST_Reset = 0x1
	// Position of SWPRST field.
	RCC_APB1HRSTR_SWPRST_Pos = 0x2
	// Bit mask of SWPRST field.
	RCC_APB1HRSTR_SWPRST_Msk = 0x4
	// Bit SWPRST.
	RCC_APB1HRSTR_SWPRST = 0x4
	// Reset the selected module
	RCC_APB1HRSTR_SWPRST_Reset = 0x1
	// Position of OPAMPRST field.
	RCC_APB1HRSTR_OPAMPRST_Pos = 0x4
	// Bit mask of OPAMPRST field.
	RCC_APB1HRSTR_OPAMPRST_Msk = 0x10
	// Bit OPAMPRST.
	RCC_APB1HRSTR_OPAMPRST = 0x10
	// Reset the selected module
	RCC_APB1HRSTR_OPAMPRST_Reset = 0x1
	// Position of MDIOSRST field.
	RCC_APB1HRSTR_MDIOSRST_Pos = 0x5
	// Bit mask of MDIOSRST field.
	RCC_APB1HRSTR_MDIOSRST_Msk = 0x20
	// Bit MDIOSRST.
	RCC_APB1HRSTR_MDIOSRST = 0x20
	// Reset the selected module
	RCC_APB1HRSTR_MDIOSRST_Reset = 0x1
	// Position of FDCANRST field.
	RCC_APB1HRSTR_FDCANRST_Pos = 0x8
	// Bit mask of FDCANRST field.
	RCC_APB1HRSTR_FDCANRST_Msk = 0x100
	// Bit FDCANRST.
	RCC_APB1HRSTR_FDCANRST = 0x100
	// Reset the selected module
	RCC_APB1HRSTR_FDCANRST_Reset = 0x1

	// APB2RSTR: RCC APB2 Peripheral Reset Register
	// Position of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Pos = 0x0
	// Bit mask of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Msk = 0x1
	// Bit TIM1RST.
	RCC_APB2RSTR_TIM1RST = 0x1
	// Reset the selected module
	RCC_APB2RSTR_TIM1RST_Reset = 0x1
	// Position of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Pos = 0x1
	// Bit mask of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Msk = 0x2
	// Bit TIM8RST.
	RCC_APB2RSTR_TIM8RST = 0x2
	// Reset the selected module
	RCC_APB2RSTR_TIM8RST_Reset = 0x1
	// Position of USART1RST field.
	RCC_APB2RSTR_USART1RST_Pos = 0x4
	// Bit mask of USART1RST field.
	RCC_APB2RSTR_USART1RST_Msk = 0x10
	// Bit USART1RST.
	RCC_APB2RSTR_USART1RST = 0x10
	// Reset the selected module
	RCC_APB2RSTR_USART1RST_Reset = 0x1
	// Position of USART6RST field.
	RCC_APB2RSTR_USART6RST_Pos = 0x5
	// Bit mask of USART6RST field.
	RCC_APB2RSTR_USART6RST_Msk = 0x20
	// Bit USART6RST.
	RCC_APB2RSTR_USART6RST = 0x20
	// Reset the selected module
	RCC_APB2RSTR_USART6RST_Reset = 0x1
	// Position of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Pos = 0xc
	// Bit mask of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Msk = 0x1000
	// Bit SPI1RST.
	RCC_APB2RSTR_SPI1RST = 0x1000
	// Reset the selected module
	RCC_APB2RSTR_SPI1RST_Reset = 0x1
	// Position of SPI4RST field.
	RCC_APB2RSTR_SPI4RST_Pos = 0xd
	// Bit mask of SPI4RST field.
	RCC_APB2RSTR_SPI4RST_Msk = 0x2000
	// Bit SPI4RST.
	RCC_APB2RSTR_SPI4RST = 0x2000
	// Reset the selected module
	RCC_APB2RSTR_SPI4RST_Reset = 0x1
	// Position of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Pos = 0x10
	// Bit mask of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Msk = 0x10000
	// Bit TIM15RST.
	RCC_APB2RSTR_TIM15RST = 0x10000
	// Reset the selected module
	RCC_APB2RSTR_TIM15RST_Reset = 0x1
	// Position of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Pos = 0x11
	// Bit mask of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Msk = 0x20000
	// Bit TIM16RST.
	RCC_APB2RSTR_TIM16RST = 0x20000
	// Reset the selected module
	RCC_APB2RSTR_TIM16RST_Reset = 0x1
	// Position of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Pos = 0x12
	// Bit mask of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Msk = 0x40000
	// Bit TIM17RST.
	RCC_APB2RSTR_TIM17RST = 0x40000
	// Reset the selected module
	RCC_APB2RSTR_TIM17RST_Reset = 0x1
	// Position of SPI5RST field.
	RCC_APB2RSTR_SPI5RST_Pos = 0x14
	// Bit mask of SPI5RST field.
	RCC_APB2RSTR_SPI5RST_Msk = 0x100000
	// Bit SPI5RST.
	RCC_APB2RSTR_SPI5RST = 0x100000
	// Reset the selected module
	RCC_APB2RSTR_SPI5RST_Reset = 0x1
	// Position of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Pos = 0x16
	// Bit mask of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Msk = 0x400000
	// Bit SAI1RST.
	RCC_APB2RSTR_SAI1RST = 0x400000
	// Reset the selected module
	RCC_APB2RSTR_SAI1RST_Reset = 0x1
	// Position of SAI2RST field.
	RCC_APB2RSTR_SAI2RST_Pos = 0x17
	// Bit mask of SAI2RST field.
	RCC_APB2RSTR_SAI2RST_Msk = 0x800000
	// Bit SAI2RST.
	RCC_APB2RSTR_SAI2RST = 0x800000
	// Reset the selected module
	RCC_APB2RSTR_SAI2RST_Reset = 0x1
	// Position of SAI3RST field.
	RCC_APB2RSTR_SAI3RST_Pos = 0x18
	// Bit mask of SAI3RST field.
	RCC_APB2RSTR_SAI3RST_Msk = 0x1000000
	// Bit SAI3RST.
	RCC_APB2RSTR_SAI3RST = 0x1000000
	// Reset the selected module
	RCC_APB2RSTR_SAI3RST_Reset = 0x1
	// Position of DFSDM1RST field.
	RCC_APB2RSTR_DFSDM1RST_Pos = 0x1c
	// Bit mask of DFSDM1RST field.
	RCC_APB2RSTR_DFSDM1RST_Msk = 0x10000000
	// Bit DFSDM1RST.
	RCC_APB2RSTR_DFSDM1RST = 0x10000000
	// Reset the selected module
	RCC_APB2RSTR_DFSDM1RST_Reset = 0x1
	// Position of HRTIMRST field.
	RCC_APB2RSTR_HRTIMRST_Pos = 0x1d
	// Bit mask of HRTIMRST field.
	RCC_APB2RSTR_HRTIMRST_Msk = 0x20000000
	// Bit HRTIMRST.
	RCC_APB2RSTR_HRTIMRST = 0x20000000
	// Reset the selected module
	RCC_APB2RSTR_HRTIMRST_Reset = 0x1

	// APB4RSTR: RCC APB4 Peripheral Reset Register
	// Position of SYSCFGRST field.
	RCC_APB4RSTR_SYSCFGRST_Pos = 0x1
	// Bit mask of SYSCFGRST field.
	RCC_APB4RSTR_SYSCFGRST_Msk = 0x2
	// Bit SYSCFGRST.
	RCC_APB4RSTR_SYSCFGRST = 0x2
	// Reset the selected module
	RCC_APB4RSTR_SYSCFGRST_Reset = 0x1
	// Position of LPUART1RST field.
	RCC_APB4RSTR_LPUART1RST_Pos = 0x3
	// Bit mask of LPUART1RST field.
	RCC_APB4RSTR_LPUART1RST_Msk = 0x8
	// Bit LPUART1RST.
	RCC_APB4RSTR_LPUART1RST = 0x8
	// Reset the selected module
	RCC_APB4RSTR_LPUART1RST_Reset = 0x1
	// Position of SPI6RST field.
	RCC_APB4RSTR_SPI6RST_Pos = 0x5
	// Bit mask of SPI6RST field.
	RCC_APB4RSTR_SPI6RST_Msk = 0x20
	// Bit SPI6RST.
	RCC_APB4RSTR_SPI6RST = 0x20
	// Reset the selected module
	RCC_APB4RSTR_SPI6RST_Reset = 0x1
	// Position of I2C4RST field.
	RCC_APB4RSTR_I2C4RST_Pos = 0x7
	// Bit mask of I2C4RST field.
	RCC_APB4RSTR_I2C4RST_Msk = 0x80
	// Bit I2C4RST.
	RCC_APB4RSTR_I2C4RST = 0x80
	// Reset the selected module
	RCC_APB4RSTR_I2C4RST_Reset = 0x1
	// Position of LPTIM2RST field.
	RCC_APB4RSTR_LPTIM2RST_Pos = 0x9
	// Bit mask of LPTIM2RST field.
	RCC_APB4RSTR_LPTIM2RST_Msk = 0x200
	// Bit LPTIM2RST.
	RCC_APB4RSTR_LPTIM2RST = 0x200
	// Reset the selected module
	RCC_APB4RSTR_LPTIM2RST_Reset = 0x1
	// Position of LPTIM3RST field.
	RCC_APB4RSTR_LPTIM3RST_Pos = 0xa
	// Bit mask of LPTIM3RST field.
	RCC_APB4RSTR_LPTIM3RST_Msk = 0x400
	// Bit LPTIM3RST.
	RCC_APB4RSTR_LPTIM3RST = 0x400
	// Reset the selected module
	RCC_APB4RSTR_LPTIM3RST_Reset = 0x1
	// Position of LPTIM4RST field.
	RCC_APB4RSTR_LPTIM4RST_Pos = 0xb
	// Bit mask of LPTIM4RST field.
	RCC_APB4RSTR_LPTIM4RST_Msk = 0x800
	// Bit LPTIM4RST.
	RCC_APB4RSTR_LPTIM4RST = 0x800
	// Reset the selected module
	RCC_APB4RSTR_LPTIM4RST_Reset = 0x1
	// Position of LPTIM5RST field.
	RCC_APB4RSTR_LPTIM5RST_Pos = 0xc
	// Bit mask of LPTIM5RST field.
	RCC_APB4RSTR_LPTIM5RST_Msk = 0x1000
	// Bit LPTIM5RST.
	RCC_APB4RSTR_LPTIM5RST = 0x1000
	// Reset the selected module
	RCC_APB4RSTR_LPTIM5RST_Reset = 0x1
	// Position of COMP12RST field.
	RCC_APB4RSTR_COMP12RST_Pos = 0xe
	// Bit mask of COMP12RST field.
	RCC_APB4RSTR_COMP12RST_Msk = 0x4000
	// Bit COMP12RST.
	RCC_APB4RSTR_COMP12RST = 0x4000
	// Reset the selected module
	RCC_APB4RSTR_COMP12RST_Reset = 0x1
	// Position of VREFRST field.
	RCC_APB4RSTR_VREFRST_Pos = 0xf
	// Bit mask of VREFRST field.
	RCC_APB4RSTR_VREFRST_Msk = 0x8000
	// Bit VREFRST.
	RCC_APB4RSTR_VREFRST = 0x8000
	// Reset the selected module
	RCC_APB4RSTR_VREFRST_Reset = 0x1
	// Position of SAI4RST field.
	RCC_APB4RSTR_SAI4RST_Pos = 0x15
	// Bit mask of SAI4RST field.
	RCC_APB4RSTR_SAI4RST_Msk = 0x200000
	// Bit SAI4RST.
	RCC_APB4RSTR_SAI4RST = 0x200000
	// Reset the selected module
	RCC_APB4RSTR_SAI4RST_Reset = 0x1

	// GCR: RCC Global Control Register
	// Position of WW1RSC field.
	RCC_GCR_WW1RSC_Pos = 0x0
	// Bit mask of WW1RSC field.
	RCC_GCR_WW1RSC_Msk = 0x1
	// Bit WW1RSC.
	RCC_GCR_WW1RSC = 0x1
	// Clear WWDG1 scope control
	RCC_GCR_WW1RSC_Clear = 0x0
	// Set WWDG1 scope control
	RCC_GCR_WW1RSC_Set = 0x1

	// D3AMR: RCC D3 Autonomous mode Register
	// Position of BDMAAMEN field.
	RCC_D3AMR_BDMAAMEN_Pos = 0x0
	// Bit mask of BDMAAMEN field.
	RCC_D3AMR_BDMAAMEN_Msk = 0x1
	// Bit BDMAAMEN.
	RCC_D3AMR_BDMAAMEN = 0x1
	// Clock disabled in autonomous mode
	RCC_D3AMR_BDMAAMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_BDMAAMEN_Enabled = 0x1
	// Position of LPUART1AMEN field.
	RCC_D3AMR_LPUART1AMEN_Pos = 0x3
	// Bit mask of LPUART1AMEN field.
	RCC_D3AMR_LPUART1AMEN_Msk = 0x8
	// Bit LPUART1AMEN.
	RCC_D3AMR_LPUART1AMEN = 0x8
	// Clock disabled in autonomous mode
	RCC_D3AMR_LPUART1AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_LPUART1AMEN_Enabled = 0x1
	// Position of SPI6AMEN field.
	RCC_D3AMR_SPI6AMEN_Pos = 0x5
	// Bit mask of SPI6AMEN field.
	RCC_D3AMR_SPI6AMEN_Msk = 0x20
	// Bit SPI6AMEN.
	RCC_D3AMR_SPI6AMEN = 0x20
	// Clock disabled in autonomous mode
	RCC_D3AMR_SPI6AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_SPI6AMEN_Enabled = 0x1
	// Position of I2C4AMEN field.
	RCC_D3AMR_I2C4AMEN_Pos = 0x7
	// Bit mask of I2C4AMEN field.
	RCC_D3AMR_I2C4AMEN_Msk = 0x80
	// Bit I2C4AMEN.
	RCC_D3AMR_I2C4AMEN = 0x80
	// Clock disabled in autonomous mode
	RCC_D3AMR_I2C4AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_I2C4AMEN_Enabled = 0x1
	// Position of LPTIM2AMEN field.
	RCC_D3AMR_LPTIM2AMEN_Pos = 0x9
	// Bit mask of LPTIM2AMEN field.
	RCC_D3AMR_LPTIM2AMEN_Msk = 0x200
	// Bit LPTIM2AMEN.
	RCC_D3AMR_LPTIM2AMEN = 0x200
	// Clock disabled in autonomous mode
	RCC_D3AMR_LPTIM2AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_LPTIM2AMEN_Enabled = 0x1
	// Position of LPTIM3AMEN field.
	RCC_D3AMR_LPTIM3AMEN_Pos = 0xa
	// Bit mask of LPTIM3AMEN field.
	RCC_D3AMR_LPTIM3AMEN_Msk = 0x400
	// Bit LPTIM3AMEN.
	RCC_D3AMR_LPTIM3AMEN = 0x400
	// Clock disabled in autonomous mode
	RCC_D3AMR_LPTIM3AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_LPTIM3AMEN_Enabled = 0x1
	// Position of LPTIM4AMEN field.
	RCC_D3AMR_LPTIM4AMEN_Pos = 0xb
	// Bit mask of LPTIM4AMEN field.
	RCC_D3AMR_LPTIM4AMEN_Msk = 0x800
	// Bit LPTIM4AMEN.
	RCC_D3AMR_LPTIM4AMEN = 0x800
	// Clock disabled in autonomous mode
	RCC_D3AMR_LPTIM4AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_LPTIM4AMEN_Enabled = 0x1
	// Position of LPTIM5AMEN field.
	RCC_D3AMR_LPTIM5AMEN_Pos = 0xc
	// Bit mask of LPTIM5AMEN field.
	RCC_D3AMR_LPTIM5AMEN_Msk = 0x1000
	// Bit LPTIM5AMEN.
	RCC_D3AMR_LPTIM5AMEN = 0x1000
	// Clock disabled in autonomous mode
	RCC_D3AMR_LPTIM5AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_LPTIM5AMEN_Enabled = 0x1
	// Position of COMP12AMEN field.
	RCC_D3AMR_COMP12AMEN_Pos = 0xe
	// Bit mask of COMP12AMEN field.
	RCC_D3AMR_COMP12AMEN_Msk = 0x4000
	// Bit COMP12AMEN.
	RCC_D3AMR_COMP12AMEN = 0x4000
	// Clock disabled in autonomous mode
	RCC_D3AMR_COMP12AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_COMP12AMEN_Enabled = 0x1
	// Position of VREFAMEN field.
	RCC_D3AMR_VREFAMEN_Pos = 0xf
	// Bit mask of VREFAMEN field.
	RCC_D3AMR_VREFAMEN_Msk = 0x8000
	// Bit VREFAMEN.
	RCC_D3AMR_VREFAMEN = 0x8000
	// Clock disabled in autonomous mode
	RCC_D3AMR_VREFAMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_VREFAMEN_Enabled = 0x1
	// Position of RTCAMEN field.
	RCC_D3AMR_RTCAMEN_Pos = 0x10
	// Bit mask of RTCAMEN field.
	RCC_D3AMR_RTCAMEN_Msk = 0x10000
	// Bit RTCAMEN.
	RCC_D3AMR_RTCAMEN = 0x10000
	// Clock disabled in autonomous mode
	RCC_D3AMR_RTCAMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_RTCAMEN_Enabled = 0x1
	// Position of CRCAMEN field.
	RCC_D3AMR_CRCAMEN_Pos = 0x13
	// Bit mask of CRCAMEN field.
	RCC_D3AMR_CRCAMEN_Msk = 0x80000
	// Bit CRCAMEN.
	RCC_D3AMR_CRCAMEN = 0x80000
	// Clock disabled in autonomous mode
	RCC_D3AMR_CRCAMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_CRCAMEN_Enabled = 0x1
	// Position of SAI4AMEN field.
	RCC_D3AMR_SAI4AMEN_Pos = 0x15
	// Bit mask of SAI4AMEN field.
	RCC_D3AMR_SAI4AMEN_Msk = 0x200000
	// Bit SAI4AMEN.
	RCC_D3AMR_SAI4AMEN = 0x200000
	// Clock disabled in autonomous mode
	RCC_D3AMR_SAI4AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_SAI4AMEN_Enabled = 0x1
	// Position of ADC3AMEN field.
	RCC_D3AMR_ADC3AMEN_Pos = 0x18
	// Bit mask of ADC3AMEN field.
	RCC_D3AMR_ADC3AMEN_Msk = 0x1000000
	// Bit ADC3AMEN.
	RCC_D3AMR_ADC3AMEN = 0x1000000
	// Clock disabled in autonomous mode
	RCC_D3AMR_ADC3AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_ADC3AMEN_Enabled = 0x1
	// Position of BKPRAMAMEN field.
	RCC_D3AMR_BKPRAMAMEN_Pos = 0x1c
	// Bit mask of BKPRAMAMEN field.
	RCC_D3AMR_BKPRAMAMEN_Msk = 0x10000000
	// Bit BKPRAMAMEN.
	RCC_D3AMR_BKPRAMAMEN = 0x10000000
	// Clock disabled in autonomous mode
	RCC_D3AMR_BKPRAMAMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_BKPRAMAMEN_Enabled = 0x1
	// Position of SRAM4AMEN field.
	RCC_D3AMR_SRAM4AMEN_Pos = 0x1d
	// Bit mask of SRAM4AMEN field.
	RCC_D3AMR_SRAM4AMEN_Msk = 0x20000000
	// Bit SRAM4AMEN.
	RCC_D3AMR_SRAM4AMEN = 0x20000000
	// Clock disabled in autonomous mode
	RCC_D3AMR_SRAM4AMEN_Disabled = 0x0
	// Clock enabled in autonomous mode
	RCC_D3AMR_SRAM4AMEN_Enabled = 0x1

	// RSR: RCC Reset Status Register
	// Position of RMVF field.
	RCC_RSR_RMVF_Pos = 0x10
	// Bit mask of RMVF field.
	RCC_RSR_RMVF_Msk = 0x10000
	// Bit RMVF.
	RCC_RSR_RMVF = 0x10000
	// Not clearing the the reset flags
	RCC_RSR_RMVF_NotActive = 0x0
	// Clear the reset flags
	RCC_RSR_RMVF_Clear = 0x1
	// Position of CPURSTF field.
	RCC_RSR_CPURSTF_Pos = 0x11
	// Bit mask of CPURSTF field.
	RCC_RSR_CPURSTF_Msk = 0x20000
	// Bit CPURSTF.
	RCC_RSR_CPURSTF = 0x20000
	// No reset occoured for block
	RCC_RSR_CPURSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_CPURSTF_ResetOccourred = 0x1
	// Position of D1RSTF field.
	RCC_RSR_D1RSTF_Pos = 0x13
	// Bit mask of D1RSTF field.
	RCC_RSR_D1RSTF_Msk = 0x80000
	// Bit D1RSTF.
	RCC_RSR_D1RSTF = 0x80000
	// No reset occoured for block
	RCC_RSR_D1RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_D1RSTF_ResetOccourred = 0x1
	// Position of D2RSTF field.
	RCC_RSR_D2RSTF_Pos = 0x14
	// Bit mask of D2RSTF field.
	RCC_RSR_D2RSTF_Msk = 0x100000
	// Bit D2RSTF.
	RCC_RSR_D2RSTF = 0x100000
	// No reset occoured for block
	RCC_RSR_D2RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_D2RSTF_ResetOccourred = 0x1
	// Position of BORRSTF field.
	RCC_RSR_BORRSTF_Pos = 0x15
	// Bit mask of BORRSTF field.
	RCC_RSR_BORRSTF_Msk = 0x200000
	// Bit BORRSTF.
	RCC_RSR_BORRSTF = 0x200000
	// No reset occoured for block
	RCC_RSR_BORRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_BORRSTF_ResetOccourred = 0x1
	// Position of PINRSTF field.
	RCC_RSR_PINRSTF_Pos = 0x16
	// Bit mask of PINRSTF field.
	RCC_RSR_PINRSTF_Msk = 0x400000
	// Bit PINRSTF.
	RCC_RSR_PINRSTF = 0x400000
	// No reset occoured for block
	RCC_RSR_PINRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_PINRSTF_ResetOccourred = 0x1
	// Position of PORRSTF field.
	RCC_RSR_PORRSTF_Pos = 0x17
	// Bit mask of PORRSTF field.
	RCC_RSR_PORRSTF_Msk = 0x800000
	// Bit PORRSTF.
	RCC_RSR_PORRSTF = 0x800000
	// No reset occoured for block
	RCC_RSR_PORRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_PORRSTF_ResetOccourred = 0x1
	// Position of SFTRSTF field.
	RCC_RSR_SFTRSTF_Pos = 0x18
	// Bit mask of SFTRSTF field.
	RCC_RSR_SFTRSTF_Msk = 0x1000000
	// Bit SFTRSTF.
	RCC_RSR_SFTRSTF = 0x1000000
	// No reset occoured for block
	RCC_RSR_SFTRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_SFTRSTF_ResetOccourred = 0x1
	// Position of IWDG1RSTF field.
	RCC_RSR_IWDG1RSTF_Pos = 0x1a
	// Bit mask of IWDG1RSTF field.
	RCC_RSR_IWDG1RSTF_Msk = 0x4000000
	// Bit IWDG1RSTF.
	RCC_RSR_IWDG1RSTF = 0x4000000
	// No reset occoured for block
	RCC_RSR_IWDG1RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_IWDG1RSTF_ResetOccourred = 0x1
	// Position of WWDG1RSTF field.
	RCC_RSR_WWDG1RSTF_Pos = 0x1c
	// Bit mask of WWDG1RSTF field.
	RCC_RSR_WWDG1RSTF_Msk = 0x10000000
	// Bit WWDG1RSTF.
	RCC_RSR_WWDG1RSTF = 0x10000000
	// No reset occoured for block
	RCC_RSR_WWDG1RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_WWDG1RSTF_ResetOccourred = 0x1
	// Position of LPWRRSTF field.
	RCC_RSR_LPWRRSTF_Pos = 0x1e
	// Bit mask of LPWRRSTF field.
	RCC_RSR_LPWRRSTF_Msk = 0x40000000
	// Bit LPWRRSTF.
	RCC_RSR_LPWRRSTF = 0x40000000
	// No reset occoured for block
	RCC_RSR_LPWRRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_RSR_LPWRRSTF_ResetOccourred = 0x1

	// AHB3ENR: RCC AHB3 Clock Register
	// Position of MDMAEN field.
	RCC_AHB3ENR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_AHB3ENR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_AHB3ENR_MDMAEN = 0x1
	// The selected clock is disabled
	RCC_AHB3ENR_MDMAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_MDMAEN_Enabled = 0x1
	// Position of DMA2DEN field.
	RCC_AHB3ENR_DMA2DEN_Pos = 0x4
	// Bit mask of DMA2DEN field.
	RCC_AHB3ENR_DMA2DEN_Msk = 0x10
	// Bit DMA2DEN.
	RCC_AHB3ENR_DMA2DEN = 0x10
	// The selected clock is disabled
	RCC_AHB3ENR_DMA2DEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_DMA2DEN_Enabled = 0x1
	// Position of JPGDECEN field.
	RCC_AHB3ENR_JPGDECEN_Pos = 0x5
	// Bit mask of JPGDECEN field.
	RCC_AHB3ENR_JPGDECEN_Msk = 0x20
	// Bit JPGDECEN.
	RCC_AHB3ENR_JPGDECEN = 0x20
	// The selected clock is disabled
	RCC_AHB3ENR_JPGDECEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_JPGDECEN_Enabled = 0x1
	// Position of FMCEN field.
	RCC_AHB3ENR_FMCEN_Pos = 0xc
	// Bit mask of FMCEN field.
	RCC_AHB3ENR_FMCEN_Msk = 0x1000
	// Bit FMCEN.
	RCC_AHB3ENR_FMCEN = 0x1000
	// The selected clock is disabled
	RCC_AHB3ENR_FMCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_FMCEN_Enabled = 0x1
	// Position of QSPIEN field.
	RCC_AHB3ENR_QSPIEN_Pos = 0xe
	// Bit mask of QSPIEN field.
	RCC_AHB3ENR_QSPIEN_Msk = 0x4000
	// Bit QSPIEN.
	RCC_AHB3ENR_QSPIEN = 0x4000
	// The selected clock is disabled
	RCC_AHB3ENR_QSPIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_QSPIEN_Enabled = 0x1
	// Position of SDMMC1EN field.
	RCC_AHB3ENR_SDMMC1EN_Pos = 0x10
	// Bit mask of SDMMC1EN field.
	RCC_AHB3ENR_SDMMC1EN_Msk = 0x10000
	// Bit SDMMC1EN.
	RCC_AHB3ENR_SDMMC1EN = 0x10000
	// The selected clock is disabled
	RCC_AHB3ENR_SDMMC1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_SDMMC1EN_Enabled = 0x1

	// AHB1ENR: RCC AHB1 Clock Register
	// Position of DMA1EN field.
	RCC_AHB1ENR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_AHB1ENR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_AHB1ENR_DMA1EN = 0x1
	// The selected clock is disabled
	RCC_AHB1ENR_DMA1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_DMA1EN_Enabled = 0x1
	// Position of DMA2EN field.
	RCC_AHB1ENR_DMA2EN_Pos = 0x1
	// Bit mask of DMA2EN field.
	RCC_AHB1ENR_DMA2EN_Msk = 0x2
	// Bit DMA2EN.
	RCC_AHB1ENR_DMA2EN = 0x2
	// The selected clock is disabled
	RCC_AHB1ENR_DMA2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_DMA2EN_Enabled = 0x1
	// Position of ADC12EN field.
	RCC_AHB1ENR_ADC12EN_Pos = 0x5
	// Bit mask of ADC12EN field.
	RCC_AHB1ENR_ADC12EN_Msk = 0x20
	// Bit ADC12EN.
	RCC_AHB1ENR_ADC12EN = 0x20
	// The selected clock is disabled
	RCC_AHB1ENR_ADC12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_ADC12EN_Enabled = 0x1
	// Position of ETH1MACEN field.
	RCC_AHB1ENR_ETH1MACEN_Pos = 0xf
	// Bit mask of ETH1MACEN field.
	RCC_AHB1ENR_ETH1MACEN_Msk = 0x8000
	// Bit ETH1MACEN.
	RCC_AHB1ENR_ETH1MACEN = 0x8000
	// The selected clock is disabled
	RCC_AHB1ENR_ETH1MACEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_ETH1MACEN_Enabled = 0x1
	// Position of ETH1TXEN field.
	RCC_AHB1ENR_ETH1TXEN_Pos = 0x10
	// Bit mask of ETH1TXEN field.
	RCC_AHB1ENR_ETH1TXEN_Msk = 0x10000
	// Bit ETH1TXEN.
	RCC_AHB1ENR_ETH1TXEN = 0x10000
	// The selected clock is disabled
	RCC_AHB1ENR_ETH1TXEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_ETH1TXEN_Enabled = 0x1
	// Position of ETH1RXEN field.
	RCC_AHB1ENR_ETH1RXEN_Pos = 0x11
	// Bit mask of ETH1RXEN field.
	RCC_AHB1ENR_ETH1RXEN_Msk = 0x20000
	// Bit ETH1RXEN.
	RCC_AHB1ENR_ETH1RXEN = 0x20000
	// The selected clock is disabled
	RCC_AHB1ENR_ETH1RXEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_ETH1RXEN_Enabled = 0x1
	// Position of USB2OTGHSULPIEN field.
	RCC_AHB1ENR_USB2OTGHSULPIEN_Pos = 0x12
	// Bit mask of USB2OTGHSULPIEN field.
	RCC_AHB1ENR_USB2OTGHSULPIEN_Msk = 0x40000
	// Bit USB2OTGHSULPIEN.
	RCC_AHB1ENR_USB2OTGHSULPIEN = 0x40000
	// The selected clock is disabled
	RCC_AHB1ENR_USB2OTGHSULPIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_USB2OTGHSULPIEN_Enabled = 0x1
	// Position of USB1OTGEN field.
	RCC_AHB1ENR_USB1OTGEN_Pos = 0x19
	// Bit mask of USB1OTGEN field.
	RCC_AHB1ENR_USB1OTGEN_Msk = 0x2000000
	// Bit USB1OTGEN.
	RCC_AHB1ENR_USB1OTGEN = 0x2000000
	// The selected clock is disabled
	RCC_AHB1ENR_USB1OTGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_USB1OTGEN_Enabled = 0x1
	// Position of USB1ULPIEN field.
	RCC_AHB1ENR_USB1ULPIEN_Pos = 0x1a
	// Bit mask of USB1ULPIEN field.
	RCC_AHB1ENR_USB1ULPIEN_Msk = 0x4000000
	// Bit USB1ULPIEN.
	RCC_AHB1ENR_USB1ULPIEN = 0x4000000
	// The selected clock is disabled
	RCC_AHB1ENR_USB1ULPIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_USB1ULPIEN_Enabled = 0x1
	// Position of USB2OTGEN field.
	RCC_AHB1ENR_USB2OTGEN_Pos = 0x1b
	// Bit mask of USB2OTGEN field.
	RCC_AHB1ENR_USB2OTGEN_Msk = 0x8000000
	// Bit USB2OTGEN.
	RCC_AHB1ENR_USB2OTGEN = 0x8000000
	// The selected clock is disabled
	RCC_AHB1ENR_USB2OTGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_USB2OTGEN_Enabled = 0x1
	// Position of USB2ULPIEN field.
	RCC_AHB1ENR_USB2ULPIEN_Pos = 0x1c
	// Bit mask of USB2ULPIEN field.
	RCC_AHB1ENR_USB2ULPIEN_Msk = 0x10000000
	// Bit USB2ULPIEN.
	RCC_AHB1ENR_USB2ULPIEN = 0x10000000
	// The selected clock is disabled
	RCC_AHB1ENR_USB2ULPIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_USB2ULPIEN_Enabled = 0x1

	// AHB2ENR: RCC AHB2 Clock Register
	// Position of DCMIEN field.
	RCC_AHB2ENR_DCMIEN_Pos = 0x0
	// Bit mask of DCMIEN field.
	RCC_AHB2ENR_DCMIEN_Msk = 0x1
	// Bit DCMIEN.
	RCC_AHB2ENR_DCMIEN = 0x1
	// The selected clock is disabled
	RCC_AHB2ENR_DCMIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_DCMIEN_Enabled = 0x1
	// Position of CRYPTEN field.
	RCC_AHB2ENR_CRYPTEN_Pos = 0x4
	// Bit mask of CRYPTEN field.
	RCC_AHB2ENR_CRYPTEN_Msk = 0x10
	// Bit CRYPTEN.
	RCC_AHB2ENR_CRYPTEN = 0x10
	// The selected clock is disabled
	RCC_AHB2ENR_CRYPTEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_CRYPTEN_Enabled = 0x1
	// Position of HASHEN field.
	RCC_AHB2ENR_HASHEN_Pos = 0x5
	// Bit mask of HASHEN field.
	RCC_AHB2ENR_HASHEN_Msk = 0x20
	// Bit HASHEN.
	RCC_AHB2ENR_HASHEN = 0x20
	// The selected clock is disabled
	RCC_AHB2ENR_HASHEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_HASHEN_Enabled = 0x1
	// Position of RNGEN field.
	RCC_AHB2ENR_RNGEN_Pos = 0x6
	// Bit mask of RNGEN field.
	RCC_AHB2ENR_RNGEN_Msk = 0x40
	// Bit RNGEN.
	RCC_AHB2ENR_RNGEN = 0x40
	// The selected clock is disabled
	RCC_AHB2ENR_RNGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_RNGEN_Enabled = 0x1
	// Position of SDMMC2EN field.
	RCC_AHB2ENR_SDMMC2EN_Pos = 0x9
	// Bit mask of SDMMC2EN field.
	RCC_AHB2ENR_SDMMC2EN_Msk = 0x200
	// Bit SDMMC2EN.
	RCC_AHB2ENR_SDMMC2EN = 0x200
	// The selected clock is disabled
	RCC_AHB2ENR_SDMMC2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_SDMMC2EN_Enabled = 0x1
	// Position of SRAM1EN field.
	RCC_AHB2ENR_SRAM1EN_Pos = 0x1d
	// Bit mask of SRAM1EN field.
	RCC_AHB2ENR_SRAM1EN_Msk = 0x20000000
	// Bit SRAM1EN.
	RCC_AHB2ENR_SRAM1EN = 0x20000000
	// The selected clock is disabled
	RCC_AHB2ENR_SRAM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_SRAM1EN_Enabled = 0x1
	// Position of SRAM2EN field.
	RCC_AHB2ENR_SRAM2EN_Pos = 0x1e
	// Bit mask of SRAM2EN field.
	RCC_AHB2ENR_SRAM2EN_Msk = 0x40000000
	// Bit SRAM2EN.
	RCC_AHB2ENR_SRAM2EN = 0x40000000
	// The selected clock is disabled
	RCC_AHB2ENR_SRAM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_SRAM2EN_Enabled = 0x1
	// Position of SRAM3EN field.
	RCC_AHB2ENR_SRAM3EN_Pos = 0x1f
	// Bit mask of SRAM3EN field.
	RCC_AHB2ENR_SRAM3EN_Msk = 0x80000000
	// Bit SRAM3EN.
	RCC_AHB2ENR_SRAM3EN = 0x80000000
	// The selected clock is disabled
	RCC_AHB2ENR_SRAM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_SRAM3EN_Enabled = 0x1

	// AHB4ENR: RCC AHB4 Clock Register
	// Position of GPIOAEN field.
	RCC_AHB4ENR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_AHB4ENR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_AHB4ENR_GPIOAEN = 0x1
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOAEN_Enabled = 0x1
	// Position of GPIOBEN field.
	RCC_AHB4ENR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_AHB4ENR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_AHB4ENR_GPIOBEN = 0x2
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOBEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOBEN_Enabled = 0x1
	// Position of GPIOCEN field.
	RCC_AHB4ENR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_AHB4ENR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_AHB4ENR_GPIOCEN = 0x4
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOCEN_Enabled = 0x1
	// Position of GPIODEN field.
	RCC_AHB4ENR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_AHB4ENR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_AHB4ENR_GPIODEN = 0x8
	// The selected clock is disabled
	RCC_AHB4ENR_GPIODEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIODEN_Enabled = 0x1
	// Position of GPIOEEN field.
	RCC_AHB4ENR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_AHB4ENR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_AHB4ENR_GPIOEEN = 0x10
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOEEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOEEN_Enabled = 0x1
	// Position of GPIOFEN field.
	RCC_AHB4ENR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_AHB4ENR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_AHB4ENR_GPIOFEN = 0x20
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOFEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOFEN_Enabled = 0x1
	// Position of GPIOGEN field.
	RCC_AHB4ENR_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_AHB4ENR_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_AHB4ENR_GPIOGEN = 0x40
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOGEN_Enabled = 0x1
	// Position of GPIOHEN field.
	RCC_AHB4ENR_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_AHB4ENR_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_AHB4ENR_GPIOHEN = 0x80
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOHEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOHEN_Enabled = 0x1
	// Position of GPIOIEN field.
	RCC_AHB4ENR_GPIOIEN_Pos = 0x8
	// Bit mask of GPIOIEN field.
	RCC_AHB4ENR_GPIOIEN_Msk = 0x100
	// Bit GPIOIEN.
	RCC_AHB4ENR_GPIOIEN = 0x100
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOIEN_Enabled = 0x1
	// Position of GPIOJEN field.
	RCC_AHB4ENR_GPIOJEN_Pos = 0x9
	// Bit mask of GPIOJEN field.
	RCC_AHB4ENR_GPIOJEN_Msk = 0x200
	// Bit GPIOJEN.
	RCC_AHB4ENR_GPIOJEN = 0x200
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOJEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOJEN_Enabled = 0x1
	// Position of GPIOKEN field.
	RCC_AHB4ENR_GPIOKEN_Pos = 0xa
	// Bit mask of GPIOKEN field.
	RCC_AHB4ENR_GPIOKEN_Msk = 0x400
	// Bit GPIOKEN.
	RCC_AHB4ENR_GPIOKEN = 0x400
	// The selected clock is disabled
	RCC_AHB4ENR_GPIOKEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_GPIOKEN_Enabled = 0x1
	// Position of CRCEN field.
	RCC_AHB4ENR_CRCEN_Pos = 0x13
	// Bit mask of CRCEN field.
	RCC_AHB4ENR_CRCEN_Msk = 0x80000
	// Bit CRCEN.
	RCC_AHB4ENR_CRCEN = 0x80000
	// The selected clock is disabled
	RCC_AHB4ENR_CRCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_CRCEN_Enabled = 0x1
	// Position of BDMAEN field.
	RCC_AHB4ENR_BDMAEN_Pos = 0x15
	// Bit mask of BDMAEN field.
	RCC_AHB4ENR_BDMAEN_Msk = 0x200000
	// Bit BDMAEN.
	RCC_AHB4ENR_BDMAEN = 0x200000
	// The selected clock is disabled
	RCC_AHB4ENR_BDMAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_BDMAEN_Enabled = 0x1
	// Position of ADC3EN field.
	RCC_AHB4ENR_ADC3EN_Pos = 0x18
	// Bit mask of ADC3EN field.
	RCC_AHB4ENR_ADC3EN_Msk = 0x1000000
	// Bit ADC3EN.
	RCC_AHB4ENR_ADC3EN = 0x1000000
	// The selected clock is disabled
	RCC_AHB4ENR_ADC3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_ADC3EN_Enabled = 0x1
	// Position of HSEMEN field.
	RCC_AHB4ENR_HSEMEN_Pos = 0x19
	// Bit mask of HSEMEN field.
	RCC_AHB4ENR_HSEMEN_Msk = 0x2000000
	// Bit HSEMEN.
	RCC_AHB4ENR_HSEMEN = 0x2000000
	// The selected clock is disabled
	RCC_AHB4ENR_HSEMEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_HSEMEN_Enabled = 0x1
	// Position of BKPRAMEN field.
	RCC_AHB4ENR_BKPRAMEN_Pos = 0x1c
	// Bit mask of BKPRAMEN field.
	RCC_AHB4ENR_BKPRAMEN_Msk = 0x10000000
	// Bit BKPRAMEN.
	RCC_AHB4ENR_BKPRAMEN = 0x10000000
	// The selected clock is disabled
	RCC_AHB4ENR_BKPRAMEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB4ENR_BKPRAMEN_Enabled = 0x1

	// APB3ENR: RCC APB3 Clock Register
	// Position of LTDCEN field.
	RCC_APB3ENR_LTDCEN_Pos = 0x3
	// Bit mask of LTDCEN field.
	RCC_APB3ENR_LTDCEN_Msk = 0x8
	// Bit LTDCEN.
	RCC_APB3ENR_LTDCEN = 0x8
	// The selected clock is disabled
	RCC_APB3ENR_LTDCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB3ENR_LTDCEN_Enabled = 0x1
	// Position of WWDG1EN field.
	RCC_APB3ENR_WWDG1EN_Pos = 0x6
	// Bit mask of WWDG1EN field.
	RCC_APB3ENR_WWDG1EN_Msk = 0x40
	// Bit WWDG1EN.
	RCC_APB3ENR_WWDG1EN = 0x40
	// The selected clock is disabled
	RCC_APB3ENR_WWDG1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB3ENR_WWDG1EN_Enabled = 0x1

	// APB1LENR: RCC APB1 Clock Register
	// Position of TIM2EN field.
	RCC_APB1LENR_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_APB1LENR_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_APB1LENR_TIM2EN = 0x1
	// The selected clock is disabled
	RCC_APB1LENR_TIM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM2EN_Enabled = 0x1
	// Position of TIM3EN field.
	RCC_APB1LENR_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_APB1LENR_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_APB1LENR_TIM3EN = 0x2
	// The selected clock is disabled
	RCC_APB1LENR_TIM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM3EN_Enabled = 0x1
	// Position of TIM4EN field.
	RCC_APB1LENR_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_APB1LENR_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_APB1LENR_TIM4EN = 0x4
	// The selected clock is disabled
	RCC_APB1LENR_TIM4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM4EN_Enabled = 0x1
	// Position of TIM5EN field.
	RCC_APB1LENR_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_APB1LENR_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_APB1LENR_TIM5EN = 0x8
	// The selected clock is disabled
	RCC_APB1LENR_TIM5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM5EN_Enabled = 0x1
	// Position of TIM6EN field.
	RCC_APB1LENR_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_APB1LENR_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_APB1LENR_TIM6EN = 0x10
	// The selected clock is disabled
	RCC_APB1LENR_TIM6EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM6EN_Enabled = 0x1
	// Position of TIM7EN field.
	RCC_APB1LENR_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_APB1LENR_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_APB1LENR_TIM7EN = 0x20
	// The selected clock is disabled
	RCC_APB1LENR_TIM7EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM7EN_Enabled = 0x1
	// Position of TIM12EN field.
	RCC_APB1LENR_TIM12EN_Pos = 0x6
	// Bit mask of TIM12EN field.
	RCC_APB1LENR_TIM12EN_Msk = 0x40
	// Bit TIM12EN.
	RCC_APB1LENR_TIM12EN = 0x40
	// The selected clock is disabled
	RCC_APB1LENR_TIM12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM12EN_Enabled = 0x1
	// Position of TIM13EN field.
	RCC_APB1LENR_TIM13EN_Pos = 0x7
	// Bit mask of TIM13EN field.
	RCC_APB1LENR_TIM13EN_Msk = 0x80
	// Bit TIM13EN.
	RCC_APB1LENR_TIM13EN = 0x80
	// The selected clock is disabled
	RCC_APB1LENR_TIM13EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM13EN_Enabled = 0x1
	// Position of TIM14EN field.
	RCC_APB1LENR_TIM14EN_Pos = 0x8
	// Bit mask of TIM14EN field.
	RCC_APB1LENR_TIM14EN_Msk = 0x100
	// Bit TIM14EN.
	RCC_APB1LENR_TIM14EN = 0x100
	// The selected clock is disabled
	RCC_APB1LENR_TIM14EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_TIM14EN_Enabled = 0x1
	// Position of LPTIM1EN field.
	RCC_APB1LENR_LPTIM1EN_Pos = 0x9
	// Bit mask of LPTIM1EN field.
	RCC_APB1LENR_LPTIM1EN_Msk = 0x200
	// Bit LPTIM1EN.
	RCC_APB1LENR_LPTIM1EN = 0x200
	// The selected clock is disabled
	RCC_APB1LENR_LPTIM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_LPTIM1EN_Enabled = 0x1
	// Position of SPI2EN field.
	RCC_APB1LENR_SPI2EN_Pos = 0xe
	// Bit mask of SPI2EN field.
	RCC_APB1LENR_SPI2EN_Msk = 0x4000
	// Bit SPI2EN.
	RCC_APB1LENR_SPI2EN = 0x4000
	// The selected clock is disabled
	RCC_APB1LENR_SPI2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_SPI2EN_Enabled = 0x1
	// Position of SPI3EN field.
	RCC_APB1LENR_SPI3EN_Pos = 0xf
	// Bit mask of SPI3EN field.
	RCC_APB1LENR_SPI3EN_Msk = 0x8000
	// Bit SPI3EN.
	RCC_APB1LENR_SPI3EN = 0x8000
	// The selected clock is disabled
	RCC_APB1LENR_SPI3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_SPI3EN_Enabled = 0x1
	// Position of SPDIFRXEN field.
	RCC_APB1LENR_SPDIFRXEN_Pos = 0x10
	// Bit mask of SPDIFRXEN field.
	RCC_APB1LENR_SPDIFRXEN_Msk = 0x10000
	// Bit SPDIFRXEN.
	RCC_APB1LENR_SPDIFRXEN = 0x10000
	// The selected clock is disabled
	RCC_APB1LENR_SPDIFRXEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_SPDIFRXEN_Enabled = 0x1
	// Position of USART2EN field.
	RCC_APB1LENR_USART2EN_Pos = 0x11
	// Bit mask of USART2EN field.
	RCC_APB1LENR_USART2EN_Msk = 0x20000
	// Bit USART2EN.
	RCC_APB1LENR_USART2EN = 0x20000
	// The selected clock is disabled
	RCC_APB1LENR_USART2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_USART2EN_Enabled = 0x1
	// Position of USART3EN field.
	RCC_APB1LENR_USART3EN_Pos = 0x12
	// Bit mask of USART3EN field.
	RCC_APB1LENR_USART3EN_Msk = 0x40000
	// Bit USART3EN.
	RCC_APB1LENR_USART3EN = 0x40000
	// The selected clock is disabled
	RCC_APB1LENR_USART3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_USART3EN_Enabled = 0x1
	// Position of UART4EN field.
	RCC_APB1LENR_UART4EN_Pos = 0x13
	// Bit mask of UART4EN field.
	RCC_APB1LENR_UART4EN_Msk = 0x80000
	// Bit UART4EN.
	RCC_APB1LENR_UART4EN = 0x80000
	// The selected clock is disabled
	RCC_APB1LENR_UART4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_UART4EN_Enabled = 0x1
	// Position of UART5EN field.
	RCC_APB1LENR_UART5EN_Pos = 0x14
	// Bit mask of UART5EN field.
	RCC_APB1LENR_UART5EN_Msk = 0x100000
	// Bit UART5EN.
	RCC_APB1LENR_UART5EN = 0x100000
	// The selected clock is disabled
	RCC_APB1LENR_UART5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_UART5EN_Enabled = 0x1
	// Position of I2C1EN field.
	RCC_APB1LENR_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_APB1LENR_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_APB1LENR_I2C1EN = 0x200000
	// The selected clock is disabled
	RCC_APB1LENR_I2C1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_I2C1EN_Enabled = 0x1
	// Position of I2C2EN field.
	RCC_APB1LENR_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_APB1LENR_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_APB1LENR_I2C2EN = 0x400000
	// The selected clock is disabled
	RCC_APB1LENR_I2C2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_I2C2EN_Enabled = 0x1
	// Position of I2C3EN field.
	RCC_APB1LENR_I2C3EN_Pos = 0x17
	// Bit mask of I2C3EN field.
	RCC_APB1LENR_I2C3EN_Msk = 0x800000
	// Bit I2C3EN.
	RCC_APB1LENR_I2C3EN = 0x800000
	// The selected clock is disabled
	RCC_APB1LENR_I2C3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_I2C3EN_Enabled = 0x1
	// Position of CECEN field.
	RCC_APB1LENR_CECEN_Pos = 0x1b
	// Bit mask of CECEN field.
	RCC_APB1LENR_CECEN_Msk = 0x8000000
	// Bit CECEN.
	RCC_APB1LENR_CECEN = 0x8000000
	// The selected clock is disabled
	RCC_APB1LENR_CECEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_CECEN_Enabled = 0x1
	// Position of DAC12EN field.
	RCC_APB1LENR_DAC12EN_Pos = 0x1d
	// Bit mask of DAC12EN field.
	RCC_APB1LENR_DAC12EN_Msk = 0x20000000
	// Bit DAC12EN.
	RCC_APB1LENR_DAC12EN = 0x20000000
	// The selected clock is disabled
	RCC_APB1LENR_DAC12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_DAC12EN_Enabled = 0x1
	// Position of UART7EN field.
	RCC_APB1LENR_UART7EN_Pos = 0x1e
	// Bit mask of UART7EN field.
	RCC_APB1LENR_UART7EN_Msk = 0x40000000
	// Bit UART7EN.
	RCC_APB1LENR_UART7EN = 0x40000000
	// The selected clock is disabled
	RCC_APB1LENR_UART7EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_UART7EN_Enabled = 0x1
	// Position of UART8EN field.
	RCC_APB1LENR_UART8EN_Pos = 0x1f
	// Bit mask of UART8EN field.
	RCC_APB1LENR_UART8EN_Msk = 0x80000000
	// Bit UART8EN.
	RCC_APB1LENR_UART8EN = 0x80000000
	// The selected clock is disabled
	RCC_APB1LENR_UART8EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1LENR_UART8EN_Enabled = 0x1

	// APB1HENR: RCC APB1 Clock Register
	// Position of CRSEN field.
	RCC_APB1HENR_CRSEN_Pos = 0x1
	// Bit mask of CRSEN field.
	RCC_APB1HENR_CRSEN_Msk = 0x2
	// Bit CRSEN.
	RCC_APB1HENR_CRSEN = 0x2
	// The selected clock is disabled
	RCC_APB1HENR_CRSEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1HENR_CRSEN_Enabled = 0x1
	// Position of SWPEN field.
	RCC_APB1HENR_SWPEN_Pos = 0x2
	// Bit mask of SWPEN field.
	RCC_APB1HENR_SWPEN_Msk = 0x4
	// Bit SWPEN.
	RCC_APB1HENR_SWPEN = 0x4
	// The selected clock is disabled
	RCC_APB1HENR_SWPEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1HENR_SWPEN_Enabled = 0x1
	// Position of OPAMPEN field.
	RCC_APB1HENR_OPAMPEN_Pos = 0x4
	// Bit mask of OPAMPEN field.
	RCC_APB1HENR_OPAMPEN_Msk = 0x10
	// Bit OPAMPEN.
	RCC_APB1HENR_OPAMPEN = 0x10
	// The selected clock is disabled
	RCC_APB1HENR_OPAMPEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1HENR_OPAMPEN_Enabled = 0x1
	// Position of MDIOSEN field.
	RCC_APB1HENR_MDIOSEN_Pos = 0x5
	// Bit mask of MDIOSEN field.
	RCC_APB1HENR_MDIOSEN_Msk = 0x20
	// Bit MDIOSEN.
	RCC_APB1HENR_MDIOSEN = 0x20
	// The selected clock is disabled
	RCC_APB1HENR_MDIOSEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1HENR_MDIOSEN_Enabled = 0x1
	// Position of FDCANEN field.
	RCC_APB1HENR_FDCANEN_Pos = 0x8
	// Bit mask of FDCANEN field.
	RCC_APB1HENR_FDCANEN_Msk = 0x100
	// Bit FDCANEN.
	RCC_APB1HENR_FDCANEN = 0x100
	// The selected clock is disabled
	RCC_APB1HENR_FDCANEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1HENR_FDCANEN_Enabled = 0x1

	// APB2ENR: RCC APB2 Clock Register
	// Position of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Pos = 0x0
	// Bit mask of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Msk = 0x1
	// Bit TIM1EN.
	RCC_APB2ENR_TIM1EN = 0x1
	// The selected clock is disabled
	RCC_APB2ENR_TIM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM1EN_Enabled = 0x1
	// Position of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Pos = 0x1
	// Bit mask of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Msk = 0x2
	// Bit TIM8EN.
	RCC_APB2ENR_TIM8EN = 0x2
	// The selected clock is disabled
	RCC_APB2ENR_TIM8EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM8EN_Enabled = 0x1
	// Position of USART1EN field.
	RCC_APB2ENR_USART1EN_Pos = 0x4
	// Bit mask of USART1EN field.
	RCC_APB2ENR_USART1EN_Msk = 0x10
	// Bit USART1EN.
	RCC_APB2ENR_USART1EN = 0x10
	// The selected clock is disabled
	RCC_APB2ENR_USART1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_USART1EN_Enabled = 0x1
	// Position of USART6EN field.
	RCC_APB2ENR_USART6EN_Pos = 0x5
	// Bit mask of USART6EN field.
	RCC_APB2ENR_USART6EN_Msk = 0x20
	// Bit USART6EN.
	RCC_APB2ENR_USART6EN = 0x20
	// The selected clock is disabled
	RCC_APB2ENR_USART6EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_USART6EN_Enabled = 0x1
	// Position of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Pos = 0xc
	// Bit mask of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Msk = 0x1000
	// Bit SPI1EN.
	RCC_APB2ENR_SPI1EN = 0x1000
	// The selected clock is disabled
	RCC_APB2ENR_SPI1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SPI1EN_Enabled = 0x1
	// Position of SPI4EN field.
	RCC_APB2ENR_SPI4EN_Pos = 0xd
	// Bit mask of SPI4EN field.
	RCC_APB2ENR_SPI4EN_Msk = 0x2000
	// Bit SPI4EN.
	RCC_APB2ENR_SPI4EN = 0x2000
	// The selected clock is disabled
	RCC_APB2ENR_SPI4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SPI4EN_Enabled = 0x1
	// Position of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Pos = 0x11
	// Bit mask of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Msk = 0x20000
	// Bit TIM16EN.
	RCC_APB2ENR_TIM16EN = 0x20000
	// The selected clock is disabled
	RCC_APB2ENR_TIM16EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM16EN_Enabled = 0x1
	// Position of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Pos = 0x10
	// Bit mask of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Msk = 0x10000
	// Bit TIM15EN.
	RCC_APB2ENR_TIM15EN = 0x10000
	// The selected clock is disabled
	RCC_APB2ENR_TIM15EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM15EN_Enabled = 0x1
	// Position of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Pos = 0x12
	// Bit mask of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Msk = 0x40000
	// Bit TIM17EN.
	RCC_APB2ENR_TIM17EN = 0x40000
	// The selected clock is disabled
	RCC_APB2ENR_TIM17EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM17EN_Enabled = 0x1
	// Position of SPI5EN field.
	RCC_APB2ENR_SPI5EN_Pos = 0x14
	// Bit mask of SPI5EN field.
	RCC_APB2ENR_SPI5EN_Msk = 0x100000
	// Bit SPI5EN.
	RCC_APB2ENR_SPI5EN = 0x100000
	// The selected clock is disabled
	RCC_APB2ENR_SPI5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SPI5EN_Enabled = 0x1
	// Position of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Pos = 0x16
	// Bit mask of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Msk = 0x400000
	// Bit SAI1EN.
	RCC_APB2ENR_SAI1EN = 0x400000
	// The selected clock is disabled
	RCC_APB2ENR_SAI1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SAI1EN_Enabled = 0x1
	// Position of SAI2EN field.
	RCC_APB2ENR_SAI2EN_Pos = 0x17
	// Bit mask of SAI2EN field.
	RCC_APB2ENR_SAI2EN_Msk = 0x800000
	// Bit SAI2EN.
	RCC_APB2ENR_SAI2EN = 0x800000
	// The selected clock is disabled
	RCC_APB2ENR_SAI2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SAI2EN_Enabled = 0x1
	// Position of SAI3EN field.
	RCC_APB2ENR_SAI3EN_Pos = 0x18
	// Bit mask of SAI3EN field.
	RCC_APB2ENR_SAI3EN_Msk = 0x1000000
	// Bit SAI3EN.
	RCC_APB2ENR_SAI3EN = 0x1000000
	// The selected clock is disabled
	RCC_APB2ENR_SAI3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SAI3EN_Enabled = 0x1
	// Position of DFSDM1EN field.
	RCC_APB2ENR_DFSDM1EN_Pos = 0x1c
	// Bit mask of DFSDM1EN field.
	RCC_APB2ENR_DFSDM1EN_Msk = 0x10000000
	// Bit DFSDM1EN.
	RCC_APB2ENR_DFSDM1EN = 0x10000000
	// The selected clock is disabled
	RCC_APB2ENR_DFSDM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_DFSDM1EN_Enabled = 0x1
	// Position of HRTIMEN field.
	RCC_APB2ENR_HRTIMEN_Pos = 0x1d
	// Bit mask of HRTIMEN field.
	RCC_APB2ENR_HRTIMEN_Msk = 0x20000000
	// Bit HRTIMEN.
	RCC_APB2ENR_HRTIMEN = 0x20000000
	// The selected clock is disabled
	RCC_APB2ENR_HRTIMEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_HRTIMEN_Enabled = 0x1

	// APB4ENR: RCC APB4 Clock Register
	// Position of SYSCFGEN field.
	RCC_APB4ENR_SYSCFGEN_Pos = 0x1
	// Bit mask of SYSCFGEN field.
	RCC_APB4ENR_SYSCFGEN_Msk = 0x2
	// Bit SYSCFGEN.
	RCC_APB4ENR_SYSCFGEN = 0x2
	// The selected clock is disabled
	RCC_APB4ENR_SYSCFGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_SYSCFGEN_Enabled = 0x1
	// Position of LPUART1EN field.
	RCC_APB4ENR_LPUART1EN_Pos = 0x3
	// Bit mask of LPUART1EN field.
	RCC_APB4ENR_LPUART1EN_Msk = 0x8
	// Bit LPUART1EN.
	RCC_APB4ENR_LPUART1EN = 0x8
	// The selected clock is disabled
	RCC_APB4ENR_LPUART1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_LPUART1EN_Enabled = 0x1
	// Position of SPI6EN field.
	RCC_APB4ENR_SPI6EN_Pos = 0x5
	// Bit mask of SPI6EN field.
	RCC_APB4ENR_SPI6EN_Msk = 0x20
	// Bit SPI6EN.
	RCC_APB4ENR_SPI6EN = 0x20
	// The selected clock is disabled
	RCC_APB4ENR_SPI6EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_SPI6EN_Enabled = 0x1
	// Position of I2C4EN field.
	RCC_APB4ENR_I2C4EN_Pos = 0x7
	// Bit mask of I2C4EN field.
	RCC_APB4ENR_I2C4EN_Msk = 0x80
	// Bit I2C4EN.
	RCC_APB4ENR_I2C4EN = 0x80
	// The selected clock is disabled
	RCC_APB4ENR_I2C4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_I2C4EN_Enabled = 0x1
	// Position of LPTIM2EN field.
	RCC_APB4ENR_LPTIM2EN_Pos = 0x9
	// Bit mask of LPTIM2EN field.
	RCC_APB4ENR_LPTIM2EN_Msk = 0x200
	// Bit LPTIM2EN.
	RCC_APB4ENR_LPTIM2EN = 0x200
	// The selected clock is disabled
	RCC_APB4ENR_LPTIM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_LPTIM2EN_Enabled = 0x1
	// Position of LPTIM3EN field.
	RCC_APB4ENR_LPTIM3EN_Pos = 0xa
	// Bit mask of LPTIM3EN field.
	RCC_APB4ENR_LPTIM3EN_Msk = 0x400
	// Bit LPTIM3EN.
	RCC_APB4ENR_LPTIM3EN = 0x400
	// The selected clock is disabled
	RCC_APB4ENR_LPTIM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_LPTIM3EN_Enabled = 0x1
	// Position of LPTIM4EN field.
	RCC_APB4ENR_LPTIM4EN_Pos = 0xb
	// Bit mask of LPTIM4EN field.
	RCC_APB4ENR_LPTIM4EN_Msk = 0x800
	// Bit LPTIM4EN.
	RCC_APB4ENR_LPTIM4EN = 0x800
	// The selected clock is disabled
	RCC_APB4ENR_LPTIM4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_LPTIM4EN_Enabled = 0x1
	// Position of LPTIM5EN field.
	RCC_APB4ENR_LPTIM5EN_Pos = 0xc
	// Bit mask of LPTIM5EN field.
	RCC_APB4ENR_LPTIM5EN_Msk = 0x1000
	// Bit LPTIM5EN.
	RCC_APB4ENR_LPTIM5EN = 0x1000
	// The selected clock is disabled
	RCC_APB4ENR_LPTIM5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_LPTIM5EN_Enabled = 0x1
	// Position of COMP12EN field.
	RCC_APB4ENR_COMP12EN_Pos = 0xe
	// Bit mask of COMP12EN field.
	RCC_APB4ENR_COMP12EN_Msk = 0x4000
	// Bit COMP12EN.
	RCC_APB4ENR_COMP12EN = 0x4000
	// The selected clock is disabled
	RCC_APB4ENR_COMP12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_COMP12EN_Enabled = 0x1
	// Position of VREFEN field.
	RCC_APB4ENR_VREFEN_Pos = 0xf
	// Bit mask of VREFEN field.
	RCC_APB4ENR_VREFEN_Msk = 0x8000
	// Bit VREFEN.
	RCC_APB4ENR_VREFEN = 0x8000
	// The selected clock is disabled
	RCC_APB4ENR_VREFEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_VREFEN_Enabled = 0x1
	// Position of RTCAPBEN field.
	RCC_APB4ENR_RTCAPBEN_Pos = 0x10
	// Bit mask of RTCAPBEN field.
	RCC_APB4ENR_RTCAPBEN_Msk = 0x10000
	// Bit RTCAPBEN.
	RCC_APB4ENR_RTCAPBEN = 0x10000
	// The selected clock is disabled
	RCC_APB4ENR_RTCAPBEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_RTCAPBEN_Enabled = 0x1
	// Position of SAI4EN field.
	RCC_APB4ENR_SAI4EN_Pos = 0x15
	// Bit mask of SAI4EN field.
	RCC_APB4ENR_SAI4EN_Msk = 0x200000
	// Bit SAI4EN.
	RCC_APB4ENR_SAI4EN = 0x200000
	// The selected clock is disabled
	RCC_APB4ENR_SAI4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB4ENR_SAI4EN_Enabled = 0x1

	// AHB3LPENR: RCC AHB3 Sleep Clock Register
	// Position of MDMALPEN field.
	RCC_AHB3LPENR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_AHB3LPENR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_AHB3LPENR_MDMALPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_MDMALPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_MDMALPEN_Enabled = 0x1
	// Position of DMA2DLPEN field.
	RCC_AHB3LPENR_DMA2DLPEN_Pos = 0x4
	// Bit mask of DMA2DLPEN field.
	RCC_AHB3LPENR_DMA2DLPEN_Msk = 0x10
	// Bit DMA2DLPEN.
	RCC_AHB3LPENR_DMA2DLPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_DMA2DLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_DMA2DLPEN_Enabled = 0x1
	// Position of JPGDECLPEN field.
	RCC_AHB3LPENR_JPGDECLPEN_Pos = 0x5
	// Bit mask of JPGDECLPEN field.
	RCC_AHB3LPENR_JPGDECLPEN_Msk = 0x20
	// Bit JPGDECLPEN.
	RCC_AHB3LPENR_JPGDECLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_JPGDECLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_JPGDECLPEN_Enabled = 0x1
	// Position of FLASHLPEN field.
	RCC_AHB3LPENR_FLASHLPEN_Pos = 0x8
	// Bit mask of FLASHLPEN field.
	RCC_AHB3LPENR_FLASHLPEN_Msk = 0x100
	// Bit FLASHLPEN.
	RCC_AHB3LPENR_FLASHLPEN = 0x100
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_FLASHLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_FLASHLPEN_Enabled = 0x1
	// Position of FMCLPEN field.
	RCC_AHB3LPENR_FMCLPEN_Pos = 0xc
	// Bit mask of FMCLPEN field.
	RCC_AHB3LPENR_FMCLPEN_Msk = 0x1000
	// Bit FMCLPEN.
	RCC_AHB3LPENR_FMCLPEN = 0x1000
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_FMCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_FMCLPEN_Enabled = 0x1
	// Position of QSPILPEN field.
	RCC_AHB3LPENR_QSPILPEN_Pos = 0xe
	// Bit mask of QSPILPEN field.
	RCC_AHB3LPENR_QSPILPEN_Msk = 0x4000
	// Bit QSPILPEN.
	RCC_AHB3LPENR_QSPILPEN = 0x4000
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_QSPILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_QSPILPEN_Enabled = 0x1
	// Position of SDMMC1LPEN field.
	RCC_AHB3LPENR_SDMMC1LPEN_Pos = 0x10
	// Bit mask of SDMMC1LPEN field.
	RCC_AHB3LPENR_SDMMC1LPEN_Msk = 0x10000
	// Bit SDMMC1LPEN.
	RCC_AHB3LPENR_SDMMC1LPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_SDMMC1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_SDMMC1LPEN_Enabled = 0x1
	// Position of D1DTCM1LPEN field.
	RCC_AHB3LPENR_D1DTCM1LPEN_Pos = 0x1c
	// Bit mask of D1DTCM1LPEN field.
	RCC_AHB3LPENR_D1DTCM1LPEN_Msk = 0x10000000
	// Bit D1DTCM1LPEN.
	RCC_AHB3LPENR_D1DTCM1LPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_D1DTCM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_D1DTCM1LPEN_Enabled = 0x1
	// Position of DTCM2LPEN field.
	RCC_AHB3LPENR_DTCM2LPEN_Pos = 0x1d
	// Bit mask of DTCM2LPEN field.
	RCC_AHB3LPENR_DTCM2LPEN_Msk = 0x20000000
	// Bit DTCM2LPEN.
	RCC_AHB3LPENR_DTCM2LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_DTCM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_DTCM2LPEN_Enabled = 0x1
	// Position of ITCMLPEN field.
	RCC_AHB3LPENR_ITCMLPEN_Pos = 0x1e
	// Bit mask of ITCMLPEN field.
	RCC_AHB3LPENR_ITCMLPEN_Msk = 0x40000000
	// Bit ITCMLPEN.
	RCC_AHB3LPENR_ITCMLPEN = 0x40000000
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_ITCMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_ITCMLPEN_Enabled = 0x1
	// Position of AXISRAMLPEN field.
	RCC_AHB3LPENR_AXISRAMLPEN_Pos = 0x1f
	// Bit mask of AXISRAMLPEN field.
	RCC_AHB3LPENR_AXISRAMLPEN_Msk = 0x80000000
	// Bit AXISRAMLPEN.
	RCC_AHB3LPENR_AXISRAMLPEN = 0x80000000
	// The selected clock is disabled during csleep mode
	RCC_AHB3LPENR_AXISRAMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB3LPENR_AXISRAMLPEN_Enabled = 0x1

	// AHB1LPENR: RCC AHB1 Sleep Clock Register
	// Position of DMA1LPEN field.
	RCC_AHB1LPENR_DMA1LPEN_Pos = 0x0
	// Bit mask of DMA1LPEN field.
	RCC_AHB1LPENR_DMA1LPEN_Msk = 0x1
	// Bit DMA1LPEN.
	RCC_AHB1LPENR_DMA1LPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_DMA1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_DMA1LPEN_Enabled = 0x1
	// Position of DMA2LPEN field.
	RCC_AHB1LPENR_DMA2LPEN_Pos = 0x1
	// Bit mask of DMA2LPEN field.
	RCC_AHB1LPENR_DMA2LPEN_Msk = 0x2
	// Bit DMA2LPEN.
	RCC_AHB1LPENR_DMA2LPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_DMA2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_DMA2LPEN_Enabled = 0x1
	// Position of ADC12LPEN field.
	RCC_AHB1LPENR_ADC12LPEN_Pos = 0x5
	// Bit mask of ADC12LPEN field.
	RCC_AHB1LPENR_ADC12LPEN_Msk = 0x20
	// Bit ADC12LPEN.
	RCC_AHB1LPENR_ADC12LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_ADC12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_ADC12LPEN_Enabled = 0x1
	// Position of ETH1MACLPEN field.
	RCC_AHB1LPENR_ETH1MACLPEN_Pos = 0xf
	// Bit mask of ETH1MACLPEN field.
	RCC_AHB1LPENR_ETH1MACLPEN_Msk = 0x8000
	// Bit ETH1MACLPEN.
	RCC_AHB1LPENR_ETH1MACLPEN = 0x8000
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_ETH1MACLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_ETH1MACLPEN_Enabled = 0x1
	// Position of ETH1TXLPEN field.
	RCC_AHB1LPENR_ETH1TXLPEN_Pos = 0x10
	// Bit mask of ETH1TXLPEN field.
	RCC_AHB1LPENR_ETH1TXLPEN_Msk = 0x10000
	// Bit ETH1TXLPEN.
	RCC_AHB1LPENR_ETH1TXLPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_ETH1TXLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_ETH1TXLPEN_Enabled = 0x1
	// Position of ETH1RXLPEN field.
	RCC_AHB1LPENR_ETH1RXLPEN_Pos = 0x11
	// Bit mask of ETH1RXLPEN field.
	RCC_AHB1LPENR_ETH1RXLPEN_Msk = 0x20000
	// Bit ETH1RXLPEN.
	RCC_AHB1LPENR_ETH1RXLPEN = 0x20000
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_ETH1RXLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_ETH1RXLPEN_Enabled = 0x1
	// Position of USB1OTGLPEN field.
	RCC_AHB1LPENR_USB1OTGLPEN_Pos = 0x19
	// Bit mask of USB1OTGLPEN field.
	RCC_AHB1LPENR_USB1OTGLPEN_Msk = 0x2000000
	// Bit USB1OTGLPEN.
	RCC_AHB1LPENR_USB1OTGLPEN = 0x2000000
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_USB1OTGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_USB1OTGLPEN_Enabled = 0x1
	// Position of USB1OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos = 0x1a
	// Bit mask of USB1OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk = 0x4000000
	// Bit USB1OTGHSULPILPEN.
	RCC_AHB1LPENR_USB1OTGHSULPILPEN = 0x4000000
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Enabled = 0x1
	// Position of USB2OTGLPEN field.
	RCC_AHB1LPENR_USB2OTGLPEN_Pos = 0x1b
	// Bit mask of USB2OTGLPEN field.
	RCC_AHB1LPENR_USB2OTGLPEN_Msk = 0x8000000
	// Bit USB2OTGLPEN.
	RCC_AHB1LPENR_USB2OTGLPEN = 0x8000000
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_USB2OTGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_USB2OTGLPEN_Enabled = 0x1
	// Position of USB2OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos = 0x1c
	// Bit mask of USB2OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk = 0x10000000
	// Bit USB2OTGHSULPILPEN.
	RCC_AHB1LPENR_USB2OTGHSULPILPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_AHB1LPENR_USB2OTGHSULPILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB1LPENR_USB2OTGHSULPILPEN_Enabled = 0x1

	// AHB2LPENR: RCC AHB2 Sleep Clock Register
	// Position of DCMILPEN field.
	RCC_AHB2LPENR_DCMILPEN_Pos = 0x0
	// Bit mask of DCMILPEN field.
	RCC_AHB2LPENR_DCMILPEN_Msk = 0x1
	// Bit DCMILPEN.
	RCC_AHB2LPENR_DCMILPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_DCMILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_DCMILPEN_Enabled = 0x1
	// Position of CRYPTLPEN field.
	RCC_AHB2LPENR_CRYPTLPEN_Pos = 0x4
	// Bit mask of CRYPTLPEN field.
	RCC_AHB2LPENR_CRYPTLPEN_Msk = 0x10
	// Bit CRYPTLPEN.
	RCC_AHB2LPENR_CRYPTLPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_CRYPTLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_CRYPTLPEN_Enabled = 0x1
	// Position of HASHLPEN field.
	RCC_AHB2LPENR_HASHLPEN_Pos = 0x5
	// Bit mask of HASHLPEN field.
	RCC_AHB2LPENR_HASHLPEN_Msk = 0x20
	// Bit HASHLPEN.
	RCC_AHB2LPENR_HASHLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_HASHLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_HASHLPEN_Enabled = 0x1
	// Position of SDMMC2LPEN field.
	RCC_AHB2LPENR_SDMMC2LPEN_Pos = 0x9
	// Bit mask of SDMMC2LPEN field.
	RCC_AHB2LPENR_SDMMC2LPEN_Msk = 0x200
	// Bit SDMMC2LPEN.
	RCC_AHB2LPENR_SDMMC2LPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_SDMMC2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_SDMMC2LPEN_Enabled = 0x1
	// Position of RNGLPEN field.
	RCC_AHB2LPENR_RNGLPEN_Pos = 0x6
	// Bit mask of RNGLPEN field.
	RCC_AHB2LPENR_RNGLPEN_Msk = 0x40
	// Bit RNGLPEN.
	RCC_AHB2LPENR_RNGLPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_RNGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_RNGLPEN_Enabled = 0x1
	// Position of SRAM1LPEN field.
	RCC_AHB2LPENR_SRAM1LPEN_Pos = 0x1d
	// Bit mask of SRAM1LPEN field.
	RCC_AHB2LPENR_SRAM1LPEN_Msk = 0x20000000
	// Bit SRAM1LPEN.
	RCC_AHB2LPENR_SRAM1LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_SRAM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_SRAM1LPEN_Enabled = 0x1
	// Position of SRAM2LPEN field.
	RCC_AHB2LPENR_SRAM2LPEN_Pos = 0x1e
	// Bit mask of SRAM2LPEN field.
	RCC_AHB2LPENR_SRAM2LPEN_Msk = 0x40000000
	// Bit SRAM2LPEN.
	RCC_AHB2LPENR_SRAM2LPEN = 0x40000000
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_SRAM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_SRAM2LPEN_Enabled = 0x1
	// Position of SRAM3LPEN field.
	RCC_AHB2LPENR_SRAM3LPEN_Pos = 0x1f
	// Bit mask of SRAM3LPEN field.
	RCC_AHB2LPENR_SRAM3LPEN_Msk = 0x80000000
	// Bit SRAM3LPEN.
	RCC_AHB2LPENR_SRAM3LPEN = 0x80000000
	// The selected clock is disabled during csleep mode
	RCC_AHB2LPENR_SRAM3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB2LPENR_SRAM3LPEN_Enabled = 0x1

	// AHB4LPENR: RCC AHB4 Sleep Clock Register
	// Position of GPIOALPEN field.
	RCC_AHB4LPENR_GPIOALPEN_Pos = 0x0
	// Bit mask of GPIOALPEN field.
	RCC_AHB4LPENR_GPIOALPEN_Msk = 0x1
	// Bit GPIOALPEN.
	RCC_AHB4LPENR_GPIOALPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOALPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOALPEN_Enabled = 0x1
	// Position of GPIOBLPEN field.
	RCC_AHB4LPENR_GPIOBLPEN_Pos = 0x1
	// Bit mask of GPIOBLPEN field.
	RCC_AHB4LPENR_GPIOBLPEN_Msk = 0x2
	// Bit GPIOBLPEN.
	RCC_AHB4LPENR_GPIOBLPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOBLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOBLPEN_Enabled = 0x1
	// Position of GPIOCLPEN field.
	RCC_AHB4LPENR_GPIOCLPEN_Pos = 0x2
	// Bit mask of GPIOCLPEN field.
	RCC_AHB4LPENR_GPIOCLPEN_Msk = 0x4
	// Bit GPIOCLPEN.
	RCC_AHB4LPENR_GPIOCLPEN = 0x4
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOCLPEN_Enabled = 0x1
	// Position of GPIODLPEN field.
	RCC_AHB4LPENR_GPIODLPEN_Pos = 0x3
	// Bit mask of GPIODLPEN field.
	RCC_AHB4LPENR_GPIODLPEN_Msk = 0x8
	// Bit GPIODLPEN.
	RCC_AHB4LPENR_GPIODLPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIODLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIODLPEN_Enabled = 0x1
	// Position of GPIOELPEN field.
	RCC_AHB4LPENR_GPIOELPEN_Pos = 0x4
	// Bit mask of GPIOELPEN field.
	RCC_AHB4LPENR_GPIOELPEN_Msk = 0x10
	// Bit GPIOELPEN.
	RCC_AHB4LPENR_GPIOELPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOELPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOELPEN_Enabled = 0x1
	// Position of GPIOFLPEN field.
	RCC_AHB4LPENR_GPIOFLPEN_Pos = 0x5
	// Bit mask of GPIOFLPEN field.
	RCC_AHB4LPENR_GPIOFLPEN_Msk = 0x20
	// Bit GPIOFLPEN.
	RCC_AHB4LPENR_GPIOFLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOFLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOFLPEN_Enabled = 0x1
	// Position of GPIOGLPEN field.
	RCC_AHB4LPENR_GPIOGLPEN_Pos = 0x6
	// Bit mask of GPIOGLPEN field.
	RCC_AHB4LPENR_GPIOGLPEN_Msk = 0x40
	// Bit GPIOGLPEN.
	RCC_AHB4LPENR_GPIOGLPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOGLPEN_Enabled = 0x1
	// Position of GPIOHLPEN field.
	RCC_AHB4LPENR_GPIOHLPEN_Pos = 0x7
	// Bit mask of GPIOHLPEN field.
	RCC_AHB4LPENR_GPIOHLPEN_Msk = 0x80
	// Bit GPIOHLPEN.
	RCC_AHB4LPENR_GPIOHLPEN = 0x80
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOHLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOHLPEN_Enabled = 0x1
	// Position of GPIOILPEN field.
	RCC_AHB4LPENR_GPIOILPEN_Pos = 0x8
	// Bit mask of GPIOILPEN field.
	RCC_AHB4LPENR_GPIOILPEN_Msk = 0x100
	// Bit GPIOILPEN.
	RCC_AHB4LPENR_GPIOILPEN = 0x100
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOILPEN_Enabled = 0x1
	// Position of GPIOJLPEN field.
	RCC_AHB4LPENR_GPIOJLPEN_Pos = 0x9
	// Bit mask of GPIOJLPEN field.
	RCC_AHB4LPENR_GPIOJLPEN_Msk = 0x200
	// Bit GPIOJLPEN.
	RCC_AHB4LPENR_GPIOJLPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOJLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOJLPEN_Enabled = 0x1
	// Position of GPIOKLPEN field.
	RCC_AHB4LPENR_GPIOKLPEN_Pos = 0xa
	// Bit mask of GPIOKLPEN field.
	RCC_AHB4LPENR_GPIOKLPEN_Msk = 0x400
	// Bit GPIOKLPEN.
	RCC_AHB4LPENR_GPIOKLPEN = 0x400
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_GPIOKLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_GPIOKLPEN_Enabled = 0x1
	// Position of CRCLPEN field.
	RCC_AHB4LPENR_CRCLPEN_Pos = 0x13
	// Bit mask of CRCLPEN field.
	RCC_AHB4LPENR_CRCLPEN_Msk = 0x80000
	// Bit CRCLPEN.
	RCC_AHB4LPENR_CRCLPEN = 0x80000
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_CRCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_CRCLPEN_Enabled = 0x1
	// Position of BDMALPEN field.
	RCC_AHB4LPENR_BDMALPEN_Pos = 0x15
	// Bit mask of BDMALPEN field.
	RCC_AHB4LPENR_BDMALPEN_Msk = 0x200000
	// Bit BDMALPEN.
	RCC_AHB4LPENR_BDMALPEN = 0x200000
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_BDMALPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_BDMALPEN_Enabled = 0x1
	// Position of ADC3LPEN field.
	RCC_AHB4LPENR_ADC3LPEN_Pos = 0x18
	// Bit mask of ADC3LPEN field.
	RCC_AHB4LPENR_ADC3LPEN_Msk = 0x1000000
	// Bit ADC3LPEN.
	RCC_AHB4LPENR_ADC3LPEN = 0x1000000
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_ADC3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_ADC3LPEN_Enabled = 0x1
	// Position of BKPRAMLPEN field.
	RCC_AHB4LPENR_BKPRAMLPEN_Pos = 0x1c
	// Bit mask of BKPRAMLPEN field.
	RCC_AHB4LPENR_BKPRAMLPEN_Msk = 0x10000000
	// Bit BKPRAMLPEN.
	RCC_AHB4LPENR_BKPRAMLPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_BKPRAMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_BKPRAMLPEN_Enabled = 0x1
	// Position of SRAM4LPEN field.
	RCC_AHB4LPENR_SRAM4LPEN_Pos = 0x1d
	// Bit mask of SRAM4LPEN field.
	RCC_AHB4LPENR_SRAM4LPEN_Msk = 0x20000000
	// Bit SRAM4LPEN.
	RCC_AHB4LPENR_SRAM4LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_AHB4LPENR_SRAM4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_AHB4LPENR_SRAM4LPEN_Enabled = 0x1

	// APB3LPENR: RCC APB3 Sleep Clock Register
	// Position of LTDCLPEN field.
	RCC_APB3LPENR_LTDCLPEN_Pos = 0x3
	// Bit mask of LTDCLPEN field.
	RCC_APB3LPENR_LTDCLPEN_Msk = 0x8
	// Bit LTDCLPEN.
	RCC_APB3LPENR_LTDCLPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_APB3LPENR_LTDCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB3LPENR_LTDCLPEN_Enabled = 0x1
	// Position of WWDG1LPEN field.
	RCC_APB3LPENR_WWDG1LPEN_Pos = 0x6
	// Bit mask of WWDG1LPEN field.
	RCC_APB3LPENR_WWDG1LPEN_Msk = 0x40
	// Bit WWDG1LPEN.
	RCC_APB3LPENR_WWDG1LPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_APB3LPENR_WWDG1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB3LPENR_WWDG1LPEN_Enabled = 0x1

	// APB1LLPENR: RCC APB1 Low Sleep Clock Register
	// Position of TIM2LPEN field.
	RCC_APB1LLPENR_TIM2LPEN_Pos = 0x0
	// Bit mask of TIM2LPEN field.
	RCC_APB1LLPENR_TIM2LPEN_Msk = 0x1
	// Bit TIM2LPEN.
	RCC_APB1LLPENR_TIM2LPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM2LPEN_Enabled = 0x1
	// Position of TIM3LPEN field.
	RCC_APB1LLPENR_TIM3LPEN_Pos = 0x1
	// Bit mask of TIM3LPEN field.
	RCC_APB1LLPENR_TIM3LPEN_Msk = 0x2
	// Bit TIM3LPEN.
	RCC_APB1LLPENR_TIM3LPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM3LPEN_Enabled = 0x1
	// Position of TIM4LPEN field.
	RCC_APB1LLPENR_TIM4LPEN_Pos = 0x2
	// Bit mask of TIM4LPEN field.
	RCC_APB1LLPENR_TIM4LPEN_Msk = 0x4
	// Bit TIM4LPEN.
	RCC_APB1LLPENR_TIM4LPEN = 0x4
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM4LPEN_Enabled = 0x1
	// Position of TIM5LPEN field.
	RCC_APB1LLPENR_TIM5LPEN_Pos = 0x3
	// Bit mask of TIM5LPEN field.
	RCC_APB1LLPENR_TIM5LPEN_Msk = 0x8
	// Bit TIM5LPEN.
	RCC_APB1LLPENR_TIM5LPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM5LPEN_Enabled = 0x1
	// Position of TIM6LPEN field.
	RCC_APB1LLPENR_TIM6LPEN_Pos = 0x4
	// Bit mask of TIM6LPEN field.
	RCC_APB1LLPENR_TIM6LPEN_Msk = 0x10
	// Bit TIM6LPEN.
	RCC_APB1LLPENR_TIM6LPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM6LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM6LPEN_Enabled = 0x1
	// Position of TIM7LPEN field.
	RCC_APB1LLPENR_TIM7LPEN_Pos = 0x5
	// Bit mask of TIM7LPEN field.
	RCC_APB1LLPENR_TIM7LPEN_Msk = 0x20
	// Bit TIM7LPEN.
	RCC_APB1LLPENR_TIM7LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM7LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM7LPEN_Enabled = 0x1
	// Position of TIM12LPEN field.
	RCC_APB1LLPENR_TIM12LPEN_Pos = 0x6
	// Bit mask of TIM12LPEN field.
	RCC_APB1LLPENR_TIM12LPEN_Msk = 0x40
	// Bit TIM12LPEN.
	RCC_APB1LLPENR_TIM12LPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM12LPEN_Enabled = 0x1
	// Position of TIM13LPEN field.
	RCC_APB1LLPENR_TIM13LPEN_Pos = 0x7
	// Bit mask of TIM13LPEN field.
	RCC_APB1LLPENR_TIM13LPEN_Msk = 0x80
	// Bit TIM13LPEN.
	RCC_APB1LLPENR_TIM13LPEN = 0x80
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM13LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM13LPEN_Enabled = 0x1
	// Position of TIM14LPEN field.
	RCC_APB1LLPENR_TIM14LPEN_Pos = 0x8
	// Bit mask of TIM14LPEN field.
	RCC_APB1LLPENR_TIM14LPEN_Msk = 0x100
	// Bit TIM14LPEN.
	RCC_APB1LLPENR_TIM14LPEN = 0x100
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_TIM14LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_TIM14LPEN_Enabled = 0x1
	// Position of LPTIM1LPEN field.
	RCC_APB1LLPENR_LPTIM1LPEN_Pos = 0x9
	// Bit mask of LPTIM1LPEN field.
	RCC_APB1LLPENR_LPTIM1LPEN_Msk = 0x200
	// Bit LPTIM1LPEN.
	RCC_APB1LLPENR_LPTIM1LPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_LPTIM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_LPTIM1LPEN_Enabled = 0x1
	// Position of SPI2LPEN field.
	RCC_APB1LLPENR_SPI2LPEN_Pos = 0xe
	// Bit mask of SPI2LPEN field.
	RCC_APB1LLPENR_SPI2LPEN_Msk = 0x4000
	// Bit SPI2LPEN.
	RCC_APB1LLPENR_SPI2LPEN = 0x4000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_SPI2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_SPI2LPEN_Enabled = 0x1
	// Position of SPI3LPEN field.
	RCC_APB1LLPENR_SPI3LPEN_Pos = 0xf
	// Bit mask of SPI3LPEN field.
	RCC_APB1LLPENR_SPI3LPEN_Msk = 0x8000
	// Bit SPI3LPEN.
	RCC_APB1LLPENR_SPI3LPEN = 0x8000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_SPI3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_SPI3LPEN_Enabled = 0x1
	// Position of SPDIFRXLPEN field.
	RCC_APB1LLPENR_SPDIFRXLPEN_Pos = 0x10
	// Bit mask of SPDIFRXLPEN field.
	RCC_APB1LLPENR_SPDIFRXLPEN_Msk = 0x10000
	// Bit SPDIFRXLPEN.
	RCC_APB1LLPENR_SPDIFRXLPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_SPDIFRXLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_SPDIFRXLPEN_Enabled = 0x1
	// Position of USART2LPEN field.
	RCC_APB1LLPENR_USART2LPEN_Pos = 0x11
	// Bit mask of USART2LPEN field.
	RCC_APB1LLPENR_USART2LPEN_Msk = 0x20000
	// Bit USART2LPEN.
	RCC_APB1LLPENR_USART2LPEN = 0x20000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_USART2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_USART2LPEN_Enabled = 0x1
	// Position of USART3LPEN field.
	RCC_APB1LLPENR_USART3LPEN_Pos = 0x12
	// Bit mask of USART3LPEN field.
	RCC_APB1LLPENR_USART3LPEN_Msk = 0x40000
	// Bit USART3LPEN.
	RCC_APB1LLPENR_USART3LPEN = 0x40000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_USART3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_USART3LPEN_Enabled = 0x1
	// Position of UART4LPEN field.
	RCC_APB1LLPENR_UART4LPEN_Pos = 0x13
	// Bit mask of UART4LPEN field.
	RCC_APB1LLPENR_UART4LPEN_Msk = 0x80000
	// Bit UART4LPEN.
	RCC_APB1LLPENR_UART4LPEN = 0x80000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_UART4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_UART4LPEN_Enabled = 0x1
	// Position of UART5LPEN field.
	RCC_APB1LLPENR_UART5LPEN_Pos = 0x14
	// Bit mask of UART5LPEN field.
	RCC_APB1LLPENR_UART5LPEN_Msk = 0x100000
	// Bit UART5LPEN.
	RCC_APB1LLPENR_UART5LPEN = 0x100000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_UART5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_UART5LPEN_Enabled = 0x1
	// Position of I2C1LPEN field.
	RCC_APB1LLPENR_I2C1LPEN_Pos = 0x15
	// Bit mask of I2C1LPEN field.
	RCC_APB1LLPENR_I2C1LPEN_Msk = 0x200000
	// Bit I2C1LPEN.
	RCC_APB1LLPENR_I2C1LPEN = 0x200000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_I2C1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_I2C1LPEN_Enabled = 0x1
	// Position of I2C2LPEN field.
	RCC_APB1LLPENR_I2C2LPEN_Pos = 0x16
	// Bit mask of I2C2LPEN field.
	RCC_APB1LLPENR_I2C2LPEN_Msk = 0x400000
	// Bit I2C2LPEN.
	RCC_APB1LLPENR_I2C2LPEN = 0x400000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_I2C2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_I2C2LPEN_Enabled = 0x1
	// Position of I2C3LPEN field.
	RCC_APB1LLPENR_I2C3LPEN_Pos = 0x17
	// Bit mask of I2C3LPEN field.
	RCC_APB1LLPENR_I2C3LPEN_Msk = 0x800000
	// Bit I2C3LPEN.
	RCC_APB1LLPENR_I2C3LPEN = 0x800000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_I2C3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_I2C3LPEN_Enabled = 0x1
	// Position of CECLPEN field.
	RCC_APB1LLPENR_CECLPEN_Pos = 0x1b
	// Bit mask of CECLPEN field.
	RCC_APB1LLPENR_CECLPEN_Msk = 0x8000000
	// Bit CECLPEN.
	RCC_APB1LLPENR_CECLPEN = 0x8000000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_CECLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_CECLPEN_Enabled = 0x1
	// Position of DAC12LPEN field.
	RCC_APB1LLPENR_DAC12LPEN_Pos = 0x1d
	// Bit mask of DAC12LPEN field.
	RCC_APB1LLPENR_DAC12LPEN_Msk = 0x20000000
	// Bit DAC12LPEN.
	RCC_APB1LLPENR_DAC12LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_DAC12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_DAC12LPEN_Enabled = 0x1
	// Position of UART7LPEN field.
	RCC_APB1LLPENR_UART7LPEN_Pos = 0x1e
	// Bit mask of UART7LPEN field.
	RCC_APB1LLPENR_UART7LPEN_Msk = 0x40000000
	// Bit UART7LPEN.
	RCC_APB1LLPENR_UART7LPEN = 0x40000000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_UART7LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_UART7LPEN_Enabled = 0x1
	// Position of UART8LPEN field.
	RCC_APB1LLPENR_UART8LPEN_Pos = 0x1f
	// Bit mask of UART8LPEN field.
	RCC_APB1LLPENR_UART8LPEN_Msk = 0x80000000
	// Bit UART8LPEN.
	RCC_APB1LLPENR_UART8LPEN = 0x80000000
	// The selected clock is disabled during csleep mode
	RCC_APB1LLPENR_UART8LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1LLPENR_UART8LPEN_Enabled = 0x1

	// APB1HLPENR: RCC APB1 High Sleep Clock Register
	// Position of CRSLPEN field.
	RCC_APB1HLPENR_CRSLPEN_Pos = 0x1
	// Bit mask of CRSLPEN field.
	RCC_APB1HLPENR_CRSLPEN_Msk = 0x2
	// Bit CRSLPEN.
	RCC_APB1HLPENR_CRSLPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_APB1HLPENR_CRSLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1HLPENR_CRSLPEN_Enabled = 0x1
	// Position of SWPLPEN field.
	RCC_APB1HLPENR_SWPLPEN_Pos = 0x2
	// Bit mask of SWPLPEN field.
	RCC_APB1HLPENR_SWPLPEN_Msk = 0x4
	// Bit SWPLPEN.
	RCC_APB1HLPENR_SWPLPEN = 0x4
	// The selected clock is disabled during csleep mode
	RCC_APB1HLPENR_SWPLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1HLPENR_SWPLPEN_Enabled = 0x1
	// Position of OPAMPLPEN field.
	RCC_APB1HLPENR_OPAMPLPEN_Pos = 0x4
	// Bit mask of OPAMPLPEN field.
	RCC_APB1HLPENR_OPAMPLPEN_Msk = 0x10
	// Bit OPAMPLPEN.
	RCC_APB1HLPENR_OPAMPLPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_APB1HLPENR_OPAMPLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1HLPENR_OPAMPLPEN_Enabled = 0x1
	// Position of MDIOSLPEN field.
	RCC_APB1HLPENR_MDIOSLPEN_Pos = 0x5
	// Bit mask of MDIOSLPEN field.
	RCC_APB1HLPENR_MDIOSLPEN_Msk = 0x20
	// Bit MDIOSLPEN.
	RCC_APB1HLPENR_MDIOSLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_APB1HLPENR_MDIOSLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1HLPENR_MDIOSLPEN_Enabled = 0x1
	// Position of FDCANLPEN field.
	RCC_APB1HLPENR_FDCANLPEN_Pos = 0x8
	// Bit mask of FDCANLPEN field.
	RCC_APB1HLPENR_FDCANLPEN_Msk = 0x100
	// Bit FDCANLPEN.
	RCC_APB1HLPENR_FDCANLPEN = 0x100
	// The selected clock is disabled during csleep mode
	RCC_APB1HLPENR_FDCANLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB1HLPENR_FDCANLPEN_Enabled = 0x1

	// APB2LPENR: RCC APB2 Sleep Clock Register
	// Position of TIM1LPEN field.
	RCC_APB2LPENR_TIM1LPEN_Pos = 0x0
	// Bit mask of TIM1LPEN field.
	RCC_APB2LPENR_TIM1LPEN_Msk = 0x1
	// Bit TIM1LPEN.
	RCC_APB2LPENR_TIM1LPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_TIM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_TIM1LPEN_Enabled = 0x1
	// Position of TIM8LPEN field.
	RCC_APB2LPENR_TIM8LPEN_Pos = 0x1
	// Bit mask of TIM8LPEN field.
	RCC_APB2LPENR_TIM8LPEN_Msk = 0x2
	// Bit TIM8LPEN.
	RCC_APB2LPENR_TIM8LPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_TIM8LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_TIM8LPEN_Enabled = 0x1
	// Position of USART1LPEN field.
	RCC_APB2LPENR_USART1LPEN_Pos = 0x4
	// Bit mask of USART1LPEN field.
	RCC_APB2LPENR_USART1LPEN_Msk = 0x10
	// Bit USART1LPEN.
	RCC_APB2LPENR_USART1LPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_USART1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_USART1LPEN_Enabled = 0x1
	// Position of USART6LPEN field.
	RCC_APB2LPENR_USART6LPEN_Pos = 0x5
	// Bit mask of USART6LPEN field.
	RCC_APB2LPENR_USART6LPEN_Msk = 0x20
	// Bit USART6LPEN.
	RCC_APB2LPENR_USART6LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_USART6LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_USART6LPEN_Enabled = 0x1
	// Position of SPI1LPEN field.
	RCC_APB2LPENR_SPI1LPEN_Pos = 0xc
	// Bit mask of SPI1LPEN field.
	RCC_APB2LPENR_SPI1LPEN_Msk = 0x1000
	// Bit SPI1LPEN.
	RCC_APB2LPENR_SPI1LPEN = 0x1000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_SPI1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_SPI1LPEN_Enabled = 0x1
	// Position of SPI4LPEN field.
	RCC_APB2LPENR_SPI4LPEN_Pos = 0xd
	// Bit mask of SPI4LPEN field.
	RCC_APB2LPENR_SPI4LPEN_Msk = 0x2000
	// Bit SPI4LPEN.
	RCC_APB2LPENR_SPI4LPEN = 0x2000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_SPI4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_SPI4LPEN_Enabled = 0x1
	// Position of TIM15LPEN field.
	RCC_APB2LPENR_TIM15LPEN_Pos = 0x10
	// Bit mask of TIM15LPEN field.
	RCC_APB2LPENR_TIM15LPEN_Msk = 0x10000
	// Bit TIM15LPEN.
	RCC_APB2LPENR_TIM15LPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_TIM15LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_TIM15LPEN_Enabled = 0x1
	// Position of TIM16LPEN field.
	RCC_APB2LPENR_TIM16LPEN_Pos = 0x11
	// Bit mask of TIM16LPEN field.
	RCC_APB2LPENR_TIM16LPEN_Msk = 0x20000
	// Bit TIM16LPEN.
	RCC_APB2LPENR_TIM16LPEN = 0x20000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_TIM16LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_TIM16LPEN_Enabled = 0x1
	// Position of TIM17LPEN field.
	RCC_APB2LPENR_TIM17LPEN_Pos = 0x12
	// Bit mask of TIM17LPEN field.
	RCC_APB2LPENR_TIM17LPEN_Msk = 0x40000
	// Bit TIM17LPEN.
	RCC_APB2LPENR_TIM17LPEN = 0x40000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_TIM17LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_TIM17LPEN_Enabled = 0x1
	// Position of SPI5LPEN field.
	RCC_APB2LPENR_SPI5LPEN_Pos = 0x14
	// Bit mask of SPI5LPEN field.
	RCC_APB2LPENR_SPI5LPEN_Msk = 0x100000
	// Bit SPI5LPEN.
	RCC_APB2LPENR_SPI5LPEN = 0x100000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_SPI5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_SPI5LPEN_Enabled = 0x1
	// Position of SAI1LPEN field.
	RCC_APB2LPENR_SAI1LPEN_Pos = 0x16
	// Bit mask of SAI1LPEN field.
	RCC_APB2LPENR_SAI1LPEN_Msk = 0x400000
	// Bit SAI1LPEN.
	RCC_APB2LPENR_SAI1LPEN = 0x400000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_SAI1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_SAI1LPEN_Enabled = 0x1
	// Position of SAI2LPEN field.
	RCC_APB2LPENR_SAI2LPEN_Pos = 0x17
	// Bit mask of SAI2LPEN field.
	RCC_APB2LPENR_SAI2LPEN_Msk = 0x800000
	// Bit SAI2LPEN.
	RCC_APB2LPENR_SAI2LPEN = 0x800000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_SAI2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_SAI2LPEN_Enabled = 0x1
	// Position of SAI3LPEN field.
	RCC_APB2LPENR_SAI3LPEN_Pos = 0x18
	// Bit mask of SAI3LPEN field.
	RCC_APB2LPENR_SAI3LPEN_Msk = 0x1000000
	// Bit SAI3LPEN.
	RCC_APB2LPENR_SAI3LPEN = 0x1000000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_SAI3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_SAI3LPEN_Enabled = 0x1
	// Position of DFSDM1LPEN field.
	RCC_APB2LPENR_DFSDM1LPEN_Pos = 0x1c
	// Bit mask of DFSDM1LPEN field.
	RCC_APB2LPENR_DFSDM1LPEN_Msk = 0x10000000
	// Bit DFSDM1LPEN.
	RCC_APB2LPENR_DFSDM1LPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_DFSDM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_DFSDM1LPEN_Enabled = 0x1
	// Position of HRTIMLPEN field.
	RCC_APB2LPENR_HRTIMLPEN_Pos = 0x1d
	// Bit mask of HRTIMLPEN field.
	RCC_APB2LPENR_HRTIMLPEN_Msk = 0x20000000
	// Bit HRTIMLPEN.
	RCC_APB2LPENR_HRTIMLPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_APB2LPENR_HRTIMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB2LPENR_HRTIMLPEN_Enabled = 0x1

	// APB4LPENR: RCC APB4 Sleep Clock Register
	// Position of SYSCFGLPEN field.
	RCC_APB4LPENR_SYSCFGLPEN_Pos = 0x1
	// Bit mask of SYSCFGLPEN field.
	RCC_APB4LPENR_SYSCFGLPEN_Msk = 0x2
	// Bit SYSCFGLPEN.
	RCC_APB4LPENR_SYSCFGLPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_SYSCFGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_SYSCFGLPEN_Enabled = 0x1
	// Position of LPUART1LPEN field.
	RCC_APB4LPENR_LPUART1LPEN_Pos = 0x3
	// Bit mask of LPUART1LPEN field.
	RCC_APB4LPENR_LPUART1LPEN_Msk = 0x8
	// Bit LPUART1LPEN.
	RCC_APB4LPENR_LPUART1LPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_LPUART1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_LPUART1LPEN_Enabled = 0x1
	// Position of SPI6LPEN field.
	RCC_APB4LPENR_SPI6LPEN_Pos = 0x5
	// Bit mask of SPI6LPEN field.
	RCC_APB4LPENR_SPI6LPEN_Msk = 0x20
	// Bit SPI6LPEN.
	RCC_APB4LPENR_SPI6LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_SPI6LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_SPI6LPEN_Enabled = 0x1
	// Position of I2C4LPEN field.
	RCC_APB4LPENR_I2C4LPEN_Pos = 0x7
	// Bit mask of I2C4LPEN field.
	RCC_APB4LPENR_I2C4LPEN_Msk = 0x80
	// Bit I2C4LPEN.
	RCC_APB4LPENR_I2C4LPEN = 0x80
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_I2C4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_I2C4LPEN_Enabled = 0x1
	// Position of LPTIM2LPEN field.
	RCC_APB4LPENR_LPTIM2LPEN_Pos = 0x9
	// Bit mask of LPTIM2LPEN field.
	RCC_APB4LPENR_LPTIM2LPEN_Msk = 0x200
	// Bit LPTIM2LPEN.
	RCC_APB4LPENR_LPTIM2LPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_LPTIM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_LPTIM2LPEN_Enabled = 0x1
	// Position of LPTIM3LPEN field.
	RCC_APB4LPENR_LPTIM3LPEN_Pos = 0xa
	// Bit mask of LPTIM3LPEN field.
	RCC_APB4LPENR_LPTIM3LPEN_Msk = 0x400
	// Bit LPTIM3LPEN.
	RCC_APB4LPENR_LPTIM3LPEN = 0x400
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_LPTIM3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_LPTIM3LPEN_Enabled = 0x1
	// Position of LPTIM4LPEN field.
	RCC_APB4LPENR_LPTIM4LPEN_Pos = 0xb
	// Bit mask of LPTIM4LPEN field.
	RCC_APB4LPENR_LPTIM4LPEN_Msk = 0x800
	// Bit LPTIM4LPEN.
	RCC_APB4LPENR_LPTIM4LPEN = 0x800
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_LPTIM4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_LPTIM4LPEN_Enabled = 0x1
	// Position of LPTIM5LPEN field.
	RCC_APB4LPENR_LPTIM5LPEN_Pos = 0xc
	// Bit mask of LPTIM5LPEN field.
	RCC_APB4LPENR_LPTIM5LPEN_Msk = 0x1000
	// Bit LPTIM5LPEN.
	RCC_APB4LPENR_LPTIM5LPEN = 0x1000
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_LPTIM5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_LPTIM5LPEN_Enabled = 0x1
	// Position of COMP12LPEN field.
	RCC_APB4LPENR_COMP12LPEN_Pos = 0xe
	// Bit mask of COMP12LPEN field.
	RCC_APB4LPENR_COMP12LPEN_Msk = 0x4000
	// Bit COMP12LPEN.
	RCC_APB4LPENR_COMP12LPEN = 0x4000
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_COMP12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_COMP12LPEN_Enabled = 0x1
	// Position of VREFLPEN field.
	RCC_APB4LPENR_VREFLPEN_Pos = 0xf
	// Bit mask of VREFLPEN field.
	RCC_APB4LPENR_VREFLPEN_Msk = 0x8000
	// Bit VREFLPEN.
	RCC_APB4LPENR_VREFLPEN = 0x8000
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_VREFLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_VREFLPEN_Enabled = 0x1
	// Position of RTCAPBLPEN field.
	RCC_APB4LPENR_RTCAPBLPEN_Pos = 0x10
	// Bit mask of RTCAPBLPEN field.
	RCC_APB4LPENR_RTCAPBLPEN_Msk = 0x10000
	// Bit RTCAPBLPEN.
	RCC_APB4LPENR_RTCAPBLPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_RTCAPBLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_RTCAPBLPEN_Enabled = 0x1
	// Position of SAI4LPEN field.
	RCC_APB4LPENR_SAI4LPEN_Pos = 0x15
	// Bit mask of SAI4LPEN field.
	RCC_APB4LPENR_SAI4LPEN_Msk = 0x200000
	// Bit SAI4LPEN.
	RCC_APB4LPENR_SAI4LPEN = 0x200000
	// The selected clock is disabled during csleep mode
	RCC_APB4LPENR_SAI4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_APB4LPENR_SAI4LPEN_Enabled = 0x1

	// C1_RSR: RCC Reset Status Register
	// Position of RMVF field.
	RCC_C1_RSR_RMVF_Pos = 0x10
	// Bit mask of RMVF field.
	RCC_C1_RSR_RMVF_Msk = 0x10000
	// Bit RMVF.
	RCC_C1_RSR_RMVF = 0x10000
	// Not clearing the the reset flags
	RCC_C1_RSR_RMVF_NotActive = 0x0
	// Clear the reset flags
	RCC_C1_RSR_RMVF_Clear = 0x1
	// Position of CPURSTF field.
	RCC_C1_RSR_CPURSTF_Pos = 0x11
	// Bit mask of CPURSTF field.
	RCC_C1_RSR_CPURSTF_Msk = 0x20000
	// Bit CPURSTF.
	RCC_C1_RSR_CPURSTF = 0x20000
	// No reset occoured for block
	RCC_C1_RSR_CPURSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_CPURSTF_ResetOccourred = 0x1
	// Position of D1RSTF field.
	RCC_C1_RSR_D1RSTF_Pos = 0x13
	// Bit mask of D1RSTF field.
	RCC_C1_RSR_D1RSTF_Msk = 0x80000
	// Bit D1RSTF.
	RCC_C1_RSR_D1RSTF = 0x80000
	// No reset occoured for block
	RCC_C1_RSR_D1RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_D1RSTF_ResetOccourred = 0x1
	// Position of D2RSTF field.
	RCC_C1_RSR_D2RSTF_Pos = 0x14
	// Bit mask of D2RSTF field.
	RCC_C1_RSR_D2RSTF_Msk = 0x100000
	// Bit D2RSTF.
	RCC_C1_RSR_D2RSTF = 0x100000
	// No reset occoured for block
	RCC_C1_RSR_D2RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_D2RSTF_ResetOccourred = 0x1
	// Position of BORRSTF field.
	RCC_C1_RSR_BORRSTF_Pos = 0x15
	// Bit mask of BORRSTF field.
	RCC_C1_RSR_BORRSTF_Msk = 0x200000
	// Bit BORRSTF.
	RCC_C1_RSR_BORRSTF = 0x200000
	// No reset occoured for block
	RCC_C1_RSR_BORRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_BORRSTF_ResetOccourred = 0x1
	// Position of PINRSTF field.
	RCC_C1_RSR_PINRSTF_Pos = 0x16
	// Bit mask of PINRSTF field.
	RCC_C1_RSR_PINRSTF_Msk = 0x400000
	// Bit PINRSTF.
	RCC_C1_RSR_PINRSTF = 0x400000
	// No reset occoured for block
	RCC_C1_RSR_PINRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_PINRSTF_ResetOccourred = 0x1
	// Position of PORRSTF field.
	RCC_C1_RSR_PORRSTF_Pos = 0x17
	// Bit mask of PORRSTF field.
	RCC_C1_RSR_PORRSTF_Msk = 0x800000
	// Bit PORRSTF.
	RCC_C1_RSR_PORRSTF = 0x800000
	// No reset occoured for block
	RCC_C1_RSR_PORRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_PORRSTF_ResetOccourred = 0x1
	// Position of SFTRSTF field.
	RCC_C1_RSR_SFTRSTF_Pos = 0x18
	// Bit mask of SFTRSTF field.
	RCC_C1_RSR_SFTRSTF_Msk = 0x1000000
	// Bit SFTRSTF.
	RCC_C1_RSR_SFTRSTF = 0x1000000
	// No reset occoured for block
	RCC_C1_RSR_SFTRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_SFTRSTF_ResetOccourred = 0x1
	// Position of IWDG1RSTF field.
	RCC_C1_RSR_IWDG1RSTF_Pos = 0x1a
	// Bit mask of IWDG1RSTF field.
	RCC_C1_RSR_IWDG1RSTF_Msk = 0x4000000
	// Bit IWDG1RSTF.
	RCC_C1_RSR_IWDG1RSTF = 0x4000000
	// No reset occoured for block
	RCC_C1_RSR_IWDG1RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_IWDG1RSTF_ResetOccourred = 0x1
	// Position of WWDG1RSTF field.
	RCC_C1_RSR_WWDG1RSTF_Pos = 0x1c
	// Bit mask of WWDG1RSTF field.
	RCC_C1_RSR_WWDG1RSTF_Msk = 0x10000000
	// Bit WWDG1RSTF.
	RCC_C1_RSR_WWDG1RSTF = 0x10000000
	// No reset occoured for block
	RCC_C1_RSR_WWDG1RSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_WWDG1RSTF_ResetOccourred = 0x1
	// Position of LPWRRSTF field.
	RCC_C1_RSR_LPWRRSTF_Pos = 0x1e
	// Bit mask of LPWRRSTF field.
	RCC_C1_RSR_LPWRRSTF_Msk = 0x40000000
	// Bit LPWRRSTF.
	RCC_C1_RSR_LPWRRSTF = 0x40000000
	// No reset occoured for block
	RCC_C1_RSR_LPWRRSTF_NoResetOccoured = 0x0
	// Reset occoured for block
	RCC_C1_RSR_LPWRRSTF_ResetOccourred = 0x1

	// C1_AHB3ENR: RCC AHB3 Clock Register
	// Position of MDMAEN field.
	RCC_C1_AHB3ENR_MDMAEN_Pos = 0x0
	// Bit mask of MDMAEN field.
	RCC_C1_AHB3ENR_MDMAEN_Msk = 0x1
	// Bit MDMAEN.
	RCC_C1_AHB3ENR_MDMAEN = 0x1
	// The selected clock is disabled
	RCC_C1_AHB3ENR_MDMAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB3ENR_MDMAEN_Enabled = 0x1
	// Position of DMA2DEN field.
	RCC_C1_AHB3ENR_DMA2DEN_Pos = 0x4
	// Bit mask of DMA2DEN field.
	RCC_C1_AHB3ENR_DMA2DEN_Msk = 0x10
	// Bit DMA2DEN.
	RCC_C1_AHB3ENR_DMA2DEN = 0x10
	// The selected clock is disabled
	RCC_C1_AHB3ENR_DMA2DEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB3ENR_DMA2DEN_Enabled = 0x1
	// Position of JPGDECEN field.
	RCC_C1_AHB3ENR_JPGDECEN_Pos = 0x5
	// Bit mask of JPGDECEN field.
	RCC_C1_AHB3ENR_JPGDECEN_Msk = 0x20
	// Bit JPGDECEN.
	RCC_C1_AHB3ENR_JPGDECEN = 0x20
	// The selected clock is disabled
	RCC_C1_AHB3ENR_JPGDECEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB3ENR_JPGDECEN_Enabled = 0x1
	// Position of FMCEN field.
	RCC_C1_AHB3ENR_FMCEN_Pos = 0xc
	// Bit mask of FMCEN field.
	RCC_C1_AHB3ENR_FMCEN_Msk = 0x1000
	// Bit FMCEN.
	RCC_C1_AHB3ENR_FMCEN = 0x1000
	// The selected clock is disabled
	RCC_C1_AHB3ENR_FMCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB3ENR_FMCEN_Enabled = 0x1
	// Position of QSPIEN field.
	RCC_C1_AHB3ENR_QSPIEN_Pos = 0xe
	// Bit mask of QSPIEN field.
	RCC_C1_AHB3ENR_QSPIEN_Msk = 0x4000
	// Bit QSPIEN.
	RCC_C1_AHB3ENR_QSPIEN = 0x4000
	// The selected clock is disabled
	RCC_C1_AHB3ENR_QSPIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB3ENR_QSPIEN_Enabled = 0x1
	// Position of SDMMC1EN field.
	RCC_C1_AHB3ENR_SDMMC1EN_Pos = 0x10
	// Bit mask of SDMMC1EN field.
	RCC_C1_AHB3ENR_SDMMC1EN_Msk = 0x10000
	// Bit SDMMC1EN.
	RCC_C1_AHB3ENR_SDMMC1EN = 0x10000
	// The selected clock is disabled
	RCC_C1_AHB3ENR_SDMMC1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB3ENR_SDMMC1EN_Enabled = 0x1

	// C1_AHB1ENR: RCC AHB1 Clock Register
	// Position of DMA1EN field.
	RCC_C1_AHB1ENR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_C1_AHB1ENR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_C1_AHB1ENR_DMA1EN = 0x1
	// The selected clock is disabled
	RCC_C1_AHB1ENR_DMA1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_DMA1EN_Enabled = 0x1
	// Position of DMA2EN field.
	RCC_C1_AHB1ENR_DMA2EN_Pos = 0x1
	// Bit mask of DMA2EN field.
	RCC_C1_AHB1ENR_DMA2EN_Msk = 0x2
	// Bit DMA2EN.
	RCC_C1_AHB1ENR_DMA2EN = 0x2
	// The selected clock is disabled
	RCC_C1_AHB1ENR_DMA2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_DMA2EN_Enabled = 0x1
	// Position of ADC12EN field.
	RCC_C1_AHB1ENR_ADC12EN_Pos = 0x5
	// Bit mask of ADC12EN field.
	RCC_C1_AHB1ENR_ADC12EN_Msk = 0x20
	// Bit ADC12EN.
	RCC_C1_AHB1ENR_ADC12EN = 0x20
	// The selected clock is disabled
	RCC_C1_AHB1ENR_ADC12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_ADC12EN_Enabled = 0x1
	// Position of ETH1MACEN field.
	RCC_C1_AHB1ENR_ETH1MACEN_Pos = 0xf
	// Bit mask of ETH1MACEN field.
	RCC_C1_AHB1ENR_ETH1MACEN_Msk = 0x8000
	// Bit ETH1MACEN.
	RCC_C1_AHB1ENR_ETH1MACEN = 0x8000
	// The selected clock is disabled
	RCC_C1_AHB1ENR_ETH1MACEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_ETH1MACEN_Enabled = 0x1
	// Position of ETH1TXEN field.
	RCC_C1_AHB1ENR_ETH1TXEN_Pos = 0x10
	// Bit mask of ETH1TXEN field.
	RCC_C1_AHB1ENR_ETH1TXEN_Msk = 0x10000
	// Bit ETH1TXEN.
	RCC_C1_AHB1ENR_ETH1TXEN = 0x10000
	// The selected clock is disabled
	RCC_C1_AHB1ENR_ETH1TXEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_ETH1TXEN_Enabled = 0x1
	// Position of ETH1RXEN field.
	RCC_C1_AHB1ENR_ETH1RXEN_Pos = 0x11
	// Bit mask of ETH1RXEN field.
	RCC_C1_AHB1ENR_ETH1RXEN_Msk = 0x20000
	// Bit ETH1RXEN.
	RCC_C1_AHB1ENR_ETH1RXEN = 0x20000
	// The selected clock is disabled
	RCC_C1_AHB1ENR_ETH1RXEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_ETH1RXEN_Enabled = 0x1
	// Position of USB1OTGEN field.
	RCC_C1_AHB1ENR_USB1OTGEN_Pos = 0x19
	// Bit mask of USB1OTGEN field.
	RCC_C1_AHB1ENR_USB1OTGEN_Msk = 0x2000000
	// Bit USB1OTGEN.
	RCC_C1_AHB1ENR_USB1OTGEN = 0x2000000
	// The selected clock is disabled
	RCC_C1_AHB1ENR_USB1OTGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_USB1OTGEN_Enabled = 0x1
	// Position of USB1ULPIEN field.
	RCC_C1_AHB1ENR_USB1ULPIEN_Pos = 0x1a
	// Bit mask of USB1ULPIEN field.
	RCC_C1_AHB1ENR_USB1ULPIEN_Msk = 0x4000000
	// Bit USB1ULPIEN.
	RCC_C1_AHB1ENR_USB1ULPIEN = 0x4000000
	// The selected clock is disabled
	RCC_C1_AHB1ENR_USB1ULPIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_USB1ULPIEN_Enabled = 0x1
	// Position of USB2OTGEN field.
	RCC_C1_AHB1ENR_USB2OTGEN_Pos = 0x1b
	// Bit mask of USB2OTGEN field.
	RCC_C1_AHB1ENR_USB2OTGEN_Msk = 0x8000000
	// Bit USB2OTGEN.
	RCC_C1_AHB1ENR_USB2OTGEN = 0x8000000
	// The selected clock is disabled
	RCC_C1_AHB1ENR_USB2OTGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_USB2OTGEN_Enabled = 0x1
	// Position of USB2ULPIEN field.
	RCC_C1_AHB1ENR_USB2ULPIEN_Pos = 0x1c
	// Bit mask of USB2ULPIEN field.
	RCC_C1_AHB1ENR_USB2ULPIEN_Msk = 0x10000000
	// Bit USB2ULPIEN.
	RCC_C1_AHB1ENR_USB2ULPIEN = 0x10000000
	// The selected clock is disabled
	RCC_C1_AHB1ENR_USB2ULPIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB1ENR_USB2ULPIEN_Enabled = 0x1

	// C1_AHB2ENR: RCC AHB2 Clock Register
	// Position of DCMIEN field.
	RCC_C1_AHB2ENR_DCMIEN_Pos = 0x0
	// Bit mask of DCMIEN field.
	RCC_C1_AHB2ENR_DCMIEN_Msk = 0x1
	// Bit DCMIEN.
	RCC_C1_AHB2ENR_DCMIEN = 0x1
	// The selected clock is disabled
	RCC_C1_AHB2ENR_DCMIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_DCMIEN_Enabled = 0x1
	// Position of CRYPTEN field.
	RCC_C1_AHB2ENR_CRYPTEN_Pos = 0x4
	// Bit mask of CRYPTEN field.
	RCC_C1_AHB2ENR_CRYPTEN_Msk = 0x10
	// Bit CRYPTEN.
	RCC_C1_AHB2ENR_CRYPTEN = 0x10
	// The selected clock is disabled
	RCC_C1_AHB2ENR_CRYPTEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_CRYPTEN_Enabled = 0x1
	// Position of HASHEN field.
	RCC_C1_AHB2ENR_HASHEN_Pos = 0x5
	// Bit mask of HASHEN field.
	RCC_C1_AHB2ENR_HASHEN_Msk = 0x20
	// Bit HASHEN.
	RCC_C1_AHB2ENR_HASHEN = 0x20
	// The selected clock is disabled
	RCC_C1_AHB2ENR_HASHEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_HASHEN_Enabled = 0x1
	// Position of RNGEN field.
	RCC_C1_AHB2ENR_RNGEN_Pos = 0x6
	// Bit mask of RNGEN field.
	RCC_C1_AHB2ENR_RNGEN_Msk = 0x40
	// Bit RNGEN.
	RCC_C1_AHB2ENR_RNGEN = 0x40
	// The selected clock is disabled
	RCC_C1_AHB2ENR_RNGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_RNGEN_Enabled = 0x1
	// Position of SDMMC2EN field.
	RCC_C1_AHB2ENR_SDMMC2EN_Pos = 0x9
	// Bit mask of SDMMC2EN field.
	RCC_C1_AHB2ENR_SDMMC2EN_Msk = 0x200
	// Bit SDMMC2EN.
	RCC_C1_AHB2ENR_SDMMC2EN = 0x200
	// The selected clock is disabled
	RCC_C1_AHB2ENR_SDMMC2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_SDMMC2EN_Enabled = 0x1
	// Position of SRAM1EN field.
	RCC_C1_AHB2ENR_SRAM1EN_Pos = 0x1d
	// Bit mask of SRAM1EN field.
	RCC_C1_AHB2ENR_SRAM1EN_Msk = 0x20000000
	// Bit SRAM1EN.
	RCC_C1_AHB2ENR_SRAM1EN = 0x20000000
	// The selected clock is disabled
	RCC_C1_AHB2ENR_SRAM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_SRAM1EN_Enabled = 0x1
	// Position of SRAM2EN field.
	RCC_C1_AHB2ENR_SRAM2EN_Pos = 0x1e
	// Bit mask of SRAM2EN field.
	RCC_C1_AHB2ENR_SRAM2EN_Msk = 0x40000000
	// Bit SRAM2EN.
	RCC_C1_AHB2ENR_SRAM2EN = 0x40000000
	// The selected clock is disabled
	RCC_C1_AHB2ENR_SRAM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_SRAM2EN_Enabled = 0x1
	// Position of SRAM3EN field.
	RCC_C1_AHB2ENR_SRAM3EN_Pos = 0x1f
	// Bit mask of SRAM3EN field.
	RCC_C1_AHB2ENR_SRAM3EN_Msk = 0x80000000
	// Bit SRAM3EN.
	RCC_C1_AHB2ENR_SRAM3EN = 0x80000000
	// The selected clock is disabled
	RCC_C1_AHB2ENR_SRAM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB2ENR_SRAM3EN_Enabled = 0x1

	// C1_AHB4ENR: RCC AHB4 Clock Register
	// Position of GPIOAEN field.
	RCC_C1_AHB4ENR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_C1_AHB4ENR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_C1_AHB4ENR_GPIOAEN = 0x1
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOAEN_Enabled = 0x1
	// Position of GPIOBEN field.
	RCC_C1_AHB4ENR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_C1_AHB4ENR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_C1_AHB4ENR_GPIOBEN = 0x2
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOBEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOBEN_Enabled = 0x1
	// Position of GPIOCEN field.
	RCC_C1_AHB4ENR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_C1_AHB4ENR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_C1_AHB4ENR_GPIOCEN = 0x4
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOCEN_Enabled = 0x1
	// Position of GPIODEN field.
	RCC_C1_AHB4ENR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_C1_AHB4ENR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_C1_AHB4ENR_GPIODEN = 0x8
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIODEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIODEN_Enabled = 0x1
	// Position of GPIOEEN field.
	RCC_C1_AHB4ENR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_C1_AHB4ENR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_C1_AHB4ENR_GPIOEEN = 0x10
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOEEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOEEN_Enabled = 0x1
	// Position of GPIOFEN field.
	RCC_C1_AHB4ENR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_C1_AHB4ENR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_C1_AHB4ENR_GPIOFEN = 0x20
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOFEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOFEN_Enabled = 0x1
	// Position of GPIOGEN field.
	RCC_C1_AHB4ENR_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_C1_AHB4ENR_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_C1_AHB4ENR_GPIOGEN = 0x40
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOGEN_Enabled = 0x1
	// Position of GPIOHEN field.
	RCC_C1_AHB4ENR_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_C1_AHB4ENR_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_C1_AHB4ENR_GPIOHEN = 0x80
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOHEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOHEN_Enabled = 0x1
	// Position of GPIOIEN field.
	RCC_C1_AHB4ENR_GPIOIEN_Pos = 0x8
	// Bit mask of GPIOIEN field.
	RCC_C1_AHB4ENR_GPIOIEN_Msk = 0x100
	// Bit GPIOIEN.
	RCC_C1_AHB4ENR_GPIOIEN = 0x100
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOIEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOIEN_Enabled = 0x1
	// Position of GPIOJEN field.
	RCC_C1_AHB4ENR_GPIOJEN_Pos = 0x9
	// Bit mask of GPIOJEN field.
	RCC_C1_AHB4ENR_GPIOJEN_Msk = 0x200
	// Bit GPIOJEN.
	RCC_C1_AHB4ENR_GPIOJEN = 0x200
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOJEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOJEN_Enabled = 0x1
	// Position of GPIOKEN field.
	RCC_C1_AHB4ENR_GPIOKEN_Pos = 0xa
	// Bit mask of GPIOKEN field.
	RCC_C1_AHB4ENR_GPIOKEN_Msk = 0x400
	// Bit GPIOKEN.
	RCC_C1_AHB4ENR_GPIOKEN = 0x400
	// The selected clock is disabled
	RCC_C1_AHB4ENR_GPIOKEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_GPIOKEN_Enabled = 0x1
	// Position of CRCEN field.
	RCC_C1_AHB4ENR_CRCEN_Pos = 0x13
	// Bit mask of CRCEN field.
	RCC_C1_AHB4ENR_CRCEN_Msk = 0x80000
	// Bit CRCEN.
	RCC_C1_AHB4ENR_CRCEN = 0x80000
	// The selected clock is disabled
	RCC_C1_AHB4ENR_CRCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_CRCEN_Enabled = 0x1
	// Position of BDMAEN field.
	RCC_C1_AHB4ENR_BDMAEN_Pos = 0x15
	// Bit mask of BDMAEN field.
	RCC_C1_AHB4ENR_BDMAEN_Msk = 0x200000
	// Bit BDMAEN.
	RCC_C1_AHB4ENR_BDMAEN = 0x200000
	// The selected clock is disabled
	RCC_C1_AHB4ENR_BDMAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_BDMAEN_Enabled = 0x1
	// Position of ADC3EN field.
	RCC_C1_AHB4ENR_ADC3EN_Pos = 0x18
	// Bit mask of ADC3EN field.
	RCC_C1_AHB4ENR_ADC3EN_Msk = 0x1000000
	// Bit ADC3EN.
	RCC_C1_AHB4ENR_ADC3EN = 0x1000000
	// The selected clock is disabled
	RCC_C1_AHB4ENR_ADC3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_ADC3EN_Enabled = 0x1
	// Position of HSEMEN field.
	RCC_C1_AHB4ENR_HSEMEN_Pos = 0x19
	// Bit mask of HSEMEN field.
	RCC_C1_AHB4ENR_HSEMEN_Msk = 0x2000000
	// Bit HSEMEN.
	RCC_C1_AHB4ENR_HSEMEN = 0x2000000
	// The selected clock is disabled
	RCC_C1_AHB4ENR_HSEMEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_HSEMEN_Enabled = 0x1
	// Position of BKPRAMEN field.
	RCC_C1_AHB4ENR_BKPRAMEN_Pos = 0x1c
	// Bit mask of BKPRAMEN field.
	RCC_C1_AHB4ENR_BKPRAMEN_Msk = 0x10000000
	// Bit BKPRAMEN.
	RCC_C1_AHB4ENR_BKPRAMEN = 0x10000000
	// The selected clock is disabled
	RCC_C1_AHB4ENR_BKPRAMEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_AHB4ENR_BKPRAMEN_Enabled = 0x1

	// C1_APB3ENR: RCC APB3 Clock Register
	// Position of LTDCEN field.
	RCC_C1_APB3ENR_LTDCEN_Pos = 0x3
	// Bit mask of LTDCEN field.
	RCC_C1_APB3ENR_LTDCEN_Msk = 0x8
	// Bit LTDCEN.
	RCC_C1_APB3ENR_LTDCEN = 0x8
	// The selected clock is disabled
	RCC_C1_APB3ENR_LTDCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB3ENR_LTDCEN_Enabled = 0x1
	// Position of WWDG1EN field.
	RCC_C1_APB3ENR_WWDG1EN_Pos = 0x6
	// Bit mask of WWDG1EN field.
	RCC_C1_APB3ENR_WWDG1EN_Msk = 0x40
	// Bit WWDG1EN.
	RCC_C1_APB3ENR_WWDG1EN = 0x40
	// The selected clock is disabled
	RCC_C1_APB3ENR_WWDG1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB3ENR_WWDG1EN_Enabled = 0x1

	// C1_APB1LENR: RCC APB1 Clock Register
	// Position of TIM2EN field.
	RCC_C1_APB1LENR_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_C1_APB1LENR_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_C1_APB1LENR_TIM2EN = 0x1
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM2EN_Enabled = 0x1
	// Position of TIM3EN field.
	RCC_C1_APB1LENR_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_C1_APB1LENR_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_C1_APB1LENR_TIM3EN = 0x2
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM3EN_Enabled = 0x1
	// Position of TIM4EN field.
	RCC_C1_APB1LENR_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_C1_APB1LENR_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_C1_APB1LENR_TIM4EN = 0x4
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM4EN_Enabled = 0x1
	// Position of TIM5EN field.
	RCC_C1_APB1LENR_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_C1_APB1LENR_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_C1_APB1LENR_TIM5EN = 0x8
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM5EN_Enabled = 0x1
	// Position of TIM6EN field.
	RCC_C1_APB1LENR_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_C1_APB1LENR_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_C1_APB1LENR_TIM6EN = 0x10
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM6EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM6EN_Enabled = 0x1
	// Position of TIM7EN field.
	RCC_C1_APB1LENR_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_C1_APB1LENR_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_C1_APB1LENR_TIM7EN = 0x20
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM7EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM7EN_Enabled = 0x1
	// Position of TIM12EN field.
	RCC_C1_APB1LENR_TIM12EN_Pos = 0x6
	// Bit mask of TIM12EN field.
	RCC_C1_APB1LENR_TIM12EN_Msk = 0x40
	// Bit TIM12EN.
	RCC_C1_APB1LENR_TIM12EN = 0x40
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM12EN_Enabled = 0x1
	// Position of TIM13EN field.
	RCC_C1_APB1LENR_TIM13EN_Pos = 0x7
	// Bit mask of TIM13EN field.
	RCC_C1_APB1LENR_TIM13EN_Msk = 0x80
	// Bit TIM13EN.
	RCC_C1_APB1LENR_TIM13EN = 0x80
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM13EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM13EN_Enabled = 0x1
	// Position of TIM14EN field.
	RCC_C1_APB1LENR_TIM14EN_Pos = 0x8
	// Bit mask of TIM14EN field.
	RCC_C1_APB1LENR_TIM14EN_Msk = 0x100
	// Bit TIM14EN.
	RCC_C1_APB1LENR_TIM14EN = 0x100
	// The selected clock is disabled
	RCC_C1_APB1LENR_TIM14EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_TIM14EN_Enabled = 0x1
	// Position of LPTIM1EN field.
	RCC_C1_APB1LENR_LPTIM1EN_Pos = 0x9
	// Bit mask of LPTIM1EN field.
	RCC_C1_APB1LENR_LPTIM1EN_Msk = 0x200
	// Bit LPTIM1EN.
	RCC_C1_APB1LENR_LPTIM1EN = 0x200
	// The selected clock is disabled
	RCC_C1_APB1LENR_LPTIM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_LPTIM1EN_Enabled = 0x1
	// Position of SPI2EN field.
	RCC_C1_APB1LENR_SPI2EN_Pos = 0xe
	// Bit mask of SPI2EN field.
	RCC_C1_APB1LENR_SPI2EN_Msk = 0x4000
	// Bit SPI2EN.
	RCC_C1_APB1LENR_SPI2EN = 0x4000
	// The selected clock is disabled
	RCC_C1_APB1LENR_SPI2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_SPI2EN_Enabled = 0x1
	// Position of SPI3EN field.
	RCC_C1_APB1LENR_SPI3EN_Pos = 0xf
	// Bit mask of SPI3EN field.
	RCC_C1_APB1LENR_SPI3EN_Msk = 0x8000
	// Bit SPI3EN.
	RCC_C1_APB1LENR_SPI3EN = 0x8000
	// The selected clock is disabled
	RCC_C1_APB1LENR_SPI3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_SPI3EN_Enabled = 0x1
	// Position of SPDIFRXEN field.
	RCC_C1_APB1LENR_SPDIFRXEN_Pos = 0x10
	// Bit mask of SPDIFRXEN field.
	RCC_C1_APB1LENR_SPDIFRXEN_Msk = 0x10000
	// Bit SPDIFRXEN.
	RCC_C1_APB1LENR_SPDIFRXEN = 0x10000
	// The selected clock is disabled
	RCC_C1_APB1LENR_SPDIFRXEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_SPDIFRXEN_Enabled = 0x1
	// Position of USART2EN field.
	RCC_C1_APB1LENR_USART2EN_Pos = 0x11
	// Bit mask of USART2EN field.
	RCC_C1_APB1LENR_USART2EN_Msk = 0x20000
	// Bit USART2EN.
	RCC_C1_APB1LENR_USART2EN = 0x20000
	// The selected clock is disabled
	RCC_C1_APB1LENR_USART2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_USART2EN_Enabled = 0x1
	// Position of USART3EN field.
	RCC_C1_APB1LENR_USART3EN_Pos = 0x12
	// Bit mask of USART3EN field.
	RCC_C1_APB1LENR_USART3EN_Msk = 0x40000
	// Bit USART3EN.
	RCC_C1_APB1LENR_USART3EN = 0x40000
	// The selected clock is disabled
	RCC_C1_APB1LENR_USART3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_USART3EN_Enabled = 0x1
	// Position of UART4EN field.
	RCC_C1_APB1LENR_UART4EN_Pos = 0x13
	// Bit mask of UART4EN field.
	RCC_C1_APB1LENR_UART4EN_Msk = 0x80000
	// Bit UART4EN.
	RCC_C1_APB1LENR_UART4EN = 0x80000
	// The selected clock is disabled
	RCC_C1_APB1LENR_UART4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_UART4EN_Enabled = 0x1
	// Position of UART5EN field.
	RCC_C1_APB1LENR_UART5EN_Pos = 0x14
	// Bit mask of UART5EN field.
	RCC_C1_APB1LENR_UART5EN_Msk = 0x100000
	// Bit UART5EN.
	RCC_C1_APB1LENR_UART5EN = 0x100000
	// The selected clock is disabled
	RCC_C1_APB1LENR_UART5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_UART5EN_Enabled = 0x1
	// Position of I2C1EN field.
	RCC_C1_APB1LENR_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_C1_APB1LENR_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_C1_APB1LENR_I2C1EN = 0x200000
	// The selected clock is disabled
	RCC_C1_APB1LENR_I2C1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_I2C1EN_Enabled = 0x1
	// Position of I2C2EN field.
	RCC_C1_APB1LENR_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_C1_APB1LENR_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_C1_APB1LENR_I2C2EN = 0x400000
	// The selected clock is disabled
	RCC_C1_APB1LENR_I2C2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_I2C2EN_Enabled = 0x1
	// Position of I2C3EN field.
	RCC_C1_APB1LENR_I2C3EN_Pos = 0x17
	// Bit mask of I2C3EN field.
	RCC_C1_APB1LENR_I2C3EN_Msk = 0x800000
	// Bit I2C3EN.
	RCC_C1_APB1LENR_I2C3EN = 0x800000
	// The selected clock is disabled
	RCC_C1_APB1LENR_I2C3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_I2C3EN_Enabled = 0x1
	// Position of CECEN field.
	RCC_C1_APB1LENR_CECEN_Pos = 0x1b
	// Bit mask of CECEN field.
	RCC_C1_APB1LENR_CECEN_Msk = 0x8000000
	// Bit CECEN.
	RCC_C1_APB1LENR_CECEN = 0x8000000
	// The selected clock is disabled
	RCC_C1_APB1LENR_CECEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_CECEN_Enabled = 0x1
	// Position of DAC12EN field.
	RCC_C1_APB1LENR_DAC12EN_Pos = 0x1d
	// Bit mask of DAC12EN field.
	RCC_C1_APB1LENR_DAC12EN_Msk = 0x20000000
	// Bit DAC12EN.
	RCC_C1_APB1LENR_DAC12EN = 0x20000000
	// The selected clock is disabled
	RCC_C1_APB1LENR_DAC12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_DAC12EN_Enabled = 0x1
	// Position of UART7EN field.
	RCC_C1_APB1LENR_UART7EN_Pos = 0x1e
	// Bit mask of UART7EN field.
	RCC_C1_APB1LENR_UART7EN_Msk = 0x40000000
	// Bit UART7EN.
	RCC_C1_APB1LENR_UART7EN = 0x40000000
	// The selected clock is disabled
	RCC_C1_APB1LENR_UART7EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_UART7EN_Enabled = 0x1
	// Position of UART8EN field.
	RCC_C1_APB1LENR_UART8EN_Pos = 0x1f
	// Bit mask of UART8EN field.
	RCC_C1_APB1LENR_UART8EN_Msk = 0x80000000
	// Bit UART8EN.
	RCC_C1_APB1LENR_UART8EN = 0x80000000
	// The selected clock is disabled
	RCC_C1_APB1LENR_UART8EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1LENR_UART8EN_Enabled = 0x1

	// C1_APB1HENR: RCC APB1 Clock Register
	// Position of CRSEN field.
	RCC_C1_APB1HENR_CRSEN_Pos = 0x1
	// Bit mask of CRSEN field.
	RCC_C1_APB1HENR_CRSEN_Msk = 0x2
	// Bit CRSEN.
	RCC_C1_APB1HENR_CRSEN = 0x2
	// The selected clock is disabled
	RCC_C1_APB1HENR_CRSEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1HENR_CRSEN_Enabled = 0x1
	// Position of SWPEN field.
	RCC_C1_APB1HENR_SWPEN_Pos = 0x2
	// Bit mask of SWPEN field.
	RCC_C1_APB1HENR_SWPEN_Msk = 0x4
	// Bit SWPEN.
	RCC_C1_APB1HENR_SWPEN = 0x4
	// The selected clock is disabled
	RCC_C1_APB1HENR_SWPEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1HENR_SWPEN_Enabled = 0x1
	// Position of OPAMPEN field.
	RCC_C1_APB1HENR_OPAMPEN_Pos = 0x4
	// Bit mask of OPAMPEN field.
	RCC_C1_APB1HENR_OPAMPEN_Msk = 0x10
	// Bit OPAMPEN.
	RCC_C1_APB1HENR_OPAMPEN = 0x10
	// The selected clock is disabled
	RCC_C1_APB1HENR_OPAMPEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1HENR_OPAMPEN_Enabled = 0x1
	// Position of MDIOSEN field.
	RCC_C1_APB1HENR_MDIOSEN_Pos = 0x5
	// Bit mask of MDIOSEN field.
	RCC_C1_APB1HENR_MDIOSEN_Msk = 0x20
	// Bit MDIOSEN.
	RCC_C1_APB1HENR_MDIOSEN = 0x20
	// The selected clock is disabled
	RCC_C1_APB1HENR_MDIOSEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1HENR_MDIOSEN_Enabled = 0x1
	// Position of FDCANEN field.
	RCC_C1_APB1HENR_FDCANEN_Pos = 0x8
	// Bit mask of FDCANEN field.
	RCC_C1_APB1HENR_FDCANEN_Msk = 0x100
	// Bit FDCANEN.
	RCC_C1_APB1HENR_FDCANEN = 0x100
	// The selected clock is disabled
	RCC_C1_APB1HENR_FDCANEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB1HENR_FDCANEN_Enabled = 0x1

	// C1_APB2ENR: RCC APB2 Clock Register
	// Position of TIM1EN field.
	RCC_C1_APB2ENR_TIM1EN_Pos = 0x0
	// Bit mask of TIM1EN field.
	RCC_C1_APB2ENR_TIM1EN_Msk = 0x1
	// Bit TIM1EN.
	RCC_C1_APB2ENR_TIM1EN = 0x1
	// The selected clock is disabled
	RCC_C1_APB2ENR_TIM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_TIM1EN_Enabled = 0x1
	// Position of TIM8EN field.
	RCC_C1_APB2ENR_TIM8EN_Pos = 0x1
	// Bit mask of TIM8EN field.
	RCC_C1_APB2ENR_TIM8EN_Msk = 0x2
	// Bit TIM8EN.
	RCC_C1_APB2ENR_TIM8EN = 0x2
	// The selected clock is disabled
	RCC_C1_APB2ENR_TIM8EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_TIM8EN_Enabled = 0x1
	// Position of USART1EN field.
	RCC_C1_APB2ENR_USART1EN_Pos = 0x4
	// Bit mask of USART1EN field.
	RCC_C1_APB2ENR_USART1EN_Msk = 0x10
	// Bit USART1EN.
	RCC_C1_APB2ENR_USART1EN = 0x10
	// The selected clock is disabled
	RCC_C1_APB2ENR_USART1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_USART1EN_Enabled = 0x1
	// Position of USART6EN field.
	RCC_C1_APB2ENR_USART6EN_Pos = 0x5
	// Bit mask of USART6EN field.
	RCC_C1_APB2ENR_USART6EN_Msk = 0x20
	// Bit USART6EN.
	RCC_C1_APB2ENR_USART6EN = 0x20
	// The selected clock is disabled
	RCC_C1_APB2ENR_USART6EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_USART6EN_Enabled = 0x1
	// Position of SPI1EN field.
	RCC_C1_APB2ENR_SPI1EN_Pos = 0xc
	// Bit mask of SPI1EN field.
	RCC_C1_APB2ENR_SPI1EN_Msk = 0x1000
	// Bit SPI1EN.
	RCC_C1_APB2ENR_SPI1EN = 0x1000
	// The selected clock is disabled
	RCC_C1_APB2ENR_SPI1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_SPI1EN_Enabled = 0x1
	// Position of SPI4EN field.
	RCC_C1_APB2ENR_SPI4EN_Pos = 0xd
	// Bit mask of SPI4EN field.
	RCC_C1_APB2ENR_SPI4EN_Msk = 0x2000
	// Bit SPI4EN.
	RCC_C1_APB2ENR_SPI4EN = 0x2000
	// The selected clock is disabled
	RCC_C1_APB2ENR_SPI4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_SPI4EN_Enabled = 0x1
	// Position of TIM16EN field.
	RCC_C1_APB2ENR_TIM16EN_Pos = 0x11
	// Bit mask of TIM16EN field.
	RCC_C1_APB2ENR_TIM16EN_Msk = 0x20000
	// Bit TIM16EN.
	RCC_C1_APB2ENR_TIM16EN = 0x20000
	// The selected clock is disabled
	RCC_C1_APB2ENR_TIM16EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_TIM16EN_Enabled = 0x1
	// Position of TIM15EN field.
	RCC_C1_APB2ENR_TIM15EN_Pos = 0x10
	// Bit mask of TIM15EN field.
	RCC_C1_APB2ENR_TIM15EN_Msk = 0x10000
	// Bit TIM15EN.
	RCC_C1_APB2ENR_TIM15EN = 0x10000
	// The selected clock is disabled
	RCC_C1_APB2ENR_TIM15EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_TIM15EN_Enabled = 0x1
	// Position of TIM17EN field.
	RCC_C1_APB2ENR_TIM17EN_Pos = 0x12
	// Bit mask of TIM17EN field.
	RCC_C1_APB2ENR_TIM17EN_Msk = 0x40000
	// Bit TIM17EN.
	RCC_C1_APB2ENR_TIM17EN = 0x40000
	// The selected clock is disabled
	RCC_C1_APB2ENR_TIM17EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_TIM17EN_Enabled = 0x1
	// Position of SPI5EN field.
	RCC_C1_APB2ENR_SPI5EN_Pos = 0x14
	// Bit mask of SPI5EN field.
	RCC_C1_APB2ENR_SPI5EN_Msk = 0x100000
	// Bit SPI5EN.
	RCC_C1_APB2ENR_SPI5EN = 0x100000
	// The selected clock is disabled
	RCC_C1_APB2ENR_SPI5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_SPI5EN_Enabled = 0x1
	// Position of SAI1EN field.
	RCC_C1_APB2ENR_SAI1EN_Pos = 0x16
	// Bit mask of SAI1EN field.
	RCC_C1_APB2ENR_SAI1EN_Msk = 0x400000
	// Bit SAI1EN.
	RCC_C1_APB2ENR_SAI1EN = 0x400000
	// The selected clock is disabled
	RCC_C1_APB2ENR_SAI1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_SAI1EN_Enabled = 0x1
	// Position of SAI2EN field.
	RCC_C1_APB2ENR_SAI2EN_Pos = 0x17
	// Bit mask of SAI2EN field.
	RCC_C1_APB2ENR_SAI2EN_Msk = 0x800000
	// Bit SAI2EN.
	RCC_C1_APB2ENR_SAI2EN = 0x800000
	// The selected clock is disabled
	RCC_C1_APB2ENR_SAI2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_SAI2EN_Enabled = 0x1
	// Position of SAI3EN field.
	RCC_C1_APB2ENR_SAI3EN_Pos = 0x18
	// Bit mask of SAI3EN field.
	RCC_C1_APB2ENR_SAI3EN_Msk = 0x1000000
	// Bit SAI3EN.
	RCC_C1_APB2ENR_SAI3EN = 0x1000000
	// The selected clock is disabled
	RCC_C1_APB2ENR_SAI3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_SAI3EN_Enabled = 0x1
	// Position of DFSDM1EN field.
	RCC_C1_APB2ENR_DFSDM1EN_Pos = 0x1c
	// Bit mask of DFSDM1EN field.
	RCC_C1_APB2ENR_DFSDM1EN_Msk = 0x10000000
	// Bit DFSDM1EN.
	RCC_C1_APB2ENR_DFSDM1EN = 0x10000000
	// The selected clock is disabled
	RCC_C1_APB2ENR_DFSDM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_DFSDM1EN_Enabled = 0x1
	// Position of HRTIMEN field.
	RCC_C1_APB2ENR_HRTIMEN_Pos = 0x1d
	// Bit mask of HRTIMEN field.
	RCC_C1_APB2ENR_HRTIMEN_Msk = 0x20000000
	// Bit HRTIMEN.
	RCC_C1_APB2ENR_HRTIMEN = 0x20000000
	// The selected clock is disabled
	RCC_C1_APB2ENR_HRTIMEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB2ENR_HRTIMEN_Enabled = 0x1

	// C1_APB4ENR: RCC APB4 Clock Register
	// Position of SYSCFGEN field.
	RCC_C1_APB4ENR_SYSCFGEN_Pos = 0x1
	// Bit mask of SYSCFGEN field.
	RCC_C1_APB4ENR_SYSCFGEN_Msk = 0x2
	// Bit SYSCFGEN.
	RCC_C1_APB4ENR_SYSCFGEN = 0x2
	// The selected clock is disabled
	RCC_C1_APB4ENR_SYSCFGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_SYSCFGEN_Enabled = 0x1
	// Position of LPUART1EN field.
	RCC_C1_APB4ENR_LPUART1EN_Pos = 0x3
	// Bit mask of LPUART1EN field.
	RCC_C1_APB4ENR_LPUART1EN_Msk = 0x8
	// Bit LPUART1EN.
	RCC_C1_APB4ENR_LPUART1EN = 0x8
	// The selected clock is disabled
	RCC_C1_APB4ENR_LPUART1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_LPUART1EN_Enabled = 0x1
	// Position of SPI6EN field.
	RCC_C1_APB4ENR_SPI6EN_Pos = 0x5
	// Bit mask of SPI6EN field.
	RCC_C1_APB4ENR_SPI6EN_Msk = 0x20
	// Bit SPI6EN.
	RCC_C1_APB4ENR_SPI6EN = 0x20
	// The selected clock is disabled
	RCC_C1_APB4ENR_SPI6EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_SPI6EN_Enabled = 0x1
	// Position of I2C4EN field.
	RCC_C1_APB4ENR_I2C4EN_Pos = 0x7
	// Bit mask of I2C4EN field.
	RCC_C1_APB4ENR_I2C4EN_Msk = 0x80
	// Bit I2C4EN.
	RCC_C1_APB4ENR_I2C4EN = 0x80
	// The selected clock is disabled
	RCC_C1_APB4ENR_I2C4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_I2C4EN_Enabled = 0x1
	// Position of LPTIM2EN field.
	RCC_C1_APB4ENR_LPTIM2EN_Pos = 0x9
	// Bit mask of LPTIM2EN field.
	RCC_C1_APB4ENR_LPTIM2EN_Msk = 0x200
	// Bit LPTIM2EN.
	RCC_C1_APB4ENR_LPTIM2EN = 0x200
	// The selected clock is disabled
	RCC_C1_APB4ENR_LPTIM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_LPTIM2EN_Enabled = 0x1
	// Position of LPTIM3EN field.
	RCC_C1_APB4ENR_LPTIM3EN_Pos = 0xa
	// Bit mask of LPTIM3EN field.
	RCC_C1_APB4ENR_LPTIM3EN_Msk = 0x400
	// Bit LPTIM3EN.
	RCC_C1_APB4ENR_LPTIM3EN = 0x400
	// The selected clock is disabled
	RCC_C1_APB4ENR_LPTIM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_LPTIM3EN_Enabled = 0x1
	// Position of LPTIM4EN field.
	RCC_C1_APB4ENR_LPTIM4EN_Pos = 0xb
	// Bit mask of LPTIM4EN field.
	RCC_C1_APB4ENR_LPTIM4EN_Msk = 0x800
	// Bit LPTIM4EN.
	RCC_C1_APB4ENR_LPTIM4EN = 0x800
	// The selected clock is disabled
	RCC_C1_APB4ENR_LPTIM4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_LPTIM4EN_Enabled = 0x1
	// Position of LPTIM5EN field.
	RCC_C1_APB4ENR_LPTIM5EN_Pos = 0xc
	// Bit mask of LPTIM5EN field.
	RCC_C1_APB4ENR_LPTIM5EN_Msk = 0x1000
	// Bit LPTIM5EN.
	RCC_C1_APB4ENR_LPTIM5EN = 0x1000
	// The selected clock is disabled
	RCC_C1_APB4ENR_LPTIM5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_LPTIM5EN_Enabled = 0x1
	// Position of COMP12EN field.
	RCC_C1_APB4ENR_COMP12EN_Pos = 0xe
	// Bit mask of COMP12EN field.
	RCC_C1_APB4ENR_COMP12EN_Msk = 0x4000
	// Bit COMP12EN.
	RCC_C1_APB4ENR_COMP12EN = 0x4000
	// The selected clock is disabled
	RCC_C1_APB4ENR_COMP12EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_COMP12EN_Enabled = 0x1
	// Position of VREFEN field.
	RCC_C1_APB4ENR_VREFEN_Pos = 0xf
	// Bit mask of VREFEN field.
	RCC_C1_APB4ENR_VREFEN_Msk = 0x8000
	// Bit VREFEN.
	RCC_C1_APB4ENR_VREFEN = 0x8000
	// The selected clock is disabled
	RCC_C1_APB4ENR_VREFEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_VREFEN_Enabled = 0x1
	// Position of RTCAPBEN field.
	RCC_C1_APB4ENR_RTCAPBEN_Pos = 0x10
	// Bit mask of RTCAPBEN field.
	RCC_C1_APB4ENR_RTCAPBEN_Msk = 0x10000
	// Bit RTCAPBEN.
	RCC_C1_APB4ENR_RTCAPBEN = 0x10000
	// The selected clock is disabled
	RCC_C1_APB4ENR_RTCAPBEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_RTCAPBEN_Enabled = 0x1
	// Position of SAI4EN field.
	RCC_C1_APB4ENR_SAI4EN_Pos = 0x15
	// Bit mask of SAI4EN field.
	RCC_C1_APB4ENR_SAI4EN_Msk = 0x200000
	// Bit SAI4EN.
	RCC_C1_APB4ENR_SAI4EN = 0x200000
	// The selected clock is disabled
	RCC_C1_APB4ENR_SAI4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_C1_APB4ENR_SAI4EN_Enabled = 0x1

	// C1_AHB3LPENR: RCC AHB3 Sleep Clock Register
	// Position of MDMALPEN field.
	RCC_C1_AHB3LPENR_MDMALPEN_Pos = 0x0
	// Bit mask of MDMALPEN field.
	RCC_C1_AHB3LPENR_MDMALPEN_Msk = 0x1
	// Bit MDMALPEN.
	RCC_C1_AHB3LPENR_MDMALPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_MDMALPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_MDMALPEN_Enabled = 0x1
	// Position of DMA2DLPEN field.
	RCC_C1_AHB3LPENR_DMA2DLPEN_Pos = 0x4
	// Bit mask of DMA2DLPEN field.
	RCC_C1_AHB3LPENR_DMA2DLPEN_Msk = 0x10
	// Bit DMA2DLPEN.
	RCC_C1_AHB3LPENR_DMA2DLPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_DMA2DLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_DMA2DLPEN_Enabled = 0x1
	// Position of JPGDECLPEN field.
	RCC_C1_AHB3LPENR_JPGDECLPEN_Pos = 0x5
	// Bit mask of JPGDECLPEN field.
	RCC_C1_AHB3LPENR_JPGDECLPEN_Msk = 0x20
	// Bit JPGDECLPEN.
	RCC_C1_AHB3LPENR_JPGDECLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_JPGDECLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_JPGDECLPEN_Enabled = 0x1
	// Position of FLASHPREN field.
	RCC_C1_AHB3LPENR_FLASHPREN_Pos = 0x8
	// Bit mask of FLASHPREN field.
	RCC_C1_AHB3LPENR_FLASHPREN_Msk = 0x100
	// Bit FLASHPREN.
	RCC_C1_AHB3LPENR_FLASHPREN = 0x100
	// Position of FMCLPEN field.
	RCC_C1_AHB3LPENR_FMCLPEN_Pos = 0xc
	// Bit mask of FMCLPEN field.
	RCC_C1_AHB3LPENR_FMCLPEN_Msk = 0x1000
	// Bit FMCLPEN.
	RCC_C1_AHB3LPENR_FMCLPEN = 0x1000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_FMCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_FMCLPEN_Enabled = 0x1
	// Position of QSPILPEN field.
	RCC_C1_AHB3LPENR_QSPILPEN_Pos = 0xe
	// Bit mask of QSPILPEN field.
	RCC_C1_AHB3LPENR_QSPILPEN_Msk = 0x4000
	// Bit QSPILPEN.
	RCC_C1_AHB3LPENR_QSPILPEN = 0x4000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_QSPILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_QSPILPEN_Enabled = 0x1
	// Position of SDMMC1LPEN field.
	RCC_C1_AHB3LPENR_SDMMC1LPEN_Pos = 0x10
	// Bit mask of SDMMC1LPEN field.
	RCC_C1_AHB3LPENR_SDMMC1LPEN_Msk = 0x10000
	// Bit SDMMC1LPEN.
	RCC_C1_AHB3LPENR_SDMMC1LPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_SDMMC1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_SDMMC1LPEN_Enabled = 0x1
	// Position of D1DTCM1LPEN field.
	RCC_C1_AHB3LPENR_D1DTCM1LPEN_Pos = 0x1c
	// Bit mask of D1DTCM1LPEN field.
	RCC_C1_AHB3LPENR_D1DTCM1LPEN_Msk = 0x10000000
	// Bit D1DTCM1LPEN.
	RCC_C1_AHB3LPENR_D1DTCM1LPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_D1DTCM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_D1DTCM1LPEN_Enabled = 0x1
	// Position of DTCM2LPEN field.
	RCC_C1_AHB3LPENR_DTCM2LPEN_Pos = 0x1d
	// Bit mask of DTCM2LPEN field.
	RCC_C1_AHB3LPENR_DTCM2LPEN_Msk = 0x20000000
	// Bit DTCM2LPEN.
	RCC_C1_AHB3LPENR_DTCM2LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_DTCM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_DTCM2LPEN_Enabled = 0x1
	// Position of ITCMLPEN field.
	RCC_C1_AHB3LPENR_ITCMLPEN_Pos = 0x1e
	// Bit mask of ITCMLPEN field.
	RCC_C1_AHB3LPENR_ITCMLPEN_Msk = 0x40000000
	// Bit ITCMLPEN.
	RCC_C1_AHB3LPENR_ITCMLPEN = 0x40000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_ITCMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_ITCMLPEN_Enabled = 0x1
	// Position of AXISRAMLPEN field.
	RCC_C1_AHB3LPENR_AXISRAMLPEN_Pos = 0x1f
	// Bit mask of AXISRAMLPEN field.
	RCC_C1_AHB3LPENR_AXISRAMLPEN_Msk = 0x80000000
	// Bit AXISRAMLPEN.
	RCC_C1_AHB3LPENR_AXISRAMLPEN = 0x80000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB3LPENR_AXISRAMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB3LPENR_AXISRAMLPEN_Enabled = 0x1

	// C1_AHB1LPENR: RCC AHB1 Sleep Clock Register
	// Position of DMA1LPEN field.
	RCC_C1_AHB1LPENR_DMA1LPEN_Pos = 0x0
	// Bit mask of DMA1LPEN field.
	RCC_C1_AHB1LPENR_DMA1LPEN_Msk = 0x1
	// Bit DMA1LPEN.
	RCC_C1_AHB1LPENR_DMA1LPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_DMA1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_DMA1LPEN_Enabled = 0x1
	// Position of DMA2LPEN field.
	RCC_C1_AHB1LPENR_DMA2LPEN_Pos = 0x1
	// Bit mask of DMA2LPEN field.
	RCC_C1_AHB1LPENR_DMA2LPEN_Msk = 0x2
	// Bit DMA2LPEN.
	RCC_C1_AHB1LPENR_DMA2LPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_DMA2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_DMA2LPEN_Enabled = 0x1
	// Position of ADC12LPEN field.
	RCC_C1_AHB1LPENR_ADC12LPEN_Pos = 0x5
	// Bit mask of ADC12LPEN field.
	RCC_C1_AHB1LPENR_ADC12LPEN_Msk = 0x20
	// Bit ADC12LPEN.
	RCC_C1_AHB1LPENR_ADC12LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_ADC12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_ADC12LPEN_Enabled = 0x1
	// Position of ETH1MACLPEN field.
	RCC_C1_AHB1LPENR_ETH1MACLPEN_Pos = 0xf
	// Bit mask of ETH1MACLPEN field.
	RCC_C1_AHB1LPENR_ETH1MACLPEN_Msk = 0x8000
	// Bit ETH1MACLPEN.
	RCC_C1_AHB1LPENR_ETH1MACLPEN = 0x8000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_ETH1MACLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_ETH1MACLPEN_Enabled = 0x1
	// Position of ETH1TXLPEN field.
	RCC_C1_AHB1LPENR_ETH1TXLPEN_Pos = 0x10
	// Bit mask of ETH1TXLPEN field.
	RCC_C1_AHB1LPENR_ETH1TXLPEN_Msk = 0x10000
	// Bit ETH1TXLPEN.
	RCC_C1_AHB1LPENR_ETH1TXLPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_ETH1TXLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_ETH1TXLPEN_Enabled = 0x1
	// Position of ETH1RXLPEN field.
	RCC_C1_AHB1LPENR_ETH1RXLPEN_Pos = 0x11
	// Bit mask of ETH1RXLPEN field.
	RCC_C1_AHB1LPENR_ETH1RXLPEN_Msk = 0x20000
	// Bit ETH1RXLPEN.
	RCC_C1_AHB1LPENR_ETH1RXLPEN = 0x20000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_ETH1RXLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_ETH1RXLPEN_Enabled = 0x1
	// Position of USB1OTGLPEN field.
	RCC_C1_AHB1LPENR_USB1OTGLPEN_Pos = 0x19
	// Bit mask of USB1OTGLPEN field.
	RCC_C1_AHB1LPENR_USB1OTGLPEN_Msk = 0x2000000
	// Bit USB1OTGLPEN.
	RCC_C1_AHB1LPENR_USB1OTGLPEN = 0x2000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_USB1OTGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_USB1OTGLPEN_Enabled = 0x1
	// Position of USB1ULPILPEN field.
	RCC_C1_AHB1LPENR_USB1ULPILPEN_Pos = 0x1a
	// Bit mask of USB1ULPILPEN field.
	RCC_C1_AHB1LPENR_USB1ULPILPEN_Msk = 0x4000000
	// Bit USB1ULPILPEN.
	RCC_C1_AHB1LPENR_USB1ULPILPEN = 0x4000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_USB1ULPILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_USB1ULPILPEN_Enabled = 0x1
	// Position of USB2OTGLPEN field.
	RCC_C1_AHB1LPENR_USB2OTGLPEN_Pos = 0x1b
	// Bit mask of USB2OTGLPEN field.
	RCC_C1_AHB1LPENR_USB2OTGLPEN_Msk = 0x8000000
	// Bit USB2OTGLPEN.
	RCC_C1_AHB1LPENR_USB2OTGLPEN = 0x8000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_USB2OTGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_USB2OTGLPEN_Enabled = 0x1
	// Position of USB2ULPILPEN field.
	RCC_C1_AHB1LPENR_USB2ULPILPEN_Pos = 0x1c
	// Bit mask of USB2ULPILPEN field.
	RCC_C1_AHB1LPENR_USB2ULPILPEN_Msk = 0x10000000
	// Bit USB2ULPILPEN.
	RCC_C1_AHB1LPENR_USB2ULPILPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB1LPENR_USB2ULPILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB1LPENR_USB2ULPILPEN_Enabled = 0x1

	// C1_AHB2LPENR: RCC AHB2 Sleep Clock Register
	// Position of DCMILPEN field.
	RCC_C1_AHB2LPENR_DCMILPEN_Pos = 0x0
	// Bit mask of DCMILPEN field.
	RCC_C1_AHB2LPENR_DCMILPEN_Msk = 0x1
	// Bit DCMILPEN.
	RCC_C1_AHB2LPENR_DCMILPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_DCMILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_DCMILPEN_Enabled = 0x1
	// Position of CRYPTLPEN field.
	RCC_C1_AHB2LPENR_CRYPTLPEN_Pos = 0x4
	// Bit mask of CRYPTLPEN field.
	RCC_C1_AHB2LPENR_CRYPTLPEN_Msk = 0x10
	// Bit CRYPTLPEN.
	RCC_C1_AHB2LPENR_CRYPTLPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_CRYPTLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_CRYPTLPEN_Enabled = 0x1
	// Position of HASHLPEN field.
	RCC_C1_AHB2LPENR_HASHLPEN_Pos = 0x5
	// Bit mask of HASHLPEN field.
	RCC_C1_AHB2LPENR_HASHLPEN_Msk = 0x20
	// Bit HASHLPEN.
	RCC_C1_AHB2LPENR_HASHLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_HASHLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_HASHLPEN_Enabled = 0x1
	// Position of SDMMC2LPEN field.
	RCC_C1_AHB2LPENR_SDMMC2LPEN_Pos = 0x9
	// Bit mask of SDMMC2LPEN field.
	RCC_C1_AHB2LPENR_SDMMC2LPEN_Msk = 0x200
	// Bit SDMMC2LPEN.
	RCC_C1_AHB2LPENR_SDMMC2LPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_SDMMC2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_SDMMC2LPEN_Enabled = 0x1
	// Position of RNGLPEN field.
	RCC_C1_AHB2LPENR_RNGLPEN_Pos = 0x6
	// Bit mask of RNGLPEN field.
	RCC_C1_AHB2LPENR_RNGLPEN_Msk = 0x40
	// Bit RNGLPEN.
	RCC_C1_AHB2LPENR_RNGLPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_RNGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_RNGLPEN_Enabled = 0x1
	// Position of SRAM1LPEN field.
	RCC_C1_AHB2LPENR_SRAM1LPEN_Pos = 0x1d
	// Bit mask of SRAM1LPEN field.
	RCC_C1_AHB2LPENR_SRAM1LPEN_Msk = 0x20000000
	// Bit SRAM1LPEN.
	RCC_C1_AHB2LPENR_SRAM1LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_SRAM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_SRAM1LPEN_Enabled = 0x1
	// Position of SRAM2LPEN field.
	RCC_C1_AHB2LPENR_SRAM2LPEN_Pos = 0x1e
	// Bit mask of SRAM2LPEN field.
	RCC_C1_AHB2LPENR_SRAM2LPEN_Msk = 0x40000000
	// Bit SRAM2LPEN.
	RCC_C1_AHB2LPENR_SRAM2LPEN = 0x40000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_SRAM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_SRAM2LPEN_Enabled = 0x1
	// Position of SRAM3LPEN field.
	RCC_C1_AHB2LPENR_SRAM3LPEN_Pos = 0x1f
	// Bit mask of SRAM3LPEN field.
	RCC_C1_AHB2LPENR_SRAM3LPEN_Msk = 0x80000000
	// Bit SRAM3LPEN.
	RCC_C1_AHB2LPENR_SRAM3LPEN = 0x80000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB2LPENR_SRAM3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB2LPENR_SRAM3LPEN_Enabled = 0x1

	// C1_AHB4LPENR: RCC AHB4 Sleep Clock Register
	// Position of GPIOALPEN field.
	RCC_C1_AHB4LPENR_GPIOALPEN_Pos = 0x0
	// Bit mask of GPIOALPEN field.
	RCC_C1_AHB4LPENR_GPIOALPEN_Msk = 0x1
	// Bit GPIOALPEN.
	RCC_C1_AHB4LPENR_GPIOALPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOALPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOALPEN_Enabled = 0x1
	// Position of GPIOBLPEN field.
	RCC_C1_AHB4LPENR_GPIOBLPEN_Pos = 0x1
	// Bit mask of GPIOBLPEN field.
	RCC_C1_AHB4LPENR_GPIOBLPEN_Msk = 0x2
	// Bit GPIOBLPEN.
	RCC_C1_AHB4LPENR_GPIOBLPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOBLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOBLPEN_Enabled = 0x1
	// Position of GPIOCLPEN field.
	RCC_C1_AHB4LPENR_GPIOCLPEN_Pos = 0x2
	// Bit mask of GPIOCLPEN field.
	RCC_C1_AHB4LPENR_GPIOCLPEN_Msk = 0x4
	// Bit GPIOCLPEN.
	RCC_C1_AHB4LPENR_GPIOCLPEN = 0x4
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOCLPEN_Enabled = 0x1
	// Position of GPIODLPEN field.
	RCC_C1_AHB4LPENR_GPIODLPEN_Pos = 0x3
	// Bit mask of GPIODLPEN field.
	RCC_C1_AHB4LPENR_GPIODLPEN_Msk = 0x8
	// Bit GPIODLPEN.
	RCC_C1_AHB4LPENR_GPIODLPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIODLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIODLPEN_Enabled = 0x1
	// Position of GPIOELPEN field.
	RCC_C1_AHB4LPENR_GPIOELPEN_Pos = 0x4
	// Bit mask of GPIOELPEN field.
	RCC_C1_AHB4LPENR_GPIOELPEN_Msk = 0x10
	// Bit GPIOELPEN.
	RCC_C1_AHB4LPENR_GPIOELPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOELPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOELPEN_Enabled = 0x1
	// Position of GPIOFLPEN field.
	RCC_C1_AHB4LPENR_GPIOFLPEN_Pos = 0x5
	// Bit mask of GPIOFLPEN field.
	RCC_C1_AHB4LPENR_GPIOFLPEN_Msk = 0x20
	// Bit GPIOFLPEN.
	RCC_C1_AHB4LPENR_GPIOFLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOFLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOFLPEN_Enabled = 0x1
	// Position of GPIOGLPEN field.
	RCC_C1_AHB4LPENR_GPIOGLPEN_Pos = 0x6
	// Bit mask of GPIOGLPEN field.
	RCC_C1_AHB4LPENR_GPIOGLPEN_Msk = 0x40
	// Bit GPIOGLPEN.
	RCC_C1_AHB4LPENR_GPIOGLPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOGLPEN_Enabled = 0x1
	// Position of GPIOHLPEN field.
	RCC_C1_AHB4LPENR_GPIOHLPEN_Pos = 0x7
	// Bit mask of GPIOHLPEN field.
	RCC_C1_AHB4LPENR_GPIOHLPEN_Msk = 0x80
	// Bit GPIOHLPEN.
	RCC_C1_AHB4LPENR_GPIOHLPEN = 0x80
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOHLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOHLPEN_Enabled = 0x1
	// Position of GPIOILPEN field.
	RCC_C1_AHB4LPENR_GPIOILPEN_Pos = 0x8
	// Bit mask of GPIOILPEN field.
	RCC_C1_AHB4LPENR_GPIOILPEN_Msk = 0x100
	// Bit GPIOILPEN.
	RCC_C1_AHB4LPENR_GPIOILPEN = 0x100
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOILPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOILPEN_Enabled = 0x1
	// Position of GPIOJLPEN field.
	RCC_C1_AHB4LPENR_GPIOJLPEN_Pos = 0x9
	// Bit mask of GPIOJLPEN field.
	RCC_C1_AHB4LPENR_GPIOJLPEN_Msk = 0x200
	// Bit GPIOJLPEN.
	RCC_C1_AHB4LPENR_GPIOJLPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOJLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOJLPEN_Enabled = 0x1
	// Position of GPIOKLPEN field.
	RCC_C1_AHB4LPENR_GPIOKLPEN_Pos = 0xa
	// Bit mask of GPIOKLPEN field.
	RCC_C1_AHB4LPENR_GPIOKLPEN_Msk = 0x400
	// Bit GPIOKLPEN.
	RCC_C1_AHB4LPENR_GPIOKLPEN = 0x400
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOKLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_GPIOKLPEN_Enabled = 0x1
	// Position of CRCLPEN field.
	RCC_C1_AHB4LPENR_CRCLPEN_Pos = 0x13
	// Bit mask of CRCLPEN field.
	RCC_C1_AHB4LPENR_CRCLPEN_Msk = 0x80000
	// Bit CRCLPEN.
	RCC_C1_AHB4LPENR_CRCLPEN = 0x80000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_CRCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_CRCLPEN_Enabled = 0x1
	// Position of BDMALPEN field.
	RCC_C1_AHB4LPENR_BDMALPEN_Pos = 0x15
	// Bit mask of BDMALPEN field.
	RCC_C1_AHB4LPENR_BDMALPEN_Msk = 0x200000
	// Bit BDMALPEN.
	RCC_C1_AHB4LPENR_BDMALPEN = 0x200000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_BDMALPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_BDMALPEN_Enabled = 0x1
	// Position of ADC3LPEN field.
	RCC_C1_AHB4LPENR_ADC3LPEN_Pos = 0x18
	// Bit mask of ADC3LPEN field.
	RCC_C1_AHB4LPENR_ADC3LPEN_Msk = 0x1000000
	// Bit ADC3LPEN.
	RCC_C1_AHB4LPENR_ADC3LPEN = 0x1000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_ADC3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_ADC3LPEN_Enabled = 0x1
	// Position of BKPRAMLPEN field.
	RCC_C1_AHB4LPENR_BKPRAMLPEN_Pos = 0x1c
	// Bit mask of BKPRAMLPEN field.
	RCC_C1_AHB4LPENR_BKPRAMLPEN_Msk = 0x10000000
	// Bit BKPRAMLPEN.
	RCC_C1_AHB4LPENR_BKPRAMLPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_BKPRAMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_BKPRAMLPEN_Enabled = 0x1
	// Position of SRAM4LPEN field.
	RCC_C1_AHB4LPENR_SRAM4LPEN_Pos = 0x1d
	// Bit mask of SRAM4LPEN field.
	RCC_C1_AHB4LPENR_SRAM4LPEN_Msk = 0x20000000
	// Bit SRAM4LPEN.
	RCC_C1_AHB4LPENR_SRAM4LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_C1_AHB4LPENR_SRAM4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_AHB4LPENR_SRAM4LPEN_Enabled = 0x1

	// C1_APB3LPENR: RCC APB3 Sleep Clock Register
	// Position of LTDCLPEN field.
	RCC_C1_APB3LPENR_LTDCLPEN_Pos = 0x3
	// Bit mask of LTDCLPEN field.
	RCC_C1_APB3LPENR_LTDCLPEN_Msk = 0x8
	// Bit LTDCLPEN.
	RCC_C1_APB3LPENR_LTDCLPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_C1_APB3LPENR_LTDCLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB3LPENR_LTDCLPEN_Enabled = 0x1
	// Position of WWDG1LPEN field.
	RCC_C1_APB3LPENR_WWDG1LPEN_Pos = 0x6
	// Bit mask of WWDG1LPEN field.
	RCC_C1_APB3LPENR_WWDG1LPEN_Msk = 0x40
	// Bit WWDG1LPEN.
	RCC_C1_APB3LPENR_WWDG1LPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_C1_APB3LPENR_WWDG1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB3LPENR_WWDG1LPEN_Enabled = 0x1

	// C1_APB1LLPENR: RCC APB1 Low Sleep Clock Register
	// Position of TIM2LPEN field.
	RCC_C1_APB1LLPENR_TIM2LPEN_Pos = 0x0
	// Bit mask of TIM2LPEN field.
	RCC_C1_APB1LLPENR_TIM2LPEN_Msk = 0x1
	// Bit TIM2LPEN.
	RCC_C1_APB1LLPENR_TIM2LPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM2LPEN_Enabled = 0x1
	// Position of TIM3LPEN field.
	RCC_C1_APB1LLPENR_TIM3LPEN_Pos = 0x1
	// Bit mask of TIM3LPEN field.
	RCC_C1_APB1LLPENR_TIM3LPEN_Msk = 0x2
	// Bit TIM3LPEN.
	RCC_C1_APB1LLPENR_TIM3LPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM3LPEN_Enabled = 0x1
	// Position of TIM4LPEN field.
	RCC_C1_APB1LLPENR_TIM4LPEN_Pos = 0x2
	// Bit mask of TIM4LPEN field.
	RCC_C1_APB1LLPENR_TIM4LPEN_Msk = 0x4
	// Bit TIM4LPEN.
	RCC_C1_APB1LLPENR_TIM4LPEN = 0x4
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM4LPEN_Enabled = 0x1
	// Position of TIM5LPEN field.
	RCC_C1_APB1LLPENR_TIM5LPEN_Pos = 0x3
	// Bit mask of TIM5LPEN field.
	RCC_C1_APB1LLPENR_TIM5LPEN_Msk = 0x8
	// Bit TIM5LPEN.
	RCC_C1_APB1LLPENR_TIM5LPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM5LPEN_Enabled = 0x1
	// Position of TIM6LPEN field.
	RCC_C1_APB1LLPENR_TIM6LPEN_Pos = 0x4
	// Bit mask of TIM6LPEN field.
	RCC_C1_APB1LLPENR_TIM6LPEN_Msk = 0x10
	// Bit TIM6LPEN.
	RCC_C1_APB1LLPENR_TIM6LPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM6LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM6LPEN_Enabled = 0x1
	// Position of TIM7LPEN field.
	RCC_C1_APB1LLPENR_TIM7LPEN_Pos = 0x5
	// Bit mask of TIM7LPEN field.
	RCC_C1_APB1LLPENR_TIM7LPEN_Msk = 0x20
	// Bit TIM7LPEN.
	RCC_C1_APB1LLPENR_TIM7LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM7LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM7LPEN_Enabled = 0x1
	// Position of TIM12LPEN field.
	RCC_C1_APB1LLPENR_TIM12LPEN_Pos = 0x6
	// Bit mask of TIM12LPEN field.
	RCC_C1_APB1LLPENR_TIM12LPEN_Msk = 0x40
	// Bit TIM12LPEN.
	RCC_C1_APB1LLPENR_TIM12LPEN = 0x40
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM12LPEN_Enabled = 0x1
	// Position of TIM13LPEN field.
	RCC_C1_APB1LLPENR_TIM13LPEN_Pos = 0x7
	// Bit mask of TIM13LPEN field.
	RCC_C1_APB1LLPENR_TIM13LPEN_Msk = 0x80
	// Bit TIM13LPEN.
	RCC_C1_APB1LLPENR_TIM13LPEN = 0x80
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM13LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM13LPEN_Enabled = 0x1
	// Position of TIM14LPEN field.
	RCC_C1_APB1LLPENR_TIM14LPEN_Pos = 0x8
	// Bit mask of TIM14LPEN field.
	RCC_C1_APB1LLPENR_TIM14LPEN_Msk = 0x100
	// Bit TIM14LPEN.
	RCC_C1_APB1LLPENR_TIM14LPEN = 0x100
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_TIM14LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_TIM14LPEN_Enabled = 0x1
	// Position of LPTIM1LPEN field.
	RCC_C1_APB1LLPENR_LPTIM1LPEN_Pos = 0x9
	// Bit mask of LPTIM1LPEN field.
	RCC_C1_APB1LLPENR_LPTIM1LPEN_Msk = 0x200
	// Bit LPTIM1LPEN.
	RCC_C1_APB1LLPENR_LPTIM1LPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_LPTIM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_LPTIM1LPEN_Enabled = 0x1
	// Position of SPI2LPEN field.
	RCC_C1_APB1LLPENR_SPI2LPEN_Pos = 0xe
	// Bit mask of SPI2LPEN field.
	RCC_C1_APB1LLPENR_SPI2LPEN_Msk = 0x4000
	// Bit SPI2LPEN.
	RCC_C1_APB1LLPENR_SPI2LPEN = 0x4000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_SPI2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_SPI2LPEN_Enabled = 0x1
	// Position of SPI3LPEN field.
	RCC_C1_APB1LLPENR_SPI3LPEN_Pos = 0xf
	// Bit mask of SPI3LPEN field.
	RCC_C1_APB1LLPENR_SPI3LPEN_Msk = 0x8000
	// Bit SPI3LPEN.
	RCC_C1_APB1LLPENR_SPI3LPEN = 0x8000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_SPI3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_SPI3LPEN_Enabled = 0x1
	// Position of SPDIFRXLPEN field.
	RCC_C1_APB1LLPENR_SPDIFRXLPEN_Pos = 0x10
	// Bit mask of SPDIFRXLPEN field.
	RCC_C1_APB1LLPENR_SPDIFRXLPEN_Msk = 0x10000
	// Bit SPDIFRXLPEN.
	RCC_C1_APB1LLPENR_SPDIFRXLPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_SPDIFRXLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_SPDIFRXLPEN_Enabled = 0x1
	// Position of USART2LPEN field.
	RCC_C1_APB1LLPENR_USART2LPEN_Pos = 0x11
	// Bit mask of USART2LPEN field.
	RCC_C1_APB1LLPENR_USART2LPEN_Msk = 0x20000
	// Bit USART2LPEN.
	RCC_C1_APB1LLPENR_USART2LPEN = 0x20000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_USART2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_USART2LPEN_Enabled = 0x1
	// Position of USART3LPEN field.
	RCC_C1_APB1LLPENR_USART3LPEN_Pos = 0x12
	// Bit mask of USART3LPEN field.
	RCC_C1_APB1LLPENR_USART3LPEN_Msk = 0x40000
	// Bit USART3LPEN.
	RCC_C1_APB1LLPENR_USART3LPEN = 0x40000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_USART3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_USART3LPEN_Enabled = 0x1
	// Position of UART4LPEN field.
	RCC_C1_APB1LLPENR_UART4LPEN_Pos = 0x13
	// Bit mask of UART4LPEN field.
	RCC_C1_APB1LLPENR_UART4LPEN_Msk = 0x80000
	// Bit UART4LPEN.
	RCC_C1_APB1LLPENR_UART4LPEN = 0x80000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_UART4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_UART4LPEN_Enabled = 0x1
	// Position of UART5LPEN field.
	RCC_C1_APB1LLPENR_UART5LPEN_Pos = 0x14
	// Bit mask of UART5LPEN field.
	RCC_C1_APB1LLPENR_UART5LPEN_Msk = 0x100000
	// Bit UART5LPEN.
	RCC_C1_APB1LLPENR_UART5LPEN = 0x100000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_UART5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_UART5LPEN_Enabled = 0x1
	// Position of I2C1LPEN field.
	RCC_C1_APB1LLPENR_I2C1LPEN_Pos = 0x15
	// Bit mask of I2C1LPEN field.
	RCC_C1_APB1LLPENR_I2C1LPEN_Msk = 0x200000
	// Bit I2C1LPEN.
	RCC_C1_APB1LLPENR_I2C1LPEN = 0x200000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_I2C1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_I2C1LPEN_Enabled = 0x1
	// Position of I2C2LPEN field.
	RCC_C1_APB1LLPENR_I2C2LPEN_Pos = 0x16
	// Bit mask of I2C2LPEN field.
	RCC_C1_APB1LLPENR_I2C2LPEN_Msk = 0x400000
	// Bit I2C2LPEN.
	RCC_C1_APB1LLPENR_I2C2LPEN = 0x400000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_I2C2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_I2C2LPEN_Enabled = 0x1
	// Position of I2C3LPEN field.
	RCC_C1_APB1LLPENR_I2C3LPEN_Pos = 0x17
	// Bit mask of I2C3LPEN field.
	RCC_C1_APB1LLPENR_I2C3LPEN_Msk = 0x800000
	// Bit I2C3LPEN.
	RCC_C1_APB1LLPENR_I2C3LPEN = 0x800000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_I2C3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_I2C3LPEN_Enabled = 0x1
	// Position of CECLPEN field.
	RCC_C1_APB1LLPENR_CECLPEN_Pos = 0x1b
	// Bit mask of CECLPEN field.
	RCC_C1_APB1LLPENR_CECLPEN_Msk = 0x8000000
	// Bit CECLPEN.
	RCC_C1_APB1LLPENR_CECLPEN = 0x8000000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_CECLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_CECLPEN_Enabled = 0x1
	// Position of DAC12LPEN field.
	RCC_C1_APB1LLPENR_DAC12LPEN_Pos = 0x1d
	// Bit mask of DAC12LPEN field.
	RCC_C1_APB1LLPENR_DAC12LPEN_Msk = 0x20000000
	// Bit DAC12LPEN.
	RCC_C1_APB1LLPENR_DAC12LPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_DAC12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_DAC12LPEN_Enabled = 0x1
	// Position of UART7LPEN field.
	RCC_C1_APB1LLPENR_UART7LPEN_Pos = 0x1e
	// Bit mask of UART7LPEN field.
	RCC_C1_APB1LLPENR_UART7LPEN_Msk = 0x40000000
	// Bit UART7LPEN.
	RCC_C1_APB1LLPENR_UART7LPEN = 0x40000000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_UART7LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_UART7LPEN_Enabled = 0x1
	// Position of UART8LPEN field.
	RCC_C1_APB1LLPENR_UART8LPEN_Pos = 0x1f
	// Bit mask of UART8LPEN field.
	RCC_C1_APB1LLPENR_UART8LPEN_Msk = 0x80000000
	// Bit UART8LPEN.
	RCC_C1_APB1LLPENR_UART8LPEN = 0x80000000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1LLPENR_UART8LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1LLPENR_UART8LPEN_Enabled = 0x1

	// C1_APB1HLPENR: RCC APB1 High Sleep Clock Register
	// Position of CRSLPEN field.
	RCC_C1_APB1HLPENR_CRSLPEN_Pos = 0x1
	// Bit mask of CRSLPEN field.
	RCC_C1_APB1HLPENR_CRSLPEN_Msk = 0x2
	// Bit CRSLPEN.
	RCC_C1_APB1HLPENR_CRSLPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1HLPENR_CRSLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1HLPENR_CRSLPEN_Enabled = 0x1
	// Position of SWPLPEN field.
	RCC_C1_APB1HLPENR_SWPLPEN_Pos = 0x2
	// Bit mask of SWPLPEN field.
	RCC_C1_APB1HLPENR_SWPLPEN_Msk = 0x4
	// Bit SWPLPEN.
	RCC_C1_APB1HLPENR_SWPLPEN = 0x4
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1HLPENR_SWPLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1HLPENR_SWPLPEN_Enabled = 0x1
	// Position of OPAMPLPEN field.
	RCC_C1_APB1HLPENR_OPAMPLPEN_Pos = 0x4
	// Bit mask of OPAMPLPEN field.
	RCC_C1_APB1HLPENR_OPAMPLPEN_Msk = 0x10
	// Bit OPAMPLPEN.
	RCC_C1_APB1HLPENR_OPAMPLPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1HLPENR_OPAMPLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1HLPENR_OPAMPLPEN_Enabled = 0x1
	// Position of MDIOSLPEN field.
	RCC_C1_APB1HLPENR_MDIOSLPEN_Pos = 0x5
	// Bit mask of MDIOSLPEN field.
	RCC_C1_APB1HLPENR_MDIOSLPEN_Msk = 0x20
	// Bit MDIOSLPEN.
	RCC_C1_APB1HLPENR_MDIOSLPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1HLPENR_MDIOSLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1HLPENR_MDIOSLPEN_Enabled = 0x1
	// Position of FDCANLPEN field.
	RCC_C1_APB1HLPENR_FDCANLPEN_Pos = 0x8
	// Bit mask of FDCANLPEN field.
	RCC_C1_APB1HLPENR_FDCANLPEN_Msk = 0x100
	// Bit FDCANLPEN.
	RCC_C1_APB1HLPENR_FDCANLPEN = 0x100
	// The selected clock is disabled during csleep mode
	RCC_C1_APB1HLPENR_FDCANLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB1HLPENR_FDCANLPEN_Enabled = 0x1

	// C1_APB2LPENR: RCC APB2 Sleep Clock Register
	// Position of TIM1LPEN field.
	RCC_C1_APB2LPENR_TIM1LPEN_Pos = 0x0
	// Bit mask of TIM1LPEN field.
	RCC_C1_APB2LPENR_TIM1LPEN_Msk = 0x1
	// Bit TIM1LPEN.
	RCC_C1_APB2LPENR_TIM1LPEN = 0x1
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_TIM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_TIM1LPEN_Enabled = 0x1
	// Position of TIM8LPEN field.
	RCC_C1_APB2LPENR_TIM8LPEN_Pos = 0x1
	// Bit mask of TIM8LPEN field.
	RCC_C1_APB2LPENR_TIM8LPEN_Msk = 0x2
	// Bit TIM8LPEN.
	RCC_C1_APB2LPENR_TIM8LPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_TIM8LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_TIM8LPEN_Enabled = 0x1
	// Position of USART1LPEN field.
	RCC_C1_APB2LPENR_USART1LPEN_Pos = 0x4
	// Bit mask of USART1LPEN field.
	RCC_C1_APB2LPENR_USART1LPEN_Msk = 0x10
	// Bit USART1LPEN.
	RCC_C1_APB2LPENR_USART1LPEN = 0x10
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_USART1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_USART1LPEN_Enabled = 0x1
	// Position of USART6LPEN field.
	RCC_C1_APB2LPENR_USART6LPEN_Pos = 0x5
	// Bit mask of USART6LPEN field.
	RCC_C1_APB2LPENR_USART6LPEN_Msk = 0x20
	// Bit USART6LPEN.
	RCC_C1_APB2LPENR_USART6LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_USART6LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_USART6LPEN_Enabled = 0x1
	// Position of SPI1LPEN field.
	RCC_C1_APB2LPENR_SPI1LPEN_Pos = 0xc
	// Bit mask of SPI1LPEN field.
	RCC_C1_APB2LPENR_SPI1LPEN_Msk = 0x1000
	// Bit SPI1LPEN.
	RCC_C1_APB2LPENR_SPI1LPEN = 0x1000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_SPI1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_SPI1LPEN_Enabled = 0x1
	// Position of SPI4LPEN field.
	RCC_C1_APB2LPENR_SPI4LPEN_Pos = 0xd
	// Bit mask of SPI4LPEN field.
	RCC_C1_APB2LPENR_SPI4LPEN_Msk = 0x2000
	// Bit SPI4LPEN.
	RCC_C1_APB2LPENR_SPI4LPEN = 0x2000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_SPI4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_SPI4LPEN_Enabled = 0x1
	// Position of TIM15LPEN field.
	RCC_C1_APB2LPENR_TIM15LPEN_Pos = 0x10
	// Bit mask of TIM15LPEN field.
	RCC_C1_APB2LPENR_TIM15LPEN_Msk = 0x10000
	// Bit TIM15LPEN.
	RCC_C1_APB2LPENR_TIM15LPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_TIM15LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_TIM15LPEN_Enabled = 0x1
	// Position of TIM16LPEN field.
	RCC_C1_APB2LPENR_TIM16LPEN_Pos = 0x11
	// Bit mask of TIM16LPEN field.
	RCC_C1_APB2LPENR_TIM16LPEN_Msk = 0x20000
	// Bit TIM16LPEN.
	RCC_C1_APB2LPENR_TIM16LPEN = 0x20000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_TIM16LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_TIM16LPEN_Enabled = 0x1
	// Position of TIM17LPEN field.
	RCC_C1_APB2LPENR_TIM17LPEN_Pos = 0x12
	// Bit mask of TIM17LPEN field.
	RCC_C1_APB2LPENR_TIM17LPEN_Msk = 0x40000
	// Bit TIM17LPEN.
	RCC_C1_APB2LPENR_TIM17LPEN = 0x40000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_TIM17LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_TIM17LPEN_Enabled = 0x1
	// Position of SPI5LPEN field.
	RCC_C1_APB2LPENR_SPI5LPEN_Pos = 0x14
	// Bit mask of SPI5LPEN field.
	RCC_C1_APB2LPENR_SPI5LPEN_Msk = 0x100000
	// Bit SPI5LPEN.
	RCC_C1_APB2LPENR_SPI5LPEN = 0x100000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_SPI5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_SPI5LPEN_Enabled = 0x1
	// Position of SAI1LPEN field.
	RCC_C1_APB2LPENR_SAI1LPEN_Pos = 0x16
	// Bit mask of SAI1LPEN field.
	RCC_C1_APB2LPENR_SAI1LPEN_Msk = 0x400000
	// Bit SAI1LPEN.
	RCC_C1_APB2LPENR_SAI1LPEN = 0x400000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_SAI1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_SAI1LPEN_Enabled = 0x1
	// Position of SAI2LPEN field.
	RCC_C1_APB2LPENR_SAI2LPEN_Pos = 0x17
	// Bit mask of SAI2LPEN field.
	RCC_C1_APB2LPENR_SAI2LPEN_Msk = 0x800000
	// Bit SAI2LPEN.
	RCC_C1_APB2LPENR_SAI2LPEN = 0x800000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_SAI2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_SAI2LPEN_Enabled = 0x1
	// Position of SAI3LPEN field.
	RCC_C1_APB2LPENR_SAI3LPEN_Pos = 0x18
	// Bit mask of SAI3LPEN field.
	RCC_C1_APB2LPENR_SAI3LPEN_Msk = 0x1000000
	// Bit SAI3LPEN.
	RCC_C1_APB2LPENR_SAI3LPEN = 0x1000000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_SAI3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_SAI3LPEN_Enabled = 0x1
	// Position of DFSDM1LPEN field.
	RCC_C1_APB2LPENR_DFSDM1LPEN_Pos = 0x1c
	// Bit mask of DFSDM1LPEN field.
	RCC_C1_APB2LPENR_DFSDM1LPEN_Msk = 0x10000000
	// Bit DFSDM1LPEN.
	RCC_C1_APB2LPENR_DFSDM1LPEN = 0x10000000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_DFSDM1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_DFSDM1LPEN_Enabled = 0x1
	// Position of HRTIMLPEN field.
	RCC_C1_APB2LPENR_HRTIMLPEN_Pos = 0x1d
	// Bit mask of HRTIMLPEN field.
	RCC_C1_APB2LPENR_HRTIMLPEN_Msk = 0x20000000
	// Bit HRTIMLPEN.
	RCC_C1_APB2LPENR_HRTIMLPEN = 0x20000000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB2LPENR_HRTIMLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB2LPENR_HRTIMLPEN_Enabled = 0x1

	// C1_APB4LPENR: RCC APB4 Sleep Clock Register
	// Position of SYSCFGLPEN field.
	RCC_C1_APB4LPENR_SYSCFGLPEN_Pos = 0x1
	// Bit mask of SYSCFGLPEN field.
	RCC_C1_APB4LPENR_SYSCFGLPEN_Msk = 0x2
	// Bit SYSCFGLPEN.
	RCC_C1_APB4LPENR_SYSCFGLPEN = 0x2
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_SYSCFGLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_SYSCFGLPEN_Enabled = 0x1
	// Position of LPUART1LPEN field.
	RCC_C1_APB4LPENR_LPUART1LPEN_Pos = 0x3
	// Bit mask of LPUART1LPEN field.
	RCC_C1_APB4LPENR_LPUART1LPEN_Msk = 0x8
	// Bit LPUART1LPEN.
	RCC_C1_APB4LPENR_LPUART1LPEN = 0x8
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_LPUART1LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_LPUART1LPEN_Enabled = 0x1
	// Position of SPI6LPEN field.
	RCC_C1_APB4LPENR_SPI6LPEN_Pos = 0x5
	// Bit mask of SPI6LPEN field.
	RCC_C1_APB4LPENR_SPI6LPEN_Msk = 0x20
	// Bit SPI6LPEN.
	RCC_C1_APB4LPENR_SPI6LPEN = 0x20
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_SPI6LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_SPI6LPEN_Enabled = 0x1
	// Position of I2C4LPEN field.
	RCC_C1_APB4LPENR_I2C4LPEN_Pos = 0x7
	// Bit mask of I2C4LPEN field.
	RCC_C1_APB4LPENR_I2C4LPEN_Msk = 0x80
	// Bit I2C4LPEN.
	RCC_C1_APB4LPENR_I2C4LPEN = 0x80
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_I2C4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_I2C4LPEN_Enabled = 0x1
	// Position of LPTIM2LPEN field.
	RCC_C1_APB4LPENR_LPTIM2LPEN_Pos = 0x9
	// Bit mask of LPTIM2LPEN field.
	RCC_C1_APB4LPENR_LPTIM2LPEN_Msk = 0x200
	// Bit LPTIM2LPEN.
	RCC_C1_APB4LPENR_LPTIM2LPEN = 0x200
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM2LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM2LPEN_Enabled = 0x1
	// Position of LPTIM3LPEN field.
	RCC_C1_APB4LPENR_LPTIM3LPEN_Pos = 0xa
	// Bit mask of LPTIM3LPEN field.
	RCC_C1_APB4LPENR_LPTIM3LPEN_Msk = 0x400
	// Bit LPTIM3LPEN.
	RCC_C1_APB4LPENR_LPTIM3LPEN = 0x400
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM3LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM3LPEN_Enabled = 0x1
	// Position of LPTIM4LPEN field.
	RCC_C1_APB4LPENR_LPTIM4LPEN_Pos = 0xb
	// Bit mask of LPTIM4LPEN field.
	RCC_C1_APB4LPENR_LPTIM4LPEN_Msk = 0x800
	// Bit LPTIM4LPEN.
	RCC_C1_APB4LPENR_LPTIM4LPEN = 0x800
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM4LPEN_Enabled = 0x1
	// Position of LPTIM5LPEN field.
	RCC_C1_APB4LPENR_LPTIM5LPEN_Pos = 0xc
	// Bit mask of LPTIM5LPEN field.
	RCC_C1_APB4LPENR_LPTIM5LPEN_Msk = 0x1000
	// Bit LPTIM5LPEN.
	RCC_C1_APB4LPENR_LPTIM5LPEN = 0x1000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM5LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_LPTIM5LPEN_Enabled = 0x1
	// Position of COMP12LPEN field.
	RCC_C1_APB4LPENR_COMP12LPEN_Pos = 0xe
	// Bit mask of COMP12LPEN field.
	RCC_C1_APB4LPENR_COMP12LPEN_Msk = 0x4000
	// Bit COMP12LPEN.
	RCC_C1_APB4LPENR_COMP12LPEN = 0x4000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_COMP12LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_COMP12LPEN_Enabled = 0x1
	// Position of VREFLPEN field.
	RCC_C1_APB4LPENR_VREFLPEN_Pos = 0xf
	// Bit mask of VREFLPEN field.
	RCC_C1_APB4LPENR_VREFLPEN_Msk = 0x8000
	// Bit VREFLPEN.
	RCC_C1_APB4LPENR_VREFLPEN = 0x8000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_VREFLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_VREFLPEN_Enabled = 0x1
	// Position of RTCAPBLPEN field.
	RCC_C1_APB4LPENR_RTCAPBLPEN_Pos = 0x10
	// Bit mask of RTCAPBLPEN field.
	RCC_C1_APB4LPENR_RTCAPBLPEN_Msk = 0x10000
	// Bit RTCAPBLPEN.
	RCC_C1_APB4LPENR_RTCAPBLPEN = 0x10000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_RTCAPBLPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_RTCAPBLPEN_Enabled = 0x1
	// Position of SAI4LPEN field.
	RCC_C1_APB4LPENR_SAI4LPEN_Pos = 0x15
	// Bit mask of SAI4LPEN field.
	RCC_C1_APB4LPENR_SAI4LPEN_Msk = 0x200000
	// Bit SAI4LPEN.
	RCC_C1_APB4LPENR_SAI4LPEN = 0x200000
	// The selected clock is disabled during csleep mode
	RCC_C1_APB4LPENR_SAI4LPEN_Disabled = 0x0
	// The selected clock is enabled during csleep mode
	RCC_C1_APB4LPENR_SAI4LPEN_Enabled = 0x1
)

// Bitfields for LPTIM1: Low power timer
const (
	// ISR: Interrupt and Status Register
	// Position of DOWN field.
	LPTIM_ISR_DOWN_Pos = 0x6
	// Bit mask of DOWN field.
	LPTIM_ISR_DOWN_Msk = 0x40
	// Bit DOWN.
	LPTIM_ISR_DOWN = 0x40
	// Counter direction change up to down
	LPTIM_ISR_DOWN_Set = 0x1
	// Position of UP field.
	LPTIM_ISR_UP_Pos = 0x5
	// Bit mask of UP field.
	LPTIM_ISR_UP_Msk = 0x20
	// Bit UP.
	LPTIM_ISR_UP = 0x20
	// Counter direction change down to up
	LPTIM_ISR_UP_Set = 0x1
	// Position of ARROK field.
	LPTIM_ISR_ARROK_Pos = 0x4
	// Bit mask of ARROK field.
	LPTIM_ISR_ARROK_Msk = 0x10
	// Bit ARROK.
	LPTIM_ISR_ARROK = 0x10
	// Autoreload register update OK
	LPTIM_ISR_ARROK_Set = 0x1
	// Position of CMPOK field.
	LPTIM_ISR_CMPOK_Pos = 0x3
	// Bit mask of CMPOK field.
	LPTIM_ISR_CMPOK_Msk = 0x8
	// Bit CMPOK.
	LPTIM_ISR_CMPOK = 0x8
	// Compare register update OK
	LPTIM_ISR_CMPOK_Set = 0x1
	// Position of EXTTRIG field.
	LPTIM_ISR_EXTTRIG_Pos = 0x2
	// Bit mask of EXTTRIG field.
	LPTIM_ISR_EXTTRIG_Msk = 0x4
	// Bit EXTTRIG.
	LPTIM_ISR_EXTTRIG = 0x4
	// External trigger edge event
	LPTIM_ISR_EXTTRIG_Set = 0x1
	// Position of ARRM field.
	LPTIM_ISR_ARRM_Pos = 0x1
	// Bit mask of ARRM field.
	LPTIM_ISR_ARRM_Msk = 0x2
	// Bit ARRM.
	LPTIM_ISR_ARRM = 0x2
	// Autoreload match
	LPTIM_ISR_ARRM_Set = 0x1
	// Position of CMPM field.
	LPTIM_ISR_CMPM_Pos = 0x0
	// Bit mask of CMPM field.
	LPTIM_ISR_CMPM_Msk = 0x1
	// Bit CMPM.
	LPTIM_ISR_CMPM = 0x1
	// Compare match
	LPTIM_ISR_CMPM_Set = 0x1

	// ICR: Interrupt Clear Register
	// Position of DOWNCF field.
	LPTIM_ICR_DOWNCF_Pos = 0x6
	// Bit mask of DOWNCF field.
	LPTIM_ICR_DOWNCF_Msk = 0x40
	// Bit DOWNCF.
	LPTIM_ICR_DOWNCF = 0x40
	// Direction change to down Clear Flag
	LPTIM_ICR_DOWNCF_Clear = 0x1
	// Position of UPCF field.
	LPTIM_ICR_UPCF_Pos = 0x5
	// Bit mask of UPCF field.
	LPTIM_ICR_UPCF_Msk = 0x20
	// Bit UPCF.
	LPTIM_ICR_UPCF = 0x20
	// Direction change to up Clear Flag
	LPTIM_ICR_UPCF_Clear = 0x1
	// Position of ARROKCF field.
	LPTIM_ICR_ARROKCF_Pos = 0x4
	// Bit mask of ARROKCF field.
	LPTIM_ICR_ARROKCF_Msk = 0x10
	// Bit ARROKCF.
	LPTIM_ICR_ARROKCF = 0x10
	// Autoreload register update OK Clear Flag
	LPTIM_ICR_ARROKCF_Clear = 0x1
	// Position of CMPOKCF field.
	LPTIM_ICR_CMPOKCF_Pos = 0x3
	// Bit mask of CMPOKCF field.
	LPTIM_ICR_CMPOKCF_Msk = 0x8
	// Bit CMPOKCF.
	LPTIM_ICR_CMPOKCF = 0x8
	// Compare register update OK Clear Flag
	LPTIM_ICR_CMPOKCF_Clear = 0x1
	// Position of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF_Pos = 0x2
	// Bit mask of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF_Msk = 0x4
	// Bit EXTTRIGCF.
	LPTIM_ICR_EXTTRIGCF = 0x4
	// External trigger valid edge Clear Flag
	LPTIM_ICR_EXTTRIGCF_Clear = 0x1
	// Position of ARRMCF field.
	LPTIM_ICR_ARRMCF_Pos = 0x1
	// Bit mask of ARRMCF field.
	LPTIM_ICR_ARRMCF_Msk = 0x2
	// Bit ARRMCF.
	LPTIM_ICR_ARRMCF = 0x2
	// Autoreload match Clear Flag
	LPTIM_ICR_ARRMCF_Clear = 0x1
	// Position of CMPMCF field.
	LPTIM_ICR_CMPMCF_Pos = 0x0
	// Bit mask of CMPMCF field.
	LPTIM_ICR_CMPMCF_Msk = 0x1
	// Bit CMPMCF.
	LPTIM_ICR_CMPMCF = 0x1
	// Compare match Clear Flag
	LPTIM_ICR_CMPMCF_Clear = 0x1

	// IER: Interrupt Enable Register
	// Position of DOWNIE field.
	LPTIM_IER_DOWNIE_Pos = 0x6
	// Bit mask of DOWNIE field.
	LPTIM_IER_DOWNIE_Msk = 0x40
	// Bit DOWNIE.
	LPTIM_IER_DOWNIE = 0x40
	// DOWN interrupt disabled
	LPTIM_IER_DOWNIE_Disabled = 0x0
	// DOWN interrupt enabled
	LPTIM_IER_DOWNIE_Enabled = 0x1
	// Position of UPIE field.
	LPTIM_IER_UPIE_Pos = 0x5
	// Bit mask of UPIE field.
	LPTIM_IER_UPIE_Msk = 0x20
	// Bit UPIE.
	LPTIM_IER_UPIE = 0x20
	// UP interrupt disabled
	LPTIM_IER_UPIE_Disabled = 0x0
	// UP interrupt enabled
	LPTIM_IER_UPIE_Enabled = 0x1
	// Position of ARROKIE field.
	LPTIM_IER_ARROKIE_Pos = 0x4
	// Bit mask of ARROKIE field.
	LPTIM_IER_ARROKIE_Msk = 0x10
	// Bit ARROKIE.
	LPTIM_IER_ARROKIE = 0x10
	// ARROK interrupt disabled
	LPTIM_IER_ARROKIE_Disabled = 0x0
	// ARROK interrupt enabled
	LPTIM_IER_ARROKIE_Enabled = 0x1
	// Position of CMPOKIE field.
	LPTIM_IER_CMPOKIE_Pos = 0x3
	// Bit mask of CMPOKIE field.
	LPTIM_IER_CMPOKIE_Msk = 0x8
	// Bit CMPOKIE.
	LPTIM_IER_CMPOKIE = 0x8
	// CMPOK interrupt disabled
	LPTIM_IER_CMPOKIE_Disabled = 0x0
	// CMPOK interrupt enabled
	LPTIM_IER_CMPOKIE_Enabled = 0x1
	// Position of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE_Pos = 0x2
	// Bit mask of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE_Msk = 0x4
	// Bit EXTTRIGIE.
	LPTIM_IER_EXTTRIGIE = 0x4
	// EXTTRIG interrupt disabled
	LPTIM_IER_EXTTRIGIE_Disabled = 0x0
	// EXTTRIG interrupt enabled
	LPTIM_IER_EXTTRIGIE_Enabled = 0x1
	// Position of ARRMIE field.
	LPTIM_IER_ARRMIE_Pos = 0x1
	// Bit mask of ARRMIE field.
	LPTIM_IER_ARRMIE_Msk = 0x2
	// Bit ARRMIE.
	LPTIM_IER_ARRMIE = 0x2
	// ARRM interrupt disabled
	LPTIM_IER_ARRMIE_Disabled = 0x0
	// ARRM interrupt enabled
	LPTIM_IER_ARRMIE_Enabled = 0x1
	// Position of CMPMIE field.
	LPTIM_IER_CMPMIE_Pos = 0x0
	// Bit mask of CMPMIE field.
	LPTIM_IER_CMPMIE_Msk = 0x1
	// Bit CMPMIE.
	LPTIM_IER_CMPMIE = 0x1
	// CMPM interrupt disabled
	LPTIM_IER_CMPMIE_Disabled = 0x0
	// CMPM interrupt enabled
	LPTIM_IER_CMPMIE_Enabled = 0x1

	// CFGR: Configuration Register
	// Position of ENC field.
	LPTIM_CFGR_ENC_Pos = 0x18
	// Bit mask of ENC field.
	LPTIM_CFGR_ENC_Msk = 0x1000000
	// Bit ENC.
	LPTIM_CFGR_ENC = 0x1000000
	// Encoder mode disabled
	LPTIM_CFGR_ENC_Disabled = 0x0
	// Encoder mode enabled
	LPTIM_CFGR_ENC_Enabled = 0x1
	// Position of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Pos = 0x17
	// Bit mask of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Msk = 0x800000
	// Bit COUNTMODE.
	LPTIM_CFGR_COUNTMODE = 0x800000
	// The counter is incremented following each internal clock pulse
	LPTIM_CFGR_COUNTMODE_Internal = 0x0
	// The counter is incremented following each valid clock pulse on the LPTIM external Input1
	LPTIM_CFGR_COUNTMODE_External = 0x1
	// Position of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Pos = 0x16
	// Bit mask of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Msk = 0x400000
	// Bit PRELOAD.
	LPTIM_CFGR_PRELOAD = 0x400000
	// Registers are updated after each APB bus write access
	LPTIM_CFGR_PRELOAD_Immediate = 0x0
	// Registers are updated at the end of the current LPTIM period
	LPTIM_CFGR_PRELOAD_EndOfPeriod = 0x1
	// Position of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Pos = 0x15
	// Bit mask of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Msk = 0x200000
	// Bit WAVPOL.
	LPTIM_CFGR_WAVPOL = 0x200000
	// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
	LPTIM_CFGR_WAVPOL_Positive = 0x0
	// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers
	LPTIM_CFGR_WAVPOL_Negative = 0x1
	// Position of WAVE field.
	LPTIM_CFGR_WAVE_Pos = 0x14
	// Bit mask of WAVE field.
	LPTIM_CFGR_WAVE_Msk = 0x100000
	// Bit WAVE.
	LPTIM_CFGR_WAVE = 0x100000
	// Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
	LPTIM_CFGR_WAVE_Inactive = 0x0
	// Activate the Set-once mode
	LPTIM_CFGR_WAVE_Active = 0x1
	// Position of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Pos = 0x13
	// Bit mask of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Msk = 0x80000
	// Bit TIMOUT.
	LPTIM_CFGR_TIMOUT = 0x80000
	// A trigger event arriving when the timer is already started will be ignored
	LPTIM_CFGR_TIMOUT_Disabled = 0x0
	// A trigger event arriving when the timer is already started will reset and restart the counter
	LPTIM_CFGR_TIMOUT_Enabled = 0x1
	// Position of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Pos = 0x11
	// Bit mask of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Msk = 0x60000
	// Software trigger (counting start is initiated by software)
	LPTIM_CFGR_TRIGEN_SW = 0x0
	// Rising edge is the active edge
	LPTIM_CFGR_TRIGEN_RisingEdge = 0x1
	// Falling edge is the active edge
	LPTIM_CFGR_TRIGEN_FallingEdge = 0x2
	// Both edges are active edges
	LPTIM_CFGR_TRIGEN_BothEdges = 0x3
	// Position of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Pos = 0xd
	// Bit mask of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Msk = 0xe000
	// lptim_ext_trig0
	LPTIM_CFGR_TRIGSEL_Trig0 = 0x0
	// lptim_ext_trig1
	LPTIM_CFGR_TRIGSEL_Trig1 = 0x1
	// lptim_ext_trig2
	LPTIM_CFGR_TRIGSEL_Trig2 = 0x2
	// lptim_ext_trig3
	LPTIM_CFGR_TRIGSEL_Trig3 = 0x3
	// lptim_ext_trig4
	LPTIM_CFGR_TRIGSEL_Trig4 = 0x4
	// lptim_ext_trig5
	LPTIM_CFGR_TRIGSEL_Trig5 = 0x5
	// lptim_ext_trig6
	LPTIM_CFGR_TRIGSEL_Trig6 = 0x6
	// lptim_ext_trig7
	LPTIM_CFGR_TRIGSEL_Trig7 = 0x7
	// Position of PRESC field.
	LPTIM_CFGR_PRESC_Pos = 0x9
	// Bit mask of PRESC field.
	LPTIM_CFGR_PRESC_Msk = 0xe00
	// /1
	LPTIM_CFGR_PRESC_Div1 = 0x0
	// /2
	LPTIM_CFGR_PRESC_Div2 = 0x1
	// /4
	LPTIM_CFGR_PRESC_Div4 = 0x2
	// /8
	LPTIM_CFGR_PRESC_Div8 = 0x3
	// /16
	LPTIM_CFGR_PRESC_Div16 = 0x4
	// /32
	LPTIM_CFGR_PRESC_Div32 = 0x5
	// /64
	LPTIM_CFGR_PRESC_Div64 = 0x6
	// /128
	LPTIM_CFGR_PRESC_Div128 = 0x7
	// Position of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Pos = 0x6
	// Bit mask of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Msk = 0xc0
	// Any trigger active level change is considered as a valid trigger
	LPTIM_CFGR_TRGFLT_Immediate = 0x0
	// Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
	LPTIM_CFGR_TRGFLT_Clocks2 = 0x1
	// Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
	LPTIM_CFGR_TRGFLT_Clocks4 = 0x2
	// Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger
	LPTIM_CFGR_TRGFLT_Clocks8 = 0x3
	// Position of CKFLT field.
	LPTIM_CFGR_CKFLT_Pos = 0x3
	// Bit mask of CKFLT field.
	LPTIM_CFGR_CKFLT_Msk = 0x18
	// Any external clock signal level change is considered as a valid transition
	LPTIM_CFGR_CKFLT_Immediate = 0x0
	// External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
	LPTIM_CFGR_CKFLT_Clocks2 = 0x1
	// External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
	LPTIM_CFGR_CKFLT_Clocks4 = 0x2
	// External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition
	LPTIM_CFGR_CKFLT_Clocks8 = 0x3
	// Position of CKPOL field.
	LPTIM_CFGR_CKPOL_Pos = 0x1
	// Bit mask of CKPOL field.
	LPTIM_CFGR_CKPOL_Msk = 0x6
	// The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
	LPTIM_CFGR_CKPOL_RisingEdge = 0x0
	// The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
	LPTIM_CFGR_CKPOL_FallingEdge = 0x1
	// Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.
	LPTIM_CFGR_CKPOL_BothEdges = 0x2
	// Position of CKSEL field.
	LPTIM_CFGR_CKSEL_Pos = 0x0
	// Bit mask of CKSEL field.
	LPTIM_CFGR_CKSEL_Msk = 0x1
	// Bit CKSEL.
	LPTIM_CFGR_CKSEL = 0x1
	// LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
	LPTIM_CFGR_CKSEL_Internal = 0x0
	// LPTIM is clocked by an external clock source through the LPTIM external Input1
	LPTIM_CFGR_CKSEL_External = 0x1

	// CR: Control Register
	// Position of ENABLE field.
	LPTIM_CR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	LPTIM_CR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	LPTIM_CR_ENABLE = 0x1
	// LPTIM is disabled
	LPTIM_CR_ENABLE_Disabled = 0x0
	// LPTIM is enabled
	LPTIM_CR_ENABLE_Enabled = 0x1
	// Position of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Pos = 0x1
	// Bit mask of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Msk = 0x2
	// Bit SNGSTRT.
	LPTIM_CR_SNGSTRT = 0x2
	// LPTIM start in Single mode
	LPTIM_CR_SNGSTRT_Start = 0x1
	// Position of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Pos = 0x2
	// Bit mask of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Msk = 0x4
	// Bit CNTSTRT.
	LPTIM_CR_CNTSTRT = 0x4
	// Timer start in Continuous mode
	LPTIM_CR_CNTSTRT_Start = 0x1
	// Position of COUNTRST field.
	LPTIM_CR_COUNTRST_Pos = 0x3
	// Bit mask of COUNTRST field.
	LPTIM_CR_COUNTRST_Msk = 0x8
	// Bit COUNTRST.
	LPTIM_CR_COUNTRST = 0x8
	// Position of RSTARE field.
	LPTIM_CR_RSTARE_Pos = 0x4
	// Bit mask of RSTARE field.
	LPTIM_CR_RSTARE_Msk = 0x10
	// Bit RSTARE.
	LPTIM_CR_RSTARE = 0x10

	// CMP: Compare Register
	// Position of CMP field.
	LPTIM_CMP_CMP_Pos = 0x0
	// Bit mask of CMP field.
	LPTIM_CMP_CMP_Msk = 0xffff

	// ARR: Autoreload Register
	// Position of ARR field.
	LPTIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	LPTIM_ARR_ARR_Msk = 0xffff

	// CNT: Counter Register
	// Position of CNT field.
	LPTIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	LPTIM_CNT_CNT_Msk = 0xffff

	// CFGR2: LPTIM configuration register 2
	// Position of IN1SEL field.
	LPTIM_CFGR2_IN1SEL_Pos = 0x0
	// Bit mask of IN1SEL field.
	LPTIM_CFGR2_IN1SEL_Msk = 0x3
	// Position of IN2SEL field.
	LPTIM_CFGR2_IN2SEL_Pos = 0x4
	// Bit mask of IN2SEL field.
	LPTIM_CFGR2_IN2SEL_Msk = 0x30
)

// Bitfields for LPUART1: LPUART1
const (
	// CR1: Control register 1
	// Position of RXFFIE field.
	LPUART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	LPUART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	LPUART_CR1_RXFFIE = 0x80000000
	// Position of TXFEIE field.
	LPUART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	LPUART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	LPUART_CR1_TXFEIE = 0x40000000
	// Position of FIFOEN field.
	LPUART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	LPUART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	LPUART_CR1_FIFOEN = 0x20000000
	// Position of M1 field.
	LPUART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	LPUART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	LPUART_CR1_M1 = 0x10000000
	// Position of DEAT field.
	LPUART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	LPUART_CR1_DEAT_Msk = 0x3e00000
	// Position of DEDT field.
	LPUART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	LPUART_CR1_DEDT_Msk = 0x1f0000
	// Position of CMIE field.
	LPUART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	LPUART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	LPUART_CR1_CMIE = 0x4000
	// Position of MME field.
	LPUART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	LPUART_CR1_MME_Msk = 0x2000
	// Bit MME.
	LPUART_CR1_MME = 0x2000
	// Position of M0 field.
	LPUART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	LPUART_CR1_M0_Msk = 0x1000
	// Bit M0.
	LPUART_CR1_M0 = 0x1000
	// Position of WAKE field.
	LPUART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	LPUART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	LPUART_CR1_WAKE = 0x800
	// Position of PCE field.
	LPUART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	LPUART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	LPUART_CR1_PCE = 0x400
	// Position of PS field.
	LPUART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	LPUART_CR1_PS_Msk = 0x200
	// Bit PS.
	LPUART_CR1_PS = 0x200
	// Position of PEIE field.
	LPUART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	LPUART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	LPUART_CR1_PEIE = 0x100
	// Position of TXEIE field.
	LPUART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	LPUART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	LPUART_CR1_TXEIE = 0x80
	// Position of TCIE field.
	LPUART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	LPUART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	LPUART_CR1_TCIE = 0x40
	// Position of RXNEIE field.
	LPUART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	LPUART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	LPUART_CR1_RXNEIE = 0x20
	// Position of IDLEIE field.
	LPUART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	LPUART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	LPUART_CR1_IDLEIE = 0x10
	// Position of TE field.
	LPUART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	LPUART_CR1_TE_Msk = 0x8
	// Bit TE.
	LPUART_CR1_TE = 0x8
	// Position of RE field.
	LPUART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	LPUART_CR1_RE_Msk = 0x4
	// Bit RE.
	LPUART_CR1_RE = 0x4
	// Position of UESM field.
	LPUART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	LPUART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	LPUART_CR1_UESM = 0x2
	// Position of UE field.
	LPUART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	LPUART_CR1_UE_Msk = 0x1
	// Bit UE.
	LPUART_CR1_UE = 0x1

	// CR2: Control register 2
	// Position of ADD field.
	LPUART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	LPUART_CR2_ADD_Msk = 0xff000000
	// Position of MSBFIRST field.
	LPUART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	LPUART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	LPUART_CR2_MSBFIRST = 0x80000
	// Position of DATAINV field.
	LPUART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	LPUART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	LPUART_CR2_DATAINV = 0x40000
	// Position of TXINV field.
	LPUART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	LPUART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	LPUART_CR2_TXINV = 0x20000
	// Position of RXINV field.
	LPUART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	LPUART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	LPUART_CR2_RXINV = 0x10000
	// Position of SWAP field.
	LPUART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	LPUART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	LPUART_CR2_SWAP = 0x8000
	// Position of STOP field.
	LPUART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	LPUART_CR2_STOP_Msk = 0x3000
	// Position of ADDM7 field.
	LPUART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	LPUART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	LPUART_CR2_ADDM7 = 0x10

	// CR3: Control register 3
	// Position of TXFTCFG field.
	LPUART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	LPUART_CR3_TXFTCFG_Msk = 0xe0000000
	// Position of RXFTIE field.
	LPUART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	LPUART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	LPUART_CR3_RXFTIE = 0x10000000
	// Position of RXFTCFG field.
	LPUART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	LPUART_CR3_RXFTCFG_Msk = 0xe000000
	// Position of TXFTIE field.
	LPUART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	LPUART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	LPUART_CR3_TXFTIE = 0x800000
	// Position of WUFIE field.
	LPUART_CR3_WUFIE_Pos = 0x16
	// Bit mask of WUFIE field.
	LPUART_CR3_WUFIE_Msk = 0x400000
	// Bit WUFIE.
	LPUART_CR3_WUFIE = 0x400000
	// Position of WUS field.
	LPUART_CR3_WUS_Pos = 0x14
	// Bit mask of WUS field.
	LPUART_CR3_WUS_Msk = 0x300000
	// Position of DEP field.
	LPUART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	LPUART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	LPUART_CR3_DEP = 0x8000
	// Position of DEM field.
	LPUART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	LPUART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	LPUART_CR3_DEM = 0x4000
	// Position of DDRE field.
	LPUART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	LPUART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	LPUART_CR3_DDRE = 0x2000
	// Position of OVRDIS field.
	LPUART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	LPUART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	LPUART_CR3_OVRDIS = 0x1000
	// Position of CTSIE field.
	LPUART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	LPUART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	LPUART_CR3_CTSIE = 0x400
	// Position of CTSE field.
	LPUART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	LPUART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	LPUART_CR3_CTSE = 0x200
	// Position of RTSE field.
	LPUART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	LPUART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	LPUART_CR3_RTSE = 0x100
	// Position of DMAT field.
	LPUART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	LPUART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	LPUART_CR3_DMAT = 0x80
	// Position of DMAR field.
	LPUART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	LPUART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	LPUART_CR3_DMAR = 0x40
	// Position of HDSEL field.
	LPUART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	LPUART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	LPUART_CR3_HDSEL = 0x8
	// Position of EIE field.
	LPUART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	LPUART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	LPUART_CR3_EIE = 0x1

	// BRR: Baud rate register
	// Position of BRR field.
	LPUART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	LPUART_BRR_BRR_Msk = 0xfffff

	// GTPR: Guard time and prescaler register
	// Position of GT field.
	LPUART_GTPR_GT_Pos = 0x8
	// Bit mask of GT field.
	LPUART_GTPR_GT_Msk = 0xff00
	// Position of PSC field.
	LPUART_GTPR_PSC_Pos = 0x0
	// Bit mask of PSC field.
	LPUART_GTPR_PSC_Msk = 0xff

	// RTOR: Receiver timeout register
	// Position of BLEN field.
	LPUART_RTOR_BLEN_Pos = 0x18
	// Bit mask of BLEN field.
	LPUART_RTOR_BLEN_Msk = 0xff000000
	// Position of RTO field.
	LPUART_RTOR_RTO_Pos = 0x0
	// Bit mask of RTO field.
	LPUART_RTOR_RTO_Msk = 0xffffff

	// RQR: Request register
	// Position of TXFRQ field.
	LPUART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	LPUART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	LPUART_RQR_TXFRQ = 0x10
	// Position of RXFRQ field.
	LPUART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	LPUART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	LPUART_RQR_RXFRQ = 0x8
	// Position of MMRQ field.
	LPUART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	LPUART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	LPUART_RQR_MMRQ = 0x4
	// Position of SBKRQ field.
	LPUART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	LPUART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	LPUART_RQR_SBKRQ = 0x2
	// Position of ABRRQ field.
	LPUART_RQR_ABRRQ_Pos = 0x0
	// Bit mask of ABRRQ field.
	LPUART_RQR_ABRRQ_Msk = 0x1
	// Bit ABRRQ.
	LPUART_RQR_ABRRQ = 0x1

	// ISR: Interrupt & status register
	// Position of TXFT field.
	LPUART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	LPUART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	LPUART_ISR_TXFT = 0x8000000
	// Position of RXFT field.
	LPUART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	LPUART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	LPUART_ISR_RXFT = 0x4000000
	// Position of RXFF field.
	LPUART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	LPUART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	LPUART_ISR_RXFF = 0x1000000
	// Position of TXFE field.
	LPUART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	LPUART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	LPUART_ISR_TXFE = 0x800000
	// Position of REACK field.
	LPUART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	LPUART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	LPUART_ISR_REACK = 0x400000
	// Position of TEACK field.
	LPUART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	LPUART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	LPUART_ISR_TEACK = 0x200000
	// Position of WUF field.
	LPUART_ISR_WUF_Pos = 0x14
	// Bit mask of WUF field.
	LPUART_ISR_WUF_Msk = 0x100000
	// Bit WUF.
	LPUART_ISR_WUF = 0x100000
	// Position of RWU field.
	LPUART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	LPUART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	LPUART_ISR_RWU = 0x80000
	// Position of SBKF field.
	LPUART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	LPUART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	LPUART_ISR_SBKF = 0x40000
	// Position of CMF field.
	LPUART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	LPUART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	LPUART_ISR_CMF = 0x20000
	// Position of BUSY field.
	LPUART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	LPUART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	LPUART_ISR_BUSY = 0x10000
	// Position of CTS field.
	LPUART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	LPUART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	LPUART_ISR_CTS = 0x400
	// Position of CTSIF field.
	LPUART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	LPUART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	LPUART_ISR_CTSIF = 0x200
	// Position of TXE field.
	LPUART_ISR_TXE_Pos = 0x7
	// Bit mask of TXE field.
	LPUART_ISR_TXE_Msk = 0x80
	// Bit TXE.
	LPUART_ISR_TXE = 0x80
	// Position of TC field.
	LPUART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	LPUART_ISR_TC_Msk = 0x40
	// Bit TC.
	LPUART_ISR_TC = 0x40
	// Position of RXNE field.
	LPUART_ISR_RXNE_Pos = 0x5
	// Bit mask of RXNE field.
	LPUART_ISR_RXNE_Msk = 0x20
	// Bit RXNE.
	LPUART_ISR_RXNE = 0x20
	// Position of IDLE field.
	LPUART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	LPUART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	LPUART_ISR_IDLE = 0x10
	// Position of ORE field.
	LPUART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	LPUART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	LPUART_ISR_ORE = 0x8
	// Position of NE field.
	LPUART_ISR_NE_Pos = 0x2
	// Bit mask of NE field.
	LPUART_ISR_NE_Msk = 0x4
	// Bit NE.
	LPUART_ISR_NE = 0x4
	// Position of FE field.
	LPUART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	LPUART_ISR_FE_Msk = 0x2
	// Bit FE.
	LPUART_ISR_FE = 0x2
	// Position of PE field.
	LPUART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	LPUART_ISR_PE_Msk = 0x1
	// Bit PE.
	LPUART_ISR_PE = 0x1

	// ICR: Interrupt flag clear register
	// Position of WUCF field.
	LPUART_ICR_WUCF_Pos = 0x14
	// Bit mask of WUCF field.
	LPUART_ICR_WUCF_Msk = 0x100000
	// Bit WUCF.
	LPUART_ICR_WUCF = 0x100000
	// Position of CMCF field.
	LPUART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	LPUART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	LPUART_ICR_CMCF = 0x20000
	// Position of CTSCF field.
	LPUART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	LPUART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	LPUART_ICR_CTSCF = 0x200
	// Position of TCCF field.
	LPUART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	LPUART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	LPUART_ICR_TCCF = 0x40
	// Position of IDLECF field.
	LPUART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	LPUART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	LPUART_ICR_IDLECF = 0x10
	// Position of ORECF field.
	LPUART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	LPUART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	LPUART_ICR_ORECF = 0x8
	// Position of NCF field.
	LPUART_ICR_NCF_Pos = 0x2
	// Bit mask of NCF field.
	LPUART_ICR_NCF_Msk = 0x4
	// Bit NCF.
	LPUART_ICR_NCF = 0x4
	// Position of FECF field.
	LPUART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	LPUART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	LPUART_ICR_FECF = 0x2
	// Position of PECF field.
	LPUART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	LPUART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	LPUART_ICR_PECF = 0x1

	// RDR: Receive data register
	// Position of RDR field.
	LPUART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	LPUART_RDR_RDR_Msk = 0x1ff

	// TDR: Transmit data register
	// Position of TDR field.
	LPUART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	LPUART_TDR_TDR_Msk = 0x1ff

	// PRESC: Prescaler register
	// Position of PRESCALER field.
	LPUART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	LPUART_PRESC_PRESCALER_Msk = 0xf
)

// Bitfields for SYSCFG: System configuration controller
const (
	// PMCR: peripheral mode configuration register
	// Position of I2C1FMP field.
	SYSCFG_PMCR_I2C1FMP_Pos = 0x0
	// Bit mask of I2C1FMP field.
	SYSCFG_PMCR_I2C1FMP_Msk = 0x1
	// Bit I2C1FMP.
	SYSCFG_PMCR_I2C1FMP = 0x1
	// Position of I2C2FMP field.
	SYSCFG_PMCR_I2C2FMP_Pos = 0x1
	// Bit mask of I2C2FMP field.
	SYSCFG_PMCR_I2C2FMP_Msk = 0x2
	// Bit I2C2FMP.
	SYSCFG_PMCR_I2C2FMP = 0x2
	// Position of I2C3FMP field.
	SYSCFG_PMCR_I2C3FMP_Pos = 0x2
	// Bit mask of I2C3FMP field.
	SYSCFG_PMCR_I2C3FMP_Msk = 0x4
	// Bit I2C3FMP.
	SYSCFG_PMCR_I2C3FMP = 0x4
	// Position of I2C4FMP field.
	SYSCFG_PMCR_I2C4FMP_Pos = 0x3
	// Bit mask of I2C4FMP field.
	SYSCFG_PMCR_I2C4FMP_Msk = 0x8
	// Bit I2C4FMP.
	SYSCFG_PMCR_I2C4FMP = 0x8
	// Position of PB6FMP field.
	SYSCFG_PMCR_PB6FMP_Pos = 0x4
	// Bit mask of PB6FMP field.
	SYSCFG_PMCR_PB6FMP_Msk = 0x10
	// Bit PB6FMP.
	SYSCFG_PMCR_PB6FMP = 0x10
	// Position of PB7FMP field.
	SYSCFG_PMCR_PB7FMP_Pos = 0x5
	// Bit mask of PB7FMP field.
	SYSCFG_PMCR_PB7FMP_Msk = 0x20
	// Bit PB7FMP.
	SYSCFG_PMCR_PB7FMP = 0x20
	// Position of PB8FMP field.
	SYSCFG_PMCR_PB8FMP_Pos = 0x6
	// Bit mask of PB8FMP field.
	SYSCFG_PMCR_PB8FMP_Msk = 0x40
	// Bit PB8FMP.
	SYSCFG_PMCR_PB8FMP = 0x40
	// Position of PB9FMP field.
	SYSCFG_PMCR_PB9FMP_Pos = 0x7
	// Bit mask of PB9FMP field.
	SYSCFG_PMCR_PB9FMP_Msk = 0x80
	// Bit PB9FMP.
	SYSCFG_PMCR_PB9FMP = 0x80
	// Position of BOOSTE field.
	SYSCFG_PMCR_BOOSTE_Pos = 0x8
	// Bit mask of BOOSTE field.
	SYSCFG_PMCR_BOOSTE_Msk = 0x100
	// Bit BOOSTE.
	SYSCFG_PMCR_BOOSTE = 0x100
	// Position of BOOSTVDDSEL field.
	SYSCFG_PMCR_BOOSTVDDSEL_Pos = 0x9
	// Bit mask of BOOSTVDDSEL field.
	SYSCFG_PMCR_BOOSTVDDSEL_Msk = 0x200
	// Bit BOOSTVDDSEL.
	SYSCFG_PMCR_BOOSTVDDSEL = 0x200
	// Position of EPIS field.
	SYSCFG_PMCR_EPIS_Pos = 0x15
	// Bit mask of EPIS field.
	SYSCFG_PMCR_EPIS_Msk = 0xe00000
	// Position of PA0SO field.
	SYSCFG_PMCR_PA0SO_Pos = 0x18
	// Bit mask of PA0SO field.
	SYSCFG_PMCR_PA0SO_Msk = 0x1000000
	// Bit PA0SO.
	SYSCFG_PMCR_PA0SO = 0x1000000
	// Position of PA1SO field.
	SYSCFG_PMCR_PA1SO_Pos = 0x19
	// Bit mask of PA1SO field.
	SYSCFG_PMCR_PA1SO_Msk = 0x2000000
	// Bit PA1SO.
	SYSCFG_PMCR_PA1SO = 0x2000000
	// Position of PC2SO field.
	SYSCFG_PMCR_PC2SO_Pos = 0x1a
	// Bit mask of PC2SO field.
	SYSCFG_PMCR_PC2SO_Msk = 0x4000000
	// Bit PC2SO.
	SYSCFG_PMCR_PC2SO = 0x4000000
	// Position of PC3SO field.
	SYSCFG_PMCR_PC3SO_Pos = 0x1b
	// Bit mask of PC3SO field.
	SYSCFG_PMCR_PC3SO_Msk = 0x8000000
	// Bit PC3SO.
	SYSCFG_PMCR_PC3SO = 0x8000000

	// EXTICR1: external interrupt configuration register 1
	// Position of EXTI3 field.
	SYSCFG_EXTICR1_EXTI3_Pos = 0xc
	// Bit mask of EXTI3 field.
	SYSCFG_EXTICR1_EXTI3_Msk = 0xf000
	// Position of EXTI2 field.
	SYSCFG_EXTICR1_EXTI2_Pos = 0x8
	// Bit mask of EXTI2 field.
	SYSCFG_EXTICR1_EXTI2_Msk = 0xf00
	// Position of EXTI1 field.
	SYSCFG_EXTICR1_EXTI1_Pos = 0x4
	// Bit mask of EXTI1 field.
	SYSCFG_EXTICR1_EXTI1_Msk = 0xf0
	// Position of EXTI0 field.
	SYSCFG_EXTICR1_EXTI0_Pos = 0x0
	// Bit mask of EXTI0 field.
	SYSCFG_EXTICR1_EXTI0_Msk = 0xf

	// EXTICR2: external interrupt configuration register 2
	// Position of EXTI7 field.
	SYSCFG_EXTICR2_EXTI7_Pos = 0xc
	// Bit mask of EXTI7 field.
	SYSCFG_EXTICR2_EXTI7_Msk = 0xf000
	// Position of EXTI6 field.
	SYSCFG_EXTICR2_EXTI6_Pos = 0x8
	// Bit mask of EXTI6 field.
	SYSCFG_EXTICR2_EXTI6_Msk = 0xf00
	// Position of EXTI5 field.
	SYSCFG_EXTICR2_EXTI5_Pos = 0x4
	// Bit mask of EXTI5 field.
	SYSCFG_EXTICR2_EXTI5_Msk = 0xf0
	// Position of EXTI4 field.
	SYSCFG_EXTICR2_EXTI4_Pos = 0x0
	// Bit mask of EXTI4 field.
	SYSCFG_EXTICR2_EXTI4_Msk = 0xf

	// EXTICR3: external interrupt configuration register 3
	// Position of EXTI11 field.
	SYSCFG_EXTICR3_EXTI11_Pos = 0xc
	// Bit mask of EXTI11 field.
	SYSCFG_EXTICR3_EXTI11_Msk = 0xf000
	// Position of EXTI10 field.
	SYSCFG_EXTICR3_EXTI10_Pos = 0x8
	// Bit mask of EXTI10 field.
	SYSCFG_EXTICR3_EXTI10_Msk = 0xf00
	// Position of EXTI9 field.
	SYSCFG_EXTICR3_EXTI9_Pos = 0x4
	// Bit mask of EXTI9 field.
	SYSCFG_EXTICR3_EXTI9_Msk = 0xf0
	// Position of EXTI8 field.
	SYSCFG_EXTICR3_EXTI8_Pos = 0x0
	// Bit mask of EXTI8 field.
	SYSCFG_EXTICR3_EXTI8_Msk = 0xf

	// EXTICR4: external interrupt configuration register 4
	// Position of EXTI15 field.
	SYSCFG_EXTICR4_EXTI15_Pos = 0xc
	// Bit mask of EXTI15 field.
	SYSCFG_EXTICR4_EXTI15_Msk = 0xf000
	// Position of EXTI14 field.
	SYSCFG_EXTICR4_EXTI14_Pos = 0x8
	// Bit mask of EXTI14 field.
	SYSCFG_EXTICR4_EXTI14_Msk = 0xf00
	// Position of EXTI13 field.
	SYSCFG_EXTICR4_EXTI13_Pos = 0x4
	// Bit mask of EXTI13 field.
	SYSCFG_EXTICR4_EXTI13_Msk = 0xf0
	// Position of EXTI12 field.
	SYSCFG_EXTICR4_EXTI12_Pos = 0x0
	// Bit mask of EXTI12 field.
	SYSCFG_EXTICR4_EXTI12_Msk = 0xf

	// CCCSR: compensation cell control/status register
	// Position of EN field.
	SYSCFG_CCCSR_EN_Pos = 0x0
	// Bit mask of EN field.
	SYSCFG_CCCSR_EN_Msk = 0x1
	// Bit EN.
	SYSCFG_CCCSR_EN = 0x1
	// Position of CS field.
	SYSCFG_CCCSR_CS_Pos = 0x1
	// Bit mask of CS field.
	SYSCFG_CCCSR_CS_Msk = 0x2
	// Bit CS.
	SYSCFG_CCCSR_CS = 0x2
	// Position of READY field.
	SYSCFG_CCCSR_READY_Pos = 0x8
	// Bit mask of READY field.
	SYSCFG_CCCSR_READY_Msk = 0x100
	// Bit READY.
	SYSCFG_CCCSR_READY = 0x100
	// Position of HSLV field.
	SYSCFG_CCCSR_HSLV_Pos = 0x10
	// Bit mask of HSLV field.
	SYSCFG_CCCSR_HSLV_Msk = 0x10000
	// Bit HSLV.
	SYSCFG_CCCSR_HSLV = 0x10000

	// CCVR: SYSCFG compensation cell value register
	// Position of NCV field.
	SYSCFG_CCVR_NCV_Pos = 0x0
	// Bit mask of NCV field.
	SYSCFG_CCVR_NCV_Msk = 0xf
	// Position of PCV field.
	SYSCFG_CCVR_PCV_Pos = 0x4
	// Bit mask of PCV field.
	SYSCFG_CCVR_PCV_Msk = 0xf0

	// CCCR: SYSCFG compensation cell code register
	// Position of NCC field.
	SYSCFG_CCCR_NCC_Pos = 0x0
	// Bit mask of NCC field.
	SYSCFG_CCCR_NCC_Msk = 0xf
	// Position of PCC field.
	SYSCFG_CCCR_PCC_Pos = 0x4
	// Bit mask of PCC field.
	SYSCFG_CCCR_PCC_Msk = 0xf0

	// PWRCR: SYSCFG power control register
	// Position of ODEN field.
	SYSCFG_PWRCR_ODEN_Pos = 0x0
	// Bit mask of ODEN field.
	SYSCFG_PWRCR_ODEN_Msk = 0xf

	// PKGR: SYSCFG package register
	// Position of PKG field.
	SYSCFG_PKGR_PKG_Pos = 0x0
	// Bit mask of PKG field.
	SYSCFG_PKGR_PKG_Msk = 0xf

	// UR0: SYSCFG user register 0
	// Position of BKS field.
	SYSCFG_UR0_BKS_Pos = 0x0
	// Bit mask of BKS field.
	SYSCFG_UR0_BKS_Msk = 0x1
	// Bit BKS.
	SYSCFG_UR0_BKS = 0x1
	// Position of RDP field.
	SYSCFG_UR0_RDP_Pos = 0x10
	// Bit mask of RDP field.
	SYSCFG_UR0_RDP_Msk = 0xff0000

	// UR2: SYSCFG user register 2
	// Position of BORH field.
	SYSCFG_UR2_BORH_Pos = 0x0
	// Bit mask of BORH field.
	SYSCFG_UR2_BORH_Msk = 0x3
	// Position of BOOT_ADD0 field.
	SYSCFG_UR2_BOOT_ADD0_Pos = 0x10
	// Bit mask of BOOT_ADD0 field.
	SYSCFG_UR2_BOOT_ADD0_Msk = 0xffff0000

	// UR3: SYSCFG user register 3
	// Position of BOOT_ADD1 field.
	SYSCFG_UR3_BOOT_ADD1_Pos = 0x10
	// Bit mask of BOOT_ADD1 field.
	SYSCFG_UR3_BOOT_ADD1_Msk = 0xffff0000

	// UR4: SYSCFG user register 4
	// Position of MEPAD_1 field.
	SYSCFG_UR4_MEPAD_1_Pos = 0x10
	// Bit mask of MEPAD_1 field.
	SYSCFG_UR4_MEPAD_1_Msk = 0x10000
	// Bit MEPAD_1.
	SYSCFG_UR4_MEPAD_1 = 0x10000

	// UR5: SYSCFG user register 5
	// Position of MESAD_1 field.
	SYSCFG_UR5_MESAD_1_Pos = 0x0
	// Bit mask of MESAD_1 field.
	SYSCFG_UR5_MESAD_1_Msk = 0x1
	// Bit MESAD_1.
	SYSCFG_UR5_MESAD_1 = 0x1
	// Position of WRPN_1 field.
	SYSCFG_UR5_WRPN_1_Pos = 0x10
	// Bit mask of WRPN_1 field.
	SYSCFG_UR5_WRPN_1_Msk = 0xff0000

	// UR6: SYSCFG user register 6
	// Position of PA_BEG_1 field.
	SYSCFG_UR6_PA_BEG_1_Pos = 0x0
	// Bit mask of PA_BEG_1 field.
	SYSCFG_UR6_PA_BEG_1_Msk = 0xfff
	// Position of PA_END_1 field.
	SYSCFG_UR6_PA_END_1_Pos = 0x10
	// Bit mask of PA_END_1 field.
	SYSCFG_UR6_PA_END_1_Msk = 0xfff0000

	// UR7: SYSCFG user register 7
	// Position of SA_BEG_1 field.
	SYSCFG_UR7_SA_BEG_1_Pos = 0x0
	// Bit mask of SA_BEG_1 field.
	SYSCFG_UR7_SA_BEG_1_Msk = 0xfff
	// Position of SA_END_1 field.
	SYSCFG_UR7_SA_END_1_Pos = 0x10
	// Bit mask of SA_END_1 field.
	SYSCFG_UR7_SA_END_1_Msk = 0xfff0000

	// UR8: SYSCFG user register 8
	// Position of MEPAD_2 field.
	SYSCFG_UR8_MEPAD_2_Pos = 0x0
	// Bit mask of MEPAD_2 field.
	SYSCFG_UR8_MEPAD_2_Msk = 0x1
	// Bit MEPAD_2.
	SYSCFG_UR8_MEPAD_2 = 0x1
	// Position of MESAD_2 field.
	SYSCFG_UR8_MESAD_2_Pos = 0x10
	// Bit mask of MESAD_2 field.
	SYSCFG_UR8_MESAD_2_Msk = 0x10000
	// Bit MESAD_2.
	SYSCFG_UR8_MESAD_2 = 0x10000

	// UR9: SYSCFG user register 9
	// Position of WRPN_2 field.
	SYSCFG_UR9_WRPN_2_Pos = 0x0
	// Bit mask of WRPN_2 field.
	SYSCFG_UR9_WRPN_2_Msk = 0xff
	// Position of PA_BEG_2 field.
	SYSCFG_UR9_PA_BEG_2_Pos = 0x10
	// Bit mask of PA_BEG_2 field.
	SYSCFG_UR9_PA_BEG_2_Msk = 0xfff0000

	// UR10: SYSCFG user register 10
	// Position of PA_END_2 field.
	SYSCFG_UR10_PA_END_2_Pos = 0x0
	// Bit mask of PA_END_2 field.
	SYSCFG_UR10_PA_END_2_Msk = 0xfff
	// Position of SA_BEG_2 field.
	SYSCFG_UR10_SA_BEG_2_Pos = 0x10
	// Bit mask of SA_BEG_2 field.
	SYSCFG_UR10_SA_BEG_2_Msk = 0xfff0000

	// UR11: SYSCFG user register 11
	// Position of SA_END_2 field.
	SYSCFG_UR11_SA_END_2_Pos = 0x0
	// Bit mask of SA_END_2 field.
	SYSCFG_UR11_SA_END_2_Msk = 0xfff
	// Position of IWDG1M field.
	SYSCFG_UR11_IWDG1M_Pos = 0x10
	// Bit mask of IWDG1M field.
	SYSCFG_UR11_IWDG1M_Msk = 0x10000
	// Bit IWDG1M.
	SYSCFG_UR11_IWDG1M = 0x10000

	// UR12: SYSCFG user register 12
	// Position of SECURE field.
	SYSCFG_UR12_SECURE_Pos = 0x10
	// Bit mask of SECURE field.
	SYSCFG_UR12_SECURE_Msk = 0x10000
	// Bit SECURE.
	SYSCFG_UR12_SECURE = 0x10000

	// UR13: SYSCFG user register 13
	// Position of SDRS field.
	SYSCFG_UR13_SDRS_Pos = 0x0
	// Bit mask of SDRS field.
	SYSCFG_UR13_SDRS_Msk = 0x3
	// Position of D1SBRST field.
	SYSCFG_UR13_D1SBRST_Pos = 0x10
	// Bit mask of D1SBRST field.
	SYSCFG_UR13_D1SBRST_Msk = 0x10000
	// Bit D1SBRST.
	SYSCFG_UR13_D1SBRST = 0x10000

	// UR14: SYSCFG user register 14
	// Position of D1STPRST field.
	SYSCFG_UR14_D1STPRST_Pos = 0x0
	// Bit mask of D1STPRST field.
	SYSCFG_UR14_D1STPRST_Msk = 0x1
	// Bit D1STPRST.
	SYSCFG_UR14_D1STPRST = 0x1

	// UR15: SYSCFG user register 15
	// Position of FZIWDGSTB field.
	SYSCFG_UR15_FZIWDGSTB_Pos = 0x10
	// Bit mask of FZIWDGSTB field.
	SYSCFG_UR15_FZIWDGSTB_Msk = 0x10000
	// Bit FZIWDGSTB.
	SYSCFG_UR15_FZIWDGSTB = 0x10000

	// UR16: SYSCFG user register 16
	// Position of FZIWDGSTP field.
	SYSCFG_UR16_FZIWDGSTP_Pos = 0x0
	// Bit mask of FZIWDGSTP field.
	SYSCFG_UR16_FZIWDGSTP_Msk = 0x1
	// Bit FZIWDGSTP.
	SYSCFG_UR16_FZIWDGSTP = 0x1
	// Position of PKP field.
	SYSCFG_UR16_PKP_Pos = 0x10
	// Bit mask of PKP field.
	SYSCFG_UR16_PKP_Msk = 0x10000
	// Bit PKP.
	SYSCFG_UR16_PKP = 0x10000

	// UR17: SYSCFG user register 17
	// Position of IO_HSLV field.
	SYSCFG_UR17_IO_HSLV_Pos = 0x0
	// Bit mask of IO_HSLV field.
	SYSCFG_UR17_IO_HSLV_Msk = 0x1
	// Bit IO_HSLV.
	SYSCFG_UR17_IO_HSLV = 0x1
)

// Bitfields for EXTI: External interrupt/event controller
const (
	// RTSR1: EXTI rising trigger selection register
	// Position of TR0 field.
	EXTI_RTSR1_TR0_Pos = 0x0
	// Bit mask of TR0 field.
	EXTI_RTSR1_TR0_Msk = 0x1
	// Bit TR0.
	EXTI_RTSR1_TR0 = 0x1
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR0_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR0_Enabled = 0x1
	// Position of TR1 field.
	EXTI_RTSR1_TR1_Pos = 0x1
	// Bit mask of TR1 field.
	EXTI_RTSR1_TR1_Msk = 0x2
	// Bit TR1.
	EXTI_RTSR1_TR1 = 0x2
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR1_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR1_Enabled = 0x1
	// Position of TR2 field.
	EXTI_RTSR1_TR2_Pos = 0x2
	// Bit mask of TR2 field.
	EXTI_RTSR1_TR2_Msk = 0x4
	// Bit TR2.
	EXTI_RTSR1_TR2 = 0x4
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR2_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR2_Enabled = 0x1
	// Position of TR3 field.
	EXTI_RTSR1_TR3_Pos = 0x3
	// Bit mask of TR3 field.
	EXTI_RTSR1_TR3_Msk = 0x8
	// Bit TR3.
	EXTI_RTSR1_TR3 = 0x8
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR3_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR3_Enabled = 0x1
	// Position of TR4 field.
	EXTI_RTSR1_TR4_Pos = 0x4
	// Bit mask of TR4 field.
	EXTI_RTSR1_TR4_Msk = 0x10
	// Bit TR4.
	EXTI_RTSR1_TR4 = 0x10
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR4_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR4_Enabled = 0x1
	// Position of TR5 field.
	EXTI_RTSR1_TR5_Pos = 0x5
	// Bit mask of TR5 field.
	EXTI_RTSR1_TR5_Msk = 0x20
	// Bit TR5.
	EXTI_RTSR1_TR5 = 0x20
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR5_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR5_Enabled = 0x1
	// Position of TR6 field.
	EXTI_RTSR1_TR6_Pos = 0x6
	// Bit mask of TR6 field.
	EXTI_RTSR1_TR6_Msk = 0x40
	// Bit TR6.
	EXTI_RTSR1_TR6 = 0x40
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR6_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR6_Enabled = 0x1
	// Position of TR7 field.
	EXTI_RTSR1_TR7_Pos = 0x7
	// Bit mask of TR7 field.
	EXTI_RTSR1_TR7_Msk = 0x80
	// Bit TR7.
	EXTI_RTSR1_TR7 = 0x80
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR7_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR7_Enabled = 0x1
	// Position of TR8 field.
	EXTI_RTSR1_TR8_Pos = 0x8
	// Bit mask of TR8 field.
	EXTI_RTSR1_TR8_Msk = 0x100
	// Bit TR8.
	EXTI_RTSR1_TR8 = 0x100
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR8_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR8_Enabled = 0x1
	// Position of TR9 field.
	EXTI_RTSR1_TR9_Pos = 0x9
	// Bit mask of TR9 field.
	EXTI_RTSR1_TR9_Msk = 0x200
	// Bit TR9.
	EXTI_RTSR1_TR9 = 0x200
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR9_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR9_Enabled = 0x1
	// Position of TR10 field.
	EXTI_RTSR1_TR10_Pos = 0xa
	// Bit mask of TR10 field.
	EXTI_RTSR1_TR10_Msk = 0x400
	// Bit TR10.
	EXTI_RTSR1_TR10 = 0x400
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR10_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR10_Enabled = 0x1
	// Position of TR11 field.
	EXTI_RTSR1_TR11_Pos = 0xb
	// Bit mask of TR11 field.
	EXTI_RTSR1_TR11_Msk = 0x800
	// Bit TR11.
	EXTI_RTSR1_TR11 = 0x800
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR11_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR11_Enabled = 0x1
	// Position of TR12 field.
	EXTI_RTSR1_TR12_Pos = 0xc
	// Bit mask of TR12 field.
	EXTI_RTSR1_TR12_Msk = 0x1000
	// Bit TR12.
	EXTI_RTSR1_TR12 = 0x1000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR12_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR12_Enabled = 0x1
	// Position of TR13 field.
	EXTI_RTSR1_TR13_Pos = 0xd
	// Bit mask of TR13 field.
	EXTI_RTSR1_TR13_Msk = 0x2000
	// Bit TR13.
	EXTI_RTSR1_TR13 = 0x2000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR13_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR13_Enabled = 0x1
	// Position of TR14 field.
	EXTI_RTSR1_TR14_Pos = 0xe
	// Bit mask of TR14 field.
	EXTI_RTSR1_TR14_Msk = 0x4000
	// Bit TR14.
	EXTI_RTSR1_TR14 = 0x4000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR14_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR14_Enabled = 0x1
	// Position of TR15 field.
	EXTI_RTSR1_TR15_Pos = 0xf
	// Bit mask of TR15 field.
	EXTI_RTSR1_TR15_Msk = 0x8000
	// Bit TR15.
	EXTI_RTSR1_TR15 = 0x8000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR15_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR15_Enabled = 0x1
	// Position of TR16 field.
	EXTI_RTSR1_TR16_Pos = 0x10
	// Bit mask of TR16 field.
	EXTI_RTSR1_TR16_Msk = 0x10000
	// Bit TR16.
	EXTI_RTSR1_TR16 = 0x10000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR16_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR16_Enabled = 0x1
	// Position of TR17 field.
	EXTI_RTSR1_TR17_Pos = 0x11
	// Bit mask of TR17 field.
	EXTI_RTSR1_TR17_Msk = 0x20000
	// Bit TR17.
	EXTI_RTSR1_TR17 = 0x20000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR17_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR17_Enabled = 0x1
	// Position of TR18 field.
	EXTI_RTSR1_TR18_Pos = 0x12
	// Bit mask of TR18 field.
	EXTI_RTSR1_TR18_Msk = 0x40000
	// Bit TR18.
	EXTI_RTSR1_TR18 = 0x40000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR18_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR18_Enabled = 0x1
	// Position of TR19 field.
	EXTI_RTSR1_TR19_Pos = 0x13
	// Bit mask of TR19 field.
	EXTI_RTSR1_TR19_Msk = 0x80000
	// Bit TR19.
	EXTI_RTSR1_TR19 = 0x80000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR19_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR19_Enabled = 0x1
	// Position of TR20 field.
	EXTI_RTSR1_TR20_Pos = 0x14
	// Bit mask of TR20 field.
	EXTI_RTSR1_TR20_Msk = 0x100000
	// Bit TR20.
	EXTI_RTSR1_TR20 = 0x100000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR20_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR20_Enabled = 0x1
	// Position of TR21 field.
	EXTI_RTSR1_TR21_Pos = 0x15
	// Bit mask of TR21 field.
	EXTI_RTSR1_TR21_Msk = 0x200000
	// Bit TR21.
	EXTI_RTSR1_TR21 = 0x200000
	// Rising edge trigger is disabled
	EXTI_RTSR1_TR21_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_TR21_Enabled = 0x1

	// FTSR1: EXTI falling trigger selection register
	// Position of TR0 field.
	EXTI_FTSR1_TR0_Pos = 0x0
	// Bit mask of TR0 field.
	EXTI_FTSR1_TR0_Msk = 0x1
	// Bit TR0.
	EXTI_FTSR1_TR0 = 0x1
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR0_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR0_Enabled = 0x1
	// Position of TR1 field.
	EXTI_FTSR1_TR1_Pos = 0x1
	// Bit mask of TR1 field.
	EXTI_FTSR1_TR1_Msk = 0x2
	// Bit TR1.
	EXTI_FTSR1_TR1 = 0x2
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR1_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR1_Enabled = 0x1
	// Position of TR2 field.
	EXTI_FTSR1_TR2_Pos = 0x2
	// Bit mask of TR2 field.
	EXTI_FTSR1_TR2_Msk = 0x4
	// Bit TR2.
	EXTI_FTSR1_TR2 = 0x4
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR2_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR2_Enabled = 0x1
	// Position of TR3 field.
	EXTI_FTSR1_TR3_Pos = 0x3
	// Bit mask of TR3 field.
	EXTI_FTSR1_TR3_Msk = 0x8
	// Bit TR3.
	EXTI_FTSR1_TR3 = 0x8
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR3_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR3_Enabled = 0x1
	// Position of TR4 field.
	EXTI_FTSR1_TR4_Pos = 0x4
	// Bit mask of TR4 field.
	EXTI_FTSR1_TR4_Msk = 0x10
	// Bit TR4.
	EXTI_FTSR1_TR4 = 0x10
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR4_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR4_Enabled = 0x1
	// Position of TR5 field.
	EXTI_FTSR1_TR5_Pos = 0x5
	// Bit mask of TR5 field.
	EXTI_FTSR1_TR5_Msk = 0x20
	// Bit TR5.
	EXTI_FTSR1_TR5 = 0x20
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR5_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR5_Enabled = 0x1
	// Position of TR6 field.
	EXTI_FTSR1_TR6_Pos = 0x6
	// Bit mask of TR6 field.
	EXTI_FTSR1_TR6_Msk = 0x40
	// Bit TR6.
	EXTI_FTSR1_TR6 = 0x40
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR6_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR6_Enabled = 0x1
	// Position of TR7 field.
	EXTI_FTSR1_TR7_Pos = 0x7
	// Bit mask of TR7 field.
	EXTI_FTSR1_TR7_Msk = 0x80
	// Bit TR7.
	EXTI_FTSR1_TR7 = 0x80
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR7_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR7_Enabled = 0x1
	// Position of TR8 field.
	EXTI_FTSR1_TR8_Pos = 0x8
	// Bit mask of TR8 field.
	EXTI_FTSR1_TR8_Msk = 0x100
	// Bit TR8.
	EXTI_FTSR1_TR8 = 0x100
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR8_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR8_Enabled = 0x1
	// Position of TR9 field.
	EXTI_FTSR1_TR9_Pos = 0x9
	// Bit mask of TR9 field.
	EXTI_FTSR1_TR9_Msk = 0x200
	// Bit TR9.
	EXTI_FTSR1_TR9 = 0x200
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR9_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR9_Enabled = 0x1
	// Position of TR10 field.
	EXTI_FTSR1_TR10_Pos = 0xa
	// Bit mask of TR10 field.
	EXTI_FTSR1_TR10_Msk = 0x400
	// Bit TR10.
	EXTI_FTSR1_TR10 = 0x400
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR10_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR10_Enabled = 0x1
	// Position of TR11 field.
	EXTI_FTSR1_TR11_Pos = 0xb
	// Bit mask of TR11 field.
	EXTI_FTSR1_TR11_Msk = 0x800
	// Bit TR11.
	EXTI_FTSR1_TR11 = 0x800
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR11_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR11_Enabled = 0x1
	// Position of TR12 field.
	EXTI_FTSR1_TR12_Pos = 0xc
	// Bit mask of TR12 field.
	EXTI_FTSR1_TR12_Msk = 0x1000
	// Bit TR12.
	EXTI_FTSR1_TR12 = 0x1000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR12_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR12_Enabled = 0x1
	// Position of TR13 field.
	EXTI_FTSR1_TR13_Pos = 0xd
	// Bit mask of TR13 field.
	EXTI_FTSR1_TR13_Msk = 0x2000
	// Bit TR13.
	EXTI_FTSR1_TR13 = 0x2000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR13_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR13_Enabled = 0x1
	// Position of TR14 field.
	EXTI_FTSR1_TR14_Pos = 0xe
	// Bit mask of TR14 field.
	EXTI_FTSR1_TR14_Msk = 0x4000
	// Bit TR14.
	EXTI_FTSR1_TR14 = 0x4000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR14_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR14_Enabled = 0x1
	// Position of TR15 field.
	EXTI_FTSR1_TR15_Pos = 0xf
	// Bit mask of TR15 field.
	EXTI_FTSR1_TR15_Msk = 0x8000
	// Bit TR15.
	EXTI_FTSR1_TR15 = 0x8000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR15_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR15_Enabled = 0x1
	// Position of TR16 field.
	EXTI_FTSR1_TR16_Pos = 0x10
	// Bit mask of TR16 field.
	EXTI_FTSR1_TR16_Msk = 0x10000
	// Bit TR16.
	EXTI_FTSR1_TR16 = 0x10000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR16_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR16_Enabled = 0x1
	// Position of TR17 field.
	EXTI_FTSR1_TR17_Pos = 0x11
	// Bit mask of TR17 field.
	EXTI_FTSR1_TR17_Msk = 0x20000
	// Bit TR17.
	EXTI_FTSR1_TR17 = 0x20000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR17_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR17_Enabled = 0x1
	// Position of TR18 field.
	EXTI_FTSR1_TR18_Pos = 0x12
	// Bit mask of TR18 field.
	EXTI_FTSR1_TR18_Msk = 0x40000
	// Bit TR18.
	EXTI_FTSR1_TR18 = 0x40000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR18_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR18_Enabled = 0x1
	// Position of TR19 field.
	EXTI_FTSR1_TR19_Pos = 0x13
	// Bit mask of TR19 field.
	EXTI_FTSR1_TR19_Msk = 0x80000
	// Bit TR19.
	EXTI_FTSR1_TR19 = 0x80000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR19_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR19_Enabled = 0x1
	// Position of TR20 field.
	EXTI_FTSR1_TR20_Pos = 0x14
	// Bit mask of TR20 field.
	EXTI_FTSR1_TR20_Msk = 0x100000
	// Bit TR20.
	EXTI_FTSR1_TR20 = 0x100000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR20_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR20_Enabled = 0x1
	// Position of TR21 field.
	EXTI_FTSR1_TR21_Pos = 0x15
	// Bit mask of TR21 field.
	EXTI_FTSR1_TR21_Msk = 0x200000
	// Bit TR21.
	EXTI_FTSR1_TR21 = 0x200000
	// Falling edge trigger is disabled
	EXTI_FTSR1_TR21_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_TR21_Enabled = 0x1

	// SWIER1: EXTI software interrupt event register
	// Position of SWIER0 field.
	EXTI_SWIER1_SWIER0_Pos = 0x0
	// Bit mask of SWIER0 field.
	EXTI_SWIER1_SWIER0_Msk = 0x1
	// Bit SWIER0.
	EXTI_SWIER1_SWIER0 = 0x1
	// Generates an interrupt request
	EXTI_SWIER1_SWIER0_Pend = 0x1
	// Position of SWIER1 field.
	EXTI_SWIER1_SWIER1_Pos = 0x1
	// Bit mask of SWIER1 field.
	EXTI_SWIER1_SWIER1_Msk = 0x2
	// Bit SWIER1.
	EXTI_SWIER1_SWIER1 = 0x2
	// Generates an interrupt request
	EXTI_SWIER1_SWIER1_Pend = 0x1
	// Position of SWIER2 field.
	EXTI_SWIER1_SWIER2_Pos = 0x2
	// Bit mask of SWIER2 field.
	EXTI_SWIER1_SWIER2_Msk = 0x4
	// Bit SWIER2.
	EXTI_SWIER1_SWIER2 = 0x4
	// Generates an interrupt request
	EXTI_SWIER1_SWIER2_Pend = 0x1
	// Position of SWIER3 field.
	EXTI_SWIER1_SWIER3_Pos = 0x3
	// Bit mask of SWIER3 field.
	EXTI_SWIER1_SWIER3_Msk = 0x8
	// Bit SWIER3.
	EXTI_SWIER1_SWIER3 = 0x8
	// Generates an interrupt request
	EXTI_SWIER1_SWIER3_Pend = 0x1
	// Position of SWIER4 field.
	EXTI_SWIER1_SWIER4_Pos = 0x4
	// Bit mask of SWIER4 field.
	EXTI_SWIER1_SWIER4_Msk = 0x10
	// Bit SWIER4.
	EXTI_SWIER1_SWIER4 = 0x10
	// Generates an interrupt request
	EXTI_SWIER1_SWIER4_Pend = 0x1
	// Position of SWIER5 field.
	EXTI_SWIER1_SWIER5_Pos = 0x5
	// Bit mask of SWIER5 field.
	EXTI_SWIER1_SWIER5_Msk = 0x20
	// Bit SWIER5.
	EXTI_SWIER1_SWIER5 = 0x20
	// Generates an interrupt request
	EXTI_SWIER1_SWIER5_Pend = 0x1
	// Position of SWIER6 field.
	EXTI_SWIER1_SWIER6_Pos = 0x6
	// Bit mask of SWIER6 field.
	EXTI_SWIER1_SWIER6_Msk = 0x40
	// Bit SWIER6.
	EXTI_SWIER1_SWIER6 = 0x40
	// Generates an interrupt request
	EXTI_SWIER1_SWIER6_Pend = 0x1
	// Position of SWIER7 field.
	EXTI_SWIER1_SWIER7_Pos = 0x7
	// Bit mask of SWIER7 field.
	EXTI_SWIER1_SWIER7_Msk = 0x80
	// Bit SWIER7.
	EXTI_SWIER1_SWIER7 = 0x80
	// Generates an interrupt request
	EXTI_SWIER1_SWIER7_Pend = 0x1
	// Position of SWIER8 field.
	EXTI_SWIER1_SWIER8_Pos = 0x8
	// Bit mask of SWIER8 field.
	EXTI_SWIER1_SWIER8_Msk = 0x100
	// Bit SWIER8.
	EXTI_SWIER1_SWIER8 = 0x100
	// Generates an interrupt request
	EXTI_SWIER1_SWIER8_Pend = 0x1
	// Position of SWIER9 field.
	EXTI_SWIER1_SWIER9_Pos = 0x9
	// Bit mask of SWIER9 field.
	EXTI_SWIER1_SWIER9_Msk = 0x200
	// Bit SWIER9.
	EXTI_SWIER1_SWIER9 = 0x200
	// Generates an interrupt request
	EXTI_SWIER1_SWIER9_Pend = 0x1
	// Position of SWIER10 field.
	EXTI_SWIER1_SWIER10_Pos = 0xa
	// Bit mask of SWIER10 field.
	EXTI_SWIER1_SWIER10_Msk = 0x400
	// Bit SWIER10.
	EXTI_SWIER1_SWIER10 = 0x400
	// Generates an interrupt request
	EXTI_SWIER1_SWIER10_Pend = 0x1
	// Position of SWIER11 field.
	EXTI_SWIER1_SWIER11_Pos = 0xb
	// Bit mask of SWIER11 field.
	EXTI_SWIER1_SWIER11_Msk = 0x800
	// Bit SWIER11.
	EXTI_SWIER1_SWIER11 = 0x800
	// Generates an interrupt request
	EXTI_SWIER1_SWIER11_Pend = 0x1
	// Position of SWIER12 field.
	EXTI_SWIER1_SWIER12_Pos = 0xc
	// Bit mask of SWIER12 field.
	EXTI_SWIER1_SWIER12_Msk = 0x1000
	// Bit SWIER12.
	EXTI_SWIER1_SWIER12 = 0x1000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER12_Pend = 0x1
	// Position of SWIER13 field.
	EXTI_SWIER1_SWIER13_Pos = 0xd
	// Bit mask of SWIER13 field.
	EXTI_SWIER1_SWIER13_Msk = 0x2000
	// Bit SWIER13.
	EXTI_SWIER1_SWIER13 = 0x2000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER13_Pend = 0x1
	// Position of SWIER14 field.
	EXTI_SWIER1_SWIER14_Pos = 0xe
	// Bit mask of SWIER14 field.
	EXTI_SWIER1_SWIER14_Msk = 0x4000
	// Bit SWIER14.
	EXTI_SWIER1_SWIER14 = 0x4000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER14_Pend = 0x1
	// Position of SWIER15 field.
	EXTI_SWIER1_SWIER15_Pos = 0xf
	// Bit mask of SWIER15 field.
	EXTI_SWIER1_SWIER15_Msk = 0x8000
	// Bit SWIER15.
	EXTI_SWIER1_SWIER15 = 0x8000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER15_Pend = 0x1
	// Position of SWIER16 field.
	EXTI_SWIER1_SWIER16_Pos = 0x10
	// Bit mask of SWIER16 field.
	EXTI_SWIER1_SWIER16_Msk = 0x10000
	// Bit SWIER16.
	EXTI_SWIER1_SWIER16 = 0x10000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER16_Pend = 0x1
	// Position of SWIER17 field.
	EXTI_SWIER1_SWIER17_Pos = 0x11
	// Bit mask of SWIER17 field.
	EXTI_SWIER1_SWIER17_Msk = 0x20000
	// Bit SWIER17.
	EXTI_SWIER1_SWIER17 = 0x20000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER17_Pend = 0x1
	// Position of SWIER18 field.
	EXTI_SWIER1_SWIER18_Pos = 0x12
	// Bit mask of SWIER18 field.
	EXTI_SWIER1_SWIER18_Msk = 0x40000
	// Bit SWIER18.
	EXTI_SWIER1_SWIER18 = 0x40000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER18_Pend = 0x1
	// Position of SWIER19 field.
	EXTI_SWIER1_SWIER19_Pos = 0x13
	// Bit mask of SWIER19 field.
	EXTI_SWIER1_SWIER19_Msk = 0x80000
	// Bit SWIER19.
	EXTI_SWIER1_SWIER19 = 0x80000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER19_Pend = 0x1
	// Position of SWIER20 field.
	EXTI_SWIER1_SWIER20_Pos = 0x14
	// Bit mask of SWIER20 field.
	EXTI_SWIER1_SWIER20_Msk = 0x100000
	// Bit SWIER20.
	EXTI_SWIER1_SWIER20 = 0x100000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER20_Pend = 0x1
	// Position of SWIER21 field.
	EXTI_SWIER1_SWIER21_Pos = 0x15
	// Bit mask of SWIER21 field.
	EXTI_SWIER1_SWIER21_Msk = 0x200000
	// Bit SWIER21.
	EXTI_SWIER1_SWIER21 = 0x200000
	// Generates an interrupt request
	EXTI_SWIER1_SWIER21_Pend = 0x1

	// D3PMR1: EXTI D3 pending mask register
	// Position of MR0 field.
	EXTI_D3PMR1_MR0_Pos = 0x0
	// Bit mask of MR0 field.
	EXTI_D3PMR1_MR0_Msk = 0x1
	// Bit MR0.
	EXTI_D3PMR1_MR0 = 0x1
	// Interrupt request line is masked
	EXTI_D3PMR1_MR0_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR0_Unmasked = 0x1
	// Position of MR1 field.
	EXTI_D3PMR1_MR1_Pos = 0x1
	// Bit mask of MR1 field.
	EXTI_D3PMR1_MR1_Msk = 0x2
	// Bit MR1.
	EXTI_D3PMR1_MR1 = 0x2
	// Interrupt request line is masked
	EXTI_D3PMR1_MR1_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR1_Unmasked = 0x1
	// Position of MR2 field.
	EXTI_D3PMR1_MR2_Pos = 0x2
	// Bit mask of MR2 field.
	EXTI_D3PMR1_MR2_Msk = 0x4
	// Bit MR2.
	EXTI_D3PMR1_MR2 = 0x4
	// Interrupt request line is masked
	EXTI_D3PMR1_MR2_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR2_Unmasked = 0x1
	// Position of MR3 field.
	EXTI_D3PMR1_MR3_Pos = 0x3
	// Bit mask of MR3 field.
	EXTI_D3PMR1_MR3_Msk = 0x8
	// Bit MR3.
	EXTI_D3PMR1_MR3 = 0x8
	// Interrupt request line is masked
	EXTI_D3PMR1_MR3_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR3_Unmasked = 0x1
	// Position of MR4 field.
	EXTI_D3PMR1_MR4_Pos = 0x4
	// Bit mask of MR4 field.
	EXTI_D3PMR1_MR4_Msk = 0x10
	// Bit MR4.
	EXTI_D3PMR1_MR4 = 0x10
	// Interrupt request line is masked
	EXTI_D3PMR1_MR4_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR4_Unmasked = 0x1
	// Position of MR5 field.
	EXTI_D3PMR1_MR5_Pos = 0x5
	// Bit mask of MR5 field.
	EXTI_D3PMR1_MR5_Msk = 0x20
	// Bit MR5.
	EXTI_D3PMR1_MR5 = 0x20
	// Interrupt request line is masked
	EXTI_D3PMR1_MR5_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR5_Unmasked = 0x1
	// Position of MR6 field.
	EXTI_D3PMR1_MR6_Pos = 0x6
	// Bit mask of MR6 field.
	EXTI_D3PMR1_MR6_Msk = 0x40
	// Bit MR6.
	EXTI_D3PMR1_MR6 = 0x40
	// Interrupt request line is masked
	EXTI_D3PMR1_MR6_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR6_Unmasked = 0x1
	// Position of MR7 field.
	EXTI_D3PMR1_MR7_Pos = 0x7
	// Bit mask of MR7 field.
	EXTI_D3PMR1_MR7_Msk = 0x80
	// Bit MR7.
	EXTI_D3PMR1_MR7 = 0x80
	// Interrupt request line is masked
	EXTI_D3PMR1_MR7_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR7_Unmasked = 0x1
	// Position of MR8 field.
	EXTI_D3PMR1_MR8_Pos = 0x8
	// Bit mask of MR8 field.
	EXTI_D3PMR1_MR8_Msk = 0x100
	// Bit MR8.
	EXTI_D3PMR1_MR8 = 0x100
	// Interrupt request line is masked
	EXTI_D3PMR1_MR8_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR8_Unmasked = 0x1
	// Position of MR9 field.
	EXTI_D3PMR1_MR9_Pos = 0x9
	// Bit mask of MR9 field.
	EXTI_D3PMR1_MR9_Msk = 0x200
	// Bit MR9.
	EXTI_D3PMR1_MR9 = 0x200
	// Interrupt request line is masked
	EXTI_D3PMR1_MR9_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR9_Unmasked = 0x1
	// Position of MR10 field.
	EXTI_D3PMR1_MR10_Pos = 0xa
	// Bit mask of MR10 field.
	EXTI_D3PMR1_MR10_Msk = 0x400
	// Bit MR10.
	EXTI_D3PMR1_MR10 = 0x400
	// Interrupt request line is masked
	EXTI_D3PMR1_MR10_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR10_Unmasked = 0x1
	// Position of MR11 field.
	EXTI_D3PMR1_MR11_Pos = 0xb
	// Bit mask of MR11 field.
	EXTI_D3PMR1_MR11_Msk = 0x800
	// Bit MR11.
	EXTI_D3PMR1_MR11 = 0x800
	// Interrupt request line is masked
	EXTI_D3PMR1_MR11_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR11_Unmasked = 0x1
	// Position of MR12 field.
	EXTI_D3PMR1_MR12_Pos = 0xc
	// Bit mask of MR12 field.
	EXTI_D3PMR1_MR12_Msk = 0x1000
	// Bit MR12.
	EXTI_D3PMR1_MR12 = 0x1000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR12_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR12_Unmasked = 0x1
	// Position of MR13 field.
	EXTI_D3PMR1_MR13_Pos = 0xd
	// Bit mask of MR13 field.
	EXTI_D3PMR1_MR13_Msk = 0x2000
	// Bit MR13.
	EXTI_D3PMR1_MR13 = 0x2000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR13_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR13_Unmasked = 0x1
	// Position of MR14 field.
	EXTI_D3PMR1_MR14_Pos = 0xe
	// Bit mask of MR14 field.
	EXTI_D3PMR1_MR14_Msk = 0x4000
	// Bit MR14.
	EXTI_D3PMR1_MR14 = 0x4000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR14_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR14_Unmasked = 0x1
	// Position of MR15 field.
	EXTI_D3PMR1_MR15_Pos = 0xf
	// Bit mask of MR15 field.
	EXTI_D3PMR1_MR15_Msk = 0x8000
	// Bit MR15.
	EXTI_D3PMR1_MR15 = 0x8000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR15_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR15_Unmasked = 0x1
	// Position of MR19 field.
	EXTI_D3PMR1_MR19_Pos = 0x13
	// Bit mask of MR19 field.
	EXTI_D3PMR1_MR19_Msk = 0x80000
	// Bit MR19.
	EXTI_D3PMR1_MR19 = 0x80000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR19_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR19_Unmasked = 0x1
	// Position of MR20 field.
	EXTI_D3PMR1_MR20_Pos = 0x14
	// Bit mask of MR20 field.
	EXTI_D3PMR1_MR20_Msk = 0x100000
	// Bit MR20.
	EXTI_D3PMR1_MR20 = 0x100000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR20_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR20_Unmasked = 0x1
	// Position of MR21 field.
	EXTI_D3PMR1_MR21_Pos = 0x15
	// Bit mask of MR21 field.
	EXTI_D3PMR1_MR21_Msk = 0x200000
	// Bit MR21.
	EXTI_D3PMR1_MR21 = 0x200000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR21_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR21_Unmasked = 0x1
	// Position of MR25 field.
	EXTI_D3PMR1_MR25_Pos = 0x19
	// Bit mask of MR25 field.
	EXTI_D3PMR1_MR25_Msk = 0x2000000
	// Bit MR25.
	EXTI_D3PMR1_MR25 = 0x2000000
	// Interrupt request line is masked
	EXTI_D3PMR1_MR25_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR1_MR25_Unmasked = 0x1

	// D3PCR1L: EXTI D3 pending clear selection register low
	// Position of PCS0 field.
	EXTI_D3PCR1L_PCS0_Pos = 0x0
	// Bit mask of PCS0 field.
	EXTI_D3PCR1L_PCS0_Msk = 0x3
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS0_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS0_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS0_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS0_LPTIM5 = 0x3
	// Position of PCS1 field.
	EXTI_D3PCR1L_PCS1_Pos = 0x2
	// Bit mask of PCS1 field.
	EXTI_D3PCR1L_PCS1_Msk = 0xc
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS1_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS1_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS1_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS1_LPTIM5 = 0x3
	// Position of PCS2 field.
	EXTI_D3PCR1L_PCS2_Pos = 0x4
	// Bit mask of PCS2 field.
	EXTI_D3PCR1L_PCS2_Msk = 0x30
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS2_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS2_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS2_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS2_LPTIM5 = 0x3
	// Position of PCS3 field.
	EXTI_D3PCR1L_PCS3_Pos = 0x6
	// Bit mask of PCS3 field.
	EXTI_D3PCR1L_PCS3_Msk = 0xc0
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS3_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS3_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS3_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS3_LPTIM5 = 0x3
	// Position of PCS4 field.
	EXTI_D3PCR1L_PCS4_Pos = 0x8
	// Bit mask of PCS4 field.
	EXTI_D3PCR1L_PCS4_Msk = 0x300
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS4_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS4_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS4_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS4_LPTIM5 = 0x3
	// Position of PCS5 field.
	EXTI_D3PCR1L_PCS5_Pos = 0xa
	// Bit mask of PCS5 field.
	EXTI_D3PCR1L_PCS5_Msk = 0xc00
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS5_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS5_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS5_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS5_LPTIM5 = 0x3
	// Position of PCS6 field.
	EXTI_D3PCR1L_PCS6_Pos = 0xc
	// Bit mask of PCS6 field.
	EXTI_D3PCR1L_PCS6_Msk = 0x3000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS6_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS6_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS6_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS6_LPTIM5 = 0x3
	// Position of PCS7 field.
	EXTI_D3PCR1L_PCS7_Pos = 0xe
	// Bit mask of PCS7 field.
	EXTI_D3PCR1L_PCS7_Msk = 0xc000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS7_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS7_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS7_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS7_LPTIM5 = 0x3
	// Position of PCS8 field.
	EXTI_D3PCR1L_PCS8_Pos = 0x10
	// Bit mask of PCS8 field.
	EXTI_D3PCR1L_PCS8_Msk = 0x30000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS8_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS8_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS8_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS8_LPTIM5 = 0x3
	// Position of PCS9 field.
	EXTI_D3PCR1L_PCS9_Pos = 0x12
	// Bit mask of PCS9 field.
	EXTI_D3PCR1L_PCS9_Msk = 0xc0000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS9_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS9_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS9_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS9_LPTIM5 = 0x3
	// Position of PCS10 field.
	EXTI_D3PCR1L_PCS10_Pos = 0x14
	// Bit mask of PCS10 field.
	EXTI_D3PCR1L_PCS10_Msk = 0x300000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS10_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS10_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS10_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS10_LPTIM5 = 0x3
	// Position of PCS11 field.
	EXTI_D3PCR1L_PCS11_Pos = 0x16
	// Bit mask of PCS11 field.
	EXTI_D3PCR1L_PCS11_Msk = 0xc00000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS11_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS11_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS11_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS11_LPTIM5 = 0x3
	// Position of PCS12 field.
	EXTI_D3PCR1L_PCS12_Pos = 0x18
	// Bit mask of PCS12 field.
	EXTI_D3PCR1L_PCS12_Msk = 0x3000000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS12_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS12_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS12_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS12_LPTIM5 = 0x3
	// Position of PCS13 field.
	EXTI_D3PCR1L_PCS13_Pos = 0x1a
	// Bit mask of PCS13 field.
	EXTI_D3PCR1L_PCS13_Msk = 0xc000000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS13_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS13_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS13_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS13_LPTIM5 = 0x3
	// Position of PCS14 field.
	EXTI_D3PCR1L_PCS14_Pos = 0x1c
	// Bit mask of PCS14 field.
	EXTI_D3PCR1L_PCS14_Msk = 0x30000000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS14_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS14_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS14_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS14_LPTIM5 = 0x3
	// Position of PCS15 field.
	EXTI_D3PCR1L_PCS15_Pos = 0x1e
	// Bit mask of PCS15 field.
	EXTI_D3PCR1L_PCS15_Msk = 0xc0000000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS15_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS15_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS15_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1L_PCS15_LPTIM5 = 0x3

	// D3PCR1H: EXTI D3 pending clear selection register high
	// Position of PCS19 field.
	EXTI_D3PCR1H_PCS19_Pos = 0x6
	// Bit mask of PCS19 field.
	EXTI_D3PCR1H_PCS19_Msk = 0xc0
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS19_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS19_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS19_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS19_LPTIM5 = 0x3
	// Position of PCS20 field.
	EXTI_D3PCR1H_PCS20_Pos = 0x8
	// Bit mask of PCS20 field.
	EXTI_D3PCR1H_PCS20_Msk = 0x300
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS20_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS20_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS20_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS20_LPTIM5 = 0x3
	// Position of PCS21 field.
	EXTI_D3PCR1H_PCS21_Pos = 0xa
	// Bit mask of PCS21 field.
	EXTI_D3PCR1H_PCS21_Msk = 0xc00
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS21_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS21_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS21_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS21_LPTIM5 = 0x3
	// Position of PCS25 field.
	EXTI_D3PCR1H_PCS25_Pos = 0x12
	// Bit mask of PCS25 field.
	EXTI_D3PCR1H_PCS25_Msk = 0xc0000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS25_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS25_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS25_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR1H_PCS25_LPTIM5 = 0x3

	// RTSR2: EXTI rising trigger selection register
	// Position of TR49 field.
	EXTI_RTSR2_TR49_Pos = 0x11
	// Bit mask of TR49 field.
	EXTI_RTSR2_TR49_Msk = 0x20000
	// Bit TR49.
	EXTI_RTSR2_TR49 = 0x20000
	// Rising edge trigger is disabled
	EXTI_RTSR2_TR49_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR2_TR49_Enabled = 0x1
	// Position of TR51 field.
	EXTI_RTSR2_TR51_Pos = 0x13
	// Bit mask of TR51 field.
	EXTI_RTSR2_TR51_Msk = 0x80000
	// Bit TR51.
	EXTI_RTSR2_TR51 = 0x80000
	// Rising edge trigger is disabled
	EXTI_RTSR2_TR51_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR2_TR51_Enabled = 0x1

	// FTSR2: EXTI falling trigger selection register
	// Position of TR49 field.
	EXTI_FTSR2_TR49_Pos = 0x11
	// Bit mask of TR49 field.
	EXTI_FTSR2_TR49_Msk = 0x20000
	// Bit TR49.
	EXTI_FTSR2_TR49 = 0x20000
	// Falling edge trigger is disabled
	EXTI_FTSR2_TR49_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR2_TR49_Enabled = 0x1
	// Position of TR51 field.
	EXTI_FTSR2_TR51_Pos = 0x13
	// Bit mask of TR51 field.
	EXTI_FTSR2_TR51_Msk = 0x80000
	// Bit TR51.
	EXTI_FTSR2_TR51 = 0x80000
	// Falling edge trigger is disabled
	EXTI_FTSR2_TR51_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR2_TR51_Enabled = 0x1

	// SWIER2: EXTI software interrupt event register
	// Position of SWIER49 field.
	EXTI_SWIER2_SWIER49_Pos = 0x11
	// Bit mask of SWIER49 field.
	EXTI_SWIER2_SWIER49_Msk = 0x20000
	// Bit SWIER49.
	EXTI_SWIER2_SWIER49 = 0x20000
	// Generates an interrupt request
	EXTI_SWIER2_SWIER49_Pend = 0x1
	// Position of SWIER51 field.
	EXTI_SWIER2_SWIER51_Pos = 0x13
	// Bit mask of SWIER51 field.
	EXTI_SWIER2_SWIER51_Msk = 0x80000
	// Bit SWIER51.
	EXTI_SWIER2_SWIER51 = 0x80000
	// Generates an interrupt request
	EXTI_SWIER2_SWIER51_Pend = 0x1

	// D3PMR2: EXTI D3 pending mask register
	// Position of MR34 field.
	EXTI_D3PMR2_MR34_Pos = 0x2
	// Bit mask of MR34 field.
	EXTI_D3PMR2_MR34_Msk = 0x4
	// Bit MR34.
	EXTI_D3PMR2_MR34 = 0x4
	// Interrupt request line is masked
	EXTI_D3PMR2_MR34_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR34_Unmasked = 0x1
	// Position of MR35 field.
	EXTI_D3PMR2_MR35_Pos = 0x3
	// Bit mask of MR35 field.
	EXTI_D3PMR2_MR35_Msk = 0x8
	// Bit MR35.
	EXTI_D3PMR2_MR35 = 0x8
	// Interrupt request line is masked
	EXTI_D3PMR2_MR35_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR35_Unmasked = 0x1
	// Position of MR41 field.
	EXTI_D3PMR2_MR41_Pos = 0x9
	// Bit mask of MR41 field.
	EXTI_D3PMR2_MR41_Msk = 0x200
	// Bit MR41.
	EXTI_D3PMR2_MR41 = 0x200
	// Interrupt request line is masked
	EXTI_D3PMR2_MR41_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR41_Unmasked = 0x1
	// Position of MR48 field.
	EXTI_D3PMR2_MR48_Pos = 0x10
	// Bit mask of MR48 field.
	EXTI_D3PMR2_MR48_Msk = 0x10000
	// Bit MR48.
	EXTI_D3PMR2_MR48 = 0x10000
	// Interrupt request line is masked
	EXTI_D3PMR2_MR48_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR48_Unmasked = 0x1
	// Position of MR49 field.
	EXTI_D3PMR2_MR49_Pos = 0x11
	// Bit mask of MR49 field.
	EXTI_D3PMR2_MR49_Msk = 0x20000
	// Bit MR49.
	EXTI_D3PMR2_MR49 = 0x20000
	// Interrupt request line is masked
	EXTI_D3PMR2_MR49_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR49_Unmasked = 0x1
	// Position of MR50 field.
	EXTI_D3PMR2_MR50_Pos = 0x12
	// Bit mask of MR50 field.
	EXTI_D3PMR2_MR50_Msk = 0x40000
	// Bit MR50.
	EXTI_D3PMR2_MR50 = 0x40000
	// Interrupt request line is masked
	EXTI_D3PMR2_MR50_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR50_Unmasked = 0x1
	// Position of MR51 field.
	EXTI_D3PMR2_MR51_Pos = 0x13
	// Bit mask of MR51 field.
	EXTI_D3PMR2_MR51_Msk = 0x80000
	// Bit MR51.
	EXTI_D3PMR2_MR51 = 0x80000
	// Interrupt request line is masked
	EXTI_D3PMR2_MR51_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR51_Unmasked = 0x1
	// Position of MR52 field.
	EXTI_D3PMR2_MR52_Pos = 0x14
	// Bit mask of MR52 field.
	EXTI_D3PMR2_MR52_Msk = 0x100000
	// Bit MR52.
	EXTI_D3PMR2_MR52 = 0x100000
	// Interrupt request line is masked
	EXTI_D3PMR2_MR52_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR52_Unmasked = 0x1
	// Position of MR53 field.
	EXTI_D3PMR2_MR53_Pos = 0x15
	// Bit mask of MR53 field.
	EXTI_D3PMR2_MR53_Msk = 0x200000
	// Bit MR53.
	EXTI_D3PMR2_MR53 = 0x200000
	// Interrupt request line is masked
	EXTI_D3PMR2_MR53_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR2_MR53_Unmasked = 0x1

	// D3PCR2L: EXTI D3 pending clear selection register low
	// Position of PCS35 field.
	EXTI_D3PCR2L_PCS35_Pos = 0x6
	// Bit mask of PCS35 field.
	EXTI_D3PCR2L_PCS35_Msk = 0xc0
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS35_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS35_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS35_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS35_LPTIM5 = 0x3
	// Position of PCS34 field.
	EXTI_D3PCR2L_PCS34_Pos = 0x4
	// Bit mask of PCS34 field.
	EXTI_D3PCR2L_PCS34_Msk = 0x30
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS34_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS34_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS34_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS34_LPTIM5 = 0x3
	// Position of PCS41 field.
	EXTI_D3PCR2L_PCS41_Pos = 0x12
	// Bit mask of PCS41 field.
	EXTI_D3PCR2L_PCS41_Msk = 0xc0000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS41_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS41_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS41_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2L_PCS41_LPTIM5 = 0x3

	// D3PCR2H: EXTI D3 pending clear selection register high
	// Position of PCS48 field.
	EXTI_D3PCR2H_PCS48_Pos = 0x0
	// Bit mask of PCS48 field.
	EXTI_D3PCR2H_PCS48_Msk = 0x3
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS48_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS48_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS48_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS48_LPTIM5 = 0x3
	// Position of PCS49 field.
	EXTI_D3PCR2H_PCS49_Pos = 0x2
	// Bit mask of PCS49 field.
	EXTI_D3PCR2H_PCS49_Msk = 0xc
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS49_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS49_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS49_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS49_LPTIM5 = 0x3
	// Position of PCS50 field.
	EXTI_D3PCR2H_PCS50_Pos = 0x4
	// Bit mask of PCS50 field.
	EXTI_D3PCR2H_PCS50_Msk = 0x30
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS50_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS50_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS50_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS50_LPTIM5 = 0x3
	// Position of PCS51 field.
	EXTI_D3PCR2H_PCS51_Pos = 0x6
	// Bit mask of PCS51 field.
	EXTI_D3PCR2H_PCS51_Msk = 0xc0
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS51_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS51_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS51_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS51_LPTIM5 = 0x3
	// Position of PCS52 field.
	EXTI_D3PCR2H_PCS52_Pos = 0x8
	// Bit mask of PCS52 field.
	EXTI_D3PCR2H_PCS52_Msk = 0x300
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS52_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS52_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS52_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS52_LPTIM5 = 0x3
	// Position of PCS53 field.
	EXTI_D3PCR2H_PCS53_Pos = 0xa
	// Bit mask of PCS53 field.
	EXTI_D3PCR2H_PCS53_Msk = 0xc00
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS53_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS53_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS53_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR2H_PCS53_LPTIM5 = 0x3

	// RTSR3: EXTI rising trigger selection register
	// Position of TR82 field.
	EXTI_RTSR3_TR82_Pos = 0x12
	// Bit mask of TR82 field.
	EXTI_RTSR3_TR82_Msk = 0x40000
	// Bit TR82.
	EXTI_RTSR3_TR82 = 0x40000
	// Rising edge trigger is disabled
	EXTI_RTSR3_TR82_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR3_TR82_Enabled = 0x1
	// Position of TR84 field.
	EXTI_RTSR3_TR84_Pos = 0x14
	// Bit mask of TR84 field.
	EXTI_RTSR3_TR84_Msk = 0x100000
	// Bit TR84.
	EXTI_RTSR3_TR84 = 0x100000
	// Rising edge trigger is disabled
	EXTI_RTSR3_TR84_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR3_TR84_Enabled = 0x1
	// Position of TR85 field.
	EXTI_RTSR3_TR85_Pos = 0x15
	// Bit mask of TR85 field.
	EXTI_RTSR3_TR85_Msk = 0x200000
	// Bit TR85.
	EXTI_RTSR3_TR85 = 0x200000
	// Rising edge trigger is disabled
	EXTI_RTSR3_TR85_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR3_TR85_Enabled = 0x1
	// Position of TR86 field.
	EXTI_RTSR3_TR86_Pos = 0x16
	// Bit mask of TR86 field.
	EXTI_RTSR3_TR86_Msk = 0x400000
	// Bit TR86.
	EXTI_RTSR3_TR86 = 0x400000
	// Rising edge trigger is disabled
	EXTI_RTSR3_TR86_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR3_TR86_Enabled = 0x1

	// FTSR3: EXTI falling trigger selection register
	// Position of TR82 field.
	EXTI_FTSR3_TR82_Pos = 0x12
	// Bit mask of TR82 field.
	EXTI_FTSR3_TR82_Msk = 0x40000
	// Bit TR82.
	EXTI_FTSR3_TR82 = 0x40000
	// Falling edge trigger is disabled
	EXTI_FTSR3_TR82_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR3_TR82_Enabled = 0x1
	// Position of TR84 field.
	EXTI_FTSR3_TR84_Pos = 0x14
	// Bit mask of TR84 field.
	EXTI_FTSR3_TR84_Msk = 0x100000
	// Bit TR84.
	EXTI_FTSR3_TR84 = 0x100000
	// Falling edge trigger is disabled
	EXTI_FTSR3_TR84_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR3_TR84_Enabled = 0x1
	// Position of TR85 field.
	EXTI_FTSR3_TR85_Pos = 0x15
	// Bit mask of TR85 field.
	EXTI_FTSR3_TR85_Msk = 0x200000
	// Bit TR85.
	EXTI_FTSR3_TR85 = 0x200000
	// Falling edge trigger is disabled
	EXTI_FTSR3_TR85_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR3_TR85_Enabled = 0x1
	// Position of TR86 field.
	EXTI_FTSR3_TR86_Pos = 0x16
	// Bit mask of TR86 field.
	EXTI_FTSR3_TR86_Msk = 0x400000
	// Bit TR86.
	EXTI_FTSR3_TR86 = 0x400000
	// Falling edge trigger is disabled
	EXTI_FTSR3_TR86_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR3_TR86_Enabled = 0x1

	// SWIER3: EXTI software interrupt event register
	// Position of SWIER82 field.
	EXTI_SWIER3_SWIER82_Pos = 0x12
	// Bit mask of SWIER82 field.
	EXTI_SWIER3_SWIER82_Msk = 0x40000
	// Bit SWIER82.
	EXTI_SWIER3_SWIER82 = 0x40000
	// Generates an interrupt request
	EXTI_SWIER3_SWIER82_Pend = 0x1
	// Position of SWIER84 field.
	EXTI_SWIER3_SWIER84_Pos = 0x14
	// Bit mask of SWIER84 field.
	EXTI_SWIER3_SWIER84_Msk = 0x100000
	// Bit SWIER84.
	EXTI_SWIER3_SWIER84 = 0x100000
	// Generates an interrupt request
	EXTI_SWIER3_SWIER84_Pend = 0x1
	// Position of SWIER85 field.
	EXTI_SWIER3_SWIER85_Pos = 0x15
	// Bit mask of SWIER85 field.
	EXTI_SWIER3_SWIER85_Msk = 0x200000
	// Bit SWIER85.
	EXTI_SWIER3_SWIER85 = 0x200000
	// Generates an interrupt request
	EXTI_SWIER3_SWIER85_Pend = 0x1
	// Position of SWIER86 field.
	EXTI_SWIER3_SWIER86_Pos = 0x16
	// Bit mask of SWIER86 field.
	EXTI_SWIER3_SWIER86_Msk = 0x400000
	// Bit SWIER86.
	EXTI_SWIER3_SWIER86 = 0x400000
	// Generates an interrupt request
	EXTI_SWIER3_SWIER86_Pend = 0x1

	// D3PMR3: EXTI D3 pending mask register
	// Position of MR88 field.
	EXTI_D3PMR3_MR88_Pos = 0x18
	// Bit mask of MR88 field.
	EXTI_D3PMR3_MR88_Msk = 0x1000000
	// Bit MR88.
	EXTI_D3PMR3_MR88 = 0x1000000
	// Interrupt request line is masked
	EXTI_D3PMR3_MR88_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_D3PMR3_MR88_Unmasked = 0x1

	// D3PCR3H: EXTI D3 pending clear selection register high
	// Position of PCS88 field.
	EXTI_D3PCR3H_PCS88_Pos = 0x12
	// Bit mask of PCS88 field.
	EXTI_D3PCR3H_PCS88_Msk = 0xc0000
	// DMA ch6 event selected as D3 domain pendclear source
	EXTI_D3PCR3H_PCS88_DMA_CH6 = 0x0
	// DMA ch7 event selected as D3 domain pendclear source
	EXTI_D3PCR3H_PCS88_DMA_CH7 = 0x1
	// LPTIM4 out selected as D3 domain pendclear source
	EXTI_D3PCR3H_PCS88_LPTIM4 = 0x2
	// LPTIM5 out selected as D3 domain pendclear source
	EXTI_D3PCR3H_PCS88_LPTIM5 = 0x3

	// CPUIMR1: EXTI interrupt mask register
	// Position of MR0 field.
	EXTI_CPUIMR1_MR0_Pos = 0x0
	// Bit mask of MR0 field.
	EXTI_CPUIMR1_MR0_Msk = 0x1
	// Bit MR0.
	EXTI_CPUIMR1_MR0 = 0x1
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR0_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR0_Unmasked = 0x1
	// Position of MR1 field.
	EXTI_CPUIMR1_MR1_Pos = 0x1
	// Bit mask of MR1 field.
	EXTI_CPUIMR1_MR1_Msk = 0x2
	// Bit MR1.
	EXTI_CPUIMR1_MR1 = 0x2
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR1_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR1_Unmasked = 0x1
	// Position of MR2 field.
	EXTI_CPUIMR1_MR2_Pos = 0x2
	// Bit mask of MR2 field.
	EXTI_CPUIMR1_MR2_Msk = 0x4
	// Bit MR2.
	EXTI_CPUIMR1_MR2 = 0x4
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR2_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR2_Unmasked = 0x1
	// Position of MR3 field.
	EXTI_CPUIMR1_MR3_Pos = 0x3
	// Bit mask of MR3 field.
	EXTI_CPUIMR1_MR3_Msk = 0x8
	// Bit MR3.
	EXTI_CPUIMR1_MR3 = 0x8
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR3_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR3_Unmasked = 0x1
	// Position of MR4 field.
	EXTI_CPUIMR1_MR4_Pos = 0x4
	// Bit mask of MR4 field.
	EXTI_CPUIMR1_MR4_Msk = 0x10
	// Bit MR4.
	EXTI_CPUIMR1_MR4 = 0x10
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR4_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR4_Unmasked = 0x1
	// Position of MR5 field.
	EXTI_CPUIMR1_MR5_Pos = 0x5
	// Bit mask of MR5 field.
	EXTI_CPUIMR1_MR5_Msk = 0x20
	// Bit MR5.
	EXTI_CPUIMR1_MR5 = 0x20
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR5_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR5_Unmasked = 0x1
	// Position of MR6 field.
	EXTI_CPUIMR1_MR6_Pos = 0x6
	// Bit mask of MR6 field.
	EXTI_CPUIMR1_MR6_Msk = 0x40
	// Bit MR6.
	EXTI_CPUIMR1_MR6 = 0x40
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR6_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR6_Unmasked = 0x1
	// Position of MR7 field.
	EXTI_CPUIMR1_MR7_Pos = 0x7
	// Bit mask of MR7 field.
	EXTI_CPUIMR1_MR7_Msk = 0x80
	// Bit MR7.
	EXTI_CPUIMR1_MR7 = 0x80
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR7_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR7_Unmasked = 0x1
	// Position of MR8 field.
	EXTI_CPUIMR1_MR8_Pos = 0x8
	// Bit mask of MR8 field.
	EXTI_CPUIMR1_MR8_Msk = 0x100
	// Bit MR8.
	EXTI_CPUIMR1_MR8 = 0x100
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR8_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR8_Unmasked = 0x1
	// Position of MR9 field.
	EXTI_CPUIMR1_MR9_Pos = 0x9
	// Bit mask of MR9 field.
	EXTI_CPUIMR1_MR9_Msk = 0x200
	// Bit MR9.
	EXTI_CPUIMR1_MR9 = 0x200
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR9_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR9_Unmasked = 0x1
	// Position of MR10 field.
	EXTI_CPUIMR1_MR10_Pos = 0xa
	// Bit mask of MR10 field.
	EXTI_CPUIMR1_MR10_Msk = 0x400
	// Bit MR10.
	EXTI_CPUIMR1_MR10 = 0x400
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR10_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR10_Unmasked = 0x1
	// Position of MR11 field.
	EXTI_CPUIMR1_MR11_Pos = 0xb
	// Bit mask of MR11 field.
	EXTI_CPUIMR1_MR11_Msk = 0x800
	// Bit MR11.
	EXTI_CPUIMR1_MR11 = 0x800
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR11_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR11_Unmasked = 0x1
	// Position of MR12 field.
	EXTI_CPUIMR1_MR12_Pos = 0xc
	// Bit mask of MR12 field.
	EXTI_CPUIMR1_MR12_Msk = 0x1000
	// Bit MR12.
	EXTI_CPUIMR1_MR12 = 0x1000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR12_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR12_Unmasked = 0x1
	// Position of MR13 field.
	EXTI_CPUIMR1_MR13_Pos = 0xd
	// Bit mask of MR13 field.
	EXTI_CPUIMR1_MR13_Msk = 0x2000
	// Bit MR13.
	EXTI_CPUIMR1_MR13 = 0x2000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR13_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR13_Unmasked = 0x1
	// Position of MR14 field.
	EXTI_CPUIMR1_MR14_Pos = 0xe
	// Bit mask of MR14 field.
	EXTI_CPUIMR1_MR14_Msk = 0x4000
	// Bit MR14.
	EXTI_CPUIMR1_MR14 = 0x4000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR14_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR14_Unmasked = 0x1
	// Position of MR15 field.
	EXTI_CPUIMR1_MR15_Pos = 0xf
	// Bit mask of MR15 field.
	EXTI_CPUIMR1_MR15_Msk = 0x8000
	// Bit MR15.
	EXTI_CPUIMR1_MR15 = 0x8000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR15_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR15_Unmasked = 0x1
	// Position of MR16 field.
	EXTI_CPUIMR1_MR16_Pos = 0x10
	// Bit mask of MR16 field.
	EXTI_CPUIMR1_MR16_Msk = 0x10000
	// Bit MR16.
	EXTI_CPUIMR1_MR16 = 0x10000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR16_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR16_Unmasked = 0x1
	// Position of MR17 field.
	EXTI_CPUIMR1_MR17_Pos = 0x11
	// Bit mask of MR17 field.
	EXTI_CPUIMR1_MR17_Msk = 0x20000
	// Bit MR17.
	EXTI_CPUIMR1_MR17 = 0x20000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR17_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR17_Unmasked = 0x1
	// Position of MR18 field.
	EXTI_CPUIMR1_MR18_Pos = 0x12
	// Bit mask of MR18 field.
	EXTI_CPUIMR1_MR18_Msk = 0x40000
	// Bit MR18.
	EXTI_CPUIMR1_MR18 = 0x40000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR18_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR18_Unmasked = 0x1
	// Position of MR19 field.
	EXTI_CPUIMR1_MR19_Pos = 0x13
	// Bit mask of MR19 field.
	EXTI_CPUIMR1_MR19_Msk = 0x80000
	// Bit MR19.
	EXTI_CPUIMR1_MR19 = 0x80000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR19_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR19_Unmasked = 0x1
	// Position of MR20 field.
	EXTI_CPUIMR1_MR20_Pos = 0x14
	// Bit mask of MR20 field.
	EXTI_CPUIMR1_MR20_Msk = 0x100000
	// Bit MR20.
	EXTI_CPUIMR1_MR20 = 0x100000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR20_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR20_Unmasked = 0x1
	// Position of MR21 field.
	EXTI_CPUIMR1_MR21_Pos = 0x15
	// Bit mask of MR21 field.
	EXTI_CPUIMR1_MR21_Msk = 0x200000
	// Bit MR21.
	EXTI_CPUIMR1_MR21 = 0x200000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR21_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR21_Unmasked = 0x1
	// Position of MR22 field.
	EXTI_CPUIMR1_MR22_Pos = 0x16
	// Bit mask of MR22 field.
	EXTI_CPUIMR1_MR22_Msk = 0x400000
	// Bit MR22.
	EXTI_CPUIMR1_MR22 = 0x400000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR22_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR22_Unmasked = 0x1
	// Position of MR23 field.
	EXTI_CPUIMR1_MR23_Pos = 0x17
	// Bit mask of MR23 field.
	EXTI_CPUIMR1_MR23_Msk = 0x800000
	// Bit MR23.
	EXTI_CPUIMR1_MR23 = 0x800000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR23_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR23_Unmasked = 0x1
	// Position of MR24 field.
	EXTI_CPUIMR1_MR24_Pos = 0x18
	// Bit mask of MR24 field.
	EXTI_CPUIMR1_MR24_Msk = 0x1000000
	// Bit MR24.
	EXTI_CPUIMR1_MR24 = 0x1000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR24_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR24_Unmasked = 0x1
	// Position of MR25 field.
	EXTI_CPUIMR1_MR25_Pos = 0x19
	// Bit mask of MR25 field.
	EXTI_CPUIMR1_MR25_Msk = 0x2000000
	// Bit MR25.
	EXTI_CPUIMR1_MR25 = 0x2000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR25_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR25_Unmasked = 0x1
	// Position of MR26 field.
	EXTI_CPUIMR1_MR26_Pos = 0x1a
	// Bit mask of MR26 field.
	EXTI_CPUIMR1_MR26_Msk = 0x4000000
	// Bit MR26.
	EXTI_CPUIMR1_MR26 = 0x4000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR26_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR26_Unmasked = 0x1
	// Position of MR27 field.
	EXTI_CPUIMR1_MR27_Pos = 0x1b
	// Bit mask of MR27 field.
	EXTI_CPUIMR1_MR27_Msk = 0x8000000
	// Bit MR27.
	EXTI_CPUIMR1_MR27 = 0x8000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR27_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR27_Unmasked = 0x1
	// Position of MR28 field.
	EXTI_CPUIMR1_MR28_Pos = 0x1c
	// Bit mask of MR28 field.
	EXTI_CPUIMR1_MR28_Msk = 0x10000000
	// Bit MR28.
	EXTI_CPUIMR1_MR28 = 0x10000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR28_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR28_Unmasked = 0x1
	// Position of MR29 field.
	EXTI_CPUIMR1_MR29_Pos = 0x1d
	// Bit mask of MR29 field.
	EXTI_CPUIMR1_MR29_Msk = 0x20000000
	// Bit MR29.
	EXTI_CPUIMR1_MR29 = 0x20000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR29_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR29_Unmasked = 0x1
	// Position of MR30 field.
	EXTI_CPUIMR1_MR30_Pos = 0x1e
	// Bit mask of MR30 field.
	EXTI_CPUIMR1_MR30_Msk = 0x40000000
	// Bit MR30.
	EXTI_CPUIMR1_MR30 = 0x40000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR30_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR30_Unmasked = 0x1
	// Position of MR31 field.
	EXTI_CPUIMR1_MR31_Pos = 0x1f
	// Bit mask of MR31 field.
	EXTI_CPUIMR1_MR31_Msk = 0x80000000
	// Bit MR31.
	EXTI_CPUIMR1_MR31 = 0x80000000
	// Interrupt request line is masked
	EXTI_CPUIMR1_MR31_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR1_MR31_Unmasked = 0x1

	// CPUEMR1: EXTI event mask register
	// Position of MR0 field.
	EXTI_CPUEMR1_MR0_Pos = 0x0
	// Bit mask of MR0 field.
	EXTI_CPUEMR1_MR0_Msk = 0x1
	// Bit MR0.
	EXTI_CPUEMR1_MR0 = 0x1
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR0_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR0_Unmasked = 0x1
	// Position of MR1 field.
	EXTI_CPUEMR1_MR1_Pos = 0x1
	// Bit mask of MR1 field.
	EXTI_CPUEMR1_MR1_Msk = 0x2
	// Bit MR1.
	EXTI_CPUEMR1_MR1 = 0x2
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR1_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR1_Unmasked = 0x1
	// Position of MR2 field.
	EXTI_CPUEMR1_MR2_Pos = 0x2
	// Bit mask of MR2 field.
	EXTI_CPUEMR1_MR2_Msk = 0x4
	// Bit MR2.
	EXTI_CPUEMR1_MR2 = 0x4
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR2_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR2_Unmasked = 0x1
	// Position of MR3 field.
	EXTI_CPUEMR1_MR3_Pos = 0x3
	// Bit mask of MR3 field.
	EXTI_CPUEMR1_MR3_Msk = 0x8
	// Bit MR3.
	EXTI_CPUEMR1_MR3 = 0x8
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR3_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR3_Unmasked = 0x1
	// Position of MR4 field.
	EXTI_CPUEMR1_MR4_Pos = 0x4
	// Bit mask of MR4 field.
	EXTI_CPUEMR1_MR4_Msk = 0x10
	// Bit MR4.
	EXTI_CPUEMR1_MR4 = 0x10
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR4_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR4_Unmasked = 0x1
	// Position of MR5 field.
	EXTI_CPUEMR1_MR5_Pos = 0x5
	// Bit mask of MR5 field.
	EXTI_CPUEMR1_MR5_Msk = 0x20
	// Bit MR5.
	EXTI_CPUEMR1_MR5 = 0x20
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR5_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR5_Unmasked = 0x1
	// Position of MR6 field.
	EXTI_CPUEMR1_MR6_Pos = 0x6
	// Bit mask of MR6 field.
	EXTI_CPUEMR1_MR6_Msk = 0x40
	// Bit MR6.
	EXTI_CPUEMR1_MR6 = 0x40
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR6_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR6_Unmasked = 0x1
	// Position of MR7 field.
	EXTI_CPUEMR1_MR7_Pos = 0x7
	// Bit mask of MR7 field.
	EXTI_CPUEMR1_MR7_Msk = 0x80
	// Bit MR7.
	EXTI_CPUEMR1_MR7 = 0x80
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR7_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR7_Unmasked = 0x1
	// Position of MR8 field.
	EXTI_CPUEMR1_MR8_Pos = 0x8
	// Bit mask of MR8 field.
	EXTI_CPUEMR1_MR8_Msk = 0x100
	// Bit MR8.
	EXTI_CPUEMR1_MR8 = 0x100
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR8_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR8_Unmasked = 0x1
	// Position of MR9 field.
	EXTI_CPUEMR1_MR9_Pos = 0x9
	// Bit mask of MR9 field.
	EXTI_CPUEMR1_MR9_Msk = 0x200
	// Bit MR9.
	EXTI_CPUEMR1_MR9 = 0x200
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR9_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR9_Unmasked = 0x1
	// Position of MR10 field.
	EXTI_CPUEMR1_MR10_Pos = 0xa
	// Bit mask of MR10 field.
	EXTI_CPUEMR1_MR10_Msk = 0x400
	// Bit MR10.
	EXTI_CPUEMR1_MR10 = 0x400
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR10_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR10_Unmasked = 0x1
	// Position of MR11 field.
	EXTI_CPUEMR1_MR11_Pos = 0xb
	// Bit mask of MR11 field.
	EXTI_CPUEMR1_MR11_Msk = 0x800
	// Bit MR11.
	EXTI_CPUEMR1_MR11 = 0x800
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR11_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR11_Unmasked = 0x1
	// Position of MR12 field.
	EXTI_CPUEMR1_MR12_Pos = 0xc
	// Bit mask of MR12 field.
	EXTI_CPUEMR1_MR12_Msk = 0x1000
	// Bit MR12.
	EXTI_CPUEMR1_MR12 = 0x1000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR12_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR12_Unmasked = 0x1
	// Position of MR13 field.
	EXTI_CPUEMR1_MR13_Pos = 0xd
	// Bit mask of MR13 field.
	EXTI_CPUEMR1_MR13_Msk = 0x2000
	// Bit MR13.
	EXTI_CPUEMR1_MR13 = 0x2000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR13_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR13_Unmasked = 0x1
	// Position of MR14 field.
	EXTI_CPUEMR1_MR14_Pos = 0xe
	// Bit mask of MR14 field.
	EXTI_CPUEMR1_MR14_Msk = 0x4000
	// Bit MR14.
	EXTI_CPUEMR1_MR14 = 0x4000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR14_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR14_Unmasked = 0x1
	// Position of MR15 field.
	EXTI_CPUEMR1_MR15_Pos = 0xf
	// Bit mask of MR15 field.
	EXTI_CPUEMR1_MR15_Msk = 0x8000
	// Bit MR15.
	EXTI_CPUEMR1_MR15 = 0x8000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR15_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR15_Unmasked = 0x1
	// Position of MR16 field.
	EXTI_CPUEMR1_MR16_Pos = 0x10
	// Bit mask of MR16 field.
	EXTI_CPUEMR1_MR16_Msk = 0x10000
	// Bit MR16.
	EXTI_CPUEMR1_MR16 = 0x10000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR16_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR16_Unmasked = 0x1
	// Position of MR17 field.
	EXTI_CPUEMR1_MR17_Pos = 0x11
	// Bit mask of MR17 field.
	EXTI_CPUEMR1_MR17_Msk = 0x20000
	// Bit MR17.
	EXTI_CPUEMR1_MR17 = 0x20000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR17_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR17_Unmasked = 0x1
	// Position of MR18 field.
	EXTI_CPUEMR1_MR18_Pos = 0x12
	// Bit mask of MR18 field.
	EXTI_CPUEMR1_MR18_Msk = 0x40000
	// Bit MR18.
	EXTI_CPUEMR1_MR18 = 0x40000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR18_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR18_Unmasked = 0x1
	// Position of MR19 field.
	EXTI_CPUEMR1_MR19_Pos = 0x13
	// Bit mask of MR19 field.
	EXTI_CPUEMR1_MR19_Msk = 0x80000
	// Bit MR19.
	EXTI_CPUEMR1_MR19 = 0x80000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR19_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR19_Unmasked = 0x1
	// Position of MR20 field.
	EXTI_CPUEMR1_MR20_Pos = 0x14
	// Bit mask of MR20 field.
	EXTI_CPUEMR1_MR20_Msk = 0x100000
	// Bit MR20.
	EXTI_CPUEMR1_MR20 = 0x100000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR20_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR20_Unmasked = 0x1
	// Position of MR21 field.
	EXTI_CPUEMR1_MR21_Pos = 0x15
	// Bit mask of MR21 field.
	EXTI_CPUEMR1_MR21_Msk = 0x200000
	// Bit MR21.
	EXTI_CPUEMR1_MR21 = 0x200000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR21_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR21_Unmasked = 0x1
	// Position of MR22 field.
	EXTI_CPUEMR1_MR22_Pos = 0x16
	// Bit mask of MR22 field.
	EXTI_CPUEMR1_MR22_Msk = 0x400000
	// Bit MR22.
	EXTI_CPUEMR1_MR22 = 0x400000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR22_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR22_Unmasked = 0x1
	// Position of MR23 field.
	EXTI_CPUEMR1_MR23_Pos = 0x17
	// Bit mask of MR23 field.
	EXTI_CPUEMR1_MR23_Msk = 0x800000
	// Bit MR23.
	EXTI_CPUEMR1_MR23 = 0x800000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR23_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR23_Unmasked = 0x1
	// Position of MR24 field.
	EXTI_CPUEMR1_MR24_Pos = 0x18
	// Bit mask of MR24 field.
	EXTI_CPUEMR1_MR24_Msk = 0x1000000
	// Bit MR24.
	EXTI_CPUEMR1_MR24 = 0x1000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR24_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR24_Unmasked = 0x1
	// Position of MR25 field.
	EXTI_CPUEMR1_MR25_Pos = 0x19
	// Bit mask of MR25 field.
	EXTI_CPUEMR1_MR25_Msk = 0x2000000
	// Bit MR25.
	EXTI_CPUEMR1_MR25 = 0x2000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR25_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR25_Unmasked = 0x1
	// Position of MR26 field.
	EXTI_CPUEMR1_MR26_Pos = 0x1a
	// Bit mask of MR26 field.
	EXTI_CPUEMR1_MR26_Msk = 0x4000000
	// Bit MR26.
	EXTI_CPUEMR1_MR26 = 0x4000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR26_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR26_Unmasked = 0x1
	// Position of MR27 field.
	EXTI_CPUEMR1_MR27_Pos = 0x1b
	// Bit mask of MR27 field.
	EXTI_CPUEMR1_MR27_Msk = 0x8000000
	// Bit MR27.
	EXTI_CPUEMR1_MR27 = 0x8000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR27_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR27_Unmasked = 0x1
	// Position of MR28 field.
	EXTI_CPUEMR1_MR28_Pos = 0x1c
	// Bit mask of MR28 field.
	EXTI_CPUEMR1_MR28_Msk = 0x10000000
	// Bit MR28.
	EXTI_CPUEMR1_MR28 = 0x10000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR28_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR28_Unmasked = 0x1
	// Position of MR29 field.
	EXTI_CPUEMR1_MR29_Pos = 0x1d
	// Bit mask of MR29 field.
	EXTI_CPUEMR1_MR29_Msk = 0x20000000
	// Bit MR29.
	EXTI_CPUEMR1_MR29 = 0x20000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR29_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR29_Unmasked = 0x1
	// Position of MR30 field.
	EXTI_CPUEMR1_MR30_Pos = 0x1e
	// Bit mask of MR30 field.
	EXTI_CPUEMR1_MR30_Msk = 0x40000000
	// Bit MR30.
	EXTI_CPUEMR1_MR30 = 0x40000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR30_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR30_Unmasked = 0x1
	// Position of MR31 field.
	EXTI_CPUEMR1_MR31_Pos = 0x1f
	// Bit mask of MR31 field.
	EXTI_CPUEMR1_MR31_Msk = 0x80000000
	// Bit MR31.
	EXTI_CPUEMR1_MR31 = 0x80000000
	// Interrupt request line is masked
	EXTI_CPUEMR1_MR31_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR1_MR31_Unmasked = 0x1

	// CPUPR1: EXTI pending register
	// Position of PR0 field.
	EXTI_CPUPR1_PR0_Pos = 0x0
	// Bit mask of PR0 field.
	EXTI_CPUPR1_PR0_Msk = 0x1
	// Bit PR0.
	EXTI_CPUPR1_PR0 = 0x1
	// No trigger request occurred
	EXTI_CPUPR1_PR0_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR0_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR0_Clear = 0x1
	// Position of PR1 field.
	EXTI_CPUPR1_PR1_Pos = 0x1
	// Bit mask of PR1 field.
	EXTI_CPUPR1_PR1_Msk = 0x2
	// Bit PR1.
	EXTI_CPUPR1_PR1 = 0x2
	// No trigger request occurred
	EXTI_CPUPR1_PR1_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR1_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR1_Clear = 0x1
	// Position of PR2 field.
	EXTI_CPUPR1_PR2_Pos = 0x2
	// Bit mask of PR2 field.
	EXTI_CPUPR1_PR2_Msk = 0x4
	// Bit PR2.
	EXTI_CPUPR1_PR2 = 0x4
	// No trigger request occurred
	EXTI_CPUPR1_PR2_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR2_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR2_Clear = 0x1
	// Position of PR3 field.
	EXTI_CPUPR1_PR3_Pos = 0x3
	// Bit mask of PR3 field.
	EXTI_CPUPR1_PR3_Msk = 0x8
	// Bit PR3.
	EXTI_CPUPR1_PR3 = 0x8
	// No trigger request occurred
	EXTI_CPUPR1_PR3_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR3_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR3_Clear = 0x1
	// Position of PR4 field.
	EXTI_CPUPR1_PR4_Pos = 0x4
	// Bit mask of PR4 field.
	EXTI_CPUPR1_PR4_Msk = 0x10
	// Bit PR4.
	EXTI_CPUPR1_PR4 = 0x10
	// No trigger request occurred
	EXTI_CPUPR1_PR4_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR4_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR4_Clear = 0x1
	// Position of PR5 field.
	EXTI_CPUPR1_PR5_Pos = 0x5
	// Bit mask of PR5 field.
	EXTI_CPUPR1_PR5_Msk = 0x20
	// Bit PR5.
	EXTI_CPUPR1_PR5 = 0x20
	// No trigger request occurred
	EXTI_CPUPR1_PR5_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR5_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR5_Clear = 0x1
	// Position of PR6 field.
	EXTI_CPUPR1_PR6_Pos = 0x6
	// Bit mask of PR6 field.
	EXTI_CPUPR1_PR6_Msk = 0x40
	// Bit PR6.
	EXTI_CPUPR1_PR6 = 0x40
	// No trigger request occurred
	EXTI_CPUPR1_PR6_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR6_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR6_Clear = 0x1
	// Position of PR7 field.
	EXTI_CPUPR1_PR7_Pos = 0x7
	// Bit mask of PR7 field.
	EXTI_CPUPR1_PR7_Msk = 0x80
	// Bit PR7.
	EXTI_CPUPR1_PR7 = 0x80
	// No trigger request occurred
	EXTI_CPUPR1_PR7_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR7_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR7_Clear = 0x1
	// Position of PR8 field.
	EXTI_CPUPR1_PR8_Pos = 0x8
	// Bit mask of PR8 field.
	EXTI_CPUPR1_PR8_Msk = 0x100
	// Bit PR8.
	EXTI_CPUPR1_PR8 = 0x100
	// No trigger request occurred
	EXTI_CPUPR1_PR8_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR8_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR8_Clear = 0x1
	// Position of PR9 field.
	EXTI_CPUPR1_PR9_Pos = 0x9
	// Bit mask of PR9 field.
	EXTI_CPUPR1_PR9_Msk = 0x200
	// Bit PR9.
	EXTI_CPUPR1_PR9 = 0x200
	// No trigger request occurred
	EXTI_CPUPR1_PR9_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR9_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR9_Clear = 0x1
	// Position of PR10 field.
	EXTI_CPUPR1_PR10_Pos = 0xa
	// Bit mask of PR10 field.
	EXTI_CPUPR1_PR10_Msk = 0x400
	// Bit PR10.
	EXTI_CPUPR1_PR10 = 0x400
	// No trigger request occurred
	EXTI_CPUPR1_PR10_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR10_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR10_Clear = 0x1
	// Position of PR11 field.
	EXTI_CPUPR1_PR11_Pos = 0xb
	// Bit mask of PR11 field.
	EXTI_CPUPR1_PR11_Msk = 0x800
	// Bit PR11.
	EXTI_CPUPR1_PR11 = 0x800
	// No trigger request occurred
	EXTI_CPUPR1_PR11_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR11_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR11_Clear = 0x1
	// Position of PR12 field.
	EXTI_CPUPR1_PR12_Pos = 0xc
	// Bit mask of PR12 field.
	EXTI_CPUPR1_PR12_Msk = 0x1000
	// Bit PR12.
	EXTI_CPUPR1_PR12 = 0x1000
	// No trigger request occurred
	EXTI_CPUPR1_PR12_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR12_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR12_Clear = 0x1
	// Position of PR13 field.
	EXTI_CPUPR1_PR13_Pos = 0xd
	// Bit mask of PR13 field.
	EXTI_CPUPR1_PR13_Msk = 0x2000
	// Bit PR13.
	EXTI_CPUPR1_PR13 = 0x2000
	// No trigger request occurred
	EXTI_CPUPR1_PR13_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR13_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR13_Clear = 0x1
	// Position of PR14 field.
	EXTI_CPUPR1_PR14_Pos = 0xe
	// Bit mask of PR14 field.
	EXTI_CPUPR1_PR14_Msk = 0x4000
	// Bit PR14.
	EXTI_CPUPR1_PR14 = 0x4000
	// No trigger request occurred
	EXTI_CPUPR1_PR14_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR14_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR14_Clear = 0x1
	// Position of PR15 field.
	EXTI_CPUPR1_PR15_Pos = 0xf
	// Bit mask of PR15 field.
	EXTI_CPUPR1_PR15_Msk = 0x8000
	// Bit PR15.
	EXTI_CPUPR1_PR15 = 0x8000
	// No trigger request occurred
	EXTI_CPUPR1_PR15_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR15_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR15_Clear = 0x1
	// Position of PR16 field.
	EXTI_CPUPR1_PR16_Pos = 0x10
	// Bit mask of PR16 field.
	EXTI_CPUPR1_PR16_Msk = 0x10000
	// Bit PR16.
	EXTI_CPUPR1_PR16 = 0x10000
	// No trigger request occurred
	EXTI_CPUPR1_PR16_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR16_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR16_Clear = 0x1
	// Position of PR17 field.
	EXTI_CPUPR1_PR17_Pos = 0x11
	// Bit mask of PR17 field.
	EXTI_CPUPR1_PR17_Msk = 0x20000
	// Bit PR17.
	EXTI_CPUPR1_PR17 = 0x20000
	// No trigger request occurred
	EXTI_CPUPR1_PR17_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR17_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR17_Clear = 0x1
	// Position of PR18 field.
	EXTI_CPUPR1_PR18_Pos = 0x12
	// Bit mask of PR18 field.
	EXTI_CPUPR1_PR18_Msk = 0x40000
	// Bit PR18.
	EXTI_CPUPR1_PR18 = 0x40000
	// No trigger request occurred
	EXTI_CPUPR1_PR18_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR18_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR18_Clear = 0x1
	// Position of PR19 field.
	EXTI_CPUPR1_PR19_Pos = 0x13
	// Bit mask of PR19 field.
	EXTI_CPUPR1_PR19_Msk = 0x80000
	// Bit PR19.
	EXTI_CPUPR1_PR19 = 0x80000
	// No trigger request occurred
	EXTI_CPUPR1_PR19_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR19_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR19_Clear = 0x1
	// Position of PR20 field.
	EXTI_CPUPR1_PR20_Pos = 0x14
	// Bit mask of PR20 field.
	EXTI_CPUPR1_PR20_Msk = 0x100000
	// Bit PR20.
	EXTI_CPUPR1_PR20 = 0x100000
	// No trigger request occurred
	EXTI_CPUPR1_PR20_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR20_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR20_Clear = 0x1
	// Position of PR21 field.
	EXTI_CPUPR1_PR21_Pos = 0x15
	// Bit mask of PR21 field.
	EXTI_CPUPR1_PR21_Msk = 0x200000
	// Bit PR21.
	EXTI_CPUPR1_PR21 = 0x200000
	// No trigger request occurred
	EXTI_CPUPR1_PR21_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR1_PR21_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR1_PR21_Clear = 0x1

	// CPUIMR2: EXTI interrupt mask register
	// Position of MR0 field.
	EXTI_CPUIMR2_MR0_Pos = 0x0
	// Bit mask of MR0 field.
	EXTI_CPUIMR2_MR0_Msk = 0x1
	// Bit MR0.
	EXTI_CPUIMR2_MR0 = 0x1
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR0_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR0_Unmasked = 0x1
	// Position of MR1 field.
	EXTI_CPUIMR2_MR1_Pos = 0x1
	// Bit mask of MR1 field.
	EXTI_CPUIMR2_MR1_Msk = 0x2
	// Bit MR1.
	EXTI_CPUIMR2_MR1 = 0x2
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR1_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR1_Unmasked = 0x1
	// Position of MR2 field.
	EXTI_CPUIMR2_MR2_Pos = 0x2
	// Bit mask of MR2 field.
	EXTI_CPUIMR2_MR2_Msk = 0x4
	// Bit MR2.
	EXTI_CPUIMR2_MR2 = 0x4
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR2_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR2_Unmasked = 0x1
	// Position of MR3 field.
	EXTI_CPUIMR2_MR3_Pos = 0x3
	// Bit mask of MR3 field.
	EXTI_CPUIMR2_MR3_Msk = 0x8
	// Bit MR3.
	EXTI_CPUIMR2_MR3 = 0x8
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR3_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR3_Unmasked = 0x1
	// Position of MR4 field.
	EXTI_CPUIMR2_MR4_Pos = 0x4
	// Bit mask of MR4 field.
	EXTI_CPUIMR2_MR4_Msk = 0x10
	// Bit MR4.
	EXTI_CPUIMR2_MR4 = 0x10
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR4_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR4_Unmasked = 0x1
	// Position of MR5 field.
	EXTI_CPUIMR2_MR5_Pos = 0x5
	// Bit mask of MR5 field.
	EXTI_CPUIMR2_MR5_Msk = 0x20
	// Bit MR5.
	EXTI_CPUIMR2_MR5 = 0x20
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR5_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR5_Unmasked = 0x1
	// Position of MR6 field.
	EXTI_CPUIMR2_MR6_Pos = 0x6
	// Bit mask of MR6 field.
	EXTI_CPUIMR2_MR6_Msk = 0x40
	// Bit MR6.
	EXTI_CPUIMR2_MR6 = 0x40
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR6_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR6_Unmasked = 0x1
	// Position of MR7 field.
	EXTI_CPUIMR2_MR7_Pos = 0x7
	// Bit mask of MR7 field.
	EXTI_CPUIMR2_MR7_Msk = 0x80
	// Bit MR7.
	EXTI_CPUIMR2_MR7 = 0x80
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR7_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR7_Unmasked = 0x1
	// Position of MR8 field.
	EXTI_CPUIMR2_MR8_Pos = 0x8
	// Bit mask of MR8 field.
	EXTI_CPUIMR2_MR8_Msk = 0x100
	// Bit MR8.
	EXTI_CPUIMR2_MR8 = 0x100
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR8_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR8_Unmasked = 0x1
	// Position of MR9 field.
	EXTI_CPUIMR2_MR9_Pos = 0x9
	// Bit mask of MR9 field.
	EXTI_CPUIMR2_MR9_Msk = 0x200
	// Bit MR9.
	EXTI_CPUIMR2_MR9 = 0x200
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR9_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR9_Unmasked = 0x1
	// Position of MR10 field.
	EXTI_CPUIMR2_MR10_Pos = 0xa
	// Bit mask of MR10 field.
	EXTI_CPUIMR2_MR10_Msk = 0x400
	// Bit MR10.
	EXTI_CPUIMR2_MR10 = 0x400
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR10_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR10_Unmasked = 0x1
	// Position of MR11 field.
	EXTI_CPUIMR2_MR11_Pos = 0xb
	// Bit mask of MR11 field.
	EXTI_CPUIMR2_MR11_Msk = 0x800
	// Bit MR11.
	EXTI_CPUIMR2_MR11 = 0x800
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR11_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR11_Unmasked = 0x1
	// Position of MR12 field.
	EXTI_CPUIMR2_MR12_Pos = 0xc
	// Bit mask of MR12 field.
	EXTI_CPUIMR2_MR12_Msk = 0x1000
	// Bit MR12.
	EXTI_CPUIMR2_MR12 = 0x1000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR12_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR12_Unmasked = 0x1
	// Position of MR14 field.
	EXTI_CPUIMR2_MR14_Pos = 0xe
	// Bit mask of MR14 field.
	EXTI_CPUIMR2_MR14_Msk = 0x4000
	// Bit MR14.
	EXTI_CPUIMR2_MR14 = 0x4000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR14_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR14_Unmasked = 0x1
	// Position of MR15 field.
	EXTI_CPUIMR2_MR15_Pos = 0xf
	// Bit mask of MR15 field.
	EXTI_CPUIMR2_MR15_Msk = 0x8000
	// Bit MR15.
	EXTI_CPUIMR2_MR15 = 0x8000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR15_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR15_Unmasked = 0x1
	// Position of MR16 field.
	EXTI_CPUIMR2_MR16_Pos = 0x10
	// Bit mask of MR16 field.
	EXTI_CPUIMR2_MR16_Msk = 0x10000
	// Bit MR16.
	EXTI_CPUIMR2_MR16 = 0x10000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR16_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR16_Unmasked = 0x1
	// Position of MR17 field.
	EXTI_CPUIMR2_MR17_Pos = 0x11
	// Bit mask of MR17 field.
	EXTI_CPUIMR2_MR17_Msk = 0x20000
	// Bit MR17.
	EXTI_CPUIMR2_MR17 = 0x20000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR17_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR17_Unmasked = 0x1
	// Position of MR18 field.
	EXTI_CPUIMR2_MR18_Pos = 0x12
	// Bit mask of MR18 field.
	EXTI_CPUIMR2_MR18_Msk = 0x40000
	// Bit MR18.
	EXTI_CPUIMR2_MR18 = 0x40000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR18_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR18_Unmasked = 0x1
	// Position of MR19 field.
	EXTI_CPUIMR2_MR19_Pos = 0x13
	// Bit mask of MR19 field.
	EXTI_CPUIMR2_MR19_Msk = 0x80000
	// Bit MR19.
	EXTI_CPUIMR2_MR19 = 0x80000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR19_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR19_Unmasked = 0x1
	// Position of MR20 field.
	EXTI_CPUIMR2_MR20_Pos = 0x14
	// Bit mask of MR20 field.
	EXTI_CPUIMR2_MR20_Msk = 0x100000
	// Bit MR20.
	EXTI_CPUIMR2_MR20 = 0x100000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR20_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR20_Unmasked = 0x1
	// Position of MR21 field.
	EXTI_CPUIMR2_MR21_Pos = 0x15
	// Bit mask of MR21 field.
	EXTI_CPUIMR2_MR21_Msk = 0x200000
	// Bit MR21.
	EXTI_CPUIMR2_MR21 = 0x200000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR21_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR21_Unmasked = 0x1
	// Position of MR22 field.
	EXTI_CPUIMR2_MR22_Pos = 0x16
	// Bit mask of MR22 field.
	EXTI_CPUIMR2_MR22_Msk = 0x400000
	// Bit MR22.
	EXTI_CPUIMR2_MR22 = 0x400000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR22_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR22_Unmasked = 0x1
	// Position of MR23 field.
	EXTI_CPUIMR2_MR23_Pos = 0x17
	// Bit mask of MR23 field.
	EXTI_CPUIMR2_MR23_Msk = 0x800000
	// Bit MR23.
	EXTI_CPUIMR2_MR23 = 0x800000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR23_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR23_Unmasked = 0x1
	// Position of MR24 field.
	EXTI_CPUIMR2_MR24_Pos = 0x18
	// Bit mask of MR24 field.
	EXTI_CPUIMR2_MR24_Msk = 0x1000000
	// Bit MR24.
	EXTI_CPUIMR2_MR24 = 0x1000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR24_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR24_Unmasked = 0x1
	// Position of MR25 field.
	EXTI_CPUIMR2_MR25_Pos = 0x19
	// Bit mask of MR25 field.
	EXTI_CPUIMR2_MR25_Msk = 0x2000000
	// Bit MR25.
	EXTI_CPUIMR2_MR25 = 0x2000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR25_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR25_Unmasked = 0x1
	// Position of MR26 field.
	EXTI_CPUIMR2_MR26_Pos = 0x1a
	// Bit mask of MR26 field.
	EXTI_CPUIMR2_MR26_Msk = 0x4000000
	// Bit MR26.
	EXTI_CPUIMR2_MR26 = 0x4000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR26_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR26_Unmasked = 0x1
	// Position of MR27 field.
	EXTI_CPUIMR2_MR27_Pos = 0x1b
	// Bit mask of MR27 field.
	EXTI_CPUIMR2_MR27_Msk = 0x8000000
	// Bit MR27.
	EXTI_CPUIMR2_MR27 = 0x8000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR27_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR27_Unmasked = 0x1
	// Position of MR28 field.
	EXTI_CPUIMR2_MR28_Pos = 0x1c
	// Bit mask of MR28 field.
	EXTI_CPUIMR2_MR28_Msk = 0x10000000
	// Bit MR28.
	EXTI_CPUIMR2_MR28 = 0x10000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR28_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR28_Unmasked = 0x1
	// Position of MR29 field.
	EXTI_CPUIMR2_MR29_Pos = 0x1d
	// Bit mask of MR29 field.
	EXTI_CPUIMR2_MR29_Msk = 0x20000000
	// Bit MR29.
	EXTI_CPUIMR2_MR29 = 0x20000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR29_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR29_Unmasked = 0x1
	// Position of MR30 field.
	EXTI_CPUIMR2_MR30_Pos = 0x1e
	// Bit mask of MR30 field.
	EXTI_CPUIMR2_MR30_Msk = 0x40000000
	// Bit MR30.
	EXTI_CPUIMR2_MR30 = 0x40000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR30_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR30_Unmasked = 0x1
	// Position of MR31 field.
	EXTI_CPUIMR2_MR31_Pos = 0x1f
	// Bit mask of MR31 field.
	EXTI_CPUIMR2_MR31_Msk = 0x80000000
	// Bit MR31.
	EXTI_CPUIMR2_MR31 = 0x80000000
	// Interrupt request line is masked
	EXTI_CPUIMR2_MR31_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR2_MR31_Unmasked = 0x1

	// CPUEMR2: EXTI event mask register
	// Position of MR32 field.
	EXTI_CPUEMR2_MR32_Pos = 0x0
	// Bit mask of MR32 field.
	EXTI_CPUEMR2_MR32_Msk = 0x1
	// Bit MR32.
	EXTI_CPUEMR2_MR32 = 0x1
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR32_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR32_Unmasked = 0x1
	// Position of MR33 field.
	EXTI_CPUEMR2_MR33_Pos = 0x1
	// Bit mask of MR33 field.
	EXTI_CPUEMR2_MR33_Msk = 0x2
	// Bit MR33.
	EXTI_CPUEMR2_MR33 = 0x2
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR33_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR33_Unmasked = 0x1
	// Position of MR34 field.
	EXTI_CPUEMR2_MR34_Pos = 0x2
	// Bit mask of MR34 field.
	EXTI_CPUEMR2_MR34_Msk = 0x4
	// Bit MR34.
	EXTI_CPUEMR2_MR34 = 0x4
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR34_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR34_Unmasked = 0x1
	// Position of MR35 field.
	EXTI_CPUEMR2_MR35_Pos = 0x3
	// Bit mask of MR35 field.
	EXTI_CPUEMR2_MR35_Msk = 0x8
	// Bit MR35.
	EXTI_CPUEMR2_MR35 = 0x8
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR35_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR35_Unmasked = 0x1
	// Position of MR36 field.
	EXTI_CPUEMR2_MR36_Pos = 0x4
	// Bit mask of MR36 field.
	EXTI_CPUEMR2_MR36_Msk = 0x10
	// Bit MR36.
	EXTI_CPUEMR2_MR36 = 0x10
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR36_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR36_Unmasked = 0x1
	// Position of MR37 field.
	EXTI_CPUEMR2_MR37_Pos = 0x5
	// Bit mask of MR37 field.
	EXTI_CPUEMR2_MR37_Msk = 0x20
	// Bit MR37.
	EXTI_CPUEMR2_MR37 = 0x20
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR37_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR37_Unmasked = 0x1
	// Position of MR38 field.
	EXTI_CPUEMR2_MR38_Pos = 0x6
	// Bit mask of MR38 field.
	EXTI_CPUEMR2_MR38_Msk = 0x40
	// Bit MR38.
	EXTI_CPUEMR2_MR38 = 0x40
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR38_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR38_Unmasked = 0x1
	// Position of MR39 field.
	EXTI_CPUEMR2_MR39_Pos = 0x7
	// Bit mask of MR39 field.
	EXTI_CPUEMR2_MR39_Msk = 0x80
	// Bit MR39.
	EXTI_CPUEMR2_MR39 = 0x80
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR39_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR39_Unmasked = 0x1
	// Position of MR40 field.
	EXTI_CPUEMR2_MR40_Pos = 0x8
	// Bit mask of MR40 field.
	EXTI_CPUEMR2_MR40_Msk = 0x100
	// Bit MR40.
	EXTI_CPUEMR2_MR40 = 0x100
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR40_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR40_Unmasked = 0x1
	// Position of MR41 field.
	EXTI_CPUEMR2_MR41_Pos = 0x9
	// Bit mask of MR41 field.
	EXTI_CPUEMR2_MR41_Msk = 0x200
	// Bit MR41.
	EXTI_CPUEMR2_MR41 = 0x200
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR41_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR41_Unmasked = 0x1
	// Position of MR42 field.
	EXTI_CPUEMR2_MR42_Pos = 0xa
	// Bit mask of MR42 field.
	EXTI_CPUEMR2_MR42_Msk = 0x400
	// Bit MR42.
	EXTI_CPUEMR2_MR42 = 0x400
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR42_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR42_Unmasked = 0x1
	// Position of MR43 field.
	EXTI_CPUEMR2_MR43_Pos = 0xb
	// Bit mask of MR43 field.
	EXTI_CPUEMR2_MR43_Msk = 0x800
	// Bit MR43.
	EXTI_CPUEMR2_MR43 = 0x800
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR43_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR43_Unmasked = 0x1
	// Position of MR44 field.
	EXTI_CPUEMR2_MR44_Pos = 0xc
	// Bit mask of MR44 field.
	EXTI_CPUEMR2_MR44_Msk = 0x1000
	// Bit MR44.
	EXTI_CPUEMR2_MR44 = 0x1000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR44_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR44_Unmasked = 0x1
	// Position of MR46 field.
	EXTI_CPUEMR2_MR46_Pos = 0xe
	// Bit mask of MR46 field.
	EXTI_CPUEMR2_MR46_Msk = 0x4000
	// Bit MR46.
	EXTI_CPUEMR2_MR46 = 0x4000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR46_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR46_Unmasked = 0x1
	// Position of MR47 field.
	EXTI_CPUEMR2_MR47_Pos = 0xf
	// Bit mask of MR47 field.
	EXTI_CPUEMR2_MR47_Msk = 0x8000
	// Bit MR47.
	EXTI_CPUEMR2_MR47 = 0x8000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR47_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR47_Unmasked = 0x1
	// Position of MR48 field.
	EXTI_CPUEMR2_MR48_Pos = 0x10
	// Bit mask of MR48 field.
	EXTI_CPUEMR2_MR48_Msk = 0x10000
	// Bit MR48.
	EXTI_CPUEMR2_MR48 = 0x10000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR48_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR48_Unmasked = 0x1
	// Position of MR49 field.
	EXTI_CPUEMR2_MR49_Pos = 0x11
	// Bit mask of MR49 field.
	EXTI_CPUEMR2_MR49_Msk = 0x20000
	// Bit MR49.
	EXTI_CPUEMR2_MR49 = 0x20000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR49_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR49_Unmasked = 0x1
	// Position of MR50 field.
	EXTI_CPUEMR2_MR50_Pos = 0x12
	// Bit mask of MR50 field.
	EXTI_CPUEMR2_MR50_Msk = 0x40000
	// Bit MR50.
	EXTI_CPUEMR2_MR50 = 0x40000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR50_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR50_Unmasked = 0x1
	// Position of MR51 field.
	EXTI_CPUEMR2_MR51_Pos = 0x13
	// Bit mask of MR51 field.
	EXTI_CPUEMR2_MR51_Msk = 0x80000
	// Bit MR51.
	EXTI_CPUEMR2_MR51 = 0x80000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR51_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR51_Unmasked = 0x1
	// Position of MR52 field.
	EXTI_CPUEMR2_MR52_Pos = 0x14
	// Bit mask of MR52 field.
	EXTI_CPUEMR2_MR52_Msk = 0x100000
	// Bit MR52.
	EXTI_CPUEMR2_MR52 = 0x100000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR52_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR52_Unmasked = 0x1
	// Position of MR53 field.
	EXTI_CPUEMR2_MR53_Pos = 0x15
	// Bit mask of MR53 field.
	EXTI_CPUEMR2_MR53_Msk = 0x200000
	// Bit MR53.
	EXTI_CPUEMR2_MR53 = 0x200000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR53_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR53_Unmasked = 0x1
	// Position of MR54 field.
	EXTI_CPUEMR2_MR54_Pos = 0x16
	// Bit mask of MR54 field.
	EXTI_CPUEMR2_MR54_Msk = 0x400000
	// Bit MR54.
	EXTI_CPUEMR2_MR54 = 0x400000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR54_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR54_Unmasked = 0x1
	// Position of MR55 field.
	EXTI_CPUEMR2_MR55_Pos = 0x17
	// Bit mask of MR55 field.
	EXTI_CPUEMR2_MR55_Msk = 0x800000
	// Bit MR55.
	EXTI_CPUEMR2_MR55 = 0x800000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR55_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR55_Unmasked = 0x1
	// Position of MR56 field.
	EXTI_CPUEMR2_MR56_Pos = 0x18
	// Bit mask of MR56 field.
	EXTI_CPUEMR2_MR56_Msk = 0x1000000
	// Bit MR56.
	EXTI_CPUEMR2_MR56 = 0x1000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR56_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR56_Unmasked = 0x1
	// Position of MR57 field.
	EXTI_CPUEMR2_MR57_Pos = 0x19
	// Bit mask of MR57 field.
	EXTI_CPUEMR2_MR57_Msk = 0x2000000
	// Bit MR57.
	EXTI_CPUEMR2_MR57 = 0x2000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR57_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR57_Unmasked = 0x1
	// Position of MR58 field.
	EXTI_CPUEMR2_MR58_Pos = 0x1a
	// Bit mask of MR58 field.
	EXTI_CPUEMR2_MR58_Msk = 0x4000000
	// Bit MR58.
	EXTI_CPUEMR2_MR58 = 0x4000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR58_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR58_Unmasked = 0x1
	// Position of MR59 field.
	EXTI_CPUEMR2_MR59_Pos = 0x1b
	// Bit mask of MR59 field.
	EXTI_CPUEMR2_MR59_Msk = 0x8000000
	// Bit MR59.
	EXTI_CPUEMR2_MR59 = 0x8000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR59_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR59_Unmasked = 0x1
	// Position of MR60 field.
	EXTI_CPUEMR2_MR60_Pos = 0x1c
	// Bit mask of MR60 field.
	EXTI_CPUEMR2_MR60_Msk = 0x10000000
	// Bit MR60.
	EXTI_CPUEMR2_MR60 = 0x10000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR60_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR60_Unmasked = 0x1
	// Position of MR61 field.
	EXTI_CPUEMR2_MR61_Pos = 0x1d
	// Bit mask of MR61 field.
	EXTI_CPUEMR2_MR61_Msk = 0x20000000
	// Bit MR61.
	EXTI_CPUEMR2_MR61 = 0x20000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR61_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR61_Unmasked = 0x1
	// Position of MR62 field.
	EXTI_CPUEMR2_MR62_Pos = 0x1e
	// Bit mask of MR62 field.
	EXTI_CPUEMR2_MR62_Msk = 0x40000000
	// Bit MR62.
	EXTI_CPUEMR2_MR62 = 0x40000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR62_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR62_Unmasked = 0x1
	// Position of MR63 field.
	EXTI_CPUEMR2_MR63_Pos = 0x1f
	// Bit mask of MR63 field.
	EXTI_CPUEMR2_MR63_Msk = 0x80000000
	// Bit MR63.
	EXTI_CPUEMR2_MR63 = 0x80000000
	// Interrupt request line is masked
	EXTI_CPUEMR2_MR63_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR2_MR63_Unmasked = 0x1

	// CPUPR2: EXTI pending register
	// Position of PR49 field.
	EXTI_CPUPR2_PR49_Pos = 0x11
	// Bit mask of PR49 field.
	EXTI_CPUPR2_PR49_Msk = 0x20000
	// Bit PR49.
	EXTI_CPUPR2_PR49 = 0x20000
	// No trigger request occurred
	EXTI_CPUPR2_PR49_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR2_PR49_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR2_PR49_Clear = 0x1
	// Position of PR51 field.
	EXTI_CPUPR2_PR51_Pos = 0x13
	// Bit mask of PR51 field.
	EXTI_CPUPR2_PR51_Msk = 0x80000
	// Bit PR51.
	EXTI_CPUPR2_PR51 = 0x80000
	// No trigger request occurred
	EXTI_CPUPR2_PR51_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR2_PR51_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR2_PR51_Clear = 0x1

	// CPUIMR3: EXTI interrupt mask register
	// Position of MR64 field.
	EXTI_CPUIMR3_MR64_Pos = 0x0
	// Bit mask of MR64 field.
	EXTI_CPUIMR3_MR64_Msk = 0x1
	// Bit MR64.
	EXTI_CPUIMR3_MR64 = 0x1
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR64_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR64_Unmasked = 0x1
	// Position of MR65 field.
	EXTI_CPUIMR3_MR65_Pos = 0x1
	// Bit mask of MR65 field.
	EXTI_CPUIMR3_MR65_Msk = 0x2
	// Bit MR65.
	EXTI_CPUIMR3_MR65 = 0x2
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR65_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR65_Unmasked = 0x1
	// Position of MR66 field.
	EXTI_CPUIMR3_MR66_Pos = 0x2
	// Bit mask of MR66 field.
	EXTI_CPUIMR3_MR66_Msk = 0x4
	// Bit MR66.
	EXTI_CPUIMR3_MR66 = 0x4
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR66_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR66_Unmasked = 0x1
	// Position of MR67 field.
	EXTI_CPUIMR3_MR67_Pos = 0x3
	// Bit mask of MR67 field.
	EXTI_CPUIMR3_MR67_Msk = 0x8
	// Bit MR67.
	EXTI_CPUIMR3_MR67 = 0x8
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR67_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR67_Unmasked = 0x1
	// Position of MR68 field.
	EXTI_CPUIMR3_MR68_Pos = 0x4
	// Bit mask of MR68 field.
	EXTI_CPUIMR3_MR68_Msk = 0x10
	// Bit MR68.
	EXTI_CPUIMR3_MR68 = 0x10
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR68_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR68_Unmasked = 0x1
	// Position of MR69 field.
	EXTI_CPUIMR3_MR69_Pos = 0x5
	// Bit mask of MR69 field.
	EXTI_CPUIMR3_MR69_Msk = 0x20
	// Bit MR69.
	EXTI_CPUIMR3_MR69 = 0x20
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR69_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR69_Unmasked = 0x1
	// Position of MR70 field.
	EXTI_CPUIMR3_MR70_Pos = 0x6
	// Bit mask of MR70 field.
	EXTI_CPUIMR3_MR70_Msk = 0x40
	// Bit MR70.
	EXTI_CPUIMR3_MR70 = 0x40
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR70_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR70_Unmasked = 0x1
	// Position of MR71 field.
	EXTI_CPUIMR3_MR71_Pos = 0x7
	// Bit mask of MR71 field.
	EXTI_CPUIMR3_MR71_Msk = 0x80
	// Bit MR71.
	EXTI_CPUIMR3_MR71 = 0x80
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR71_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR71_Unmasked = 0x1
	// Position of MR72 field.
	EXTI_CPUIMR3_MR72_Pos = 0x8
	// Bit mask of MR72 field.
	EXTI_CPUIMR3_MR72_Msk = 0x100
	// Bit MR72.
	EXTI_CPUIMR3_MR72 = 0x100
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR72_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR72_Unmasked = 0x1
	// Position of MR73 field.
	EXTI_CPUIMR3_MR73_Pos = 0x9
	// Bit mask of MR73 field.
	EXTI_CPUIMR3_MR73_Msk = 0x200
	// Bit MR73.
	EXTI_CPUIMR3_MR73 = 0x200
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR73_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR73_Unmasked = 0x1
	// Position of MR74 field.
	EXTI_CPUIMR3_MR74_Pos = 0xa
	// Bit mask of MR74 field.
	EXTI_CPUIMR3_MR74_Msk = 0x400
	// Bit MR74.
	EXTI_CPUIMR3_MR74 = 0x400
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR74_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR74_Unmasked = 0x1
	// Position of MR75 field.
	EXTI_CPUIMR3_MR75_Pos = 0xb
	// Bit mask of MR75 field.
	EXTI_CPUIMR3_MR75_Msk = 0x800
	// Bit MR75.
	EXTI_CPUIMR3_MR75 = 0x800
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR75_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR75_Unmasked = 0x1
	// Position of MR76 field.
	EXTI_CPUIMR3_MR76_Pos = 0xc
	// Bit mask of MR76 field.
	EXTI_CPUIMR3_MR76_Msk = 0x1000
	// Bit MR76.
	EXTI_CPUIMR3_MR76 = 0x1000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR76_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR76_Unmasked = 0x1
	// Position of MR77 field.
	EXTI_CPUIMR3_MR77_Pos = 0xd
	// Bit mask of MR77 field.
	EXTI_CPUIMR3_MR77_Msk = 0x2000
	// Bit MR77.
	EXTI_CPUIMR3_MR77 = 0x2000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR77_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR77_Unmasked = 0x1
	// Position of MR78 field.
	EXTI_CPUIMR3_MR78_Pos = 0xe
	// Bit mask of MR78 field.
	EXTI_CPUIMR3_MR78_Msk = 0x4000
	// Bit MR78.
	EXTI_CPUIMR3_MR78 = 0x4000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR78_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR78_Unmasked = 0x1
	// Position of MR79 field.
	EXTI_CPUIMR3_MR79_Pos = 0xf
	// Bit mask of MR79 field.
	EXTI_CPUIMR3_MR79_Msk = 0x8000
	// Bit MR79.
	EXTI_CPUIMR3_MR79 = 0x8000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR79_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR79_Unmasked = 0x1
	// Position of MR80 field.
	EXTI_CPUIMR3_MR80_Pos = 0x10
	// Bit mask of MR80 field.
	EXTI_CPUIMR3_MR80_Msk = 0x10000
	// Bit MR80.
	EXTI_CPUIMR3_MR80 = 0x10000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR80_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR80_Unmasked = 0x1
	// Position of MR82 field.
	EXTI_CPUIMR3_MR82_Pos = 0x12
	// Bit mask of MR82 field.
	EXTI_CPUIMR3_MR82_Msk = 0x40000
	// Bit MR82.
	EXTI_CPUIMR3_MR82 = 0x40000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR82_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR82_Unmasked = 0x1
	// Position of MR84 field.
	EXTI_CPUIMR3_MR84_Pos = 0x14
	// Bit mask of MR84 field.
	EXTI_CPUIMR3_MR84_Msk = 0x100000
	// Bit MR84.
	EXTI_CPUIMR3_MR84 = 0x100000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR84_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR84_Unmasked = 0x1
	// Position of MR85 field.
	EXTI_CPUIMR3_MR85_Pos = 0x15
	// Bit mask of MR85 field.
	EXTI_CPUIMR3_MR85_Msk = 0x200000
	// Bit MR85.
	EXTI_CPUIMR3_MR85 = 0x200000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR85_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR85_Unmasked = 0x1
	// Position of MR86 field.
	EXTI_CPUIMR3_MR86_Pos = 0x16
	// Bit mask of MR86 field.
	EXTI_CPUIMR3_MR86_Msk = 0x400000
	// Bit MR86.
	EXTI_CPUIMR3_MR86 = 0x400000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR86_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR86_Unmasked = 0x1
	// Position of MR87 field.
	EXTI_CPUIMR3_MR87_Pos = 0x17
	// Bit mask of MR87 field.
	EXTI_CPUIMR3_MR87_Msk = 0x800000
	// Bit MR87.
	EXTI_CPUIMR3_MR87 = 0x800000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR87_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR87_Unmasked = 0x1
	// Position of MR88 field.
	EXTI_CPUIMR3_MR88_Pos = 0x18
	// Bit mask of MR88 field.
	EXTI_CPUIMR3_MR88_Msk = 0x1000000
	// Bit MR88.
	EXTI_CPUIMR3_MR88 = 0x1000000
	// Interrupt request line is masked
	EXTI_CPUIMR3_MR88_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUIMR3_MR88_Unmasked = 0x1

	// CPUEMR3: EXTI event mask register
	// Position of MR64 field.
	EXTI_CPUEMR3_MR64_Pos = 0x0
	// Bit mask of MR64 field.
	EXTI_CPUEMR3_MR64_Msk = 0x1
	// Bit MR64.
	EXTI_CPUEMR3_MR64 = 0x1
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR64_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR64_Unmasked = 0x1
	// Position of MR65 field.
	EXTI_CPUEMR3_MR65_Pos = 0x1
	// Bit mask of MR65 field.
	EXTI_CPUEMR3_MR65_Msk = 0x2
	// Bit MR65.
	EXTI_CPUEMR3_MR65 = 0x2
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR65_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR65_Unmasked = 0x1
	// Position of MR66 field.
	EXTI_CPUEMR3_MR66_Pos = 0x2
	// Bit mask of MR66 field.
	EXTI_CPUEMR3_MR66_Msk = 0x4
	// Bit MR66.
	EXTI_CPUEMR3_MR66 = 0x4
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR66_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR66_Unmasked = 0x1
	// Position of MR67 field.
	EXTI_CPUEMR3_MR67_Pos = 0x3
	// Bit mask of MR67 field.
	EXTI_CPUEMR3_MR67_Msk = 0x8
	// Bit MR67.
	EXTI_CPUEMR3_MR67 = 0x8
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR67_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR67_Unmasked = 0x1
	// Position of MR68 field.
	EXTI_CPUEMR3_MR68_Pos = 0x4
	// Bit mask of MR68 field.
	EXTI_CPUEMR3_MR68_Msk = 0x10
	// Bit MR68.
	EXTI_CPUEMR3_MR68 = 0x10
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR68_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR68_Unmasked = 0x1
	// Position of MR69 field.
	EXTI_CPUEMR3_MR69_Pos = 0x5
	// Bit mask of MR69 field.
	EXTI_CPUEMR3_MR69_Msk = 0x20
	// Bit MR69.
	EXTI_CPUEMR3_MR69 = 0x20
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR69_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR69_Unmasked = 0x1
	// Position of MR70 field.
	EXTI_CPUEMR3_MR70_Pos = 0x6
	// Bit mask of MR70 field.
	EXTI_CPUEMR3_MR70_Msk = 0x40
	// Bit MR70.
	EXTI_CPUEMR3_MR70 = 0x40
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR70_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR70_Unmasked = 0x1
	// Position of MR71 field.
	EXTI_CPUEMR3_MR71_Pos = 0x7
	// Bit mask of MR71 field.
	EXTI_CPUEMR3_MR71_Msk = 0x80
	// Bit MR71.
	EXTI_CPUEMR3_MR71 = 0x80
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR71_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR71_Unmasked = 0x1
	// Position of MR72 field.
	EXTI_CPUEMR3_MR72_Pos = 0x8
	// Bit mask of MR72 field.
	EXTI_CPUEMR3_MR72_Msk = 0x100
	// Bit MR72.
	EXTI_CPUEMR3_MR72 = 0x100
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR72_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR72_Unmasked = 0x1
	// Position of MR73 field.
	EXTI_CPUEMR3_MR73_Pos = 0x9
	// Bit mask of MR73 field.
	EXTI_CPUEMR3_MR73_Msk = 0x200
	// Bit MR73.
	EXTI_CPUEMR3_MR73 = 0x200
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR73_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR73_Unmasked = 0x1
	// Position of MR74 field.
	EXTI_CPUEMR3_MR74_Pos = 0xa
	// Bit mask of MR74 field.
	EXTI_CPUEMR3_MR74_Msk = 0x400
	// Bit MR74.
	EXTI_CPUEMR3_MR74 = 0x400
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR74_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR74_Unmasked = 0x1
	// Position of MR75 field.
	EXTI_CPUEMR3_MR75_Pos = 0xb
	// Bit mask of MR75 field.
	EXTI_CPUEMR3_MR75_Msk = 0x800
	// Bit MR75.
	EXTI_CPUEMR3_MR75 = 0x800
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR75_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR75_Unmasked = 0x1
	// Position of MR76 field.
	EXTI_CPUEMR3_MR76_Pos = 0xc
	// Bit mask of MR76 field.
	EXTI_CPUEMR3_MR76_Msk = 0x1000
	// Bit MR76.
	EXTI_CPUEMR3_MR76 = 0x1000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR76_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR76_Unmasked = 0x1
	// Position of MR77 field.
	EXTI_CPUEMR3_MR77_Pos = 0xd
	// Bit mask of MR77 field.
	EXTI_CPUEMR3_MR77_Msk = 0x2000
	// Bit MR77.
	EXTI_CPUEMR3_MR77 = 0x2000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR77_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR77_Unmasked = 0x1
	// Position of MR78 field.
	EXTI_CPUEMR3_MR78_Pos = 0xe
	// Bit mask of MR78 field.
	EXTI_CPUEMR3_MR78_Msk = 0x4000
	// Bit MR78.
	EXTI_CPUEMR3_MR78 = 0x4000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR78_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR78_Unmasked = 0x1
	// Position of MR79 field.
	EXTI_CPUEMR3_MR79_Pos = 0xf
	// Bit mask of MR79 field.
	EXTI_CPUEMR3_MR79_Msk = 0x8000
	// Bit MR79.
	EXTI_CPUEMR3_MR79 = 0x8000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR79_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR79_Unmasked = 0x1
	// Position of MR80 field.
	EXTI_CPUEMR3_MR80_Pos = 0x10
	// Bit mask of MR80 field.
	EXTI_CPUEMR3_MR80_Msk = 0x10000
	// Bit MR80.
	EXTI_CPUEMR3_MR80 = 0x10000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR80_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR80_Unmasked = 0x1
	// Position of MR82 field.
	EXTI_CPUEMR3_MR82_Pos = 0x12
	// Bit mask of MR82 field.
	EXTI_CPUEMR3_MR82_Msk = 0x40000
	// Bit MR82.
	EXTI_CPUEMR3_MR82 = 0x40000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR82_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR82_Unmasked = 0x1
	// Position of MR84 field.
	EXTI_CPUEMR3_MR84_Pos = 0x14
	// Bit mask of MR84 field.
	EXTI_CPUEMR3_MR84_Msk = 0x100000
	// Bit MR84.
	EXTI_CPUEMR3_MR84 = 0x100000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR84_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR84_Unmasked = 0x1
	// Position of MR85 field.
	EXTI_CPUEMR3_MR85_Pos = 0x15
	// Bit mask of MR85 field.
	EXTI_CPUEMR3_MR85_Msk = 0x200000
	// Bit MR85.
	EXTI_CPUEMR3_MR85 = 0x200000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR85_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR85_Unmasked = 0x1
	// Position of MR86 field.
	EXTI_CPUEMR3_MR86_Pos = 0x16
	// Bit mask of MR86 field.
	EXTI_CPUEMR3_MR86_Msk = 0x400000
	// Bit MR86.
	EXTI_CPUEMR3_MR86 = 0x400000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR86_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR86_Unmasked = 0x1
	// Position of MR87 field.
	EXTI_CPUEMR3_MR87_Pos = 0x17
	// Bit mask of MR87 field.
	EXTI_CPUEMR3_MR87_Msk = 0x800000
	// Bit MR87.
	EXTI_CPUEMR3_MR87 = 0x800000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR87_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR87_Unmasked = 0x1
	// Position of MR88 field.
	EXTI_CPUEMR3_MR88_Pos = 0x18
	// Bit mask of MR88 field.
	EXTI_CPUEMR3_MR88_Msk = 0x1000000
	// Bit MR88.
	EXTI_CPUEMR3_MR88 = 0x1000000
	// Interrupt request line is masked
	EXTI_CPUEMR3_MR88_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_CPUEMR3_MR88_Unmasked = 0x1

	// CPUPR3: EXTI pending register
	// Position of PR82 field.
	EXTI_CPUPR3_PR82_Pos = 0x12
	// Bit mask of PR82 field.
	EXTI_CPUPR3_PR82_Msk = 0x40000
	// Bit PR82.
	EXTI_CPUPR3_PR82 = 0x40000
	// No trigger request occurred
	EXTI_CPUPR3_PR82_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR3_PR82_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR3_PR82_Clear = 0x1
	// Position of PR84 field.
	EXTI_CPUPR3_PR84_Pos = 0x14
	// Bit mask of PR84 field.
	EXTI_CPUPR3_PR84_Msk = 0x100000
	// Bit PR84.
	EXTI_CPUPR3_PR84 = 0x100000
	// No trigger request occurred
	EXTI_CPUPR3_PR84_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR3_PR84_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR3_PR84_Clear = 0x1
	// Position of PR85 field.
	EXTI_CPUPR3_PR85_Pos = 0x15
	// Bit mask of PR85 field.
	EXTI_CPUPR3_PR85_Msk = 0x200000
	// Bit PR85.
	EXTI_CPUPR3_PR85 = 0x200000
	// No trigger request occurred
	EXTI_CPUPR3_PR85_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR3_PR85_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR3_PR85_Clear = 0x1
	// Position of PR86 field.
	EXTI_CPUPR3_PR86_Pos = 0x16
	// Bit mask of PR86 field.
	EXTI_CPUPR3_PR86_Msk = 0x400000
	// Bit PR86.
	EXTI_CPUPR3_PR86 = 0x400000
	// No trigger request occurred
	EXTI_CPUPR3_PR86_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_CPUPR3_PR86_Pending = 0x1
	// Clears pending bit
	EXTI_CPUPR3_PR86_Clear = 0x1
)

// Bitfields for DELAY_Block_SDMMC1: DELAY_Block_SDMMC1
const (
	// CR: DLYB control register
	// Position of DEN field.
	DLYB_CR_DEN_Pos = 0x0
	// Bit mask of DEN field.
	DLYB_CR_DEN_Msk = 0x1
	// Bit DEN.
	DLYB_CR_DEN = 0x1
	// Position of SEN field.
	DLYB_CR_SEN_Pos = 0x1
	// Bit mask of SEN field.
	DLYB_CR_SEN_Msk = 0x2
	// Bit SEN.
	DLYB_CR_SEN = 0x2

	// CFGR: DLYB configuration register
	// Position of SEL field.
	DLYB_CFGR_SEL_Pos = 0x0
	// Bit mask of SEL field.
	DLYB_CFGR_SEL_Msk = 0xf
	// Position of UNIT field.
	DLYB_CFGR_UNIT_Pos = 0x8
	// Bit mask of UNIT field.
	DLYB_CFGR_UNIT_Msk = 0x7f00
	// Position of LNG field.
	DLYB_CFGR_LNG_Pos = 0x10
	// Bit mask of LNG field.
	DLYB_CFGR_LNG_Msk = 0xfff0000
	// Position of LNGF field.
	DLYB_CFGR_LNGF_Pos = 0x1f
	// Bit mask of LNGF field.
	DLYB_CFGR_LNGF_Msk = 0x80000000
	// Bit LNGF.
	DLYB_CFGR_LNGF = 0x80000000
)

// Bitfields for FLASH: Flash
const (
	// ACR: Access control register
	// Position of LATENCY field.
	Flash_ACR_LATENCY_Pos = 0x0
	// Bit mask of LATENCY field.
	Flash_ACR_LATENCY_Msk = 0x7
	// Position of WRHIGHFREQ field.
	Flash_ACR_WRHIGHFREQ_Pos = 0x4
	// Bit mask of WRHIGHFREQ field.
	Flash_ACR_WRHIGHFREQ_Msk = 0x30

	// BANK.KEYR: FLASH key register for bank 1
	// Position of KEYR field.
	Flash_BANK_KEYR_KEYR_Pos = 0x0
	// Bit mask of KEYR field.
	Flash_BANK_KEYR_KEYR_Msk = 0xffffffff

	// BANK.CR: FLASH control register for bank 1
	// Position of LOCK field.
	Flash_BANK_CR_LOCK_Pos = 0x0
	// Bit mask of LOCK field.
	Flash_BANK_CR_LOCK_Msk = 0x1
	// Bit LOCK.
	Flash_BANK_CR_LOCK = 0x1
	// Position of PG field.
	Flash_BANK_CR_PG_Pos = 0x1
	// Bit mask of PG field.
	Flash_BANK_CR_PG_Msk = 0x2
	// Bit PG.
	Flash_BANK_CR_PG = 0x2
	// Position of SER field.
	Flash_BANK_CR_SER_Pos = 0x2
	// Bit mask of SER field.
	Flash_BANK_CR_SER_Msk = 0x4
	// Bit SER.
	Flash_BANK_CR_SER = 0x4
	// Position of BER field.
	Flash_BANK_CR_BER_Pos = 0x3
	// Bit mask of BER field.
	Flash_BANK_CR_BER_Msk = 0x8
	// Bit BER.
	Flash_BANK_CR_BER = 0x8
	// Position of PSIZE field.
	Flash_BANK_CR_PSIZE_Pos = 0x4
	// Bit mask of PSIZE field.
	Flash_BANK_CR_PSIZE_Msk = 0x30
	// Position of FW field.
	Flash_BANK_CR_FW_Pos = 0x6
	// Bit mask of FW field.
	Flash_BANK_CR_FW_Msk = 0x40
	// Bit FW.
	Flash_BANK_CR_FW = 0x40
	// Position of START field.
	Flash_BANK_CR_START_Pos = 0x7
	// Bit mask of START field.
	Flash_BANK_CR_START_Msk = 0x80
	// Bit START.
	Flash_BANK_CR_START = 0x80
	// Position of SNB field.
	Flash_BANK_CR_SNB_Pos = 0x8
	// Bit mask of SNB field.
	Flash_BANK_CR_SNB_Msk = 0x700
	// Position of CRC_EN field.
	Flash_BANK_CR_CRC_EN_Pos = 0xf
	// Bit mask of CRC_EN field.
	Flash_BANK_CR_CRC_EN_Msk = 0x8000
	// Bit CRC_EN.
	Flash_BANK_CR_CRC_EN = 0x8000
	// Position of EOPIE field.
	Flash_BANK_CR_EOPIE_Pos = 0x10
	// Bit mask of EOPIE field.
	Flash_BANK_CR_EOPIE_Msk = 0x10000
	// Bit EOPIE.
	Flash_BANK_CR_EOPIE = 0x10000
	// Position of WRPERRIE field.
	Flash_BANK_CR_WRPERRIE_Pos = 0x11
	// Bit mask of WRPERRIE field.
	Flash_BANK_CR_WRPERRIE_Msk = 0x20000
	// Bit WRPERRIE.
	Flash_BANK_CR_WRPERRIE = 0x20000
	// Position of PGSERRIE field.
	Flash_BANK_CR_PGSERRIE_Pos = 0x12
	// Bit mask of PGSERRIE field.
	Flash_BANK_CR_PGSERRIE_Msk = 0x40000
	// Bit PGSERRIE.
	Flash_BANK_CR_PGSERRIE = 0x40000
	// Position of STRBERRIE field.
	Flash_BANK_CR_STRBERRIE_Pos = 0x13
	// Bit mask of STRBERRIE field.
	Flash_BANK_CR_STRBERRIE_Msk = 0x80000
	// Bit STRBERRIE.
	Flash_BANK_CR_STRBERRIE = 0x80000
	// Position of INCERRIE field.
	Flash_BANK_CR_INCERRIE_Pos = 0x15
	// Bit mask of INCERRIE field.
	Flash_BANK_CR_INCERRIE_Msk = 0x200000
	// Bit INCERRIE.
	Flash_BANK_CR_INCERRIE = 0x200000
	// Position of OPERRIE field.
	Flash_BANK_CR_OPERRIE_Pos = 0x16
	// Bit mask of OPERRIE field.
	Flash_BANK_CR_OPERRIE_Msk = 0x400000
	// Bit OPERRIE.
	Flash_BANK_CR_OPERRIE = 0x400000
	// Position of RDPERRIE field.
	Flash_BANK_CR_RDPERRIE_Pos = 0x17
	// Bit mask of RDPERRIE field.
	Flash_BANK_CR_RDPERRIE_Msk = 0x800000
	// Bit RDPERRIE.
	Flash_BANK_CR_RDPERRIE = 0x800000
	// Position of RDSERRIE field.
	Flash_BANK_CR_RDSERRIE_Pos = 0x18
	// Bit mask of RDSERRIE field.
	Flash_BANK_CR_RDSERRIE_Msk = 0x1000000
	// Bit RDSERRIE.
	Flash_BANK_CR_RDSERRIE = 0x1000000
	// Position of SNECCERRIE field.
	Flash_BANK_CR_SNECCERRIE_Pos = 0x19
	// Bit mask of SNECCERRIE field.
	Flash_BANK_CR_SNECCERRIE_Msk = 0x2000000
	// Bit SNECCERRIE.
	Flash_BANK_CR_SNECCERRIE = 0x2000000
	// Position of DBECCERRIE field.
	Flash_BANK_CR_DBECCERRIE_Pos = 0x1a
	// Bit mask of DBECCERRIE field.
	Flash_BANK_CR_DBECCERRIE_Msk = 0x4000000
	// Bit DBECCERRIE.
	Flash_BANK_CR_DBECCERRIE = 0x4000000
	// Position of CRCENDIE field.
	Flash_BANK_CR_CRCENDIE_Pos = 0x1b
	// Bit mask of CRCENDIE field.
	Flash_BANK_CR_CRCENDIE_Msk = 0x8000000
	// Bit CRCENDIE.
	Flash_BANK_CR_CRCENDIE = 0x8000000

	// BANK.SR: FLASH status register for bank 1
	// Position of BSY field.
	Flash_BANK_SR_BSY_Pos = 0x0
	// Bit mask of BSY field.
	Flash_BANK_SR_BSY_Msk = 0x1
	// Bit BSY.
	Flash_BANK_SR_BSY = 0x1
	// Position of WBNE field.
	Flash_BANK_SR_WBNE_Pos = 0x1
	// Bit mask of WBNE field.
	Flash_BANK_SR_WBNE_Msk = 0x2
	// Bit WBNE.
	Flash_BANK_SR_WBNE = 0x2
	// Position of QW field.
	Flash_BANK_SR_QW_Pos = 0x2
	// Bit mask of QW field.
	Flash_BANK_SR_QW_Msk = 0x4
	// Bit QW.
	Flash_BANK_SR_QW = 0x4
	// Position of CRC_BUSY field.
	Flash_BANK_SR_CRC_BUSY_Pos = 0x3
	// Bit mask of CRC_BUSY field.
	Flash_BANK_SR_CRC_BUSY_Msk = 0x8
	// Bit CRC_BUSY.
	Flash_BANK_SR_CRC_BUSY = 0x8
	// Position of EOP field.
	Flash_BANK_SR_EOP_Pos = 0x10
	// Bit mask of EOP field.
	Flash_BANK_SR_EOP_Msk = 0x10000
	// Bit EOP.
	Flash_BANK_SR_EOP = 0x10000
	// Position of WRPERR field.
	Flash_BANK_SR_WRPERR_Pos = 0x11
	// Bit mask of WRPERR field.
	Flash_BANK_SR_WRPERR_Msk = 0x20000
	// Bit WRPERR.
	Flash_BANK_SR_WRPERR = 0x20000
	// Position of PGSERR field.
	Flash_BANK_SR_PGSERR_Pos = 0x12
	// Bit mask of PGSERR field.
	Flash_BANK_SR_PGSERR_Msk = 0x40000
	// Bit PGSERR.
	Flash_BANK_SR_PGSERR = 0x40000
	// Position of STRBERR field.
	Flash_BANK_SR_STRBERR_Pos = 0x13
	// Bit mask of STRBERR field.
	Flash_BANK_SR_STRBERR_Msk = 0x80000
	// Bit STRBERR.
	Flash_BANK_SR_STRBERR = 0x80000
	// Position of INCERR field.
	Flash_BANK_SR_INCERR_Pos = 0x15
	// Bit mask of INCERR field.
	Flash_BANK_SR_INCERR_Msk = 0x200000
	// Bit INCERR.
	Flash_BANK_SR_INCERR = 0x200000
	// Position of OPERR field.
	Flash_BANK_SR_OPERR_Pos = 0x16
	// Bit mask of OPERR field.
	Flash_BANK_SR_OPERR_Msk = 0x400000
	// Bit OPERR.
	Flash_BANK_SR_OPERR = 0x400000
	// Position of RDPERR field.
	Flash_BANK_SR_RDPERR_Pos = 0x17
	// Bit mask of RDPERR field.
	Flash_BANK_SR_RDPERR_Msk = 0x800000
	// Bit RDPERR.
	Flash_BANK_SR_RDPERR = 0x800000
	// Position of RDSERR field.
	Flash_BANK_SR_RDSERR_Pos = 0x18
	// Bit mask of RDSERR field.
	Flash_BANK_SR_RDSERR_Msk = 0x1000000
	// Bit RDSERR.
	Flash_BANK_SR_RDSERR = 0x1000000
	// Position of SNECCERR1 field.
	Flash_BANK_SR_SNECCERR1_Pos = 0x19
	// Bit mask of SNECCERR1 field.
	Flash_BANK_SR_SNECCERR1_Msk = 0x2000000
	// Bit SNECCERR1.
	Flash_BANK_SR_SNECCERR1 = 0x2000000
	// Position of DBECCERR field.
	Flash_BANK_SR_DBECCERR_Pos = 0x1a
	// Bit mask of DBECCERR field.
	Flash_BANK_SR_DBECCERR_Msk = 0x4000000
	// Bit DBECCERR.
	Flash_BANK_SR_DBECCERR = 0x4000000
	// Position of CRCEND field.
	Flash_BANK_SR_CRCEND_Pos = 0x1b
	// Bit mask of CRCEND field.
	Flash_BANK_SR_CRCEND_Msk = 0x8000000
	// Bit CRCEND.
	Flash_BANK_SR_CRCEND = 0x8000000

	// BANK.CCR: FLASH clear control register for bank 1
	// Position of CLR_EOP field.
	Flash_BANK_CCR_CLR_EOP_Pos = 0x10
	// Bit mask of CLR_EOP field.
	Flash_BANK_CCR_CLR_EOP_Msk = 0x10000
	// Bit CLR_EOP.
	Flash_BANK_CCR_CLR_EOP = 0x10000
	// Position of CLR_WRPERR field.
	Flash_BANK_CCR_CLR_WRPERR_Pos = 0x11
	// Bit mask of CLR_WRPERR field.
	Flash_BANK_CCR_CLR_WRPERR_Msk = 0x20000
	// Bit CLR_WRPERR.
	Flash_BANK_CCR_CLR_WRPERR = 0x20000
	// Position of CLR_PGSERR field.
	Flash_BANK_CCR_CLR_PGSERR_Pos = 0x12
	// Bit mask of CLR_PGSERR field.
	Flash_BANK_CCR_CLR_PGSERR_Msk = 0x40000
	// Bit CLR_PGSERR.
	Flash_BANK_CCR_CLR_PGSERR = 0x40000
	// Position of CLR_STRBERR field.
	Flash_BANK_CCR_CLR_STRBERR_Pos = 0x13
	// Bit mask of CLR_STRBERR field.
	Flash_BANK_CCR_CLR_STRBERR_Msk = 0x80000
	// Bit CLR_STRBERR.
	Flash_BANK_CCR_CLR_STRBERR = 0x80000
	// Position of CLR_INCERR field.
	Flash_BANK_CCR_CLR_INCERR_Pos = 0x15
	// Bit mask of CLR_INCERR field.
	Flash_BANK_CCR_CLR_INCERR_Msk = 0x200000
	// Bit CLR_INCERR.
	Flash_BANK_CCR_CLR_INCERR = 0x200000
	// Position of CLR_OPERR field.
	Flash_BANK_CCR_CLR_OPERR_Pos = 0x16
	// Bit mask of CLR_OPERR field.
	Flash_BANK_CCR_CLR_OPERR_Msk = 0x400000
	// Bit CLR_OPERR.
	Flash_BANK_CCR_CLR_OPERR = 0x400000
	// Position of CLR_RDPERR field.
	Flash_BANK_CCR_CLR_RDPERR_Pos = 0x17
	// Bit mask of CLR_RDPERR field.
	Flash_BANK_CCR_CLR_RDPERR_Msk = 0x800000
	// Bit CLR_RDPERR.
	Flash_BANK_CCR_CLR_RDPERR = 0x800000
	// Position of CLR_RDSERR field.
	Flash_BANK_CCR_CLR_RDSERR_Pos = 0x18
	// Bit mask of CLR_RDSERR field.
	Flash_BANK_CCR_CLR_RDSERR_Msk = 0x1000000
	// Bit CLR_RDSERR.
	Flash_BANK_CCR_CLR_RDSERR = 0x1000000
	// Position of CLR_SNECCERR field.
	Flash_BANK_CCR_CLR_SNECCERR_Pos = 0x19
	// Bit mask of CLR_SNECCERR field.
	Flash_BANK_CCR_CLR_SNECCERR_Msk = 0x2000000
	// Bit CLR_SNECCERR.
	Flash_BANK_CCR_CLR_SNECCERR = 0x2000000
	// Position of CLR_DBECCERR field.
	Flash_BANK_CCR_CLR_DBECCERR_Pos = 0x1a
	// Bit mask of CLR_DBECCERR field.
	Flash_BANK_CCR_CLR_DBECCERR_Msk = 0x4000000
	// Bit CLR_DBECCERR.
	Flash_BANK_CCR_CLR_DBECCERR = 0x4000000
	// Position of CLR_CRCEND field.
	Flash_BANK_CCR_CLR_CRCEND_Pos = 0x1b
	// Bit mask of CLR_CRCEND field.
	Flash_BANK_CCR_CLR_CRCEND_Msk = 0x8000000
	// Bit CLR_CRCEND.
	Flash_BANK_CCR_CLR_CRCEND = 0x8000000

	// BANK.PRAR_CUR: FLASH protection address for bank 1
	// Position of PROT_AREA_START field.
	Flash_BANK_PRAR_CUR_PROT_AREA_START_Pos = 0x0
	// Bit mask of PROT_AREA_START field.
	Flash_BANK_PRAR_CUR_PROT_AREA_START_Msk = 0xfff
	// Position of PROT_AREA_END field.
	Flash_BANK_PRAR_CUR_PROT_AREA_END_Pos = 0x10
	// Bit mask of PROT_AREA_END field.
	Flash_BANK_PRAR_CUR_PROT_AREA_END_Msk = 0xfff0000
	// Position of DMEP field.
	Flash_BANK_PRAR_CUR_DMEP_Pos = 0x1f
	// Bit mask of DMEP field.
	Flash_BANK_PRAR_CUR_DMEP_Msk = 0x80000000
	// Bit DMEP.
	Flash_BANK_PRAR_CUR_DMEP = 0x80000000

	// BANK.PRAR_PRG: FLASH protection address for bank 1
	// Position of PROT_AREA_START field.
	Flash_BANK_PRAR_PRG_PROT_AREA_START_Pos = 0x0
	// Bit mask of PROT_AREA_START field.
	Flash_BANK_PRAR_PRG_PROT_AREA_START_Msk = 0xfff
	// Position of PROT_AREA_END field.
	Flash_BANK_PRAR_PRG_PROT_AREA_END_Pos = 0x10
	// Bit mask of PROT_AREA_END field.
	Flash_BANK_PRAR_PRG_PROT_AREA_END_Msk = 0xfff0000
	// Position of DMEP field.
	Flash_BANK_PRAR_PRG_DMEP_Pos = 0x1f
	// Bit mask of DMEP field.
	Flash_BANK_PRAR_PRG_DMEP_Msk = 0x80000000
	// Bit DMEP.
	Flash_BANK_PRAR_PRG_DMEP = 0x80000000

	// BANK.SCAR_CUR: FLASH secure address for bank 1
	// Position of SEC_AREA_START field.
	Flash_BANK_SCAR_CUR_SEC_AREA_START_Pos = 0x0
	// Bit mask of SEC_AREA_START field.
	Flash_BANK_SCAR_CUR_SEC_AREA_START_Msk = 0xfff
	// Position of SEC_AREA_END field.
	Flash_BANK_SCAR_CUR_SEC_AREA_END_Pos = 0x10
	// Bit mask of SEC_AREA_END field.
	Flash_BANK_SCAR_CUR_SEC_AREA_END_Msk = 0xfff0000
	// Position of DMES field.
	Flash_BANK_SCAR_CUR_DMES_Pos = 0x1f
	// Bit mask of DMES field.
	Flash_BANK_SCAR_CUR_DMES_Msk = 0x80000000
	// Bit DMES.
	Flash_BANK_SCAR_CUR_DMES = 0x80000000

	// BANK.SCAR_PRG: FLASH secure address for bank 1
	// Position of SEC_AREA_START field.
	Flash_BANK_SCAR_PRG_SEC_AREA_START_Pos = 0x0
	// Bit mask of SEC_AREA_START field.
	Flash_BANK_SCAR_PRG_SEC_AREA_START_Msk = 0xfff
	// Position of SEC_AREA_END field.
	Flash_BANK_SCAR_PRG_SEC_AREA_END_Pos = 0x10
	// Bit mask of SEC_AREA_END field.
	Flash_BANK_SCAR_PRG_SEC_AREA_END_Msk = 0xfff0000
	// Position of DMES field.
	Flash_BANK_SCAR_PRG_DMES_Pos = 0x1f
	// Bit mask of DMES field.
	Flash_BANK_SCAR_PRG_DMES_Msk = 0x80000000
	// Bit DMES.
	Flash_BANK_SCAR_PRG_DMES = 0x80000000

	// BANK.WPSN_CURR: FLASH write sector protection for bank 1
	// Position of WRPSn field.
	Flash_BANK_WPSN_CURR_WRPSn_Pos = 0x0
	// Bit mask of WRPSn field.
	Flash_BANK_WPSN_CURR_WRPSn_Msk = 0xff

	// BANK.WPSN_PRGR: FLASH write sector protection for bank 1
	// Position of WRPSn field.
	Flash_BANK_WPSN_PRGR_WRPSn_Pos = 0x0
	// Bit mask of WRPSn field.
	Flash_BANK_WPSN_PRGR_WRPSn_Msk = 0xff

	// BANK.CRCCR: FLASH CRC control register for bank 1
	// Position of CRC_SECT field.
	Flash_BANK_CRCCR_CRC_SECT_Pos = 0x0
	// Bit mask of CRC_SECT field.
	Flash_BANK_CRCCR_CRC_SECT_Msk = 0x7
	// Position of ALL_BANK field.
	Flash_BANK_CRCCR_ALL_BANK_Pos = 0x7
	// Bit mask of ALL_BANK field.
	Flash_BANK_CRCCR_ALL_BANK_Msk = 0x80
	// Bit ALL_BANK.
	Flash_BANK_CRCCR_ALL_BANK = 0x80
	// Position of CRC_BY_SECT field.
	Flash_BANK_CRCCR_CRC_BY_SECT_Pos = 0x8
	// Bit mask of CRC_BY_SECT field.
	Flash_BANK_CRCCR_CRC_BY_SECT_Msk = 0x100
	// Bit CRC_BY_SECT.
	Flash_BANK_CRCCR_CRC_BY_SECT = 0x100
	// Position of ADD_SECT field.
	Flash_BANK_CRCCR_ADD_SECT_Pos = 0x9
	// Bit mask of ADD_SECT field.
	Flash_BANK_CRCCR_ADD_SECT_Msk = 0x200
	// Bit ADD_SECT.
	Flash_BANK_CRCCR_ADD_SECT = 0x200
	// Position of CLEAN_SECT field.
	Flash_BANK_CRCCR_CLEAN_SECT_Pos = 0xa
	// Bit mask of CLEAN_SECT field.
	Flash_BANK_CRCCR_CLEAN_SECT_Msk = 0x400
	// Bit CLEAN_SECT.
	Flash_BANK_CRCCR_CLEAN_SECT = 0x400
	// Position of START_CRC field.
	Flash_BANK_CRCCR_START_CRC_Pos = 0x10
	// Bit mask of START_CRC field.
	Flash_BANK_CRCCR_START_CRC_Msk = 0x10000
	// Bit START_CRC.
	Flash_BANK_CRCCR_START_CRC = 0x10000
	// Position of CLEAN_CRC field.
	Flash_BANK_CRCCR_CLEAN_CRC_Pos = 0x11
	// Bit mask of CLEAN_CRC field.
	Flash_BANK_CRCCR_CLEAN_CRC_Msk = 0x20000
	// Bit CLEAN_CRC.
	Flash_BANK_CRCCR_CLEAN_CRC = 0x20000
	// Position of CRC_BURST field.
	Flash_BANK_CRCCR_CRC_BURST_Pos = 0x14
	// Bit mask of CRC_BURST field.
	Flash_BANK_CRCCR_CRC_BURST_Msk = 0x300000

	// BANK.CRCSADDR: FLASH CRC start address register for bank 1
	// Position of CRC_START_ADDR field.
	Flash_BANK_CRCSADDR_CRC_START_ADDR_Pos = 0x0
	// Bit mask of CRC_START_ADDR field.
	Flash_BANK_CRCSADDR_CRC_START_ADDR_Msk = 0xffffffff

	// BANK.CRCEADDR: FLASH CRC end address register for bank 1
	// Position of CRC_END_ADDR field.
	Flash_BANK_CRCEADDR_CRC_END_ADDR_Pos = 0x0
	// Bit mask of CRC_END_ADDR field.
	Flash_BANK_CRCEADDR_CRC_END_ADDR_Msk = 0xffffffff

	// BANK.FAR: FLASH ECC fail address for bank 1
	// Position of FAIL_ECC_ADDR field.
	Flash_BANK_FAR_FAIL_ECC_ADDR_Pos = 0x0
	// Bit mask of FAIL_ECC_ADDR field.
	Flash_BANK_FAR_FAIL_ECC_ADDR_Msk = 0x7fff

	// OPTKEYR: FLASH option key register
	// Position of OPTKEYR field.
	Flash_OPTKEYR_OPTKEYR_Pos = 0x0
	// Bit mask of OPTKEYR field.
	Flash_OPTKEYR_OPTKEYR_Msk = 0xffffffff

	// OPTCR: FLASH option control register
	// Position of OPTLOCK field.
	Flash_OPTCR_OPTLOCK_Pos = 0x0
	// Bit mask of OPTLOCK field.
	Flash_OPTCR_OPTLOCK_Msk = 0x1
	// Bit OPTLOCK.
	Flash_OPTCR_OPTLOCK = 0x1
	// Position of OPTSTART field.
	Flash_OPTCR_OPTSTART_Pos = 0x1
	// Bit mask of OPTSTART field.
	Flash_OPTCR_OPTSTART_Msk = 0x2
	// Bit OPTSTART.
	Flash_OPTCR_OPTSTART = 0x2
	// Position of MER field.
	Flash_OPTCR_MER_Pos = 0x4
	// Bit mask of MER field.
	Flash_OPTCR_MER_Msk = 0x10
	// Bit MER.
	Flash_OPTCR_MER = 0x10
	// Position of OPTCHANGEERRIE field.
	Flash_OPTCR_OPTCHANGEERRIE_Pos = 0x1e
	// Bit mask of OPTCHANGEERRIE field.
	Flash_OPTCR_OPTCHANGEERRIE_Msk = 0x40000000
	// Bit OPTCHANGEERRIE.
	Flash_OPTCR_OPTCHANGEERRIE = 0x40000000
	// Position of SWAP_BANK field.
	Flash_OPTCR_SWAP_BANK_Pos = 0x1f
	// Bit mask of SWAP_BANK field.
	Flash_OPTCR_SWAP_BANK_Msk = 0x80000000
	// Bit SWAP_BANK.
	Flash_OPTCR_SWAP_BANK = 0x80000000

	// OPTSR_CUR: FLASH option status register
	// Position of OPT_BUSY field.
	Flash_OPTSR_CUR_OPT_BUSY_Pos = 0x0
	// Bit mask of OPT_BUSY field.
	Flash_OPTSR_CUR_OPT_BUSY_Msk = 0x1
	// Bit OPT_BUSY.
	Flash_OPTSR_CUR_OPT_BUSY = 0x1
	// Position of BOR_LEV field.
	Flash_OPTSR_CUR_BOR_LEV_Pos = 0x2
	// Bit mask of BOR_LEV field.
	Flash_OPTSR_CUR_BOR_LEV_Msk = 0xc
	// Position of IWDG1_HW field.
	Flash_OPTSR_CUR_IWDG1_HW_Pos = 0x4
	// Bit mask of IWDG1_HW field.
	Flash_OPTSR_CUR_IWDG1_HW_Msk = 0x10
	// Bit IWDG1_HW.
	Flash_OPTSR_CUR_IWDG1_HW = 0x10
	// Position of NRST_STOP_D1 field.
	Flash_OPTSR_CUR_NRST_STOP_D1_Pos = 0x6
	// Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_CUR_NRST_STOP_D1_Msk = 0x40
	// Bit NRST_STOP_D1.
	Flash_OPTSR_CUR_NRST_STOP_D1 = 0x40
	// Position of NRST_STBY_D1 field.
	Flash_OPTSR_CUR_NRST_STBY_D1_Pos = 0x7
	// Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_CUR_NRST_STBY_D1_Msk = 0x80
	// Bit NRST_STBY_D1.
	Flash_OPTSR_CUR_NRST_STBY_D1 = 0x80
	// Position of RDP field.
	Flash_OPTSR_CUR_RDP_Pos = 0x8
	// Bit mask of RDP field.
	Flash_OPTSR_CUR_RDP_Msk = 0xff00
	// Position of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR_FZ_IWDG_STOP_Pos = 0x11
	// Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR_FZ_IWDG_STOP_Msk = 0x20000
	// Bit FZ_IWDG_STOP.
	Flash_OPTSR_CUR_FZ_IWDG_STOP = 0x20000
	// Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR_FZ_IWDG_SDBY_Pos = 0x12
	// Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR_FZ_IWDG_SDBY_Msk = 0x40000
	// Bit FZ_IWDG_SDBY.
	Flash_OPTSR_CUR_FZ_IWDG_SDBY = 0x40000
	// Position of ST_RAM_SIZE field.
	Flash_OPTSR_CUR_ST_RAM_SIZE_Pos = 0x13
	// Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_CUR_ST_RAM_SIZE_Msk = 0x180000
	// Position of SECURITY field.
	Flash_OPTSR_CUR_SECURITY_Pos = 0x15
	// Bit mask of SECURITY field.
	Flash_OPTSR_CUR_SECURITY_Msk = 0x200000
	// Bit SECURITY.
	Flash_OPTSR_CUR_SECURITY = 0x200000
	// Position of RSS1 field.
	Flash_OPTSR_CUR_RSS1_Pos = 0x1a
	// Bit mask of RSS1 field.
	Flash_OPTSR_CUR_RSS1_Msk = 0x4000000
	// Bit RSS1.
	Flash_OPTSR_CUR_RSS1 = 0x4000000
	// Position of PERSO_OK field.
	Flash_OPTSR_CUR_PERSO_OK_Pos = 0x1c
	// Bit mask of PERSO_OK field.
	Flash_OPTSR_CUR_PERSO_OK_Msk = 0x10000000
	// Bit PERSO_OK.
	Flash_OPTSR_CUR_PERSO_OK = 0x10000000
	// Position of IO_HSLV field.
	Flash_OPTSR_CUR_IO_HSLV_Pos = 0x1d
	// Bit mask of IO_HSLV field.
	Flash_OPTSR_CUR_IO_HSLV_Msk = 0x20000000
	// Bit IO_HSLV.
	Flash_OPTSR_CUR_IO_HSLV = 0x20000000
	// Position of OPTCHANGEERR field.
	Flash_OPTSR_CUR_OPTCHANGEERR_Pos = 0x1e
	// Bit mask of OPTCHANGEERR field.
	Flash_OPTSR_CUR_OPTCHANGEERR_Msk = 0x40000000
	// Bit OPTCHANGEERR.
	Flash_OPTSR_CUR_OPTCHANGEERR = 0x40000000
	// Position of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR_SWAP_BANK_OPT_Pos = 0x1f
	// Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR_SWAP_BANK_OPT_Msk = 0x80000000
	// Bit SWAP_BANK_OPT.
	Flash_OPTSR_CUR_SWAP_BANK_OPT = 0x80000000

	// OPTSR_PRG: FLASH option status register
	// Position of BOR_LEV field.
	Flash_OPTSR_PRG_BOR_LEV_Pos = 0x2
	// Bit mask of BOR_LEV field.
	Flash_OPTSR_PRG_BOR_LEV_Msk = 0xc
	// Position of IWDG1_HW field.
	Flash_OPTSR_PRG_IWDG1_HW_Pos = 0x4
	// Bit mask of IWDG1_HW field.
	Flash_OPTSR_PRG_IWDG1_HW_Msk = 0x10
	// Bit IWDG1_HW.
	Flash_OPTSR_PRG_IWDG1_HW = 0x10
	// Position of NRST_STOP_D1 field.
	Flash_OPTSR_PRG_NRST_STOP_D1_Pos = 0x6
	// Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_PRG_NRST_STOP_D1_Msk = 0x40
	// Bit NRST_STOP_D1.
	Flash_OPTSR_PRG_NRST_STOP_D1 = 0x40
	// Position of NRST_STBY_D1 field.
	Flash_OPTSR_PRG_NRST_STBY_D1_Pos = 0x7
	// Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_PRG_NRST_STBY_D1_Msk = 0x80
	// Bit NRST_STBY_D1.
	Flash_OPTSR_PRG_NRST_STBY_D1 = 0x80
	// Position of RDP field.
	Flash_OPTSR_PRG_RDP_Pos = 0x8
	// Bit mask of RDP field.
	Flash_OPTSR_PRG_RDP_Msk = 0xff00
	// Position of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG_FZ_IWDG_STOP_Pos = 0x11
	// Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG_FZ_IWDG_STOP_Msk = 0x20000
	// Bit FZ_IWDG_STOP.
	Flash_OPTSR_PRG_FZ_IWDG_STOP = 0x20000
	// Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG_FZ_IWDG_SDBY_Pos = 0x12
	// Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG_FZ_IWDG_SDBY_Msk = 0x40000
	// Bit FZ_IWDG_SDBY.
	Flash_OPTSR_PRG_FZ_IWDG_SDBY = 0x40000
	// Position of ST_RAM_SIZE field.
	Flash_OPTSR_PRG_ST_RAM_SIZE_Pos = 0x13
	// Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_PRG_ST_RAM_SIZE_Msk = 0x180000
	// Position of SECURITY field.
	Flash_OPTSR_PRG_SECURITY_Pos = 0x15
	// Bit mask of SECURITY field.
	Flash_OPTSR_PRG_SECURITY_Msk = 0x200000
	// Bit SECURITY.
	Flash_OPTSR_PRG_SECURITY = 0x200000
	// Position of RSS1 field.
	Flash_OPTSR_PRG_RSS1_Pos = 0x1a
	// Bit mask of RSS1 field.
	Flash_OPTSR_PRG_RSS1_Msk = 0x4000000
	// Bit RSS1.
	Flash_OPTSR_PRG_RSS1 = 0x4000000
	// Position of RSS2 field.
	Flash_OPTSR_PRG_RSS2_Pos = 0x1b
	// Bit mask of RSS2 field.
	Flash_OPTSR_PRG_RSS2_Msk = 0x8000000
	// Bit RSS2.
	Flash_OPTSR_PRG_RSS2 = 0x8000000
	// Position of IO_HSLV field.
	Flash_OPTSR_PRG_IO_HSLV_Pos = 0x1d
	// Bit mask of IO_HSLV field.
	Flash_OPTSR_PRG_IO_HSLV_Msk = 0x20000000
	// Bit IO_HSLV.
	Flash_OPTSR_PRG_IO_HSLV = 0x20000000
	// Position of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG_SWAP_BANK_OPT_Pos = 0x1f
	// Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG_SWAP_BANK_OPT_Msk = 0x80000000
	// Bit SWAP_BANK_OPT.
	Flash_OPTSR_PRG_SWAP_BANK_OPT = 0x80000000

	// OPTCCR: FLASH option clear control register
	// Position of CLR_OPTCHANGEERR field.
	Flash_OPTCCR_CLR_OPTCHANGEERR_Pos = 0x1e
	// Bit mask of CLR_OPTCHANGEERR field.
	Flash_OPTCCR_CLR_OPTCHANGEERR_Msk = 0x40000000
	// Bit CLR_OPTCHANGEERR.
	Flash_OPTCCR_CLR_OPTCHANGEERR = 0x40000000

	// BOOT_CURR: FLASH register with boot address
	// Position of BOOT_ADD0 field.
	Flash_BOOT_CURR_BOOT_ADD0_Pos = 0x0
	// Bit mask of BOOT_ADD0 field.
	Flash_BOOT_CURR_BOOT_ADD0_Msk = 0xffff
	// Position of BOOT_ADD1 field.
	Flash_BOOT_CURR_BOOT_ADD1_Pos = 0x10
	// Bit mask of BOOT_ADD1 field.
	Flash_BOOT_CURR_BOOT_ADD1_Msk = 0xffff0000

	// BOOT_PRGR: FLASH register with boot address
	// Position of BOOT_ADD0 field.
	Flash_BOOT_PRGR_BOOT_ADD0_Pos = 0x0
	// Bit mask of BOOT_ADD0 field.
	Flash_BOOT_PRGR_BOOT_ADD0_Msk = 0xffff
	// Position of BOOT_ADD1 field.
	Flash_BOOT_PRGR_BOOT_ADD1_Pos = 0x10
	// Bit mask of BOOT_ADD1 field.
	Flash_BOOT_PRGR_BOOT_ADD1_Msk = 0xffff0000

	// CRCDATAR: FLASH CRC data register
	// Position of CRC_DATA field.
	Flash_CRCDATAR_CRC_DATA_Pos = 0x0
	// Bit mask of CRC_DATA field.
	Flash_CRCDATAR_CRC_DATA_Msk = 0xffffffff

	// ACR_: Access control register
	// Position of LATENCY field.
	Flash_ACR__LATENCY_Pos = 0x0
	// Bit mask of LATENCY field.
	Flash_ACR__LATENCY_Msk = 0x7
	// Position of WRHIGHFREQ field.
	Flash_ACR__WRHIGHFREQ_Pos = 0x4
	// Bit mask of WRHIGHFREQ field.
	Flash_ACR__WRHIGHFREQ_Msk = 0x30

	// OPTKEYR_: FLASH option key register
	// Position of OPTKEYR field.
	Flash_OPTKEYR__OPTKEYR_Pos = 0x0
	// Bit mask of OPTKEYR field.
	Flash_OPTKEYR__OPTKEYR_Msk = 0xffffffff

	// OPTCR_: FLASH option control register
	// Position of OPTLOCK field.
	Flash_OPTCR__OPTLOCK_Pos = 0x0
	// Bit mask of OPTLOCK field.
	Flash_OPTCR__OPTLOCK_Msk = 0x1
	// Bit OPTLOCK.
	Flash_OPTCR__OPTLOCK = 0x1
	// Position of OPTSTART field.
	Flash_OPTCR__OPTSTART_Pos = 0x1
	// Bit mask of OPTSTART field.
	Flash_OPTCR__OPTSTART_Msk = 0x2
	// Bit OPTSTART.
	Flash_OPTCR__OPTSTART = 0x2
	// Position of MER field.
	Flash_OPTCR__MER_Pos = 0x4
	// Bit mask of MER field.
	Flash_OPTCR__MER_Msk = 0x10
	// Bit MER.
	Flash_OPTCR__MER = 0x10
	// Position of OPTCHANGEERRIE field.
	Flash_OPTCR__OPTCHANGEERRIE_Pos = 0x1e
	// Bit mask of OPTCHANGEERRIE field.
	Flash_OPTCR__OPTCHANGEERRIE_Msk = 0x40000000
	// Bit OPTCHANGEERRIE.
	Flash_OPTCR__OPTCHANGEERRIE = 0x40000000
	// Position of SWAP_BANK field.
	Flash_OPTCR__SWAP_BANK_Pos = 0x1f
	// Bit mask of SWAP_BANK field.
	Flash_OPTCR__SWAP_BANK_Msk = 0x80000000
	// Bit SWAP_BANK.
	Flash_OPTCR__SWAP_BANK = 0x80000000

	// OPTSR_CUR_: FLASH option status register
	// Position of OPT_BUSY field.
	Flash_OPTSR_CUR__OPT_BUSY_Pos = 0x0
	// Bit mask of OPT_BUSY field.
	Flash_OPTSR_CUR__OPT_BUSY_Msk = 0x1
	// Bit OPT_BUSY.
	Flash_OPTSR_CUR__OPT_BUSY = 0x1
	// Position of BOR_LEV field.
	Flash_OPTSR_CUR__BOR_LEV_Pos = 0x2
	// Bit mask of BOR_LEV field.
	Flash_OPTSR_CUR__BOR_LEV_Msk = 0xc
	// Position of IWDG1_HW field.
	Flash_OPTSR_CUR__IWDG1_HW_Pos = 0x4
	// Bit mask of IWDG1_HW field.
	Flash_OPTSR_CUR__IWDG1_HW_Msk = 0x10
	// Bit IWDG1_HW.
	Flash_OPTSR_CUR__IWDG1_HW = 0x10
	// Position of NRST_STOP_D1 field.
	Flash_OPTSR_CUR__NRST_STOP_D1_Pos = 0x6
	// Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_CUR__NRST_STOP_D1_Msk = 0x40
	// Bit NRST_STOP_D1.
	Flash_OPTSR_CUR__NRST_STOP_D1 = 0x40
	// Position of NRST_STBY_D1 field.
	Flash_OPTSR_CUR__NRST_STBY_D1_Pos = 0x7
	// Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_CUR__NRST_STBY_D1_Msk = 0x80
	// Bit NRST_STBY_D1.
	Flash_OPTSR_CUR__NRST_STBY_D1 = 0x80
	// Position of RDP field.
	Flash_OPTSR_CUR__RDP_Pos = 0x8
	// Bit mask of RDP field.
	Flash_OPTSR_CUR__RDP_Msk = 0xff00
	// Position of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR__FZ_IWDG_STOP_Pos = 0x11
	// Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR__FZ_IWDG_STOP_Msk = 0x20000
	// Bit FZ_IWDG_STOP.
	Flash_OPTSR_CUR__FZ_IWDG_STOP = 0x20000
	// Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR__FZ_IWDG_SDBY_Pos = 0x12
	// Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR__FZ_IWDG_SDBY_Msk = 0x40000
	// Bit FZ_IWDG_SDBY.
	Flash_OPTSR_CUR__FZ_IWDG_SDBY = 0x40000
	// Position of ST_RAM_SIZE field.
	Flash_OPTSR_CUR__ST_RAM_SIZE_Pos = 0x13
	// Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_CUR__ST_RAM_SIZE_Msk = 0x180000
	// Position of SECURITY field.
	Flash_OPTSR_CUR__SECURITY_Pos = 0x15
	// Bit mask of SECURITY field.
	Flash_OPTSR_CUR__SECURITY_Msk = 0x200000
	// Bit SECURITY.
	Flash_OPTSR_CUR__SECURITY = 0x200000
	// Position of RSS1 field.
	Flash_OPTSR_CUR__RSS1_Pos = 0x1a
	// Bit mask of RSS1 field.
	Flash_OPTSR_CUR__RSS1_Msk = 0x4000000
	// Bit RSS1.
	Flash_OPTSR_CUR__RSS1 = 0x4000000
	// Position of PERSO_OK field.
	Flash_OPTSR_CUR__PERSO_OK_Pos = 0x1c
	// Bit mask of PERSO_OK field.
	Flash_OPTSR_CUR__PERSO_OK_Msk = 0x10000000
	// Bit PERSO_OK.
	Flash_OPTSR_CUR__PERSO_OK = 0x10000000
	// Position of IO_HSLV field.
	Flash_OPTSR_CUR__IO_HSLV_Pos = 0x1d
	// Bit mask of IO_HSLV field.
	Flash_OPTSR_CUR__IO_HSLV_Msk = 0x20000000
	// Bit IO_HSLV.
	Flash_OPTSR_CUR__IO_HSLV = 0x20000000
	// Position of OPTCHANGEERR field.
	Flash_OPTSR_CUR__OPTCHANGEERR_Pos = 0x1e
	// Bit mask of OPTCHANGEERR field.
	Flash_OPTSR_CUR__OPTCHANGEERR_Msk = 0x40000000
	// Bit OPTCHANGEERR.
	Flash_OPTSR_CUR__OPTCHANGEERR = 0x40000000
	// Position of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR__SWAP_BANK_OPT_Pos = 0x1f
	// Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR__SWAP_BANK_OPT_Msk = 0x80000000
	// Bit SWAP_BANK_OPT.
	Flash_OPTSR_CUR__SWAP_BANK_OPT = 0x80000000

	// OPTSR_PRG_: FLASH option status register
	// Position of BOR_LEV field.
	Flash_OPTSR_PRG__BOR_LEV_Pos = 0x2
	// Bit mask of BOR_LEV field.
	Flash_OPTSR_PRG__BOR_LEV_Msk = 0xc
	// Position of IWDG1_HW field.
	Flash_OPTSR_PRG__IWDG1_HW_Pos = 0x4
	// Bit mask of IWDG1_HW field.
	Flash_OPTSR_PRG__IWDG1_HW_Msk = 0x10
	// Bit IWDG1_HW.
	Flash_OPTSR_PRG__IWDG1_HW = 0x10
	// Position of NRST_STOP_D1 field.
	Flash_OPTSR_PRG__NRST_STOP_D1_Pos = 0x6
	// Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_PRG__NRST_STOP_D1_Msk = 0x40
	// Bit NRST_STOP_D1.
	Flash_OPTSR_PRG__NRST_STOP_D1 = 0x40
	// Position of NRST_STBY_D1 field.
	Flash_OPTSR_PRG__NRST_STBY_D1_Pos = 0x7
	// Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_PRG__NRST_STBY_D1_Msk = 0x80
	// Bit NRST_STBY_D1.
	Flash_OPTSR_PRG__NRST_STBY_D1 = 0x80
	// Position of RDP field.
	Flash_OPTSR_PRG__RDP_Pos = 0x8
	// Bit mask of RDP field.
	Flash_OPTSR_PRG__RDP_Msk = 0xff00
	// Position of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG__FZ_IWDG_STOP_Pos = 0x11
	// Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG__FZ_IWDG_STOP_Msk = 0x20000
	// Bit FZ_IWDG_STOP.
	Flash_OPTSR_PRG__FZ_IWDG_STOP = 0x20000
	// Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG__FZ_IWDG_SDBY_Pos = 0x12
	// Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG__FZ_IWDG_SDBY_Msk = 0x40000
	// Bit FZ_IWDG_SDBY.
	Flash_OPTSR_PRG__FZ_IWDG_SDBY = 0x40000
	// Position of ST_RAM_SIZE field.
	Flash_OPTSR_PRG__ST_RAM_SIZE_Pos = 0x13
	// Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_PRG__ST_RAM_SIZE_Msk = 0x180000
	// Position of SECURITY field.
	Flash_OPTSR_PRG__SECURITY_Pos = 0x15
	// Bit mask of SECURITY field.
	Flash_OPTSR_PRG__SECURITY_Msk = 0x200000
	// Bit SECURITY.
	Flash_OPTSR_PRG__SECURITY = 0x200000
	// Position of RSS1 field.
	Flash_OPTSR_PRG__RSS1_Pos = 0x1a
	// Bit mask of RSS1 field.
	Flash_OPTSR_PRG__RSS1_Msk = 0x4000000
	// Bit RSS1.
	Flash_OPTSR_PRG__RSS1 = 0x4000000
	// Position of RSS2 field.
	Flash_OPTSR_PRG__RSS2_Pos = 0x1b
	// Bit mask of RSS2 field.
	Flash_OPTSR_PRG__RSS2_Msk = 0x8000000
	// Bit RSS2.
	Flash_OPTSR_PRG__RSS2 = 0x8000000
	// Position of IO_HSLV field.
	Flash_OPTSR_PRG__IO_HSLV_Pos = 0x1d
	// Bit mask of IO_HSLV field.
	Flash_OPTSR_PRG__IO_HSLV_Msk = 0x20000000
	// Bit IO_HSLV.
	Flash_OPTSR_PRG__IO_HSLV = 0x20000000
	// Position of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG__SWAP_BANK_OPT_Pos = 0x1f
	// Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG__SWAP_BANK_OPT_Msk = 0x80000000
	// Bit SWAP_BANK_OPT.
	Flash_OPTSR_PRG__SWAP_BANK_OPT = 0x80000000

	// OPTCCR_: FLASH option clear control register
	// Position of CLR_OPTCHANGEERR field.
	Flash_OPTCCR__CLR_OPTCHANGEERR_Pos = 0x1e
	// Bit mask of CLR_OPTCHANGEERR field.
	Flash_OPTCCR__CLR_OPTCHANGEERR_Msk = 0x40000000
	// Bit CLR_OPTCHANGEERR.
	Flash_OPTCCR__CLR_OPTCHANGEERR = 0x40000000
)

// Bitfields for AXI: AXI interconnect registers
const (
	// PERIPH_ID_4: AXI interconnect - peripheral ID4 register
	// Position of JEP106CON field.
	AXI_PERIPH_ID_4_JEP106CON_Pos = 0x0
	// Bit mask of JEP106CON field.
	AXI_PERIPH_ID_4_JEP106CON_Msk = 0xf
	// Position of KCOUNT4 field.
	AXI_PERIPH_ID_4_KCOUNT4_Pos = 0x4
	// Bit mask of KCOUNT4 field.
	AXI_PERIPH_ID_4_KCOUNT4_Msk = 0xf0

	// PERIPH_ID_0: AXI interconnect - peripheral ID0 register
	// Position of PARTNUM field.
	AXI_PERIPH_ID_0_PARTNUM_Pos = 0x0
	// Bit mask of PARTNUM field.
	AXI_PERIPH_ID_0_PARTNUM_Msk = 0xff

	// PERIPH_ID_1: AXI interconnect - peripheral ID1 register
	// Position of PARTNUM field.
	AXI_PERIPH_ID_1_PARTNUM_Pos = 0x0
	// Bit mask of PARTNUM field.
	AXI_PERIPH_ID_1_PARTNUM_Msk = 0xf
	// Position of JEP106I field.
	AXI_PERIPH_ID_1_JEP106I_Pos = 0x4
	// Bit mask of JEP106I field.
	AXI_PERIPH_ID_1_JEP106I_Msk = 0xf0

	// PERIPH_ID_2: AXI interconnect - peripheral ID2 register
	// Position of JEP106ID field.
	AXI_PERIPH_ID_2_JEP106ID_Pos = 0x0
	// Bit mask of JEP106ID field.
	AXI_PERIPH_ID_2_JEP106ID_Msk = 0x7
	// Position of JEDEC field.
	AXI_PERIPH_ID_2_JEDEC_Pos = 0x3
	// Bit mask of JEDEC field.
	AXI_PERIPH_ID_2_JEDEC_Msk = 0x8
	// Bit JEDEC.
	AXI_PERIPH_ID_2_JEDEC = 0x8
	// Position of REVISION field.
	AXI_PERIPH_ID_2_REVISION_Pos = 0x4
	// Bit mask of REVISION field.
	AXI_PERIPH_ID_2_REVISION_Msk = 0xf0

	// PERIPH_ID_3: AXI interconnect - peripheral ID3 register
	// Position of CUST_MOD_NUM field.
	AXI_PERIPH_ID_3_CUST_MOD_NUM_Pos = 0x0
	// Bit mask of CUST_MOD_NUM field.
	AXI_PERIPH_ID_3_CUST_MOD_NUM_Msk = 0xf
	// Position of REV_AND field.
	AXI_PERIPH_ID_3_REV_AND_Pos = 0x4
	// Bit mask of REV_AND field.
	AXI_PERIPH_ID_3_REV_AND_Msk = 0xf0

	// COMP_ID_0: AXI interconnect - component ID0 register
	// Position of PREAMBLE field.
	AXI_COMP_ID_0_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXI_COMP_ID_0_PREAMBLE_Msk = 0xff

	// COMP_ID_1: AXI interconnect - component ID1 register
	// Position of PREAMBLE field.
	AXI_COMP_ID_1_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXI_COMP_ID_1_PREAMBLE_Msk = 0xf
	// Position of CLASS field.
	AXI_COMP_ID_1_CLASS_Pos = 0x4
	// Bit mask of CLASS field.
	AXI_COMP_ID_1_CLASS_Msk = 0xf0

	// COMP_ID_2: AXI interconnect - component ID2 register
	// Position of PREAMBLE field.
	AXI_COMP_ID_2_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXI_COMP_ID_2_PREAMBLE_Msk = 0xff

	// COMP_ID_3: AXI interconnect - component ID3 register
	// Position of PREAMBLE field.
	AXI_COMP_ID_3_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	AXI_COMP_ID_3_PREAMBLE_Msk = 0xff

	// TARG1_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG1_FN_MOD_ISS_BM_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG1_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE = 0x2

	// TARG1_FN_MOD2: AXI interconnect - TARG x bus matrix functionality 2 register
	// Position of BYPASS_MERGE field.
	AXI_TARG1_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXI_TARG1_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXI_TARG1_FN_MOD2_BYPASS_MERGE = 0x1

	// TARG1_FN_MOD_LB: AXI interconnect - TARG x long burst functionality modification
	// Position of FN_MOD_LB field.
	AXI_TARG1_FN_MOD_LB_FN_MOD_LB_Pos = 0x0
	// Bit mask of FN_MOD_LB field.
	AXI_TARG1_FN_MOD_LB_FN_MOD_LB_Msk = 0x1
	// Bit FN_MOD_LB.
	AXI_TARG1_FN_MOD_LB_FN_MOD_LB = 0x1

	// TARG1_FN_MOD: AXI interconnect - TARG x long burst functionality modification
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG1_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG1_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG1_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// TARG2_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG2_FN_MOD_ISS_BM_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG2_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE = 0x2

	// TARG2_FN_MOD2: AXI interconnect - TARG x bus matrix functionality 2 register
	// Position of BYPASS_MERGE field.
	AXI_TARG2_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXI_TARG2_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXI_TARG2_FN_MOD2_BYPASS_MERGE = 0x1

	// TARG2_FN_MOD_LB: AXI interconnect - TARG x long burst functionality modification
	// Position of FN_MOD_LB field.
	AXI_TARG2_FN_MOD_LB_FN_MOD_LB_Pos = 0x0
	// Bit mask of FN_MOD_LB field.
	AXI_TARG2_FN_MOD_LB_FN_MOD_LB_Msk = 0x1
	// Bit FN_MOD_LB.
	AXI_TARG2_FN_MOD_LB_FN_MOD_LB = 0x1

	// TARG2_FN_MOD: AXI interconnect - TARG x long burst functionality modification
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG2_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG2_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG2_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// TARG3_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG3_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG3_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG3_FN_MOD_ISS_BM_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG3_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG3_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG3_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE = 0x2

	// TARG4_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG4_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG4_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG4_FN_MOD_ISS_BM_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG4_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG4_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG4_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE = 0x2

	// TARG5_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG5_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG5_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG5_FN_MOD_ISS_BM_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG5_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG5_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG5_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE = 0x2

	// TARG6_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG6_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG6_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG6_FN_MOD_ISS_BM_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG6_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG6_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG6_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE = 0x2

	// TARG7_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing functionality register
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG7_FN_MOD_ISS_BM_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG7_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE = 0x2

	// TARG7_FN_MOD2: AXI interconnect - TARG x bus matrix functionality 2 register
	// Position of BYPASS_MERGE field.
	AXI_TARG7_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXI_TARG7_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXI_TARG7_FN_MOD2_BYPASS_MERGE = 0x1

	// TARG7_FN_MOD: AXI interconnect - TARG x long burst functionality modification
	// Position of READ_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_TARG7_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_TARG7_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_TARG7_FN_MOD_WRITE_ISS_OVERRIDE = 0x2

	// INI1_FN_MOD2: AXI interconnect - INI x functionality modification 2 register
	// Position of BYPASS_MERGE field.
	AXI_INI1_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXI_INI1_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXI_INI1_FN_MOD2_BYPASS_MERGE = 0x1

	// INI1_FN_MOD_AHB: AXI interconnect - INI x AHB functionality modification register
	// Position of RD_INC_OVERRIDE field.
	AXI_INI1_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0
	// Bit mask of RD_INC_OVERRIDE field.
	AXI_INI1_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1
	// Bit RD_INC_OVERRIDE.
	AXI_INI1_FN_MOD_AHB_RD_INC_OVERRIDE = 0x1
	// Position of WR_INC_OVERRIDE field.
	AXI_INI1_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1
	// Bit mask of WR_INC_OVERRIDE field.
	AXI_INI1_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2
	// Bit WR_INC_OVERRIDE.
	AXI_INI1_FN_MOD_AHB_WR_INC_OVERRIDE = 0x2

	// INI1_READ_QOS: AXI interconnect - INI x read QoS register
	// Position of AR_QOS field.
	AXI_INI1_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXI_INI1_READ_QOS_AR_QOS_Msk = 0xf

	// INI1_WRITE_QOS: AXI interconnect - INI x write QoS register
	// Position of AW_QOS field.
	AXI_INI1_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXI_INI1_WRITE_QOS_AW_QOS_Msk = 0xf

	// INI1_FN_MOD: AXI interconnect - INI x issuing functionality modification register
	// Position of READ_ISS_OVERRIDE field.
	AXI_INI1_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_INI1_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_INI1_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Normal ASIB read issuing capability
	AXI_INI1_FN_MOD_READ_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB read issuing capability to 1
	AXI_INI1_FN_MOD_READ_ISS_OVERRIDE_Force1 = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE = 0x2
	// Normal ASIB write issuing capability
	AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB write issuing capability to 1
	AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE_Force1 = 0x1

	// INI2_READ_QOS: AXI interconnect - INI x read QoS register
	// Position of AR_QOS field.
	AXI_INI2_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXI_INI2_READ_QOS_AR_QOS_Msk = 0xf

	// INI2_WRITE_QOS: AXI interconnect - INI x write QoS register
	// Position of AW_QOS field.
	AXI_INI2_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXI_INI2_WRITE_QOS_AW_QOS_Msk = 0xf

	// INI2_FN_MOD: AXI interconnect - INI x issuing functionality modification register
	// Position of READ_ISS_OVERRIDE field.
	AXI_INI2_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_INI2_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_INI2_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Normal ASIB read issuing capability
	AXI_INI2_FN_MOD_READ_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB read issuing capability to 1
	AXI_INI2_FN_MOD_READ_ISS_OVERRIDE_Force1 = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE = 0x2
	// Normal ASIB write issuing capability
	AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB write issuing capability to 1
	AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE_Force1 = 0x1

	// INI3_FN_MOD2: AXI interconnect - INI x functionality modification 2 register
	// Position of BYPASS_MERGE field.
	AXI_INI3_FN_MOD2_BYPASS_MERGE_Pos = 0x0
	// Bit mask of BYPASS_MERGE field.
	AXI_INI3_FN_MOD2_BYPASS_MERGE_Msk = 0x1
	// Bit BYPASS_MERGE.
	AXI_INI3_FN_MOD2_BYPASS_MERGE = 0x1

	// INI3_FN_MOD_AHB: AXI interconnect - INI x AHB functionality modification register
	// Position of RD_INC_OVERRIDE field.
	AXI_INI3_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0
	// Bit mask of RD_INC_OVERRIDE field.
	AXI_INI3_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1
	// Bit RD_INC_OVERRIDE.
	AXI_INI3_FN_MOD_AHB_RD_INC_OVERRIDE = 0x1
	// Position of WR_INC_OVERRIDE field.
	AXI_INI3_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1
	// Bit mask of WR_INC_OVERRIDE field.
	AXI_INI3_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2
	// Bit WR_INC_OVERRIDE.
	AXI_INI3_FN_MOD_AHB_WR_INC_OVERRIDE = 0x2

	// INI3_READ_QOS: AXI interconnect - INI x read QoS register
	// Position of AR_QOS field.
	AXI_INI3_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXI_INI3_READ_QOS_AR_QOS_Msk = 0xf

	// INI3_WRITE_QOS: AXI interconnect - INI x write QoS register
	// Position of AW_QOS field.
	AXI_INI3_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXI_INI3_WRITE_QOS_AW_QOS_Msk = 0xf

	// INI3_FN_MOD: AXI interconnect - INI x issuing functionality modification register
	// Position of READ_ISS_OVERRIDE field.
	AXI_INI3_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_INI3_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_INI3_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Normal ASIB read issuing capability
	AXI_INI3_FN_MOD_READ_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB read issuing capability to 1
	AXI_INI3_FN_MOD_READ_ISS_OVERRIDE_Force1 = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE = 0x2
	// Normal ASIB write issuing capability
	AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB write issuing capability to 1
	AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE_Force1 = 0x1

	// INI4_READ_QOS: AXI interconnect - INI x read QoS register
	// Position of AR_QOS field.
	AXI_INI4_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXI_INI4_READ_QOS_AR_QOS_Msk = 0xf

	// INI4_WRITE_QOS: AXI interconnect - INI x write QoS register
	// Position of AW_QOS field.
	AXI_INI4_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXI_INI4_WRITE_QOS_AW_QOS_Msk = 0xf

	// INI4_FN_MOD: AXI interconnect - INI x issuing functionality modification register
	// Position of READ_ISS_OVERRIDE field.
	AXI_INI4_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_INI4_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_INI4_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Normal ASIB read issuing capability
	AXI_INI4_FN_MOD_READ_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB read issuing capability to 1
	AXI_INI4_FN_MOD_READ_ISS_OVERRIDE_Force1 = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE = 0x2
	// Normal ASIB write issuing capability
	AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB write issuing capability to 1
	AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE_Force1 = 0x1

	// INI5_READ_QOS: AXI interconnect - INI x read QoS register
	// Position of AR_QOS field.
	AXI_INI5_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXI_INI5_READ_QOS_AR_QOS_Msk = 0xf

	// INI5_WRITE_QOS: AXI interconnect - INI x write QoS register
	// Position of AW_QOS field.
	AXI_INI5_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXI_INI5_WRITE_QOS_AW_QOS_Msk = 0xf

	// INI5_FN_MOD: AXI interconnect - INI x issuing functionality modification register
	// Position of READ_ISS_OVERRIDE field.
	AXI_INI5_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_INI5_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_INI5_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Normal ASIB read issuing capability
	AXI_INI5_FN_MOD_READ_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB read issuing capability to 1
	AXI_INI5_FN_MOD_READ_ISS_OVERRIDE_Force1 = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE = 0x2
	// Normal ASIB write issuing capability
	AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB write issuing capability to 1
	AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE_Force1 = 0x1

	// INI6_READ_QOS: AXI interconnect - INI x read QoS register
	// Position of AR_QOS field.
	AXI_INI6_READ_QOS_AR_QOS_Pos = 0x0
	// Bit mask of AR_QOS field.
	AXI_INI6_READ_QOS_AR_QOS_Msk = 0xf

	// INI6_WRITE_QOS: AXI interconnect - INI x write QoS register
	// Position of AW_QOS field.
	AXI_INI6_WRITE_QOS_AW_QOS_Pos = 0x0
	// Bit mask of AW_QOS field.
	AXI_INI6_WRITE_QOS_AW_QOS_Msk = 0xf

	// INI6_FN_MOD: AXI interconnect - INI x issuing functionality modification register
	// Position of READ_ISS_OVERRIDE field.
	AXI_INI6_FN_MOD_READ_ISS_OVERRIDE_Pos = 0x0
	// Bit mask of READ_ISS_OVERRIDE field.
	AXI_INI6_FN_MOD_READ_ISS_OVERRIDE_Msk = 0x1
	// Bit READ_ISS_OVERRIDE.
	AXI_INI6_FN_MOD_READ_ISS_OVERRIDE = 0x1
	// Normal ASIB read issuing capability
	AXI_INI6_FN_MOD_READ_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB read issuing capability to 1
	AXI_INI6_FN_MOD_READ_ISS_OVERRIDE_Force1 = 0x1
	// Position of WRITE_ISS_OVERRIDE field.
	AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1
	// Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2
	// Bit WRITE_ISS_OVERRIDE.
	AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE = 0x2
	// Normal ASIB write issuing capability
	AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE_Normal = 0x0
	// Force ASIB write issuing capability to 1
	AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE_Force1 = 0x1
)

// Bitfields for HASH: Hash processor
const (
	// CR: control register
	// Position of INIT field.
	HASH_CR_INIT_Pos = 0x2
	// Bit mask of INIT field.
	HASH_CR_INIT_Msk = 0x4
	// Bit INIT.
	HASH_CR_INIT = 0x4
	// Position of DMAE field.
	HASH_CR_DMAE_Pos = 0x3
	// Bit mask of DMAE field.
	HASH_CR_DMAE_Msk = 0x8
	// Bit DMAE.
	HASH_CR_DMAE = 0x8
	// Position of DATATYPE field.
	HASH_CR_DATATYPE_Pos = 0x4
	// Bit mask of DATATYPE field.
	HASH_CR_DATATYPE_Msk = 0x30
	// Position of MODE field.
	HASH_CR_MODE_Pos = 0x6
	// Bit mask of MODE field.
	HASH_CR_MODE_Msk = 0x40
	// Bit MODE.
	HASH_CR_MODE = 0x40
	// Position of ALGO0 field.
	HASH_CR_ALGO0_Pos = 0x7
	// Bit mask of ALGO0 field.
	HASH_CR_ALGO0_Msk = 0x80
	// Bit ALGO0.
	HASH_CR_ALGO0 = 0x80
	// Position of NBW field.
	HASH_CR_NBW_Pos = 0x8
	// Bit mask of NBW field.
	HASH_CR_NBW_Msk = 0xf00
	// Position of DINNE field.
	HASH_CR_DINNE_Pos = 0xc
	// Bit mask of DINNE field.
	HASH_CR_DINNE_Msk = 0x1000
	// Bit DINNE.
	HASH_CR_DINNE = 0x1000
	// Position of MDMAT field.
	HASH_CR_MDMAT_Pos = 0xd
	// Bit mask of MDMAT field.
	HASH_CR_MDMAT_Msk = 0x2000
	// Bit MDMAT.
	HASH_CR_MDMAT = 0x2000
	// Position of LKEY field.
	HASH_CR_LKEY_Pos = 0x10
	// Bit mask of LKEY field.
	HASH_CR_LKEY_Msk = 0x10000
	// Bit LKEY.
	HASH_CR_LKEY = 0x10000
	// Position of ALGO1 field.
	HASH_CR_ALGO1_Pos = 0x12
	// Bit mask of ALGO1 field.
	HASH_CR_ALGO1_Msk = 0x40000
	// Bit ALGO1.
	HASH_CR_ALGO1 = 0x40000

	// DIN: data input register
	// Position of DATAIN field.
	HASH_DIN_DATAIN_Pos = 0x0
	// Bit mask of DATAIN field.
	HASH_DIN_DATAIN_Msk = 0xffffffff

	// STR: start register
	// Position of DCAL field.
	HASH_STR_DCAL_Pos = 0x8
	// Bit mask of DCAL field.
	HASH_STR_DCAL_Msk = 0x100
	// Bit DCAL.
	HASH_STR_DCAL = 0x100
	// Position of NBLW field.
	HASH_STR_NBLW_Pos = 0x0
	// Bit mask of NBLW field.
	HASH_STR_NBLW_Msk = 0x1f

	// HR0: digest registers
	// Position of H0 field.
	HASH_HR0_H0_Pos = 0x0
	// Bit mask of H0 field.
	HASH_HR0_H0_Msk = 0xffffffff

	// HR1: digest registers
	// Position of H1 field.
	HASH_HR1_H1_Pos = 0x0
	// Bit mask of H1 field.
	HASH_HR1_H1_Msk = 0xffffffff

	// HR2: digest registers
	// Position of H2 field.
	HASH_HR2_H2_Pos = 0x0
	// Bit mask of H2 field.
	HASH_HR2_H2_Msk = 0xffffffff

	// HR3: digest registers
	// Position of H3 field.
	HASH_HR3_H3_Pos = 0x0
	// Bit mask of H3 field.
	HASH_HR3_H3_Msk = 0xffffffff

	// HR4: digest registers
	// Position of H4 field.
	HASH_HR4_H4_Pos = 0x0
	// Bit mask of H4 field.
	HASH_HR4_H4_Msk = 0xffffffff

	// IMR: interrupt enable register
	// Position of DCIE field.
	HASH_IMR_DCIE_Pos = 0x1
	// Bit mask of DCIE field.
	HASH_IMR_DCIE_Msk = 0x2
	// Bit DCIE.
	HASH_IMR_DCIE = 0x2
	// Position of DINIE field.
	HASH_IMR_DINIE_Pos = 0x0
	// Bit mask of DINIE field.
	HASH_IMR_DINIE_Msk = 0x1
	// Bit DINIE.
	HASH_IMR_DINIE = 0x1

	// SR: status register
	// Position of BUSY field.
	HASH_SR_BUSY_Pos = 0x3
	// Bit mask of BUSY field.
	HASH_SR_BUSY_Msk = 0x8
	// Bit BUSY.
	HASH_SR_BUSY = 0x8
	// Position of DMAS field.
	HASH_SR_DMAS_Pos = 0x2
	// Bit mask of DMAS field.
	HASH_SR_DMAS_Msk = 0x4
	// Bit DMAS.
	HASH_SR_DMAS = 0x4
	// Position of DCIS field.
	HASH_SR_DCIS_Pos = 0x1
	// Bit mask of DCIS field.
	HASH_SR_DCIS_Msk = 0x2
	// Bit DCIS.
	HASH_SR_DCIS = 0x2
	// Position of DINIS field.
	HASH_SR_DINIS_Pos = 0x0
	// Bit mask of DINIS field.
	HASH_SR_DINIS_Msk = 0x1
	// Bit DINIS.
	HASH_SR_DINIS = 0x1

	// CSR0: context swap registers
	// Position of CSR0 field.
	HASH_CSR0_CSR0_Pos = 0x0
	// Bit mask of CSR0 field.
	HASH_CSR0_CSR0_Msk = 0xffffffff

	// CSR1: context swap registers
	// Position of CSR1 field.
	HASH_CSR1_CSR1_Pos = 0x0
	// Bit mask of CSR1 field.
	HASH_CSR1_CSR1_Msk = 0xffffffff

	// CSR2: context swap registers
	// Position of CSR2 field.
	HASH_CSR2_CSR2_Pos = 0x0
	// Bit mask of CSR2 field.
	HASH_CSR2_CSR2_Msk = 0xffffffff

	// CSR3: context swap registers
	// Position of CSR3 field.
	HASH_CSR3_CSR3_Pos = 0x0
	// Bit mask of CSR3 field.
	HASH_CSR3_CSR3_Msk = 0xffffffff

	// CSR4: context swap registers
	// Position of CSR4 field.
	HASH_CSR4_CSR4_Pos = 0x0
	// Bit mask of CSR4 field.
	HASH_CSR4_CSR4_Msk = 0xffffffff

	// CSR5: context swap registers
	// Position of CSR5 field.
	HASH_CSR5_CSR5_Pos = 0x0
	// Bit mask of CSR5 field.
	HASH_CSR5_CSR5_Msk = 0xffffffff

	// CSR6: context swap registers
	// Position of CSR6 field.
	HASH_CSR6_CSR6_Pos = 0x0
	// Bit mask of CSR6 field.
	HASH_CSR6_CSR6_Msk = 0xffffffff

	// CSR7: context swap registers
	// Position of CSR7 field.
	HASH_CSR7_CSR7_Pos = 0x0
	// Bit mask of CSR7 field.
	HASH_CSR7_CSR7_Msk = 0xffffffff

	// CSR8: context swap registers
	// Position of CSR8 field.
	HASH_CSR8_CSR8_Pos = 0x0
	// Bit mask of CSR8 field.
	HASH_CSR8_CSR8_Msk = 0xffffffff

	// CSR9: context swap registers
	// Position of CSR9 field.
	HASH_CSR9_CSR9_Pos = 0x0
	// Bit mask of CSR9 field.
	HASH_CSR9_CSR9_Msk = 0xffffffff

	// CSR10: context swap registers
	// Position of CSR10 field.
	HASH_CSR10_CSR10_Pos = 0x0
	// Bit mask of CSR10 field.
	HASH_CSR10_CSR10_Msk = 0xffffffff

	// CSR11: context swap registers
	// Position of CSR11 field.
	HASH_CSR11_CSR11_Pos = 0x0
	// Bit mask of CSR11 field.
	HASH_CSR11_CSR11_Msk = 0xffffffff

	// CSR12: context swap registers
	// Position of CSR12 field.
	HASH_CSR12_CSR12_Pos = 0x0
	// Bit mask of CSR12 field.
	HASH_CSR12_CSR12_Msk = 0xffffffff

	// CSR13: context swap registers
	// Position of CSR13 field.
	HASH_CSR13_CSR13_Pos = 0x0
	// Bit mask of CSR13 field.
	HASH_CSR13_CSR13_Msk = 0xffffffff

	// CSR14: context swap registers
	// Position of CSR14 field.
	HASH_CSR14_CSR14_Pos = 0x0
	// Bit mask of CSR14 field.
	HASH_CSR14_CSR14_Msk = 0xffffffff

	// CSR15: context swap registers
	// Position of CSR15 field.
	HASH_CSR15_CSR15_Pos = 0x0
	// Bit mask of CSR15 field.
	HASH_CSR15_CSR15_Msk = 0xffffffff

	// CSR16: context swap registers
	// Position of CSR16 field.
	HASH_CSR16_CSR16_Pos = 0x0
	// Bit mask of CSR16 field.
	HASH_CSR16_CSR16_Msk = 0xffffffff

	// CSR17: context swap registers
	// Position of CSR17 field.
	HASH_CSR17_CSR17_Pos = 0x0
	// Bit mask of CSR17 field.
	HASH_CSR17_CSR17_Msk = 0xffffffff

	// CSR18: context swap registers
	// Position of CSR18 field.
	HASH_CSR18_CSR18_Pos = 0x0
	// Bit mask of CSR18 field.
	HASH_CSR18_CSR18_Msk = 0xffffffff

	// CSR19: context swap registers
	// Position of CSR19 field.
	HASH_CSR19_CSR19_Pos = 0x0
	// Bit mask of CSR19 field.
	HASH_CSR19_CSR19_Msk = 0xffffffff

	// CSR20: context swap registers
	// Position of CSR20 field.
	HASH_CSR20_CSR20_Pos = 0x0
	// Bit mask of CSR20 field.
	HASH_CSR20_CSR20_Msk = 0xffffffff

	// CSR21: context swap registers
	// Position of CSR21 field.
	HASH_CSR21_CSR21_Pos = 0x0
	// Bit mask of CSR21 field.
	HASH_CSR21_CSR21_Msk = 0xffffffff

	// CSR22: context swap registers
	// Position of CSR22 field.
	HASH_CSR22_CSR22_Pos = 0x0
	// Bit mask of CSR22 field.
	HASH_CSR22_CSR22_Msk = 0xffffffff

	// CSR23: context swap registers
	// Position of CSR23 field.
	HASH_CSR23_CSR23_Pos = 0x0
	// Bit mask of CSR23 field.
	HASH_CSR23_CSR23_Msk = 0xffffffff

	// CSR24: context swap registers
	// Position of CSR24 field.
	HASH_CSR24_CSR24_Pos = 0x0
	// Bit mask of CSR24 field.
	HASH_CSR24_CSR24_Msk = 0xffffffff

	// CSR25: context swap registers
	// Position of CSR25 field.
	HASH_CSR25_CSR25_Pos = 0x0
	// Bit mask of CSR25 field.
	HASH_CSR25_CSR25_Msk = 0xffffffff

	// CSR26: context swap registers
	// Position of CSR26 field.
	HASH_CSR26_CSR26_Pos = 0x0
	// Bit mask of CSR26 field.
	HASH_CSR26_CSR26_Msk = 0xffffffff

	// CSR27: context swap registers
	// Position of CSR27 field.
	HASH_CSR27_CSR27_Pos = 0x0
	// Bit mask of CSR27 field.
	HASH_CSR27_CSR27_Msk = 0xffffffff

	// CSR28: context swap registers
	// Position of CSR28 field.
	HASH_CSR28_CSR28_Pos = 0x0
	// Bit mask of CSR28 field.
	HASH_CSR28_CSR28_Msk = 0xffffffff

	// CSR29: context swap registers
	// Position of CSR29 field.
	HASH_CSR29_CSR29_Pos = 0x0
	// Bit mask of CSR29 field.
	HASH_CSR29_CSR29_Msk = 0xffffffff

	// CSR30: context swap registers
	// Position of CSR30 field.
	HASH_CSR30_CSR30_Pos = 0x0
	// Bit mask of CSR30 field.
	HASH_CSR30_CSR30_Msk = 0xffffffff

	// CSR31: context swap registers
	// Position of CSR31 field.
	HASH_CSR31_CSR31_Pos = 0x0
	// Bit mask of CSR31 field.
	HASH_CSR31_CSR31_Msk = 0xffffffff

	// CSR32: context swap registers
	// Position of CSR32 field.
	HASH_CSR32_CSR32_Pos = 0x0
	// Bit mask of CSR32 field.
	HASH_CSR32_CSR32_Msk = 0xffffffff

	// CSR33: context swap registers
	// Position of CSR33 field.
	HASH_CSR33_CSR33_Pos = 0x0
	// Bit mask of CSR33 field.
	HASH_CSR33_CSR33_Msk = 0xffffffff

	// CSR34: context swap registers
	// Position of CSR34 field.
	HASH_CSR34_CSR34_Pos = 0x0
	// Bit mask of CSR34 field.
	HASH_CSR34_CSR34_Msk = 0xffffffff

	// CSR35: context swap registers
	// Position of CSR35 field.
	HASH_CSR35_CSR35_Pos = 0x0
	// Bit mask of CSR35 field.
	HASH_CSR35_CSR35_Msk = 0xffffffff

	// CSR36: context swap registers
	// Position of CSR36 field.
	HASH_CSR36_CSR36_Pos = 0x0
	// Bit mask of CSR36 field.
	HASH_CSR36_CSR36_Msk = 0xffffffff

	// CSR37: context swap registers
	// Position of CSR37 field.
	HASH_CSR37_CSR37_Pos = 0x0
	// Bit mask of CSR37 field.
	HASH_CSR37_CSR37_Msk = 0xffffffff

	// CSR38: context swap registers
	// Position of CSR38 field.
	HASH_CSR38_CSR38_Pos = 0x0
	// Bit mask of CSR38 field.
	HASH_CSR38_CSR38_Msk = 0xffffffff

	// CSR39: context swap registers
	// Position of CSR39 field.
	HASH_CSR39_CSR39_Pos = 0x0
	// Bit mask of CSR39 field.
	HASH_CSR39_CSR39_Msk = 0xffffffff

	// CSR40: context swap registers
	// Position of CSR40 field.
	HASH_CSR40_CSR40_Pos = 0x0
	// Bit mask of CSR40 field.
	HASH_CSR40_CSR40_Msk = 0xffffffff

	// CSR41: context swap registers
	// Position of CSR41 field.
	HASH_CSR41_CSR41_Pos = 0x0
	// Bit mask of CSR41 field.
	HASH_CSR41_CSR41_Msk = 0xffffffff

	// CSR42: context swap registers
	// Position of CSR42 field.
	HASH_CSR42_CSR42_Pos = 0x0
	// Bit mask of CSR42 field.
	HASH_CSR42_CSR42_Msk = 0xffffffff

	// CSR43: context swap registers
	// Position of CSR43 field.
	HASH_CSR43_CSR43_Pos = 0x0
	// Bit mask of CSR43 field.
	HASH_CSR43_CSR43_Msk = 0xffffffff

	// CSR44: context swap registers
	// Position of CSR44 field.
	HASH_CSR44_CSR44_Pos = 0x0
	// Bit mask of CSR44 field.
	HASH_CSR44_CSR44_Msk = 0xffffffff

	// CSR45: context swap registers
	// Position of CSR45 field.
	HASH_CSR45_CSR45_Pos = 0x0
	// Bit mask of CSR45 field.
	HASH_CSR45_CSR45_Msk = 0xffffffff

	// CSR46: context swap registers
	// Position of CSR46 field.
	HASH_CSR46_CSR46_Pos = 0x0
	// Bit mask of CSR46 field.
	HASH_CSR46_CSR46_Msk = 0xffffffff

	// CSR47: context swap registers
	// Position of CSR47 field.
	HASH_CSR47_CSR47_Pos = 0x0
	// Bit mask of CSR47 field.
	HASH_CSR47_CSR47_Msk = 0xffffffff

	// CSR48: context swap registers
	// Position of CSR48 field.
	HASH_CSR48_CSR48_Pos = 0x0
	// Bit mask of CSR48 field.
	HASH_CSR48_CSR48_Msk = 0xffffffff

	// CSR49: context swap registers
	// Position of CSR49 field.
	HASH_CSR49_CSR49_Pos = 0x0
	// Bit mask of CSR49 field.
	HASH_CSR49_CSR49_Msk = 0xffffffff

	// CSR50: context swap registers
	// Position of CSR50 field.
	HASH_CSR50_CSR50_Pos = 0x0
	// Bit mask of CSR50 field.
	HASH_CSR50_CSR50_Msk = 0xffffffff

	// CSR51: context swap registers
	// Position of CSR51 field.
	HASH_CSR51_CSR51_Pos = 0x0
	// Bit mask of CSR51 field.
	HASH_CSR51_CSR51_Msk = 0xffffffff

	// CSR52: context swap registers
	// Position of CSR52 field.
	HASH_CSR52_CSR52_Pos = 0x0
	// Bit mask of CSR52 field.
	HASH_CSR52_CSR52_Msk = 0xffffffff

	// CSR53: context swap registers
	// Position of CSR53 field.
	HASH_CSR53_CSR53_Pos = 0x0
	// Bit mask of CSR53 field.
	HASH_CSR53_CSR53_Msk = 0xffffffff

	// HASH_HR0: HASH digest register
	// Position of H0 field.
	HASH_HASH_HR0_H0_Pos = 0x0
	// Bit mask of H0 field.
	HASH_HASH_HR0_H0_Msk = 0xffffffff

	// HASH_HR1: read-only
	// Position of H1 field.
	HASH_HASH_HR1_H1_Pos = 0x0
	// Bit mask of H1 field.
	HASH_HASH_HR1_H1_Msk = 0xffffffff

	// HASH_HR2: read-only
	// Position of H2 field.
	HASH_HASH_HR2_H2_Pos = 0x0
	// Bit mask of H2 field.
	HASH_HASH_HR2_H2_Msk = 0xffffffff

	// HASH_HR3: read-only
	// Position of H3 field.
	HASH_HASH_HR3_H3_Pos = 0x0
	// Bit mask of H3 field.
	HASH_HASH_HR3_H3_Msk = 0xffffffff

	// HASH_HR4: read-only
	// Position of H4 field.
	HASH_HASH_HR4_H4_Pos = 0x0
	// Bit mask of H4 field.
	HASH_HASH_HR4_H4_Msk = 0xffffffff

	// HASH_HR5: read-only
	// Position of H5 field.
	HASH_HASH_HR5_H5_Pos = 0x0
	// Bit mask of H5 field.
	HASH_HASH_HR5_H5_Msk = 0xffffffff

	// HASH_HR6: read-only
	// Position of H6 field.
	HASH_HASH_HR6_H6_Pos = 0x0
	// Bit mask of H6 field.
	HASH_HASH_HR6_H6_Msk = 0xffffffff

	// HASH_HR7: read-only
	// Position of H7 field.
	HASH_HASH_HR7_H7_Pos = 0x0
	// Bit mask of H7 field.
	HASH_HASH_HR7_H7_Msk = 0xffffffff
)

// Bitfields for CRYP: Cryptographic processor
const (
	// CR: control register
	// Position of ALGODIR field.
	CRYP_CR_ALGODIR_Pos = 0x2
	// Bit mask of ALGODIR field.
	CRYP_CR_ALGODIR_Msk = 0x4
	// Bit ALGODIR.
	CRYP_CR_ALGODIR = 0x4
	// Position of ALGOMODE0 field.
	CRYP_CR_ALGOMODE0_Pos = 0x3
	// Bit mask of ALGOMODE0 field.
	CRYP_CR_ALGOMODE0_Msk = 0x38
	// Position of DATATYPE field.
	CRYP_CR_DATATYPE_Pos = 0x6
	// Bit mask of DATATYPE field.
	CRYP_CR_DATATYPE_Msk = 0xc0
	// Position of KEYSIZE field.
	CRYP_CR_KEYSIZE_Pos = 0x8
	// Bit mask of KEYSIZE field.
	CRYP_CR_KEYSIZE_Msk = 0x300
	// Position of FFLUSH field.
	CRYP_CR_FFLUSH_Pos = 0xe
	// Bit mask of FFLUSH field.
	CRYP_CR_FFLUSH_Msk = 0x4000
	// Bit FFLUSH.
	CRYP_CR_FFLUSH = 0x4000
	// Position of CRYPEN field.
	CRYP_CR_CRYPEN_Pos = 0xf
	// Bit mask of CRYPEN field.
	CRYP_CR_CRYPEN_Msk = 0x8000
	// Bit CRYPEN.
	CRYP_CR_CRYPEN = 0x8000
	// Position of GCM_CCMPH field.
	CRYP_CR_GCM_CCMPH_Pos = 0x10
	// Bit mask of GCM_CCMPH field.
	CRYP_CR_GCM_CCMPH_Msk = 0x30000
	// Position of ALGOMODE3 field.
	CRYP_CR_ALGOMODE3_Pos = 0x13
	// Bit mask of ALGOMODE3 field.
	CRYP_CR_ALGOMODE3_Msk = 0x80000
	// Bit ALGOMODE3.
	CRYP_CR_ALGOMODE3 = 0x80000

	// SR: status register
	// Position of BUSY field.
	CRYP_SR_BUSY_Pos = 0x4
	// Bit mask of BUSY field.
	CRYP_SR_BUSY_Msk = 0x10
	// Bit BUSY.
	CRYP_SR_BUSY = 0x10
	// Position of OFFU field.
	CRYP_SR_OFFU_Pos = 0x3
	// Bit mask of OFFU field.
	CRYP_SR_OFFU_Msk = 0x8
	// Bit OFFU.
	CRYP_SR_OFFU = 0x8
	// Position of OFNE field.
	CRYP_SR_OFNE_Pos = 0x2
	// Bit mask of OFNE field.
	CRYP_SR_OFNE_Msk = 0x4
	// Bit OFNE.
	CRYP_SR_OFNE = 0x4
	// Position of IFNF field.
	CRYP_SR_IFNF_Pos = 0x1
	// Bit mask of IFNF field.
	CRYP_SR_IFNF_Msk = 0x2
	// Bit IFNF.
	CRYP_SR_IFNF = 0x2
	// Position of IFEM field.
	CRYP_SR_IFEM_Pos = 0x0
	// Bit mask of IFEM field.
	CRYP_SR_IFEM_Msk = 0x1
	// Bit IFEM.
	CRYP_SR_IFEM = 0x1

	// DIN: data input register
	// Position of DATAIN field.
	CRYP_DIN_DATAIN_Pos = 0x0
	// Bit mask of DATAIN field.
	CRYP_DIN_DATAIN_Msk = 0xffffffff

	// DOUT: data output register
	// Position of DATAOUT field.
	CRYP_DOUT_DATAOUT_Pos = 0x0
	// Bit mask of DATAOUT field.
	CRYP_DOUT_DATAOUT_Msk = 0xffffffff

	// DMACR: DMA control register
	// Position of DOEN field.
	CRYP_DMACR_DOEN_Pos = 0x1
	// Bit mask of DOEN field.
	CRYP_DMACR_DOEN_Msk = 0x2
	// Bit DOEN.
	CRYP_DMACR_DOEN = 0x2
	// Position of DIEN field.
	CRYP_DMACR_DIEN_Pos = 0x0
	// Bit mask of DIEN field.
	CRYP_DMACR_DIEN_Msk = 0x1
	// Bit DIEN.
	CRYP_DMACR_DIEN = 0x1

	// IMSCR: interrupt mask set/clear register
	// Position of OUTIM field.
	CRYP_IMSCR_OUTIM_Pos = 0x1
	// Bit mask of OUTIM field.
	CRYP_IMSCR_OUTIM_Msk = 0x2
	// Bit OUTIM.
	CRYP_IMSCR_OUTIM = 0x2
	// Position of INIM field.
	CRYP_IMSCR_INIM_Pos = 0x0
	// Bit mask of INIM field.
	CRYP_IMSCR_INIM_Msk = 0x1
	// Bit INIM.
	CRYP_IMSCR_INIM = 0x1

	// RISR: raw interrupt status register
	// Position of OUTRIS field.
	CRYP_RISR_OUTRIS_Pos = 0x1
	// Bit mask of OUTRIS field.
	CRYP_RISR_OUTRIS_Msk = 0x2
	// Bit OUTRIS.
	CRYP_RISR_OUTRIS = 0x2
	// Position of INRIS field.
	CRYP_RISR_INRIS_Pos = 0x0
	// Bit mask of INRIS field.
	CRYP_RISR_INRIS_Msk = 0x1
	// Bit INRIS.
	CRYP_RISR_INRIS = 0x1

	// MISR: masked interrupt status register
	// Position of OUTMIS field.
	CRYP_MISR_OUTMIS_Pos = 0x1
	// Bit mask of OUTMIS field.
	CRYP_MISR_OUTMIS_Msk = 0x2
	// Bit OUTMIS.
	CRYP_MISR_OUTMIS = 0x2
	// Position of INMIS field.
	CRYP_MISR_INMIS_Pos = 0x0
	// Bit mask of INMIS field.
	CRYP_MISR_INMIS_Msk = 0x1
	// Bit INMIS.
	CRYP_MISR_INMIS = 0x1

	// K0LR: key registers
	// Position of K2 field.
	CRYP_K0LR_K2_Pos = 0x0
	// Bit mask of K2 field.
	CRYP_K0LR_K2_Msk = 0xffffffff

	// K0RR: key registers
	// Position of K field.
	CRYP_K0RR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP_K0RR_K_Msk = 0xffffffff

	// K1LR: key registers
	// Position of K1 field.
	CRYP_K1LR_K1_Pos = 0x0
	// Bit mask of K1 field.
	CRYP_K1LR_K1_Msk = 0xffffffff

	// K1RR: key registers
	// Position of K1 field.
	CRYP_K1RR_K1_Pos = 0x0
	// Bit mask of K1 field.
	CRYP_K1RR_K1_Msk = 0xffffffff

	// K2LR: key registers
	// Position of K field.
	CRYP_K2LR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP_K2LR_K_Msk = 0xffffffff

	// K2RR: key registers
	// Position of K field.
	CRYP_K2RR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP_K2RR_K_Msk = 0xffffffff

	// K3LR: key registers
	// Position of K field.
	CRYP_K3LR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP_K3LR_K_Msk = 0xffffffff

	// K3RR: key registers
	// Position of K field.
	CRYP_K3RR_K_Pos = 0x0
	// Bit mask of K field.
	CRYP_K3RR_K_Msk = 0xffffffff

	// IV0LR: initialization vector registers
	// Position of IV field.
	CRYP_IV0LR_IV_Pos = 0x0
	// Bit mask of IV field.
	CRYP_IV0LR_IV_Msk = 0xffffffff

	// IV0RR: initialization vector registers
	// Position of IV field.
	CRYP_IV0RR_IV_Pos = 0x0
	// Bit mask of IV field.
	CRYP_IV0RR_IV_Msk = 0xffffffff

	// IV1LR: initialization vector registers
	// Position of IV field.
	CRYP_IV1LR_IV_Pos = 0x0
	// Bit mask of IV field.
	CRYP_IV1LR_IV_Msk = 0xffffffff

	// IV1RR: initialization vector registers
	// Position of IV field.
	CRYP_IV1RR_IV_Pos = 0x0
	// Bit mask of IV field.
	CRYP_IV1RR_IV_Msk = 0xffffffff

	// CSGCMCCM0R: context swap register
	// Position of CSGCMCCM0 field.
	CRYP_CSGCMCCM0R_CSGCMCCM0_Pos = 0x0
	// Bit mask of CSGCMCCM0 field.
	CRYP_CSGCMCCM0R_CSGCMCCM0_Msk = 0xffffffff

	// CSGCMCCM1R: context swap register
	// Position of CSGCMCCM1 field.
	CRYP_CSGCMCCM1R_CSGCMCCM1_Pos = 0x0
	// Bit mask of CSGCMCCM1 field.
	CRYP_CSGCMCCM1R_CSGCMCCM1_Msk = 0xffffffff

	// CSGCMCCM2R: context swap register
	// Position of CSGCMCCM2 field.
	CRYP_CSGCMCCM2R_CSGCMCCM2_Pos = 0x0
	// Bit mask of CSGCMCCM2 field.
	CRYP_CSGCMCCM2R_CSGCMCCM2_Msk = 0xffffffff

	// CSGCMCCM3R: context swap register
	// Position of CSGCMCCM3 field.
	CRYP_CSGCMCCM3R_CSGCMCCM3_Pos = 0x0
	// Bit mask of CSGCMCCM3 field.
	CRYP_CSGCMCCM3R_CSGCMCCM3_Msk = 0xffffffff

	// CSGCMCCM4R: context swap register
	// Position of CSGCMCCM4 field.
	CRYP_CSGCMCCM4R_CSGCMCCM4_Pos = 0x0
	// Bit mask of CSGCMCCM4 field.
	CRYP_CSGCMCCM4R_CSGCMCCM4_Msk = 0xffffffff

	// CSGCMCCM5R: context swap register
	// Position of CSGCMCCM5 field.
	CRYP_CSGCMCCM5R_CSGCMCCM5_Pos = 0x0
	// Bit mask of CSGCMCCM5 field.
	CRYP_CSGCMCCM5R_CSGCMCCM5_Msk = 0xffffffff

	// CSGCMCCM6R: context swap register
	// Position of CSGCMCCM6 field.
	CRYP_CSGCMCCM6R_CSGCMCCM6_Pos = 0x0
	// Bit mask of CSGCMCCM6 field.
	CRYP_CSGCMCCM6R_CSGCMCCM6_Msk = 0xffffffff

	// CSGCMCCM7R: context swap register
	// Position of CSGCMCCM7 field.
	CRYP_CSGCMCCM7R_CSGCMCCM7_Pos = 0x0
	// Bit mask of CSGCMCCM7 field.
	CRYP_CSGCMCCM7R_CSGCMCCM7_Msk = 0xffffffff

	// CSGCM0R: context swap register
	// Position of CSGCM0 field.
	CRYP_CSGCM0R_CSGCM0_Pos = 0x0
	// Bit mask of CSGCM0 field.
	CRYP_CSGCM0R_CSGCM0_Msk = 0xffffffff

	// CSGCM1R: context swap register
	// Position of CSGCM1 field.
	CRYP_CSGCM1R_CSGCM1_Pos = 0x0
	// Bit mask of CSGCM1 field.
	CRYP_CSGCM1R_CSGCM1_Msk = 0xffffffff

	// CSGCM2R: context swap register
	// Position of CSGCM2 field.
	CRYP_CSGCM2R_CSGCM2_Pos = 0x0
	// Bit mask of CSGCM2 field.
	CRYP_CSGCM2R_CSGCM2_Msk = 0xffffffff

	// CSGCM3R: context swap register
	// Position of CSGCM3 field.
	CRYP_CSGCM3R_CSGCM3_Pos = 0x0
	// Bit mask of CSGCM3 field.
	CRYP_CSGCM3R_CSGCM3_Msk = 0xffffffff

	// CSGCM4R: context swap register
	// Position of CSGCM4 field.
	CRYP_CSGCM4R_CSGCM4_Pos = 0x0
	// Bit mask of CSGCM4 field.
	CRYP_CSGCM4R_CSGCM4_Msk = 0xffffffff

	// CSGCM5R: context swap register
	// Position of CSGCM5 field.
	CRYP_CSGCM5R_CSGCM5_Pos = 0x0
	// Bit mask of CSGCM5 field.
	CRYP_CSGCM5R_CSGCM5_Msk = 0xffffffff

	// CSGCM6R: context swap register
	// Position of CSGCM6 field.
	CRYP_CSGCM6R_CSGCM6_Pos = 0x0
	// Bit mask of CSGCM6 field.
	CRYP_CSGCM6R_CSGCM6_Msk = 0xffffffff

	// CSGCM7R: context swap register
	// Position of CSGCM7 field.
	CRYP_CSGCM7R_CSGCM7_Pos = 0x0
	// Bit mask of CSGCM7 field.
	CRYP_CSGCM7R_CSGCM7_Msk = 0xffffffff
)

// Bitfields for DCMI: Digital camera interface
const (
	// CR: control register 1
	// Position of OELS field.
	DCMI_CR_OELS_Pos = 0x14
	// Bit mask of OELS field.
	DCMI_CR_OELS_Msk = 0x100000
	// Bit OELS.
	DCMI_CR_OELS = 0x100000
	// Position of LSM field.
	DCMI_CR_LSM_Pos = 0x13
	// Bit mask of LSM field.
	DCMI_CR_LSM_Msk = 0x80000
	// Bit LSM.
	DCMI_CR_LSM = 0x80000
	// Position of OEBS field.
	DCMI_CR_OEBS_Pos = 0x12
	// Bit mask of OEBS field.
	DCMI_CR_OEBS_Msk = 0x40000
	// Bit OEBS.
	DCMI_CR_OEBS = 0x40000
	// Position of BSM field.
	DCMI_CR_BSM_Pos = 0x10
	// Bit mask of BSM field.
	DCMI_CR_BSM_Msk = 0x30000
	// Position of ENABLE field.
	DCMI_CR_ENABLE_Pos = 0xe
	// Bit mask of ENABLE field.
	DCMI_CR_ENABLE_Msk = 0x4000
	// Bit ENABLE.
	DCMI_CR_ENABLE = 0x4000
	// Position of EDM field.
	DCMI_CR_EDM_Pos = 0xa
	// Bit mask of EDM field.
	DCMI_CR_EDM_Msk = 0xc00
	// Position of FCRC field.
	DCMI_CR_FCRC_Pos = 0x8
	// Bit mask of FCRC field.
	DCMI_CR_FCRC_Msk = 0x300
	// Position of VSPOL field.
	DCMI_CR_VSPOL_Pos = 0x7
	// Bit mask of VSPOL field.
	DCMI_CR_VSPOL_Msk = 0x80
	// Bit VSPOL.
	DCMI_CR_VSPOL = 0x80
	// Position of HSPOL field.
	DCMI_CR_HSPOL_Pos = 0x6
	// Bit mask of HSPOL field.
	DCMI_CR_HSPOL_Msk = 0x40
	// Bit HSPOL.
	DCMI_CR_HSPOL = 0x40
	// Position of PCKPOL field.
	DCMI_CR_PCKPOL_Pos = 0x5
	// Bit mask of PCKPOL field.
	DCMI_CR_PCKPOL_Msk = 0x20
	// Bit PCKPOL.
	DCMI_CR_PCKPOL = 0x20
	// Position of ESS field.
	DCMI_CR_ESS_Pos = 0x4
	// Bit mask of ESS field.
	DCMI_CR_ESS_Msk = 0x10
	// Bit ESS.
	DCMI_CR_ESS = 0x10
	// Position of JPEG field.
	DCMI_CR_JPEG_Pos = 0x3
	// Bit mask of JPEG field.
	DCMI_CR_JPEG_Msk = 0x8
	// Bit JPEG.
	DCMI_CR_JPEG = 0x8
	// Position of CROP field.
	DCMI_CR_CROP_Pos = 0x2
	// Bit mask of CROP field.
	DCMI_CR_CROP_Msk = 0x4
	// Bit CROP.
	DCMI_CR_CROP = 0x4
	// Position of CM field.
	DCMI_CR_CM_Pos = 0x1
	// Bit mask of CM field.
	DCMI_CR_CM_Msk = 0x2
	// Bit CM.
	DCMI_CR_CM = 0x2
	// Position of CAPTURE field.
	DCMI_CR_CAPTURE_Pos = 0x0
	// Bit mask of CAPTURE field.
	DCMI_CR_CAPTURE_Msk = 0x1
	// Bit CAPTURE.
	DCMI_CR_CAPTURE = 0x1

	// SR: status register
	// Position of FNE field.
	DCMI_SR_FNE_Pos = 0x2
	// Bit mask of FNE field.
	DCMI_SR_FNE_Msk = 0x4
	// Bit FNE.
	DCMI_SR_FNE = 0x4
	// Position of VSYNC field.
	DCMI_SR_VSYNC_Pos = 0x1
	// Bit mask of VSYNC field.
	DCMI_SR_VSYNC_Msk = 0x2
	// Bit VSYNC.
	DCMI_SR_VSYNC = 0x2
	// Position of HSYNC field.
	DCMI_SR_HSYNC_Pos = 0x0
	// Bit mask of HSYNC field.
	DCMI_SR_HSYNC_Msk = 0x1
	// Bit HSYNC.
	DCMI_SR_HSYNC = 0x1

	// RIS: raw interrupt status register
	// Position of LINE_RIS field.
	DCMI_RIS_LINE_RIS_Pos = 0x4
	// Bit mask of LINE_RIS field.
	DCMI_RIS_LINE_RIS_Msk = 0x10
	// Bit LINE_RIS.
	DCMI_RIS_LINE_RIS = 0x10
	// Position of VSYNC_RIS field.
	DCMI_RIS_VSYNC_RIS_Pos = 0x3
	// Bit mask of VSYNC_RIS field.
	DCMI_RIS_VSYNC_RIS_Msk = 0x8
	// Bit VSYNC_RIS.
	DCMI_RIS_VSYNC_RIS = 0x8
	// Position of ERR_RIS field.
	DCMI_RIS_ERR_RIS_Pos = 0x2
	// Bit mask of ERR_RIS field.
	DCMI_RIS_ERR_RIS_Msk = 0x4
	// Bit ERR_RIS.
	DCMI_RIS_ERR_RIS = 0x4
	// Position of OVR_RIS field.
	DCMI_RIS_OVR_RIS_Pos = 0x1
	// Bit mask of OVR_RIS field.
	DCMI_RIS_OVR_RIS_Msk = 0x2
	// Bit OVR_RIS.
	DCMI_RIS_OVR_RIS = 0x2
	// Position of FRAME_RIS field.
	DCMI_RIS_FRAME_RIS_Pos = 0x0
	// Bit mask of FRAME_RIS field.
	DCMI_RIS_FRAME_RIS_Msk = 0x1
	// Bit FRAME_RIS.
	DCMI_RIS_FRAME_RIS = 0x1

	// IER: interrupt enable register
	// Position of LINE_IE field.
	DCMI_IER_LINE_IE_Pos = 0x4
	// Bit mask of LINE_IE field.
	DCMI_IER_LINE_IE_Msk = 0x10
	// Bit LINE_IE.
	DCMI_IER_LINE_IE = 0x10
	// Position of VSYNC_IE field.
	DCMI_IER_VSYNC_IE_Pos = 0x3
	// Bit mask of VSYNC_IE field.
	DCMI_IER_VSYNC_IE_Msk = 0x8
	// Bit VSYNC_IE.
	DCMI_IER_VSYNC_IE = 0x8
	// Position of ERR_IE field.
	DCMI_IER_ERR_IE_Pos = 0x2
	// Bit mask of ERR_IE field.
	DCMI_IER_ERR_IE_Msk = 0x4
	// Bit ERR_IE.
	DCMI_IER_ERR_IE = 0x4
	// Position of OVR_IE field.
	DCMI_IER_OVR_IE_Pos = 0x1
	// Bit mask of OVR_IE field.
	DCMI_IER_OVR_IE_Msk = 0x2
	// Bit OVR_IE.
	DCMI_IER_OVR_IE = 0x2
	// Position of FRAME_IE field.
	DCMI_IER_FRAME_IE_Pos = 0x0
	// Bit mask of FRAME_IE field.
	DCMI_IER_FRAME_IE_Msk = 0x1
	// Bit FRAME_IE.
	DCMI_IER_FRAME_IE = 0x1

	// MIS: masked interrupt status register
	// Position of LINE_MIS field.
	DCMI_MIS_LINE_MIS_Pos = 0x4
	// Bit mask of LINE_MIS field.
	DCMI_MIS_LINE_MIS_Msk = 0x10
	// Bit LINE_MIS.
	DCMI_MIS_LINE_MIS = 0x10
	// Position of VSYNC_MIS field.
	DCMI_MIS_VSYNC_MIS_Pos = 0x3
	// Bit mask of VSYNC_MIS field.
	DCMI_MIS_VSYNC_MIS_Msk = 0x8
	// Bit VSYNC_MIS.
	DCMI_MIS_VSYNC_MIS = 0x8
	// Position of ERR_MIS field.
	DCMI_MIS_ERR_MIS_Pos = 0x2
	// Bit mask of ERR_MIS field.
	DCMI_MIS_ERR_MIS_Msk = 0x4
	// Bit ERR_MIS.
	DCMI_MIS_ERR_MIS = 0x4
	// Position of OVR_MIS field.
	DCMI_MIS_OVR_MIS_Pos = 0x1
	// Bit mask of OVR_MIS field.
	DCMI_MIS_OVR_MIS_Msk = 0x2
	// Bit OVR_MIS.
	DCMI_MIS_OVR_MIS = 0x2
	// Position of FRAME_MIS field.
	DCMI_MIS_FRAME_MIS_Pos = 0x0
	// Bit mask of FRAME_MIS field.
	DCMI_MIS_FRAME_MIS_Msk = 0x1
	// Bit FRAME_MIS.
	DCMI_MIS_FRAME_MIS = 0x1

	// ICR: interrupt clear register
	// Position of LINE_ISC field.
	DCMI_ICR_LINE_ISC_Pos = 0x4
	// Bit mask of LINE_ISC field.
	DCMI_ICR_LINE_ISC_Msk = 0x10
	// Bit LINE_ISC.
	DCMI_ICR_LINE_ISC = 0x10
	// Position of VSYNC_ISC field.
	DCMI_ICR_VSYNC_ISC_Pos = 0x3
	// Bit mask of VSYNC_ISC field.
	DCMI_ICR_VSYNC_ISC_Msk = 0x8
	// Bit VSYNC_ISC.
	DCMI_ICR_VSYNC_ISC = 0x8
	// Position of ERR_ISC field.
	DCMI_ICR_ERR_ISC_Pos = 0x2
	// Bit mask of ERR_ISC field.
	DCMI_ICR_ERR_ISC_Msk = 0x4
	// Bit ERR_ISC.
	DCMI_ICR_ERR_ISC = 0x4
	// Position of OVR_ISC field.
	DCMI_ICR_OVR_ISC_Pos = 0x1
	// Bit mask of OVR_ISC field.
	DCMI_ICR_OVR_ISC_Msk = 0x2
	// Bit OVR_ISC.
	DCMI_ICR_OVR_ISC = 0x2
	// Position of FRAME_ISC field.
	DCMI_ICR_FRAME_ISC_Pos = 0x0
	// Bit mask of FRAME_ISC field.
	DCMI_ICR_FRAME_ISC_Msk = 0x1
	// Bit FRAME_ISC.
	DCMI_ICR_FRAME_ISC = 0x1

	// ESCR: embedded synchronization code register
	// Position of FEC field.
	DCMI_ESCR_FEC_Pos = 0x18
	// Bit mask of FEC field.
	DCMI_ESCR_FEC_Msk = 0xff000000
	// Position of LEC field.
	DCMI_ESCR_LEC_Pos = 0x10
	// Bit mask of LEC field.
	DCMI_ESCR_LEC_Msk = 0xff0000
	// Position of LSC field.
	DCMI_ESCR_LSC_Pos = 0x8
	// Bit mask of LSC field.
	DCMI_ESCR_LSC_Msk = 0xff00
	// Position of FSC field.
	DCMI_ESCR_FSC_Pos = 0x0
	// Bit mask of FSC field.
	DCMI_ESCR_FSC_Msk = 0xff

	// ESUR: embedded synchronization unmask register
	// Position of FEU field.
	DCMI_ESUR_FEU_Pos = 0x18
	// Bit mask of FEU field.
	DCMI_ESUR_FEU_Msk = 0xff000000
	// Position of LEU field.
	DCMI_ESUR_LEU_Pos = 0x10
	// Bit mask of LEU field.
	DCMI_ESUR_LEU_Msk = 0xff0000
	// Position of LSU field.
	DCMI_ESUR_LSU_Pos = 0x8
	// Bit mask of LSU field.
	DCMI_ESUR_LSU_Msk = 0xff00
	// Position of FSU field.
	DCMI_ESUR_FSU_Pos = 0x0
	// Bit mask of FSU field.
	DCMI_ESUR_FSU_Msk = 0xff

	// CWSTRT: crop window start
	// Position of VST field.
	DCMI_CWSTRT_VST_Pos = 0x10
	// Bit mask of VST field.
	DCMI_CWSTRT_VST_Msk = 0x1fff0000
	// Position of HOFFCNT field.
	DCMI_CWSTRT_HOFFCNT_Pos = 0x0
	// Bit mask of HOFFCNT field.
	DCMI_CWSTRT_HOFFCNT_Msk = 0x3fff

	// CWSIZE: crop window size
	// Position of VLINE field.
	DCMI_CWSIZE_VLINE_Pos = 0x10
	// Bit mask of VLINE field.
	DCMI_CWSIZE_VLINE_Msk = 0x3fff0000
	// Position of CAPCNT field.
	DCMI_CWSIZE_CAPCNT_Pos = 0x0
	// Bit mask of CAPCNT field.
	DCMI_CWSIZE_CAPCNT_Msk = 0x3fff

	// DR: data register
	// Position of Byte3 field.
	DCMI_DR_Byte3_Pos = 0x18
	// Bit mask of Byte3 field.
	DCMI_DR_Byte3_Msk = 0xff000000
	// Position of Byte2 field.
	DCMI_DR_Byte2_Pos = 0x10
	// Bit mask of Byte2 field.
	DCMI_DR_Byte2_Msk = 0xff0000
	// Position of Byte1 field.
	DCMI_DR_Byte1_Pos = 0x8
	// Bit mask of Byte1 field.
	DCMI_DR_Byte1_Msk = 0xff00
	// Position of Byte0 field.
	DCMI_DR_Byte0_Pos = 0x0
	// Bit mask of Byte0 field.
	DCMI_DR_Byte0_Msk = 0xff
)

// Bitfields for OTG1_HS_GLOBAL: USB 1 on the go high speed
const (
	// GOTGCTL: OTG_HS control and status register
	// Position of SRQSCS field.
	USB_OTG_HS_GOTGCTL_SRQSCS_Pos = 0x0
	// Bit mask of SRQSCS field.
	USB_OTG_HS_GOTGCTL_SRQSCS_Msk = 0x1
	// Bit SRQSCS.
	USB_OTG_HS_GOTGCTL_SRQSCS = 0x1
	// Position of SRQ field.
	USB_OTG_HS_GOTGCTL_SRQ_Pos = 0x1
	// Bit mask of SRQ field.
	USB_OTG_HS_GOTGCTL_SRQ_Msk = 0x2
	// Bit SRQ.
	USB_OTG_HS_GOTGCTL_SRQ = 0x2
	// Position of HNGSCS field.
	USB_OTG_HS_GOTGCTL_HNGSCS_Pos = 0x8
	// Bit mask of HNGSCS field.
	USB_OTG_HS_GOTGCTL_HNGSCS_Msk = 0x100
	// Bit HNGSCS.
	USB_OTG_HS_GOTGCTL_HNGSCS = 0x100
	// Position of HNPRQ field.
	USB_OTG_HS_GOTGCTL_HNPRQ_Pos = 0x9
	// Bit mask of HNPRQ field.
	USB_OTG_HS_GOTGCTL_HNPRQ_Msk = 0x200
	// Bit HNPRQ.
	USB_OTG_HS_GOTGCTL_HNPRQ = 0x200
	// Position of HSHNPEN field.
	USB_OTG_HS_GOTGCTL_HSHNPEN_Pos = 0xa
	// Bit mask of HSHNPEN field.
	USB_OTG_HS_GOTGCTL_HSHNPEN_Msk = 0x400
	// Bit HSHNPEN.
	USB_OTG_HS_GOTGCTL_HSHNPEN = 0x400
	// Position of DHNPEN field.
	USB_OTG_HS_GOTGCTL_DHNPEN_Pos = 0xb
	// Bit mask of DHNPEN field.
	USB_OTG_HS_GOTGCTL_DHNPEN_Msk = 0x800
	// Bit DHNPEN.
	USB_OTG_HS_GOTGCTL_DHNPEN = 0x800
	// Position of CIDSTS field.
	USB_OTG_HS_GOTGCTL_CIDSTS_Pos = 0x10
	// Bit mask of CIDSTS field.
	USB_OTG_HS_GOTGCTL_CIDSTS_Msk = 0x10000
	// Bit CIDSTS.
	USB_OTG_HS_GOTGCTL_CIDSTS = 0x10000
	// Position of DBCT field.
	USB_OTG_HS_GOTGCTL_DBCT_Pos = 0x11
	// Bit mask of DBCT field.
	USB_OTG_HS_GOTGCTL_DBCT_Msk = 0x20000
	// Bit DBCT.
	USB_OTG_HS_GOTGCTL_DBCT = 0x20000
	// Position of ASVLD field.
	USB_OTG_HS_GOTGCTL_ASVLD_Pos = 0x12
	// Bit mask of ASVLD field.
	USB_OTG_HS_GOTGCTL_ASVLD_Msk = 0x40000
	// Bit ASVLD.
	USB_OTG_HS_GOTGCTL_ASVLD = 0x40000
	// Position of BSVLD field.
	USB_OTG_HS_GOTGCTL_BSVLD_Pos = 0x13
	// Bit mask of BSVLD field.
	USB_OTG_HS_GOTGCTL_BSVLD_Msk = 0x80000
	// Bit BSVLD.
	USB_OTG_HS_GOTGCTL_BSVLD = 0x80000
	// Position of EHEN field.
	USB_OTG_HS_GOTGCTL_EHEN_Pos = 0xc
	// Bit mask of EHEN field.
	USB_OTG_HS_GOTGCTL_EHEN_Msk = 0x1000
	// Bit EHEN.
	USB_OTG_HS_GOTGCTL_EHEN = 0x1000

	// GOTGINT: OTG_HS interrupt register
	// Position of SEDET field.
	USB_OTG_HS_GOTGINT_SEDET_Pos = 0x2
	// Bit mask of SEDET field.
	USB_OTG_HS_GOTGINT_SEDET_Msk = 0x4
	// Bit SEDET.
	USB_OTG_HS_GOTGINT_SEDET = 0x4
	// Position of SRSSCHG field.
	USB_OTG_HS_GOTGINT_SRSSCHG_Pos = 0x8
	// Bit mask of SRSSCHG field.
	USB_OTG_HS_GOTGINT_SRSSCHG_Msk = 0x100
	// Bit SRSSCHG.
	USB_OTG_HS_GOTGINT_SRSSCHG = 0x100
	// Position of HNSSCHG field.
	USB_OTG_HS_GOTGINT_HNSSCHG_Pos = 0x9
	// Bit mask of HNSSCHG field.
	USB_OTG_HS_GOTGINT_HNSSCHG_Msk = 0x200
	// Bit HNSSCHG.
	USB_OTG_HS_GOTGINT_HNSSCHG = 0x200
	// Position of HNGDET field.
	USB_OTG_HS_GOTGINT_HNGDET_Pos = 0x11
	// Bit mask of HNGDET field.
	USB_OTG_HS_GOTGINT_HNGDET_Msk = 0x20000
	// Bit HNGDET.
	USB_OTG_HS_GOTGINT_HNGDET = 0x20000
	// Position of ADTOCHG field.
	USB_OTG_HS_GOTGINT_ADTOCHG_Pos = 0x12
	// Bit mask of ADTOCHG field.
	USB_OTG_HS_GOTGINT_ADTOCHG_Msk = 0x40000
	// Bit ADTOCHG.
	USB_OTG_HS_GOTGINT_ADTOCHG = 0x40000
	// Position of DBCDNE field.
	USB_OTG_HS_GOTGINT_DBCDNE_Pos = 0x13
	// Bit mask of DBCDNE field.
	USB_OTG_HS_GOTGINT_DBCDNE_Msk = 0x80000
	// Bit DBCDNE.
	USB_OTG_HS_GOTGINT_DBCDNE = 0x80000
	// Position of IDCHNG field.
	USB_OTG_HS_GOTGINT_IDCHNG_Pos = 0x14
	// Bit mask of IDCHNG field.
	USB_OTG_HS_GOTGINT_IDCHNG_Msk = 0x100000
	// Bit IDCHNG.
	USB_OTG_HS_GOTGINT_IDCHNG = 0x100000

	// GAHBCFG: OTG_HS AHB configuration register
	// Position of GINT field.
	USB_OTG_HS_GAHBCFG_GINT_Pos = 0x0
	// Bit mask of GINT field.
	USB_OTG_HS_GAHBCFG_GINT_Msk = 0x1
	// Bit GINT.
	USB_OTG_HS_GAHBCFG_GINT = 0x1
	// Position of HBSTLEN field.
	USB_OTG_HS_GAHBCFG_HBSTLEN_Pos = 0x1
	// Bit mask of HBSTLEN field.
	USB_OTG_HS_GAHBCFG_HBSTLEN_Msk = 0x1e
	// Position of DMAEN field.
	USB_OTG_HS_GAHBCFG_DMAEN_Pos = 0x5
	// Bit mask of DMAEN field.
	USB_OTG_HS_GAHBCFG_DMAEN_Msk = 0x20
	// Bit DMAEN.
	USB_OTG_HS_GAHBCFG_DMAEN = 0x20
	// Position of TXFELVL field.
	USB_OTG_HS_GAHBCFG_TXFELVL_Pos = 0x7
	// Bit mask of TXFELVL field.
	USB_OTG_HS_GAHBCFG_TXFELVL_Msk = 0x80
	// Bit TXFELVL.
	USB_OTG_HS_GAHBCFG_TXFELVL = 0x80
	// Position of PTXFELVL field.
	USB_OTG_HS_GAHBCFG_PTXFELVL_Pos = 0x8
	// Bit mask of PTXFELVL field.
	USB_OTG_HS_GAHBCFG_PTXFELVL_Msk = 0x100
	// Bit PTXFELVL.
	USB_OTG_HS_GAHBCFG_PTXFELVL = 0x100

	// GUSBCFG: OTG_HS USB configuration register
	// Position of TOCAL field.
	USB_OTG_HS_GUSBCFG_TOCAL_Pos = 0x0
	// Bit mask of TOCAL field.
	USB_OTG_HS_GUSBCFG_TOCAL_Msk = 0x7
	// Position of PHYSEL field.
	USB_OTG_HS_GUSBCFG_PHYSEL_Pos = 0x6
	// Bit mask of PHYSEL field.
	USB_OTG_HS_GUSBCFG_PHYSEL_Msk = 0x40
	// Bit PHYSEL.
	USB_OTG_HS_GUSBCFG_PHYSEL = 0x40
	// Position of SRPCAP field.
	USB_OTG_HS_GUSBCFG_SRPCAP_Pos = 0x8
	// Bit mask of SRPCAP field.
	USB_OTG_HS_GUSBCFG_SRPCAP_Msk = 0x100
	// Bit SRPCAP.
	USB_OTG_HS_GUSBCFG_SRPCAP = 0x100
	// Position of HNPCAP field.
	USB_OTG_HS_GUSBCFG_HNPCAP_Pos = 0x9
	// Bit mask of HNPCAP field.
	USB_OTG_HS_GUSBCFG_HNPCAP_Msk = 0x200
	// Bit HNPCAP.
	USB_OTG_HS_GUSBCFG_HNPCAP = 0x200
	// Position of TRDT field.
	USB_OTG_HS_GUSBCFG_TRDT_Pos = 0xa
	// Bit mask of TRDT field.
	USB_OTG_HS_GUSBCFG_TRDT_Msk = 0x3c00
	// Position of PHYLPCS field.
	USB_OTG_HS_GUSBCFG_PHYLPCS_Pos = 0xf
	// Bit mask of PHYLPCS field.
	USB_OTG_HS_GUSBCFG_PHYLPCS_Msk = 0x8000
	// Bit PHYLPCS.
	USB_OTG_HS_GUSBCFG_PHYLPCS = 0x8000
	// Position of ULPIFSLS field.
	USB_OTG_HS_GUSBCFG_ULPIFSLS_Pos = 0x11
	// Bit mask of ULPIFSLS field.
	USB_OTG_HS_GUSBCFG_ULPIFSLS_Msk = 0x20000
	// Bit ULPIFSLS.
	USB_OTG_HS_GUSBCFG_ULPIFSLS = 0x20000
	// Position of ULPIAR field.
	USB_OTG_HS_GUSBCFG_ULPIAR_Pos = 0x12
	// Bit mask of ULPIAR field.
	USB_OTG_HS_GUSBCFG_ULPIAR_Msk = 0x40000
	// Bit ULPIAR.
	USB_OTG_HS_GUSBCFG_ULPIAR = 0x40000
	// Position of ULPICSM field.
	USB_OTG_HS_GUSBCFG_ULPICSM_Pos = 0x13
	// Bit mask of ULPICSM field.
	USB_OTG_HS_GUSBCFG_ULPICSM_Msk = 0x80000
	// Bit ULPICSM.
	USB_OTG_HS_GUSBCFG_ULPICSM = 0x80000
	// Position of ULPIEVBUSD field.
	USB_OTG_HS_GUSBCFG_ULPIEVBUSD_Pos = 0x14
	// Bit mask of ULPIEVBUSD field.
	USB_OTG_HS_GUSBCFG_ULPIEVBUSD_Msk = 0x100000
	// Bit ULPIEVBUSD.
	USB_OTG_HS_GUSBCFG_ULPIEVBUSD = 0x100000
	// Position of ULPIEVBUSI field.
	USB_OTG_HS_GUSBCFG_ULPIEVBUSI_Pos = 0x15
	// Bit mask of ULPIEVBUSI field.
	USB_OTG_HS_GUSBCFG_ULPIEVBUSI_Msk = 0x200000
	// Bit ULPIEVBUSI.
	USB_OTG_HS_GUSBCFG_ULPIEVBUSI = 0x200000
	// Position of TSDPS field.
	USB_OTG_HS_GUSBCFG_TSDPS_Pos = 0x16
	// Bit mask of TSDPS field.
	USB_OTG_HS_GUSBCFG_TSDPS_Msk = 0x400000
	// Bit TSDPS.
	USB_OTG_HS_GUSBCFG_TSDPS = 0x400000
	// Position of PCCI field.
	USB_OTG_HS_GUSBCFG_PCCI_Pos = 0x17
	// Bit mask of PCCI field.
	USB_OTG_HS_GUSBCFG_PCCI_Msk = 0x800000
	// Bit PCCI.
	USB_OTG_HS_GUSBCFG_PCCI = 0x800000
	// Position of PTCI field.
	USB_OTG_HS_GUSBCFG_PTCI_Pos = 0x18
	// Bit mask of PTCI field.
	USB_OTG_HS_GUSBCFG_PTCI_Msk = 0x1000000
	// Bit PTCI.
	USB_OTG_HS_GUSBCFG_PTCI = 0x1000000
	// Position of ULPIIPD field.
	USB_OTG_HS_GUSBCFG_ULPIIPD_Pos = 0x19
	// Bit mask of ULPIIPD field.
	USB_OTG_HS_GUSBCFG_ULPIIPD_Msk = 0x2000000
	// Bit ULPIIPD.
	USB_OTG_HS_GUSBCFG_ULPIIPD = 0x2000000
	// Position of FHMOD field.
	USB_OTG_HS_GUSBCFG_FHMOD_Pos = 0x1d
	// Bit mask of FHMOD field.
	USB_OTG_HS_GUSBCFG_FHMOD_Msk = 0x20000000
	// Bit FHMOD.
	USB_OTG_HS_GUSBCFG_FHMOD = 0x20000000
	// Position of FDMOD field.
	USB_OTG_HS_GUSBCFG_FDMOD_Pos = 0x1e
	// Bit mask of FDMOD field.
	USB_OTG_HS_GUSBCFG_FDMOD_Msk = 0x40000000
	// Bit FDMOD.
	USB_OTG_HS_GUSBCFG_FDMOD = 0x40000000

	// GRSTCTL: OTG_HS reset register
	// Position of CSRST field.
	USB_OTG_HS_GRSTCTL_CSRST_Pos = 0x0
	// Bit mask of CSRST field.
	USB_OTG_HS_GRSTCTL_CSRST_Msk = 0x1
	// Bit CSRST.
	USB_OTG_HS_GRSTCTL_CSRST = 0x1
	// Position of HSRST field.
	USB_OTG_HS_GRSTCTL_HSRST_Pos = 0x1
	// Bit mask of HSRST field.
	USB_OTG_HS_GRSTCTL_HSRST_Msk = 0x2
	// Bit HSRST.
	USB_OTG_HS_GRSTCTL_HSRST = 0x2
	// Position of FCRST field.
	USB_OTG_HS_GRSTCTL_FCRST_Pos = 0x2
	// Bit mask of FCRST field.
	USB_OTG_HS_GRSTCTL_FCRST_Msk = 0x4
	// Bit FCRST.
	USB_OTG_HS_GRSTCTL_FCRST = 0x4
	// Position of RXFFLSH field.
	USB_OTG_HS_GRSTCTL_RXFFLSH_Pos = 0x4
	// Bit mask of RXFFLSH field.
	USB_OTG_HS_GRSTCTL_RXFFLSH_Msk = 0x10
	// Bit RXFFLSH.
	USB_OTG_HS_GRSTCTL_RXFFLSH = 0x10
	// Position of TXFFLSH field.
	USB_OTG_HS_GRSTCTL_TXFFLSH_Pos = 0x5
	// Bit mask of TXFFLSH field.
	USB_OTG_HS_GRSTCTL_TXFFLSH_Msk = 0x20
	// Bit TXFFLSH.
	USB_OTG_HS_GRSTCTL_TXFFLSH = 0x20
	// Position of TXFNUM field.
	USB_OTG_HS_GRSTCTL_TXFNUM_Pos = 0x6
	// Bit mask of TXFNUM field.
	USB_OTG_HS_GRSTCTL_TXFNUM_Msk = 0x7c0
	// Position of AHBIDL field.
	USB_OTG_HS_GRSTCTL_AHBIDL_Pos = 0x1f
	// Bit mask of AHBIDL field.
	USB_OTG_HS_GRSTCTL_AHBIDL_Msk = 0x80000000
	// Bit AHBIDL.
	USB_OTG_HS_GRSTCTL_AHBIDL = 0x80000000
	// Position of DMAREQ field.
	USB_OTG_HS_GRSTCTL_DMAREQ_Pos = 0x1e
	// Bit mask of DMAREQ field.
	USB_OTG_HS_GRSTCTL_DMAREQ_Msk = 0x40000000
	// Bit DMAREQ.
	USB_OTG_HS_GRSTCTL_DMAREQ = 0x40000000

	// GINTSTS: OTG_HS core interrupt register
	// Position of CMOD field.
	USB_OTG_HS_GINTSTS_CMOD_Pos = 0x0
	// Bit mask of CMOD field.
	USB_OTG_HS_GINTSTS_CMOD_Msk = 0x1
	// Bit CMOD.
	USB_OTG_HS_GINTSTS_CMOD = 0x1
	// Position of MMIS field.
	USB_OTG_HS_GINTSTS_MMIS_Pos = 0x1
	// Bit mask of MMIS field.
	USB_OTG_HS_GINTSTS_MMIS_Msk = 0x2
	// Bit MMIS.
	USB_OTG_HS_GINTSTS_MMIS = 0x2
	// Position of OTGINT field.
	USB_OTG_HS_GINTSTS_OTGINT_Pos = 0x2
	// Bit mask of OTGINT field.
	USB_OTG_HS_GINTSTS_OTGINT_Msk = 0x4
	// Bit OTGINT.
	USB_OTG_HS_GINTSTS_OTGINT = 0x4
	// Position of SOF field.
	USB_OTG_HS_GINTSTS_SOF_Pos = 0x3
	// Bit mask of SOF field.
	USB_OTG_HS_GINTSTS_SOF_Msk = 0x8
	// Bit SOF.
	USB_OTG_HS_GINTSTS_SOF = 0x8
	// Position of RXFLVL field.
	USB_OTG_HS_GINTSTS_RXFLVL_Pos = 0x4
	// Bit mask of RXFLVL field.
	USB_OTG_HS_GINTSTS_RXFLVL_Msk = 0x10
	// Bit RXFLVL.
	USB_OTG_HS_GINTSTS_RXFLVL = 0x10
	// Position of NPTXFE field.
	USB_OTG_HS_GINTSTS_NPTXFE_Pos = 0x5
	// Bit mask of NPTXFE field.
	USB_OTG_HS_GINTSTS_NPTXFE_Msk = 0x20
	// Bit NPTXFE.
	USB_OTG_HS_GINTSTS_NPTXFE = 0x20
	// Position of GINAKEFF field.
	USB_OTG_HS_GINTSTS_GINAKEFF_Pos = 0x6
	// Bit mask of GINAKEFF field.
	USB_OTG_HS_GINTSTS_GINAKEFF_Msk = 0x40
	// Bit GINAKEFF.
	USB_OTG_HS_GINTSTS_GINAKEFF = 0x40
	// Position of BOUTNAKEFF field.
	USB_OTG_HS_GINTSTS_BOUTNAKEFF_Pos = 0x7
	// Bit mask of BOUTNAKEFF field.
	USB_OTG_HS_GINTSTS_BOUTNAKEFF_Msk = 0x80
	// Bit BOUTNAKEFF.
	USB_OTG_HS_GINTSTS_BOUTNAKEFF = 0x80
	// Position of ESUSP field.
	USB_OTG_HS_GINTSTS_ESUSP_Pos = 0xa
	// Bit mask of ESUSP field.
	USB_OTG_HS_GINTSTS_ESUSP_Msk = 0x400
	// Bit ESUSP.
	USB_OTG_HS_GINTSTS_ESUSP = 0x400
	// Position of USBSUSP field.
	USB_OTG_HS_GINTSTS_USBSUSP_Pos = 0xb
	// Bit mask of USBSUSP field.
	USB_OTG_HS_GINTSTS_USBSUSP_Msk = 0x800
	// Bit USBSUSP.
	USB_OTG_HS_GINTSTS_USBSUSP = 0x800
	// Position of USBRST field.
	USB_OTG_HS_GINTSTS_USBRST_Pos = 0xc
	// Bit mask of USBRST field.
	USB_OTG_HS_GINTSTS_USBRST_Msk = 0x1000
	// Bit USBRST.
	USB_OTG_HS_GINTSTS_USBRST = 0x1000
	// Position of ENUMDNE field.
	USB_OTG_HS_GINTSTS_ENUMDNE_Pos = 0xd
	// Bit mask of ENUMDNE field.
	USB_OTG_HS_GINTSTS_ENUMDNE_Msk = 0x2000
	// Bit ENUMDNE.
	USB_OTG_HS_GINTSTS_ENUMDNE = 0x2000
	// Position of ISOODRP field.
	USB_OTG_HS_GINTSTS_ISOODRP_Pos = 0xe
	// Bit mask of ISOODRP field.
	USB_OTG_HS_GINTSTS_ISOODRP_Msk = 0x4000
	// Bit ISOODRP.
	USB_OTG_HS_GINTSTS_ISOODRP = 0x4000
	// Position of EOPF field.
	USB_OTG_HS_GINTSTS_EOPF_Pos = 0xf
	// Bit mask of EOPF field.
	USB_OTG_HS_GINTSTS_EOPF_Msk = 0x8000
	// Bit EOPF.
	USB_OTG_HS_GINTSTS_EOPF = 0x8000
	// Position of IEPINT field.
	USB_OTG_HS_GINTSTS_IEPINT_Pos = 0x12
	// Bit mask of IEPINT field.
	USB_OTG_HS_GINTSTS_IEPINT_Msk = 0x40000
	// Bit IEPINT.
	USB_OTG_HS_GINTSTS_IEPINT = 0x40000
	// Position of OEPINT field.
	USB_OTG_HS_GINTSTS_OEPINT_Pos = 0x13
	// Bit mask of OEPINT field.
	USB_OTG_HS_GINTSTS_OEPINT_Msk = 0x80000
	// Bit OEPINT.
	USB_OTG_HS_GINTSTS_OEPINT = 0x80000
	// Position of IISOIXFR field.
	USB_OTG_HS_GINTSTS_IISOIXFR_Pos = 0x14
	// Bit mask of IISOIXFR field.
	USB_OTG_HS_GINTSTS_IISOIXFR_Msk = 0x100000
	// Bit IISOIXFR.
	USB_OTG_HS_GINTSTS_IISOIXFR = 0x100000
	// Position of PXFR_INCOMPISOOUT field.
	USB_OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Pos = 0x15
	// Bit mask of PXFR_INCOMPISOOUT field.
	USB_OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Msk = 0x200000
	// Bit PXFR_INCOMPISOOUT.
	USB_OTG_HS_GINTSTS_PXFR_INCOMPISOOUT = 0x200000
	// Position of DATAFSUSP field.
	USB_OTG_HS_GINTSTS_DATAFSUSP_Pos = 0x16
	// Bit mask of DATAFSUSP field.
	USB_OTG_HS_GINTSTS_DATAFSUSP_Msk = 0x400000
	// Bit DATAFSUSP.
	USB_OTG_HS_GINTSTS_DATAFSUSP = 0x400000
	// Position of HPRTINT field.
	USB_OTG_HS_GINTSTS_HPRTINT_Pos = 0x18
	// Bit mask of HPRTINT field.
	USB_OTG_HS_GINTSTS_HPRTINT_Msk = 0x1000000
	// Bit HPRTINT.
	USB_OTG_HS_GINTSTS_HPRTINT = 0x1000000
	// Position of HCINT field.
	USB_OTG_HS_GINTSTS_HCINT_Pos = 0x19
	// Bit mask of HCINT field.
	USB_OTG_HS_GINTSTS_HCINT_Msk = 0x2000000
	// Bit HCINT.
	USB_OTG_HS_GINTSTS_HCINT = 0x2000000
	// Position of PTXFE field.
	USB_OTG_HS_GINTSTS_PTXFE_Pos = 0x1a
	// Bit mask of PTXFE field.
	USB_OTG_HS_GINTSTS_PTXFE_Msk = 0x4000000
	// Bit PTXFE.
	USB_OTG_HS_GINTSTS_PTXFE = 0x4000000
	// Position of CIDSCHG field.
	USB_OTG_HS_GINTSTS_CIDSCHG_Pos = 0x1c
	// Bit mask of CIDSCHG field.
	USB_OTG_HS_GINTSTS_CIDSCHG_Msk = 0x10000000
	// Bit CIDSCHG.
	USB_OTG_HS_GINTSTS_CIDSCHG = 0x10000000
	// Position of DISCINT field.
	USB_OTG_HS_GINTSTS_DISCINT_Pos = 0x1d
	// Bit mask of DISCINT field.
	USB_OTG_HS_GINTSTS_DISCINT_Msk = 0x20000000
	// Bit DISCINT.
	USB_OTG_HS_GINTSTS_DISCINT = 0x20000000
	// Position of SRQINT field.
	USB_OTG_HS_GINTSTS_SRQINT_Pos = 0x1e
	// Bit mask of SRQINT field.
	USB_OTG_HS_GINTSTS_SRQINT_Msk = 0x40000000
	// Bit SRQINT.
	USB_OTG_HS_GINTSTS_SRQINT = 0x40000000
	// Position of WKUINT field.
	USB_OTG_HS_GINTSTS_WKUINT_Pos = 0x1f
	// Bit mask of WKUINT field.
	USB_OTG_HS_GINTSTS_WKUINT_Msk = 0x80000000
	// Bit WKUINT.
	USB_OTG_HS_GINTSTS_WKUINT = 0x80000000

	// GINTMSK: OTG_HS interrupt mask register
	// Position of MMISM field.
	USB_OTG_HS_GINTMSK_MMISM_Pos = 0x1
	// Bit mask of MMISM field.
	USB_OTG_HS_GINTMSK_MMISM_Msk = 0x2
	// Bit MMISM.
	USB_OTG_HS_GINTMSK_MMISM = 0x2
	// Position of OTGINT field.
	USB_OTG_HS_GINTMSK_OTGINT_Pos = 0x2
	// Bit mask of OTGINT field.
	USB_OTG_HS_GINTMSK_OTGINT_Msk = 0x4
	// Bit OTGINT.
	USB_OTG_HS_GINTMSK_OTGINT = 0x4
	// Position of SOFM field.
	USB_OTG_HS_GINTMSK_SOFM_Pos = 0x3
	// Bit mask of SOFM field.
	USB_OTG_HS_GINTMSK_SOFM_Msk = 0x8
	// Bit SOFM.
	USB_OTG_HS_GINTMSK_SOFM = 0x8
	// Position of RXFLVLM field.
	USB_OTG_HS_GINTMSK_RXFLVLM_Pos = 0x4
	// Bit mask of RXFLVLM field.
	USB_OTG_HS_GINTMSK_RXFLVLM_Msk = 0x10
	// Bit RXFLVLM.
	USB_OTG_HS_GINTMSK_RXFLVLM = 0x10
	// Position of NPTXFEM field.
	USB_OTG_HS_GINTMSK_NPTXFEM_Pos = 0x5
	// Bit mask of NPTXFEM field.
	USB_OTG_HS_GINTMSK_NPTXFEM_Msk = 0x20
	// Bit NPTXFEM.
	USB_OTG_HS_GINTMSK_NPTXFEM = 0x20
	// Position of GINAKEFFM field.
	USB_OTG_HS_GINTMSK_GINAKEFFM_Pos = 0x6
	// Bit mask of GINAKEFFM field.
	USB_OTG_HS_GINTMSK_GINAKEFFM_Msk = 0x40
	// Bit GINAKEFFM.
	USB_OTG_HS_GINTMSK_GINAKEFFM = 0x40
	// Position of GONAKEFFM field.
	USB_OTG_HS_GINTMSK_GONAKEFFM_Pos = 0x7
	// Bit mask of GONAKEFFM field.
	USB_OTG_HS_GINTMSK_GONAKEFFM_Msk = 0x80
	// Bit GONAKEFFM.
	USB_OTG_HS_GINTMSK_GONAKEFFM = 0x80
	// Position of ESUSPM field.
	USB_OTG_HS_GINTMSK_ESUSPM_Pos = 0xa
	// Bit mask of ESUSPM field.
	USB_OTG_HS_GINTMSK_ESUSPM_Msk = 0x400
	// Bit ESUSPM.
	USB_OTG_HS_GINTMSK_ESUSPM = 0x400
	// Position of USBSUSPM field.
	USB_OTG_HS_GINTMSK_USBSUSPM_Pos = 0xb
	// Bit mask of USBSUSPM field.
	USB_OTG_HS_GINTMSK_USBSUSPM_Msk = 0x800
	// Bit USBSUSPM.
	USB_OTG_HS_GINTMSK_USBSUSPM = 0x800
	// Position of USBRST field.
	USB_OTG_HS_GINTMSK_USBRST_Pos = 0xc
	// Bit mask of USBRST field.
	USB_OTG_HS_GINTMSK_USBRST_Msk = 0x1000
	// Bit USBRST.
	USB_OTG_HS_GINTMSK_USBRST = 0x1000
	// Position of ENUMDNEM field.
	USB_OTG_HS_GINTMSK_ENUMDNEM_Pos = 0xd
	// Bit mask of ENUMDNEM field.
	USB_OTG_HS_GINTMSK_ENUMDNEM_Msk = 0x2000
	// Bit ENUMDNEM.
	USB_OTG_HS_GINTMSK_ENUMDNEM = 0x2000
	// Position of ISOODRPM field.
	USB_OTG_HS_GINTMSK_ISOODRPM_Pos = 0xe
	// Bit mask of ISOODRPM field.
	USB_OTG_HS_GINTMSK_ISOODRPM_Msk = 0x4000
	// Bit ISOODRPM.
	USB_OTG_HS_GINTMSK_ISOODRPM = 0x4000
	// Position of EOPFM field.
	USB_OTG_HS_GINTMSK_EOPFM_Pos = 0xf
	// Bit mask of EOPFM field.
	USB_OTG_HS_GINTMSK_EOPFM_Msk = 0x8000
	// Bit EOPFM.
	USB_OTG_HS_GINTMSK_EOPFM = 0x8000
	// Position of IEPINT field.
	USB_OTG_HS_GINTMSK_IEPINT_Pos = 0x12
	// Bit mask of IEPINT field.
	USB_OTG_HS_GINTMSK_IEPINT_Msk = 0x40000
	// Bit IEPINT.
	USB_OTG_HS_GINTMSK_IEPINT = 0x40000
	// Position of OEPINT field.
	USB_OTG_HS_GINTMSK_OEPINT_Pos = 0x13
	// Bit mask of OEPINT field.
	USB_OTG_HS_GINTMSK_OEPINT_Msk = 0x80000
	// Bit OEPINT.
	USB_OTG_HS_GINTMSK_OEPINT = 0x80000
	// Position of IISOIXFRM field.
	USB_OTG_HS_GINTMSK_IISOIXFRM_Pos = 0x14
	// Bit mask of IISOIXFRM field.
	USB_OTG_HS_GINTMSK_IISOIXFRM_Msk = 0x100000
	// Bit IISOIXFRM.
	USB_OTG_HS_GINTMSK_IISOIXFRM = 0x100000
	// Position of PXFRM_IISOOXFRM field.
	USB_OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Pos = 0x15
	// Bit mask of PXFRM_IISOOXFRM field.
	USB_OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Msk = 0x200000
	// Bit PXFRM_IISOOXFRM.
	USB_OTG_HS_GINTMSK_PXFRM_IISOOXFRM = 0x200000
	// Position of FSUSPM field.
	USB_OTG_HS_GINTMSK_FSUSPM_Pos = 0x16
	// Bit mask of FSUSPM field.
	USB_OTG_HS_GINTMSK_FSUSPM_Msk = 0x400000
	// Bit FSUSPM.
	USB_OTG_HS_GINTMSK_FSUSPM = 0x400000
	// Position of PRTIM field.
	USB_OTG_HS_GINTMSK_PRTIM_Pos = 0x18
	// Bit mask of PRTIM field.
	USB_OTG_HS_GINTMSK_PRTIM_Msk = 0x1000000
	// Bit PRTIM.
	USB_OTG_HS_GINTMSK_PRTIM = 0x1000000
	// Position of HCIM field.
	USB_OTG_HS_GINTMSK_HCIM_Pos = 0x19
	// Bit mask of HCIM field.
	USB_OTG_HS_GINTMSK_HCIM_Msk = 0x2000000
	// Bit HCIM.
	USB_OTG_HS_GINTMSK_HCIM = 0x2000000
	// Position of PTXFEM field.
	USB_OTG_HS_GINTMSK_PTXFEM_Pos = 0x1a
	// Bit mask of PTXFEM field.
	USB_OTG_HS_GINTMSK_PTXFEM_Msk = 0x4000000
	// Bit PTXFEM.
	USB_OTG_HS_GINTMSK_PTXFEM = 0x4000000
	// Position of CIDSCHGM field.
	USB_OTG_HS_GINTMSK_CIDSCHGM_Pos = 0x1c
	// Bit mask of CIDSCHGM field.
	USB_OTG_HS_GINTMSK_CIDSCHGM_Msk = 0x10000000
	// Bit CIDSCHGM.
	USB_OTG_HS_GINTMSK_CIDSCHGM = 0x10000000
	// Position of DISCINT field.
	USB_OTG_HS_GINTMSK_DISCINT_Pos = 0x1d
	// Bit mask of DISCINT field.
	USB_OTG_HS_GINTMSK_DISCINT_Msk = 0x20000000
	// Bit DISCINT.
	USB_OTG_HS_GINTMSK_DISCINT = 0x20000000
	// Position of SRQIM field.
	USB_OTG_HS_GINTMSK_SRQIM_Pos = 0x1e
	// Bit mask of SRQIM field.
	USB_OTG_HS_GINTMSK_SRQIM_Msk = 0x40000000
	// Bit SRQIM.
	USB_OTG_HS_GINTMSK_SRQIM = 0x40000000
	// Position of WUIM field.
	USB_OTG_HS_GINTMSK_WUIM_Pos = 0x1f
	// Bit mask of WUIM field.
	USB_OTG_HS_GINTMSK_WUIM_Msk = 0x80000000
	// Bit WUIM.
	USB_OTG_HS_GINTMSK_WUIM = 0x80000000
	// Position of RSTDE field.
	USB_OTG_HS_GINTMSK_RSTDE_Pos = 0x17
	// Bit mask of RSTDE field.
	USB_OTG_HS_GINTMSK_RSTDE_Msk = 0x800000
	// Bit RSTDE.
	USB_OTG_HS_GINTMSK_RSTDE = 0x800000
	// Position of LPMINTM field.
	USB_OTG_HS_GINTMSK_LPMINTM_Pos = 0x1b
	// Bit mask of LPMINTM field.
	USB_OTG_HS_GINTMSK_LPMINTM_Msk = 0x8000000
	// Bit LPMINTM.
	USB_OTG_HS_GINTMSK_LPMINTM = 0x8000000

	// GRXSTSR_Host: OTG_HS Receive status debug read register (host mode)
	// Position of CHNUM field.
	USB_OTG_HS_GRXSTSR_Host_CHNUM_Pos = 0x0
	// Bit mask of CHNUM field.
	USB_OTG_HS_GRXSTSR_Host_CHNUM_Msk = 0xf
	// Position of BCNT field.
	USB_OTG_HS_GRXSTSR_Host_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	USB_OTG_HS_GRXSTSR_Host_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	USB_OTG_HS_GRXSTSR_Host_DPID_Pos = 0xf
	// Bit mask of DPID field.
	USB_OTG_HS_GRXSTSR_Host_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	USB_OTG_HS_GRXSTSR_Host_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	USB_OTG_HS_GRXSTSR_Host_PKTSTS_Msk = 0x1e0000

	// GRXSTSR_Device: OTG_HS Receive status debug read register (peripheral mode mode)
	// Position of EPNUM field.
	USB_OTG_HS_GRXSTSR_Device_EPNUM_Pos = 0x0
	// Bit mask of EPNUM field.
	USB_OTG_HS_GRXSTSR_Device_EPNUM_Msk = 0xf
	// Position of BCNT field.
	USB_OTG_HS_GRXSTSR_Device_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	USB_OTG_HS_GRXSTSR_Device_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	USB_OTG_HS_GRXSTSR_Device_DPID_Pos = 0xf
	// Bit mask of DPID field.
	USB_OTG_HS_GRXSTSR_Device_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	USB_OTG_HS_GRXSTSR_Device_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	USB_OTG_HS_GRXSTSR_Device_PKTSTS_Msk = 0x1e0000
	// Position of FRMNUM field.
	USB_OTG_HS_GRXSTSR_Device_FRMNUM_Pos = 0x15
	// Bit mask of FRMNUM field.
	USB_OTG_HS_GRXSTSR_Device_FRMNUM_Msk = 0x1e00000

	// GRXSTSP_Host: OTG_HS status read and pop register (host mode)
	// Position of CHNUM field.
	USB_OTG_HS_GRXSTSP_Host_CHNUM_Pos = 0x0
	// Bit mask of CHNUM field.
	USB_OTG_HS_GRXSTSP_Host_CHNUM_Msk = 0xf
	// Position of BCNT field.
	USB_OTG_HS_GRXSTSP_Host_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	USB_OTG_HS_GRXSTSP_Host_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	USB_OTG_HS_GRXSTSP_Host_DPID_Pos = 0xf
	// Bit mask of DPID field.
	USB_OTG_HS_GRXSTSP_Host_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	USB_OTG_HS_GRXSTSP_Host_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	USB_OTG_HS_GRXSTSP_Host_PKTSTS_Msk = 0x1e0000

	// GRXSTSP_Device: OTG_HS status read and pop register (peripheral mode)
	// Position of EPNUM field.
	USB_OTG_HS_GRXSTSP_Device_EPNUM_Pos = 0x0
	// Bit mask of EPNUM field.
	USB_OTG_HS_GRXSTSP_Device_EPNUM_Msk = 0xf
	// Position of BCNT field.
	USB_OTG_HS_GRXSTSP_Device_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	USB_OTG_HS_GRXSTSP_Device_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	USB_OTG_HS_GRXSTSP_Device_DPID_Pos = 0xf
	// Bit mask of DPID field.
	USB_OTG_HS_GRXSTSP_Device_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	USB_OTG_HS_GRXSTSP_Device_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	USB_OTG_HS_GRXSTSP_Device_PKTSTS_Msk = 0x1e0000
	// Position of FRMNUM field.
	USB_OTG_HS_GRXSTSP_Device_FRMNUM_Pos = 0x15
	// Bit mask of FRMNUM field.
	USB_OTG_HS_GRXSTSP_Device_FRMNUM_Msk = 0x1e00000

	// GRXFSIZ: OTG_HS Receive FIFO size register
	// Position of RXFD field.
	USB_OTG_HS_GRXFSIZ_RXFD_Pos = 0x0
	// Bit mask of RXFD field.
	USB_OTG_HS_GRXFSIZ_RXFD_Msk = 0xffff

	// HNPTXFSIZ_Host: OTG_HS nonperiodic transmit FIFO size register (host mode)
	// Position of NPTXFSA field.
	USB_OTG_HS_HNPTXFSIZ_Host_NPTXFSA_Pos = 0x0
	// Bit mask of NPTXFSA field.
	USB_OTG_HS_HNPTXFSIZ_Host_NPTXFSA_Msk = 0xffff
	// Position of NPTXFD field.
	USB_OTG_HS_HNPTXFSIZ_Host_NPTXFD_Pos = 0x10
	// Bit mask of NPTXFD field.
	USB_OTG_HS_HNPTXFSIZ_Host_NPTXFD_Msk = 0xffff0000

	// DIEPTXF0_Device: Endpoint 0 transmit FIFO size (peripheral mode)
	// Position of TX0FSA field.
	USB_OTG_HS_DIEPTXF0_Device_TX0FSA_Pos = 0x0
	// Bit mask of TX0FSA field.
	USB_OTG_HS_DIEPTXF0_Device_TX0FSA_Msk = 0xffff
	// Position of TX0FD field.
	USB_OTG_HS_DIEPTXF0_Device_TX0FD_Pos = 0x10
	// Bit mask of TX0FD field.
	USB_OTG_HS_DIEPTXF0_Device_TX0FD_Msk = 0xffff0000

	// GNPTXSTS: OTG_HS nonperiodic transmit FIFO/queue status register
	// Position of NPTXFSAV field.
	USB_OTG_HS_GNPTXSTS_NPTXFSAV_Pos = 0x0
	// Bit mask of NPTXFSAV field.
	USB_OTG_HS_GNPTXSTS_NPTXFSAV_Msk = 0xffff
	// Position of NPTQXSAV field.
	USB_OTG_HS_GNPTXSTS_NPTQXSAV_Pos = 0x10
	// Bit mask of NPTQXSAV field.
	USB_OTG_HS_GNPTXSTS_NPTQXSAV_Msk = 0xff0000
	// Position of NPTXQTOP field.
	USB_OTG_HS_GNPTXSTS_NPTXQTOP_Pos = 0x18
	// Bit mask of NPTXQTOP field.
	USB_OTG_HS_GNPTXSTS_NPTXQTOP_Msk = 0x7f000000

	// GCCFG: OTG_HS general core configuration register
	// Position of PWRDWN field.
	USB_OTG_HS_GCCFG_PWRDWN_Pos = 0x10
	// Bit mask of PWRDWN field.
	USB_OTG_HS_GCCFG_PWRDWN_Msk = 0x10000
	// Bit PWRDWN.
	USB_OTG_HS_GCCFG_PWRDWN = 0x10000
	// Position of BCDEN field.
	USB_OTG_HS_GCCFG_BCDEN_Pos = 0x11
	// Bit mask of BCDEN field.
	USB_OTG_HS_GCCFG_BCDEN_Msk = 0x20000
	// Bit BCDEN.
	USB_OTG_HS_GCCFG_BCDEN = 0x20000
	// Position of DCDEN field.
	USB_OTG_HS_GCCFG_DCDEN_Pos = 0x12
	// Bit mask of DCDEN field.
	USB_OTG_HS_GCCFG_DCDEN_Msk = 0x40000
	// Bit DCDEN.
	USB_OTG_HS_GCCFG_DCDEN = 0x40000
	// Position of PDEN field.
	USB_OTG_HS_GCCFG_PDEN_Pos = 0x13
	// Bit mask of PDEN field.
	USB_OTG_HS_GCCFG_PDEN_Msk = 0x80000
	// Bit PDEN.
	USB_OTG_HS_GCCFG_PDEN = 0x80000
	// Position of SDEN field.
	USB_OTG_HS_GCCFG_SDEN_Pos = 0x14
	// Bit mask of SDEN field.
	USB_OTG_HS_GCCFG_SDEN_Msk = 0x100000
	// Bit SDEN.
	USB_OTG_HS_GCCFG_SDEN = 0x100000
	// Position of VBDEN field.
	USB_OTG_HS_GCCFG_VBDEN_Pos = 0x15
	// Bit mask of VBDEN field.
	USB_OTG_HS_GCCFG_VBDEN_Msk = 0x200000
	// Bit VBDEN.
	USB_OTG_HS_GCCFG_VBDEN = 0x200000
	// Position of DCDET field.
	USB_OTG_HS_GCCFG_DCDET_Pos = 0x0
	// Bit mask of DCDET field.
	USB_OTG_HS_GCCFG_DCDET_Msk = 0x1
	// Bit DCDET.
	USB_OTG_HS_GCCFG_DCDET = 0x1
	// Position of PDET field.
	USB_OTG_HS_GCCFG_PDET_Pos = 0x1
	// Bit mask of PDET field.
	USB_OTG_HS_GCCFG_PDET_Msk = 0x2
	// Bit PDET.
	USB_OTG_HS_GCCFG_PDET = 0x2
	// Position of SDET field.
	USB_OTG_HS_GCCFG_SDET_Pos = 0x2
	// Bit mask of SDET field.
	USB_OTG_HS_GCCFG_SDET_Msk = 0x4
	// Bit SDET.
	USB_OTG_HS_GCCFG_SDET = 0x4
	// Position of PS2DET field.
	USB_OTG_HS_GCCFG_PS2DET_Pos = 0x3
	// Bit mask of PS2DET field.
	USB_OTG_HS_GCCFG_PS2DET_Msk = 0x8
	// Bit PS2DET.
	USB_OTG_HS_GCCFG_PS2DET = 0x8

	// CID: OTG_HS core ID register
	// Position of PRODUCT_ID field.
	USB_OTG_HS_CID_PRODUCT_ID_Pos = 0x0
	// Bit mask of PRODUCT_ID field.
	USB_OTG_HS_CID_PRODUCT_ID_Msk = 0xffffffff

	// GLPMCFG: OTG core LPM configuration register
	// Position of LPMEN field.
	USB_OTG_HS_GLPMCFG_LPMEN_Pos = 0x0
	// Bit mask of LPMEN field.
	USB_OTG_HS_GLPMCFG_LPMEN_Msk = 0x1
	// Bit LPMEN.
	USB_OTG_HS_GLPMCFG_LPMEN = 0x1
	// Position of LPMACK field.
	USB_OTG_HS_GLPMCFG_LPMACK_Pos = 0x1
	// Bit mask of LPMACK field.
	USB_OTG_HS_GLPMCFG_LPMACK_Msk = 0x2
	// Bit LPMACK.
	USB_OTG_HS_GLPMCFG_LPMACK = 0x2
	// Position of BESL field.
	USB_OTG_HS_GLPMCFG_BESL_Pos = 0x2
	// Bit mask of BESL field.
	USB_OTG_HS_GLPMCFG_BESL_Msk = 0x3c
	// Position of REMWAKE field.
	USB_OTG_HS_GLPMCFG_REMWAKE_Pos = 0x6
	// Bit mask of REMWAKE field.
	USB_OTG_HS_GLPMCFG_REMWAKE_Msk = 0x40
	// Bit REMWAKE.
	USB_OTG_HS_GLPMCFG_REMWAKE = 0x40
	// Position of L1SSEN field.
	USB_OTG_HS_GLPMCFG_L1SSEN_Pos = 0x7
	// Bit mask of L1SSEN field.
	USB_OTG_HS_GLPMCFG_L1SSEN_Msk = 0x80
	// Bit L1SSEN.
	USB_OTG_HS_GLPMCFG_L1SSEN = 0x80
	// Position of BESLTHRS field.
	USB_OTG_HS_GLPMCFG_BESLTHRS_Pos = 0x8
	// Bit mask of BESLTHRS field.
	USB_OTG_HS_GLPMCFG_BESLTHRS_Msk = 0xf00
	// Position of L1DSEN field.
	USB_OTG_HS_GLPMCFG_L1DSEN_Pos = 0xc
	// Bit mask of L1DSEN field.
	USB_OTG_HS_GLPMCFG_L1DSEN_Msk = 0x1000
	// Bit L1DSEN.
	USB_OTG_HS_GLPMCFG_L1DSEN = 0x1000
	// Position of LPMRST field.
	USB_OTG_HS_GLPMCFG_LPMRST_Pos = 0xd
	// Bit mask of LPMRST field.
	USB_OTG_HS_GLPMCFG_LPMRST_Msk = 0x6000
	// Position of SLPSTS field.
	USB_OTG_HS_GLPMCFG_SLPSTS_Pos = 0xf
	// Bit mask of SLPSTS field.
	USB_OTG_HS_GLPMCFG_SLPSTS_Msk = 0x8000
	// Bit SLPSTS.
	USB_OTG_HS_GLPMCFG_SLPSTS = 0x8000
	// Position of L1RSMOK field.
	USB_OTG_HS_GLPMCFG_L1RSMOK_Pos = 0x10
	// Bit mask of L1RSMOK field.
	USB_OTG_HS_GLPMCFG_L1RSMOK_Msk = 0x10000
	// Bit L1RSMOK.
	USB_OTG_HS_GLPMCFG_L1RSMOK = 0x10000
	// Position of LPMCHIDX field.
	USB_OTG_HS_GLPMCFG_LPMCHIDX_Pos = 0x11
	// Bit mask of LPMCHIDX field.
	USB_OTG_HS_GLPMCFG_LPMCHIDX_Msk = 0x1e0000
	// Position of LPMRCNT field.
	USB_OTG_HS_GLPMCFG_LPMRCNT_Pos = 0x15
	// Bit mask of LPMRCNT field.
	USB_OTG_HS_GLPMCFG_LPMRCNT_Msk = 0xe00000
	// Position of SNDLPM field.
	USB_OTG_HS_GLPMCFG_SNDLPM_Pos = 0x18
	// Bit mask of SNDLPM field.
	USB_OTG_HS_GLPMCFG_SNDLPM_Msk = 0x1000000
	// Bit SNDLPM.
	USB_OTG_HS_GLPMCFG_SNDLPM = 0x1000000
	// Position of LPMRCNTSTS field.
	USB_OTG_HS_GLPMCFG_LPMRCNTSTS_Pos = 0x19
	// Bit mask of LPMRCNTSTS field.
	USB_OTG_HS_GLPMCFG_LPMRCNTSTS_Msk = 0xe000000
	// Position of ENBESL field.
	USB_OTG_HS_GLPMCFG_ENBESL_Pos = 0x1c
	// Bit mask of ENBESL field.
	USB_OTG_HS_GLPMCFG_ENBESL_Msk = 0x10000000
	// Bit ENBESL.
	USB_OTG_HS_GLPMCFG_ENBESL = 0x10000000

	// HPTXFSIZ: OTG_HS Host periodic transmit FIFO size register
	// Position of PTXSA field.
	USB_OTG_HS_HPTXFSIZ_PTXSA_Pos = 0x0
	// Bit mask of PTXSA field.
	USB_OTG_HS_HPTXFSIZ_PTXSA_Msk = 0xffff
	// Position of PTXFD field.
	USB_OTG_HS_HPTXFSIZ_PTXFD_Pos = 0x10
	// Bit mask of PTXFD field.
	USB_OTG_HS_HPTXFSIZ_PTXFD_Msk = 0xffff0000

	// DIEPTXF1: OTG_HS device IN endpoint transmit FIFO size register
	// Position of INEPTXSA field.
	USB_OTG_HS_DIEPTXF1_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	USB_OTG_HS_DIEPTXF1_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	USB_OTG_HS_DIEPTXF1_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	USB_OTG_HS_DIEPTXF1_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF2: OTG_HS device IN endpoint transmit FIFO size register
	// Position of INEPTXSA field.
	USB_OTG_HS_DIEPTXF2_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	USB_OTG_HS_DIEPTXF2_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	USB_OTG_HS_DIEPTXF2_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	USB_OTG_HS_DIEPTXF2_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF3: OTG_HS device IN endpoint transmit FIFO size register
	// Position of INEPTXSA field.
	USB_OTG_HS_DIEPTXF3_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	USB_OTG_HS_DIEPTXF3_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	USB_OTG_HS_DIEPTXF3_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	USB_OTG_HS_DIEPTXF3_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF4: OTG_HS device IN endpoint transmit FIFO size register
	// Position of INEPTXSA field.
	USB_OTG_HS_DIEPTXF4_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	USB_OTG_HS_DIEPTXF4_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	USB_OTG_HS_DIEPTXF4_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	USB_OTG_HS_DIEPTXF4_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF5: OTG_HS device IN endpoint transmit FIFO size register
	// Position of INEPTXSA field.
	USB_OTG_HS_DIEPTXF5_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	USB_OTG_HS_DIEPTXF5_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	USB_OTG_HS_DIEPTXF5_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	USB_OTG_HS_DIEPTXF5_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF6: OTG_HS device IN endpoint transmit FIFO size register
	// Position of INEPTXSA field.
	USB_OTG_HS_DIEPTXF6_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	USB_OTG_HS_DIEPTXF6_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	USB_OTG_HS_DIEPTXF6_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	USB_OTG_HS_DIEPTXF6_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF7: OTG_HS device IN endpoint transmit FIFO size register
	// Position of INEPTXSA field.
	USB_OTG_HS_DIEPTXF7_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	USB_OTG_HS_DIEPTXF7_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	USB_OTG_HS_DIEPTXF7_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	USB_OTG_HS_DIEPTXF7_INEPTXFD_Msk = 0xffff0000
)

// Bitfields for Ethernet_DMA: Ethernet: DMA mode register (DMA)
const (
	// DMAMR: DMA mode register
	// Position of SWR field.
	Ethernet_DMAMR_SWR_Pos = 0x0
	// Bit mask of SWR field.
	Ethernet_DMAMR_SWR_Msk = 0x1
	// Bit SWR.
	Ethernet_DMAMR_SWR = 0x1
	// Position of DA field.
	Ethernet_DMAMR_DA_Pos = 0x1
	// Bit mask of DA field.
	Ethernet_DMAMR_DA_Msk = 0x2
	// Bit DA.
	Ethernet_DMAMR_DA = 0x2
	// Position of TXPR field.
	Ethernet_DMAMR_TXPR_Pos = 0xb
	// Bit mask of TXPR field.
	Ethernet_DMAMR_TXPR_Msk = 0x800
	// Bit TXPR.
	Ethernet_DMAMR_TXPR = 0x800
	// Position of PR field.
	Ethernet_DMAMR_PR_Pos = 0xc
	// Bit mask of PR field.
	Ethernet_DMAMR_PR_Msk = 0x7000
	// Position of INTM field.
	Ethernet_DMAMR_INTM_Pos = 0x10
	// Bit mask of INTM field.
	Ethernet_DMAMR_INTM_Msk = 0x30000

	// DMASBMR: System bus mode register
	// Position of FB field.
	Ethernet_DMASBMR_FB_Pos = 0x0
	// Bit mask of FB field.
	Ethernet_DMASBMR_FB_Msk = 0x1
	// Bit FB.
	Ethernet_DMASBMR_FB = 0x1
	// Position of AAL field.
	Ethernet_DMASBMR_AAL_Pos = 0xc
	// Bit mask of AAL field.
	Ethernet_DMASBMR_AAL_Msk = 0x1000
	// Bit AAL.
	Ethernet_DMASBMR_AAL = 0x1000
	// Position of MB field.
	Ethernet_DMASBMR_MB_Pos = 0xe
	// Bit mask of MB field.
	Ethernet_DMASBMR_MB_Msk = 0x4000
	// Bit MB.
	Ethernet_DMASBMR_MB = 0x4000
	// Position of RB field.
	Ethernet_DMASBMR_RB_Pos = 0xf
	// Bit mask of RB field.
	Ethernet_DMASBMR_RB_Msk = 0x8000
	// Bit RB.
	Ethernet_DMASBMR_RB = 0x8000

	// DMAISR: Interrupt status register
	// Position of DC0IS field.
	Ethernet_DMAISR_DC0IS_Pos = 0x0
	// Bit mask of DC0IS field.
	Ethernet_DMAISR_DC0IS_Msk = 0x1
	// Bit DC0IS.
	Ethernet_DMAISR_DC0IS = 0x1
	// Position of MTLIS field.
	Ethernet_DMAISR_MTLIS_Pos = 0x10
	// Bit mask of MTLIS field.
	Ethernet_DMAISR_MTLIS_Msk = 0x10000
	// Bit MTLIS.
	Ethernet_DMAISR_MTLIS = 0x10000
	// Position of MACIS field.
	Ethernet_DMAISR_MACIS_Pos = 0x11
	// Bit mask of MACIS field.
	Ethernet_DMAISR_MACIS_Msk = 0x20000
	// Bit MACIS.
	Ethernet_DMAISR_MACIS = 0x20000

	// DMADSR: Debug status register
	// Position of AXWHSTS field.
	Ethernet_DMADSR_AXWHSTS_Pos = 0x0
	// Bit mask of AXWHSTS field.
	Ethernet_DMADSR_AXWHSTS_Msk = 0x1
	// Bit AXWHSTS.
	Ethernet_DMADSR_AXWHSTS = 0x1
	// Position of RPS0 field.
	Ethernet_DMADSR_RPS0_Pos = 0x8
	// Bit mask of RPS0 field.
	Ethernet_DMADSR_RPS0_Msk = 0xf00
	// Position of TPS0 field.
	Ethernet_DMADSR_TPS0_Pos = 0xc
	// Bit mask of TPS0 field.
	Ethernet_DMADSR_TPS0_Msk = 0xf000

	// DMACCR: Channel control register
	// Position of MSS field.
	Ethernet_DMACCR_MSS_Pos = 0x0
	// Bit mask of MSS field.
	Ethernet_DMACCR_MSS_Msk = 0x3fff
	// Position of PBLX8 field.
	Ethernet_DMACCR_PBLX8_Pos = 0x10
	// Bit mask of PBLX8 field.
	Ethernet_DMACCR_PBLX8_Msk = 0x10000
	// Bit PBLX8.
	Ethernet_DMACCR_PBLX8 = 0x10000
	// Position of DSL field.
	Ethernet_DMACCR_DSL_Pos = 0x12
	// Bit mask of DSL field.
	Ethernet_DMACCR_DSL_Msk = 0x1c0000

	// DMACTxCR: Channel transmit control register
	// Position of ST field.
	Ethernet_DMACTxCR_ST_Pos = 0x0
	// Bit mask of ST field.
	Ethernet_DMACTxCR_ST_Msk = 0x1
	// Bit ST.
	Ethernet_DMACTxCR_ST = 0x1
	// Position of OSF field.
	Ethernet_DMACTxCR_OSF_Pos = 0x4
	// Bit mask of OSF field.
	Ethernet_DMACTxCR_OSF_Msk = 0x10
	// Bit OSF.
	Ethernet_DMACTxCR_OSF = 0x10
	// Position of TSE field.
	Ethernet_DMACTxCR_TSE_Pos = 0xc
	// Bit mask of TSE field.
	Ethernet_DMACTxCR_TSE_Msk = 0x1000
	// Bit TSE.
	Ethernet_DMACTxCR_TSE = 0x1000
	// Position of TXPBL field.
	Ethernet_DMACTxCR_TXPBL_Pos = 0x10
	// Bit mask of TXPBL field.
	Ethernet_DMACTxCR_TXPBL_Msk = 0x3f0000

	// DMACRxCR: Channel receive control register
	// Position of SR field.
	Ethernet_DMACRxCR_SR_Pos = 0x0
	// Bit mask of SR field.
	Ethernet_DMACRxCR_SR_Msk = 0x1
	// Bit SR.
	Ethernet_DMACRxCR_SR = 0x1
	// Position of RBSZ field.
	Ethernet_DMACRxCR_RBSZ_Pos = 0x1
	// Bit mask of RBSZ field.
	Ethernet_DMACRxCR_RBSZ_Msk = 0x7ffe
	// Position of RXPBL field.
	Ethernet_DMACRxCR_RXPBL_Pos = 0x10
	// Bit mask of RXPBL field.
	Ethernet_DMACRxCR_RXPBL_Msk = 0x3f0000
	// Position of RPF field.
	Ethernet_DMACRxCR_RPF_Pos = 0x1f
	// Bit mask of RPF field.
	Ethernet_DMACRxCR_RPF_Msk = 0x80000000
	// Bit RPF.
	Ethernet_DMACRxCR_RPF = 0x80000000

	// DMACTxDLAR: Channel Tx descriptor list address register
	// Position of TDESLA field.
	Ethernet_DMACTxDLAR_TDESLA_Pos = 0x2
	// Bit mask of TDESLA field.
	Ethernet_DMACTxDLAR_TDESLA_Msk = 0xfffffffc

	// DMACRxDLAR: Channel Rx descriptor list address register
	// Position of RDESLA field.
	Ethernet_DMACRxDLAR_RDESLA_Pos = 0x2
	// Bit mask of RDESLA field.
	Ethernet_DMACRxDLAR_RDESLA_Msk = 0xfffffffc

	// DMACTxDTPR: Channel Tx descriptor tail pointer register
	// Position of TDT field.
	Ethernet_DMACTxDTPR_TDT_Pos = 0x2
	// Bit mask of TDT field.
	Ethernet_DMACTxDTPR_TDT_Msk = 0xfffffffc

	// DMACRxDTPR: Channel Rx descriptor tail pointer register
	// Position of RDT field.
	Ethernet_DMACRxDTPR_RDT_Pos = 0x2
	// Bit mask of RDT field.
	Ethernet_DMACRxDTPR_RDT_Msk = 0xfffffffc

	// DMACTxRLR: Channel Tx descriptor ring length register
	// Position of TDRL field.
	Ethernet_DMACTxRLR_TDRL_Pos = 0x0
	// Bit mask of TDRL field.
	Ethernet_DMACTxRLR_TDRL_Msk = 0x3ff

	// DMACRxRLR: Channel Rx descriptor ring length register
	// Position of RDRL field.
	Ethernet_DMACRxRLR_RDRL_Pos = 0x0
	// Bit mask of RDRL field.
	Ethernet_DMACRxRLR_RDRL_Msk = 0x3ff

	// DMACIER: Channel interrupt enable register
	// Position of TIE field.
	Ethernet_DMACIER_TIE_Pos = 0x0
	// Bit mask of TIE field.
	Ethernet_DMACIER_TIE_Msk = 0x1
	// Bit TIE.
	Ethernet_DMACIER_TIE = 0x1
	// Position of TXSE field.
	Ethernet_DMACIER_TXSE_Pos = 0x1
	// Bit mask of TXSE field.
	Ethernet_DMACIER_TXSE_Msk = 0x2
	// Bit TXSE.
	Ethernet_DMACIER_TXSE = 0x2
	// Position of TBUE field.
	Ethernet_DMACIER_TBUE_Pos = 0x2
	// Bit mask of TBUE field.
	Ethernet_DMACIER_TBUE_Msk = 0x4
	// Bit TBUE.
	Ethernet_DMACIER_TBUE = 0x4
	// Position of RIE field.
	Ethernet_DMACIER_RIE_Pos = 0x6
	// Bit mask of RIE field.
	Ethernet_DMACIER_RIE_Msk = 0x40
	// Bit RIE.
	Ethernet_DMACIER_RIE = 0x40
	// Position of RBUE field.
	Ethernet_DMACIER_RBUE_Pos = 0x7
	// Bit mask of RBUE field.
	Ethernet_DMACIER_RBUE_Msk = 0x80
	// Bit RBUE.
	Ethernet_DMACIER_RBUE = 0x80
	// Position of RSE field.
	Ethernet_DMACIER_RSE_Pos = 0x8
	// Bit mask of RSE field.
	Ethernet_DMACIER_RSE_Msk = 0x100
	// Bit RSE.
	Ethernet_DMACIER_RSE = 0x100
	// Position of RWTE field.
	Ethernet_DMACIER_RWTE_Pos = 0x9
	// Bit mask of RWTE field.
	Ethernet_DMACIER_RWTE_Msk = 0x200
	// Bit RWTE.
	Ethernet_DMACIER_RWTE = 0x200
	// Position of ETIE field.
	Ethernet_DMACIER_ETIE_Pos = 0xa
	// Bit mask of ETIE field.
	Ethernet_DMACIER_ETIE_Msk = 0x400
	// Bit ETIE.
	Ethernet_DMACIER_ETIE = 0x400
	// Position of ERIE field.
	Ethernet_DMACIER_ERIE_Pos = 0xb
	// Bit mask of ERIE field.
	Ethernet_DMACIER_ERIE_Msk = 0x800
	// Bit ERIE.
	Ethernet_DMACIER_ERIE = 0x800
	// Position of FBEE field.
	Ethernet_DMACIER_FBEE_Pos = 0xc
	// Bit mask of FBEE field.
	Ethernet_DMACIER_FBEE_Msk = 0x1000
	// Bit FBEE.
	Ethernet_DMACIER_FBEE = 0x1000
	// Position of CDEE field.
	Ethernet_DMACIER_CDEE_Pos = 0xd
	// Bit mask of CDEE field.
	Ethernet_DMACIER_CDEE_Msk = 0x2000
	// Bit CDEE.
	Ethernet_DMACIER_CDEE = 0x2000
	// Position of AIE field.
	Ethernet_DMACIER_AIE_Pos = 0xe
	// Bit mask of AIE field.
	Ethernet_DMACIER_AIE_Msk = 0x4000
	// Bit AIE.
	Ethernet_DMACIER_AIE = 0x4000
	// Position of NIE field.
	Ethernet_DMACIER_NIE_Pos = 0xf
	// Bit mask of NIE field.
	Ethernet_DMACIER_NIE_Msk = 0x8000
	// Bit NIE.
	Ethernet_DMACIER_NIE = 0x8000

	// DMACRxIWTR: Channel Rx interrupt watchdog timer register
	// Position of RWT field.
	Ethernet_DMACRxIWTR_RWT_Pos = 0x0
	// Bit mask of RWT field.
	Ethernet_DMACRxIWTR_RWT_Msk = 0xff

	// DMACCATxDR: Channel current application transmit descriptor register
	// Position of CURTDESAPTR field.
	Ethernet_DMACCATxDR_CURTDESAPTR_Pos = 0x0
	// Bit mask of CURTDESAPTR field.
	Ethernet_DMACCATxDR_CURTDESAPTR_Msk = 0xffffffff

	// DMACCARxDR: Channel current application receive descriptor register
	// Position of CURRDESAPTR field.
	Ethernet_DMACCARxDR_CURRDESAPTR_Pos = 0x0
	// Bit mask of CURRDESAPTR field.
	Ethernet_DMACCARxDR_CURRDESAPTR_Msk = 0xffffffff

	// DMACCATxBR: Channel current application transmit buffer register
	// Position of CURTBUFAPTR field.
	Ethernet_DMACCATxBR_CURTBUFAPTR_Pos = 0x0
	// Bit mask of CURTBUFAPTR field.
	Ethernet_DMACCATxBR_CURTBUFAPTR_Msk = 0xffffffff

	// DMACCARxBR: Channel current application receive buffer register
	// Position of CURRBUFAPTR field.
	Ethernet_DMACCARxBR_CURRBUFAPTR_Pos = 0x0
	// Bit mask of CURRBUFAPTR field.
	Ethernet_DMACCARxBR_CURRBUFAPTR_Msk = 0xffffffff

	// DMACSR: Channel status register
	// Position of TI field.
	Ethernet_DMACSR_TI_Pos = 0x0
	// Bit mask of TI field.
	Ethernet_DMACSR_TI_Msk = 0x1
	// Bit TI.
	Ethernet_DMACSR_TI = 0x1
	// Position of TPS field.
	Ethernet_DMACSR_TPS_Pos = 0x1
	// Bit mask of TPS field.
	Ethernet_DMACSR_TPS_Msk = 0x2
	// Bit TPS.
	Ethernet_DMACSR_TPS = 0x2
	// Position of TBU field.
	Ethernet_DMACSR_TBU_Pos = 0x2
	// Bit mask of TBU field.
	Ethernet_DMACSR_TBU_Msk = 0x4
	// Bit TBU.
	Ethernet_DMACSR_TBU = 0x4
	// Position of RI field.
	Ethernet_DMACSR_RI_Pos = 0x6
	// Bit mask of RI field.
	Ethernet_DMACSR_RI_Msk = 0x40
	// Bit RI.
	Ethernet_DMACSR_RI = 0x40
	// Position of RBU field.
	Ethernet_DMACSR_RBU_Pos = 0x7
	// Bit mask of RBU field.
	Ethernet_DMACSR_RBU_Msk = 0x80
	// Bit RBU.
	Ethernet_DMACSR_RBU = 0x80
	// Position of RPS field.
	Ethernet_DMACSR_RPS_Pos = 0x8
	// Bit mask of RPS field.
	Ethernet_DMACSR_RPS_Msk = 0x100
	// Bit RPS.
	Ethernet_DMACSR_RPS = 0x100
	// Position of RWT field.
	Ethernet_DMACSR_RWT_Pos = 0x9
	// Bit mask of RWT field.
	Ethernet_DMACSR_RWT_Msk = 0x200
	// Bit RWT.
	Ethernet_DMACSR_RWT = 0x200
	// Position of ET field.
	Ethernet_DMACSR_ET_Pos = 0xa
	// Bit mask of ET field.
	Ethernet_DMACSR_ET_Msk = 0x400
	// Bit ET.
	Ethernet_DMACSR_ET = 0x400
	// Position of ER field.
	Ethernet_DMACSR_ER_Pos = 0xb
	// Bit mask of ER field.
	Ethernet_DMACSR_ER_Msk = 0x800
	// Bit ER.
	Ethernet_DMACSR_ER = 0x800
	// Position of FBE field.
	Ethernet_DMACSR_FBE_Pos = 0xc
	// Bit mask of FBE field.
	Ethernet_DMACSR_FBE_Msk = 0x1000
	// Bit FBE.
	Ethernet_DMACSR_FBE = 0x1000
	// Position of CDE field.
	Ethernet_DMACSR_CDE_Pos = 0xd
	// Bit mask of CDE field.
	Ethernet_DMACSR_CDE_Msk = 0x2000
	// Bit CDE.
	Ethernet_DMACSR_CDE = 0x2000
	// Position of AIS field.
	Ethernet_DMACSR_AIS_Pos = 0xe
	// Bit mask of AIS field.
	Ethernet_DMACSR_AIS_Msk = 0x4000
	// Bit AIS.
	Ethernet_DMACSR_AIS = 0x4000
	// Position of NIS field.
	Ethernet_DMACSR_NIS_Pos = 0xf
	// Bit mask of NIS field.
	Ethernet_DMACSR_NIS_Msk = 0x8000
	// Bit NIS.
	Ethernet_DMACSR_NIS = 0x8000
	// Position of TEB field.
	Ethernet_DMACSR_TEB_Pos = 0x10
	// Bit mask of TEB field.
	Ethernet_DMACSR_TEB_Msk = 0x70000
	// Position of REB field.
	Ethernet_DMACSR_REB_Pos = 0x13
	// Bit mask of REB field.
	Ethernet_DMACSR_REB_Msk = 0x380000

	// DMACMFCR: Channel missed frame count register
	// Position of MFC field.
	Ethernet_DMACMFCR_MFC_Pos = 0x0
	// Bit mask of MFC field.
	Ethernet_DMACMFCR_MFC_Msk = 0x7ff
	// Position of MFCO field.
	Ethernet_DMACMFCR_MFCO_Pos = 0xf
	// Bit mask of MFCO field.
	Ethernet_DMACMFCR_MFCO_Msk = 0x8000
	// Bit MFCO.
	Ethernet_DMACMFCR_MFCO = 0x8000
)

// Bitfields for DMA1: DMA controller
const (
	// LISR: low interrupt status register
	// Position of TCIF3 field.
	DMA_LISR_TCIF3_Pos = 0x1b
	// Bit mask of TCIF3 field.
	DMA_LISR_TCIF3_Msk = 0x8000000
	// Bit TCIF3.
	DMA_LISR_TCIF3 = 0x8000000
	// No transfer complete event on stream x
	DMA_LISR_TCIF3_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_LISR_TCIF3_Complete = 0x1
	// Position of HTIF3 field.
	DMA_LISR_HTIF3_Pos = 0x1a
	// Bit mask of HTIF3 field.
	DMA_LISR_HTIF3_Msk = 0x4000000
	// Bit HTIF3.
	DMA_LISR_HTIF3 = 0x4000000
	// No half transfer event on stream x
	DMA_LISR_HTIF3_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_LISR_HTIF3_Half = 0x1
	// Position of TEIF3 field.
	DMA_LISR_TEIF3_Pos = 0x19
	// Bit mask of TEIF3 field.
	DMA_LISR_TEIF3_Msk = 0x2000000
	// Bit TEIF3.
	DMA_LISR_TEIF3 = 0x2000000
	// No transfer error on stream x
	DMA_LISR_TEIF3_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_LISR_TEIF3_Error = 0x1
	// Position of DMEIF3 field.
	DMA_LISR_DMEIF3_Pos = 0x18
	// Bit mask of DMEIF3 field.
	DMA_LISR_DMEIF3_Msk = 0x1000000
	// Bit DMEIF3.
	DMA_LISR_DMEIF3 = 0x1000000
	// No Direct Mode error on stream x
	DMA_LISR_DMEIF3_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_LISR_DMEIF3_Error = 0x1
	// Position of FEIF3 field.
	DMA_LISR_FEIF3_Pos = 0x16
	// Bit mask of FEIF3 field.
	DMA_LISR_FEIF3_Msk = 0x400000
	// Bit FEIF3.
	DMA_LISR_FEIF3 = 0x400000
	// No FIFO error event on stream x
	DMA_LISR_FEIF3_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_LISR_FEIF3_Error = 0x1
	// Position of TCIF2 field.
	DMA_LISR_TCIF2_Pos = 0x15
	// Bit mask of TCIF2 field.
	DMA_LISR_TCIF2_Msk = 0x200000
	// Bit TCIF2.
	DMA_LISR_TCIF2 = 0x200000
	// No transfer complete event on stream x
	DMA_LISR_TCIF2_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_LISR_TCIF2_Complete = 0x1
	// Position of HTIF2 field.
	DMA_LISR_HTIF2_Pos = 0x14
	// Bit mask of HTIF2 field.
	DMA_LISR_HTIF2_Msk = 0x100000
	// Bit HTIF2.
	DMA_LISR_HTIF2 = 0x100000
	// No half transfer event on stream x
	DMA_LISR_HTIF2_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_LISR_HTIF2_Half = 0x1
	// Position of TEIF2 field.
	DMA_LISR_TEIF2_Pos = 0x13
	// Bit mask of TEIF2 field.
	DMA_LISR_TEIF2_Msk = 0x80000
	// Bit TEIF2.
	DMA_LISR_TEIF2 = 0x80000
	// No transfer error on stream x
	DMA_LISR_TEIF2_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_LISR_TEIF2_Error = 0x1
	// Position of DMEIF2 field.
	DMA_LISR_DMEIF2_Pos = 0x12
	// Bit mask of DMEIF2 field.
	DMA_LISR_DMEIF2_Msk = 0x40000
	// Bit DMEIF2.
	DMA_LISR_DMEIF2 = 0x40000
	// No Direct Mode error on stream x
	DMA_LISR_DMEIF2_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_LISR_DMEIF2_Error = 0x1
	// Position of FEIF2 field.
	DMA_LISR_FEIF2_Pos = 0x10
	// Bit mask of FEIF2 field.
	DMA_LISR_FEIF2_Msk = 0x10000
	// Bit FEIF2.
	DMA_LISR_FEIF2 = 0x10000
	// No FIFO error event on stream x
	DMA_LISR_FEIF2_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_LISR_FEIF2_Error = 0x1
	// Position of TCIF1 field.
	DMA_LISR_TCIF1_Pos = 0xb
	// Bit mask of TCIF1 field.
	DMA_LISR_TCIF1_Msk = 0x800
	// Bit TCIF1.
	DMA_LISR_TCIF1 = 0x800
	// No transfer complete event on stream x
	DMA_LISR_TCIF1_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_LISR_TCIF1_Complete = 0x1
	// Position of HTIF1 field.
	DMA_LISR_HTIF1_Pos = 0xa
	// Bit mask of HTIF1 field.
	DMA_LISR_HTIF1_Msk = 0x400
	// Bit HTIF1.
	DMA_LISR_HTIF1 = 0x400
	// No half transfer event on stream x
	DMA_LISR_HTIF1_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_LISR_HTIF1_Half = 0x1
	// Position of TEIF1 field.
	DMA_LISR_TEIF1_Pos = 0x9
	// Bit mask of TEIF1 field.
	DMA_LISR_TEIF1_Msk = 0x200
	// Bit TEIF1.
	DMA_LISR_TEIF1 = 0x200
	// No transfer error on stream x
	DMA_LISR_TEIF1_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_LISR_TEIF1_Error = 0x1
	// Position of DMEIF1 field.
	DMA_LISR_DMEIF1_Pos = 0x8
	// Bit mask of DMEIF1 field.
	DMA_LISR_DMEIF1_Msk = 0x100
	// Bit DMEIF1.
	DMA_LISR_DMEIF1 = 0x100
	// No Direct Mode error on stream x
	DMA_LISR_DMEIF1_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_LISR_DMEIF1_Error = 0x1
	// Position of FEIF1 field.
	DMA_LISR_FEIF1_Pos = 0x6
	// Bit mask of FEIF1 field.
	DMA_LISR_FEIF1_Msk = 0x40
	// Bit FEIF1.
	DMA_LISR_FEIF1 = 0x40
	// No FIFO error event on stream x
	DMA_LISR_FEIF1_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_LISR_FEIF1_Error = 0x1
	// Position of TCIF0 field.
	DMA_LISR_TCIF0_Pos = 0x5
	// Bit mask of TCIF0 field.
	DMA_LISR_TCIF0_Msk = 0x20
	// Bit TCIF0.
	DMA_LISR_TCIF0 = 0x20
	// No transfer complete event on stream x
	DMA_LISR_TCIF0_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_LISR_TCIF0_Complete = 0x1
	// Position of HTIF0 field.
	DMA_LISR_HTIF0_Pos = 0x4
	// Bit mask of HTIF0 field.
	DMA_LISR_HTIF0_Msk = 0x10
	// Bit HTIF0.
	DMA_LISR_HTIF0 = 0x10
	// No half transfer event on stream x
	DMA_LISR_HTIF0_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_LISR_HTIF0_Half = 0x1
	// Position of TEIF0 field.
	DMA_LISR_TEIF0_Pos = 0x3
	// Bit mask of TEIF0 field.
	DMA_LISR_TEIF0_Msk = 0x8
	// Bit TEIF0.
	DMA_LISR_TEIF0 = 0x8
	// No transfer error on stream x
	DMA_LISR_TEIF0_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_LISR_TEIF0_Error = 0x1
	// Position of DMEIF0 field.
	DMA_LISR_DMEIF0_Pos = 0x2
	// Bit mask of DMEIF0 field.
	DMA_LISR_DMEIF0_Msk = 0x4
	// Bit DMEIF0.
	DMA_LISR_DMEIF0 = 0x4
	// No Direct Mode error on stream x
	DMA_LISR_DMEIF0_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_LISR_DMEIF0_Error = 0x1
	// Position of FEIF0 field.
	DMA_LISR_FEIF0_Pos = 0x0
	// Bit mask of FEIF0 field.
	DMA_LISR_FEIF0_Msk = 0x1
	// Bit FEIF0.
	DMA_LISR_FEIF0 = 0x1
	// No FIFO error event on stream x
	DMA_LISR_FEIF0_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_LISR_FEIF0_Error = 0x1

	// HISR: high interrupt status register
	// Position of TCIF7 field.
	DMA_HISR_TCIF7_Pos = 0x1b
	// Bit mask of TCIF7 field.
	DMA_HISR_TCIF7_Msk = 0x8000000
	// Bit TCIF7.
	DMA_HISR_TCIF7 = 0x8000000
	// No transfer complete event on stream x
	DMA_HISR_TCIF7_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_HISR_TCIF7_Complete = 0x1
	// Position of HTIF7 field.
	DMA_HISR_HTIF7_Pos = 0x1a
	// Bit mask of HTIF7 field.
	DMA_HISR_HTIF7_Msk = 0x4000000
	// Bit HTIF7.
	DMA_HISR_HTIF7 = 0x4000000
	// No half transfer event on stream x
	DMA_HISR_HTIF7_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_HISR_HTIF7_Half = 0x1
	// Position of TEIF7 field.
	DMA_HISR_TEIF7_Pos = 0x19
	// Bit mask of TEIF7 field.
	DMA_HISR_TEIF7_Msk = 0x2000000
	// Bit TEIF7.
	DMA_HISR_TEIF7 = 0x2000000
	// No transfer error on stream x
	DMA_HISR_TEIF7_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_HISR_TEIF7_Error = 0x1
	// Position of DMEIF7 field.
	DMA_HISR_DMEIF7_Pos = 0x18
	// Bit mask of DMEIF7 field.
	DMA_HISR_DMEIF7_Msk = 0x1000000
	// Bit DMEIF7.
	DMA_HISR_DMEIF7 = 0x1000000
	// No Direct Mode error on stream x
	DMA_HISR_DMEIF7_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_HISR_DMEIF7_Error = 0x1
	// Position of FEIF7 field.
	DMA_HISR_FEIF7_Pos = 0x16
	// Bit mask of FEIF7 field.
	DMA_HISR_FEIF7_Msk = 0x400000
	// Bit FEIF7.
	DMA_HISR_FEIF7 = 0x400000
	// No FIFO error event on stream x
	DMA_HISR_FEIF7_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_HISR_FEIF7_Error = 0x1
	// Position of TCIF6 field.
	DMA_HISR_TCIF6_Pos = 0x15
	// Bit mask of TCIF6 field.
	DMA_HISR_TCIF6_Msk = 0x200000
	// Bit TCIF6.
	DMA_HISR_TCIF6 = 0x200000
	// No transfer complete event on stream x
	DMA_HISR_TCIF6_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_HISR_TCIF6_Complete = 0x1
	// Position of HTIF6 field.
	DMA_HISR_HTIF6_Pos = 0x14
	// Bit mask of HTIF6 field.
	DMA_HISR_HTIF6_Msk = 0x100000
	// Bit HTIF6.
	DMA_HISR_HTIF6 = 0x100000
	// No half transfer event on stream x
	DMA_HISR_HTIF6_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_HISR_HTIF6_Half = 0x1
	// Position of TEIF6 field.
	DMA_HISR_TEIF6_Pos = 0x13
	// Bit mask of TEIF6 field.
	DMA_HISR_TEIF6_Msk = 0x80000
	// Bit TEIF6.
	DMA_HISR_TEIF6 = 0x80000
	// No transfer error on stream x
	DMA_HISR_TEIF6_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_HISR_TEIF6_Error = 0x1
	// Position of DMEIF6 field.
	DMA_HISR_DMEIF6_Pos = 0x12
	// Bit mask of DMEIF6 field.
	DMA_HISR_DMEIF6_Msk = 0x40000
	// Bit DMEIF6.
	DMA_HISR_DMEIF6 = 0x40000
	// No Direct Mode error on stream x
	DMA_HISR_DMEIF6_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_HISR_DMEIF6_Error = 0x1
	// Position of FEIF6 field.
	DMA_HISR_FEIF6_Pos = 0x10
	// Bit mask of FEIF6 field.
	DMA_HISR_FEIF6_Msk = 0x10000
	// Bit FEIF6.
	DMA_HISR_FEIF6 = 0x10000
	// No FIFO error event on stream x
	DMA_HISR_FEIF6_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_HISR_FEIF6_Error = 0x1
	// Position of TCIF5 field.
	DMA_HISR_TCIF5_Pos = 0xb
	// Bit mask of TCIF5 field.
	DMA_HISR_TCIF5_Msk = 0x800
	// Bit TCIF5.
	DMA_HISR_TCIF5 = 0x800
	// No transfer complete event on stream x
	DMA_HISR_TCIF5_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_HISR_TCIF5_Complete = 0x1
	// Position of HTIF5 field.
	DMA_HISR_HTIF5_Pos = 0xa
	// Bit mask of HTIF5 field.
	DMA_HISR_HTIF5_Msk = 0x400
	// Bit HTIF5.
	DMA_HISR_HTIF5 = 0x400
	// No half transfer event on stream x
	DMA_HISR_HTIF5_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_HISR_HTIF5_Half = 0x1
	// Position of TEIF5 field.
	DMA_HISR_TEIF5_Pos = 0x9
	// Bit mask of TEIF5 field.
	DMA_HISR_TEIF5_Msk = 0x200
	// Bit TEIF5.
	DMA_HISR_TEIF5 = 0x200
	// No transfer error on stream x
	DMA_HISR_TEIF5_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_HISR_TEIF5_Error = 0x1
	// Position of DMEIF5 field.
	DMA_HISR_DMEIF5_Pos = 0x8
	// Bit mask of DMEIF5 field.
	DMA_HISR_DMEIF5_Msk = 0x100
	// Bit DMEIF5.
	DMA_HISR_DMEIF5 = 0x100
	// No Direct Mode error on stream x
	DMA_HISR_DMEIF5_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_HISR_DMEIF5_Error = 0x1
	// Position of FEIF5 field.
	DMA_HISR_FEIF5_Pos = 0x6
	// Bit mask of FEIF5 field.
	DMA_HISR_FEIF5_Msk = 0x40
	// Bit FEIF5.
	DMA_HISR_FEIF5 = 0x40
	// No FIFO error event on stream x
	DMA_HISR_FEIF5_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_HISR_FEIF5_Error = 0x1
	// Position of TCIF4 field.
	DMA_HISR_TCIF4_Pos = 0x5
	// Bit mask of TCIF4 field.
	DMA_HISR_TCIF4_Msk = 0x20
	// Bit TCIF4.
	DMA_HISR_TCIF4 = 0x20
	// No transfer complete event on stream x
	DMA_HISR_TCIF4_NotComplete = 0x0
	// A transfer complete event occurred on stream x
	DMA_HISR_TCIF4_Complete = 0x1
	// Position of HTIF4 field.
	DMA_HISR_HTIF4_Pos = 0x4
	// Bit mask of HTIF4 field.
	DMA_HISR_HTIF4_Msk = 0x10
	// Bit HTIF4.
	DMA_HISR_HTIF4 = 0x10
	// No half transfer event on stream x
	DMA_HISR_HTIF4_NotHalf = 0x0
	// A half transfer event occurred on stream x
	DMA_HISR_HTIF4_Half = 0x1
	// Position of TEIF4 field.
	DMA_HISR_TEIF4_Pos = 0x3
	// Bit mask of TEIF4 field.
	DMA_HISR_TEIF4_Msk = 0x8
	// Bit TEIF4.
	DMA_HISR_TEIF4 = 0x8
	// No transfer error on stream x
	DMA_HISR_TEIF4_NoError = 0x0
	// A transfer error occurred on stream x
	DMA_HISR_TEIF4_Error = 0x1
	// Position of DMEIF4 field.
	DMA_HISR_DMEIF4_Pos = 0x2
	// Bit mask of DMEIF4 field.
	DMA_HISR_DMEIF4_Msk = 0x4
	// Bit DMEIF4.
	DMA_HISR_DMEIF4 = 0x4
	// No Direct Mode error on stream x
	DMA_HISR_DMEIF4_NoError = 0x0
	// A Direct Mode error occurred on stream x
	DMA_HISR_DMEIF4_Error = 0x1
	// Position of FEIF4 field.
	DMA_HISR_FEIF4_Pos = 0x0
	// Bit mask of FEIF4 field.
	DMA_HISR_FEIF4_Msk = 0x1
	// Bit FEIF4.
	DMA_HISR_FEIF4 = 0x1
	// No FIFO error event on stream x
	DMA_HISR_FEIF4_NoError = 0x0
	// A FIFO error event occurred on stream x
	DMA_HISR_FEIF4_Error = 0x1

	// LIFCR: low interrupt flag clear register
	// Position of CTCIF3 field.
	DMA_LIFCR_CTCIF3_Pos = 0x1b
	// Bit mask of CTCIF3 field.
	DMA_LIFCR_CTCIF3_Msk = 0x8000000
	// Bit CTCIF3.
	DMA_LIFCR_CTCIF3 = 0x8000000
	// Clear the corresponding TCIFx flag
	DMA_LIFCR_CTCIF3_Clear = 0x1
	// Position of CHTIF3 field.
	DMA_LIFCR_CHTIF3_Pos = 0x1a
	// Bit mask of CHTIF3 field.
	DMA_LIFCR_CHTIF3_Msk = 0x4000000
	// Bit CHTIF3.
	DMA_LIFCR_CHTIF3 = 0x4000000
	// Clear the corresponding HTIFx flag
	DMA_LIFCR_CHTIF3_Clear = 0x1
	// Position of CTEIF3 field.
	DMA_LIFCR_CTEIF3_Pos = 0x19
	// Bit mask of CTEIF3 field.
	DMA_LIFCR_CTEIF3_Msk = 0x2000000
	// Bit CTEIF3.
	DMA_LIFCR_CTEIF3 = 0x2000000
	// Clear the corresponding TEIFx flag
	DMA_LIFCR_CTEIF3_Clear = 0x1
	// Position of CDMEIF3 field.
	DMA_LIFCR_CDMEIF3_Pos = 0x18
	// Bit mask of CDMEIF3 field.
	DMA_LIFCR_CDMEIF3_Msk = 0x1000000
	// Bit CDMEIF3.
	DMA_LIFCR_CDMEIF3 = 0x1000000
	// Clear the corresponding DMEIFx flag
	DMA_LIFCR_CDMEIF3_Clear = 0x1
	// Position of CFEIF3 field.
	DMA_LIFCR_CFEIF3_Pos = 0x16
	// Bit mask of CFEIF3 field.
	DMA_LIFCR_CFEIF3_Msk = 0x400000
	// Bit CFEIF3.
	DMA_LIFCR_CFEIF3 = 0x400000
	// Clear the corresponding CFEIFx flag
	DMA_LIFCR_CFEIF3_Clear = 0x1
	// Position of CTCIF2 field.
	DMA_LIFCR_CTCIF2_Pos = 0x15
	// Bit mask of CTCIF2 field.
	DMA_LIFCR_CTCIF2_Msk = 0x200000
	// Bit CTCIF2.
	DMA_LIFCR_CTCIF2 = 0x200000
	// Clear the corresponding TCIFx flag
	DMA_LIFCR_CTCIF2_Clear = 0x1
	// Position of CHTIF2 field.
	DMA_LIFCR_CHTIF2_Pos = 0x14
	// Bit mask of CHTIF2 field.
	DMA_LIFCR_CHTIF2_Msk = 0x100000
	// Bit CHTIF2.
	DMA_LIFCR_CHTIF2 = 0x100000
	// Clear the corresponding HTIFx flag
	DMA_LIFCR_CHTIF2_Clear = 0x1
	// Position of CTEIF2 field.
	DMA_LIFCR_CTEIF2_Pos = 0x13
	// Bit mask of CTEIF2 field.
	DMA_LIFCR_CTEIF2_Msk = 0x80000
	// Bit CTEIF2.
	DMA_LIFCR_CTEIF2 = 0x80000
	// Clear the corresponding TEIFx flag
	DMA_LIFCR_CTEIF2_Clear = 0x1
	// Position of CDMEIF2 field.
	DMA_LIFCR_CDMEIF2_Pos = 0x12
	// Bit mask of CDMEIF2 field.
	DMA_LIFCR_CDMEIF2_Msk = 0x40000
	// Bit CDMEIF2.
	DMA_LIFCR_CDMEIF2 = 0x40000
	// Clear the corresponding DMEIFx flag
	DMA_LIFCR_CDMEIF2_Clear = 0x1
	// Position of CFEIF2 field.
	DMA_LIFCR_CFEIF2_Pos = 0x10
	// Bit mask of CFEIF2 field.
	DMA_LIFCR_CFEIF2_Msk = 0x10000
	// Bit CFEIF2.
	DMA_LIFCR_CFEIF2 = 0x10000
	// Clear the corresponding CFEIFx flag
	DMA_LIFCR_CFEIF2_Clear = 0x1
	// Position of CTCIF1 field.
	DMA_LIFCR_CTCIF1_Pos = 0xb
	// Bit mask of CTCIF1 field.
	DMA_LIFCR_CTCIF1_Msk = 0x800
	// Bit CTCIF1.
	DMA_LIFCR_CTCIF1 = 0x800
	// Clear the corresponding TCIFx flag
	DMA_LIFCR_CTCIF1_Clear = 0x1
	// Position of CHTIF1 field.
	DMA_LIFCR_CHTIF1_Pos = 0xa
	// Bit mask of CHTIF1 field.
	DMA_LIFCR_CHTIF1_Msk = 0x400
	// Bit CHTIF1.
	DMA_LIFCR_CHTIF1 = 0x400
	// Clear the corresponding HTIFx flag
	DMA_LIFCR_CHTIF1_Clear = 0x1
	// Position of CTEIF1 field.
	DMA_LIFCR_CTEIF1_Pos = 0x9
	// Bit mask of CTEIF1 field.
	DMA_LIFCR_CTEIF1_Msk = 0x200
	// Bit CTEIF1.
	DMA_LIFCR_CTEIF1 = 0x200
	// Clear the corresponding TEIFx flag
	DMA_LIFCR_CTEIF1_Clear = 0x1
	// Position of CDMEIF1 field.
	DMA_LIFCR_CDMEIF1_Pos = 0x8
	// Bit mask of CDMEIF1 field.
	DMA_LIFCR_CDMEIF1_Msk = 0x100
	// Bit CDMEIF1.
	DMA_LIFCR_CDMEIF1 = 0x100
	// Clear the corresponding DMEIFx flag
	DMA_LIFCR_CDMEIF1_Clear = 0x1
	// Position of CFEIF1 field.
	DMA_LIFCR_CFEIF1_Pos = 0x6
	// Bit mask of CFEIF1 field.
	DMA_LIFCR_CFEIF1_Msk = 0x40
	// Bit CFEIF1.
	DMA_LIFCR_CFEIF1 = 0x40
	// Clear the corresponding CFEIFx flag
	DMA_LIFCR_CFEIF1_Clear = 0x1
	// Position of CTCIF0 field.
	DMA_LIFCR_CTCIF0_Pos = 0x5
	// Bit mask of CTCIF0 field.
	DMA_LIFCR_CTCIF0_Msk = 0x20
	// Bit CTCIF0.
	DMA_LIFCR_CTCIF0 = 0x20
	// Clear the corresponding TCIFx flag
	DMA_LIFCR_CTCIF0_Clear = 0x1
	// Position of CHTIF0 field.
	DMA_LIFCR_CHTIF0_Pos = 0x4
	// Bit mask of CHTIF0 field.
	DMA_LIFCR_CHTIF0_Msk = 0x10
	// Bit CHTIF0.
	DMA_LIFCR_CHTIF0 = 0x10
	// Clear the corresponding HTIFx flag
	DMA_LIFCR_CHTIF0_Clear = 0x1
	// Position of CTEIF0 field.
	DMA_LIFCR_CTEIF0_Pos = 0x3
	// Bit mask of CTEIF0 field.
	DMA_LIFCR_CTEIF0_Msk = 0x8
	// Bit CTEIF0.
	DMA_LIFCR_CTEIF0 = 0x8
	// Clear the corresponding TEIFx flag
	DMA_LIFCR_CTEIF0_Clear = 0x1
	// Position of CDMEIF0 field.
	DMA_LIFCR_CDMEIF0_Pos = 0x2
	// Bit mask of CDMEIF0 field.
	DMA_LIFCR_CDMEIF0_Msk = 0x4
	// Bit CDMEIF0.
	DMA_LIFCR_CDMEIF0 = 0x4
	// Clear the corresponding DMEIFx flag
	DMA_LIFCR_CDMEIF0_Clear = 0x1
	// Position of CFEIF0 field.
	DMA_LIFCR_CFEIF0_Pos = 0x0
	// Bit mask of CFEIF0 field.
	DMA_LIFCR_CFEIF0_Msk = 0x1
	// Bit CFEIF0.
	DMA_LIFCR_CFEIF0 = 0x1
	// Clear the corresponding CFEIFx flag
	DMA_LIFCR_CFEIF0_Clear = 0x1
	// Position of TRBUFF field.
	DMA_LIFCR_TRBUFF_Pos = 0x14
	// Bit mask of TRBUFF field.
	DMA_LIFCR_TRBUFF_Msk = 0x100000
	// Bit TRBUFF.
	DMA_LIFCR_TRBUFF = 0x100000
	// Bufferable transfers not enabled
	DMA_LIFCR_TRBUFF_Disabled = 0x0
	// Bufferable transfers enabled
	DMA_LIFCR_TRBUFF_Enabled = 0x1

	// HIFCR: high interrupt flag clear register
	// Position of CTCIF7 field.
	DMA_HIFCR_CTCIF7_Pos = 0x1b
	// Bit mask of CTCIF7 field.
	DMA_HIFCR_CTCIF7_Msk = 0x8000000
	// Bit CTCIF7.
	DMA_HIFCR_CTCIF7 = 0x8000000
	// Clear the corresponding TCIFx flag
	DMA_HIFCR_CTCIF7_Clear = 0x1
	// Position of CHTIF7 field.
	DMA_HIFCR_CHTIF7_Pos = 0x1a
	// Bit mask of CHTIF7 field.
	DMA_HIFCR_CHTIF7_Msk = 0x4000000
	// Bit CHTIF7.
	DMA_HIFCR_CHTIF7 = 0x4000000
	// Clear the corresponding HTIFx flag
	DMA_HIFCR_CHTIF7_Clear = 0x1
	// Position of CTEIF7 field.
	DMA_HIFCR_CTEIF7_Pos = 0x19
	// Bit mask of CTEIF7 field.
	DMA_HIFCR_CTEIF7_Msk = 0x2000000
	// Bit CTEIF7.
	DMA_HIFCR_CTEIF7 = 0x2000000
	// Clear the corresponding TEIFx flag
	DMA_HIFCR_CTEIF7_Clear = 0x1
	// Position of CDMEIF7 field.
	DMA_HIFCR_CDMEIF7_Pos = 0x18
	// Bit mask of CDMEIF7 field.
	DMA_HIFCR_CDMEIF7_Msk = 0x1000000
	// Bit CDMEIF7.
	DMA_HIFCR_CDMEIF7 = 0x1000000
	// Clear the corresponding DMEIFx flag
	DMA_HIFCR_CDMEIF7_Clear = 0x1
	// Position of CFEIF7 field.
	DMA_HIFCR_CFEIF7_Pos = 0x16
	// Bit mask of CFEIF7 field.
	DMA_HIFCR_CFEIF7_Msk = 0x400000
	// Bit CFEIF7.
	DMA_HIFCR_CFEIF7 = 0x400000
	// Clear the corresponding CFEIFx flag
	DMA_HIFCR_CFEIF7_Clear = 0x1
	// Position of CTCIF6 field.
	DMA_HIFCR_CTCIF6_Pos = 0x15
	// Bit mask of CTCIF6 field.
	DMA_HIFCR_CTCIF6_Msk = 0x200000
	// Bit CTCIF6.
	DMA_HIFCR_CTCIF6 = 0x200000
	// Clear the corresponding TCIFx flag
	DMA_HIFCR_CTCIF6_Clear = 0x1
	// Position of CHTIF6 field.
	DMA_HIFCR_CHTIF6_Pos = 0x14
	// Bit mask of CHTIF6 field.
	DMA_HIFCR_CHTIF6_Msk = 0x100000
	// Bit CHTIF6.
	DMA_HIFCR_CHTIF6 = 0x100000
	// Clear the corresponding HTIFx flag
	DMA_HIFCR_CHTIF6_Clear = 0x1
	// Position of CTEIF6 field.
	DMA_HIFCR_CTEIF6_Pos = 0x13
	// Bit mask of CTEIF6 field.
	DMA_HIFCR_CTEIF6_Msk = 0x80000
	// Bit CTEIF6.
	DMA_HIFCR_CTEIF6 = 0x80000
	// Clear the corresponding TEIFx flag
	DMA_HIFCR_CTEIF6_Clear = 0x1
	// Position of CDMEIF6 field.
	DMA_HIFCR_CDMEIF6_Pos = 0x12
	// Bit mask of CDMEIF6 field.
	DMA_HIFCR_CDMEIF6_Msk = 0x40000
	// Bit CDMEIF6.
	DMA_HIFCR_CDMEIF6 = 0x40000
	// Clear the corresponding DMEIFx flag
	DMA_HIFCR_CDMEIF6_Clear = 0x1
	// Position of CFEIF6 field.
	DMA_HIFCR_CFEIF6_Pos = 0x10
	// Bit mask of CFEIF6 field.
	DMA_HIFCR_CFEIF6_Msk = 0x10000
	// Bit CFEIF6.
	DMA_HIFCR_CFEIF6 = 0x10000
	// Clear the corresponding CFEIFx flag
	DMA_HIFCR_CFEIF6_Clear = 0x1
	// Position of CTCIF5 field.
	DMA_HIFCR_CTCIF5_Pos = 0xb
	// Bit mask of CTCIF5 field.
	DMA_HIFCR_CTCIF5_Msk = 0x800
	// Bit CTCIF5.
	DMA_HIFCR_CTCIF5 = 0x800
	// Clear the corresponding TCIFx flag
	DMA_HIFCR_CTCIF5_Clear = 0x1
	// Position of CHTIF5 field.
	DMA_HIFCR_CHTIF5_Pos = 0xa
	// Bit mask of CHTIF5 field.
	DMA_HIFCR_CHTIF5_Msk = 0x400
	// Bit CHTIF5.
	DMA_HIFCR_CHTIF5 = 0x400
	// Clear the corresponding HTIFx flag
	DMA_HIFCR_CHTIF5_Clear = 0x1
	// Position of CTEIF5 field.
	DMA_HIFCR_CTEIF5_Pos = 0x9
	// Bit mask of CTEIF5 field.
	DMA_HIFCR_CTEIF5_Msk = 0x200
	// Bit CTEIF5.
	DMA_HIFCR_CTEIF5 = 0x200
	// Clear the corresponding TEIFx flag
	DMA_HIFCR_CTEIF5_Clear = 0x1
	// Position of CDMEIF5 field.
	DMA_HIFCR_CDMEIF5_Pos = 0x8
	// Bit mask of CDMEIF5 field.
	DMA_HIFCR_CDMEIF5_Msk = 0x100
	// Bit CDMEIF5.
	DMA_HIFCR_CDMEIF5 = 0x100
	// Clear the corresponding DMEIFx flag
	DMA_HIFCR_CDMEIF5_Clear = 0x1
	// Position of CFEIF5 field.
	DMA_HIFCR_CFEIF5_Pos = 0x6
	// Bit mask of CFEIF5 field.
	DMA_HIFCR_CFEIF5_Msk = 0x40
	// Bit CFEIF5.
	DMA_HIFCR_CFEIF5 = 0x40
	// Clear the corresponding CFEIFx flag
	DMA_HIFCR_CFEIF5_Clear = 0x1
	// Position of CTCIF4 field.
	DMA_HIFCR_CTCIF4_Pos = 0x5
	// Bit mask of CTCIF4 field.
	DMA_HIFCR_CTCIF4_Msk = 0x20
	// Bit CTCIF4.
	DMA_HIFCR_CTCIF4 = 0x20
	// Clear the corresponding TCIFx flag
	DMA_HIFCR_CTCIF4_Clear = 0x1
	// Position of CHTIF4 field.
	DMA_HIFCR_CHTIF4_Pos = 0x4
	// Bit mask of CHTIF4 field.
	DMA_HIFCR_CHTIF4_Msk = 0x10
	// Bit CHTIF4.
	DMA_HIFCR_CHTIF4 = 0x10
	// Clear the corresponding HTIFx flag
	DMA_HIFCR_CHTIF4_Clear = 0x1
	// Position of CTEIF4 field.
	DMA_HIFCR_CTEIF4_Pos = 0x3
	// Bit mask of CTEIF4 field.
	DMA_HIFCR_CTEIF4_Msk = 0x8
	// Bit CTEIF4.
	DMA_HIFCR_CTEIF4 = 0x8
	// Clear the corresponding TEIFx flag
	DMA_HIFCR_CTEIF4_Clear = 0x1
	// Position of CDMEIF4 field.
	DMA_HIFCR_CDMEIF4_Pos = 0x2
	// Bit mask of CDMEIF4 field.
	DMA_HIFCR_CDMEIF4_Msk = 0x4
	// Bit CDMEIF4.
	DMA_HIFCR_CDMEIF4 = 0x4
	// Clear the corresponding DMEIFx flag
	DMA_HIFCR_CDMEIF4_Clear = 0x1
	// Position of CFEIF4 field.
	DMA_HIFCR_CFEIF4_Pos = 0x0
	// Bit mask of CFEIF4 field.
	DMA_HIFCR_CFEIF4_Msk = 0x1
	// Bit CFEIF4.
	DMA_HIFCR_CFEIF4 = 0x1
	// Clear the corresponding CFEIFx flag
	DMA_HIFCR_CFEIF4_Clear = 0x1
	// Position of TRBUFF field.
	DMA_HIFCR_TRBUFF_Pos = 0x14
	// Bit mask of TRBUFF field.
	DMA_HIFCR_TRBUFF_Msk = 0x100000
	// Bit TRBUFF.
	DMA_HIFCR_TRBUFF = 0x100000
	// Bufferable transfers not enabled
	DMA_HIFCR_TRBUFF_Disabled = 0x0
	// Bufferable transfers enabled
	DMA_HIFCR_TRBUFF_Enabled = 0x1

	// ST.CR: stream x configuration register
	// Position of MBURST field.
	DMA_ST_CR_MBURST_Pos = 0x17
	// Bit mask of MBURST field.
	DMA_ST_CR_MBURST_Msk = 0x1800000
	// Single transfer
	DMA_ST_CR_MBURST_Single = 0x0
	// Incremental burst of 4 beats
	DMA_ST_CR_MBURST_INCR4 = 0x1
	// Incremental burst of 8 beats
	DMA_ST_CR_MBURST_INCR8 = 0x2
	// Incremental burst of 16 beats
	DMA_ST_CR_MBURST_INCR16 = 0x3
	// Position of PBURST field.
	DMA_ST_CR_PBURST_Pos = 0x15
	// Bit mask of PBURST field.
	DMA_ST_CR_PBURST_Msk = 0x600000
	// Single transfer
	DMA_ST_CR_PBURST_Single = 0x0
	// Incremental burst of 4 beats
	DMA_ST_CR_PBURST_INCR4 = 0x1
	// Incremental burst of 8 beats
	DMA_ST_CR_PBURST_INCR8 = 0x2
	// Incremental burst of 16 beats
	DMA_ST_CR_PBURST_INCR16 = 0x3
	// Position of CT field.
	DMA_ST_CR_CT_Pos = 0x13
	// Bit mask of CT field.
	DMA_ST_CR_CT_Msk = 0x80000
	// Bit CT.
	DMA_ST_CR_CT = 0x80000
	// The current target memory is Memory 0
	DMA_ST_CR_CT_Memory0 = 0x0
	// The current target memory is Memory 1
	DMA_ST_CR_CT_Memory1 = 0x1
	// Position of DBM field.
	DMA_ST_CR_DBM_Pos = 0x12
	// Bit mask of DBM field.
	DMA_ST_CR_DBM_Msk = 0x40000
	// Bit DBM.
	DMA_ST_CR_DBM = 0x40000
	// No buffer switching at the end of transfer
	DMA_ST_CR_DBM_Disabled = 0x0
	// Memory target switched at the end of the DMA transfer
	DMA_ST_CR_DBM_Enabled = 0x1
	// Position of PL field.
	DMA_ST_CR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA_ST_CR_PL_Msk = 0x30000
	// Low
	DMA_ST_CR_PL_Low = 0x0
	// Medium
	DMA_ST_CR_PL_Medium = 0x1
	// High
	DMA_ST_CR_PL_High = 0x2
	// Very high
	DMA_ST_CR_PL_VeryHigh = 0x3
	// Position of PINCOS field.
	DMA_ST_CR_PINCOS_Pos = 0xf
	// Bit mask of PINCOS field.
	DMA_ST_CR_PINCOS_Msk = 0x8000
	// Bit PINCOS.
	DMA_ST_CR_PINCOS = 0x8000
	// The offset size for the peripheral address calculation is linked to the PSIZE
	DMA_ST_CR_PINCOS_PSIZE = 0x0
	// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
	DMA_ST_CR_PINCOS_Fixed4 = 0x1
	// Position of MSIZE field.
	DMA_ST_CR_MSIZE_Pos = 0xd
	// Bit mask of MSIZE field.
	DMA_ST_CR_MSIZE_Msk = 0x6000
	// Byte (8-bit)
	DMA_ST_CR_MSIZE_Bits8 = 0x0
	// Half-word (16-bit)
	DMA_ST_CR_MSIZE_Bits16 = 0x1
	// Word (32-bit)
	DMA_ST_CR_MSIZE_Bits32 = 0x2
	// Position of PSIZE field.
	DMA_ST_CR_PSIZE_Pos = 0xb
	// Bit mask of PSIZE field.
	DMA_ST_CR_PSIZE_Msk = 0x1800
	// Byte (8-bit)
	DMA_ST_CR_PSIZE_Bits8 = 0x0
	// Half-word (16-bit)
	DMA_ST_CR_PSIZE_Bits16 = 0x1
	// Word (32-bit)
	DMA_ST_CR_PSIZE_Bits32 = 0x2
	// Position of MINC field.
	DMA_ST_CR_MINC_Pos = 0xa
	// Bit mask of MINC field.
	DMA_ST_CR_MINC_Msk = 0x400
	// Bit MINC.
	DMA_ST_CR_MINC = 0x400
	// Address pointer is fixed
	DMA_ST_CR_MINC_Fixed = 0x0
	// Address pointer is incremented after each data transfer
	DMA_ST_CR_MINC_Incremented = 0x1
	// Position of PINC field.
	DMA_ST_CR_PINC_Pos = 0x9
	// Bit mask of PINC field.
	DMA_ST_CR_PINC_Msk = 0x200
	// Bit PINC.
	DMA_ST_CR_PINC = 0x200
	// Address pointer is fixed
	DMA_ST_CR_PINC_Fixed = 0x0
	// Address pointer is incremented after each data transfer
	DMA_ST_CR_PINC_Incremented = 0x1
	// Position of CIRC field.
	DMA_ST_CR_CIRC_Pos = 0x8
	// Bit mask of CIRC field.
	DMA_ST_CR_CIRC_Msk = 0x100
	// Bit CIRC.
	DMA_ST_CR_CIRC = 0x100
	// Circular mode disabled
	DMA_ST_CR_CIRC_Disabled = 0x0
	// Circular mode enabled
	DMA_ST_CR_CIRC_Enabled = 0x1
	// Position of DIR field.
	DMA_ST_CR_DIR_Pos = 0x6
	// Bit mask of DIR field.
	DMA_ST_CR_DIR_Msk = 0xc0
	// Peripheral-to-memory
	DMA_ST_CR_DIR_PeripheralToMemory = 0x0
	// Memory-to-peripheral
	DMA_ST_CR_DIR_MemoryToPeripheral = 0x1
	// Memory-to-memory
	DMA_ST_CR_DIR_MemoryToMemory = 0x2
	// Position of PFCTRL field.
	DMA_ST_CR_PFCTRL_Pos = 0x5
	// Bit mask of PFCTRL field.
	DMA_ST_CR_PFCTRL_Msk = 0x20
	// Bit PFCTRL.
	DMA_ST_CR_PFCTRL = 0x20
	// The DMA is the flow controller
	DMA_ST_CR_PFCTRL_DMA = 0x0
	// The peripheral is the flow controller
	DMA_ST_CR_PFCTRL_Peripheral = 0x1
	// Position of TCIE field.
	DMA_ST_CR_TCIE_Pos = 0x4
	// Bit mask of TCIE field.
	DMA_ST_CR_TCIE_Msk = 0x10
	// Bit TCIE.
	DMA_ST_CR_TCIE = 0x10
	// TC interrupt disabled
	DMA_ST_CR_TCIE_Disabled = 0x0
	// TC interrupt enabled
	DMA_ST_CR_TCIE_Enabled = 0x1
	// Position of HTIE field.
	DMA_ST_CR_HTIE_Pos = 0x3
	// Bit mask of HTIE field.
	DMA_ST_CR_HTIE_Msk = 0x8
	// Bit HTIE.
	DMA_ST_CR_HTIE = 0x8
	// HT interrupt disabled
	DMA_ST_CR_HTIE_Disabled = 0x0
	// HT interrupt enabled
	DMA_ST_CR_HTIE_Enabled = 0x1
	// Position of TEIE field.
	DMA_ST_CR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	DMA_ST_CR_TEIE_Msk = 0x4
	// Bit TEIE.
	DMA_ST_CR_TEIE = 0x4
	// TE interrupt disabled
	DMA_ST_CR_TEIE_Disabled = 0x0
	// TE interrupt enabled
	DMA_ST_CR_TEIE_Enabled = 0x1
	// Position of DMEIE field.
	DMA_ST_CR_DMEIE_Pos = 0x1
	// Bit mask of DMEIE field.
	DMA_ST_CR_DMEIE_Msk = 0x2
	// Bit DMEIE.
	DMA_ST_CR_DMEIE = 0x2
	// DME interrupt disabled
	DMA_ST_CR_DMEIE_Disabled = 0x0
	// DME interrupt enabled
	DMA_ST_CR_DMEIE_Enabled = 0x1
	// Position of EN field.
	DMA_ST_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA_ST_CR_EN_Msk = 0x1
	// Bit EN.
	DMA_ST_CR_EN = 0x1
	// Stream disabled
	DMA_ST_CR_EN_Disabled = 0x0
	// Stream enabled
	DMA_ST_CR_EN_Enabled = 0x1
	// Position of TRBUFF field.
	DMA_ST_CR_TRBUFF_Pos = 0x14
	// Bit mask of TRBUFF field.
	DMA_ST_CR_TRBUFF_Msk = 0x100000
	// Bit TRBUFF.
	DMA_ST_CR_TRBUFF = 0x100000
	// Bufferable transfers not enabled
	DMA_ST_CR_TRBUFF_Disabled = 0x0
	// Bufferable transfers enabled
	DMA_ST_CR_TRBUFF_Enabled = 0x1

	// ST.NDTR: stream x number of data register
	// Position of NDT field.
	DMA_ST_NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA_ST_NDTR_NDT_Msk = 0xffff

	// ST.PAR: stream x peripheral address register
	// Position of PA field.
	DMA_ST_PAR_PA_Pos = 0x0
	// Bit mask of PA field.
	DMA_ST_PAR_PA_Msk = 0xffffffff

	// ST.M0AR: stream x memory 0 address register
	// Position of M0A field.
	DMA_ST_M0AR_M0A_Pos = 0x0
	// Bit mask of M0A field.
	DMA_ST_M0AR_M0A_Msk = 0xffffffff

	// ST.M1AR: stream x memory 1 address register
	// Position of M1A field.
	DMA_ST_M1AR_M1A_Pos = 0x0
	// Bit mask of M1A field.
	DMA_ST_M1AR_M1A_Msk = 0xffffffff

	// ST.FCR: stream x FIFO control register
	// Position of FEIE field.
	DMA_ST_FCR_FEIE_Pos = 0x7
	// Bit mask of FEIE field.
	DMA_ST_FCR_FEIE_Msk = 0x80
	// Bit FEIE.
	DMA_ST_FCR_FEIE = 0x80
	// FE interrupt disabled
	DMA_ST_FCR_FEIE_Disabled = 0x0
	// FE interrupt enabled
	DMA_ST_FCR_FEIE_Enabled = 0x1
	// Position of FS field.
	DMA_ST_FCR_FS_Pos = 0x3
	// Bit mask of FS field.
	DMA_ST_FCR_FS_Msk = 0x38
	// 0 < fifo_level < 1/4
	DMA_ST_FCR_FS_Quarter1 = 0x0
	// 1/4 <= fifo_level < 1/2
	DMA_ST_FCR_FS_Quarter2 = 0x1
	// 1/2 <= fifo_level < 3/4
	DMA_ST_FCR_FS_Quarter3 = 0x2
	// 3/4 <= fifo_level < full
	DMA_ST_FCR_FS_Quarter4 = 0x3
	// FIFO is empty
	DMA_ST_FCR_FS_Empty = 0x4
	// FIFO is full
	DMA_ST_FCR_FS_Full = 0x5
	// Position of DMDIS field.
	DMA_ST_FCR_DMDIS_Pos = 0x2
	// Bit mask of DMDIS field.
	DMA_ST_FCR_DMDIS_Msk = 0x4
	// Bit DMDIS.
	DMA_ST_FCR_DMDIS = 0x4
	// Direct mode is enabled
	DMA_ST_FCR_DMDIS_Enabled = 0x0
	// Direct mode is disabled
	DMA_ST_FCR_DMDIS_Disabled = 0x1
	// Position of FTH field.
	DMA_ST_FCR_FTH_Pos = 0x0
	// Bit mask of FTH field.
	DMA_ST_FCR_FTH_Msk = 0x3
	// 1/4 full FIFO
	DMA_ST_FCR_FTH_Quarter = 0x0
	// 1/2 full FIFO
	DMA_ST_FCR_FTH_Half = 0x1
	// 3/4 full FIFO
	DMA_ST_FCR_FTH_ThreeQuarters = 0x2
	// Full FIFO
	DMA_ST_FCR_FTH_Full = 0x3
	// Position of TRBUFF field.
	DMA_ST_FCR_TRBUFF_Pos = 0x14
	// Bit mask of TRBUFF field.
	DMA_ST_FCR_TRBUFF_Msk = 0x100000
	// Bit TRBUFF.
	DMA_ST_FCR_TRBUFF = 0x100000
	// Bufferable transfers not enabled
	DMA_ST_FCR_TRBUFF_Disabled = 0x0
	// Bufferable transfers enabled
	DMA_ST_FCR_TRBUFF_Enabled = 0x1
)

// Bitfields for HRTIM_Master: High Resolution Timer: Master Timers
const (
	// MCR: Master Timer Control Register
	// Position of BRSTDMA field.
	HRTIM_MCR_BRSTDMA_Pos = 0x1e
	// Bit mask of BRSTDMA field.
	HRTIM_MCR_BRSTDMA_Msk = 0xc0000000
	// Position of MREPU field.
	HRTIM_MCR_MREPU_Pos = 0x1d
	// Bit mask of MREPU field.
	HRTIM_MCR_MREPU_Msk = 0x20000000
	// Bit MREPU.
	HRTIM_MCR_MREPU = 0x20000000
	// Position of PREEN field.
	HRTIM_MCR_PREEN_Pos = 0x1b
	// Bit mask of PREEN field.
	HRTIM_MCR_PREEN_Msk = 0x8000000
	// Bit PREEN.
	HRTIM_MCR_PREEN = 0x8000000
	// Position of DACSYNC field.
	HRTIM_MCR_DACSYNC_Pos = 0x19
	// Bit mask of DACSYNC field.
	HRTIM_MCR_DACSYNC_Msk = 0x6000000
	// Position of TECEN field.
	HRTIM_MCR_TECEN_Pos = 0x15
	// Bit mask of TECEN field.
	HRTIM_MCR_TECEN_Msk = 0x200000
	// Bit TECEN.
	HRTIM_MCR_TECEN = 0x200000
	// Position of TDCEN field.
	HRTIM_MCR_TDCEN_Pos = 0x14
	// Bit mask of TDCEN field.
	HRTIM_MCR_TDCEN_Msk = 0x100000
	// Bit TDCEN.
	HRTIM_MCR_TDCEN = 0x100000
	// Position of TCCEN field.
	HRTIM_MCR_TCCEN_Pos = 0x13
	// Bit mask of TCCEN field.
	HRTIM_MCR_TCCEN_Msk = 0x80000
	// Bit TCCEN.
	HRTIM_MCR_TCCEN = 0x80000
	// Position of TBCEN field.
	HRTIM_MCR_TBCEN_Pos = 0x12
	// Bit mask of TBCEN field.
	HRTIM_MCR_TBCEN_Msk = 0x40000
	// Bit TBCEN.
	HRTIM_MCR_TBCEN = 0x40000
	// Position of TACEN field.
	HRTIM_MCR_TACEN_Pos = 0x11
	// Bit mask of TACEN field.
	HRTIM_MCR_TACEN_Msk = 0x20000
	// Bit TACEN.
	HRTIM_MCR_TACEN = 0x20000
	// Position of MCEN field.
	HRTIM_MCR_MCEN_Pos = 0x10
	// Bit mask of MCEN field.
	HRTIM_MCR_MCEN_Msk = 0x10000
	// Bit MCEN.
	HRTIM_MCR_MCEN = 0x10000
	// Position of SYNC_SRC field.
	HRTIM_MCR_SYNC_SRC_Pos = 0xe
	// Bit mask of SYNC_SRC field.
	HRTIM_MCR_SYNC_SRC_Msk = 0xc000
	// Position of SYNC_OUT field.
	HRTIM_MCR_SYNC_OUT_Pos = 0xc
	// Bit mask of SYNC_OUT field.
	HRTIM_MCR_SYNC_OUT_Msk = 0x3000
	// Position of SYNCSTRTM field.
	HRTIM_MCR_SYNCSTRTM_Pos = 0xb
	// Bit mask of SYNCSTRTM field.
	HRTIM_MCR_SYNCSTRTM_Msk = 0x800
	// Bit SYNCSTRTM.
	HRTIM_MCR_SYNCSTRTM = 0x800
	// Position of SYNCRSTM field.
	HRTIM_MCR_SYNCRSTM_Pos = 0xa
	// Bit mask of SYNCRSTM field.
	HRTIM_MCR_SYNCRSTM_Msk = 0x400
	// Bit SYNCRSTM.
	HRTIM_MCR_SYNCRSTM = 0x400
	// Position of SYNC_IN field.
	HRTIM_MCR_SYNC_IN_Pos = 0x8
	// Bit mask of SYNC_IN field.
	HRTIM_MCR_SYNC_IN_Msk = 0x300
	// Position of HALF field.
	HRTIM_MCR_HALF_Pos = 0x5
	// Bit mask of HALF field.
	HRTIM_MCR_HALF_Msk = 0x20
	// Bit HALF.
	HRTIM_MCR_HALF = 0x20
	// Position of RETRIG field.
	HRTIM_MCR_RETRIG_Pos = 0x4
	// Bit mask of RETRIG field.
	HRTIM_MCR_RETRIG_Msk = 0x10
	// Bit RETRIG.
	HRTIM_MCR_RETRIG = 0x10
	// Position of CONT field.
	HRTIM_MCR_CONT_Pos = 0x3
	// Bit mask of CONT field.
	HRTIM_MCR_CONT_Msk = 0x8
	// Bit CONT.
	HRTIM_MCR_CONT = 0x8
	// Position of CK_PSC field.
	HRTIM_MCR_CK_PSC_Pos = 0x0
	// Bit mask of CK_PSC field.
	HRTIM_MCR_CK_PSC_Msk = 0x7

	// MISR: Master Timer Interrupt Status Register
	// Position of MUPD field.
	HRTIM_MISR_MUPD_Pos = 0x6
	// Bit mask of MUPD field.
	HRTIM_MISR_MUPD_Msk = 0x40
	// Bit MUPD.
	HRTIM_MISR_MUPD = 0x40
	// Position of SYNC field.
	HRTIM_MISR_SYNC_Pos = 0x5
	// Bit mask of SYNC field.
	HRTIM_MISR_SYNC_Msk = 0x20
	// Bit SYNC.
	HRTIM_MISR_SYNC = 0x20
	// Position of MREP field.
	HRTIM_MISR_MREP_Pos = 0x4
	// Bit mask of MREP field.
	HRTIM_MISR_MREP_Msk = 0x10
	// Bit MREP.
	HRTIM_MISR_MREP = 0x10
	// Position of MCMP4 field.
	HRTIM_MISR_MCMP4_Pos = 0x3
	// Bit mask of MCMP4 field.
	HRTIM_MISR_MCMP4_Msk = 0x8
	// Bit MCMP4.
	HRTIM_MISR_MCMP4 = 0x8
	// Position of MCMP3 field.
	HRTIM_MISR_MCMP3_Pos = 0x2
	// Bit mask of MCMP3 field.
	HRTIM_MISR_MCMP3_Msk = 0x4
	// Bit MCMP3.
	HRTIM_MISR_MCMP3 = 0x4
	// Position of MCMP2 field.
	HRTIM_MISR_MCMP2_Pos = 0x1
	// Bit mask of MCMP2 field.
	HRTIM_MISR_MCMP2_Msk = 0x2
	// Bit MCMP2.
	HRTIM_MISR_MCMP2 = 0x2
	// Position of MCMP1 field.
	HRTIM_MISR_MCMP1_Pos = 0x0
	// Bit mask of MCMP1 field.
	HRTIM_MISR_MCMP1_Msk = 0x1
	// Bit MCMP1.
	HRTIM_MISR_MCMP1 = 0x1

	// MICR: Master Timer Interrupt Clear Register
	// Position of MUPDC field.
	HRTIM_MICR_MUPDC_Pos = 0x6
	// Bit mask of MUPDC field.
	HRTIM_MICR_MUPDC_Msk = 0x40
	// Bit MUPDC.
	HRTIM_MICR_MUPDC = 0x40
	// Position of SYNCC field.
	HRTIM_MICR_SYNCC_Pos = 0x5
	// Bit mask of SYNCC field.
	HRTIM_MICR_SYNCC_Msk = 0x20
	// Bit SYNCC.
	HRTIM_MICR_SYNCC = 0x20
	// Position of MREPC field.
	HRTIM_MICR_MREPC_Pos = 0x4
	// Bit mask of MREPC field.
	HRTIM_MICR_MREPC_Msk = 0x10
	// Bit MREPC.
	HRTIM_MICR_MREPC = 0x10
	// Position of MCMP4C field.
	HRTIM_MICR_MCMP4C_Pos = 0x3
	// Bit mask of MCMP4C field.
	HRTIM_MICR_MCMP4C_Msk = 0x8
	// Bit MCMP4C.
	HRTIM_MICR_MCMP4C = 0x8
	// Position of MCMP3C field.
	HRTIM_MICR_MCMP3C_Pos = 0x2
	// Bit mask of MCMP3C field.
	HRTIM_MICR_MCMP3C_Msk = 0x4
	// Bit MCMP3C.
	HRTIM_MICR_MCMP3C = 0x4
	// Position of MCMP2C field.
	HRTIM_MICR_MCMP2C_Pos = 0x1
	// Bit mask of MCMP2C field.
	HRTIM_MICR_MCMP2C_Msk = 0x2
	// Bit MCMP2C.
	HRTIM_MICR_MCMP2C = 0x2
	// Position of MCMP1C field.
	HRTIM_MICR_MCMP1C_Pos = 0x0
	// Bit mask of MCMP1C field.
	HRTIM_MICR_MCMP1C_Msk = 0x1
	// Bit MCMP1C.
	HRTIM_MICR_MCMP1C = 0x1

	// MDIER4: MDIER4
	// Position of MUPDDE field.
	HRTIM_MDIER4_MUPDDE_Pos = 0x16
	// Bit mask of MUPDDE field.
	HRTIM_MDIER4_MUPDDE_Msk = 0x400000
	// Bit MUPDDE.
	HRTIM_MDIER4_MUPDDE = 0x400000
	// Position of SYNCDE field.
	HRTIM_MDIER4_SYNCDE_Pos = 0x15
	// Bit mask of SYNCDE field.
	HRTIM_MDIER4_SYNCDE_Msk = 0x200000
	// Bit SYNCDE.
	HRTIM_MDIER4_SYNCDE = 0x200000
	// Position of MREPDE field.
	HRTIM_MDIER4_MREPDE_Pos = 0x14
	// Bit mask of MREPDE field.
	HRTIM_MDIER4_MREPDE_Msk = 0x100000
	// Bit MREPDE.
	HRTIM_MDIER4_MREPDE = 0x100000
	// Position of MCMP4DE field.
	HRTIM_MDIER4_MCMP4DE_Pos = 0x13
	// Bit mask of MCMP4DE field.
	HRTIM_MDIER4_MCMP4DE_Msk = 0x80000
	// Bit MCMP4DE.
	HRTIM_MDIER4_MCMP4DE = 0x80000
	// Position of MCMP3DE field.
	HRTIM_MDIER4_MCMP3DE_Pos = 0x12
	// Bit mask of MCMP3DE field.
	HRTIM_MDIER4_MCMP3DE_Msk = 0x40000
	// Bit MCMP3DE.
	HRTIM_MDIER4_MCMP3DE = 0x40000
	// Position of MCMP2DE field.
	HRTIM_MDIER4_MCMP2DE_Pos = 0x11
	// Bit mask of MCMP2DE field.
	HRTIM_MDIER4_MCMP2DE_Msk = 0x20000
	// Bit MCMP2DE.
	HRTIM_MDIER4_MCMP2DE = 0x20000
	// Position of MCMP1DE field.
	HRTIM_MDIER4_MCMP1DE_Pos = 0x10
	// Bit mask of MCMP1DE field.
	HRTIM_MDIER4_MCMP1DE_Msk = 0x10000
	// Bit MCMP1DE.
	HRTIM_MDIER4_MCMP1DE = 0x10000
	// Position of MUPDIE field.
	HRTIM_MDIER4_MUPDIE_Pos = 0x6
	// Bit mask of MUPDIE field.
	HRTIM_MDIER4_MUPDIE_Msk = 0x40
	// Bit MUPDIE.
	HRTIM_MDIER4_MUPDIE = 0x40
	// Position of SYNCIE field.
	HRTIM_MDIER4_SYNCIE_Pos = 0x5
	// Bit mask of SYNCIE field.
	HRTIM_MDIER4_SYNCIE_Msk = 0x20
	// Bit SYNCIE.
	HRTIM_MDIER4_SYNCIE = 0x20
	// Position of MREPIE field.
	HRTIM_MDIER4_MREPIE_Pos = 0x4
	// Bit mask of MREPIE field.
	HRTIM_MDIER4_MREPIE_Msk = 0x10
	// Bit MREPIE.
	HRTIM_MDIER4_MREPIE = 0x10
	// Position of MCMP4IE field.
	HRTIM_MDIER4_MCMP4IE_Pos = 0x3
	// Bit mask of MCMP4IE field.
	HRTIM_MDIER4_MCMP4IE_Msk = 0x8
	// Bit MCMP4IE.
	HRTIM_MDIER4_MCMP4IE = 0x8
	// Position of MCMP3IE field.
	HRTIM_MDIER4_MCMP3IE_Pos = 0x2
	// Bit mask of MCMP3IE field.
	HRTIM_MDIER4_MCMP3IE_Msk = 0x4
	// Bit MCMP3IE.
	HRTIM_MDIER4_MCMP3IE = 0x4
	// Position of MCMP2IE field.
	HRTIM_MDIER4_MCMP2IE_Pos = 0x1
	// Bit mask of MCMP2IE field.
	HRTIM_MDIER4_MCMP2IE_Msk = 0x2
	// Bit MCMP2IE.
	HRTIM_MDIER4_MCMP2IE = 0x2
	// Position of MCMP1IE field.
	HRTIM_MDIER4_MCMP1IE_Pos = 0x0
	// Bit mask of MCMP1IE field.
	HRTIM_MDIER4_MCMP1IE_Msk = 0x1
	// Bit MCMP1IE.
	HRTIM_MDIER4_MCMP1IE = 0x1

	// MCNTR: Master Timer Counter Register
	// Position of MCNT field.
	HRTIM_MCNTR_MCNT_Pos = 0x0
	// Bit mask of MCNT field.
	HRTIM_MCNTR_MCNT_Msk = 0xffff

	// MPER: Master Timer Period Register
	// Position of MPER field.
	HRTIM_MPER_MPER_Pos = 0x0
	// Bit mask of MPER field.
	HRTIM_MPER_MPER_Msk = 0xffff

	// MREP: Master Timer Repetition Register
	// Position of MREP field.
	HRTIM_MREP_MREP_Pos = 0x0
	// Bit mask of MREP field.
	HRTIM_MREP_MREP_Msk = 0xff

	// MCMP1R: Master Timer Compare 1 Register
	// Position of MCMP1 field.
	HRTIM_MCMP1R_MCMP1_Pos = 0x0
	// Bit mask of MCMP1 field.
	HRTIM_MCMP1R_MCMP1_Msk = 0xffff

	// MCMP2R: Master Timer Compare 2 Register
	// Position of MCMP2 field.
	HRTIM_MCMP2R_MCMP2_Pos = 0x0
	// Bit mask of MCMP2 field.
	HRTIM_MCMP2R_MCMP2_Msk = 0xffff

	// MCMP3R: Master Timer Compare 3 Register
	// Position of MCMP3 field.
	HRTIM_MCMP3R_MCMP3_Pos = 0x0
	// Bit mask of MCMP3 field.
	HRTIM_MCMP3R_MCMP3_Msk = 0xffff

	// MCMP4R: Master Timer Compare 4 Register
	// Position of MCMP4 field.
	HRTIM_MCMP4R_MCMP4_Pos = 0x0
	// Bit mask of MCMP4 field.
	HRTIM_MCMP4R_MCMP4_Msk = 0xffff
)

// Bitfields for DFSDM: Digital filter for sigma delta modulators
const (
	// DFSDM_CHCFG0R1: DFSDM channel configuration 0 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG0R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG0R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG0R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG0R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG0R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG0R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG0R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG0R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG0R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG0R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG0R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG0R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG0R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG0R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG0R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG0R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG0R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG0R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG0R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG0R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG0R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG0R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG0R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG0R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG1R1: DFSDM channel configuration 1 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG1R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG1R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG1R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG1R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG1R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG1R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG1R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG1R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG1R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG1R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG1R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG1R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG1R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG1R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG1R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG1R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG1R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG1R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG1R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG1R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG1R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG1R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG1R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG1R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG2R1: DFSDM channel configuration 2 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG2R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG2R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG2R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG2R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG2R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG2R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG2R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG2R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG2R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG2R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG2R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG2R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG2R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG2R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG2R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG2R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG2R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG2R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG2R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG2R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG2R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG2R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG2R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG2R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG3R1: DFSDM channel configuration 3 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG3R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG3R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG3R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG3R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG3R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG3R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG3R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG3R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG3R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG3R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG3R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG3R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG3R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG3R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG3R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG3R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG3R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG3R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG3R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG3R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG3R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG3R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG3R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG3R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG4R1: DFSDM channel configuration 4 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG4R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG4R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG4R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG4R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG4R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG4R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG4R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG4R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG4R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG4R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG4R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG4R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG4R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG4R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG4R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG4R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG4R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG4R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG4R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG4R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG4R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG4R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG4R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG4R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG5R1: DFSDM channel configuration 5 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG5R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG5R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG5R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG5R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG5R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG5R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG5R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG5R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG5R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG5R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG5R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG5R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG5R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG5R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG5R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG5R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG5R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG5R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG5R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG5R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG5R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG5R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG5R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG5R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG6R1: DFSDM channel configuration 6 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG6R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG6R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG6R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG6R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG6R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG6R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG6R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG6R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG6R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG6R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG6R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG6R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG6R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG6R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG6R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG6R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG6R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG6R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG6R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG6R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG6R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG6R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG6R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG6R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG7R1: DFSDM channel configuration 7 register 1
	// Position of SITP field.
	DFSDM_DFSDM_CHCFG7R1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG7R1_SITP_Msk = 0x3
	// Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG7R1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG7R1_SPICKSEL_Msk = 0xc
	// Position of SCDEN field.
	DFSDM_DFSDM_CHCFG7R1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG7R1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_DFSDM_CHCFG7R1_SCDEN = 0x20
	// Position of CKABEN field.
	DFSDM_DFSDM_CHCFG7R1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG7R1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_DFSDM_CHCFG7R1_CKABEN = 0x40
	// Position of CHEN field.
	DFSDM_DFSDM_CHCFG7R1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG7R1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_DFSDM_CHCFG7R1_CHEN = 0x80
	// Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG7R1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG7R1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_DFSDM_CHCFG7R1_CHINSEL = 0x100
	// Position of DATMPX field.
	DFSDM_DFSDM_CHCFG7R1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG7R1_DATMPX_Msk = 0x3000
	// Position of DATPACK field.
	DFSDM_DFSDM_CHCFG7R1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG7R1_DATPACK_Msk = 0xc000
	// Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTDIV_Msk = 0xff0000
	// Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG7R1_CKOUTSRC = 0x40000000
	// Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG7R1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG7R1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_DFSDM_CHCFG7R1_DFSDMEN = 0x80000000

	// DFSDM_CHCFG0R2: DFSDM channel configuration 0 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG0R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG0R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG0R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG0R2_OFFSET_Msk = 0xffffff00

	// DFSDM_CHCFG1R2: DFSDM channel configuration 1 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG1R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG1R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG1R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG1R2_OFFSET_Msk = 0xffffff00

	// DFSDM_CHCFG2R2: DFSDM channel configuration 2 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG2R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG2R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG2R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG2R2_OFFSET_Msk = 0xffffff00

	// DFSDM_CHCFG3R2: DFSDM channel configuration 3 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG3R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG3R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG3R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG3R2_OFFSET_Msk = 0xffffff00

	// DFSDM_CHCFG4R2: DFSDM channel configuration 4 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG4R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG4R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG4R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG4R2_OFFSET_Msk = 0xffffff00

	// DFSDM_CHCFG5R2: DFSDM channel configuration 5 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG5R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG5R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG5R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG5R2_OFFSET_Msk = 0xffffff00

	// DFSDM_CHCFG6R2: DFSDM channel configuration 6 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG6R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG6R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG6R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG6R2_OFFSET_Msk = 0xffffff00

	// DFSDM_CHCFG7R2: DFSDM channel configuration 7 register 2
	// Position of DTRBS field.
	DFSDM_DFSDM_CHCFG7R2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG7R2_DTRBS_Msk = 0xf8
	// Position of OFFSET field.
	DFSDM_DFSDM_CHCFG7R2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_DFSDM_CHCFG7R2_OFFSET_Msk = 0xffffff00

	// DFSDM_AWSCD0R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD0R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD0R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD0R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD0R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD0R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD0R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD0R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD0R_AWFORD_Msk = 0xc00000

	// DFSDM_AWSCD1R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD1R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD1R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD1R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD1R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD1R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD1R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD1R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD1R_AWFORD_Msk = 0xc00000

	// DFSDM_AWSCD2R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD2R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD2R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD2R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD2R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD2R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD2R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD2R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD2R_AWFORD_Msk = 0xc00000

	// DFSDM_AWSCD3R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD3R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD3R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD3R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD3R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD3R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD3R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD3R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD3R_AWFORD_Msk = 0xc00000

	// DFSDM_AWSCD4R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD4R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD4R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD4R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD4R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD4R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD4R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD4R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD4R_AWFORD_Msk = 0xc00000

	// DFSDM_AWSCD5R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD5R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD5R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD5R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD5R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD5R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD5R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD5R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD5R_AWFORD_Msk = 0xc00000

	// DFSDM_AWSCD6R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD6R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD6R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD6R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD6R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD6R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD6R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD6R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD6R_AWFORD_Msk = 0xc00000

	// DFSDM_AWSCD7R: DFSDM analog watchdog and short-circuit detector register
	// Position of SCDT field.
	DFSDM_DFSDM_AWSCD7R_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD7R_SCDT_Msk = 0xff
	// Position of BKSCD field.
	DFSDM_DFSDM_AWSCD7R_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD7R_BKSCD_Msk = 0xf000
	// Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD7R_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD7R_AWFOSR_Msk = 0x1f0000
	// Position of AWFORD field.
	DFSDM_DFSDM_AWSCD7R_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_DFSDM_AWSCD7R_AWFORD_Msk = 0xc00000

	// DFSDM_CHWDAT0R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT0R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT0R_WDATA_Msk = 0xffff

	// DFSDM_CHWDAT1R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT1R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT1R_WDATA_Msk = 0xffff

	// DFSDM_CHWDAT2R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT2R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT2R_WDATA_Msk = 0xffff

	// DFSDM_CHWDAT3R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT3R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT3R_WDATA_Msk = 0xffff

	// DFSDM_CHWDAT4R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT4R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT4R_WDATA_Msk = 0xffff

	// DFSDM_CHWDAT5R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT5R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT5R_WDATA_Msk = 0xffff

	// DFSDM_CHWDAT6R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT6R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT6R_WDATA_Msk = 0xffff

	// DFSDM_CHWDAT7R: DFSDM channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_DFSDM_CHWDAT7R_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_DFSDM_CHWDAT7R_WDATA_Msk = 0xffff

	// DFSDM_CHDATIN0R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN0R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN0R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN0R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN0R_INDAT1_Msk = 0xffff0000

	// DFSDM_CHDATIN1R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN1R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN1R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN1R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN1R_INDAT1_Msk = 0xffff0000

	// DFSDM_CHDATIN2R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN2R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN2R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN2R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN2R_INDAT1_Msk = 0xffff0000

	// DFSDM_CHDATIN3R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN3R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN3R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN3R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN3R_INDAT1_Msk = 0xffff0000

	// DFSDM_CHDATIN4R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN4R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN4R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN4R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN4R_INDAT1_Msk = 0xffff0000

	// DFSDM_CHDATIN5R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN5R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN5R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN5R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN5R_INDAT1_Msk = 0xffff0000

	// DFSDM_CHDATIN6R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN6R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN6R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN6R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN6R_INDAT1_Msk = 0xffff0000

	// DFSDM_CHDATIN7R: DFSDM channel data input register
	// Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN7R_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN7R_INDAT0_Msk = 0xffff
	// Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN7R_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_DFSDM_CHDATIN7R_INDAT1_Msk = 0xffff0000

	// DFSDM0_CR1: DFSDM control register 1
	// Position of DFEN field.
	DFSDM_DFSDM0_CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM_DFSDM0_CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM_DFSDM0_CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM_DFSDM0_CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM_DFSDM0_CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM_DFSDM0_CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM_DFSDM0_CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM_DFSDM0_CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM_DFSDM0_CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM_DFSDM0_CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM_DFSDM0_CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM_DFSDM0_CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM_DFSDM0_CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM_DFSDM0_CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM_DFSDM0_CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM_DFSDM0_CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM_DFSDM0_CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM_DFSDM0_CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM_DFSDM0_CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM_DFSDM0_CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM_DFSDM0_CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM_DFSDM0_CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM_DFSDM0_CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM_DFSDM0_CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM_DFSDM0_CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM_DFSDM0_CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM_DFSDM0_CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM_DFSDM0_CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM_DFSDM0_CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM_DFSDM0_CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM_DFSDM0_CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM_DFSDM0_CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM_DFSDM0_CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM_DFSDM0_CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM_DFSDM0_CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM_DFSDM0_CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM_DFSDM0_CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM_DFSDM0_CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM_DFSDM0_CR1_AWFSEL = 0x40000000

	// DFSDM1_CR1: DFSDM control register 1
	// Position of DFEN field.
	DFSDM_DFSDM1_CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM_DFSDM1_CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM_DFSDM1_CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM_DFSDM1_CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM_DFSDM1_CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM_DFSDM1_CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM_DFSDM1_CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM_DFSDM1_CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM_DFSDM1_CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM_DFSDM1_CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM_DFSDM1_CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM_DFSDM1_CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM_DFSDM1_CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM_DFSDM1_CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM_DFSDM1_CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM_DFSDM1_CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM_DFSDM1_CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM_DFSDM1_CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM_DFSDM1_CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM_DFSDM1_CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM_DFSDM1_CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM_DFSDM1_CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM_DFSDM1_CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM_DFSDM1_CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM_DFSDM1_CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM_DFSDM1_CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM_DFSDM1_CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM_DFSDM1_CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM_DFSDM1_CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM_DFSDM1_CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM_DFSDM1_CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM_DFSDM1_CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM_DFSDM1_CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM_DFSDM1_CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM_DFSDM1_CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM_DFSDM1_CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM_DFSDM1_CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM_DFSDM1_CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM_DFSDM1_CR1_AWFSEL = 0x40000000

	// DFSDM2_CR1: DFSDM control register 1
	// Position of DFEN field.
	DFSDM_DFSDM2_CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM_DFSDM2_CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM_DFSDM2_CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM_DFSDM2_CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM_DFSDM2_CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM_DFSDM2_CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM_DFSDM2_CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM_DFSDM2_CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM_DFSDM2_CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM_DFSDM2_CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM_DFSDM2_CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM_DFSDM2_CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM_DFSDM2_CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM_DFSDM2_CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM_DFSDM2_CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM_DFSDM2_CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM_DFSDM2_CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM_DFSDM2_CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM_DFSDM2_CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM_DFSDM2_CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM_DFSDM2_CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM_DFSDM2_CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM_DFSDM2_CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM_DFSDM2_CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM_DFSDM2_CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM_DFSDM2_CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM_DFSDM2_CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM_DFSDM2_CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM_DFSDM2_CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM_DFSDM2_CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM_DFSDM2_CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM_DFSDM2_CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM_DFSDM2_CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM_DFSDM2_CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM_DFSDM2_CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM_DFSDM2_CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM_DFSDM2_CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM_DFSDM2_CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM_DFSDM2_CR1_AWFSEL = 0x40000000

	// DFSDM3_CR1: DFSDM control register 1
	// Position of DFEN field.
	DFSDM_DFSDM3_CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM_DFSDM3_CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM_DFSDM3_CR1_DFEN = 0x1
	// Position of JSWSTART field.
	DFSDM_DFSDM3_CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM_DFSDM3_CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM_DFSDM3_CR1_JSWSTART = 0x2
	// Position of JSYNC field.
	DFSDM_DFSDM3_CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM_DFSDM3_CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM_DFSDM3_CR1_JSYNC = 0x8
	// Position of JSCAN field.
	DFSDM_DFSDM3_CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM_DFSDM3_CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM_DFSDM3_CR1_JSCAN = 0x10
	// Position of JDMAEN field.
	DFSDM_DFSDM3_CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM_DFSDM3_CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM_DFSDM3_CR1_JDMAEN = 0x20
	// Position of JEXTSEL field.
	DFSDM_DFSDM3_CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM_DFSDM3_CR1_JEXTSEL_Msk = 0x1f00
	// Position of JEXTEN field.
	DFSDM_DFSDM3_CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM_DFSDM3_CR1_JEXTEN_Msk = 0x6000
	// Position of RSWSTART field.
	DFSDM_DFSDM3_CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM_DFSDM3_CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM_DFSDM3_CR1_RSWSTART = 0x20000
	// Position of RCONT field.
	DFSDM_DFSDM3_CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM_DFSDM3_CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM_DFSDM3_CR1_RCONT = 0x40000
	// Position of RSYNC field.
	DFSDM_DFSDM3_CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM_DFSDM3_CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM_DFSDM3_CR1_RSYNC = 0x80000
	// Position of RDMAEN field.
	DFSDM_DFSDM3_CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM_DFSDM3_CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM_DFSDM3_CR1_RDMAEN = 0x200000
	// Position of RCH field.
	DFSDM_DFSDM3_CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM_DFSDM3_CR1_RCH_Msk = 0x7000000
	// Position of FAST field.
	DFSDM_DFSDM3_CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM_DFSDM3_CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM_DFSDM3_CR1_FAST = 0x20000000
	// Position of AWFSEL field.
	DFSDM_DFSDM3_CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM_DFSDM3_CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM_DFSDM3_CR1_AWFSEL = 0x40000000

	// DFSDM0_CR2: DFSDM control register 2
	// Position of JEOCIE field.
	DFSDM_DFSDM0_CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM_DFSDM0_CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM_DFSDM0_CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM_DFSDM0_CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM_DFSDM0_CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM_DFSDM0_CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM_DFSDM0_CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM_DFSDM0_CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM_DFSDM0_CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM_DFSDM0_CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM_DFSDM0_CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM_DFSDM0_CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM_DFSDM0_CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM_DFSDM0_CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM_DFSDM0_CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM_DFSDM0_CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM_DFSDM0_CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM_DFSDM0_CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM_DFSDM0_CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM_DFSDM0_CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM_DFSDM0_CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM_DFSDM0_CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM_DFSDM0_CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM_DFSDM0_CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM_DFSDM0_CR2_AWDCH_Msk = 0xff0000

	// DFSDM1_CR2: DFSDM control register 2
	// Position of JEOCIE field.
	DFSDM_DFSDM1_CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM_DFSDM1_CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM_DFSDM1_CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM_DFSDM1_CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM_DFSDM1_CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM_DFSDM1_CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM_DFSDM1_CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM_DFSDM1_CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM_DFSDM1_CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM_DFSDM1_CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM_DFSDM1_CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM_DFSDM1_CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM_DFSDM1_CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM_DFSDM1_CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM_DFSDM1_CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM_DFSDM1_CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM_DFSDM1_CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM_DFSDM1_CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM_DFSDM1_CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM_DFSDM1_CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM_DFSDM1_CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM_DFSDM1_CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM_DFSDM1_CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM_DFSDM1_CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM_DFSDM1_CR2_AWDCH_Msk = 0xff0000

	// DFSDM2_CR2: DFSDM control register 2
	// Position of JEOCIE field.
	DFSDM_DFSDM2_CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM_DFSDM2_CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM_DFSDM2_CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM_DFSDM2_CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM_DFSDM2_CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM_DFSDM2_CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM_DFSDM2_CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM_DFSDM2_CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM_DFSDM2_CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM_DFSDM2_CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM_DFSDM2_CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM_DFSDM2_CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM_DFSDM2_CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM_DFSDM2_CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM_DFSDM2_CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM_DFSDM2_CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM_DFSDM2_CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM_DFSDM2_CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM_DFSDM2_CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM_DFSDM2_CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM_DFSDM2_CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM_DFSDM2_CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM_DFSDM2_CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM_DFSDM2_CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM_DFSDM2_CR2_AWDCH_Msk = 0xff0000

	// DFSDM3_CR2: DFSDM control register 2
	// Position of JEOCIE field.
	DFSDM_DFSDM3_CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM_DFSDM3_CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM_DFSDM3_CR2_JEOCIE = 0x1
	// Position of REOCIE field.
	DFSDM_DFSDM3_CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM_DFSDM3_CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM_DFSDM3_CR2_REOCIE = 0x2
	// Position of JOVRIE field.
	DFSDM_DFSDM3_CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM_DFSDM3_CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM_DFSDM3_CR2_JOVRIE = 0x4
	// Position of ROVRIE field.
	DFSDM_DFSDM3_CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM_DFSDM3_CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM_DFSDM3_CR2_ROVRIE = 0x8
	// Position of AWDIE field.
	DFSDM_DFSDM3_CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM_DFSDM3_CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM_DFSDM3_CR2_AWDIE = 0x10
	// Position of SCDIE field.
	DFSDM_DFSDM3_CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM_DFSDM3_CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM_DFSDM3_CR2_SCDIE = 0x20
	// Position of CKABIE field.
	DFSDM_DFSDM3_CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM_DFSDM3_CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM_DFSDM3_CR2_CKABIE = 0x40
	// Position of EXCH field.
	DFSDM_DFSDM3_CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM_DFSDM3_CR2_EXCH_Msk = 0xff00
	// Position of AWDCH field.
	DFSDM_DFSDM3_CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM_DFSDM3_CR2_AWDCH_Msk = 0xff0000

	// DFSDM0_ISR: DFSDM interrupt and status register
	// Position of JEOCF field.
	DFSDM_DFSDM0_ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM_DFSDM0_ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM_DFSDM0_ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM_DFSDM0_ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM_DFSDM0_ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM_DFSDM0_ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM_DFSDM0_ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM_DFSDM0_ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM_DFSDM0_ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM_DFSDM0_ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM_DFSDM0_ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM_DFSDM0_ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM_DFSDM0_ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM_DFSDM0_ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM_DFSDM0_ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM_DFSDM0_ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM_DFSDM0_ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM_DFSDM0_ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM_DFSDM0_ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM_DFSDM0_ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM_DFSDM0_ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM_DFSDM0_ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM_DFSDM0_ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM_DFSDM0_ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM_DFSDM0_ISR_SCDF_Msk = 0xff000000

	// DFSDM1_ISR: DFSDM interrupt and status register
	// Position of JEOCF field.
	DFSDM_DFSDM1_ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM_DFSDM1_ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM_DFSDM1_ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM_DFSDM1_ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM_DFSDM1_ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM_DFSDM1_ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM_DFSDM1_ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM_DFSDM1_ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM_DFSDM1_ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM_DFSDM1_ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM_DFSDM1_ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM_DFSDM1_ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM_DFSDM1_ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM_DFSDM1_ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM_DFSDM1_ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM_DFSDM1_ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM_DFSDM1_ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM_DFSDM1_ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM_DFSDM1_ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM_DFSDM1_ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM_DFSDM1_ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM_DFSDM1_ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM_DFSDM1_ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM_DFSDM1_ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM_DFSDM1_ISR_SCDF_Msk = 0xff000000

	// DFSDM2_ISR: DFSDM interrupt and status register
	// Position of JEOCF field.
	DFSDM_DFSDM2_ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM_DFSDM2_ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM_DFSDM2_ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM_DFSDM2_ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM_DFSDM2_ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM_DFSDM2_ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM_DFSDM2_ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM_DFSDM2_ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM_DFSDM2_ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM_DFSDM2_ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM_DFSDM2_ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM_DFSDM2_ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM_DFSDM2_ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM_DFSDM2_ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM_DFSDM2_ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM_DFSDM2_ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM_DFSDM2_ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM_DFSDM2_ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM_DFSDM2_ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM_DFSDM2_ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM_DFSDM2_ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM_DFSDM2_ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM_DFSDM2_ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM_DFSDM2_ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM_DFSDM2_ISR_SCDF_Msk = 0xff000000

	// DFSDM3_ISR: DFSDM interrupt and status register
	// Position of JEOCF field.
	DFSDM_DFSDM3_ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM_DFSDM3_ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM_DFSDM3_ISR_JEOCF = 0x1
	// Position of REOCF field.
	DFSDM_DFSDM3_ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM_DFSDM3_ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM_DFSDM3_ISR_REOCF = 0x2
	// Position of JOVRF field.
	DFSDM_DFSDM3_ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM_DFSDM3_ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM_DFSDM3_ISR_JOVRF = 0x4
	// Position of ROVRF field.
	DFSDM_DFSDM3_ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM_DFSDM3_ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM_DFSDM3_ISR_ROVRF = 0x8
	// Position of AWDF field.
	DFSDM_DFSDM3_ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM_DFSDM3_ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM_DFSDM3_ISR_AWDF = 0x10
	// Position of JCIP field.
	DFSDM_DFSDM3_ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM_DFSDM3_ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM_DFSDM3_ISR_JCIP = 0x2000
	// Position of RCIP field.
	DFSDM_DFSDM3_ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM_DFSDM3_ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM_DFSDM3_ISR_RCIP = 0x4000
	// Position of CKABF field.
	DFSDM_DFSDM3_ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM_DFSDM3_ISR_CKABF_Msk = 0xff0000
	// Position of SCDF field.
	DFSDM_DFSDM3_ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM_DFSDM3_ISR_SCDF_Msk = 0xff000000

	// DFSDM0_ICR: DFSDM interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM_DFSDM0_ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM_DFSDM0_ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM_DFSDM0_ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM_DFSDM0_ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM_DFSDM0_ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM_DFSDM0_ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM_DFSDM0_ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM_DFSDM0_ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM_DFSDM0_ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM_DFSDM0_ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM1_ICR: DFSDM interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM_DFSDM1_ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM_DFSDM1_ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM_DFSDM1_ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM_DFSDM1_ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM_DFSDM1_ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM_DFSDM1_ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM_DFSDM1_ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM_DFSDM1_ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM_DFSDM1_ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM_DFSDM1_ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM2_ICR: DFSDM interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM_DFSDM2_ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM_DFSDM2_ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM_DFSDM2_ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM_DFSDM2_ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM_DFSDM2_ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM_DFSDM2_ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM_DFSDM2_ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM_DFSDM2_ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM_DFSDM2_ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM_DFSDM2_ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM3_ICR: DFSDM interrupt flag clear register
	// Position of CLRJOVRF field.
	DFSDM_DFSDM3_ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM_DFSDM3_ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM_DFSDM3_ICR_CLRJOVRF = 0x4
	// Position of CLRROVRF field.
	DFSDM_DFSDM3_ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM_DFSDM3_ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM_DFSDM3_ICR_CLRROVRF = 0x8
	// Position of CLRCKABF field.
	DFSDM_DFSDM3_ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM_DFSDM3_ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRSCDF field.
	DFSDM_DFSDM3_ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM_DFSDM3_ICR_CLRSCDF_Msk = 0xff000000

	// DFSDM0_JCHGR: DFSDM injected channel group selection register
	// Position of JCHG field.
	DFSDM_DFSDM0_JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM_DFSDM0_JCHGR_JCHG_Msk = 0xff

	// DFSDM1_JCHGR: DFSDM injected channel group selection register
	// Position of JCHG field.
	DFSDM_DFSDM1_JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM_DFSDM1_JCHGR_JCHG_Msk = 0xff

	// DFSDM2_JCHGR: DFSDM injected channel group selection register
	// Position of JCHG field.
	DFSDM_DFSDM2_JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM_DFSDM2_JCHGR_JCHG_Msk = 0xff

	// DFSDM3_JCHGR: DFSDM injected channel group selection register
	// Position of JCHG field.
	DFSDM_DFSDM3_JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM_DFSDM3_JCHGR_JCHG_Msk = 0xff

	// DFSDM0_FCR: DFSDM filter control register
	// Position of IOSR field.
	DFSDM_DFSDM0_FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM_DFSDM0_FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM_DFSDM0_FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM_DFSDM0_FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM_DFSDM0_FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM_DFSDM0_FCR_FORD_Msk = 0xe0000000

	// DFSDM1_FCR: DFSDM filter control register
	// Position of IOSR field.
	DFSDM_DFSDM1_FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM_DFSDM1_FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM_DFSDM1_FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM_DFSDM1_FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM_DFSDM1_FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM_DFSDM1_FCR_FORD_Msk = 0xe0000000

	// DFSDM2_FCR: DFSDM filter control register
	// Position of IOSR field.
	DFSDM_DFSDM2_FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM_DFSDM2_FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM_DFSDM2_FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM_DFSDM2_FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM_DFSDM2_FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM_DFSDM2_FCR_FORD_Msk = 0xe0000000

	// DFSDM3_FCR: DFSDM filter control register
	// Position of IOSR field.
	DFSDM_DFSDM3_FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM_DFSDM3_FCR_IOSR_Msk = 0xff
	// Position of FOSR field.
	DFSDM_DFSDM3_FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM_DFSDM3_FCR_FOSR_Msk = 0x3ff0000
	// Position of FORD field.
	DFSDM_DFSDM3_FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM_DFSDM3_FCR_FORD_Msk = 0xe0000000

	// DFSDM0_JDATAR: DFSDM data register for injected group
	// Position of JDATACH field.
	DFSDM_DFSDM0_JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM_DFSDM0_JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM_DFSDM0_JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM_DFSDM0_JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM1_JDATAR: DFSDM data register for injected group
	// Position of JDATACH field.
	DFSDM_DFSDM1_JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM_DFSDM1_JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM_DFSDM1_JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM_DFSDM1_JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM2_JDATAR: DFSDM data register for injected group
	// Position of JDATACH field.
	DFSDM_DFSDM2_JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM_DFSDM2_JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM_DFSDM2_JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM_DFSDM2_JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM3_JDATAR: DFSDM data register for injected group
	// Position of JDATACH field.
	DFSDM_DFSDM3_JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM_DFSDM3_JDATAR_JDATACH_Msk = 0x7
	// Position of JDATA field.
	DFSDM_DFSDM3_JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM_DFSDM3_JDATAR_JDATA_Msk = 0xffffff00

	// DFSDM0_RDATAR: DFSDM data register for the regular channel
	// Position of RDATACH field.
	DFSDM_DFSDM0_RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM_DFSDM0_RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM_DFSDM0_RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM_DFSDM0_RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM_DFSDM0_RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM_DFSDM0_RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM_DFSDM0_RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM1_RDATAR: DFSDM data register for the regular channel
	// Position of RDATACH field.
	DFSDM_DFSDM1_RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM_DFSDM1_RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM_DFSDM1_RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM_DFSDM1_RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM_DFSDM1_RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM_DFSDM1_RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM_DFSDM1_RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM2_RDATAR: DFSDM data register for the regular channel
	// Position of RDATACH field.
	DFSDM_DFSDM2_RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM_DFSDM2_RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM_DFSDM2_RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM_DFSDM2_RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM_DFSDM2_RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM_DFSDM2_RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM_DFSDM2_RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM3_RDATAR: DFSDM data register for the regular channel
	// Position of RDATACH field.
	DFSDM_DFSDM3_RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM_DFSDM3_RDATAR_RDATACH_Msk = 0x7
	// Position of RPEND field.
	DFSDM_DFSDM3_RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM_DFSDM3_RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM_DFSDM3_RDATAR_RPEND = 0x10
	// Position of RDATA field.
	DFSDM_DFSDM3_RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM_DFSDM3_RDATAR_RDATA_Msk = 0xffffff00

	// DFSDM0_AWHTR: DFSDM analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM_DFSDM0_AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM_DFSDM0_AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM_DFSDM0_AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM_DFSDM0_AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM1_AWHTR: DFSDM analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM_DFSDM1_AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM_DFSDM1_AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM_DFSDM1_AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM_DFSDM1_AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM2_AWHTR: DFSDM analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM_DFSDM2_AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM_DFSDM2_AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM_DFSDM2_AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM_DFSDM2_AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM3_AWHTR: DFSDM analog watchdog high threshold register
	// Position of BKAWH field.
	DFSDM_DFSDM3_AWHTR_BKAWH_Pos = 0x0
	// Bit mask of BKAWH field.
	DFSDM_DFSDM3_AWHTR_BKAWH_Msk = 0xf
	// Position of AWHT field.
	DFSDM_DFSDM3_AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM_DFSDM3_AWHTR_AWHT_Msk = 0xffffff00

	// DFSDM0_AWLTR: DFSDM analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM_DFSDM0_AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM_DFSDM0_AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM_DFSDM0_AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM_DFSDM0_AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM1_AWLTR: DFSDM analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM_DFSDM1_AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM_DFSDM1_AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM_DFSDM1_AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM_DFSDM1_AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM2_AWLTR: DFSDM analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM_DFSDM2_AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM_DFSDM2_AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM_DFSDM2_AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM_DFSDM2_AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM3_AWLTR: DFSDM analog watchdog low threshold register
	// Position of BKAWL field.
	DFSDM_DFSDM3_AWLTR_BKAWL_Pos = 0x0
	// Bit mask of BKAWL field.
	DFSDM_DFSDM3_AWLTR_BKAWL_Msk = 0xf
	// Position of AWLT field.
	DFSDM_DFSDM3_AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM_DFSDM3_AWLTR_AWLT_Msk = 0xffffff00

	// DFSDM0_AWSR: DFSDM analog watchdog status register
	// Position of AWLTF field.
	DFSDM_DFSDM0_AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM_DFSDM0_AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM_DFSDM0_AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM_DFSDM0_AWSR_AWHTF_Msk = 0xff00

	// DFSDM1_AWSR: DFSDM analog watchdog status register
	// Position of AWLTF field.
	DFSDM_DFSDM1_AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM_DFSDM1_AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM_DFSDM1_AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM_DFSDM1_AWSR_AWHTF_Msk = 0xff00

	// DFSDM2_AWSR: DFSDM analog watchdog status register
	// Position of AWLTF field.
	DFSDM_DFSDM2_AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM_DFSDM2_AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM_DFSDM2_AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM_DFSDM2_AWSR_AWHTF_Msk = 0xff00

	// DFSDM3_AWSR: DFSDM analog watchdog status register
	// Position of AWLTF field.
	DFSDM_DFSDM3_AWSR_AWLTF_Pos = 0x0
	// Bit mask of AWLTF field.
	DFSDM_DFSDM3_AWSR_AWLTF_Msk = 0xff
	// Position of AWHTF field.
	DFSDM_DFSDM3_AWSR_AWHTF_Pos = 0x8
	// Bit mask of AWHTF field.
	DFSDM_DFSDM3_AWSR_AWHTF_Msk = 0xff00

	// DFSDM0_AWCFR: DFSDM analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM_DFSDM0_AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM_DFSDM0_AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM_DFSDM0_AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM_DFSDM0_AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM1_AWCFR: DFSDM analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM_DFSDM1_AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM_DFSDM1_AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM_DFSDM1_AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM_DFSDM1_AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM2_AWCFR: DFSDM analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM_DFSDM2_AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM_DFSDM2_AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM_DFSDM2_AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM_DFSDM2_AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM3_AWCFR: DFSDM analog watchdog clear flag register
	// Position of CLRAWLTF field.
	DFSDM_DFSDM3_AWCFR_CLRAWLTF_Pos = 0x0
	// Bit mask of CLRAWLTF field.
	DFSDM_DFSDM3_AWCFR_CLRAWLTF_Msk = 0xff
	// Position of CLRAWHTF field.
	DFSDM_DFSDM3_AWCFR_CLRAWHTF_Pos = 0x8
	// Bit mask of CLRAWHTF field.
	DFSDM_DFSDM3_AWCFR_CLRAWHTF_Msk = 0xff00

	// DFSDM0_EXMAX: DFSDM Extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM_DFSDM0_EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM_DFSDM0_EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM_DFSDM0_EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM_DFSDM0_EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM1_EXMAX: DFSDM Extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM_DFSDM1_EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM_DFSDM1_EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM_DFSDM1_EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM_DFSDM1_EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM2_EXMAX: DFSDM Extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM_DFSDM2_EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM_DFSDM2_EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM_DFSDM2_EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM_DFSDM2_EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM3_EXMAX: DFSDM Extremes detector maximum register
	// Position of EXMAXCH field.
	DFSDM_DFSDM3_EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM_DFSDM3_EXMAX_EXMAXCH_Msk = 0x7
	// Position of EXMAX field.
	DFSDM_DFSDM3_EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM_DFSDM3_EXMAX_EXMAX_Msk = 0xffffff00

	// DFSDM0_EXMIN: DFSDM Extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM_DFSDM0_EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM_DFSDM0_EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM_DFSDM0_EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM_DFSDM0_EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM1_EXMIN: DFSDM Extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM_DFSDM1_EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM_DFSDM1_EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM_DFSDM1_EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM_DFSDM1_EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM2_EXMIN: DFSDM Extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM_DFSDM2_EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM_DFSDM2_EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM_DFSDM2_EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM_DFSDM2_EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM3_EXMIN: DFSDM Extremes detector minimum register
	// Position of EXMINCH field.
	DFSDM_DFSDM3_EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM_DFSDM3_EXMIN_EXMINCH_Msk = 0x7
	// Position of EXMIN field.
	DFSDM_DFSDM3_EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM_DFSDM3_EXMIN_EXMIN_Msk = 0xffffff00

	// DFSDM0_CNVTIMR: DFSDM conversion timer register
	// Position of CNVCNT field.
	DFSDM_DFSDM0_CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM_DFSDM0_CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM1_CNVTIMR: DFSDM conversion timer register
	// Position of CNVCNT field.
	DFSDM_DFSDM1_CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM_DFSDM1_CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM2_CNVTIMR: DFSDM conversion timer register
	// Position of CNVCNT field.
	DFSDM_DFSDM2_CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM_DFSDM2_CNVTIMR_CNVCNT_Msk = 0xfffffff0

	// DFSDM3_CNVTIMR: DFSDM conversion timer register
	// Position of CNVCNT field.
	DFSDM_DFSDM3_CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM_DFSDM3_CNVTIMR_CNVCNT_Msk = 0xfffffff0
)

// Bitfields for TIM16: General-purpose-timers
const (
	// CR1: control register 1
	// Position of CEN field.
	TIMs_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIMs_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIMs_CR1_CEN = 0x1
	// Counter disabled
	TIMs_CR1_CEN_Disabled = 0x0
	// Counter enabled
	TIMs_CR1_CEN_Enabled = 0x1
	// Position of UDIS field.
	TIMs_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIMs_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIMs_CR1_UDIS = 0x2
	// Update event enabled
	TIMs_CR1_UDIS_Enabled = 0x0
	// Update event disabled
	TIMs_CR1_UDIS_Disabled = 0x1
	// Position of URS field.
	TIMs_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIMs_CR1_URS_Msk = 0x4
	// Bit URS.
	TIMs_CR1_URS = 0x4
	// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
	TIMs_CR1_URS_AnyEvent = 0x0
	// Only counter overflow/underflow generates an update interrupt or DMA request
	TIMs_CR1_URS_CounterOnly = 0x1
	// Position of OPM field.
	TIMs_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIMs_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIMs_CR1_OPM = 0x8
	// Not stopped at update event
	TIMs_CR1_OPM_NotStopped = 0x0
	// Counter stops counting at next update event
	TIMs_CR1_OPM_Stopped = 0x1
	// Position of ARPE field.
	TIMs_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIMs_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIMs_CR1_ARPE = 0x80
	// TIMx_APRR register is not buffered
	TIMs_CR1_ARPE_Disabled = 0x0
	// TIMx_APRR register is buffered
	TIMs_CR1_ARPE_Enabled = 0x1
	// Position of CKD field.
	TIMs_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIMs_CR1_CKD_Msk = 0x300
	// t_DTS = t_CK_INT
	TIMs_CR1_CKD_Div1 = 0x0
	// t_DTS = 2 × t_CK_INT
	TIMs_CR1_CKD_Div2 = 0x1
	// t_DTS = 4 × t_CK_INT
	TIMs_CR1_CKD_Div4 = 0x2
	// Position of UIFREMAP field.
	TIMs_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIMs_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIMs_CR1_UIFREMAP = 0x800

	// CR2: control register 2
	// Position of OIS1N field.
	TIMs_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIMs_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIMs_CR2_OIS1N = 0x200
	// OC1N=0 after a dead-time when MOE=0
	TIMs_CR2_OIS1N_Low = 0x0
	// OC1N=1 after a dead-time when MOE=0
	TIMs_CR2_OIS1N_High = 0x1
	// Position of OIS1 field.
	TIMs_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIMs_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIMs_CR2_OIS1 = 0x100
	// OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
	TIMs_CR2_OIS1_Low = 0x0
	// OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
	TIMs_CR2_OIS1_High = 0x1
	// Position of CCDS field.
	TIMs_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIMs_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIMs_CR2_CCDS = 0x8
	// CCx DMA request sent when CCx event occurs
	TIMs_CR2_CCDS_OnCompare = 0x0
	// CCx DMA request sent when update event occurs
	TIMs_CR2_CCDS_OnUpdate = 0x1
	// Position of CCUS field.
	TIMs_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIMs_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIMs_CR2_CCUS = 0x4
	// Capture/compare are updated only by setting the COMG bit
	TIMs_CR2_CCUS_Default = 0x0
	// Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI
	TIMs_CR2_CCUS_WithRisingEdge = 0x1
	// Position of CCPC field.
	TIMs_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIMs_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIMs_CR2_CCPC = 0x1
	// CCxE, CCxNE and OCxM bits are not preloaded
	TIMs_CR2_CCPC_NotPreloaded = 0x0
	// CCxE, CCxNE and OCxM bits are preloaded
	TIMs_CR2_CCPC_Preloaded = 0x1

	// DIER: DMA/Interrupt enable register
	// Position of UIE field.
	TIMs_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIMs_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIMs_DIER_UIE = 0x1
	// Update interrupt disabled
	TIMs_DIER_UIE_Disabled = 0x0
	// Update interrupt enabled
	TIMs_DIER_UIE_Enabled = 0x1
	// Position of CC1IE field.
	TIMs_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIMs_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIMs_DIER_CC1IE = 0x2
	// CC1 interrupt disabled
	TIMs_DIER_CC1IE_Disabled = 0x0
	// CC1 interrupt enabled
	TIMs_DIER_CC1IE_Enabled = 0x1
	// Position of COMIE field.
	TIMs_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIMs_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIMs_DIER_COMIE = 0x20
	// COM interrupt disabled
	TIMs_DIER_COMIE_Disabled = 0x0
	// COM interrupt enabled
	TIMs_DIER_COMIE_Enabled = 0x1
	// Position of BIE field.
	TIMs_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIMs_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIMs_DIER_BIE = 0x80
	// Break interrupt disabled
	TIMs_DIER_BIE_Disabled = 0x0
	// Break interrupt enabled
	TIMs_DIER_BIE_Enabled = 0x1
	// Position of UDE field.
	TIMs_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIMs_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIMs_DIER_UDE = 0x100
	// Position of CC1DE field.
	TIMs_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIMs_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIMs_DIER_CC1DE = 0x200
	// CC1 DMA request disabled
	TIMs_DIER_CC1DE_Disabled = 0x0
	// CC1 DMA request enabled
	TIMs_DIER_CC1DE_Enabled = 0x1
	// Position of COMDE field.
	TIMs_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIMs_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIMs_DIER_COMDE = 0x2000

	// SR: status register
	// Position of CC1OF field.
	TIMs_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIMs_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIMs_SR_CC1OF = 0x200
	// Position of BIF field.
	TIMs_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIMs_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIMs_SR_BIF = 0x80
	// Position of COMIF field.
	TIMs_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIMs_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIMs_SR_COMIF = 0x20
	// Position of CC1IF field.
	TIMs_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIMs_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIMs_SR_CC1IF = 0x2
	// Position of UIF field.
	TIMs_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIMs_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIMs_SR_UIF = 0x1
	// No update occurred
	TIMs_SR_UIF_Clear = 0x0
	// Update interrupt pending.
	TIMs_SR_UIF_UpdatePending = 0x1

	// EGR: event generation register
	// Position of BG field.
	TIMs_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIMs_EGR_BG_Msk = 0x80
	// Bit BG.
	TIMs_EGR_BG = 0x80
	// Position of COMG field.
	TIMs_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIMs_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIMs_EGR_COMG = 0x20
	// Position of CC1G field.
	TIMs_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIMs_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIMs_EGR_CC1G = 0x2
	// Position of UG field.
	TIMs_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIMs_EGR_UG_Msk = 0x1
	// Bit UG.
	TIMs_EGR_UG = 0x1
	// Re-initializes the timer counter and generates an update of the registers.
	TIMs_EGR_UG_Update = 0x1

	// CCMR1_Output: capture/compare mode register (output mode)
	// Position of CC1S field.
	TIMs_CCMR1_Output_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIMs_CCMR1_Output_CC1S_Msk = 0x3
	// CC1 channel is configured as output
	TIMs_CCMR1_Output_CC1S_Output = 0x0
	// Position of OC1FE field.
	TIMs_CCMR1_Output_OC1FE_Pos = 0x2
	// Bit mask of OC1FE field.
	TIMs_CCMR1_Output_OC1FE_Msk = 0x4
	// Bit OC1FE.
	TIMs_CCMR1_Output_OC1FE = 0x4
	// Position of OC1PE field.
	TIMs_CCMR1_Output_OC1PE_Pos = 0x3
	// Bit mask of OC1PE field.
	TIMs_CCMR1_Output_OC1PE_Msk = 0x8
	// Bit OC1PE.
	TIMs_CCMR1_Output_OC1PE = 0x8
	// Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
	TIMs_CCMR1_Output_OC1PE_Disabled = 0x0
	// Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
	TIMs_CCMR1_Output_OC1PE_Enabled = 0x1
	// Position of OC1M field.
	TIMs_CCMR1_Output_OC1M_Pos = 0x4
	// Bit mask of OC1M field.
	TIMs_CCMR1_Output_OC1M_Msk = 0x70
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
	TIMs_CCMR1_Output_OC1M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
	TIMs_CCMR1_Output_OC1M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
	TIMs_CCMR1_Output_OC1M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy
	TIMs_CCMR1_Output_OC1M_Toggle = 0x3
	// OCyREF is forced low
	TIMs_CCMR1_Output_OC1M_ForceInactive = 0x4
	// OCyREF is forced high
	TIMs_CCMR1_Output_OC1M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
	TIMs_CCMR1_Output_OC1M_PwmMode1 = 0x6
	// Inversely to PwmMode1
	TIMs_CCMR1_Output_OC1M_PwmMode2 = 0x7
	// Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIMs_CCMR1_Output_OC1M_OpmMode1 = 0x8
	// Inversely to OpmMode1
	TIMs_CCMR1_Output_OC1M_OpmMode2 = 0x9
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIMs_CCMR1_Output_OC1M_CombinedPwmMode1 = 0xc
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIMs_CCMR1_Output_OC1M_CombinedPwmMode2 = 0xd
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIMs_CCMR1_Output_OC1M_AsymmetricPwmMode1 = 0xe
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIMs_CCMR1_Output_OC1M_AsymmetricPwmMode2 = 0xf
	// Position of OC1M_3 field.
	TIMs_CCMR1_Output_OC1M_3_Pos = 0x10
	// Bit mask of OC1M_3 field.
	TIMs_CCMR1_Output_OC1M_3_Msk = 0x10000
	// Bit OC1M_3.
	TIMs_CCMR1_Output_OC1M_3 = 0x10000

	// CCMR1_Input: capture/compare mode register 1 (input mode)
	// Position of IC1F field.
	TIMs_CCMR1_Input_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIMs_CCMR1_Input_IC1F_Msk = 0xf0
	// No filter, sampling is done at fDTS
	TIMs_CCMR1_Input_IC1F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIMs_CCMR1_Input_IC1F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIMs_CCMR1_Input_IC1F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIMs_CCMR1_Input_IC1F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIMs_CCMR1_Input_IC1F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIMs_CCMR1_Input_IC1F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIMs_CCMR1_Input_IC1F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIMs_CCMR1_Input_IC1F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIMs_CCMR1_Input_IC1F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIMs_CCMR1_Input_IC1F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIMs_CCMR1_Input_IC1F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIMs_CCMR1_Input_IC1F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIMs_CCMR1_Input_IC1F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIMs_CCMR1_Input_IC1F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIMs_CCMR1_Input_IC1F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIMs_CCMR1_Input_IC1F_FDTS_Div32_N8 = 0xf
	// Position of IC1PSC field.
	TIMs_CCMR1_Input_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIMs_CCMR1_Input_IC1PSC_Msk = 0xc
	// Position of CC1S field.
	TIMs_CCMR1_Input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIMs_CCMR1_Input_CC1S_Msk = 0x3
	// CC1 channel is configured as input, IC1 is mapped on TI1
	TIMs_CCMR1_Input_CC1S_TI1 = 0x1
	// CC1 channel is configured as input, IC1 is mapped on TI2
	TIMs_CCMR1_Input_CC1S_TI2 = 0x2
	// CC1 channel is configured as input, IC1 is mapped on TRC
	TIMs_CCMR1_Input_CC1S_TRC = 0x3

	// CCER: capture/compare enable register
	// Position of CC1NP field.
	TIMs_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIMs_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIMs_CCER_CC1NP = 0x8
	// Position of CC1NE field.
	TIMs_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIMs_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIMs_CCER_CC1NE = 0x4
	// Position of CC1P field.
	TIMs_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIMs_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIMs_CCER_CC1P = 0x2
	// Position of CC1E field.
	TIMs_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIMs_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIMs_CCER_CC1E = 0x1

	// CNT: counter
	// Position of CNT field.
	TIMs_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIMs_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIMs_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIMs_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIMs_CNT_UIFCPY = 0x80000000

	// PSC: prescaler
	// Position of PSC field.
	TIMs_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIMs_PSC_PSC_Msk = 0xffff

	// ARR: auto-reload register
	// Position of ARR field.
	TIMs_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIMs_ARR_ARR_Msk = 0xffff

	// RCR: repetition counter register
	// Position of REP field.
	TIMs_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIMs_RCR_REP_Msk = 0xff

	// CCR1: capture/compare register 1
	// Position of CCR field.
	TIMs_CCR1_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIMs_CCR1_CCR_Msk = 0xffff

	// BDTR: break and dead-time register
	// Position of DTG field.
	TIMs_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIMs_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIMs_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIMs_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIMs_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIMs_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIMs_BDTR_OSSI = 0x400
	// Position of OSSR field.
	TIMs_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIMs_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIMs_BDTR_OSSR = 0x800
	// Position of BKE field.
	TIMs_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIMs_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIMs_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIMs_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIMs_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIMs_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIMs_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIMs_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIMs_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIMs_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIMs_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIMs_BDTR_MOE = 0x8000
	// Position of BKF field.
	TIMs_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIMs_BDTR_BKF_Msk = 0xf0000

	// DCR: DMA control register
	// Position of DBL field.
	TIMs_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIMs_DCR_DBL_Msk = 0x1f00
	// Position of DBA field.
	TIMs_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIMs_DCR_DBA_Msk = 0x1f

	// DMAR: DMA address for full transfer
	// Position of DMAB field.
	TIMs_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIMs_DMAR_DMAB_Msk = 0xffff

	// TIM16_AF1: TIM16 alternate function register 1
	// Position of BKINE field.
	TIMs_TIM16_AF1_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIMs_TIM16_AF1_BKINE_Msk = 0x1
	// Bit BKINE.
	TIMs_TIM16_AF1_BKINE = 0x1
	// Position of BKCMP1E field.
	TIMs_TIM16_AF1_BKCMP1E_Pos = 0x1
	// Bit mask of BKCMP1E field.
	TIMs_TIM16_AF1_BKCMP1E_Msk = 0x2
	// Bit BKCMP1E.
	TIMs_TIM16_AF1_BKCMP1E = 0x2
	// Position of BKCMP2E field.
	TIMs_TIM16_AF1_BKCMP2E_Pos = 0x2
	// Bit mask of BKCMP2E field.
	TIMs_TIM16_AF1_BKCMP2E_Msk = 0x4
	// Bit BKCMP2E.
	TIMs_TIM16_AF1_BKCMP2E = 0x4
	// Position of BKDFBK1E field.
	TIMs_TIM16_AF1_BKDFBK1E_Pos = 0x8
	// Bit mask of BKDFBK1E field.
	TIMs_TIM16_AF1_BKDFBK1E_Msk = 0x100
	// Bit BKDFBK1E.
	TIMs_TIM16_AF1_BKDFBK1E = 0x100
	// Position of BKINP field.
	TIMs_TIM16_AF1_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIMs_TIM16_AF1_BKINP_Msk = 0x200
	// Bit BKINP.
	TIMs_TIM16_AF1_BKINP = 0x200
	// Position of BKCMP1P field.
	TIMs_TIM16_AF1_BKCMP1P_Pos = 0xa
	// Bit mask of BKCMP1P field.
	TIMs_TIM16_AF1_BKCMP1P_Msk = 0x400
	// Bit BKCMP1P.
	TIMs_TIM16_AF1_BKCMP1P = 0x400
	// Position of BKCMP2P field.
	TIMs_TIM16_AF1_BKCMP2P_Pos = 0xb
	// Bit mask of BKCMP2P field.
	TIMs_TIM16_AF1_BKCMP2P_Msk = 0x800
	// Bit BKCMP2P.
	TIMs_TIM16_AF1_BKCMP2P = 0x800

	// TIM16_TISEL: TIM16 input selection register
	// Position of TI1SEL field.
	TIMs_TIM16_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIMs_TIM16_TISEL_TI1SEL_Msk = 0xf
)

// Bitfields for USART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	// Position of RXFFIE field.
	USART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	USART_CR1_RXFFIE = 0x80000000
	// Position of TXFEIE field.
	USART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	USART_CR1_TXFEIE = 0x40000000
	// Position of FIFOEN field.
	USART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	USART_CR1_FIFOEN = 0x20000000
	// Position of M1 field.
	USART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	USART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	USART_CR1_M1 = 0x10000000
	// Use M0 to set the data bits
	USART_CR1_M1_M0 = 0x0
	// 1 start bit, 7 data bits, n stop bits
	USART_CR1_M1_Bit7 = 0x1
	// Position of EOBIE field.
	USART_CR1_EOBIE_Pos = 0x1b
	// Bit mask of EOBIE field.
	USART_CR1_EOBIE_Msk = 0x8000000
	// Bit EOBIE.
	USART_CR1_EOBIE = 0x8000000
	// Interrupt is inhibited
	USART_CR1_EOBIE_Disabled = 0x0
	// A USART interrupt is generated when the EOBF flag is set in the ISR register
	USART_CR1_EOBIE_Enabled = 0x1
	// Position of RTOIE field.
	USART_CR1_RTOIE_Pos = 0x1a
	// Bit mask of RTOIE field.
	USART_CR1_RTOIE_Msk = 0x4000000
	// Bit RTOIE.
	USART_CR1_RTOIE = 0x4000000
	// Interrupt is inhibited
	USART_CR1_RTOIE_Disabled = 0x0
	// An USART interrupt is generated when the RTOF bit is set in the ISR register
	USART_CR1_RTOIE_Enabled = 0x1
	// Position of OVER8 field.
	USART_CR1_OVER8_Pos = 0xf
	// Bit mask of OVER8 field.
	USART_CR1_OVER8_Msk = 0x8000
	// Bit OVER8.
	USART_CR1_OVER8 = 0x8000
	// Oversampling by 16
	USART_CR1_OVER8_Oversampling16 = 0x0
	// Oversampling by 8
	USART_CR1_OVER8_Oversampling8 = 0x1
	// Position of CMIE field.
	USART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	USART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	USART_CR1_CMIE = 0x4000
	// Interrupt is disabled
	USART_CR1_CMIE_Disabled = 0x0
	// Interrupt is generated when the CMF bit is set in the ISR register
	USART_CR1_CMIE_Enabled = 0x1
	// Position of MME field.
	USART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	USART_CR1_MME_Msk = 0x2000
	// Bit MME.
	USART_CR1_MME = 0x2000
	// Receiver in active mode permanently
	USART_CR1_MME_Disabled = 0x0
	// Receiver can switch between mute mode and active mode
	USART_CR1_MME_Enabled = 0x1
	// Position of M0 field.
	USART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	USART_CR1_M0_Msk = 0x1000
	// Bit M0.
	USART_CR1_M0 = 0x1000
	// 1 start bit, 8 data bits, n stop bits
	USART_CR1_M0_Bit8 = 0x0
	// 1 start bit, 9 data bits, n stop bits
	USART_CR1_M0_Bit9 = 0x1
	// Position of WAKE field.
	USART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	USART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	USART_CR1_WAKE = 0x800
	// Idle line
	USART_CR1_WAKE_Idle = 0x0
	// Address mask
	USART_CR1_WAKE_Address = 0x1
	// Position of PCE field.
	USART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	USART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	USART_CR1_PCE = 0x400
	// Parity control disabled
	USART_CR1_PCE_Disabled = 0x0
	// Parity control enabled
	USART_CR1_PCE_Enabled = 0x1
	// Position of PS field.
	USART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	USART_CR1_PS_Msk = 0x200
	// Bit PS.
	USART_CR1_PS = 0x200
	// Even parity
	USART_CR1_PS_Even = 0x0
	// Odd parity
	USART_CR1_PS_Odd = 0x1
	// Position of PEIE field.
	USART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	USART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	USART_CR1_PEIE = 0x100
	// Interrupt is disabled
	USART_CR1_PEIE_Disabled = 0x0
	// Interrupt is generated whenever PE=1 in the ISR register
	USART_CR1_PEIE_Enabled = 0x1
	// Position of TXEIE field.
	USART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	USART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	USART_CR1_TXEIE = 0x80
	// Interrupt is disabled
	USART_CR1_TXEIE_Disabled = 0x0
	// Interrupt is generated whenever TXE=1 in the ISR register
	USART_CR1_TXEIE_Enabled = 0x1
	// Position of TCIE field.
	USART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	USART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	USART_CR1_TCIE = 0x40
	// Interrupt is disabled
	USART_CR1_TCIE_Disabled = 0x0
	// Interrupt is generated whenever TC=1 in the ISR register
	USART_CR1_TCIE_Enabled = 0x1
	// Position of RXNEIE field.
	USART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	USART_CR1_RXNEIE = 0x20
	// Interrupt is disabled
	USART_CR1_RXNEIE_Disabled = 0x0
	// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
	USART_CR1_RXNEIE_Enabled = 0x1
	// Position of IDLEIE field.
	USART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	USART_CR1_IDLEIE = 0x10
	// Interrupt is disabled
	USART_CR1_IDLEIE_Disabled = 0x0
	// Interrupt is generated whenever IDLE=1 in the ISR register
	USART_CR1_IDLEIE_Enabled = 0x1
	// Position of TE field.
	USART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	USART_CR1_TE_Msk = 0x8
	// Bit TE.
	USART_CR1_TE = 0x8
	// Transmitter is disabled
	USART_CR1_TE_Disabled = 0x0
	// Transmitter is enabled
	USART_CR1_TE_Enabled = 0x1
	// Position of RE field.
	USART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	USART_CR1_RE_Msk = 0x4
	// Bit RE.
	USART_CR1_RE = 0x4
	// Receiver is disabled
	USART_CR1_RE_Disabled = 0x0
	// Receiver is enabled
	USART_CR1_RE_Enabled = 0x1
	// Position of UESM field.
	USART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	USART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	USART_CR1_UESM = 0x2
	// USART not able to wake up the MCU from Stop mode
	USART_CR1_UESM_Disabled = 0x0
	// USART able to wake up the MCU from Stop mode
	USART_CR1_UESM_Enabled = 0x1
	// Position of UE field.
	USART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	USART_CR1_UE_Msk = 0x1
	// Bit UE.
	USART_CR1_UE = 0x1
	// UART is disabled
	USART_CR1_UE_Disabled = 0x0
	// UART is enabled
	USART_CR1_UE_Enabled = 0x1
	// Position of DEAT field.
	USART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	USART_CR1_DEAT_Msk = 0x3e00000
	// Position of DEDT field.
	USART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	USART_CR1_DEDT_Msk = 0x1f0000

	// CR2: Control register 2
	// Position of RTOEN field.
	USART_CR2_RTOEN_Pos = 0x17
	// Bit mask of RTOEN field.
	USART_CR2_RTOEN_Msk = 0x800000
	// Bit RTOEN.
	USART_CR2_RTOEN = 0x800000
	// Receiver timeout feature disabled
	USART_CR2_RTOEN_Disabled = 0x0
	// Receiver timeout feature enabled
	USART_CR2_RTOEN_Enabled = 0x1
	// Position of ABREN field.
	USART_CR2_ABREN_Pos = 0x14
	// Bit mask of ABREN field.
	USART_CR2_ABREN_Msk = 0x100000
	// Bit ABREN.
	USART_CR2_ABREN = 0x100000
	// Auto baud rate detection is disabled
	USART_CR2_ABREN_Disabled = 0x0
	// Auto baud rate detection is enabled
	USART_CR2_ABREN_Enabled = 0x1
	// Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	USART_CR2_MSBFIRST = 0x80000
	// data is transmitted/received with data bit 0 first, following the start bit
	USART_CR2_MSBFIRST_LSB = 0x0
	// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
	USART_CR2_MSBFIRST_MSB = 0x1
	// Position of DATAINV field.
	USART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	USART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	USART_CR2_DATAINV = 0x40000
	// Logical data from the data register are send/received in positive/direct logic
	USART_CR2_DATAINV_Positive = 0x0
	// Logical data from the data register are send/received in negative/inverse logic
	USART_CR2_DATAINV_Negative = 0x1
	// Position of TXINV field.
	USART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	USART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	USART_CR2_TXINV = 0x20000
	// TX pin signal works using the standard logic levels
	USART_CR2_TXINV_Standard = 0x0
	// TX pin signal values are inverted
	USART_CR2_TXINV_Inverted = 0x1
	// Position of RXINV field.
	USART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	USART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	USART_CR2_RXINV = 0x10000
	// RX pin signal works using the standard logic levels
	USART_CR2_RXINV_Standard = 0x0
	// RX pin signal values are inverted
	USART_CR2_RXINV_Inverted = 0x1
	// Position of SWAP field.
	USART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	USART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	USART_CR2_SWAP = 0x8000
	// TX/RX pins are used as defined in standard pinout
	USART_CR2_SWAP_Standard = 0x0
	// The TX and RX pins functions are swapped
	USART_CR2_SWAP_Swapped = 0x1
	// Position of LINEN field.
	USART_CR2_LINEN_Pos = 0xe
	// Bit mask of LINEN field.
	USART_CR2_LINEN_Msk = 0x4000
	// Bit LINEN.
	USART_CR2_LINEN = 0x4000
	// LIN mode disabled
	USART_CR2_LINEN_Disabled = 0x0
	// LIN mode enabled
	USART_CR2_LINEN_Enabled = 0x1
	// Position of STOP field.
	USART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	USART_CR2_STOP_Msk = 0x3000
	// 1 stop bit
	USART_CR2_STOP_Stop1 = 0x0
	// 0.5 stop bit
	USART_CR2_STOP_Stop0p5 = 0x1
	// 2 stop bit
	USART_CR2_STOP_Stop2 = 0x2
	// 1.5 stop bit
	USART_CR2_STOP_Stop1p5 = 0x3
	// Position of CLKEN field.
	USART_CR2_CLKEN_Pos = 0xb
	// Bit mask of CLKEN field.
	USART_CR2_CLKEN_Msk = 0x800
	// Bit CLKEN.
	USART_CR2_CLKEN = 0x800
	// CK pin disabled
	USART_CR2_CLKEN_Disabled = 0x0
	// CK pin enabled
	USART_CR2_CLKEN_Enabled = 0x1
	// Position of CPOL field.
	USART_CR2_CPOL_Pos = 0xa
	// Bit mask of CPOL field.
	USART_CR2_CPOL_Msk = 0x400
	// Bit CPOL.
	USART_CR2_CPOL = 0x400
	// Steady low value on CK pin outside transmission window
	USART_CR2_CPOL_Low = 0x0
	// Steady high value on CK pin outside transmission window
	USART_CR2_CPOL_High = 0x1
	// Position of CPHA field.
	USART_CR2_CPHA_Pos = 0x9
	// Bit mask of CPHA field.
	USART_CR2_CPHA_Msk = 0x200
	// Bit CPHA.
	USART_CR2_CPHA = 0x200
	// The first clock transition is the first data capture edge
	USART_CR2_CPHA_First = 0x0
	// The second clock transition is the first data capture edge
	USART_CR2_CPHA_Second = 0x1
	// Position of LBCL field.
	USART_CR2_LBCL_Pos = 0x8
	// Bit mask of LBCL field.
	USART_CR2_LBCL_Msk = 0x100
	// Bit LBCL.
	USART_CR2_LBCL = 0x100
	// The clock pulse of the last data bit is not output to the CK pin
	USART_CR2_LBCL_NotOutput = 0x0
	// The clock pulse of the last data bit is output to the CK pin
	USART_CR2_LBCL_Output = 0x1
	// Position of LBDIE field.
	USART_CR2_LBDIE_Pos = 0x6
	// Bit mask of LBDIE field.
	USART_CR2_LBDIE_Msk = 0x40
	// Bit LBDIE.
	USART_CR2_LBDIE = 0x40
	// Interrupt is inhibited
	USART_CR2_LBDIE_Disabled = 0x0
	// An interrupt is generated whenever LBDF=1 in the ISR register
	USART_CR2_LBDIE_Enabled = 0x1
	// Position of LBDL field.
	USART_CR2_LBDL_Pos = 0x5
	// Bit mask of LBDL field.
	USART_CR2_LBDL_Msk = 0x20
	// Bit LBDL.
	USART_CR2_LBDL = 0x20
	// 10-bit break detection
	USART_CR2_LBDL_Bit10 = 0x0
	// 11-bit break detection
	USART_CR2_LBDL_Bit11 = 0x1
	// Position of ADDM7 field.
	USART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	USART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	USART_CR2_ADDM7 = 0x10
	// 4-bit address detection
	USART_CR2_ADDM7_Bit4 = 0x0
	// 7-bit address detection
	USART_CR2_ADDM7_Bit7 = 0x1
	// Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Pos = 0x3
	// Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk = 0x8
	// Bit DIS_NSS.
	USART_CR2_DIS_NSS = 0x8
	// Position of SLVEN field.
	USART_CR2_SLVEN_Pos = 0x0
	// Bit mask of SLVEN field.
	USART_CR2_SLVEN_Msk = 0x1
	// Bit SLVEN.
	USART_CR2_SLVEN = 0x1
	// Position of ABRMOD field.
	USART_CR2_ABRMOD_Pos = 0x15
	// Bit mask of ABRMOD field.
	USART_CR2_ABRMOD_Msk = 0x600000
	// Measurement of the start bit is used to detect the baud rate
	USART_CR2_ABRMOD_Start = 0x0
	// Falling edge to falling edge measurement
	USART_CR2_ABRMOD_Edge = 0x1
	// 0x7F frame detection
	USART_CR2_ABRMOD_Frame7F = 0x2
	// 0x55 frame detection
	USART_CR2_ABRMOD_Frame55 = 0x3
	// Position of ADD field.
	USART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	USART_CR2_ADD_Msk = 0xff000000

	// CR3: Control register 3
	// Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000
	// Position of RXFTIE field.
	USART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	USART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	USART_CR3_RXFTIE = 0x10000000
	// Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000
	// Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Pos = 0x18
	// Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000
	// Bit TCBGTIE.
	USART_CR3_TCBGTIE = 0x1000000
	// Position of TXFTIE field.
	USART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	USART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	USART_CR3_TXFTIE = 0x800000
	// Position of WUFIE field.
	USART_CR3_WUFIE_Pos = 0x16
	// Bit mask of WUFIE field.
	USART_CR3_WUFIE_Msk = 0x400000
	// Bit WUFIE.
	USART_CR3_WUFIE = 0x400000
	// Interrupt is inhibited
	USART_CR3_WUFIE_Disabled = 0x0
	// An USART interrupt is generated whenever WUF=1 in the ISR register
	USART_CR3_WUFIE_Enabled = 0x1
	// Position of WUS field.
	USART_CR3_WUS_Pos = 0x14
	// Bit mask of WUS field.
	USART_CR3_WUS_Msk = 0x300000
	// WUF active on address match
	USART_CR3_WUS_Address = 0x0
	// WuF active on Start bit detection
	USART_CR3_WUS_Start = 0x2
	// WUF active on RXNE
	USART_CR3_WUS_RXNE = 0x3
	// Position of SCARCNT field.
	USART_CR3_SCARCNT_Pos = 0x11
	// Bit mask of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000
	// Position of DEP field.
	USART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	USART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	USART_CR3_DEP = 0x8000
	// DE signal is active high
	USART_CR3_DEP_High = 0x0
	// DE signal is active low
	USART_CR3_DEP_Low = 0x1
	// Position of DEM field.
	USART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	USART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	USART_CR3_DEM = 0x4000
	// DE function is disabled
	USART_CR3_DEM_Disabled = 0x0
	// The DE signal is output on the RTS pin
	USART_CR3_DEM_Enabled = 0x1
	// Position of DDRE field.
	USART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	USART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	USART_CR3_DDRE = 0x2000
	// DMA is not disabled in case of reception error
	USART_CR3_DDRE_NotDisabled = 0x0
	// DMA is disabled following a reception error
	USART_CR3_DDRE_Disabled = 0x1
	// Position of OVRDIS field.
	USART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	USART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	USART_CR3_OVRDIS = 0x1000
	// Overrun Error Flag, ORE, is set when received data is not read before receiving new data
	USART_CR3_OVRDIS_Enabled = 0x0
	// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
	USART_CR3_OVRDIS_Disabled = 0x1
	// Position of ONEBIT field.
	USART_CR3_ONEBIT_Pos = 0xb
	// Bit mask of ONEBIT field.
	USART_CR3_ONEBIT_Msk = 0x800
	// Bit ONEBIT.
	USART_CR3_ONEBIT = 0x800
	// Three sample bit method
	USART_CR3_ONEBIT_Sample3 = 0x0
	// One sample bit method
	USART_CR3_ONEBIT_Sample1 = 0x1
	// Position of CTSIE field.
	USART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	USART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	USART_CR3_CTSIE = 0x400
	// Interrupt is inhibited
	USART_CR3_CTSIE_Disabled = 0x0
	// An interrupt is generated whenever CTSIF=1 in the ISR register
	USART_CR3_CTSIE_Enabled = 0x1
	// Position of CTSE field.
	USART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	USART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	USART_CR3_CTSE = 0x200
	// CTS hardware flow control disabled
	USART_CR3_CTSE_Disabled = 0x0
	// CTS mode enabled, data is only transmitted when the CTS input is asserted
	USART_CR3_CTSE_Enabled = 0x1
	// Position of RTSE field.
	USART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	USART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	USART_CR3_RTSE = 0x100
	// RTS hardware flow control disabled
	USART_CR3_RTSE_Disabled = 0x0
	// RTS output enabled, data is only requested when there is space in the receive buffer
	USART_CR3_RTSE_Enabled = 0x1
	// Position of DMAT field.
	USART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	USART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	USART_CR3_DMAT = 0x80
	// DMA mode is disabled for transmission
	USART_CR3_DMAT_Disabled = 0x0
	// DMA mode is enabled for transmission
	USART_CR3_DMAT_Enabled = 0x1
	// Position of DMAR field.
	USART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	USART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	USART_CR3_DMAR = 0x40
	// DMA mode is disabled for reception
	USART_CR3_DMAR_Disabled = 0x0
	// DMA mode is enabled for reception
	USART_CR3_DMAR_Enabled = 0x1
	// Position of SCEN field.
	USART_CR3_SCEN_Pos = 0x5
	// Bit mask of SCEN field.
	USART_CR3_SCEN_Msk = 0x20
	// Bit SCEN.
	USART_CR3_SCEN = 0x20
	// Smartcard Mode disabled
	USART_CR3_SCEN_Disabled = 0x0
	// Smartcard Mode enabled
	USART_CR3_SCEN_Enabled = 0x1
	// Position of NACK field.
	USART_CR3_NACK_Pos = 0x4
	// Bit mask of NACK field.
	USART_CR3_NACK_Msk = 0x10
	// Bit NACK.
	USART_CR3_NACK = 0x10
	// NACK transmission in case of parity error is disabled
	USART_CR3_NACK_Disabled = 0x0
	// NACK transmission during parity error is enabled
	USART_CR3_NACK_Enabled = 0x1
	// Position of HDSEL field.
	USART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	USART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	USART_CR3_HDSEL = 0x8
	// Half duplex mode is not selected
	USART_CR3_HDSEL_NotSelected = 0x0
	// Half duplex mode is selected
	USART_CR3_HDSEL_Selected = 0x1
	// Position of IRLP field.
	USART_CR3_IRLP_Pos = 0x2
	// Bit mask of IRLP field.
	USART_CR3_IRLP_Msk = 0x4
	// Bit IRLP.
	USART_CR3_IRLP = 0x4
	// Normal mode
	USART_CR3_IRLP_Normal = 0x0
	// Low-power mode
	USART_CR3_IRLP_LowPower = 0x1
	// Position of IREN field.
	USART_CR3_IREN_Pos = 0x1
	// Bit mask of IREN field.
	USART_CR3_IREN_Msk = 0x2
	// Bit IREN.
	USART_CR3_IREN = 0x2
	// IrDA disabled
	USART_CR3_IREN_Disabled = 0x0
	// IrDA enabled
	USART_CR3_IREN_Enabled = 0x1
	// Position of EIE field.
	USART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	USART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	USART_CR3_EIE = 0x1
	// Interrupt is inhibited
	USART_CR3_EIE_Disabled = 0x0
	// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
	USART_CR3_EIE_Enabled = 0x1

	// BRR: Baud rate register
	// Position of BRR field.
	USART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	USART_BRR_BRR_Msk = 0xffff

	// GTPR: Guard time and prescaler register
	// Position of GT field.
	USART_GTPR_GT_Pos = 0x8
	// Bit mask of GT field.
	USART_GTPR_GT_Msk = 0xff00
	// Position of PSC field.
	USART_GTPR_PSC_Pos = 0x0
	// Bit mask of PSC field.
	USART_GTPR_PSC_Msk = 0xff

	// RTOR: Receiver timeout register
	// Position of BLEN field.
	USART_RTOR_BLEN_Pos = 0x18
	// Bit mask of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000
	// Position of RTO field.
	USART_RTOR_RTO_Pos = 0x0
	// Bit mask of RTO field.
	USART_RTOR_RTO_Msk = 0xffffff

	// RQR: Request register
	// Position of TXFRQ field.
	USART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	USART_RQR_TXFRQ = 0x10
	// Set the TXE flags. This allows to discard the transmit data
	USART_RQR_TXFRQ_Discard = 0x1
	// Position of RXFRQ field.
	USART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	USART_RQR_RXFRQ = 0x8
	// clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
	USART_RQR_RXFRQ_Discard = 0x1
	// Position of MMRQ field.
	USART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	USART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	USART_RQR_MMRQ = 0x4
	// Puts the USART in mute mode and sets the RWU flag
	USART_RQR_MMRQ_Mute = 0x1
	// Position of SBKRQ field.
	USART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	USART_RQR_SBKRQ = 0x2
	// sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
	USART_RQR_SBKRQ_Break = 0x1
	// Position of ABRRQ field.
	USART_RQR_ABRRQ_Pos = 0x0
	// Bit mask of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1
	// Bit ABRRQ.
	USART_RQR_ABRRQ = 0x1
	// resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
	USART_RQR_ABRRQ_Request = 0x1

	// ISR: Interrupt & status register
	// Position of TXFT field.
	USART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	USART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	USART_ISR_TXFT = 0x8000000
	// Position of RXFT field.
	USART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	USART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	USART_ISR_RXFT = 0x4000000
	// Position of TCBGT field.
	USART_ISR_TCBGT_Pos = 0x19
	// Bit mask of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000
	// Bit TCBGT.
	USART_ISR_TCBGT = 0x2000000
	// Position of RXFF field.
	USART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	USART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	USART_ISR_RXFF = 0x1000000
	// Position of TXFE field.
	USART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	USART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	USART_ISR_TXFE = 0x800000
	// Position of REACK field.
	USART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	USART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	USART_ISR_REACK = 0x400000
	// Position of TEACK field.
	USART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	USART_ISR_TEACK = 0x200000
	// Position of WUF field.
	USART_ISR_WUF_Pos = 0x14
	// Bit mask of WUF field.
	USART_ISR_WUF_Msk = 0x100000
	// Bit WUF.
	USART_ISR_WUF = 0x100000
	// Position of RWU field.
	USART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	USART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	USART_ISR_RWU = 0x80000
	// Position of SBKF field.
	USART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	USART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	USART_ISR_SBKF = 0x40000
	// Position of CMF field.
	USART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	USART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	USART_ISR_CMF = 0x20000
	// Position of BUSY field.
	USART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	USART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	USART_ISR_BUSY = 0x10000
	// Position of ABRF field.
	USART_ISR_ABRF_Pos = 0xf
	// Bit mask of ABRF field.
	USART_ISR_ABRF_Msk = 0x8000
	// Bit ABRF.
	USART_ISR_ABRF = 0x8000
	// Position of ABRE field.
	USART_ISR_ABRE_Pos = 0xe
	// Bit mask of ABRE field.
	USART_ISR_ABRE_Msk = 0x4000
	// Bit ABRE.
	USART_ISR_ABRE = 0x4000
	// Position of UDR field.
	USART_ISR_UDR_Pos = 0xd
	// Bit mask of UDR field.
	USART_ISR_UDR_Msk = 0x2000
	// Bit UDR.
	USART_ISR_UDR = 0x2000
	// Position of EOBF field.
	USART_ISR_EOBF_Pos = 0xc
	// Bit mask of EOBF field.
	USART_ISR_EOBF_Msk = 0x1000
	// Bit EOBF.
	USART_ISR_EOBF = 0x1000
	// Position of RTOF field.
	USART_ISR_RTOF_Pos = 0xb
	// Bit mask of RTOF field.
	USART_ISR_RTOF_Msk = 0x800
	// Bit RTOF.
	USART_ISR_RTOF = 0x800
	// Position of CTS field.
	USART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	USART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	USART_ISR_CTS = 0x400
	// Position of CTSIF field.
	USART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	USART_ISR_CTSIF = 0x200
	// Position of LBDF field.
	USART_ISR_LBDF_Pos = 0x8
	// Bit mask of LBDF field.
	USART_ISR_LBDF_Msk = 0x100
	// Bit LBDF.
	USART_ISR_LBDF = 0x100
	// Position of TXE field.
	USART_ISR_TXE_Pos = 0x7
	// Bit mask of TXE field.
	USART_ISR_TXE_Msk = 0x80
	// Bit TXE.
	USART_ISR_TXE = 0x80
	// Position of TC field.
	USART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	USART_ISR_TC_Msk = 0x40
	// Bit TC.
	USART_ISR_TC = 0x40
	// Position of RXNE field.
	USART_ISR_RXNE_Pos = 0x5
	// Bit mask of RXNE field.
	USART_ISR_RXNE_Msk = 0x20
	// Bit RXNE.
	USART_ISR_RXNE = 0x20
	// Position of IDLE field.
	USART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	USART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	USART_ISR_IDLE = 0x10
	// Position of ORE field.
	USART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	USART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	USART_ISR_ORE = 0x8
	// Position of NF field.
	USART_ISR_NF_Pos = 0x2
	// Bit mask of NF field.
	USART_ISR_NF_Msk = 0x4
	// Bit NF.
	USART_ISR_NF = 0x4
	// Position of FE field.
	USART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	USART_ISR_FE_Msk = 0x2
	// Bit FE.
	USART_ISR_FE = 0x2
	// Position of PE field.
	USART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	USART_ISR_PE_Msk = 0x1
	// Bit PE.
	USART_ISR_PE = 0x1

	// ICR: Interrupt flag clear register
	// Position of WUCF field.
	USART_ICR_WUCF_Pos = 0x14
	// Bit mask of WUCF field.
	USART_ICR_WUCF_Msk = 0x100000
	// Bit WUCF.
	USART_ICR_WUCF = 0x100000
	// Clears the WUF flag in the ISR register
	USART_ICR_WUCF_Clear = 0x1
	// Position of CMCF field.
	USART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	USART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	USART_ICR_CMCF = 0x20000
	// Clears the CMF flag in the ISR register
	USART_ICR_CMCF_Clear = 0x1
	// Position of UDRCF field.
	USART_ICR_UDRCF_Pos = 0xd
	// Bit mask of UDRCF field.
	USART_ICR_UDRCF_Msk = 0x2000
	// Bit UDRCF.
	USART_ICR_UDRCF = 0x2000
	// Position of EOBCF field.
	USART_ICR_EOBCF_Pos = 0xc
	// Bit mask of EOBCF field.
	USART_ICR_EOBCF_Msk = 0x1000
	// Bit EOBCF.
	USART_ICR_EOBCF = 0x1000
	// Clears the EOBF flag in the ISR register
	USART_ICR_EOBCF_Clear = 0x1
	// Position of RTOCF field.
	USART_ICR_RTOCF_Pos = 0xb
	// Bit mask of RTOCF field.
	USART_ICR_RTOCF_Msk = 0x800
	// Bit RTOCF.
	USART_ICR_RTOCF = 0x800
	// Clears the RTOF flag in the ISR register
	USART_ICR_RTOCF_Clear = 0x1
	// Position of CTSCF field.
	USART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	USART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	USART_ICR_CTSCF = 0x200
	// Clears the CTSIF flag in the ISR register
	USART_ICR_CTSCF_Clear = 0x1
	// Position of LBDCF field.
	USART_ICR_LBDCF_Pos = 0x8
	// Bit mask of LBDCF field.
	USART_ICR_LBDCF_Msk = 0x100
	// Bit LBDCF.
	USART_ICR_LBDCF = 0x100
	// Clears the LBDF flag in the ISR register
	USART_ICR_LBDCF_Clear = 0x1
	// Position of TCBGTC field.
	USART_ICR_TCBGTC_Pos = 0x7
	// Bit mask of TCBGTC field.
	USART_ICR_TCBGTC_Msk = 0x80
	// Bit TCBGTC.
	USART_ICR_TCBGTC = 0x80
	// Position of TCCF field.
	USART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	USART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	USART_ICR_TCCF = 0x40
	// Clears the TC flag in the ISR register
	USART_ICR_TCCF_Clear = 0x1
	// Position of TXFECF field.
	USART_ICR_TXFECF_Pos = 0x5
	// Bit mask of TXFECF field.
	USART_ICR_TXFECF_Msk = 0x20
	// Bit TXFECF.
	USART_ICR_TXFECF = 0x20
	// Position of IDLECF field.
	USART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	USART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	USART_ICR_IDLECF = 0x10
	// Clears the IDLE flag in the ISR register
	USART_ICR_IDLECF_Clear = 0x1
	// Position of ORECF field.
	USART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	USART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	USART_ICR_ORECF = 0x8
	// Clears the ORE flag in the ISR register
	USART_ICR_ORECF_Clear = 0x1
	// Position of NCF field.
	USART_ICR_NCF_Pos = 0x2
	// Bit mask of NCF field.
	USART_ICR_NCF_Msk = 0x4
	// Bit NCF.
	USART_ICR_NCF = 0x4
	// Clears the NF flag in the ISR register
	USART_ICR_NCF_Clear = 0x1
	// Position of FECF field.
	USART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	USART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	USART_ICR_FECF = 0x2
	// Clears the FE flag in the ISR register
	USART_ICR_FECF_Clear = 0x1
	// Position of PECF field.
	USART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	USART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	USART_ICR_PECF = 0x1
	// Clears the PE flag in the ISR register
	USART_ICR_PECF_Clear = 0x1

	// RDR: Receive data register
	// Position of RDR field.
	USART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	USART_RDR_RDR_Msk = 0x1ff

	// TDR: Transmit data register
	// Position of TDR field.
	USART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	USART_TDR_TDR_Msk = 0x1ff

	// PRESC: USART prescaler register
	// Position of PRESCALER field.
	USART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf
)

// Bitfields for TIM1: Advanced-timers
const (
	// CR1: control register 1
	// Position of CEN field.
	TIM_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM_CR1_CEN = 0x1
	// Counter disabled
	TIM_CR1_CEN_Disabled = 0x0
	// Counter enabled
	TIM_CR1_CEN_Enabled = 0x1
	// Position of UDIS field.
	TIM_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM_CR1_UDIS = 0x2
	// Update event enabled
	TIM_CR1_UDIS_Enabled = 0x0
	// Update event disabled
	TIM_CR1_UDIS_Disabled = 0x1
	// Position of URS field.
	TIM_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM_CR1_URS = 0x4
	// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
	TIM_CR1_URS_AnyEvent = 0x0
	// Only counter overflow/underflow generates an update interrupt or DMA request
	TIM_CR1_URS_CounterOnly = 0x1
	// Position of OPM field.
	TIM_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM_CR1_OPM = 0x8
	// Counter is not stopped at update event
	TIM_CR1_OPM_Disabled = 0x0
	// Counter stops counting at the next update event (clearing the CEN bit)
	TIM_CR1_OPM_Enabled = 0x1
	// Position of DIR field.
	TIM_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM_CR1_DIR = 0x10
	// Counter used as upcounter
	TIM_CR1_DIR_Up = 0x0
	// Counter used as downcounter
	TIM_CR1_DIR_Down = 0x1
	// Position of CMS field.
	TIM_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM_CR1_CMS_Msk = 0x60
	// The counter counts up or down depending on the direction bit
	TIM_CR1_CMS_EdgeAligned = 0x0
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
	TIM_CR1_CMS_CenterAligned1 = 0x1
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
	TIM_CR1_CMS_CenterAligned2 = 0x2
	// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
	TIM_CR1_CMS_CenterAligned3 = 0x3
	// Position of ARPE field.
	TIM_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM_CR1_ARPE = 0x80
	// TIMx_APRR register is not buffered
	TIM_CR1_ARPE_Disabled = 0x0
	// TIMx_APRR register is buffered
	TIM_CR1_ARPE_Enabled = 0x1
	// Position of CKD field.
	TIM_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM_CR1_CKD_Msk = 0x300
	// t_DTS = t_CK_INT
	TIM_CR1_CKD_Div1 = 0x0
	// t_DTS = 2 × t_CK_INT
	TIM_CR1_CKD_Div2 = 0x1
	// t_DTS = 4 × t_CK_INT
	TIM_CR1_CKD_Div4 = 0x2
	// Position of UIFREMAP field.
	TIM_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM_CR1_UIFREMAP = 0x800

	// CR2: control register 2
	// Position of MMS2 field.
	TIM_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM_CR2_MMS2_Msk = 0xf00000
	// Position of OIS6 field.
	TIM_CR2_OIS6_Pos = 0x12
	// Bit mask of OIS6 field.
	TIM_CR2_OIS6_Msk = 0x40000
	// Bit OIS6.
	TIM_CR2_OIS6 = 0x40000
	// Position of OIS5 field.
	TIM_CR2_OIS5_Pos = 0x10
	// Bit mask of OIS5 field.
	TIM_CR2_OIS5_Msk = 0x10000
	// Bit OIS5.
	TIM_CR2_OIS5 = 0x10000
	// Position of OIS4 field.
	TIM_CR2_OIS4_Pos = 0xe
	// Bit mask of OIS4 field.
	TIM_CR2_OIS4_Msk = 0x4000
	// Bit OIS4.
	TIM_CR2_OIS4 = 0x4000
	// Position of OIS3N field.
	TIM_CR2_OIS3N_Pos = 0xd
	// Bit mask of OIS3N field.
	TIM_CR2_OIS3N_Msk = 0x2000
	// Bit OIS3N.
	TIM_CR2_OIS3N = 0x2000
	// Position of OIS3 field.
	TIM_CR2_OIS3_Pos = 0xc
	// Bit mask of OIS3 field.
	TIM_CR2_OIS3_Msk = 0x1000
	// Bit OIS3.
	TIM_CR2_OIS3 = 0x1000
	// Position of OIS2N field.
	TIM_CR2_OIS2N_Pos = 0xb
	// Bit mask of OIS2N field.
	TIM_CR2_OIS2N_Msk = 0x800
	// Bit OIS2N.
	TIM_CR2_OIS2N = 0x800
	// Position of OIS2 field.
	TIM_CR2_OIS2_Pos = 0xa
	// Bit mask of OIS2 field.
	TIM_CR2_OIS2_Msk = 0x400
	// Bit OIS2.
	TIM_CR2_OIS2 = 0x400
	// Position of OIS1N field.
	TIM_CR2_OIS1N_Pos = 0x9
	// Bit mask of OIS1N field.
	TIM_CR2_OIS1N_Msk = 0x200
	// Bit OIS1N.
	TIM_CR2_OIS1N = 0x200
	// Position of OIS1 field.
	TIM_CR2_OIS1_Pos = 0x8
	// Bit mask of OIS1 field.
	TIM_CR2_OIS1_Msk = 0x100
	// Bit OIS1.
	TIM_CR2_OIS1 = 0x100
	// Position of TI1S field.
	TIM_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM_CR2_TI1S = 0x80
	// The TIMx_CH1 pin is connected to TI1 input
	TIM_CR2_TI1S_Normal = 0x0
	// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
	TIM_CR2_TI1S_XOR = 0x1
	// Position of MMS field.
	TIM_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM_CR2_MMS_Msk = 0x70
	// The UG bit from the TIMx_EGR register is used as trigger output
	TIM_CR2_MMS_Reset = 0x0
	// The counter enable signal, CNT_EN, is used as trigger output
	TIM_CR2_MMS_Enable = 0x1
	// The update event is selected as trigger output
	TIM_CR2_MMS_Update = 0x2
	// The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
	TIM_CR2_MMS_ComparePulse = 0x3
	// OC1REF signal is used as trigger output
	TIM_CR2_MMS_CompareOC1 = 0x4
	// OC2REF signal is used as trigger output
	TIM_CR2_MMS_CompareOC2 = 0x5
	// OC3REF signal is used as trigger output
	TIM_CR2_MMS_CompareOC3 = 0x6
	// OC4REF signal is used as trigger output
	TIM_CR2_MMS_CompareOC4 = 0x7
	// Position of CCDS field.
	TIM_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM_CR2_CCDS = 0x8
	// CCx DMA request sent when CCx event occurs
	TIM_CR2_CCDS_OnCompare = 0x0
	// CCx DMA request sent when update event occurs
	TIM_CR2_CCDS_OnUpdate = 0x1
	// Position of CCUS field.
	TIM_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM_CR2_CCUS = 0x4
	// Position of CCPC field.
	TIM_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM_CR2_CCPC = 0x1

	// SMCR: slave mode control register
	// Position of SMS field.
	TIM_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM_SMCR_SMS_Msk = 0x7
	// Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
	TIM_SMCR_SMS_Disabled = 0x0
	// Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
	TIM_SMCR_SMS_Encoder_Mode_1 = 0x1
	// Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
	TIM_SMCR_SMS_Encoder_Mode_2 = 0x2
	// Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
	TIM_SMCR_SMS_Encoder_Mode_3 = 0x3
	// Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
	TIM_SMCR_SMS_Reset_Mode = 0x4
	// Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
	TIM_SMCR_SMS_Gated_Mode = 0x5
	// Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
	TIM_SMCR_SMS_Trigger_Mode = 0x6
	// External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
	TIM_SMCR_SMS_Ext_Clock_Mode = 0x7
	// Position of TS field.
	TIM_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM_SMCR_TS_Msk = 0x70
	// Internal Trigger 0 (ITR0)
	TIM_SMCR_TS_ITR0 = 0x0
	// Internal Trigger 1 (ITR1)
	TIM_SMCR_TS_ITR1 = 0x1
	// Internal Trigger 2 (ITR2)
	TIM_SMCR_TS_ITR2 = 0x2
	// TI1 Edge Detector (TI1F_ED)
	TIM_SMCR_TS_TI1F_ED = 0x4
	// Filtered Timer Input 1 (TI1FP1)
	TIM_SMCR_TS_TI1FP1 = 0x5
	// Filtered Timer Input 2 (TI2FP2)
	TIM_SMCR_TS_TI2FP2 = 0x6
	// External Trigger input (ETRF)
	TIM_SMCR_TS_ETRF = 0x7
	// Position of MSM field.
	TIM_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM_SMCR_MSM = 0x80
	// No action
	TIM_SMCR_MSM_NoSync = 0x0
	// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
	TIM_SMCR_MSM_Sync = 0x1
	// Position of ETF field.
	TIM_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM_SMCR_ETF_Msk = 0xf00
	// No filter, sampling is done at fDTS
	TIM_SMCR_ETF_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_SMCR_ETF_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_SMCR_ETF_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_SMCR_ETF_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_SMCR_ETF_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_SMCR_ETF_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_SMCR_ETF_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_SMCR_ETF_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_SMCR_ETF_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_SMCR_ETF_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_SMCR_ETF_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_SMCR_ETF_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_SMCR_ETF_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_SMCR_ETF_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_SMCR_ETF_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_SMCR_ETF_FDTS_Div32_N8 = 0xf
	// Position of ETPS field.
	TIM_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM_SMCR_ETPS_Msk = 0x3000
	// Prescaler OFF
	TIM_SMCR_ETPS_Div1 = 0x0
	// ETRP frequency divided by 2
	TIM_SMCR_ETPS_Div2 = 0x1
	// ETRP frequency divided by 4
	TIM_SMCR_ETPS_Div4 = 0x2
	// ETRP frequency divided by 8
	TIM_SMCR_ETPS_Div8 = 0x3
	// Position of ECE field.
	TIM_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM_SMCR_ECE = 0x4000
	// External clock mode 2 disabled
	TIM_SMCR_ECE_Disabled = 0x0
	// External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
	TIM_SMCR_ECE_Enabled = 0x1
	// Position of ETP field.
	TIM_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM_SMCR_ETP = 0x8000
	// ETR is noninverted, active at high level or rising edge
	TIM_SMCR_ETP_NotInverted = 0x0
	// ETR is inverted, active at low level or falling edge
	TIM_SMCR_ETP_Inverted = 0x1
	// Position of SMS_3 field.
	TIM_SMCR_SMS_3_Pos = 0x10
	// Bit mask of SMS_3 field.
	TIM_SMCR_SMS_3_Msk = 0x10000
	// Bit SMS_3.
	TIM_SMCR_SMS_3 = 0x10000
	// Position of TS_4_3 field.
	TIM_SMCR_TS_4_3_Pos = 0x14
	// Bit mask of TS_4_3 field.
	TIM_SMCR_TS_4_3_Msk = 0x300000

	// DIER: DMA/Interrupt enable register
	// Position of TDE field.
	TIM_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM_DIER_TDE = 0x4000
	// Trigger DMA request disabled
	TIM_DIER_TDE_Disabled = 0x0
	// Trigger DMA request enabled
	TIM_DIER_TDE_Enabled = 0x1
	// Position of COMDE field.
	TIM_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM_DIER_COMDE = 0x2000
	// Position of CC4DE field.
	TIM_DIER_CC4DE_Pos = 0xc
	// Bit mask of CC4DE field.
	TIM_DIER_CC4DE_Msk = 0x1000
	// Bit CC4DE.
	TIM_DIER_CC4DE = 0x1000
	// CCx DMA request disabled
	TIM_DIER_CC4DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC4DE_Enabled = 0x1
	// Position of CC3DE field.
	TIM_DIER_CC3DE_Pos = 0xb
	// Bit mask of CC3DE field.
	TIM_DIER_CC3DE_Msk = 0x800
	// Bit CC3DE.
	TIM_DIER_CC3DE = 0x800
	// CCx DMA request disabled
	TIM_DIER_CC3DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC3DE_Enabled = 0x1
	// Position of CC2DE field.
	TIM_DIER_CC2DE_Pos = 0xa
	// Bit mask of CC2DE field.
	TIM_DIER_CC2DE_Msk = 0x400
	// Bit CC2DE.
	TIM_DIER_CC2DE = 0x400
	// CCx DMA request disabled
	TIM_DIER_CC2DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC2DE_Enabled = 0x1
	// Position of CC1DE field.
	TIM_DIER_CC1DE_Pos = 0x9
	// Bit mask of CC1DE field.
	TIM_DIER_CC1DE_Msk = 0x200
	// Bit CC1DE.
	TIM_DIER_CC1DE = 0x200
	// CCx DMA request disabled
	TIM_DIER_CC1DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC1DE_Enabled = 0x1
	// Position of UDE field.
	TIM_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM_DIER_UDE = 0x100
	// Update DMA request disabled
	TIM_DIER_UDE_Disabled = 0x0
	// Update DMA request enabled
	TIM_DIER_UDE_Enabled = 0x1
	// Position of TIE field.
	TIM_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM_DIER_TIE = 0x40
	// Trigger interrupt disabled
	TIM_DIER_TIE_Disabled = 0x0
	// Trigger interrupt enabled
	TIM_DIER_TIE_Enabled = 0x1
	// Position of CC4IE field.
	TIM_DIER_CC4IE_Pos = 0x4
	// Bit mask of CC4IE field.
	TIM_DIER_CC4IE_Msk = 0x10
	// Bit CC4IE.
	TIM_DIER_CC4IE = 0x10
	// CCx interrupt disabled
	TIM_DIER_CC4IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC4IE_Enabled = 0x1
	// Position of CC3IE field.
	TIM_DIER_CC3IE_Pos = 0x3
	// Bit mask of CC3IE field.
	TIM_DIER_CC3IE_Msk = 0x8
	// Bit CC3IE.
	TIM_DIER_CC3IE = 0x8
	// CCx interrupt disabled
	TIM_DIER_CC3IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC3IE_Enabled = 0x1
	// Position of CC2IE field.
	TIM_DIER_CC2IE_Pos = 0x2
	// Bit mask of CC2IE field.
	TIM_DIER_CC2IE_Msk = 0x4
	// Bit CC2IE.
	TIM_DIER_CC2IE = 0x4
	// CCx interrupt disabled
	TIM_DIER_CC2IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC2IE_Enabled = 0x1
	// Position of CC1IE field.
	TIM_DIER_CC1IE_Pos = 0x1
	// Bit mask of CC1IE field.
	TIM_DIER_CC1IE_Msk = 0x2
	// Bit CC1IE.
	TIM_DIER_CC1IE = 0x2
	// CCx interrupt disabled
	TIM_DIER_CC1IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC1IE_Enabled = 0x1
	// Position of UIE field.
	TIM_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM_DIER_UIE = 0x1
	// Update interrupt disabled
	TIM_DIER_UIE_Disabled = 0x0
	// Update interrupt enabled
	TIM_DIER_UIE_Enabled = 0x1
	// Position of BIE field.
	TIM_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM_DIER_BIE = 0x80
	// Position of COMIE field.
	TIM_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM_DIER_COMIE = 0x20

	// SR: status register
	// Position of CC6IF field.
	TIM_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM_SR_CC6IF = 0x20000
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC6IF_Match = 0x1
	// Clear flag
	TIM_SR_CC6IF_Clear = 0x0
	// Position of CC5IF field.
	TIM_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM_SR_CC5IF = 0x10000
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC5IF_Match = 0x1
	// Clear flag
	TIM_SR_CC5IF_Clear = 0x0
	// Position of SBIF field.
	TIM_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM_SR_SBIF = 0x2000
	// Position of CC4OF field.
	TIM_SR_CC4OF_Pos = 0xc
	// Bit mask of CC4OF field.
	TIM_SR_CC4OF_Msk = 0x1000
	// Bit CC4OF.
	TIM_SR_CC4OF = 0x1000
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC4OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC4OF_Clear = 0x0
	// Position of CC3OF field.
	TIM_SR_CC3OF_Pos = 0xb
	// Bit mask of CC3OF field.
	TIM_SR_CC3OF_Msk = 0x800
	// Bit CC3OF.
	TIM_SR_CC3OF = 0x800
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC3OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC3OF_Clear = 0x0
	// Position of CC2OF field.
	TIM_SR_CC2OF_Pos = 0xa
	// Bit mask of CC2OF field.
	TIM_SR_CC2OF_Msk = 0x400
	// Bit CC2OF.
	TIM_SR_CC2OF = 0x400
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC2OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC2OF_Clear = 0x0
	// Position of CC1OF field.
	TIM_SR_CC1OF_Pos = 0x9
	// Bit mask of CC1OF field.
	TIM_SR_CC1OF_Msk = 0x200
	// Bit CC1OF.
	TIM_SR_CC1OF = 0x200
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC1OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC1OF_Clear = 0x0
	// Position of B2IF field.
	TIM_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM_SR_B2IF = 0x100
	// Position of BIF field.
	TIM_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM_SR_BIF = 0x80
	// Position of TIF field.
	TIM_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM_SR_TIF = 0x40
	// No trigger event occurred
	TIM_SR_TIF_NoTrigger = 0x0
	// Trigger interrupt pending
	TIM_SR_TIF_Trigger = 0x1
	// Clear flag
	TIM_SR_TIF_Clear = 0x0
	// Position of COMIF field.
	TIM_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM_SR_COMIF = 0x20
	// Position of CC4IF field.
	TIM_SR_CC4IF_Pos = 0x4
	// Bit mask of CC4IF field.
	TIM_SR_CC4IF_Msk = 0x10
	// Bit CC4IF.
	TIM_SR_CC4IF = 0x10
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC4IF_Match = 0x1
	// Clear flag
	TIM_SR_CC4IF_Clear = 0x0
	// Position of CC3IF field.
	TIM_SR_CC3IF_Pos = 0x3
	// Bit mask of CC3IF field.
	TIM_SR_CC3IF_Msk = 0x8
	// Bit CC3IF.
	TIM_SR_CC3IF = 0x8
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC3IF_Match = 0x1
	// Clear flag
	TIM_SR_CC3IF_Clear = 0x0
	// Position of CC2IF field.
	TIM_SR_CC2IF_Pos = 0x2
	// Bit mask of CC2IF field.
	TIM_SR_CC2IF_Msk = 0x4
	// Bit CC2IF.
	TIM_SR_CC2IF = 0x4
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC2IF_Match = 0x1
	// Clear flag
	TIM_SR_CC2IF_Clear = 0x0
	// Position of CC1IF field.
	TIM_SR_CC1IF_Pos = 0x1
	// Bit mask of CC1IF field.
	TIM_SR_CC1IF_Msk = 0x2
	// Bit CC1IF.
	TIM_SR_CC1IF = 0x2
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC1IF_Match = 0x1
	// Clear flag
	TIM_SR_CC1IF_Clear = 0x0
	// Position of UIF field.
	TIM_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM_SR_UIF = 0x1
	// No update occurred
	TIM_SR_UIF_Clear = 0x0
	// Update interrupt pending.
	TIM_SR_UIF_UpdatePending = 0x1

	// EGR: event generation register
	// Position of UG field.
	TIM_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM_EGR_UG = 0x1
	// Re-initializes the timer counter and generates an update of the registers.
	TIM_EGR_UG_Update = 0x1
	// Position of CC1G field.
	TIM_EGR_CC1G_Pos = 0x1
	// Bit mask of CC1G field.
	TIM_EGR_CC1G_Msk = 0x2
	// Bit CC1G.
	TIM_EGR_CC1G = 0x2
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC1G_Trigger = 0x1
	// Position of CC2G field.
	TIM_EGR_CC2G_Pos = 0x2
	// Bit mask of CC2G field.
	TIM_EGR_CC2G_Msk = 0x4
	// Bit CC2G.
	TIM_EGR_CC2G = 0x4
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC2G_Trigger = 0x1
	// Position of CC3G field.
	TIM_EGR_CC3G_Pos = 0x3
	// Bit mask of CC3G field.
	TIM_EGR_CC3G_Msk = 0x8
	// Bit CC3G.
	TIM_EGR_CC3G = 0x8
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC3G_Trigger = 0x1
	// Position of CC4G field.
	TIM_EGR_CC4G_Pos = 0x4
	// Bit mask of CC4G field.
	TIM_EGR_CC4G_Msk = 0x10
	// Bit CC4G.
	TIM_EGR_CC4G = 0x10
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC4G_Trigger = 0x1
	// Position of COMG field.
	TIM_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM_EGR_COMG = 0x20
	// Position of TG field.
	TIM_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM_EGR_TG = 0x40
	// The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
	TIM_EGR_TG_Trigger = 0x1
	// Position of BG field.
	TIM_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM_EGR_BG = 0x80
	// Position of B2G field.
	TIM_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM_EGR_B2G = 0x100

	// CCMR1_Output: capture/compare mode register 1 (output mode)
	// Position of CC1S field.
	TIM_CCMR1_Output_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM_CCMR1_Output_CC1S_Msk = 0x3
	// CC1 channel is configured as output
	TIM_CCMR1_Output_CC1S_Output = 0x0
	// Position of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Pos = 0x2
	// Bit mask of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Msk = 0x4
	// Bit OC1FE.
	TIM_CCMR1_Output_OC1FE = 0x4
	// Position of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Pos = 0x3
	// Bit mask of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Msk = 0x8
	// Bit OC1PE.
	TIM_CCMR1_Output_OC1PE = 0x8
	// Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
	TIM_CCMR1_Output_OC1PE_Disabled = 0x0
	// Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC1PE_Enabled = 0x1
	// Position of OC1M field.
	TIM_CCMR1_Output_OC1M_Pos = 0x4
	// Bit mask of OC1M field.
	TIM_CCMR1_Output_OC1M_Msk = 0x70
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
	TIM_CCMR1_Output_OC1M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
	TIM_CCMR1_Output_OC1M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
	TIM_CCMR1_Output_OC1M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy
	TIM_CCMR1_Output_OC1M_Toggle = 0x3
	// OCyREF is forced low
	TIM_CCMR1_Output_OC1M_ForceInactive = 0x4
	// OCyREF is forced high
	TIM_CCMR1_Output_OC1M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
	TIM_CCMR1_Output_OC1M_PwmMode1 = 0x6
	// Inversely to PwmMode1
	TIM_CCMR1_Output_OC1M_PwmMode2 = 0x7
	// Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC1M_OpmMode1 = 0x8
	// Inversely to OpmMode1
	TIM_CCMR1_Output_OC1M_OpmMode2 = 0x9
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_CombinedPwmMode1 = 0xc
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_CombinedPwmMode2 = 0xd
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC1M_AsymmetricPwmMode1 = 0xe
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC1M_AsymmetricPwmMode2 = 0xf
	// Position of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Pos = 0x7
	// Bit mask of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Msk = 0x80
	// Bit OC1CE.
	TIM_CCMR1_Output_OC1CE = 0x80
	// Position of CC2S field.
	TIM_CCMR1_Output_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM_CCMR1_Output_CC2S_Msk = 0x300
	// CC2 channel is configured as output
	TIM_CCMR1_Output_CC2S_Output = 0x0
	// Position of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Pos = 0xa
	// Bit mask of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Msk = 0x400
	// Bit OC2FE.
	TIM_CCMR1_Output_OC2FE = 0x400
	// Position of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Pos = 0xb
	// Bit mask of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Msk = 0x800
	// Bit OC2PE.
	TIM_CCMR1_Output_OC2PE = 0x800
	// Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
	TIM_CCMR1_Output_OC2PE_Disabled = 0x0
	// Preload register on CCR2 enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC2PE_Enabled = 0x1
	// Position of OC2M field.
	TIM_CCMR1_Output_OC2M_Pos = 0xc
	// Bit mask of OC2M field.
	TIM_CCMR1_Output_OC2M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
	TIM_CCMR1_Output_OC2M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
	TIM_CCMR1_Output_OC2M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
	TIM_CCMR1_Output_OC2M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy
	TIM_CCMR1_Output_OC2M_Toggle = 0x3
	// OCyREF is forced low
	TIM_CCMR1_Output_OC2M_ForceInactive = 0x4
	// OCyREF is forced high
	TIM_CCMR1_Output_OC2M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
	TIM_CCMR1_Output_OC2M_PwmMode1 = 0x6
	// Inversely to PwmMode1
	TIM_CCMR1_Output_OC2M_PwmMode2 = 0x7
	// Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC2M_OpmMode1 = 0x8
	// Inversely to OpmMode1
	TIM_CCMR1_Output_OC2M_OpmMode2 = 0x9
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_CombinedPwmMode1 = 0xc
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_CombinedPwmMode2 = 0xd
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC2M_AsymmetricPwmMode1 = 0xe
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC2M_AsymmetricPwmMode2 = 0xf
	// Position of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Pos = 0xf
	// Bit mask of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Msk = 0x8000
	// Bit OC2CE.
	TIM_CCMR1_Output_OC2CE = 0x8000
	// Position of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Pos = 0x10
	// Bit mask of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Msk = 0x10000
	// Bit OC1M_3.
	TIM_CCMR1_Output_OC1M_3 = 0x10000
	// Position of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Pos = 0x18
	// Bit mask of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Msk = 0x1000000
	// Bit OC2M_3.
	TIM_CCMR1_Output_OC2M_3 = 0x1000000

	// CCMR1_Input: capture/compare mode register 1 (input mode)
	// Position of IC2F field.
	TIM_CCMR1_Input_IC2F_Pos = 0xc
	// Bit mask of IC2F field.
	TIM_CCMR1_Input_IC2F_Msk = 0xf000
	// Position of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Pos = 0xa
	// Bit mask of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Msk = 0xc00
	// Position of CC2S field.
	TIM_CCMR1_Input_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM_CCMR1_Input_CC2S_Msk = 0x300
	// CC2 channel is configured as input, IC2 is mapped on TI2
	TIM_CCMR1_Input_CC2S_TI2 = 0x1
	// CC2 channel is configured as input, IC2 is mapped on TI1
	TIM_CCMR1_Input_CC2S_TI1 = 0x2
	// CC2 channel is configured as input, IC2 is mapped on TRC
	TIM_CCMR1_Input_CC2S_TRC = 0x3
	// Position of IC1F field.
	TIM_CCMR1_Input_IC1F_Pos = 0x4
	// Bit mask of IC1F field.
	TIM_CCMR1_Input_IC1F_Msk = 0xf0
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC1F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC1F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC1F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC1F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N8 = 0xf
	// Position of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Pos = 0x2
	// Bit mask of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Msk = 0xc
	// Position of CC1S field.
	TIM_CCMR1_Input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM_CCMR1_Input_CC1S_Msk = 0x3
	// CC1 channel is configured as input, IC1 is mapped on TI1
	TIM_CCMR1_Input_CC1S_TI1 = 0x1
	// CC1 channel is configured as input, IC1 is mapped on TI2
	TIM_CCMR1_Input_CC1S_TI2 = 0x2
	// CC1 channel is configured as input, IC1 is mapped on TRC
	TIM_CCMR1_Input_CC1S_TRC = 0x3

	// CCMR2_Output: capture/compare mode register 2 (output mode)
	// Position of CC3S field.
	TIM_CCMR2_Output_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM_CCMR2_Output_CC3S_Msk = 0x3
	// CC3 channel is configured as output
	TIM_CCMR2_Output_CC3S_Output = 0x0
	// Position of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Pos = 0x2
	// Bit mask of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Msk = 0x4
	// Bit OC3FE.
	TIM_CCMR2_Output_OC3FE = 0x4
	// Position of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Pos = 0x3
	// Bit mask of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Msk = 0x8
	// Bit OC3PE.
	TIM_CCMR2_Output_OC3PE = 0x8
	// Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
	TIM_CCMR2_Output_OC3PE_Disabled = 0x0
	// Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC3PE_Enabled = 0x1
	// Position of OC3M field.
	TIM_CCMR2_Output_OC3M_Pos = 0x4
	// Bit mask of OC3M field.
	TIM_CCMR2_Output_OC3M_Msk = 0x70
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
	TIM_CCMR2_Output_OC3M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
	TIM_CCMR2_Output_OC3M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
	TIM_CCMR2_Output_OC3M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy
	TIM_CCMR2_Output_OC3M_Toggle = 0x3
	// OCyREF is forced low
	TIM_CCMR2_Output_OC3M_ForceInactive = 0x4
	// OCyREF is forced high
	TIM_CCMR2_Output_OC3M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
	TIM_CCMR2_Output_OC3M_PwmMode1 = 0x6
	// Inversely to PwmMode1
	TIM_CCMR2_Output_OC3M_PwmMode2 = 0x7
	// Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC3M_OpmMode1 = 0x8
	// Inversely to OpmMode1
	TIM_CCMR2_Output_OC3M_OpmMode2 = 0x9
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_CombinedPwmMode1 = 0xc
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_CombinedPwmMode2 = 0xd
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC3M_AsymmetricPwmMode1 = 0xe
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC3M_AsymmetricPwmMode2 = 0xf
	// Position of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Pos = 0x7
	// Bit mask of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Msk = 0x80
	// Bit OC3CE.
	TIM_CCMR2_Output_OC3CE = 0x80
	// Position of CC4S field.
	TIM_CCMR2_Output_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM_CCMR2_Output_CC4S_Msk = 0x300
	// CC4 channel is configured as output
	TIM_CCMR2_Output_CC4S_Output = 0x0
	// Position of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Pos = 0xa
	// Bit mask of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Msk = 0x400
	// Bit OC4FE.
	TIM_CCMR2_Output_OC4FE = 0x400
	// Position of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Pos = 0xb
	// Bit mask of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Msk = 0x800
	// Bit OC4PE.
	TIM_CCMR2_Output_OC4PE = 0x800
	// Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately
	TIM_CCMR2_Output_OC4PE_Disabled = 0x0
	// Preload register on CCR4 enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC4PE_Enabled = 0x1
	// Position of OC4M field.
	TIM_CCMR2_Output_OC4M_Pos = 0xc
	// Bit mask of OC4M field.
	TIM_CCMR2_Output_OC4M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
	TIM_CCMR2_Output_OC4M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
	TIM_CCMR2_Output_OC4M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
	TIM_CCMR2_Output_OC4M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy
	TIM_CCMR2_Output_OC4M_Toggle = 0x3
	// OCyREF is forced low
	TIM_CCMR2_Output_OC4M_ForceInactive = 0x4
	// OCyREF is forced high
	TIM_CCMR2_Output_OC4M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
	TIM_CCMR2_Output_OC4M_PwmMode1 = 0x6
	// Inversely to PwmMode1
	TIM_CCMR2_Output_OC4M_PwmMode2 = 0x7
	// Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC4M_OpmMode1 = 0x8
	// Inversely to OpmMode1
	TIM_CCMR2_Output_OC4M_OpmMode2 = 0x9
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_CombinedPwmMode1 = 0xc
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_CombinedPwmMode2 = 0xd
	// OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC4M_AsymmetricPwmMode1 = 0xe
	// OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC4M_AsymmetricPwmMode2 = 0xf
	// Position of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Pos = 0xf
	// Bit mask of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Msk = 0x8000
	// Bit OC4CE.
	TIM_CCMR2_Output_OC4CE = 0x8000
	// Position of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Pos = 0x10
	// Bit mask of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Msk = 0x10000
	// Bit OC3M_3.
	TIM_CCMR2_Output_OC3M_3 = 0x10000
	// Position of OC4M_4 field.
	TIM_CCMR2_Output_OC4M_4_Pos = 0x18
	// Bit mask of OC4M_4 field.
	TIM_CCMR2_Output_OC4M_4_Msk = 0x1000000
	// Bit OC4M_4.
	TIM_CCMR2_Output_OC4M_4 = 0x1000000

	// CCMR2_Input: capture/compare mode register 2 (input mode)
	// Position of IC4F field.
	TIM_CCMR2_Input_IC4F_Pos = 0xc
	// Bit mask of IC4F field.
	TIM_CCMR2_Input_IC4F_Msk = 0xf000
	// Position of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Pos = 0xa
	// Bit mask of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Msk = 0xc00
	// Position of CC4S field.
	TIM_CCMR2_Input_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM_CCMR2_Input_CC4S_Msk = 0x300
	// CC4 channel is configured as input, IC4 is mapped on TI4
	TIM_CCMR2_Input_CC4S_TI4 = 0x1
	// CC4 channel is configured as input, IC4 is mapped on TI3
	TIM_CCMR2_Input_CC4S_TI3 = 0x2
	// CC4 channel is configured as input, IC4 is mapped on TRC
	TIM_CCMR2_Input_CC4S_TRC = 0x3
	// Position of IC3F field.
	TIM_CCMR2_Input_IC3F_Pos = 0x4
	// Bit mask of IC3F field.
	TIM_CCMR2_Input_IC3F_Msk = 0xf0
	// Position of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Pos = 0x2
	// Bit mask of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Msk = 0xc
	// Position of CC3S field.
	TIM_CCMR2_Input_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM_CCMR2_Input_CC3S_Msk = 0x3
	// CC3 channel is configured as input, IC3 is mapped on TI3
	TIM_CCMR2_Input_CC3S_TI3 = 0x1
	// CC3 channel is configured as input, IC3 is mapped on TI4
	TIM_CCMR2_Input_CC3S_TI4 = 0x2
	// CC3 channel is configured as input, IC3 is mapped on TRC
	TIM_CCMR2_Input_CC3S_TRC = 0x3

	// CCER: capture/compare enable register
	// Position of CC1E field.
	TIM_CCER_CC1E_Pos = 0x0
	// Bit mask of CC1E field.
	TIM_CCER_CC1E_Msk = 0x1
	// Bit CC1E.
	TIM_CCER_CC1E = 0x1
	// Position of CC1P field.
	TIM_CCER_CC1P_Pos = 0x1
	// Bit mask of CC1P field.
	TIM_CCER_CC1P_Msk = 0x2
	// Bit CC1P.
	TIM_CCER_CC1P = 0x2
	// Position of CC1NE field.
	TIM_CCER_CC1NE_Pos = 0x2
	// Bit mask of CC1NE field.
	TIM_CCER_CC1NE_Msk = 0x4
	// Bit CC1NE.
	TIM_CCER_CC1NE = 0x4
	// Position of CC1NP field.
	TIM_CCER_CC1NP_Pos = 0x3
	// Bit mask of CC1NP field.
	TIM_CCER_CC1NP_Msk = 0x8
	// Bit CC1NP.
	TIM_CCER_CC1NP = 0x8
	// Position of CC2E field.
	TIM_CCER_CC2E_Pos = 0x4
	// Bit mask of CC2E field.
	TIM_CCER_CC2E_Msk = 0x10
	// Bit CC2E.
	TIM_CCER_CC2E = 0x10
	// Position of CC2P field.
	TIM_CCER_CC2P_Pos = 0x5
	// Bit mask of CC2P field.
	TIM_CCER_CC2P_Msk = 0x20
	// Bit CC2P.
	TIM_CCER_CC2P = 0x20
	// Position of CC2NE field.
	TIM_CCER_CC2NE_Pos = 0x6
	// Bit mask of CC2NE field.
	TIM_CCER_CC2NE_Msk = 0x40
	// Bit CC2NE.
	TIM_CCER_CC2NE = 0x40
	// Position of CC2NP field.
	TIM_CCER_CC2NP_Pos = 0x7
	// Bit mask of CC2NP field.
	TIM_CCER_CC2NP_Msk = 0x80
	// Bit CC2NP.
	TIM_CCER_CC2NP = 0x80
	// Position of CC3E field.
	TIM_CCER_CC3E_Pos = 0x8
	// Bit mask of CC3E field.
	TIM_CCER_CC3E_Msk = 0x100
	// Bit CC3E.
	TIM_CCER_CC3E = 0x100
	// Position of CC3P field.
	TIM_CCER_CC3P_Pos = 0x9
	// Bit mask of CC3P field.
	TIM_CCER_CC3P_Msk = 0x200
	// Bit CC3P.
	TIM_CCER_CC3P = 0x200
	// Position of CC3NE field.
	TIM_CCER_CC3NE_Pos = 0xa
	// Bit mask of CC3NE field.
	TIM_CCER_CC3NE_Msk = 0x400
	// Bit CC3NE.
	TIM_CCER_CC3NE = 0x400
	// Position of CC3NP field.
	TIM_CCER_CC3NP_Pos = 0xb
	// Bit mask of CC3NP field.
	TIM_CCER_CC3NP_Msk = 0x800
	// Bit CC3NP.
	TIM_CCER_CC3NP = 0x800
	// Position of CC4E field.
	TIM_CCER_CC4E_Pos = 0xc
	// Bit mask of CC4E field.
	TIM_CCER_CC4E_Msk = 0x1000
	// Bit CC4E.
	TIM_CCER_CC4E = 0x1000
	// Position of CC4P field.
	TIM_CCER_CC4P_Pos = 0xd
	// Bit mask of CC4P field.
	TIM_CCER_CC4P_Msk = 0x2000
	// Bit CC4P.
	TIM_CCER_CC4P = 0x2000
	// Position of CC4NP field.
	TIM_CCER_CC4NP_Pos = 0xf
	// Bit mask of CC4NP field.
	TIM_CCER_CC4NP_Msk = 0x8000
	// Bit CC4NP.
	TIM_CCER_CC4NP = 0x8000
	// Position of CC5E field.
	TIM_CCER_CC5E_Pos = 0x10
	// Bit mask of CC5E field.
	TIM_CCER_CC5E_Msk = 0x10000
	// Bit CC5E.
	TIM_CCER_CC5E = 0x10000
	// Position of CC5P field.
	TIM_CCER_CC5P_Pos = 0x11
	// Bit mask of CC5P field.
	TIM_CCER_CC5P_Msk = 0x20000
	// Bit CC5P.
	TIM_CCER_CC5P = 0x20000
	// Position of CC6E field.
	TIM_CCER_CC6E_Pos = 0x14
	// Bit mask of CC6E field.
	TIM_CCER_CC6E_Msk = 0x100000
	// Bit CC6E.
	TIM_CCER_CC6E = 0x100000
	// Position of CC6P field.
	TIM_CCER_CC6P_Pos = 0x15
	// Bit mask of CC6P field.
	TIM_CCER_CC6P_Msk = 0x200000
	// Bit CC6P.
	TIM_CCER_CC6P = 0x200000

	// CNT: counter
	// Position of CNT field.
	TIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM_CNT_UIFCPY = 0x80000000

	// PSC: prescaler
	// Position of PSC field.
	TIM_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM_PSC_PSC_Msk = 0xffff

	// ARR: auto-reload register
	// Position of ARR field.
	TIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM_ARR_ARR_Msk = 0xffff

	// RCR: repetition counter register
	// Position of REP field.
	TIM_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM_RCR_REP_Msk = 0xff

	// CCR1: capture/compare register 1
	// Position of CCR field.
	TIM_CCR_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR_CCR_Msk = 0xffff

	// BDTR: break and dead-time register
	// Position of DTG field.
	TIM_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM_BDTR_LOCK_Msk = 0x300
	// Position of OSSI field.
	TIM_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM_BDTR_OSSI = 0x400
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSI_Disabled = 0x0
	// When inactive, OC/OCN outputs are forced to idle level
	TIM_BDTR_OSSI_IdleLevel = 0x1
	// Position of OSSR field.
	TIM_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM_BDTR_OSSR = 0x800
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSR_Disabled = 0x0
	// When inactive, OC/OCN outputs are enabled with their inactive level
	TIM_BDTR_OSSR_IdleLevel = 0x1
	// Position of BKE field.
	TIM_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM_BDTR_BKE = 0x1000
	// Position of BKP field.
	TIM_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM_BDTR_BKP = 0x2000
	// Position of AOE field.
	TIM_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM_BDTR_AOE = 0x4000
	// Position of MOE field.
	TIM_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM_BDTR_MOE = 0x8000
	// OC/OCN are disabled or forced idle depending on OSSI
	TIM_BDTR_MOE_DisabledIdle = 0x0
	// OC/OCN are enabled if CCxE/CCxNE are set
	TIM_BDTR_MOE_Enabled = 0x1
	// Position of BKF field.
	TIM_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM_BDTR_BK2E = 0x1000000
	// Position of BK2P field.
	TIM_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM_BDTR_BK2P = 0x2000000

	// DCR: DMA control register
	// Position of DBL field.
	TIM_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM_DCR_DBL_Msk = 0x1f00
	// Position of DBA field.
	TIM_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM_DCR_DBA_Msk = 0x1f

	// DMAR: DMA address for full transfer
	// Position of DMAB field.
	TIM_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM_DMAR_DMAB_Msk = 0xffff

	// CCMR3_Output: capture/compare mode register 3 (output mode)
	// Position of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Pos = 0x2
	// Bit mask of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Msk = 0x4
	// Bit OC5FE.
	TIM_CCMR3_Output_OC5FE = 0x4
	// Position of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Pos = 0x3
	// Bit mask of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Msk = 0x8
	// Bit OC5PE.
	TIM_CCMR3_Output_OC5PE = 0x8
	// Position of OC5M field.
	TIM_CCMR3_Output_OC5M_Pos = 0x4
	// Bit mask of OC5M field.
	TIM_CCMR3_Output_OC5M_Msk = 0x70
	// Position of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Pos = 0x7
	// Bit mask of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Msk = 0x80
	// Bit OC5CE.
	TIM_CCMR3_Output_OC5CE = 0x80
	// Position of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Pos = 0xa
	// Bit mask of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Msk = 0x400
	// Bit OC6FE.
	TIM_CCMR3_Output_OC6FE = 0x400
	// Position of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Pos = 0xb
	// Bit mask of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Msk = 0x800
	// Bit OC6PE.
	TIM_CCMR3_Output_OC6PE = 0x800
	// Position of OC6M field.
	TIM_CCMR3_Output_OC6M_Pos = 0xc
	// Bit mask of OC6M field.
	TIM_CCMR3_Output_OC6M_Msk = 0x7000
	// Position of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Pos = 0xf
	// Bit mask of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Msk = 0x8000
	// Bit OC6CE.
	TIM_CCMR3_Output_OC6CE = 0x8000
	// Position of OC5M3 field.
	TIM_CCMR3_Output_OC5M3_Pos = 0x10
	// Bit mask of OC5M3 field.
	TIM_CCMR3_Output_OC5M3_Msk = 0x10000
	// Bit OC5M3.
	TIM_CCMR3_Output_OC5M3 = 0x10000
	// Position of OC6M3 field.
	TIM_CCMR3_Output_OC6M3_Pos = 0x18
	// Bit mask of OC6M3 field.
	TIM_CCMR3_Output_OC6M3_Msk = 0x1000000
	// Bit OC6M3.
	TIM_CCMR3_Output_OC6M3 = 0x1000000

	// CCR5: capture/compare register 5
	// Position of CCR field.
	TIM_CCR5_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR5_CCR_Msk = 0xffff
	// Position of GC5C1 field.
	TIM_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM_CCR5_GC5C3 = 0x80000000

	// CRR6: capture/compare register 6
	// Position of CCR6 field.
	TIM_CRR6_CCR6_Pos = 0x0
	// Bit mask of CCR6 field.
	TIM_CRR6_CCR6_Msk = 0xffff

	// AF1: TIM1 alternate function option register 1
	// Position of BKINE field.
	TIM_AF1_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIM_AF1_BKINE_Msk = 0x1
	// Bit BKINE.
	TIM_AF1_BKINE = 0x1
	// Position of BKCMP1E field.
	TIM_AF1_BKCMP1E_Pos = 0x1
	// Bit mask of BKCMP1E field.
	TIM_AF1_BKCMP1E_Msk = 0x2
	// Bit BKCMP1E.
	TIM_AF1_BKCMP1E = 0x2
	// Position of BKCMP2E field.
	TIM_AF1_BKCMP2E_Pos = 0x2
	// Bit mask of BKCMP2E field.
	TIM_AF1_BKCMP2E_Msk = 0x4
	// Bit BKCMP2E.
	TIM_AF1_BKCMP2E = 0x4
	// Position of BKDF1BK0E field.
	TIM_AF1_BKDF1BK0E_Pos = 0x8
	// Bit mask of BKDF1BK0E field.
	TIM_AF1_BKDF1BK0E_Msk = 0x100
	// Bit BKDF1BK0E.
	TIM_AF1_BKDF1BK0E = 0x100
	// Position of BKINP field.
	TIM_AF1_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIM_AF1_BKINP_Msk = 0x200
	// Bit BKINP.
	TIM_AF1_BKINP = 0x200
	// Position of BKCMP1P field.
	TIM_AF1_BKCMP1P_Pos = 0xa
	// Bit mask of BKCMP1P field.
	TIM_AF1_BKCMP1P_Msk = 0x400
	// Bit BKCMP1P.
	TIM_AF1_BKCMP1P = 0x400
	// Position of BKCMP2P field.
	TIM_AF1_BKCMP2P_Pos = 0xb
	// Bit mask of BKCMP2P field.
	TIM_AF1_BKCMP2P_Msk = 0x800
	// Bit BKCMP2P.
	TIM_AF1_BKCMP2P = 0x800
	// Position of ETRSEL field.
	TIM_AF1_ETRSEL_Pos = 0xe
	// Bit mask of ETRSEL field.
	TIM_AF1_ETRSEL_Msk = 0x3c000

	// AF2: TIM1 Alternate function odfsdm1_breakster 2
	// Position of BK2INE field.
	TIM_AF2_BK2INE_Pos = 0x0
	// Bit mask of BK2INE field.
	TIM_AF2_BK2INE_Msk = 0x1
	// Bit BK2INE.
	TIM_AF2_BK2INE = 0x1
	// Position of BK2CMP1E field.
	TIM_AF2_BK2CMP1E_Pos = 0x1
	// Bit mask of BK2CMP1E field.
	TIM_AF2_BK2CMP1E_Msk = 0x2
	// Bit BK2CMP1E.
	TIM_AF2_BK2CMP1E = 0x2
	// Position of BK2CMP2E field.
	TIM_AF2_BK2CMP2E_Pos = 0x2
	// Bit mask of BK2CMP2E field.
	TIM_AF2_BK2CMP2E_Msk = 0x4
	// Bit BK2CMP2E.
	TIM_AF2_BK2CMP2E = 0x4
	// Position of BK2DF1BK1E field.
	TIM_AF2_BK2DF1BK1E_Pos = 0x8
	// Bit mask of BK2DF1BK1E field.
	TIM_AF2_BK2DF1BK1E_Msk = 0x100
	// Bit BK2DF1BK1E.
	TIM_AF2_BK2DF1BK1E = 0x100
	// Position of BK2INP field.
	TIM_AF2_BK2INP_Pos = 0x9
	// Bit mask of BK2INP field.
	TIM_AF2_BK2INP_Msk = 0x200
	// Bit BK2INP.
	TIM_AF2_BK2INP = 0x200
	// Position of BK2CMP1P field.
	TIM_AF2_BK2CMP1P_Pos = 0xa
	// Bit mask of BK2CMP1P field.
	TIM_AF2_BK2CMP1P_Msk = 0x400
	// Bit BK2CMP1P.
	TIM_AF2_BK2CMP1P = 0x400
	// Position of BK2CMP2P field.
	TIM_AF2_BK2CMP2P_Pos = 0xb
	// Bit mask of BK2CMP2P field.
	TIM_AF2_BK2CMP2P_Msk = 0x800
	// Bit BK2CMP2P.
	TIM_AF2_BK2CMP2P = 0x800

	// TISEL: TIM1 timer input selection register
	// Position of TI1SEL field.
	TIM_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM_TISEL_TI1SEL_Msk = 0xf
	// Position of TI2SEL field.
	TIM_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIM_TISEL_TI2SEL_Msk = 0xf00
	// Position of TI3SEL field.
	TIM_TISEL_TI3SEL_Pos = 0x10
	// Bit mask of TI3SEL field.
	TIM_TISEL_TI3SEL_Msk = 0xf0000
	// Position of TI4SEL field.
	TIM_TISEL_TI4SEL_Pos = 0x18
	// Bit mask of TI4SEL field.
	TIM_TISEL_TI4SEL_Msk = 0xf000000
)

// Bitfields for FDCAN1: FDCAN1
const (
	// CREL: FDCAN Core Release Register
	// Position of REL field.
	FDCAN_CREL_REL_Pos = 0x1c
	// Bit mask of REL field.
	FDCAN_CREL_REL_Msk = 0xf0000000
	// Position of STEP field.
	FDCAN_CREL_STEP_Pos = 0x18
	// Bit mask of STEP field.
	FDCAN_CREL_STEP_Msk = 0xf000000
	// Position of SUBSTEP field.
	FDCAN_CREL_SUBSTEP_Pos = 0x14
	// Bit mask of SUBSTEP field.
	FDCAN_CREL_SUBSTEP_Msk = 0xf00000
	// Position of YEAR field.
	FDCAN_CREL_YEAR_Pos = 0x10
	// Bit mask of YEAR field.
	FDCAN_CREL_YEAR_Msk = 0xf0000
	// Position of MON field.
	FDCAN_CREL_MON_Pos = 0x8
	// Bit mask of MON field.
	FDCAN_CREL_MON_Msk = 0xff00
	// Position of DAY field.
	FDCAN_CREL_DAY_Pos = 0x0
	// Bit mask of DAY field.
	FDCAN_CREL_DAY_Msk = 0xff

	// ENDN: FDCAN Core Release Register
	// Position of ETV field.
	FDCAN_ENDN_ETV_Pos = 0x0
	// Bit mask of ETV field.
	FDCAN_ENDN_ETV_Msk = 0xffffffff

	// DBTP: FDCAN Data Bit Timing and Prescaler Register
	// Position of DSJW field.
	FDCAN_DBTP_DSJW_Pos = 0x0
	// Bit mask of DSJW field.
	FDCAN_DBTP_DSJW_Msk = 0xf
	// Position of DTSEG2 field.
	FDCAN_DBTP_DTSEG2_Pos = 0x4
	// Bit mask of DTSEG2 field.
	FDCAN_DBTP_DTSEG2_Msk = 0xf0
	// Position of DTSEG1 field.
	FDCAN_DBTP_DTSEG1_Pos = 0x8
	// Bit mask of DTSEG1 field.
	FDCAN_DBTP_DTSEG1_Msk = 0x1f00
	// Position of DBRP field.
	FDCAN_DBTP_DBRP_Pos = 0x10
	// Bit mask of DBRP field.
	FDCAN_DBTP_DBRP_Msk = 0x1f0000
	// Position of TDC field.
	FDCAN_DBTP_TDC_Pos = 0x17
	// Bit mask of TDC field.
	FDCAN_DBTP_TDC_Msk = 0x800000
	// Bit TDC.
	FDCAN_DBTP_TDC = 0x800000

	// TEST: FDCAN Test Register
	// Position of LBCK field.
	FDCAN_TEST_LBCK_Pos = 0x4
	// Bit mask of LBCK field.
	FDCAN_TEST_LBCK_Msk = 0x10
	// Bit LBCK.
	FDCAN_TEST_LBCK = 0x10
	// Position of TX field.
	FDCAN_TEST_TX_Pos = 0x5
	// Bit mask of TX field.
	FDCAN_TEST_TX_Msk = 0x60
	// Position of RX field.
	FDCAN_TEST_RX_Pos = 0x7
	// Bit mask of RX field.
	FDCAN_TEST_RX_Msk = 0x80
	// Bit RX.
	FDCAN_TEST_RX = 0x80

	// RWD: FDCAN RAM Watchdog Register
	// Position of WDV field.
	FDCAN_RWD_WDV_Pos = 0x8
	// Bit mask of WDV field.
	FDCAN_RWD_WDV_Msk = 0xff00
	// Position of WDC field.
	FDCAN_RWD_WDC_Pos = 0x0
	// Bit mask of WDC field.
	FDCAN_RWD_WDC_Msk = 0xff

	// CCCR: FDCAN CC Control Register
	// Position of INIT field.
	FDCAN_CCCR_INIT_Pos = 0x0
	// Bit mask of INIT field.
	FDCAN_CCCR_INIT_Msk = 0x1
	// Bit INIT.
	FDCAN_CCCR_INIT = 0x1
	// Position of CCE field.
	FDCAN_CCCR_CCE_Pos = 0x1
	// Bit mask of CCE field.
	FDCAN_CCCR_CCE_Msk = 0x2
	// Bit CCE.
	FDCAN_CCCR_CCE = 0x2
	// Position of ASM field.
	FDCAN_CCCR_ASM_Pos = 0x2
	// Bit mask of ASM field.
	FDCAN_CCCR_ASM_Msk = 0x4
	// Bit ASM.
	FDCAN_CCCR_ASM = 0x4
	// Position of CSA field.
	FDCAN_CCCR_CSA_Pos = 0x3
	// Bit mask of CSA field.
	FDCAN_CCCR_CSA_Msk = 0x8
	// Bit CSA.
	FDCAN_CCCR_CSA = 0x8
	// Position of CSR field.
	FDCAN_CCCR_CSR_Pos = 0x4
	// Bit mask of CSR field.
	FDCAN_CCCR_CSR_Msk = 0x10
	// Bit CSR.
	FDCAN_CCCR_CSR = 0x10
	// Position of MON field.
	FDCAN_CCCR_MON_Pos = 0x5
	// Bit mask of MON field.
	FDCAN_CCCR_MON_Msk = 0x20
	// Bit MON.
	FDCAN_CCCR_MON = 0x20
	// Position of DAR field.
	FDCAN_CCCR_DAR_Pos = 0x6
	// Bit mask of DAR field.
	FDCAN_CCCR_DAR_Msk = 0x40
	// Bit DAR.
	FDCAN_CCCR_DAR = 0x40
	// Position of TEST field.
	FDCAN_CCCR_TEST_Pos = 0x7
	// Bit mask of TEST field.
	FDCAN_CCCR_TEST_Msk = 0x80
	// Bit TEST.
	FDCAN_CCCR_TEST = 0x80
	// Position of FDOE field.
	FDCAN_CCCR_FDOE_Pos = 0x8
	// Bit mask of FDOE field.
	FDCAN_CCCR_FDOE_Msk = 0x100
	// Bit FDOE.
	FDCAN_CCCR_FDOE = 0x100
	// Position of BSE field.
	FDCAN_CCCR_BSE_Pos = 0x9
	// Bit mask of BSE field.
	FDCAN_CCCR_BSE_Msk = 0x200
	// Bit BSE.
	FDCAN_CCCR_BSE = 0x200
	// Position of PXHD field.
	FDCAN_CCCR_PXHD_Pos = 0xc
	// Bit mask of PXHD field.
	FDCAN_CCCR_PXHD_Msk = 0x1000
	// Bit PXHD.
	FDCAN_CCCR_PXHD = 0x1000
	// Position of EFBI field.
	FDCAN_CCCR_EFBI_Pos = 0xd
	// Bit mask of EFBI field.
	FDCAN_CCCR_EFBI_Msk = 0x2000
	// Bit EFBI.
	FDCAN_CCCR_EFBI = 0x2000
	// Position of TXP field.
	FDCAN_CCCR_TXP_Pos = 0xe
	// Bit mask of TXP field.
	FDCAN_CCCR_TXP_Msk = 0x4000
	// Bit TXP.
	FDCAN_CCCR_TXP = 0x4000
	// Position of NISO field.
	FDCAN_CCCR_NISO_Pos = 0xf
	// Bit mask of NISO field.
	FDCAN_CCCR_NISO_Msk = 0x8000
	// Bit NISO.
	FDCAN_CCCR_NISO = 0x8000

	// NBTP: FDCAN Nominal Bit Timing and Prescaler Register
	// Position of NSJW field.
	FDCAN_NBTP_NSJW_Pos = 0x19
	// Bit mask of NSJW field.
	FDCAN_NBTP_NSJW_Msk = 0xfe000000
	// Position of NBRP field.
	FDCAN_NBTP_NBRP_Pos = 0x10
	// Bit mask of NBRP field.
	FDCAN_NBTP_NBRP_Msk = 0x1ff0000
	// Position of NTSEG1 field.
	FDCAN_NBTP_NTSEG1_Pos = 0x8
	// Bit mask of NTSEG1 field.
	FDCAN_NBTP_NTSEG1_Msk = 0xff00
	// Position of NTSEG2 field.
	FDCAN_NBTP_NTSEG2_Pos = 0x0
	// Bit mask of NTSEG2 field.
	FDCAN_NBTP_NTSEG2_Msk = 0x7f

	// TSCC: FDCAN Timestamp Counter Configuration Register
	// Position of TCP field.
	FDCAN_TSCC_TCP_Pos = 0x10
	// Bit mask of TCP field.
	FDCAN_TSCC_TCP_Msk = 0xf0000
	// Position of TSS field.
	FDCAN_TSCC_TSS_Pos = 0x0
	// Bit mask of TSS field.
	FDCAN_TSCC_TSS_Msk = 0x3

	// TSCV: FDCAN Timestamp Counter Value Register
	// Position of TSC field.
	FDCAN_TSCV_TSC_Pos = 0x0
	// Bit mask of TSC field.
	FDCAN_TSCV_TSC_Msk = 0xffff

	// TOCC: FDCAN Timeout Counter Configuration Register
	// Position of ETOC field.
	FDCAN_TOCC_ETOC_Pos = 0x0
	// Bit mask of ETOC field.
	FDCAN_TOCC_ETOC_Msk = 0x1
	// Bit ETOC.
	FDCAN_TOCC_ETOC = 0x1
	// Position of TOS field.
	FDCAN_TOCC_TOS_Pos = 0x1
	// Bit mask of TOS field.
	FDCAN_TOCC_TOS_Msk = 0x6
	// Position of TOP field.
	FDCAN_TOCC_TOP_Pos = 0x10
	// Bit mask of TOP field.
	FDCAN_TOCC_TOP_Msk = 0xffff0000

	// TOCV: FDCAN Timeout Counter Value Register
	// Position of TOC field.
	FDCAN_TOCV_TOC_Pos = 0x0
	// Bit mask of TOC field.
	FDCAN_TOCV_TOC_Msk = 0xffff

	// ECR: FDCAN Error Counter Register
	// Position of CEL field.
	FDCAN_ECR_CEL_Pos = 0x10
	// Bit mask of CEL field.
	FDCAN_ECR_CEL_Msk = 0xff0000
	// Position of RP field.
	FDCAN_ECR_RP_Pos = 0xf
	// Bit mask of RP field.
	FDCAN_ECR_RP_Msk = 0x8000
	// Bit RP.
	FDCAN_ECR_RP = 0x8000
	// Position of REC field.
	FDCAN_ECR_REC_Pos = 0x8
	// Bit mask of REC field.
	FDCAN_ECR_REC_Msk = 0x7f00
	// Position of TEC field.
	FDCAN_ECR_TEC_Pos = 0x0
	// Bit mask of TEC field.
	FDCAN_ECR_TEC_Msk = 0xff

	// PSR: FDCAN Protocol Status Register
	// Position of LEC field.
	FDCAN_PSR_LEC_Pos = 0x0
	// Bit mask of LEC field.
	FDCAN_PSR_LEC_Msk = 0x7
	// Position of ACT field.
	FDCAN_PSR_ACT_Pos = 0x3
	// Bit mask of ACT field.
	FDCAN_PSR_ACT_Msk = 0x18
	// Position of EP field.
	FDCAN_PSR_EP_Pos = 0x5
	// Bit mask of EP field.
	FDCAN_PSR_EP_Msk = 0x20
	// Bit EP.
	FDCAN_PSR_EP = 0x20
	// Position of EW field.
	FDCAN_PSR_EW_Pos = 0x6
	// Bit mask of EW field.
	FDCAN_PSR_EW_Msk = 0x40
	// Bit EW.
	FDCAN_PSR_EW = 0x40
	// Position of BO field.
	FDCAN_PSR_BO_Pos = 0x7
	// Bit mask of BO field.
	FDCAN_PSR_BO_Msk = 0x80
	// Bit BO.
	FDCAN_PSR_BO = 0x80
	// Position of DLEC field.
	FDCAN_PSR_DLEC_Pos = 0x8
	// Bit mask of DLEC field.
	FDCAN_PSR_DLEC_Msk = 0x700
	// Position of RESI field.
	FDCAN_PSR_RESI_Pos = 0xb
	// Bit mask of RESI field.
	FDCAN_PSR_RESI_Msk = 0x800
	// Bit RESI.
	FDCAN_PSR_RESI = 0x800
	// Position of RBRS field.
	FDCAN_PSR_RBRS_Pos = 0xc
	// Bit mask of RBRS field.
	FDCAN_PSR_RBRS_Msk = 0x1000
	// Bit RBRS.
	FDCAN_PSR_RBRS = 0x1000
	// Position of REDL field.
	FDCAN_PSR_REDL_Pos = 0xd
	// Bit mask of REDL field.
	FDCAN_PSR_REDL_Msk = 0x2000
	// Bit REDL.
	FDCAN_PSR_REDL = 0x2000
	// Position of PXE field.
	FDCAN_PSR_PXE_Pos = 0xe
	// Bit mask of PXE field.
	FDCAN_PSR_PXE_Msk = 0x4000
	// Bit PXE.
	FDCAN_PSR_PXE = 0x4000
	// Position of TDCV field.
	FDCAN_PSR_TDCV_Pos = 0x10
	// Bit mask of TDCV field.
	FDCAN_PSR_TDCV_Msk = 0x7f0000

	// TDCR: FDCAN Transmitter Delay Compensation Register
	// Position of TDCF field.
	FDCAN_TDCR_TDCF_Pos = 0x0
	// Bit mask of TDCF field.
	FDCAN_TDCR_TDCF_Msk = 0x7f
	// Position of TDCO field.
	FDCAN_TDCR_TDCO_Pos = 0x8
	// Bit mask of TDCO field.
	FDCAN_TDCR_TDCO_Msk = 0x7f00

	// IR: FDCAN Interrupt Register
	// Position of RF0N field.
	FDCAN_IR_RF0N_Pos = 0x0
	// Bit mask of RF0N field.
	FDCAN_IR_RF0N_Msk = 0x1
	// Bit RF0N.
	FDCAN_IR_RF0N = 0x1
	// Position of RF0W field.
	FDCAN_IR_RF0W_Pos = 0x1
	// Bit mask of RF0W field.
	FDCAN_IR_RF0W_Msk = 0x2
	// Bit RF0W.
	FDCAN_IR_RF0W = 0x2
	// Position of RF0F field.
	FDCAN_IR_RF0F_Pos = 0x2
	// Bit mask of RF0F field.
	FDCAN_IR_RF0F_Msk = 0x4
	// Bit RF0F.
	FDCAN_IR_RF0F = 0x4
	// Position of RF0L field.
	FDCAN_IR_RF0L_Pos = 0x3
	// Bit mask of RF0L field.
	FDCAN_IR_RF0L_Msk = 0x8
	// Bit RF0L.
	FDCAN_IR_RF0L = 0x8
	// Position of RF1N field.
	FDCAN_IR_RF1N_Pos = 0x4
	// Bit mask of RF1N field.
	FDCAN_IR_RF1N_Msk = 0x10
	// Bit RF1N.
	FDCAN_IR_RF1N = 0x10
	// Position of RF1W field.
	FDCAN_IR_RF1W_Pos = 0x5
	// Bit mask of RF1W field.
	FDCAN_IR_RF1W_Msk = 0x20
	// Bit RF1W.
	FDCAN_IR_RF1W = 0x20
	// Position of RF1F field.
	FDCAN_IR_RF1F_Pos = 0x6
	// Bit mask of RF1F field.
	FDCAN_IR_RF1F_Msk = 0x40
	// Bit RF1F.
	FDCAN_IR_RF1F = 0x40
	// Position of RF1L field.
	FDCAN_IR_RF1L_Pos = 0x7
	// Bit mask of RF1L field.
	FDCAN_IR_RF1L_Msk = 0x80
	// Bit RF1L.
	FDCAN_IR_RF1L = 0x80
	// Position of HPM field.
	FDCAN_IR_HPM_Pos = 0x8
	// Bit mask of HPM field.
	FDCAN_IR_HPM_Msk = 0x100
	// Bit HPM.
	FDCAN_IR_HPM = 0x100
	// Position of TC field.
	FDCAN_IR_TC_Pos = 0x9
	// Bit mask of TC field.
	FDCAN_IR_TC_Msk = 0x200
	// Bit TC.
	FDCAN_IR_TC = 0x200
	// Position of TCF field.
	FDCAN_IR_TCF_Pos = 0xa
	// Bit mask of TCF field.
	FDCAN_IR_TCF_Msk = 0x400
	// Bit TCF.
	FDCAN_IR_TCF = 0x400
	// Position of TEF field.
	FDCAN_IR_TEF_Pos = 0xb
	// Bit mask of TEF field.
	FDCAN_IR_TEF_Msk = 0x800
	// Bit TEF.
	FDCAN_IR_TEF = 0x800
	// Position of TEFN field.
	FDCAN_IR_TEFN_Pos = 0xc
	// Bit mask of TEFN field.
	FDCAN_IR_TEFN_Msk = 0x1000
	// Bit TEFN.
	FDCAN_IR_TEFN = 0x1000
	// Position of TEFW field.
	FDCAN_IR_TEFW_Pos = 0xd
	// Bit mask of TEFW field.
	FDCAN_IR_TEFW_Msk = 0x2000
	// Bit TEFW.
	FDCAN_IR_TEFW = 0x2000
	// Position of TEFF field.
	FDCAN_IR_TEFF_Pos = 0xe
	// Bit mask of TEFF field.
	FDCAN_IR_TEFF_Msk = 0x4000
	// Bit TEFF.
	FDCAN_IR_TEFF = 0x4000
	// Position of TEFL field.
	FDCAN_IR_TEFL_Pos = 0xf
	// Bit mask of TEFL field.
	FDCAN_IR_TEFL_Msk = 0x8000
	// Bit TEFL.
	FDCAN_IR_TEFL = 0x8000
	// Position of TSW field.
	FDCAN_IR_TSW_Pos = 0x10
	// Bit mask of TSW field.
	FDCAN_IR_TSW_Msk = 0x10000
	// Bit TSW.
	FDCAN_IR_TSW = 0x10000
	// Position of MRAF field.
	FDCAN_IR_MRAF_Pos = 0x11
	// Bit mask of MRAF field.
	FDCAN_IR_MRAF_Msk = 0x20000
	// Bit MRAF.
	FDCAN_IR_MRAF = 0x20000
	// Position of TOO field.
	FDCAN_IR_TOO_Pos = 0x12
	// Bit mask of TOO field.
	FDCAN_IR_TOO_Msk = 0x40000
	// Bit TOO.
	FDCAN_IR_TOO = 0x40000
	// Position of DRX field.
	FDCAN_IR_DRX_Pos = 0x13
	// Bit mask of DRX field.
	FDCAN_IR_DRX_Msk = 0x80000
	// Bit DRX.
	FDCAN_IR_DRX = 0x80000
	// Position of ELO field.
	FDCAN_IR_ELO_Pos = 0x16
	// Bit mask of ELO field.
	FDCAN_IR_ELO_Msk = 0x400000
	// Bit ELO.
	FDCAN_IR_ELO = 0x400000
	// Position of EP field.
	FDCAN_IR_EP_Pos = 0x17
	// Bit mask of EP field.
	FDCAN_IR_EP_Msk = 0x800000
	// Bit EP.
	FDCAN_IR_EP = 0x800000
	// Position of EW field.
	FDCAN_IR_EW_Pos = 0x18
	// Bit mask of EW field.
	FDCAN_IR_EW_Msk = 0x1000000
	// Bit EW.
	FDCAN_IR_EW = 0x1000000
	// Position of BO field.
	FDCAN_IR_BO_Pos = 0x19
	// Bit mask of BO field.
	FDCAN_IR_BO_Msk = 0x2000000
	// Bit BO.
	FDCAN_IR_BO = 0x2000000
	// Position of WDI field.
	FDCAN_IR_WDI_Pos = 0x1a
	// Bit mask of WDI field.
	FDCAN_IR_WDI_Msk = 0x4000000
	// Bit WDI.
	FDCAN_IR_WDI = 0x4000000
	// Position of PEA field.
	FDCAN_IR_PEA_Pos = 0x1b
	// Bit mask of PEA field.
	FDCAN_IR_PEA_Msk = 0x8000000
	// Bit PEA.
	FDCAN_IR_PEA = 0x8000000
	// Position of PED field.
	FDCAN_IR_PED_Pos = 0x1c
	// Bit mask of PED field.
	FDCAN_IR_PED_Msk = 0x10000000
	// Bit PED.
	FDCAN_IR_PED = 0x10000000
	// Position of ARA field.
	FDCAN_IR_ARA_Pos = 0x1d
	// Bit mask of ARA field.
	FDCAN_IR_ARA_Msk = 0x20000000
	// Bit ARA.
	FDCAN_IR_ARA = 0x20000000

	// IE: FDCAN Interrupt Enable Register
	// Position of RF0NE field.
	FDCAN_IE_RF0NE_Pos = 0x0
	// Bit mask of RF0NE field.
	FDCAN_IE_RF0NE_Msk = 0x1
	// Bit RF0NE.
	FDCAN_IE_RF0NE = 0x1
	// Position of RF0WE field.
	FDCAN_IE_RF0WE_Pos = 0x1
	// Bit mask of RF0WE field.
	FDCAN_IE_RF0WE_Msk = 0x2
	// Bit RF0WE.
	FDCAN_IE_RF0WE = 0x2
	// Position of RF0FE field.
	FDCAN_IE_RF0FE_Pos = 0x2
	// Bit mask of RF0FE field.
	FDCAN_IE_RF0FE_Msk = 0x4
	// Bit RF0FE.
	FDCAN_IE_RF0FE = 0x4
	// Position of RF0LE field.
	FDCAN_IE_RF0LE_Pos = 0x3
	// Bit mask of RF0LE field.
	FDCAN_IE_RF0LE_Msk = 0x8
	// Bit RF0LE.
	FDCAN_IE_RF0LE = 0x8
	// Position of RF1NE field.
	FDCAN_IE_RF1NE_Pos = 0x4
	// Bit mask of RF1NE field.
	FDCAN_IE_RF1NE_Msk = 0x10
	// Bit RF1NE.
	FDCAN_IE_RF1NE = 0x10
	// Position of RF1WE field.
	FDCAN_IE_RF1WE_Pos = 0x5
	// Bit mask of RF1WE field.
	FDCAN_IE_RF1WE_Msk = 0x20
	// Bit RF1WE.
	FDCAN_IE_RF1WE = 0x20
	// Position of RF1FE field.
	FDCAN_IE_RF1FE_Pos = 0x6
	// Bit mask of RF1FE field.
	FDCAN_IE_RF1FE_Msk = 0x40
	// Bit RF1FE.
	FDCAN_IE_RF1FE = 0x40
	// Position of RF1LE field.
	FDCAN_IE_RF1LE_Pos = 0x7
	// Bit mask of RF1LE field.
	FDCAN_IE_RF1LE_Msk = 0x80
	// Bit RF1LE.
	FDCAN_IE_RF1LE = 0x80
	// Position of HPME field.
	FDCAN_IE_HPME_Pos = 0x8
	// Bit mask of HPME field.
	FDCAN_IE_HPME_Msk = 0x100
	// Bit HPME.
	FDCAN_IE_HPME = 0x100
	// Position of TCE field.
	FDCAN_IE_TCE_Pos = 0x9
	// Bit mask of TCE field.
	FDCAN_IE_TCE_Msk = 0x200
	// Bit TCE.
	FDCAN_IE_TCE = 0x200
	// Position of TCFE field.
	FDCAN_IE_TCFE_Pos = 0xa
	// Bit mask of TCFE field.
	FDCAN_IE_TCFE_Msk = 0x400
	// Bit TCFE.
	FDCAN_IE_TCFE = 0x400
	// Position of TEFE field.
	FDCAN_IE_TEFE_Pos = 0xb
	// Bit mask of TEFE field.
	FDCAN_IE_TEFE_Msk = 0x800
	// Bit TEFE.
	FDCAN_IE_TEFE = 0x800
	// Position of TEFNE field.
	FDCAN_IE_TEFNE_Pos = 0xc
	// Bit mask of TEFNE field.
	FDCAN_IE_TEFNE_Msk = 0x1000
	// Bit TEFNE.
	FDCAN_IE_TEFNE = 0x1000
	// Position of TEFWE field.
	FDCAN_IE_TEFWE_Pos = 0xd
	// Bit mask of TEFWE field.
	FDCAN_IE_TEFWE_Msk = 0x2000
	// Bit TEFWE.
	FDCAN_IE_TEFWE = 0x2000
	// Position of TEFFE field.
	FDCAN_IE_TEFFE_Pos = 0xe
	// Bit mask of TEFFE field.
	FDCAN_IE_TEFFE_Msk = 0x4000
	// Bit TEFFE.
	FDCAN_IE_TEFFE = 0x4000
	// Position of TEFLE field.
	FDCAN_IE_TEFLE_Pos = 0xf
	// Bit mask of TEFLE field.
	FDCAN_IE_TEFLE_Msk = 0x8000
	// Bit TEFLE.
	FDCAN_IE_TEFLE = 0x8000
	// Position of TSWE field.
	FDCAN_IE_TSWE_Pos = 0x10
	// Bit mask of TSWE field.
	FDCAN_IE_TSWE_Msk = 0x10000
	// Bit TSWE.
	FDCAN_IE_TSWE = 0x10000
	// Position of MRAFE field.
	FDCAN_IE_MRAFE_Pos = 0x11
	// Bit mask of MRAFE field.
	FDCAN_IE_MRAFE_Msk = 0x20000
	// Bit MRAFE.
	FDCAN_IE_MRAFE = 0x20000
	// Position of TOOE field.
	FDCAN_IE_TOOE_Pos = 0x12
	// Bit mask of TOOE field.
	FDCAN_IE_TOOE_Msk = 0x40000
	// Bit TOOE.
	FDCAN_IE_TOOE = 0x40000
	// Position of DRXE field.
	FDCAN_IE_DRXE_Pos = 0x13
	// Bit mask of DRXE field.
	FDCAN_IE_DRXE_Msk = 0x80000
	// Bit DRXE.
	FDCAN_IE_DRXE = 0x80000
	// Position of BECE field.
	FDCAN_IE_BECE_Pos = 0x14
	// Bit mask of BECE field.
	FDCAN_IE_BECE_Msk = 0x100000
	// Bit BECE.
	FDCAN_IE_BECE = 0x100000
	// Position of BEUE field.
	FDCAN_IE_BEUE_Pos = 0x15
	// Bit mask of BEUE field.
	FDCAN_IE_BEUE_Msk = 0x200000
	// Bit BEUE.
	FDCAN_IE_BEUE = 0x200000
	// Position of ELOE field.
	FDCAN_IE_ELOE_Pos = 0x16
	// Bit mask of ELOE field.
	FDCAN_IE_ELOE_Msk = 0x400000
	// Bit ELOE.
	FDCAN_IE_ELOE = 0x400000
	// Position of EPE field.
	FDCAN_IE_EPE_Pos = 0x17
	// Bit mask of EPE field.
	FDCAN_IE_EPE_Msk = 0x800000
	// Bit EPE.
	FDCAN_IE_EPE = 0x800000
	// Position of EWE field.
	FDCAN_IE_EWE_Pos = 0x18
	// Bit mask of EWE field.
	FDCAN_IE_EWE_Msk = 0x1000000
	// Bit EWE.
	FDCAN_IE_EWE = 0x1000000
	// Position of BOE field.
	FDCAN_IE_BOE_Pos = 0x19
	// Bit mask of BOE field.
	FDCAN_IE_BOE_Msk = 0x2000000
	// Bit BOE.
	FDCAN_IE_BOE = 0x2000000
	// Position of WDIE field.
	FDCAN_IE_WDIE_Pos = 0x1a
	// Bit mask of WDIE field.
	FDCAN_IE_WDIE_Msk = 0x4000000
	// Bit WDIE.
	FDCAN_IE_WDIE = 0x4000000
	// Position of PEAE field.
	FDCAN_IE_PEAE_Pos = 0x1b
	// Bit mask of PEAE field.
	FDCAN_IE_PEAE_Msk = 0x8000000
	// Bit PEAE.
	FDCAN_IE_PEAE = 0x8000000
	// Position of PEDE field.
	FDCAN_IE_PEDE_Pos = 0x1c
	// Bit mask of PEDE field.
	FDCAN_IE_PEDE_Msk = 0x10000000
	// Bit PEDE.
	FDCAN_IE_PEDE = 0x10000000
	// Position of ARAE field.
	FDCAN_IE_ARAE_Pos = 0x1d
	// Bit mask of ARAE field.
	FDCAN_IE_ARAE_Msk = 0x20000000
	// Bit ARAE.
	FDCAN_IE_ARAE = 0x20000000

	// ILS: FDCAN Interrupt Line Select Register
	// Position of RF0NL field.
	FDCAN_ILS_RF0NL_Pos = 0x0
	// Bit mask of RF0NL field.
	FDCAN_ILS_RF0NL_Msk = 0x1
	// Bit RF0NL.
	FDCAN_ILS_RF0NL = 0x1
	// Position of RF0WL field.
	FDCAN_ILS_RF0WL_Pos = 0x1
	// Bit mask of RF0WL field.
	FDCAN_ILS_RF0WL_Msk = 0x2
	// Bit RF0WL.
	FDCAN_ILS_RF0WL = 0x2
	// Position of RF0FL field.
	FDCAN_ILS_RF0FL_Pos = 0x2
	// Bit mask of RF0FL field.
	FDCAN_ILS_RF0FL_Msk = 0x4
	// Bit RF0FL.
	FDCAN_ILS_RF0FL = 0x4
	// Position of RF0LL field.
	FDCAN_ILS_RF0LL_Pos = 0x3
	// Bit mask of RF0LL field.
	FDCAN_ILS_RF0LL_Msk = 0x8
	// Bit RF0LL.
	FDCAN_ILS_RF0LL = 0x8
	// Position of RF1NL field.
	FDCAN_ILS_RF1NL_Pos = 0x4
	// Bit mask of RF1NL field.
	FDCAN_ILS_RF1NL_Msk = 0x10
	// Bit RF1NL.
	FDCAN_ILS_RF1NL = 0x10
	// Position of RF1WL field.
	FDCAN_ILS_RF1WL_Pos = 0x5
	// Bit mask of RF1WL field.
	FDCAN_ILS_RF1WL_Msk = 0x20
	// Bit RF1WL.
	FDCAN_ILS_RF1WL = 0x20
	// Position of RF1FL field.
	FDCAN_ILS_RF1FL_Pos = 0x6
	// Bit mask of RF1FL field.
	FDCAN_ILS_RF1FL_Msk = 0x40
	// Bit RF1FL.
	FDCAN_ILS_RF1FL = 0x40
	// Position of RF1LL field.
	FDCAN_ILS_RF1LL_Pos = 0x7
	// Bit mask of RF1LL field.
	FDCAN_ILS_RF1LL_Msk = 0x80
	// Bit RF1LL.
	FDCAN_ILS_RF1LL = 0x80
	// Position of HPML field.
	FDCAN_ILS_HPML_Pos = 0x8
	// Bit mask of HPML field.
	FDCAN_ILS_HPML_Msk = 0x100
	// Bit HPML.
	FDCAN_ILS_HPML = 0x100
	// Position of TCL field.
	FDCAN_ILS_TCL_Pos = 0x9
	// Bit mask of TCL field.
	FDCAN_ILS_TCL_Msk = 0x200
	// Bit TCL.
	FDCAN_ILS_TCL = 0x200
	// Position of TCFL field.
	FDCAN_ILS_TCFL_Pos = 0xa
	// Bit mask of TCFL field.
	FDCAN_ILS_TCFL_Msk = 0x400
	// Bit TCFL.
	FDCAN_ILS_TCFL = 0x400
	// Position of TEFL field.
	FDCAN_ILS_TEFL_Pos = 0xb
	// Bit mask of TEFL field.
	FDCAN_ILS_TEFL_Msk = 0x800
	// Bit TEFL.
	FDCAN_ILS_TEFL = 0x800
	// Position of TEFNL field.
	FDCAN_ILS_TEFNL_Pos = 0xc
	// Bit mask of TEFNL field.
	FDCAN_ILS_TEFNL_Msk = 0x1000
	// Bit TEFNL.
	FDCAN_ILS_TEFNL = 0x1000
	// Position of TEFWL field.
	FDCAN_ILS_TEFWL_Pos = 0xd
	// Bit mask of TEFWL field.
	FDCAN_ILS_TEFWL_Msk = 0x2000
	// Bit TEFWL.
	FDCAN_ILS_TEFWL = 0x2000
	// Position of TEFFL field.
	FDCAN_ILS_TEFFL_Pos = 0xe
	// Bit mask of TEFFL field.
	FDCAN_ILS_TEFFL_Msk = 0x4000
	// Bit TEFFL.
	FDCAN_ILS_TEFFL = 0x4000
	// Position of TEFLL field.
	FDCAN_ILS_TEFLL_Pos = 0xf
	// Bit mask of TEFLL field.
	FDCAN_ILS_TEFLL_Msk = 0x8000
	// Bit TEFLL.
	FDCAN_ILS_TEFLL = 0x8000
	// Position of TSWL field.
	FDCAN_ILS_TSWL_Pos = 0x10
	// Bit mask of TSWL field.
	FDCAN_ILS_TSWL_Msk = 0x10000
	// Bit TSWL.
	FDCAN_ILS_TSWL = 0x10000
	// Position of MRAFL field.
	FDCAN_ILS_MRAFL_Pos = 0x11
	// Bit mask of MRAFL field.
	FDCAN_ILS_MRAFL_Msk = 0x20000
	// Bit MRAFL.
	FDCAN_ILS_MRAFL = 0x20000
	// Position of TOOL field.
	FDCAN_ILS_TOOL_Pos = 0x12
	// Bit mask of TOOL field.
	FDCAN_ILS_TOOL_Msk = 0x40000
	// Bit TOOL.
	FDCAN_ILS_TOOL = 0x40000
	// Position of DRXL field.
	FDCAN_ILS_DRXL_Pos = 0x13
	// Bit mask of DRXL field.
	FDCAN_ILS_DRXL_Msk = 0x80000
	// Bit DRXL.
	FDCAN_ILS_DRXL = 0x80000
	// Position of BECL field.
	FDCAN_ILS_BECL_Pos = 0x14
	// Bit mask of BECL field.
	FDCAN_ILS_BECL_Msk = 0x100000
	// Bit BECL.
	FDCAN_ILS_BECL = 0x100000
	// Position of BEUL field.
	FDCAN_ILS_BEUL_Pos = 0x15
	// Bit mask of BEUL field.
	FDCAN_ILS_BEUL_Msk = 0x200000
	// Bit BEUL.
	FDCAN_ILS_BEUL = 0x200000
	// Position of ELOL field.
	FDCAN_ILS_ELOL_Pos = 0x16
	// Bit mask of ELOL field.
	FDCAN_ILS_ELOL_Msk = 0x400000
	// Bit ELOL.
	FDCAN_ILS_ELOL = 0x400000
	// Position of EPL field.
	FDCAN_ILS_EPL_Pos = 0x17
	// Bit mask of EPL field.
	FDCAN_ILS_EPL_Msk = 0x800000
	// Bit EPL.
	FDCAN_ILS_EPL = 0x800000
	// Position of EWL field.
	FDCAN_ILS_EWL_Pos = 0x18
	// Bit mask of EWL field.
	FDCAN_ILS_EWL_Msk = 0x1000000
	// Bit EWL.
	FDCAN_ILS_EWL = 0x1000000
	// Position of BOL field.
	FDCAN_ILS_BOL_Pos = 0x19
	// Bit mask of BOL field.
	FDCAN_ILS_BOL_Msk = 0x2000000
	// Bit BOL.
	FDCAN_ILS_BOL = 0x2000000
	// Position of WDIL field.
	FDCAN_ILS_WDIL_Pos = 0x1a
	// Bit mask of WDIL field.
	FDCAN_ILS_WDIL_Msk = 0x4000000
	// Bit WDIL.
	FDCAN_ILS_WDIL = 0x4000000
	// Position of PEAL field.
	FDCAN_ILS_PEAL_Pos = 0x1b
	// Bit mask of PEAL field.
	FDCAN_ILS_PEAL_Msk = 0x8000000
	// Bit PEAL.
	FDCAN_ILS_PEAL = 0x8000000
	// Position of PEDL field.
	FDCAN_ILS_PEDL_Pos = 0x1c
	// Bit mask of PEDL field.
	FDCAN_ILS_PEDL_Msk = 0x10000000
	// Bit PEDL.
	FDCAN_ILS_PEDL = 0x10000000
	// Position of ARAL field.
	FDCAN_ILS_ARAL_Pos = 0x1d
	// Bit mask of ARAL field.
	FDCAN_ILS_ARAL_Msk = 0x20000000
	// Bit ARAL.
	FDCAN_ILS_ARAL = 0x20000000

	// ILE: FDCAN Interrupt Line Enable Register
	// Position of EINT0 field.
	FDCAN_ILE_EINT0_Pos = 0x0
	// Bit mask of EINT0 field.
	FDCAN_ILE_EINT0_Msk = 0x1
	// Bit EINT0.
	FDCAN_ILE_EINT0 = 0x1
	// Position of EINT1 field.
	FDCAN_ILE_EINT1_Pos = 0x1
	// Bit mask of EINT1 field.
	FDCAN_ILE_EINT1_Msk = 0x2
	// Bit EINT1.
	FDCAN_ILE_EINT1 = 0x2

	// GFC: FDCAN Global Filter Configuration Register
	// Position of RRFE field.
	FDCAN_GFC_RRFE_Pos = 0x0
	// Bit mask of RRFE field.
	FDCAN_GFC_RRFE_Msk = 0x1
	// Bit RRFE.
	FDCAN_GFC_RRFE = 0x1
	// Position of RRFS field.
	FDCAN_GFC_RRFS_Pos = 0x1
	// Bit mask of RRFS field.
	FDCAN_GFC_RRFS_Msk = 0x2
	// Bit RRFS.
	FDCAN_GFC_RRFS = 0x2
	// Position of ANFE field.
	FDCAN_GFC_ANFE_Pos = 0x2
	// Bit mask of ANFE field.
	FDCAN_GFC_ANFE_Msk = 0xc
	// Position of ANFS field.
	FDCAN_GFC_ANFS_Pos = 0x4
	// Bit mask of ANFS field.
	FDCAN_GFC_ANFS_Msk = 0x30

	// SIDFC: FDCAN Standard ID Filter Configuration Register
	// Position of FLSSA field.
	FDCAN_SIDFC_FLSSA_Pos = 0x2
	// Bit mask of FLSSA field.
	FDCAN_SIDFC_FLSSA_Msk = 0xfffc
	// Position of LSS field.
	FDCAN_SIDFC_LSS_Pos = 0x10
	// Bit mask of LSS field.
	FDCAN_SIDFC_LSS_Msk = 0xff0000

	// XIDFC: FDCAN Extended ID Filter Configuration Register
	// Position of FLESA field.
	FDCAN_XIDFC_FLESA_Pos = 0x2
	// Bit mask of FLESA field.
	FDCAN_XIDFC_FLESA_Msk = 0xfffc
	// Position of LSE field.
	FDCAN_XIDFC_LSE_Pos = 0x10
	// Bit mask of LSE field.
	FDCAN_XIDFC_LSE_Msk = 0xff0000

	// XIDAM: FDCAN Extended ID and Mask Register
	// Position of EIDM field.
	FDCAN_XIDAM_EIDM_Pos = 0x0
	// Bit mask of EIDM field.
	FDCAN_XIDAM_EIDM_Msk = 0x1fffffff

	// HPMS: FDCAN High Priority Message Status Register
	// Position of BIDX field.
	FDCAN_HPMS_BIDX_Pos = 0x0
	// Bit mask of BIDX field.
	FDCAN_HPMS_BIDX_Msk = 0x3f
	// Position of MSI field.
	FDCAN_HPMS_MSI_Pos = 0x6
	// Bit mask of MSI field.
	FDCAN_HPMS_MSI_Msk = 0xc0
	// Position of FIDX field.
	FDCAN_HPMS_FIDX_Pos = 0x8
	// Bit mask of FIDX field.
	FDCAN_HPMS_FIDX_Msk = 0x7f00
	// Position of FLST field.
	FDCAN_HPMS_FLST_Pos = 0xf
	// Bit mask of FLST field.
	FDCAN_HPMS_FLST_Msk = 0x8000
	// Bit FLST.
	FDCAN_HPMS_FLST = 0x8000

	// NDAT1: FDCAN New Data 1 Register
	// Position of ND0 field.
	FDCAN_NDAT1_ND0_Pos = 0x0
	// Bit mask of ND0 field.
	FDCAN_NDAT1_ND0_Msk = 0x1
	// Bit ND0.
	FDCAN_NDAT1_ND0 = 0x1
	// Position of ND1 field.
	FDCAN_NDAT1_ND1_Pos = 0x1
	// Bit mask of ND1 field.
	FDCAN_NDAT1_ND1_Msk = 0x2
	// Bit ND1.
	FDCAN_NDAT1_ND1 = 0x2
	// Position of ND2 field.
	FDCAN_NDAT1_ND2_Pos = 0x2
	// Bit mask of ND2 field.
	FDCAN_NDAT1_ND2_Msk = 0x4
	// Bit ND2.
	FDCAN_NDAT1_ND2 = 0x4
	// Position of ND3 field.
	FDCAN_NDAT1_ND3_Pos = 0x3
	// Bit mask of ND3 field.
	FDCAN_NDAT1_ND3_Msk = 0x8
	// Bit ND3.
	FDCAN_NDAT1_ND3 = 0x8
	// Position of ND4 field.
	FDCAN_NDAT1_ND4_Pos = 0x4
	// Bit mask of ND4 field.
	FDCAN_NDAT1_ND4_Msk = 0x10
	// Bit ND4.
	FDCAN_NDAT1_ND4 = 0x10
	// Position of ND5 field.
	FDCAN_NDAT1_ND5_Pos = 0x5
	// Bit mask of ND5 field.
	FDCAN_NDAT1_ND5_Msk = 0x20
	// Bit ND5.
	FDCAN_NDAT1_ND5 = 0x20
	// Position of ND6 field.
	FDCAN_NDAT1_ND6_Pos = 0x6
	// Bit mask of ND6 field.
	FDCAN_NDAT1_ND6_Msk = 0x40
	// Bit ND6.
	FDCAN_NDAT1_ND6 = 0x40
	// Position of ND7 field.
	FDCAN_NDAT1_ND7_Pos = 0x7
	// Bit mask of ND7 field.
	FDCAN_NDAT1_ND7_Msk = 0x80
	// Bit ND7.
	FDCAN_NDAT1_ND7 = 0x80
	// Position of ND8 field.
	FDCAN_NDAT1_ND8_Pos = 0x8
	// Bit mask of ND8 field.
	FDCAN_NDAT1_ND8_Msk = 0x100
	// Bit ND8.
	FDCAN_NDAT1_ND8 = 0x100
	// Position of ND9 field.
	FDCAN_NDAT1_ND9_Pos = 0x9
	// Bit mask of ND9 field.
	FDCAN_NDAT1_ND9_Msk = 0x200
	// Bit ND9.
	FDCAN_NDAT1_ND9 = 0x200
	// Position of ND10 field.
	FDCAN_NDAT1_ND10_Pos = 0xa
	// Bit mask of ND10 field.
	FDCAN_NDAT1_ND10_Msk = 0x400
	// Bit ND10.
	FDCAN_NDAT1_ND10 = 0x400
	// Position of ND11 field.
	FDCAN_NDAT1_ND11_Pos = 0xb
	// Bit mask of ND11 field.
	FDCAN_NDAT1_ND11_Msk = 0x800
	// Bit ND11.
	FDCAN_NDAT1_ND11 = 0x800
	// Position of ND12 field.
	FDCAN_NDAT1_ND12_Pos = 0xc
	// Bit mask of ND12 field.
	FDCAN_NDAT1_ND12_Msk = 0x1000
	// Bit ND12.
	FDCAN_NDAT1_ND12 = 0x1000
	// Position of ND13 field.
	FDCAN_NDAT1_ND13_Pos = 0xd
	// Bit mask of ND13 field.
	FDCAN_NDAT1_ND13_Msk = 0x2000
	// Bit ND13.
	FDCAN_NDAT1_ND13 = 0x2000
	// Position of ND14 field.
	FDCAN_NDAT1_ND14_Pos = 0xe
	// Bit mask of ND14 field.
	FDCAN_NDAT1_ND14_Msk = 0x4000
	// Bit ND14.
	FDCAN_NDAT1_ND14 = 0x4000
	// Position of ND15 field.
	FDCAN_NDAT1_ND15_Pos = 0xf
	// Bit mask of ND15 field.
	FDCAN_NDAT1_ND15_Msk = 0x8000
	// Bit ND15.
	FDCAN_NDAT1_ND15 = 0x8000
	// Position of ND16 field.
	FDCAN_NDAT1_ND16_Pos = 0x10
	// Bit mask of ND16 field.
	FDCAN_NDAT1_ND16_Msk = 0x10000
	// Bit ND16.
	FDCAN_NDAT1_ND16 = 0x10000
	// Position of ND17 field.
	FDCAN_NDAT1_ND17_Pos = 0x11
	// Bit mask of ND17 field.
	FDCAN_NDAT1_ND17_Msk = 0x20000
	// Bit ND17.
	FDCAN_NDAT1_ND17 = 0x20000
	// Position of ND18 field.
	FDCAN_NDAT1_ND18_Pos = 0x12
	// Bit mask of ND18 field.
	FDCAN_NDAT1_ND18_Msk = 0x40000
	// Bit ND18.
	FDCAN_NDAT1_ND18 = 0x40000
	// Position of ND19 field.
	FDCAN_NDAT1_ND19_Pos = 0x13
	// Bit mask of ND19 field.
	FDCAN_NDAT1_ND19_Msk = 0x80000
	// Bit ND19.
	FDCAN_NDAT1_ND19 = 0x80000
	// Position of ND20 field.
	FDCAN_NDAT1_ND20_Pos = 0x14
	// Bit mask of ND20 field.
	FDCAN_NDAT1_ND20_Msk = 0x100000
	// Bit ND20.
	FDCAN_NDAT1_ND20 = 0x100000
	// Position of ND21 field.
	FDCAN_NDAT1_ND21_Pos = 0x15
	// Bit mask of ND21 field.
	FDCAN_NDAT1_ND21_Msk = 0x200000
	// Bit ND21.
	FDCAN_NDAT1_ND21 = 0x200000
	// Position of ND22 field.
	FDCAN_NDAT1_ND22_Pos = 0x16
	// Bit mask of ND22 field.
	FDCAN_NDAT1_ND22_Msk = 0x400000
	// Bit ND22.
	FDCAN_NDAT1_ND22 = 0x400000
	// Position of ND23 field.
	FDCAN_NDAT1_ND23_Pos = 0x17
	// Bit mask of ND23 field.
	FDCAN_NDAT1_ND23_Msk = 0x800000
	// Bit ND23.
	FDCAN_NDAT1_ND23 = 0x800000
	// Position of ND24 field.
	FDCAN_NDAT1_ND24_Pos = 0x18
	// Bit mask of ND24 field.
	FDCAN_NDAT1_ND24_Msk = 0x1000000
	// Bit ND24.
	FDCAN_NDAT1_ND24 = 0x1000000
	// Position of ND25 field.
	FDCAN_NDAT1_ND25_Pos = 0x19
	// Bit mask of ND25 field.
	FDCAN_NDAT1_ND25_Msk = 0x2000000
	// Bit ND25.
	FDCAN_NDAT1_ND25 = 0x2000000
	// Position of ND26 field.
	FDCAN_NDAT1_ND26_Pos = 0x1a
	// Bit mask of ND26 field.
	FDCAN_NDAT1_ND26_Msk = 0x4000000
	// Bit ND26.
	FDCAN_NDAT1_ND26 = 0x4000000
	// Position of ND27 field.
	FDCAN_NDAT1_ND27_Pos = 0x1b
	// Bit mask of ND27 field.
	FDCAN_NDAT1_ND27_Msk = 0x8000000
	// Bit ND27.
	FDCAN_NDAT1_ND27 = 0x8000000
	// Position of ND28 field.
	FDCAN_NDAT1_ND28_Pos = 0x1c
	// Bit mask of ND28 field.
	FDCAN_NDAT1_ND28_Msk = 0x10000000
	// Bit ND28.
	FDCAN_NDAT1_ND28 = 0x10000000
	// Position of ND29 field.
	FDCAN_NDAT1_ND29_Pos = 0x1d
	// Bit mask of ND29 field.
	FDCAN_NDAT1_ND29_Msk = 0x20000000
	// Bit ND29.
	FDCAN_NDAT1_ND29 = 0x20000000
	// Position of ND30 field.
	FDCAN_NDAT1_ND30_Pos = 0x1e
	// Bit mask of ND30 field.
	FDCAN_NDAT1_ND30_Msk = 0x40000000
	// Bit ND30.
	FDCAN_NDAT1_ND30 = 0x40000000
	// Position of ND31 field.
	FDCAN_NDAT1_ND31_Pos = 0x1f
	// Bit mask of ND31 field.
	FDCAN_NDAT1_ND31_Msk = 0x80000000
	// Bit ND31.
	FDCAN_NDAT1_ND31 = 0x80000000

	// NDAT2: FDCAN New Data 2 Register
	// Position of ND32 field.
	FDCAN_NDAT2_ND32_Pos = 0x0
	// Bit mask of ND32 field.
	FDCAN_NDAT2_ND32_Msk = 0x1
	// Bit ND32.
	FDCAN_NDAT2_ND32 = 0x1
	// Position of ND33 field.
	FDCAN_NDAT2_ND33_Pos = 0x1
	// Bit mask of ND33 field.
	FDCAN_NDAT2_ND33_Msk = 0x2
	// Bit ND33.
	FDCAN_NDAT2_ND33 = 0x2
	// Position of ND34 field.
	FDCAN_NDAT2_ND34_Pos = 0x2
	// Bit mask of ND34 field.
	FDCAN_NDAT2_ND34_Msk = 0x4
	// Bit ND34.
	FDCAN_NDAT2_ND34 = 0x4
	// Position of ND35 field.
	FDCAN_NDAT2_ND35_Pos = 0x3
	// Bit mask of ND35 field.
	FDCAN_NDAT2_ND35_Msk = 0x8
	// Bit ND35.
	FDCAN_NDAT2_ND35 = 0x8
	// Position of ND36 field.
	FDCAN_NDAT2_ND36_Pos = 0x4
	// Bit mask of ND36 field.
	FDCAN_NDAT2_ND36_Msk = 0x10
	// Bit ND36.
	FDCAN_NDAT2_ND36 = 0x10
	// Position of ND37 field.
	FDCAN_NDAT2_ND37_Pos = 0x5
	// Bit mask of ND37 field.
	FDCAN_NDAT2_ND37_Msk = 0x20
	// Bit ND37.
	FDCAN_NDAT2_ND37 = 0x20
	// Position of ND38 field.
	FDCAN_NDAT2_ND38_Pos = 0x6
	// Bit mask of ND38 field.
	FDCAN_NDAT2_ND38_Msk = 0x40
	// Bit ND38.
	FDCAN_NDAT2_ND38 = 0x40
	// Position of ND39 field.
	FDCAN_NDAT2_ND39_Pos = 0x7
	// Bit mask of ND39 field.
	FDCAN_NDAT2_ND39_Msk = 0x80
	// Bit ND39.
	FDCAN_NDAT2_ND39 = 0x80
	// Position of ND40 field.
	FDCAN_NDAT2_ND40_Pos = 0x8
	// Bit mask of ND40 field.
	FDCAN_NDAT2_ND40_Msk = 0x100
	// Bit ND40.
	FDCAN_NDAT2_ND40 = 0x100
	// Position of ND41 field.
	FDCAN_NDAT2_ND41_Pos = 0x9
	// Bit mask of ND41 field.
	FDCAN_NDAT2_ND41_Msk = 0x200
	// Bit ND41.
	FDCAN_NDAT2_ND41 = 0x200
	// Position of ND42 field.
	FDCAN_NDAT2_ND42_Pos = 0xa
	// Bit mask of ND42 field.
	FDCAN_NDAT2_ND42_Msk = 0x400
	// Bit ND42.
	FDCAN_NDAT2_ND42 = 0x400
	// Position of ND43 field.
	FDCAN_NDAT2_ND43_Pos = 0xb
	// Bit mask of ND43 field.
	FDCAN_NDAT2_ND43_Msk = 0x800
	// Bit ND43.
	FDCAN_NDAT2_ND43 = 0x800
	// Position of ND44 field.
	FDCAN_NDAT2_ND44_Pos = 0xc
	// Bit mask of ND44 field.
	FDCAN_NDAT2_ND44_Msk = 0x1000
	// Bit ND44.
	FDCAN_NDAT2_ND44 = 0x1000
	// Position of ND45 field.
	FDCAN_NDAT2_ND45_Pos = 0xd
	// Bit mask of ND45 field.
	FDCAN_NDAT2_ND45_Msk = 0x2000
	// Bit ND45.
	FDCAN_NDAT2_ND45 = 0x2000
	// Position of ND46 field.
	FDCAN_NDAT2_ND46_Pos = 0xe
	// Bit mask of ND46 field.
	FDCAN_NDAT2_ND46_Msk = 0x4000
	// Bit ND46.
	FDCAN_NDAT2_ND46 = 0x4000
	// Position of ND47 field.
	FDCAN_NDAT2_ND47_Pos = 0xf
	// Bit mask of ND47 field.
	FDCAN_NDAT2_ND47_Msk = 0x8000
	// Bit ND47.
	FDCAN_NDAT2_ND47 = 0x8000
	// Position of ND48 field.
	FDCAN_NDAT2_ND48_Pos = 0x10
	// Bit mask of ND48 field.
	FDCAN_NDAT2_ND48_Msk = 0x10000
	// Bit ND48.
	FDCAN_NDAT2_ND48 = 0x10000
	// Position of ND49 field.
	FDCAN_NDAT2_ND49_Pos = 0x11
	// Bit mask of ND49 field.
	FDCAN_NDAT2_ND49_Msk = 0x20000
	// Bit ND49.
	FDCAN_NDAT2_ND49 = 0x20000
	// Position of ND50 field.
	FDCAN_NDAT2_ND50_Pos = 0x12
	// Bit mask of ND50 field.
	FDCAN_NDAT2_ND50_Msk = 0x40000
	// Bit ND50.
	FDCAN_NDAT2_ND50 = 0x40000
	// Position of ND51 field.
	FDCAN_NDAT2_ND51_Pos = 0x13
	// Bit mask of ND51 field.
	FDCAN_NDAT2_ND51_Msk = 0x80000
	// Bit ND51.
	FDCAN_NDAT2_ND51 = 0x80000
	// Position of ND52 field.
	FDCAN_NDAT2_ND52_Pos = 0x14
	// Bit mask of ND52 field.
	FDCAN_NDAT2_ND52_Msk = 0x100000
	// Bit ND52.
	FDCAN_NDAT2_ND52 = 0x100000
	// Position of ND53 field.
	FDCAN_NDAT2_ND53_Pos = 0x15
	// Bit mask of ND53 field.
	FDCAN_NDAT2_ND53_Msk = 0x200000
	// Bit ND53.
	FDCAN_NDAT2_ND53 = 0x200000
	// Position of ND54 field.
	FDCAN_NDAT2_ND54_Pos = 0x16
	// Bit mask of ND54 field.
	FDCAN_NDAT2_ND54_Msk = 0x400000
	// Bit ND54.
	FDCAN_NDAT2_ND54 = 0x400000
	// Position of ND55 field.
	FDCAN_NDAT2_ND55_Pos = 0x17
	// Bit mask of ND55 field.
	FDCAN_NDAT2_ND55_Msk = 0x800000
	// Bit ND55.
	FDCAN_NDAT2_ND55 = 0x800000
	// Position of ND56 field.
	FDCAN_NDAT2_ND56_Pos = 0x18
	// Bit mask of ND56 field.
	FDCAN_NDAT2_ND56_Msk = 0x1000000
	// Bit ND56.
	FDCAN_NDAT2_ND56 = 0x1000000
	// Position of ND57 field.
	FDCAN_NDAT2_ND57_Pos = 0x19
	// Bit mask of ND57 field.
	FDCAN_NDAT2_ND57_Msk = 0x2000000
	// Bit ND57.
	FDCAN_NDAT2_ND57 = 0x2000000
	// Position of ND58 field.
	FDCAN_NDAT2_ND58_Pos = 0x1a
	// Bit mask of ND58 field.
	FDCAN_NDAT2_ND58_Msk = 0x4000000
	// Bit ND58.
	FDCAN_NDAT2_ND58 = 0x4000000
	// Position of ND59 field.
	FDCAN_NDAT2_ND59_Pos = 0x1b
	// Bit mask of ND59 field.
	FDCAN_NDAT2_ND59_Msk = 0x8000000
	// Bit ND59.
	FDCAN_NDAT2_ND59 = 0x8000000
	// Position of ND60 field.
	FDCAN_NDAT2_ND60_Pos = 0x1c
	// Bit mask of ND60 field.
	FDCAN_NDAT2_ND60_Msk = 0x10000000
	// Bit ND60.
	FDCAN_NDAT2_ND60 = 0x10000000
	// Position of ND61 field.
	FDCAN_NDAT2_ND61_Pos = 0x1d
	// Bit mask of ND61 field.
	FDCAN_NDAT2_ND61_Msk = 0x20000000
	// Bit ND61.
	FDCAN_NDAT2_ND61 = 0x20000000
	// Position of ND62 field.
	FDCAN_NDAT2_ND62_Pos = 0x1e
	// Bit mask of ND62 field.
	FDCAN_NDAT2_ND62_Msk = 0x40000000
	// Bit ND62.
	FDCAN_NDAT2_ND62 = 0x40000000
	// Position of ND63 field.
	FDCAN_NDAT2_ND63_Pos = 0x1f
	// Bit mask of ND63 field.
	FDCAN_NDAT2_ND63_Msk = 0x80000000
	// Bit ND63.
	FDCAN_NDAT2_ND63 = 0x80000000

	// RXF0C: FDCAN Rx FIFO 0 Configuration Register
	// Position of F0SA field.
	FDCAN_RXF0C_F0SA_Pos = 0x2
	// Bit mask of F0SA field.
	FDCAN_RXF0C_F0SA_Msk = 0xfffc
	// Position of F0S field.
	FDCAN_RXF0C_F0S_Pos = 0x10
	// Bit mask of F0S field.
	FDCAN_RXF0C_F0S_Msk = 0x7f0000
	// Position of F0WM field.
	FDCAN_RXF0C_F0WM_Pos = 0x18
	// Bit mask of F0WM field.
	FDCAN_RXF0C_F0WM_Msk = 0x7f000000
	// Position of F0OM field.
	FDCAN_RXF0C_F0OM_Pos = 0x1f
	// Bit mask of F0OM field.
	FDCAN_RXF0C_F0OM_Msk = 0x80000000
	// Bit F0OM.
	FDCAN_RXF0C_F0OM = 0x80000000

	// RXF0S: FDCAN Rx FIFO 0 Status Register
	// Position of F0FL field.
	FDCAN_RXF0S_F0FL_Pos = 0x0
	// Bit mask of F0FL field.
	FDCAN_RXF0S_F0FL_Msk = 0x7f
	// Position of F0GI field.
	FDCAN_RXF0S_F0GI_Pos = 0x8
	// Bit mask of F0GI field.
	FDCAN_RXF0S_F0GI_Msk = 0x3f00
	// Position of F0PI field.
	FDCAN_RXF0S_F0PI_Pos = 0x10
	// Bit mask of F0PI field.
	FDCAN_RXF0S_F0PI_Msk = 0x3f0000
	// Position of F0F field.
	FDCAN_RXF0S_F0F_Pos = 0x18
	// Bit mask of F0F field.
	FDCAN_RXF0S_F0F_Msk = 0x1000000
	// Bit F0F.
	FDCAN_RXF0S_F0F = 0x1000000
	// Position of RF0L field.
	FDCAN_RXF0S_RF0L_Pos = 0x19
	// Bit mask of RF0L field.
	FDCAN_RXF0S_RF0L_Msk = 0x2000000
	// Bit RF0L.
	FDCAN_RXF0S_RF0L = 0x2000000

	// RXF0A: CAN Rx FIFO 0 Acknowledge Register
	// Position of F0AI field.
	FDCAN_RXF0A_F0AI_Pos = 0x0
	// Bit mask of F0AI field.
	FDCAN_RXF0A_F0AI_Msk = 0x3f

	// RXBC: FDCAN Rx Buffer Configuration Register
	// Position of RBSA field.
	FDCAN_RXBC_RBSA_Pos = 0x2
	// Bit mask of RBSA field.
	FDCAN_RXBC_RBSA_Msk = 0xfffc

	// RXF1C: FDCAN Rx FIFO 1 Configuration Register
	// Position of F1SA field.
	FDCAN_RXF1C_F1SA_Pos = 0x2
	// Bit mask of F1SA field.
	FDCAN_RXF1C_F1SA_Msk = 0xfffc
	// Position of F1S field.
	FDCAN_RXF1C_F1S_Pos = 0x10
	// Bit mask of F1S field.
	FDCAN_RXF1C_F1S_Msk = 0x7f0000
	// Position of F1WM field.
	FDCAN_RXF1C_F1WM_Pos = 0x18
	// Bit mask of F1WM field.
	FDCAN_RXF1C_F1WM_Msk = 0x7f000000
	// Position of F1OM field.
	FDCAN_RXF1C_F1OM_Pos = 0x1f
	// Bit mask of F1OM field.
	FDCAN_RXF1C_F1OM_Msk = 0x80000000
	// Bit F1OM.
	FDCAN_RXF1C_F1OM = 0x80000000

	// RXF1S: FDCAN Rx FIFO 1 Status Register
	// Position of F1FL field.
	FDCAN_RXF1S_F1FL_Pos = 0x0
	// Bit mask of F1FL field.
	FDCAN_RXF1S_F1FL_Msk = 0x7f
	// Position of F1GI field.
	FDCAN_RXF1S_F1GI_Pos = 0x8
	// Bit mask of F1GI field.
	FDCAN_RXF1S_F1GI_Msk = 0x7f00
	// Position of F1PI field.
	FDCAN_RXF1S_F1PI_Pos = 0x10
	// Bit mask of F1PI field.
	FDCAN_RXF1S_F1PI_Msk = 0x7f0000
	// Position of F1F field.
	FDCAN_RXF1S_F1F_Pos = 0x18
	// Bit mask of F1F field.
	FDCAN_RXF1S_F1F_Msk = 0x1000000
	// Bit F1F.
	FDCAN_RXF1S_F1F = 0x1000000
	// Position of RF1L field.
	FDCAN_RXF1S_RF1L_Pos = 0x19
	// Bit mask of RF1L field.
	FDCAN_RXF1S_RF1L_Msk = 0x2000000
	// Bit RF1L.
	FDCAN_RXF1S_RF1L = 0x2000000
	// Position of DMS field.
	FDCAN_RXF1S_DMS_Pos = 0x1e
	// Bit mask of DMS field.
	FDCAN_RXF1S_DMS_Msk = 0xc0000000

	// RXF1A: FDCAN Rx FIFO 1 Acknowledge Register
	// Position of F1AI field.
	FDCAN_RXF1A_F1AI_Pos = 0x0
	// Bit mask of F1AI field.
	FDCAN_RXF1A_F1AI_Msk = 0x3f

	// RXESC: FDCAN Rx Buffer Element Size Configuration Register
	// Position of F0DS field.
	FDCAN_RXESC_F0DS_Pos = 0x0
	// Bit mask of F0DS field.
	FDCAN_RXESC_F0DS_Msk = 0x7
	// Position of F1DS field.
	FDCAN_RXESC_F1DS_Pos = 0x4
	// Bit mask of F1DS field.
	FDCAN_RXESC_F1DS_Msk = 0x70
	// Position of RBDS field.
	FDCAN_RXESC_RBDS_Pos = 0x8
	// Bit mask of RBDS field.
	FDCAN_RXESC_RBDS_Msk = 0x700

	// TXBC: FDCAN Tx Buffer Configuration Register
	// Position of TBSA field.
	FDCAN_TXBC_TBSA_Pos = 0x2
	// Bit mask of TBSA field.
	FDCAN_TXBC_TBSA_Msk = 0xfffc
	// Position of NDTB field.
	FDCAN_TXBC_NDTB_Pos = 0x10
	// Bit mask of NDTB field.
	FDCAN_TXBC_NDTB_Msk = 0x3f0000
	// Position of TFQS field.
	FDCAN_TXBC_TFQS_Pos = 0x18
	// Bit mask of TFQS field.
	FDCAN_TXBC_TFQS_Msk = 0x3f000000
	// Position of TFQM field.
	FDCAN_TXBC_TFQM_Pos = 0x1e
	// Bit mask of TFQM field.
	FDCAN_TXBC_TFQM_Msk = 0x40000000
	// Bit TFQM.
	FDCAN_TXBC_TFQM = 0x40000000

	// TXFQS: FDCAN Tx FIFO/Queue Status Register
	// Position of TFFL field.
	FDCAN_TXFQS_TFFL_Pos = 0x0
	// Bit mask of TFFL field.
	FDCAN_TXFQS_TFFL_Msk = 0x3f
	// Position of TFGI field.
	FDCAN_TXFQS_TFGI_Pos = 0x8
	// Bit mask of TFGI field.
	FDCAN_TXFQS_TFGI_Msk = 0x1f00
	// Position of TFQPI field.
	FDCAN_TXFQS_TFQPI_Pos = 0x10
	// Bit mask of TFQPI field.
	FDCAN_TXFQS_TFQPI_Msk = 0x1f0000
	// Position of TFQF field.
	FDCAN_TXFQS_TFQF_Pos = 0x15
	// Bit mask of TFQF field.
	FDCAN_TXFQS_TFQF_Msk = 0x200000
	// Bit TFQF.
	FDCAN_TXFQS_TFQF = 0x200000

	// TXESC: FDCAN Tx Buffer Element Size Configuration Register
	// Position of TBDS field.
	FDCAN_TXESC_TBDS_Pos = 0x0
	// Bit mask of TBDS field.
	FDCAN_TXESC_TBDS_Msk = 0x7

	// TXBRP: FDCAN Tx Buffer Request Pending Register
	// Position of TRP field.
	FDCAN_TXBRP_TRP_Pos = 0x0
	// Bit mask of TRP field.
	FDCAN_TXBRP_TRP_Msk = 0xffffffff

	// TXBAR: FDCAN Tx Buffer Add Request Register
	// Position of AR field.
	FDCAN_TXBAR_AR_Pos = 0x0
	// Bit mask of AR field.
	FDCAN_TXBAR_AR_Msk = 0xffffffff

	// TXBCR: FDCAN Tx Buffer Cancellation Request Register
	// Position of CR field.
	FDCAN_TXBCR_CR_Pos = 0x0
	// Bit mask of CR field.
	FDCAN_TXBCR_CR_Msk = 0xffffffff

	// TXBTO: FDCAN Tx Buffer Transmission Occurred Register
	// Position of TO field.
	FDCAN_TXBTO_TO_Pos = 0x0
	// Bit mask of TO field.
	FDCAN_TXBTO_TO_Msk = 0xffffffff

	// TXBCF: FDCAN Tx Buffer Cancellation Finished Register
	// Position of CF field.
	FDCAN_TXBCF_CF_Pos = 0x0
	// Bit mask of CF field.
	FDCAN_TXBCF_CF_Msk = 0xffffffff

	// TXBTIE: FDCAN Tx Buffer Transmission Interrupt Enable Register
	// Position of TIE field.
	FDCAN_TXBTIE_TIE_Pos = 0x0
	// Bit mask of TIE field.
	FDCAN_TXBTIE_TIE_Msk = 0xffffffff

	// TXBCIE: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
	// Position of CF field.
	FDCAN_TXBCIE_CF_Pos = 0x0
	// Bit mask of CF field.
	FDCAN_TXBCIE_CF_Msk = 0xffffffff

	// TXEFC: FDCAN Tx Event FIFO Configuration Register
	// Position of EFSA field.
	FDCAN_TXEFC_EFSA_Pos = 0x2
	// Bit mask of EFSA field.
	FDCAN_TXEFC_EFSA_Msk = 0xfffc
	// Position of EFS field.
	FDCAN_TXEFC_EFS_Pos = 0x10
	// Bit mask of EFS field.
	FDCAN_TXEFC_EFS_Msk = 0x3f0000
	// Position of EFWM field.
	FDCAN_TXEFC_EFWM_Pos = 0x18
	// Bit mask of EFWM field.
	FDCAN_TXEFC_EFWM_Msk = 0x3f000000

	// TXEFS: FDCAN Tx Event FIFO Status Register
	// Position of EFFL field.
	FDCAN_TXEFS_EFFL_Pos = 0x0
	// Bit mask of EFFL field.
	FDCAN_TXEFS_EFFL_Msk = 0x3f
	// Position of EFGI field.
	FDCAN_TXEFS_EFGI_Pos = 0x8
	// Bit mask of EFGI field.
	FDCAN_TXEFS_EFGI_Msk = 0x1f00
	// Position of EFF field.
	FDCAN_TXEFS_EFF_Pos = 0x18
	// Bit mask of EFF field.
	FDCAN_TXEFS_EFF_Msk = 0x1000000
	// Bit EFF.
	FDCAN_TXEFS_EFF = 0x1000000
	// Position of TEFL field.
	FDCAN_TXEFS_TEFL_Pos = 0x19
	// Bit mask of TEFL field.
	FDCAN_TXEFS_TEFL_Msk = 0x2000000
	// Bit TEFL.
	FDCAN_TXEFS_TEFL = 0x2000000
	// Position of EFPI field.
	FDCAN_TXEFS_EFPI_Pos = 0x10
	// Bit mask of EFPI field.
	FDCAN_TXEFS_EFPI_Msk = 0x1f0000

	// TXEFA: FDCAN Tx Event FIFO Acknowledge Register
	// Position of EFAI field.
	FDCAN_TXEFA_EFAI_Pos = 0x0
	// Bit mask of EFAI field.
	FDCAN_TXEFA_EFAI_Msk = 0x1f

	// TTTMC: FDCAN TT Trigger Memory Configuration Register
	// Position of TMSA field.
	FDCAN_TTTMC_TMSA_Pos = 0x2
	// Bit mask of TMSA field.
	FDCAN_TTTMC_TMSA_Msk = 0xfffc
	// Position of TME field.
	FDCAN_TTTMC_TME_Pos = 0x10
	// Bit mask of TME field.
	FDCAN_TTTMC_TME_Msk = 0x7f0000

	// TTRMC: FDCAN TT Reference Message Configuration Register
	// Position of RID field.
	FDCAN_TTRMC_RID_Pos = 0x0
	// Bit mask of RID field.
	FDCAN_TTRMC_RID_Msk = 0x1fffffff
	// Position of XTD field.
	FDCAN_TTRMC_XTD_Pos = 0x1e
	// Bit mask of XTD field.
	FDCAN_TTRMC_XTD_Msk = 0x40000000
	// Bit XTD.
	FDCAN_TTRMC_XTD = 0x40000000
	// Position of RMPS field.
	FDCAN_TTRMC_RMPS_Pos = 0x1f
	// Bit mask of RMPS field.
	FDCAN_TTRMC_RMPS_Msk = 0x80000000
	// Bit RMPS.
	FDCAN_TTRMC_RMPS = 0x80000000

	// TTOCF: FDCAN TT Operation Configuration Register
	// Position of OM field.
	FDCAN_TTOCF_OM_Pos = 0x0
	// Bit mask of OM field.
	FDCAN_TTOCF_OM_Msk = 0x3
	// Position of GEN field.
	FDCAN_TTOCF_GEN_Pos = 0x3
	// Bit mask of GEN field.
	FDCAN_TTOCF_GEN_Msk = 0x8
	// Bit GEN.
	FDCAN_TTOCF_GEN = 0x8
	// Position of TM field.
	FDCAN_TTOCF_TM_Pos = 0x4
	// Bit mask of TM field.
	FDCAN_TTOCF_TM_Msk = 0x10
	// Bit TM.
	FDCAN_TTOCF_TM = 0x10
	// Position of LDSDL field.
	FDCAN_TTOCF_LDSDL_Pos = 0x5
	// Bit mask of LDSDL field.
	FDCAN_TTOCF_LDSDL_Msk = 0xe0
	// Position of IRTO field.
	FDCAN_TTOCF_IRTO_Pos = 0x8
	// Bit mask of IRTO field.
	FDCAN_TTOCF_IRTO_Msk = 0x7f00
	// Position of EECS field.
	FDCAN_TTOCF_EECS_Pos = 0xf
	// Bit mask of EECS field.
	FDCAN_TTOCF_EECS_Msk = 0x8000
	// Bit EECS.
	FDCAN_TTOCF_EECS = 0x8000
	// Position of AWL field.
	FDCAN_TTOCF_AWL_Pos = 0x10
	// Bit mask of AWL field.
	FDCAN_TTOCF_AWL_Msk = 0xff0000
	// Position of EGTF field.
	FDCAN_TTOCF_EGTF_Pos = 0x18
	// Bit mask of EGTF field.
	FDCAN_TTOCF_EGTF_Msk = 0x1000000
	// Bit EGTF.
	FDCAN_TTOCF_EGTF = 0x1000000
	// Position of ECC field.
	FDCAN_TTOCF_ECC_Pos = 0x19
	// Bit mask of ECC field.
	FDCAN_TTOCF_ECC_Msk = 0x2000000
	// Bit ECC.
	FDCAN_TTOCF_ECC = 0x2000000
	// Position of EVTP field.
	FDCAN_TTOCF_EVTP_Pos = 0x1a
	// Bit mask of EVTP field.
	FDCAN_TTOCF_EVTP_Msk = 0x4000000
	// Bit EVTP.
	FDCAN_TTOCF_EVTP = 0x4000000

	// TTMLM: FDCAN TT Matrix Limits Register
	// Position of CCM field.
	FDCAN_TTMLM_CCM_Pos = 0x0
	// Bit mask of CCM field.
	FDCAN_TTMLM_CCM_Msk = 0x3f
	// Position of CSS field.
	FDCAN_TTMLM_CSS_Pos = 0x6
	// Bit mask of CSS field.
	FDCAN_TTMLM_CSS_Msk = 0xc0
	// Position of TXEW field.
	FDCAN_TTMLM_TXEW_Pos = 0x8
	// Bit mask of TXEW field.
	FDCAN_TTMLM_TXEW_Msk = 0xf00
	// Position of ENTT field.
	FDCAN_TTMLM_ENTT_Pos = 0x10
	// Bit mask of ENTT field.
	FDCAN_TTMLM_ENTT_Msk = 0xfff0000

	// TURCF: FDCAN TUR Configuration Register
	// Position of NCL field.
	FDCAN_TURCF_NCL_Pos = 0x0
	// Bit mask of NCL field.
	FDCAN_TURCF_NCL_Msk = 0xffff
	// Position of DC field.
	FDCAN_TURCF_DC_Pos = 0x10
	// Bit mask of DC field.
	FDCAN_TURCF_DC_Msk = 0x3fff0000
	// Position of ELT field.
	FDCAN_TURCF_ELT_Pos = 0x1f
	// Bit mask of ELT field.
	FDCAN_TURCF_ELT_Msk = 0x80000000
	// Bit ELT.
	FDCAN_TURCF_ELT = 0x80000000

	// TTOCN: FDCAN TT Operation Control Register
	// Position of SGT field.
	FDCAN_TTOCN_SGT_Pos = 0x0
	// Bit mask of SGT field.
	FDCAN_TTOCN_SGT_Msk = 0x1
	// Bit SGT.
	FDCAN_TTOCN_SGT = 0x1
	// Position of ECS field.
	FDCAN_TTOCN_ECS_Pos = 0x1
	// Bit mask of ECS field.
	FDCAN_TTOCN_ECS_Msk = 0x2
	// Bit ECS.
	FDCAN_TTOCN_ECS = 0x2
	// Position of SWP field.
	FDCAN_TTOCN_SWP_Pos = 0x2
	// Bit mask of SWP field.
	FDCAN_TTOCN_SWP_Msk = 0x4
	// Bit SWP.
	FDCAN_TTOCN_SWP = 0x4
	// Position of SWS field.
	FDCAN_TTOCN_SWS_Pos = 0x3
	// Bit mask of SWS field.
	FDCAN_TTOCN_SWS_Msk = 0x18
	// Position of RTIE field.
	FDCAN_TTOCN_RTIE_Pos = 0x5
	// Bit mask of RTIE field.
	FDCAN_TTOCN_RTIE_Msk = 0x20
	// Bit RTIE.
	FDCAN_TTOCN_RTIE = 0x20
	// Position of TMC field.
	FDCAN_TTOCN_TMC_Pos = 0x6
	// Bit mask of TMC field.
	FDCAN_TTOCN_TMC_Msk = 0xc0
	// Position of TTIE field.
	FDCAN_TTOCN_TTIE_Pos = 0x8
	// Bit mask of TTIE field.
	FDCAN_TTOCN_TTIE_Msk = 0x100
	// Bit TTIE.
	FDCAN_TTOCN_TTIE = 0x100
	// Position of GCS field.
	FDCAN_TTOCN_GCS_Pos = 0x9
	// Bit mask of GCS field.
	FDCAN_TTOCN_GCS_Msk = 0x200
	// Bit GCS.
	FDCAN_TTOCN_GCS = 0x200
	// Position of FGP field.
	FDCAN_TTOCN_FGP_Pos = 0xa
	// Bit mask of FGP field.
	FDCAN_TTOCN_FGP_Msk = 0x400
	// Bit FGP.
	FDCAN_TTOCN_FGP = 0x400
	// Position of TMG field.
	FDCAN_TTOCN_TMG_Pos = 0xb
	// Bit mask of TMG field.
	FDCAN_TTOCN_TMG_Msk = 0x800
	// Bit TMG.
	FDCAN_TTOCN_TMG = 0x800
	// Position of NIG field.
	FDCAN_TTOCN_NIG_Pos = 0xc
	// Bit mask of NIG field.
	FDCAN_TTOCN_NIG_Msk = 0x1000
	// Bit NIG.
	FDCAN_TTOCN_NIG = 0x1000
	// Position of ESCN field.
	FDCAN_TTOCN_ESCN_Pos = 0xd
	// Bit mask of ESCN field.
	FDCAN_TTOCN_ESCN_Msk = 0x2000
	// Bit ESCN.
	FDCAN_TTOCN_ESCN = 0x2000
	// Position of LCKC field.
	FDCAN_TTOCN_LCKC_Pos = 0xf
	// Bit mask of LCKC field.
	FDCAN_TTOCN_LCKC_Msk = 0x8000
	// Bit LCKC.
	FDCAN_TTOCN_LCKC = 0x8000

	// TTGTP: FDCAN TT Global Time Preset Register
	// Position of NCL field.
	FDCAN_TTGTP_NCL_Pos = 0x0
	// Bit mask of NCL field.
	FDCAN_TTGTP_NCL_Msk = 0xffff
	// Position of CTP field.
	FDCAN_TTGTP_CTP_Pos = 0x10
	// Bit mask of CTP field.
	FDCAN_TTGTP_CTP_Msk = 0xffff0000

	// TTTMK: FDCAN TT Time Mark Register
	// Position of TM field.
	FDCAN_TTTMK_TM_Pos = 0x0
	// Bit mask of TM field.
	FDCAN_TTTMK_TM_Msk = 0xffff
	// Position of TICC field.
	FDCAN_TTTMK_TICC_Pos = 0x10
	// Bit mask of TICC field.
	FDCAN_TTTMK_TICC_Msk = 0x7f0000
	// Position of LCKM field.
	FDCAN_TTTMK_LCKM_Pos = 0x1f
	// Bit mask of LCKM field.
	FDCAN_TTTMK_LCKM_Msk = 0x80000000
	// Bit LCKM.
	FDCAN_TTTMK_LCKM = 0x80000000

	// TTIR: FDCAN TT Interrupt Register
	// Position of SBC field.
	FDCAN_TTIR_SBC_Pos = 0x0
	// Bit mask of SBC field.
	FDCAN_TTIR_SBC_Msk = 0x1
	// Bit SBC.
	FDCAN_TTIR_SBC = 0x1
	// Position of SMC field.
	FDCAN_TTIR_SMC_Pos = 0x1
	// Bit mask of SMC field.
	FDCAN_TTIR_SMC_Msk = 0x2
	// Bit SMC.
	FDCAN_TTIR_SMC = 0x2
	// Position of CSM field.
	FDCAN_TTIR_CSM_Pos = 0x2
	// Bit mask of CSM field.
	FDCAN_TTIR_CSM_Msk = 0x4
	// Bit CSM.
	FDCAN_TTIR_CSM = 0x4
	// Position of SOG field.
	FDCAN_TTIR_SOG_Pos = 0x3
	// Bit mask of SOG field.
	FDCAN_TTIR_SOG_Msk = 0x8
	// Bit SOG.
	FDCAN_TTIR_SOG = 0x8
	// Position of RTMI field.
	FDCAN_TTIR_RTMI_Pos = 0x4
	// Bit mask of RTMI field.
	FDCAN_TTIR_RTMI_Msk = 0x10
	// Bit RTMI.
	FDCAN_TTIR_RTMI = 0x10
	// Position of TTMI field.
	FDCAN_TTIR_TTMI_Pos = 0x5
	// Bit mask of TTMI field.
	FDCAN_TTIR_TTMI_Msk = 0x20
	// Bit TTMI.
	FDCAN_TTIR_TTMI = 0x20
	// Position of SWE field.
	FDCAN_TTIR_SWE_Pos = 0x6
	// Bit mask of SWE field.
	FDCAN_TTIR_SWE_Msk = 0x40
	// Bit SWE.
	FDCAN_TTIR_SWE = 0x40
	// Position of GTW field.
	FDCAN_TTIR_GTW_Pos = 0x7
	// Bit mask of GTW field.
	FDCAN_TTIR_GTW_Msk = 0x80
	// Bit GTW.
	FDCAN_TTIR_GTW = 0x80
	// Position of GTD field.
	FDCAN_TTIR_GTD_Pos = 0x8
	// Bit mask of GTD field.
	FDCAN_TTIR_GTD_Msk = 0x100
	// Bit GTD.
	FDCAN_TTIR_GTD = 0x100
	// Position of GTE field.
	FDCAN_TTIR_GTE_Pos = 0x9
	// Bit mask of GTE field.
	FDCAN_TTIR_GTE_Msk = 0x200
	// Bit GTE.
	FDCAN_TTIR_GTE = 0x200
	// Position of TXU field.
	FDCAN_TTIR_TXU_Pos = 0xa
	// Bit mask of TXU field.
	FDCAN_TTIR_TXU_Msk = 0x400
	// Bit TXU.
	FDCAN_TTIR_TXU = 0x400
	// Position of TXO field.
	FDCAN_TTIR_TXO_Pos = 0xb
	// Bit mask of TXO field.
	FDCAN_TTIR_TXO_Msk = 0x800
	// Bit TXO.
	FDCAN_TTIR_TXO = 0x800
	// Position of SE1 field.
	FDCAN_TTIR_SE1_Pos = 0xc
	// Bit mask of SE1 field.
	FDCAN_TTIR_SE1_Msk = 0x1000
	// Bit SE1.
	FDCAN_TTIR_SE1 = 0x1000
	// Position of SE2 field.
	FDCAN_TTIR_SE2_Pos = 0xd
	// Bit mask of SE2 field.
	FDCAN_TTIR_SE2_Msk = 0x2000
	// Bit SE2.
	FDCAN_TTIR_SE2 = 0x2000
	// Position of ELC field.
	FDCAN_TTIR_ELC_Pos = 0xe
	// Bit mask of ELC field.
	FDCAN_TTIR_ELC_Msk = 0x4000
	// Bit ELC.
	FDCAN_TTIR_ELC = 0x4000
	// Position of IWTG field.
	FDCAN_TTIR_IWTG_Pos = 0xf
	// Bit mask of IWTG field.
	FDCAN_TTIR_IWTG_Msk = 0x8000
	// Bit IWTG.
	FDCAN_TTIR_IWTG = 0x8000
	// Position of WT field.
	FDCAN_TTIR_WT_Pos = 0x10
	// Bit mask of WT field.
	FDCAN_TTIR_WT_Msk = 0x10000
	// Bit WT.
	FDCAN_TTIR_WT = 0x10000
	// Position of AW field.
	FDCAN_TTIR_AW_Pos = 0x11
	// Bit mask of AW field.
	FDCAN_TTIR_AW_Msk = 0x20000
	// Bit AW.
	FDCAN_TTIR_AW = 0x20000
	// Position of CER field.
	FDCAN_TTIR_CER_Pos = 0x12
	// Bit mask of CER field.
	FDCAN_TTIR_CER_Msk = 0x40000
	// Bit CER.
	FDCAN_TTIR_CER = 0x40000

	// TTIE: FDCAN TT Interrupt Enable Register
	// Position of SBCE field.
	FDCAN_TTIE_SBCE_Pos = 0x0
	// Bit mask of SBCE field.
	FDCAN_TTIE_SBCE_Msk = 0x1
	// Bit SBCE.
	FDCAN_TTIE_SBCE = 0x1
	// Position of SMCE field.
	FDCAN_TTIE_SMCE_Pos = 0x1
	// Bit mask of SMCE field.
	FDCAN_TTIE_SMCE_Msk = 0x2
	// Bit SMCE.
	FDCAN_TTIE_SMCE = 0x2
	// Position of CSME field.
	FDCAN_TTIE_CSME_Pos = 0x2
	// Bit mask of CSME field.
	FDCAN_TTIE_CSME_Msk = 0x4
	// Bit CSME.
	FDCAN_TTIE_CSME = 0x4
	// Position of SOGE field.
	FDCAN_TTIE_SOGE_Pos = 0x3
	// Bit mask of SOGE field.
	FDCAN_TTIE_SOGE_Msk = 0x8
	// Bit SOGE.
	FDCAN_TTIE_SOGE = 0x8
	// Position of RTMIE field.
	FDCAN_TTIE_RTMIE_Pos = 0x4
	// Bit mask of RTMIE field.
	FDCAN_TTIE_RTMIE_Msk = 0x10
	// Bit RTMIE.
	FDCAN_TTIE_RTMIE = 0x10
	// Position of TTMIE field.
	FDCAN_TTIE_TTMIE_Pos = 0x5
	// Bit mask of TTMIE field.
	FDCAN_TTIE_TTMIE_Msk = 0x20
	// Bit TTMIE.
	FDCAN_TTIE_TTMIE = 0x20
	// Position of SWEE field.
	FDCAN_TTIE_SWEE_Pos = 0x6
	// Bit mask of SWEE field.
	FDCAN_TTIE_SWEE_Msk = 0x40
	// Bit SWEE.
	FDCAN_TTIE_SWEE = 0x40
	// Position of GTWE field.
	FDCAN_TTIE_GTWE_Pos = 0x7
	// Bit mask of GTWE field.
	FDCAN_TTIE_GTWE_Msk = 0x80
	// Bit GTWE.
	FDCAN_TTIE_GTWE = 0x80
	// Position of GTDE field.
	FDCAN_TTIE_GTDE_Pos = 0x8
	// Bit mask of GTDE field.
	FDCAN_TTIE_GTDE_Msk = 0x100
	// Bit GTDE.
	FDCAN_TTIE_GTDE = 0x100
	// Position of GTEE field.
	FDCAN_TTIE_GTEE_Pos = 0x9
	// Bit mask of GTEE field.
	FDCAN_TTIE_GTEE_Msk = 0x200
	// Bit GTEE.
	FDCAN_TTIE_GTEE = 0x200
	// Position of TXUE field.
	FDCAN_TTIE_TXUE_Pos = 0xa
	// Bit mask of TXUE field.
	FDCAN_TTIE_TXUE_Msk = 0x400
	// Bit TXUE.
	FDCAN_TTIE_TXUE = 0x400
	// Position of TXOE field.
	FDCAN_TTIE_TXOE_Pos = 0xb
	// Bit mask of TXOE field.
	FDCAN_TTIE_TXOE_Msk = 0x800
	// Bit TXOE.
	FDCAN_TTIE_TXOE = 0x800
	// Position of SE1E field.
	FDCAN_TTIE_SE1E_Pos = 0xc
	// Bit mask of SE1E field.
	FDCAN_TTIE_SE1E_Msk = 0x1000
	// Bit SE1E.
	FDCAN_TTIE_SE1E = 0x1000
	// Position of SE2E field.
	FDCAN_TTIE_SE2E_Pos = 0xd
	// Bit mask of SE2E field.
	FDCAN_TTIE_SE2E_Msk = 0x2000
	// Bit SE2E.
	FDCAN_TTIE_SE2E = 0x2000
	// Position of ELCE field.
	FDCAN_TTIE_ELCE_Pos = 0xe
	// Bit mask of ELCE field.
	FDCAN_TTIE_ELCE_Msk = 0x4000
	// Bit ELCE.
	FDCAN_TTIE_ELCE = 0x4000
	// Position of IWTGE field.
	FDCAN_TTIE_IWTGE_Pos = 0xf
	// Bit mask of IWTGE field.
	FDCAN_TTIE_IWTGE_Msk = 0x8000
	// Bit IWTGE.
	FDCAN_TTIE_IWTGE = 0x8000
	// Position of WTE field.
	FDCAN_TTIE_WTE_Pos = 0x10
	// Bit mask of WTE field.
	FDCAN_TTIE_WTE_Msk = 0x10000
	// Bit WTE.
	FDCAN_TTIE_WTE = 0x10000
	// Position of AWE field.
	FDCAN_TTIE_AWE_Pos = 0x11
	// Bit mask of AWE field.
	FDCAN_TTIE_AWE_Msk = 0x20000
	// Bit AWE.
	FDCAN_TTIE_AWE = 0x20000
	// Position of CERE field.
	FDCAN_TTIE_CERE_Pos = 0x12
	// Bit mask of CERE field.
	FDCAN_TTIE_CERE_Msk = 0x40000
	// Bit CERE.
	FDCAN_TTIE_CERE = 0x40000

	// TTILS: FDCAN TT Interrupt Line Select Register
	// Position of SBCL field.
	FDCAN_TTILS_SBCL_Pos = 0x0
	// Bit mask of SBCL field.
	FDCAN_TTILS_SBCL_Msk = 0x1
	// Bit SBCL.
	FDCAN_TTILS_SBCL = 0x1
	// Position of SMCL field.
	FDCAN_TTILS_SMCL_Pos = 0x1
	// Bit mask of SMCL field.
	FDCAN_TTILS_SMCL_Msk = 0x2
	// Bit SMCL.
	FDCAN_TTILS_SMCL = 0x2
	// Position of CSML field.
	FDCAN_TTILS_CSML_Pos = 0x2
	// Bit mask of CSML field.
	FDCAN_TTILS_CSML_Msk = 0x4
	// Bit CSML.
	FDCAN_TTILS_CSML = 0x4
	// Position of SOGL field.
	FDCAN_TTILS_SOGL_Pos = 0x3
	// Bit mask of SOGL field.
	FDCAN_TTILS_SOGL_Msk = 0x8
	// Bit SOGL.
	FDCAN_TTILS_SOGL = 0x8
	// Position of RTMIL field.
	FDCAN_TTILS_RTMIL_Pos = 0x4
	// Bit mask of RTMIL field.
	FDCAN_TTILS_RTMIL_Msk = 0x10
	// Bit RTMIL.
	FDCAN_TTILS_RTMIL = 0x10
	// Position of TTMIL field.
	FDCAN_TTILS_TTMIL_Pos = 0x5
	// Bit mask of TTMIL field.
	FDCAN_TTILS_TTMIL_Msk = 0x20
	// Bit TTMIL.
	FDCAN_TTILS_TTMIL = 0x20
	// Position of SWEL field.
	FDCAN_TTILS_SWEL_Pos = 0x6
	// Bit mask of SWEL field.
	FDCAN_TTILS_SWEL_Msk = 0x40
	// Bit SWEL.
	FDCAN_TTILS_SWEL = 0x40
	// Position of GTWL field.
	FDCAN_TTILS_GTWL_Pos = 0x7
	// Bit mask of GTWL field.
	FDCAN_TTILS_GTWL_Msk = 0x80
	// Bit GTWL.
	FDCAN_TTILS_GTWL = 0x80
	// Position of GTDL field.
	FDCAN_TTILS_GTDL_Pos = 0x8
	// Bit mask of GTDL field.
	FDCAN_TTILS_GTDL_Msk = 0x100
	// Bit GTDL.
	FDCAN_TTILS_GTDL = 0x100
	// Position of GTEL field.
	FDCAN_TTILS_GTEL_Pos = 0x9
	// Bit mask of GTEL field.
	FDCAN_TTILS_GTEL_Msk = 0x200
	// Bit GTEL.
	FDCAN_TTILS_GTEL = 0x200
	// Position of TXUL field.
	FDCAN_TTILS_TXUL_Pos = 0xa
	// Bit mask of TXUL field.
	FDCAN_TTILS_TXUL_Msk = 0x400
	// Bit TXUL.
	FDCAN_TTILS_TXUL = 0x400
	// Position of TXOL field.
	FDCAN_TTILS_TXOL_Pos = 0xb
	// Bit mask of TXOL field.
	FDCAN_TTILS_TXOL_Msk = 0x800
	// Bit TXOL.
	FDCAN_TTILS_TXOL = 0x800
	// Position of SE1L field.
	FDCAN_TTILS_SE1L_Pos = 0xc
	// Bit mask of SE1L field.
	FDCAN_TTILS_SE1L_Msk = 0x1000
	// Bit SE1L.
	FDCAN_TTILS_SE1L = 0x1000
	// Position of SE2L field.
	FDCAN_TTILS_SE2L_Pos = 0xd
	// Bit mask of SE2L field.
	FDCAN_TTILS_SE2L_Msk = 0x2000
	// Bit SE2L.
	FDCAN_TTILS_SE2L = 0x2000
	// Position of ELCL field.
	FDCAN_TTILS_ELCL_Pos = 0xe
	// Bit mask of ELCL field.
	FDCAN_TTILS_ELCL_Msk = 0x4000
	// Bit ELCL.
	FDCAN_TTILS_ELCL = 0x4000
	// Position of IWTGL field.
	FDCAN_TTILS_IWTGL_Pos = 0xf
	// Bit mask of IWTGL field.
	FDCAN_TTILS_IWTGL_Msk = 0x8000
	// Bit IWTGL.
	FDCAN_TTILS_IWTGL = 0x8000
	// Position of WTL field.
	FDCAN_TTILS_WTL_Pos = 0x10
	// Bit mask of WTL field.
	FDCAN_TTILS_WTL_Msk = 0x10000
	// Bit WTL.
	FDCAN_TTILS_WTL = 0x10000
	// Position of AWL field.
	FDCAN_TTILS_AWL_Pos = 0x11
	// Bit mask of AWL field.
	FDCAN_TTILS_AWL_Msk = 0x20000
	// Bit AWL.
	FDCAN_TTILS_AWL = 0x20000
	// Position of CERL field.
	FDCAN_TTILS_CERL_Pos = 0x12
	// Bit mask of CERL field.
	FDCAN_TTILS_CERL_Msk = 0x40000
	// Bit CERL.
	FDCAN_TTILS_CERL = 0x40000

	// TTOST: FDCAN TT Operation Status Register
	// Position of EL field.
	FDCAN_TTOST_EL_Pos = 0x0
	// Bit mask of EL field.
	FDCAN_TTOST_EL_Msk = 0x3
	// Position of MS field.
	FDCAN_TTOST_MS_Pos = 0x2
	// Bit mask of MS field.
	FDCAN_TTOST_MS_Msk = 0xc
	// Position of SYS field.
	FDCAN_TTOST_SYS_Pos = 0x4
	// Bit mask of SYS field.
	FDCAN_TTOST_SYS_Msk = 0x30
	// Position of QGTP field.
	FDCAN_TTOST_QGTP_Pos = 0x6
	// Bit mask of QGTP field.
	FDCAN_TTOST_QGTP_Msk = 0x40
	// Bit QGTP.
	FDCAN_TTOST_QGTP = 0x40
	// Position of QCS field.
	FDCAN_TTOST_QCS_Pos = 0x7
	// Bit mask of QCS field.
	FDCAN_TTOST_QCS_Msk = 0x80
	// Bit QCS.
	FDCAN_TTOST_QCS = 0x80
	// Position of RTO field.
	FDCAN_TTOST_RTO_Pos = 0x8
	// Bit mask of RTO field.
	FDCAN_TTOST_RTO_Msk = 0xff00
	// Position of WGTD field.
	FDCAN_TTOST_WGTD_Pos = 0x16
	// Bit mask of WGTD field.
	FDCAN_TTOST_WGTD_Msk = 0x400000
	// Bit WGTD.
	FDCAN_TTOST_WGTD = 0x400000
	// Position of GFI field.
	FDCAN_TTOST_GFI_Pos = 0x17
	// Bit mask of GFI field.
	FDCAN_TTOST_GFI_Msk = 0x800000
	// Bit GFI.
	FDCAN_TTOST_GFI = 0x800000
	// Position of TMP field.
	FDCAN_TTOST_TMP_Pos = 0x18
	// Bit mask of TMP field.
	FDCAN_TTOST_TMP_Msk = 0x7000000
	// Position of GSI field.
	FDCAN_TTOST_GSI_Pos = 0x1b
	// Bit mask of GSI field.
	FDCAN_TTOST_GSI_Msk = 0x8000000
	// Bit GSI.
	FDCAN_TTOST_GSI = 0x8000000
	// Position of WFE field.
	FDCAN_TTOST_WFE_Pos = 0x1c
	// Bit mask of WFE field.
	FDCAN_TTOST_WFE_Msk = 0x10000000
	// Bit WFE.
	FDCAN_TTOST_WFE = 0x10000000
	// Position of AWE field.
	FDCAN_TTOST_AWE_Pos = 0x1d
	// Bit mask of AWE field.
	FDCAN_TTOST_AWE_Msk = 0x20000000
	// Bit AWE.
	FDCAN_TTOST_AWE = 0x20000000
	// Position of WECS field.
	FDCAN_TTOST_WECS_Pos = 0x1e
	// Bit mask of WECS field.
	FDCAN_TTOST_WECS_Msk = 0x40000000
	// Bit WECS.
	FDCAN_TTOST_WECS = 0x40000000
	// Position of SPL field.
	FDCAN_TTOST_SPL_Pos = 0x1f
	// Bit mask of SPL field.
	FDCAN_TTOST_SPL_Msk = 0x80000000
	// Bit SPL.
	FDCAN_TTOST_SPL = 0x80000000

	// TURNA: FDCAN TUR Numerator Actual Register
	// Position of NAV field.
	FDCAN_TURNA_NAV_Pos = 0x0
	// Bit mask of NAV field.
	FDCAN_TURNA_NAV_Msk = 0x3ffff

	// TTLGT: FDCAN TT Local and Global Time Register
	// Position of LT field.
	FDCAN_TTLGT_LT_Pos = 0x0
	// Bit mask of LT field.
	FDCAN_TTLGT_LT_Msk = 0xffff
	// Position of GT field.
	FDCAN_TTLGT_GT_Pos = 0x10
	// Bit mask of GT field.
	FDCAN_TTLGT_GT_Msk = 0xffff0000

	// TTCTC: FDCAN TT Cycle Time and Count Register
	// Position of CT field.
	FDCAN_TTCTC_CT_Pos = 0x0
	// Bit mask of CT field.
	FDCAN_TTCTC_CT_Msk = 0xffff
	// Position of CC field.
	FDCAN_TTCTC_CC_Pos = 0x10
	// Bit mask of CC field.
	FDCAN_TTCTC_CC_Msk = 0x3f0000

	// TTCPT: FDCAN TT Capture Time Register
	// Position of CCV field.
	FDCAN_TTCPT_CCV_Pos = 0x0
	// Bit mask of CCV field.
	FDCAN_TTCPT_CCV_Msk = 0x3f
	// Position of SWV field.
	FDCAN_TTCPT_SWV_Pos = 0x10
	// Bit mask of SWV field.
	FDCAN_TTCPT_SWV_Msk = 0xffff0000

	// TTCSM: FDCAN TT Cycle Sync Mark Register
	// Position of CSM field.
	FDCAN_TTCSM_CSM_Pos = 0x0
	// Bit mask of CSM field.
	FDCAN_TTCSM_CSM_Msk = 0xffff

	// TTTS: FDCAN TT Trigger Select Register
	// Position of SWTDEL field.
	FDCAN_TTTS_SWTDEL_Pos = 0x0
	// Bit mask of SWTDEL field.
	FDCAN_TTTS_SWTDEL_Msk = 0x3
	// Position of EVTSEL field.
	FDCAN_TTTS_EVTSEL_Pos = 0x4
	// Bit mask of EVTSEL field.
	FDCAN_TTTS_EVTSEL_Msk = 0x30
)

// Bitfields for MDIOS: Management data input/output slave
const (
	// CR: MDIOS configuration register
	// Position of EN field.
	MDIOS_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	MDIOS_CR_EN_Msk = 0x1
	// Bit EN.
	MDIOS_CR_EN = 0x1
	// Position of WRIE field.
	MDIOS_CR_WRIE_Pos = 0x1
	// Bit mask of WRIE field.
	MDIOS_CR_WRIE_Msk = 0x2
	// Bit WRIE.
	MDIOS_CR_WRIE = 0x2
	// Position of RDIE field.
	MDIOS_CR_RDIE_Pos = 0x2
	// Bit mask of RDIE field.
	MDIOS_CR_RDIE_Msk = 0x4
	// Bit RDIE.
	MDIOS_CR_RDIE = 0x4
	// Position of EIE field.
	MDIOS_CR_EIE_Pos = 0x3
	// Bit mask of EIE field.
	MDIOS_CR_EIE_Msk = 0x8
	// Bit EIE.
	MDIOS_CR_EIE = 0x8
	// Position of DPC field.
	MDIOS_CR_DPC_Pos = 0x7
	// Bit mask of DPC field.
	MDIOS_CR_DPC_Msk = 0x80
	// Bit DPC.
	MDIOS_CR_DPC = 0x80
	// Position of PORT_ADDRESS field.
	MDIOS_CR_PORT_ADDRESS_Pos = 0x8
	// Bit mask of PORT_ADDRESS field.
	MDIOS_CR_PORT_ADDRESS_Msk = 0x1f00

	// WRFR: MDIOS write flag register
	// Position of WRF field.
	MDIOS_WRFR_WRF_Pos = 0x0
	// Bit mask of WRF field.
	MDIOS_WRFR_WRF_Msk = 0xffffffff

	// CWRFR: MDIOS clear write flag register
	// Position of CWRF field.
	MDIOS_CWRFR_CWRF_Pos = 0x0
	// Bit mask of CWRF field.
	MDIOS_CWRFR_CWRF_Msk = 0xffffffff

	// RDFR: MDIOS read flag register
	// Position of RDF field.
	MDIOS_RDFR_RDF_Pos = 0x0
	// Bit mask of RDF field.
	MDIOS_RDFR_RDF_Msk = 0xffffffff

	// CRDFR: MDIOS clear read flag register
	// Position of CRDF field.
	MDIOS_CRDFR_CRDF_Pos = 0x0
	// Bit mask of CRDF field.
	MDIOS_CRDFR_CRDF_Msk = 0xffffffff

	// SR: MDIOS status register
	// Position of PERF field.
	MDIOS_SR_PERF_Pos = 0x0
	// Bit mask of PERF field.
	MDIOS_SR_PERF_Msk = 0x1
	// Bit PERF.
	MDIOS_SR_PERF = 0x1
	// Position of SERF field.
	MDIOS_SR_SERF_Pos = 0x1
	// Bit mask of SERF field.
	MDIOS_SR_SERF_Msk = 0x2
	// Bit SERF.
	MDIOS_SR_SERF = 0x2
	// Position of TERF field.
	MDIOS_SR_TERF_Pos = 0x2
	// Bit mask of TERF field.
	MDIOS_SR_TERF_Msk = 0x4
	// Bit TERF.
	MDIOS_SR_TERF = 0x4

	// CLRFR: MDIOS clear flag register
	// Position of CPERF field.
	MDIOS_CLRFR_CPERF_Pos = 0x0
	// Bit mask of CPERF field.
	MDIOS_CLRFR_CPERF_Msk = 0x1
	// Bit CPERF.
	MDIOS_CLRFR_CPERF = 0x1
	// Position of CSERF field.
	MDIOS_CLRFR_CSERF_Pos = 0x1
	// Bit mask of CSERF field.
	MDIOS_CLRFR_CSERF_Msk = 0x2
	// Bit CSERF.
	MDIOS_CLRFR_CSERF = 0x2
	// Position of CTERF field.
	MDIOS_CLRFR_CTERF_Pos = 0x2
	// Bit mask of CTERF field.
	MDIOS_CLRFR_CTERF_Msk = 0x4
	// Bit CTERF.
	MDIOS_CLRFR_CTERF = 0x4

	// DINR0: MDIOS input data register 0
	// Position of DIN0 field.
	MDIOS_DINR0_DIN0_Pos = 0x0
	// Bit mask of DIN0 field.
	MDIOS_DINR0_DIN0_Msk = 0xffff

	// DINR1: MDIOS input data register 1
	// Position of DIN1 field.
	MDIOS_DINR1_DIN1_Pos = 0x0
	// Bit mask of DIN1 field.
	MDIOS_DINR1_DIN1_Msk = 0xffff

	// DINR2: MDIOS input data register 2
	// Position of DIN2 field.
	MDIOS_DINR2_DIN2_Pos = 0x0
	// Bit mask of DIN2 field.
	MDIOS_DINR2_DIN2_Msk = 0xffff

	// DINR3: MDIOS input data register 3
	// Position of DIN3 field.
	MDIOS_DINR3_DIN3_Pos = 0x0
	// Bit mask of DIN3 field.
	MDIOS_DINR3_DIN3_Msk = 0xffff

	// DINR4: MDIOS input data register 4
	// Position of DIN4 field.
	MDIOS_DINR4_DIN4_Pos = 0x0
	// Bit mask of DIN4 field.
	MDIOS_DINR4_DIN4_Msk = 0xffff

	// DINR5: MDIOS input data register 5
	// Position of DIN5 field.
	MDIOS_DINR5_DIN5_Pos = 0x0
	// Bit mask of DIN5 field.
	MDIOS_DINR5_DIN5_Msk = 0xffff

	// DINR6: MDIOS input data register 6
	// Position of DIN6 field.
	MDIOS_DINR6_DIN6_Pos = 0x0
	// Bit mask of DIN6 field.
	MDIOS_DINR6_DIN6_Msk = 0xffff

	// DINR7: MDIOS input data register 7
	// Position of DIN7 field.
	MDIOS_DINR7_DIN7_Pos = 0x0
	// Bit mask of DIN7 field.
	MDIOS_DINR7_DIN7_Msk = 0xffff

	// DINR8: MDIOS input data register 8
	// Position of DIN8 field.
	MDIOS_DINR8_DIN8_Pos = 0x0
	// Bit mask of DIN8 field.
	MDIOS_DINR8_DIN8_Msk = 0xffff

	// DINR9: MDIOS input data register 9
	// Position of DIN9 field.
	MDIOS_DINR9_DIN9_Pos = 0x0
	// Bit mask of DIN9 field.
	MDIOS_DINR9_DIN9_Msk = 0xffff

	// DINR10: MDIOS input data register 10
	// Position of DIN10 field.
	MDIOS_DINR10_DIN10_Pos = 0x0
	// Bit mask of DIN10 field.
	MDIOS_DINR10_DIN10_Msk = 0xffff

	// DINR11: MDIOS input data register 11
	// Position of DIN11 field.
	MDIOS_DINR11_DIN11_Pos = 0x0
	// Bit mask of DIN11 field.
	MDIOS_DINR11_DIN11_Msk = 0xffff

	// DINR12: MDIOS input data register 12
	// Position of DIN12 field.
	MDIOS_DINR12_DIN12_Pos = 0x0
	// Bit mask of DIN12 field.
	MDIOS_DINR12_DIN12_Msk = 0xffff

	// DINR13: MDIOS input data register 13
	// Position of DIN13 field.
	MDIOS_DINR13_DIN13_Pos = 0x0
	// Bit mask of DIN13 field.
	MDIOS_DINR13_DIN13_Msk = 0xffff

	// DINR14: MDIOS input data register 14
	// Position of DIN14 field.
	MDIOS_DINR14_DIN14_Pos = 0x0
	// Bit mask of DIN14 field.
	MDIOS_DINR14_DIN14_Msk = 0xffff

	// DINR15: MDIOS input data register 15
	// Position of DIN15 field.
	MDIOS_DINR15_DIN15_Pos = 0x0
	// Bit mask of DIN15 field.
	MDIOS_DINR15_DIN15_Msk = 0xffff

	// DINR16: MDIOS input data register 16
	// Position of DIN16 field.
	MDIOS_DINR16_DIN16_Pos = 0x0
	// Bit mask of DIN16 field.
	MDIOS_DINR16_DIN16_Msk = 0xffff

	// DINR17: MDIOS input data register 17
	// Position of DIN17 field.
	MDIOS_DINR17_DIN17_Pos = 0x0
	// Bit mask of DIN17 field.
	MDIOS_DINR17_DIN17_Msk = 0xffff

	// DINR18: MDIOS input data register 18
	// Position of DIN18 field.
	MDIOS_DINR18_DIN18_Pos = 0x0
	// Bit mask of DIN18 field.
	MDIOS_DINR18_DIN18_Msk = 0xffff

	// DINR19: MDIOS input data register 19
	// Position of DIN19 field.
	MDIOS_DINR19_DIN19_Pos = 0x0
	// Bit mask of DIN19 field.
	MDIOS_DINR19_DIN19_Msk = 0xffff

	// DINR20: MDIOS input data register 20
	// Position of DIN20 field.
	MDIOS_DINR20_DIN20_Pos = 0x0
	// Bit mask of DIN20 field.
	MDIOS_DINR20_DIN20_Msk = 0xffff

	// DINR21: MDIOS input data register 21
	// Position of DIN21 field.
	MDIOS_DINR21_DIN21_Pos = 0x0
	// Bit mask of DIN21 field.
	MDIOS_DINR21_DIN21_Msk = 0xffff

	// DINR22: MDIOS input data register 22
	// Position of DIN22 field.
	MDIOS_DINR22_DIN22_Pos = 0x0
	// Bit mask of DIN22 field.
	MDIOS_DINR22_DIN22_Msk = 0xffff

	// DINR23: MDIOS input data register 23
	// Position of DIN23 field.
	MDIOS_DINR23_DIN23_Pos = 0x0
	// Bit mask of DIN23 field.
	MDIOS_DINR23_DIN23_Msk = 0xffff

	// DINR24: MDIOS input data register 24
	// Position of DIN24 field.
	MDIOS_DINR24_DIN24_Pos = 0x0
	// Bit mask of DIN24 field.
	MDIOS_DINR24_DIN24_Msk = 0xffff

	// DINR25: MDIOS input data register 25
	// Position of DIN25 field.
	MDIOS_DINR25_DIN25_Pos = 0x0
	// Bit mask of DIN25 field.
	MDIOS_DINR25_DIN25_Msk = 0xffff

	// DINR26: MDIOS input data register 26
	// Position of DIN26 field.
	MDIOS_DINR26_DIN26_Pos = 0x0
	// Bit mask of DIN26 field.
	MDIOS_DINR26_DIN26_Msk = 0xffff

	// DINR27: MDIOS input data register 27
	// Position of DIN27 field.
	MDIOS_DINR27_DIN27_Pos = 0x0
	// Bit mask of DIN27 field.
	MDIOS_DINR27_DIN27_Msk = 0xffff

	// DINR28: MDIOS input data register 28
	// Position of DIN28 field.
	MDIOS_DINR28_DIN28_Pos = 0x0
	// Bit mask of DIN28 field.
	MDIOS_DINR28_DIN28_Msk = 0xffff

	// DINR29: MDIOS input data register 29
	// Position of DIN29 field.
	MDIOS_DINR29_DIN29_Pos = 0x0
	// Bit mask of DIN29 field.
	MDIOS_DINR29_DIN29_Msk = 0xffff

	// DINR30: MDIOS input data register 30
	// Position of DIN30 field.
	MDIOS_DINR30_DIN30_Pos = 0x0
	// Bit mask of DIN30 field.
	MDIOS_DINR30_DIN30_Msk = 0xffff

	// DINR31: MDIOS input data register 31
	// Position of DIN31 field.
	MDIOS_DINR31_DIN31_Pos = 0x0
	// Bit mask of DIN31 field.
	MDIOS_DINR31_DIN31_Msk = 0xffff

	// DOUTR0: MDIOS output data register 0
	// Position of DOUT0 field.
	MDIOS_DOUTR0_DOUT0_Pos = 0x0
	// Bit mask of DOUT0 field.
	MDIOS_DOUTR0_DOUT0_Msk = 0xffff

	// DOUTR1: MDIOS output data register 1
	// Position of DOUT1 field.
	MDIOS_DOUTR1_DOUT1_Pos = 0x0
	// Bit mask of DOUT1 field.
	MDIOS_DOUTR1_DOUT1_Msk = 0xffff

	// DOUTR2: MDIOS output data register 2
	// Position of DOUT2 field.
	MDIOS_DOUTR2_DOUT2_Pos = 0x0
	// Bit mask of DOUT2 field.
	MDIOS_DOUTR2_DOUT2_Msk = 0xffff

	// DOUTR3: MDIOS output data register 3
	// Position of DOUT3 field.
	MDIOS_DOUTR3_DOUT3_Pos = 0x0
	// Bit mask of DOUT3 field.
	MDIOS_DOUTR3_DOUT3_Msk = 0xffff

	// DOUTR4: MDIOS output data register 4
	// Position of DOUT4 field.
	MDIOS_DOUTR4_DOUT4_Pos = 0x0
	// Bit mask of DOUT4 field.
	MDIOS_DOUTR4_DOUT4_Msk = 0xffff

	// DOUTR5: MDIOS output data register 5
	// Position of DOUT5 field.
	MDIOS_DOUTR5_DOUT5_Pos = 0x0
	// Bit mask of DOUT5 field.
	MDIOS_DOUTR5_DOUT5_Msk = 0xffff

	// DOUTR6: MDIOS output data register 6
	// Position of DOUT6 field.
	MDIOS_DOUTR6_DOUT6_Pos = 0x0
	// Bit mask of DOUT6 field.
	MDIOS_DOUTR6_DOUT6_Msk = 0xffff

	// DOUTR7: MDIOS output data register 7
	// Position of DOUT7 field.
	MDIOS_DOUTR7_DOUT7_Pos = 0x0
	// Bit mask of DOUT7 field.
	MDIOS_DOUTR7_DOUT7_Msk = 0xffff

	// DOUTR8: MDIOS output data register 8
	// Position of DOUT8 field.
	MDIOS_DOUTR8_DOUT8_Pos = 0x0
	// Bit mask of DOUT8 field.
	MDIOS_DOUTR8_DOUT8_Msk = 0xffff

	// DOUTR9: MDIOS output data register 9
	// Position of DOUT9 field.
	MDIOS_DOUTR9_DOUT9_Pos = 0x0
	// Bit mask of DOUT9 field.
	MDIOS_DOUTR9_DOUT9_Msk = 0xffff

	// DOUTR10: MDIOS output data register 10
	// Position of DOUT10 field.
	MDIOS_DOUTR10_DOUT10_Pos = 0x0
	// Bit mask of DOUT10 field.
	MDIOS_DOUTR10_DOUT10_Msk = 0xffff

	// DOUTR11: MDIOS output data register 11
	// Position of DOUT11 field.
	MDIOS_DOUTR11_DOUT11_Pos = 0x0
	// Bit mask of DOUT11 field.
	MDIOS_DOUTR11_DOUT11_Msk = 0xffff

	// DOUTR12: MDIOS output data register 12
	// Position of DOUT12 field.
	MDIOS_DOUTR12_DOUT12_Pos = 0x0
	// Bit mask of DOUT12 field.
	MDIOS_DOUTR12_DOUT12_Msk = 0xffff

	// DOUTR13: MDIOS output data register 13
	// Position of DOUT13 field.
	MDIOS_DOUTR13_DOUT13_Pos = 0x0
	// Bit mask of DOUT13 field.
	MDIOS_DOUTR13_DOUT13_Msk = 0xffff

	// DOUTR14: MDIOS output data register 14
	// Position of DOUT14 field.
	MDIOS_DOUTR14_DOUT14_Pos = 0x0
	// Bit mask of DOUT14 field.
	MDIOS_DOUTR14_DOUT14_Msk = 0xffff

	// DOUTR15: MDIOS output data register 15
	// Position of DOUT15 field.
	MDIOS_DOUTR15_DOUT15_Pos = 0x0
	// Bit mask of DOUT15 field.
	MDIOS_DOUTR15_DOUT15_Msk = 0xffff

	// DOUTR16: MDIOS output data register 16
	// Position of DOUT16 field.
	MDIOS_DOUTR16_DOUT16_Pos = 0x0
	// Bit mask of DOUT16 field.
	MDIOS_DOUTR16_DOUT16_Msk = 0xffff

	// DOUTR17: MDIOS output data register 17
	// Position of DOUT17 field.
	MDIOS_DOUTR17_DOUT17_Pos = 0x0
	// Bit mask of DOUT17 field.
	MDIOS_DOUTR17_DOUT17_Msk = 0xffff

	// DOUTR18: MDIOS output data register 18
	// Position of DOUT18 field.
	MDIOS_DOUTR18_DOUT18_Pos = 0x0
	// Bit mask of DOUT18 field.
	MDIOS_DOUTR18_DOUT18_Msk = 0xffff

	// DOUTR19: MDIOS output data register 19
	// Position of DOUT19 field.
	MDIOS_DOUTR19_DOUT19_Pos = 0x0
	// Bit mask of DOUT19 field.
	MDIOS_DOUTR19_DOUT19_Msk = 0xffff

	// DOUTR20: MDIOS output data register 20
	// Position of DOUT20 field.
	MDIOS_DOUTR20_DOUT20_Pos = 0x0
	// Bit mask of DOUT20 field.
	MDIOS_DOUTR20_DOUT20_Msk = 0xffff

	// DOUTR21: MDIOS output data register 21
	// Position of DOUT21 field.
	MDIOS_DOUTR21_DOUT21_Pos = 0x0
	// Bit mask of DOUT21 field.
	MDIOS_DOUTR21_DOUT21_Msk = 0xffff

	// DOUTR22: MDIOS output data register 22
	// Position of DOUT22 field.
	MDIOS_DOUTR22_DOUT22_Pos = 0x0
	// Bit mask of DOUT22 field.
	MDIOS_DOUTR22_DOUT22_Msk = 0xffff

	// DOUTR23: MDIOS output data register 23
	// Position of DOUT23 field.
	MDIOS_DOUTR23_DOUT23_Pos = 0x0
	// Bit mask of DOUT23 field.
	MDIOS_DOUTR23_DOUT23_Msk = 0xffff

	// DOUTR24: MDIOS output data register 24
	// Position of DOUT24 field.
	MDIOS_DOUTR24_DOUT24_Pos = 0x0
	// Bit mask of DOUT24 field.
	MDIOS_DOUTR24_DOUT24_Msk = 0xffff

	// DOUTR25: MDIOS output data register 25
	// Position of DOUT25 field.
	MDIOS_DOUTR25_DOUT25_Pos = 0x0
	// Bit mask of DOUT25 field.
	MDIOS_DOUTR25_DOUT25_Msk = 0xffff

	// DOUTR26: MDIOS output data register 26
	// Position of DOUT26 field.
	MDIOS_DOUTR26_DOUT26_Pos = 0x0
	// Bit mask of DOUT26 field.
	MDIOS_DOUTR26_DOUT26_Msk = 0xffff

	// DOUTR27: MDIOS output data register 27
	// Position of DOUT27 field.
	MDIOS_DOUTR27_DOUT27_Pos = 0x0
	// Bit mask of DOUT27 field.
	MDIOS_DOUTR27_DOUT27_Msk = 0xffff

	// DOUTR28: MDIOS output data register 28
	// Position of DOUT28 field.
	MDIOS_DOUTR28_DOUT28_Pos = 0x0
	// Bit mask of DOUT28 field.
	MDIOS_DOUTR28_DOUT28_Msk = 0xffff

	// DOUTR29: MDIOS output data register 29
	// Position of DOUT29 field.
	MDIOS_DOUTR29_DOUT29_Pos = 0x0
	// Bit mask of DOUT29 field.
	MDIOS_DOUTR29_DOUT29_Msk = 0xffff

	// DOUTR30: MDIOS output data register 30
	// Position of DOUT30 field.
	MDIOS_DOUTR30_DOUT30_Pos = 0x0
	// Bit mask of DOUT30 field.
	MDIOS_DOUTR30_DOUT30_Msk = 0xffff

	// DOUTR31: MDIOS output data register 31
	// Position of DOUT31 field.
	MDIOS_DOUTR31_DOUT31_Pos = 0x0
	// Bit mask of DOUT31 field.
	MDIOS_DOUTR31_DOUT31_Msk = 0xffff
)

// Bitfields for OPAMP: Operational amplifiers
const (
	// OPAMP1_CSR: OPAMP1 control/status register
	// Position of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Pos = 0x0
	// Bit mask of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Msk = 0x1
	// Bit OPAEN.
	OPAMP_OPAMP1_CSR_OPAEN = 0x1
	// Position of FORCE_VP field.
	OPAMP_OPAMP1_CSR_FORCE_VP_Pos = 0x1
	// Bit mask of FORCE_VP field.
	OPAMP_OPAMP1_CSR_FORCE_VP_Msk = 0x2
	// Bit FORCE_VP.
	OPAMP_OPAMP1_CSR_FORCE_VP = 0x2
	// Position of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Pos = 0x2
	// Bit mask of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Msk = 0xc
	// Position of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Pos = 0x5
	// Bit mask of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Msk = 0x60
	// Position of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM_Pos = 0x8
	// Bit mask of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM_Msk = 0x100
	// Bit OPAHSM.
	OPAMP_OPAMP1_CSR_OPAHSM = 0x100
	// Position of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Pos = 0xb
	// Bit mask of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Msk = 0x800
	// Bit CALON.
	OPAMP_OPAMP1_CSR_CALON = 0x800
	// Position of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Pos = 0xc
	// Bit mask of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Msk = 0x3000
	// Position of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Pos = 0xe
	// Bit mask of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Msk = 0x3c000
	// Position of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Pos = 0x12
	// Bit mask of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Msk = 0x40000
	// Bit USERTRIM.
	OPAMP_OPAMP1_CSR_USERTRIM = 0x40000
	// Position of TSTREF field.
	OPAMP_OPAMP1_CSR_TSTREF_Pos = 0x1d
	// Bit mask of TSTREF field.
	OPAMP_OPAMP1_CSR_TSTREF_Msk = 0x20000000
	// Bit TSTREF.
	OPAMP_OPAMP1_CSR_TSTREF = 0x20000000
	// Position of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Pos = 0x1e
	// Bit mask of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Msk = 0x40000000
	// Bit CALOUT.
	OPAMP_OPAMP1_CSR_CALOUT = 0x40000000

	// OPAMP1_OTR: OPAMP1 offset trimming register in normal mode
	// Position of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Pos = 0x0
	// Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Msk = 0x1f
	// Position of TRIMOFFSETP field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Pos = 0x8
	// Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Msk = 0x1f00

	// OPAMP1_HSOTR: OPAMP1 offset trimming register in low-power mode
	// Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETN_Pos = 0x0
	// Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETN_Msk = 0x1f
	// Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETP_Pos = 0x8
	// Bit mask of TRIMLPOFFSETP field.
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETP_Msk = 0x1f00

	// OPAMP2_CSR: OPAMP2 control/status register
	// Position of OPAEN field.
	OPAMP_OPAMP2_CSR_OPAEN_Pos = 0x0
	// Bit mask of OPAEN field.
	OPAMP_OPAMP2_CSR_OPAEN_Msk = 0x1
	// Bit OPAEN.
	OPAMP_OPAMP2_CSR_OPAEN = 0x1
	// Position of FORCE_VP field.
	OPAMP_OPAMP2_CSR_FORCE_VP_Pos = 0x1
	// Bit mask of FORCE_VP field.
	OPAMP_OPAMP2_CSR_FORCE_VP_Msk = 0x2
	// Bit FORCE_VP.
	OPAMP_OPAMP2_CSR_FORCE_VP = 0x2
	// Position of VM_SEL field.
	OPAMP_OPAMP2_CSR_VM_SEL_Pos = 0x5
	// Bit mask of VM_SEL field.
	OPAMP_OPAMP2_CSR_VM_SEL_Msk = 0x60
	// Position of OPAHSM field.
	OPAMP_OPAMP2_CSR_OPAHSM_Pos = 0x8
	// Bit mask of OPAHSM field.
	OPAMP_OPAMP2_CSR_OPAHSM_Msk = 0x100
	// Bit OPAHSM.
	OPAMP_OPAMP2_CSR_OPAHSM = 0x100
	// Position of CALON field.
	OPAMP_OPAMP2_CSR_CALON_Pos = 0xb
	// Bit mask of CALON field.
	OPAMP_OPAMP2_CSR_CALON_Msk = 0x800
	// Bit CALON.
	OPAMP_OPAMP2_CSR_CALON = 0x800
	// Position of CALSEL field.
	OPAMP_OPAMP2_CSR_CALSEL_Pos = 0xc
	// Bit mask of CALSEL field.
	OPAMP_OPAMP2_CSR_CALSEL_Msk = 0x3000
	// Position of PGA_GAIN field.
	OPAMP_OPAMP2_CSR_PGA_GAIN_Pos = 0xe
	// Bit mask of PGA_GAIN field.
	OPAMP_OPAMP2_CSR_PGA_GAIN_Msk = 0x3c000
	// Position of USERTRIM field.
	OPAMP_OPAMP2_CSR_USERTRIM_Pos = 0x12
	// Bit mask of USERTRIM field.
	OPAMP_OPAMP2_CSR_USERTRIM_Msk = 0x40000
	// Bit USERTRIM.
	OPAMP_OPAMP2_CSR_USERTRIM = 0x40000
	// Position of TSTREF field.
	OPAMP_OPAMP2_CSR_TSTREF_Pos = 0x1d
	// Bit mask of TSTREF field.
	OPAMP_OPAMP2_CSR_TSTREF_Msk = 0x20000000
	// Bit TSTREF.
	OPAMP_OPAMP2_CSR_TSTREF = 0x20000000
	// Position of CALOUT field.
	OPAMP_OPAMP2_CSR_CALOUT_Pos = 0x1e
	// Bit mask of CALOUT field.
	OPAMP_OPAMP2_CSR_CALOUT_Msk = 0x40000000
	// Bit CALOUT.
	OPAMP_OPAMP2_CSR_CALOUT = 0x40000000

	// OPAMP2_OTR: OPAMP2 offset trimming register in normal mode
	// Position of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Pos = 0x0
	// Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Msk = 0x1f
	// Position of TRIMOFFSETP field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Pos = 0x8
	// Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Msk = 0x1f00

	// OPAMP2_HSOTR: OPAMP2 offset trimming register in low-power mode
	// Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETN_Pos = 0x0
	// Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETN_Msk = 0x1f
	// Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETP_Pos = 0x8
	// Bit mask of TRIMLPOFFSETP field.
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETP_Msk = 0x1f00
)

// Bitfields for SWPMI: Single Wire Protocol Master Interface
const (
	// CR: SWPMI Configuration/Control register
	// Position of RXDMA field.
	SWPMI_CR_RXDMA_Pos = 0x0
	// Bit mask of RXDMA field.
	SWPMI_CR_RXDMA_Msk = 0x1
	// Bit RXDMA.
	SWPMI_CR_RXDMA = 0x1
	// Position of TXDMA field.
	SWPMI_CR_TXDMA_Pos = 0x1
	// Bit mask of TXDMA field.
	SWPMI_CR_TXDMA_Msk = 0x2
	// Bit TXDMA.
	SWPMI_CR_TXDMA = 0x2
	// Position of RXMODE field.
	SWPMI_CR_RXMODE_Pos = 0x2
	// Bit mask of RXMODE field.
	SWPMI_CR_RXMODE_Msk = 0x4
	// Bit RXMODE.
	SWPMI_CR_RXMODE = 0x4
	// Position of TXMODE field.
	SWPMI_CR_TXMODE_Pos = 0x3
	// Bit mask of TXMODE field.
	SWPMI_CR_TXMODE_Msk = 0x8
	// Bit TXMODE.
	SWPMI_CR_TXMODE = 0x8
	// Position of LPBK field.
	SWPMI_CR_LPBK_Pos = 0x4
	// Bit mask of LPBK field.
	SWPMI_CR_LPBK_Msk = 0x10
	// Bit LPBK.
	SWPMI_CR_LPBK = 0x10
	// Position of SWPACT field.
	SWPMI_CR_SWPACT_Pos = 0x5
	// Bit mask of SWPACT field.
	SWPMI_CR_SWPACT_Msk = 0x20
	// Bit SWPACT.
	SWPMI_CR_SWPACT = 0x20
	// Position of DEACT field.
	SWPMI_CR_DEACT_Pos = 0xa
	// Bit mask of DEACT field.
	SWPMI_CR_DEACT_Msk = 0x400
	// Bit DEACT.
	SWPMI_CR_DEACT = 0x400
	// Position of SWPTEN field.
	SWPMI_CR_SWPTEN_Pos = 0xb
	// Bit mask of SWPTEN field.
	SWPMI_CR_SWPTEN_Msk = 0x800
	// Bit SWPTEN.
	SWPMI_CR_SWPTEN = 0x800

	// BRR: SWPMI Bitrate register
	// Position of BR field.
	SWPMI_BRR_BR_Pos = 0x0
	// Bit mask of BR field.
	SWPMI_BRR_BR_Msk = 0xff

	// ISR: SWPMI Interrupt and Status register
	// Position of RXBFF field.
	SWPMI_ISR_RXBFF_Pos = 0x0
	// Bit mask of RXBFF field.
	SWPMI_ISR_RXBFF_Msk = 0x1
	// Bit RXBFF.
	SWPMI_ISR_RXBFF = 0x1
	// Position of TXBEF field.
	SWPMI_ISR_TXBEF_Pos = 0x1
	// Bit mask of TXBEF field.
	SWPMI_ISR_TXBEF_Msk = 0x2
	// Bit TXBEF.
	SWPMI_ISR_TXBEF = 0x2
	// Position of RXBERF field.
	SWPMI_ISR_RXBERF_Pos = 0x2
	// Bit mask of RXBERF field.
	SWPMI_ISR_RXBERF_Msk = 0x4
	// Bit RXBERF.
	SWPMI_ISR_RXBERF = 0x4
	// Position of RXOVRF field.
	SWPMI_ISR_RXOVRF_Pos = 0x3
	// Bit mask of RXOVRF field.
	SWPMI_ISR_RXOVRF_Msk = 0x8
	// Bit RXOVRF.
	SWPMI_ISR_RXOVRF = 0x8
	// Position of TXUNRF field.
	SWPMI_ISR_TXUNRF_Pos = 0x4
	// Bit mask of TXUNRF field.
	SWPMI_ISR_TXUNRF_Msk = 0x10
	// Bit TXUNRF.
	SWPMI_ISR_TXUNRF = 0x10
	// Position of RXNE field.
	SWPMI_ISR_RXNE_Pos = 0x5
	// Bit mask of RXNE field.
	SWPMI_ISR_RXNE_Msk = 0x20
	// Bit RXNE.
	SWPMI_ISR_RXNE = 0x20
	// Position of TXE field.
	SWPMI_ISR_TXE_Pos = 0x6
	// Bit mask of TXE field.
	SWPMI_ISR_TXE_Msk = 0x40
	// Bit TXE.
	SWPMI_ISR_TXE = 0x40
	// Position of TCF field.
	SWPMI_ISR_TCF_Pos = 0x7
	// Bit mask of TCF field.
	SWPMI_ISR_TCF_Msk = 0x80
	// Bit TCF.
	SWPMI_ISR_TCF = 0x80
	// Position of SRF field.
	SWPMI_ISR_SRF_Pos = 0x8
	// Bit mask of SRF field.
	SWPMI_ISR_SRF_Msk = 0x100
	// Bit SRF.
	SWPMI_ISR_SRF = 0x100
	// Position of SUSP field.
	SWPMI_ISR_SUSP_Pos = 0x9
	// Bit mask of SUSP field.
	SWPMI_ISR_SUSP_Msk = 0x200
	// Bit SUSP.
	SWPMI_ISR_SUSP = 0x200
	// Position of DEACTF field.
	SWPMI_ISR_DEACTF_Pos = 0xa
	// Bit mask of DEACTF field.
	SWPMI_ISR_DEACTF_Msk = 0x400
	// Bit DEACTF.
	SWPMI_ISR_DEACTF = 0x400
	// Position of RDYF field.
	SWPMI_ISR_RDYF_Pos = 0xb
	// Bit mask of RDYF field.
	SWPMI_ISR_RDYF_Msk = 0x800
	// Bit RDYF.
	SWPMI_ISR_RDYF = 0x800

	// ICR: SWPMI Interrupt Flag Clear register
	// Position of CRXBFF field.
	SWPMI_ICR_CRXBFF_Pos = 0x0
	// Bit mask of CRXBFF field.
	SWPMI_ICR_CRXBFF_Msk = 0x1
	// Bit CRXBFF.
	SWPMI_ICR_CRXBFF = 0x1
	// Position of CTXBEF field.
	SWPMI_ICR_CTXBEF_Pos = 0x1
	// Bit mask of CTXBEF field.
	SWPMI_ICR_CTXBEF_Msk = 0x2
	// Bit CTXBEF.
	SWPMI_ICR_CTXBEF = 0x2
	// Position of CRXBERF field.
	SWPMI_ICR_CRXBERF_Pos = 0x2
	// Bit mask of CRXBERF field.
	SWPMI_ICR_CRXBERF_Msk = 0x4
	// Bit CRXBERF.
	SWPMI_ICR_CRXBERF = 0x4
	// Position of CRXOVRF field.
	SWPMI_ICR_CRXOVRF_Pos = 0x3
	// Bit mask of CRXOVRF field.
	SWPMI_ICR_CRXOVRF_Msk = 0x8
	// Bit CRXOVRF.
	SWPMI_ICR_CRXOVRF = 0x8
	// Position of CTXUNRF field.
	SWPMI_ICR_CTXUNRF_Pos = 0x4
	// Bit mask of CTXUNRF field.
	SWPMI_ICR_CTXUNRF_Msk = 0x10
	// Bit CTXUNRF.
	SWPMI_ICR_CTXUNRF = 0x10
	// Position of CTCF field.
	SWPMI_ICR_CTCF_Pos = 0x7
	// Bit mask of CTCF field.
	SWPMI_ICR_CTCF_Msk = 0x80
	// Bit CTCF.
	SWPMI_ICR_CTCF = 0x80
	// Position of CSRF field.
	SWPMI_ICR_CSRF_Pos = 0x8
	// Bit mask of CSRF field.
	SWPMI_ICR_CSRF_Msk = 0x100
	// Bit CSRF.
	SWPMI_ICR_CSRF = 0x100
	// Position of CRDYF field.
	SWPMI_ICR_CRDYF_Pos = 0xb
	// Bit mask of CRDYF field.
	SWPMI_ICR_CRDYF_Msk = 0x800
	// Bit CRDYF.
	SWPMI_ICR_CRDYF = 0x800

	// IER: SWPMI Interrupt Enable register
	// Position of RXBFIE field.
	SWPMI_IER_RXBFIE_Pos = 0x0
	// Bit mask of RXBFIE field.
	SWPMI_IER_RXBFIE_Msk = 0x1
	// Bit RXBFIE.
	SWPMI_IER_RXBFIE = 0x1
	// Position of TXBEIE field.
	SWPMI_IER_TXBEIE_Pos = 0x1
	// Bit mask of TXBEIE field.
	SWPMI_IER_TXBEIE_Msk = 0x2
	// Bit TXBEIE.
	SWPMI_IER_TXBEIE = 0x2
	// Position of RXBERIE field.
	SWPMI_IER_RXBERIE_Pos = 0x2
	// Bit mask of RXBERIE field.
	SWPMI_IER_RXBERIE_Msk = 0x4
	// Bit RXBERIE.
	SWPMI_IER_RXBERIE = 0x4
	// Position of RXOVRIE field.
	SWPMI_IER_RXOVRIE_Pos = 0x3
	// Bit mask of RXOVRIE field.
	SWPMI_IER_RXOVRIE_Msk = 0x8
	// Bit RXOVRIE.
	SWPMI_IER_RXOVRIE = 0x8
	// Position of TXUNRIE field.
	SWPMI_IER_TXUNRIE_Pos = 0x4
	// Bit mask of TXUNRIE field.
	SWPMI_IER_TXUNRIE_Msk = 0x10
	// Bit TXUNRIE.
	SWPMI_IER_TXUNRIE = 0x10
	// Position of RIE field.
	SWPMI_IER_RIE_Pos = 0x5
	// Bit mask of RIE field.
	SWPMI_IER_RIE_Msk = 0x20
	// Bit RIE.
	SWPMI_IER_RIE = 0x20
	// Position of TIE field.
	SWPMI_IER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	SWPMI_IER_TIE_Msk = 0x40
	// Bit TIE.
	SWPMI_IER_TIE = 0x40
	// Position of TCIE field.
	SWPMI_IER_TCIE_Pos = 0x7
	// Bit mask of TCIE field.
	SWPMI_IER_TCIE_Msk = 0x80
	// Bit TCIE.
	SWPMI_IER_TCIE = 0x80
	// Position of SRIE field.
	SWPMI_IER_SRIE_Pos = 0x8
	// Bit mask of SRIE field.
	SWPMI_IER_SRIE_Msk = 0x100
	// Bit SRIE.
	SWPMI_IER_SRIE = 0x100
	// Position of RDYIE field.
	SWPMI_IER_RDYIE_Pos = 0xb
	// Bit mask of RDYIE field.
	SWPMI_IER_RDYIE_Msk = 0x800
	// Bit RDYIE.
	SWPMI_IER_RDYIE = 0x800

	// RFL: SWPMI Receive Frame Length register
	// Position of RFL field.
	SWPMI_RFL_RFL_Pos = 0x0
	// Bit mask of RFL field.
	SWPMI_RFL_RFL_Msk = 0x1f

	// TDR: SWPMI Transmit data register
	// Position of TD field.
	SWPMI_TDR_TD_Pos = 0x0
	// Bit mask of TD field.
	SWPMI_TDR_TD_Msk = 0xffffffff

	// RDR: SWPMI Receive data register
	// Position of RD field.
	SWPMI_RDR_RD_Pos = 0x0
	// Bit mask of RD field.
	SWPMI_RDR_RD_Msk = 0xffffffff

	// OR: SWPMI Option register
	// Position of SWP_TBYP field.
	SWPMI_OR_SWP_TBYP_Pos = 0x0
	// Bit mask of SWP_TBYP field.
	SWPMI_OR_SWP_TBYP_Msk = 0x1
	// Bit SWP_TBYP.
	SWPMI_OR_SWP_TBYP = 0x1
	// Position of SWP_CLASS field.
	SWPMI_OR_SWP_CLASS_Pos = 0x1
	// Bit mask of SWP_CLASS field.
	SWPMI_OR_SWP_CLASS_Msk = 0x2
	// Bit SWP_CLASS.
	SWPMI_OR_SWP_CLASS = 0x2
)

// Bitfields for NVIC: Nested Vectored Interrupt Controller
const (
	// ISER0: Interrupt Set-Enable Register
	// Position of SETENA field.
	NVIC_ISER0_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER0_SETENA_Msk = 0xffffffff

	// ISER1: Interrupt Set-Enable Register
	// Position of SETENA field.
	NVIC_ISER1_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER1_SETENA_Msk = 0xffffffff

	// ISER2: Interrupt Set-Enable Register
	// Position of SETENA field.
	NVIC_ISER2_SETENA_Pos = 0x0
	// Bit mask of SETENA field.
	NVIC_ISER2_SETENA_Msk = 0xffffffff

	// ICER0: Interrupt Clear-Enable Register
	// Position of CLRENA field.
	NVIC_ICER0_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER0_CLRENA_Msk = 0xffffffff

	// ICER1: Interrupt Clear-Enable Register
	// Position of CLRENA field.
	NVIC_ICER1_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER1_CLRENA_Msk = 0xffffffff

	// ICER2: Interrupt Clear-Enable Register
	// Position of CLRENA field.
	NVIC_ICER2_CLRENA_Pos = 0x0
	// Bit mask of CLRENA field.
	NVIC_ICER2_CLRENA_Msk = 0xffffffff

	// ISPR0: Interrupt Set-Pending Register
	// Position of SETPEND field.
	NVIC_ISPR0_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR0_SETPEND_Msk = 0xffffffff

	// ISPR1: Interrupt Set-Pending Register
	// Position of SETPEND field.
	NVIC_ISPR1_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR1_SETPEND_Msk = 0xffffffff

	// ISPR2: Interrupt Set-Pending Register
	// Position of SETPEND field.
	NVIC_ISPR2_SETPEND_Pos = 0x0
	// Bit mask of SETPEND field.
	NVIC_ISPR2_SETPEND_Msk = 0xffffffff

	// ICPR0: Interrupt Clear-Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR0_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR0_CLRPEND_Msk = 0xffffffff

	// ICPR1: Interrupt Clear-Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR1_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR1_CLRPEND_Msk = 0xffffffff

	// ICPR2: Interrupt Clear-Pending Register
	// Position of CLRPEND field.
	NVIC_ICPR2_CLRPEND_Pos = 0x0
	// Bit mask of CLRPEND field.
	NVIC_ICPR2_CLRPEND_Msk = 0xffffffff

	// IABR0: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR0_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR0_ACTIVE_Msk = 0xffffffff

	// IABR1: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR1_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR1_ACTIVE_Msk = 0xffffffff

	// IABR2: Interrupt Active Bit Register
	// Position of ACTIVE field.
	NVIC_IABR2_ACTIVE_Pos = 0x0
	// Bit mask of ACTIVE field.
	NVIC_IABR2_ACTIVE_Msk = 0xffffffff

	// IPR0: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR0_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR0_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR0_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR0_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR0_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR0_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR0_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR0_IPR_N3_Msk = 0xff000000

	// IPR1: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR1_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR1_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR1_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR1_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR1_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR1_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR1_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR1_IPR_N3_Msk = 0xff000000

	// IPR2: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR2_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR2_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR2_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR2_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR2_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR2_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR2_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR2_IPR_N3_Msk = 0xff000000

	// IPR3: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR3_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR3_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR3_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR3_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR3_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR3_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR3_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR3_IPR_N3_Msk = 0xff000000

	// IPR4: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR4_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR4_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR4_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR4_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR4_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR4_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR4_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR4_IPR_N3_Msk = 0xff000000

	// IPR5: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR5_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR5_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR5_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR5_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR5_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR5_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR5_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR5_IPR_N3_Msk = 0xff000000

	// IPR6: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR6_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR6_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR6_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR6_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR6_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR6_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR6_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR6_IPR_N3_Msk = 0xff000000

	// IPR7: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR7_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR7_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR7_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR7_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR7_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR7_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR7_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR7_IPR_N3_Msk = 0xff000000

	// IPR8: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR8_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR8_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR8_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR8_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR8_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR8_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR8_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR8_IPR_N3_Msk = 0xff000000

	// IPR9: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR9_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR9_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR9_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR9_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR9_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR9_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR9_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR9_IPR_N3_Msk = 0xff000000

	// IPR10: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR10_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR10_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR10_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR10_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR10_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR10_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR10_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR10_IPR_N3_Msk = 0xff000000

	// IPR11: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR11_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR11_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR11_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR11_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR11_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR11_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR11_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR11_IPR_N3_Msk = 0xff000000

	// IPR12: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR12_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR12_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR12_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR12_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR12_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR12_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR12_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR12_IPR_N3_Msk = 0xff000000

	// IPR13: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR13_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR13_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR13_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR13_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR13_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR13_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR13_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR13_IPR_N3_Msk = 0xff000000

	// IPR14: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR14_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR14_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR14_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR14_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR14_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR14_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR14_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR14_IPR_N3_Msk = 0xff000000

	// IPR15: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR15_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR15_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR15_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR15_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR15_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR15_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR15_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR15_IPR_N3_Msk = 0xff000000

	// IPR16: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR16_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR16_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR16_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR16_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR16_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR16_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR16_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR16_IPR_N3_Msk = 0xff000000

	// IPR17: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR17_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR17_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR17_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR17_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR17_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR17_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR17_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR17_IPR_N3_Msk = 0xff000000

	// IPR18: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR18_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR18_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR18_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR18_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR18_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR18_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR18_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR18_IPR_N3_Msk = 0xff000000

	// IPR19: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR19_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR19_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR19_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR19_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR19_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR19_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR19_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR19_IPR_N3_Msk = 0xff000000

	// IPR20: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR20_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR20_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR20_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR20_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR20_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR20_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR20_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR20_IPR_N3_Msk = 0xff000000

	// IPR21: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR21_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR21_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR21_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR21_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR21_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR21_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR21_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR21_IPR_N3_Msk = 0xff000000

	// IPR22: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR22_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR22_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR22_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR22_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR22_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR22_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR22_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR22_IPR_N3_Msk = 0xff000000

	// IPR23: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR23_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR23_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR23_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR23_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR23_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR23_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR23_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR23_IPR_N3_Msk = 0xff000000

	// IPR24: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR24_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR24_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR24_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR24_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR24_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR24_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR24_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR24_IPR_N3_Msk = 0xff000000

	// IPR25: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR25_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR25_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR25_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR25_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR25_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR25_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR25_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR25_IPR_N3_Msk = 0xff000000

	// IPR26: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR26_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR26_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR26_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR26_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR26_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR26_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR26_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR26_IPR_N3_Msk = 0xff000000

	// IPR27: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR27_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR27_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR27_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR27_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR27_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR27_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR27_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR27_IPR_N3_Msk = 0xff000000

	// IPR28: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR28_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR28_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR28_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR28_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR28_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR28_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR28_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR28_IPR_N3_Msk = 0xff000000

	// IPR29: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR29_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR29_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR29_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR29_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR29_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR29_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR29_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR29_IPR_N3_Msk = 0xff000000

	// IPR30: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR30_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR30_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR30_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR30_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR30_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR30_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR30_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR30_IPR_N3_Msk = 0xff000000

	// IPR31: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR31_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR31_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR31_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR31_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR31_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR31_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR31_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR31_IPR_N3_Msk = 0xff000000

	// IPR32: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR32_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR32_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR32_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR32_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR32_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR32_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR32_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR32_IPR_N3_Msk = 0xff000000

	// IPR33: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR33_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR33_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR33_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR33_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR33_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR33_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR33_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR33_IPR_N3_Msk = 0xff000000

	// IPR34: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR34_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR34_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR34_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR34_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR34_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR34_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR34_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR34_IPR_N3_Msk = 0xff000000

	// IPR35: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR35_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR35_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR35_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR35_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR35_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR35_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR35_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR35_IPR_N3_Msk = 0xff000000

	// IPR36: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR36_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR36_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR36_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR36_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR36_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR36_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR36_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR36_IPR_N3_Msk = 0xff000000

	// IPR37: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR37_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR37_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR37_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR37_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR37_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR37_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR37_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR37_IPR_N3_Msk = 0xff000000

	// IPR38: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR38_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR38_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR38_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR38_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR38_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR38_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR38_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR38_IPR_N3_Msk = 0xff000000

	// IPR39: Interrupt Priority Register
	// Position of IPR_N0 field.
	NVIC_IPR39_IPR_N0_Pos = 0x0
	// Bit mask of IPR_N0 field.
	NVIC_IPR39_IPR_N0_Msk = 0xff
	// Position of IPR_N1 field.
	NVIC_IPR39_IPR_N1_Pos = 0x8
	// Bit mask of IPR_N1 field.
	NVIC_IPR39_IPR_N1_Msk = 0xff00
	// Position of IPR_N2 field.
	NVIC_IPR39_IPR_N2_Pos = 0x10
	// Bit mask of IPR_N2 field.
	NVIC_IPR39_IPR_N2_Msk = 0xff0000
	// Position of IPR_N3 field.
	NVIC_IPR39_IPR_N3_Pos = 0x18
	// Bit mask of IPR_N3 field.
	NVIC_IPR39_IPR_N3_Msk = 0xff000000
)

// Bitfields for MPU: Memory protection unit
const (
	// MPU_TYPER: MPU type register
	// Position of SEPARATE field.
	MPU_MPU_TYPER_SEPARATE_Pos = 0x0
	// Bit mask of SEPARATE field.
	MPU_MPU_TYPER_SEPARATE_Msk = 0x1
	// Bit SEPARATE.
	MPU_MPU_TYPER_SEPARATE = 0x1
	// Position of DREGION field.
	MPU_MPU_TYPER_DREGION_Pos = 0x8
	// Bit mask of DREGION field.
	MPU_MPU_TYPER_DREGION_Msk = 0xff00
	// Position of IREGION field.
	MPU_MPU_TYPER_IREGION_Pos = 0x10
	// Bit mask of IREGION field.
	MPU_MPU_TYPER_IREGION_Msk = 0xff0000

	// MPU_CTRL: MPU control register
	// Position of ENABLE field.
	MPU_MPU_CTRL_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	MPU_MPU_CTRL_ENABLE_Msk = 0x1
	// Bit ENABLE.
	MPU_MPU_CTRL_ENABLE = 0x1
	// Position of HFNMIENA field.
	MPU_MPU_CTRL_HFNMIENA_Pos = 0x1
	// Bit mask of HFNMIENA field.
	MPU_MPU_CTRL_HFNMIENA_Msk = 0x2
	// Bit HFNMIENA.
	MPU_MPU_CTRL_HFNMIENA = 0x2
	// Position of PRIVDEFENA field.
	MPU_MPU_CTRL_PRIVDEFENA_Pos = 0x2
	// Bit mask of PRIVDEFENA field.
	MPU_MPU_CTRL_PRIVDEFENA_Msk = 0x4
	// Bit PRIVDEFENA.
	MPU_MPU_CTRL_PRIVDEFENA = 0x4

	// MPU_RNR: MPU region number register
	// Position of REGION field.
	MPU_MPU_RNR_REGION_Pos = 0x0
	// Bit mask of REGION field.
	MPU_MPU_RNR_REGION_Msk = 0xff

	// MPU_RBAR: MPU region base address register
	// Position of REGION field.
	MPU_MPU_RBAR_REGION_Pos = 0x0
	// Bit mask of REGION field.
	MPU_MPU_RBAR_REGION_Msk = 0xf
	// Position of VALID field.
	MPU_MPU_RBAR_VALID_Pos = 0x4
	// Bit mask of VALID field.
	MPU_MPU_RBAR_VALID_Msk = 0x10
	// Bit VALID.
	MPU_MPU_RBAR_VALID = 0x10
	// Position of ADDR field.
	MPU_MPU_RBAR_ADDR_Pos = 0x5
	// Bit mask of ADDR field.
	MPU_MPU_RBAR_ADDR_Msk = 0xffffffe0

	// MPU_RASR: MPU region attribute and size register
	// Position of ENABLE field.
	MPU_MPU_RASR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	MPU_MPU_RASR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	MPU_MPU_RASR_ENABLE = 0x1
	// Position of SIZE field.
	MPU_MPU_RASR_SIZE_Pos = 0x1
	// Bit mask of SIZE field.
	MPU_MPU_RASR_SIZE_Msk = 0x3e
	// Position of SRD field.
	MPU_MPU_RASR_SRD_Pos = 0x8
	// Bit mask of SRD field.
	MPU_MPU_RASR_SRD_Msk = 0xff00
	// Position of B field.
	MPU_MPU_RASR_B_Pos = 0x10
	// Bit mask of B field.
	MPU_MPU_RASR_B_Msk = 0x10000
	// Bit B.
	MPU_MPU_RASR_B = 0x10000
	// Position of C field.
	MPU_MPU_RASR_C_Pos = 0x11
	// Bit mask of C field.
	MPU_MPU_RASR_C_Msk = 0x20000
	// Bit C.
	MPU_MPU_RASR_C = 0x20000
	// Position of S field.
	MPU_MPU_RASR_S_Pos = 0x12
	// Bit mask of S field.
	MPU_MPU_RASR_S_Msk = 0x40000
	// Bit S.
	MPU_MPU_RASR_S = 0x40000
	// Position of TEX field.
	MPU_MPU_RASR_TEX_Pos = 0x13
	// Bit mask of TEX field.
	MPU_MPU_RASR_TEX_Msk = 0x380000
	// Position of AP field.
	MPU_MPU_RASR_AP_Pos = 0x18
	// Bit mask of AP field.
	MPU_MPU_RASR_AP_Msk = 0x7000000
	// Position of XN field.
	MPU_MPU_RASR_XN_Pos = 0x1c
	// Bit mask of XN field.
	MPU_MPU_RASR_XN_Msk = 0x10000000
	// Bit XN.
	MPU_MPU_RASR_XN = 0x10000000
)

// Bitfields for STK: SysTick timer
const (
	// CSR: SysTick control and status register
	// Position of ENABLE field.
	STK_CSR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	STK_CSR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	STK_CSR_ENABLE = 0x1
	// Position of TICKINT field.
	STK_CSR_TICKINT_Pos = 0x1
	// Bit mask of TICKINT field.
	STK_CSR_TICKINT_Msk = 0x2
	// Bit TICKINT.
	STK_CSR_TICKINT = 0x2
	// Position of CLKSOURCE field.
	STK_CSR_CLKSOURCE_Pos = 0x2
	// Bit mask of CLKSOURCE field.
	STK_CSR_CLKSOURCE_Msk = 0x4
	// Bit CLKSOURCE.
	STK_CSR_CLKSOURCE = 0x4
	// Position of COUNTFLAG field.
	STK_CSR_COUNTFLAG_Pos = 0x10
	// Bit mask of COUNTFLAG field.
	STK_CSR_COUNTFLAG_Msk = 0x10000
	// Bit COUNTFLAG.
	STK_CSR_COUNTFLAG = 0x10000

	// RVR: SysTick reload value register
	// Position of RELOAD field.
	STK_RVR_RELOAD_Pos = 0x0
	// Bit mask of RELOAD field.
	STK_RVR_RELOAD_Msk = 0xffffff

	// CVR: SysTick current value register
	// Position of CURRENT field.
	STK_CVR_CURRENT_Pos = 0x0
	// Bit mask of CURRENT field.
	STK_CVR_CURRENT_Msk = 0xffffff

	// CALIB: SysTick calibration value register
	// Position of TENMS field.
	STK_CALIB_TENMS_Pos = 0x0
	// Bit mask of TENMS field.
	STK_CALIB_TENMS_Msk = 0xffffff
	// Position of SKEW field.
	STK_CALIB_SKEW_Pos = 0x1e
	// Bit mask of SKEW field.
	STK_CALIB_SKEW_Msk = 0x40000000
	// Bit SKEW.
	STK_CALIB_SKEW = 0x40000000
	// Position of NOREF field.
	STK_CALIB_NOREF_Pos = 0x1f
	// Bit mask of NOREF field.
	STK_CALIB_NOREF_Msk = 0x80000000
	// Bit NOREF.
	STK_CALIB_NOREF = 0x80000000
)

// Bitfields for FPU_CPACR: Floating point unit CPACR
const (
	// CPACR: Coprocessor access control register
	// Position of CP field.
	FPU_CPACR_CP_Pos = 0x14
	// Bit mask of CP field.
	FPU_CPACR_CP_Msk = 0xf00000
)

// Bitfields for SCB_ACTRL: System control block ACTLR
const (
	// ACTRL: Auxiliary control register
	// Position of DISFOLD field.
	SCB_ACTRL_DISFOLD_Pos = 0x2
	// Bit mask of DISFOLD field.
	SCB_ACTRL_DISFOLD_Msk = 0x4
	// Bit DISFOLD.
	SCB_ACTRL_DISFOLD = 0x4
	// Position of FPEXCODIS field.
	SCB_ACTRL_FPEXCODIS_Pos = 0xa
	// Bit mask of FPEXCODIS field.
	SCB_ACTRL_FPEXCODIS_Msk = 0x400
	// Bit FPEXCODIS.
	SCB_ACTRL_FPEXCODIS = 0x400
	// Position of DISRAMODE field.
	SCB_ACTRL_DISRAMODE_Pos = 0xb
	// Bit mask of DISRAMODE field.
	SCB_ACTRL_DISRAMODE_Msk = 0x800
	// Bit DISRAMODE.
	SCB_ACTRL_DISRAMODE = 0x800
	// Position of DISITMATBFLUSH field.
	SCB_ACTRL_DISITMATBFLUSH_Pos = 0xc
	// Bit mask of DISITMATBFLUSH field.
	SCB_ACTRL_DISITMATBFLUSH_Msk = 0x1000
	// Bit DISITMATBFLUSH.
	SCB_ACTRL_DISITMATBFLUSH = 0x1000
)

// Bitfields for PF: Processor features
const (
	// CLIDR: Cache Level ID register
	// Position of CL1 field.
	PF_CLIDR_CL1_Pos = 0x0
	// Bit mask of CL1 field.
	PF_CLIDR_CL1_Msk = 0x7
	// Position of CL2 field.
	PF_CLIDR_CL2_Pos = 0x3
	// Bit mask of CL2 field.
	PF_CLIDR_CL2_Msk = 0x38
	// Position of CL3 field.
	PF_CLIDR_CL3_Pos = 0x6
	// Bit mask of CL3 field.
	PF_CLIDR_CL3_Msk = 0x1c0
	// Position of CL4 field.
	PF_CLIDR_CL4_Pos = 0x9
	// Bit mask of CL4 field.
	PF_CLIDR_CL4_Msk = 0xe00
	// Position of CL5 field.
	PF_CLIDR_CL5_Pos = 0xc
	// Bit mask of CL5 field.
	PF_CLIDR_CL5_Msk = 0x7000
	// Position of CL6 field.
	PF_CLIDR_CL6_Pos = 0xf
	// Bit mask of CL6 field.
	PF_CLIDR_CL6_Msk = 0x38000
	// Position of CL7 field.
	PF_CLIDR_CL7_Pos = 0x12
	// Bit mask of CL7 field.
	PF_CLIDR_CL7_Msk = 0x1c0000
	// Position of LoUIS field.
	PF_CLIDR_LoUIS_Pos = 0x15
	// Bit mask of LoUIS field.
	PF_CLIDR_LoUIS_Msk = 0xe00000
	// Position of LoC field.
	PF_CLIDR_LoC_Pos = 0x18
	// Bit mask of LoC field.
	PF_CLIDR_LoC_Msk = 0x7000000
	// Position of LoU field.
	PF_CLIDR_LoU_Pos = 0x1b
	// Bit mask of LoU field.
	PF_CLIDR_LoU_Msk = 0x38000000

	// CTR: Cache Type register
	// Position of _IMINLINE field.
	PF_CTR__IMINLINE_Pos = 0x0
	// Bit mask of _IMINLINE field.
	PF_CTR__IMINLINE_Msk = 0xf
	// Position of DMinLine field.
	PF_CTR_DMinLine_Pos = 0x10
	// Bit mask of DMinLine field.
	PF_CTR_DMinLine_Msk = 0xf0000
	// Position of ERG field.
	PF_CTR_ERG_Pos = 0x14
	// Bit mask of ERG field.
	PF_CTR_ERG_Msk = 0xf00000
	// Position of CWG field.
	PF_CTR_CWG_Pos = 0x18
	// Bit mask of CWG field.
	PF_CTR_CWG_Msk = 0xf000000
	// Position of Format field.
	PF_CTR_Format_Pos = 0x1d
	// Bit mask of Format field.
	PF_CTR_Format_Msk = 0xe0000000

	// CCSIDR: Cache Size ID register
	// Position of LineSize field.
	PF_CCSIDR_LineSize_Pos = 0x0
	// Bit mask of LineSize field.
	PF_CCSIDR_LineSize_Msk = 0x7
	// Position of Associativity field.
	PF_CCSIDR_Associativity_Pos = 0x3
	// Bit mask of Associativity field.
	PF_CCSIDR_Associativity_Msk = 0x1ff8
	// Position of NumSets field.
	PF_CCSIDR_NumSets_Pos = 0xd
	// Bit mask of NumSets field.
	PF_CCSIDR_NumSets_Msk = 0xfffe000
	// Position of WA field.
	PF_CCSIDR_WA_Pos = 0x1c
	// Bit mask of WA field.
	PF_CCSIDR_WA_Msk = 0x10000000
	// Bit WA.
	PF_CCSIDR_WA = 0x10000000
	// Position of RA field.
	PF_CCSIDR_RA_Pos = 0x1d
	// Bit mask of RA field.
	PF_CCSIDR_RA_Msk = 0x20000000
	// Bit RA.
	PF_CCSIDR_RA = 0x20000000
	// Position of WB field.
	PF_CCSIDR_WB_Pos = 0x1e
	// Bit mask of WB field.
	PF_CCSIDR_WB_Msk = 0x40000000
	// Bit WB.
	PF_CCSIDR_WB = 0x40000000
	// Position of WT field.
	PF_CCSIDR_WT_Pos = 0x1f
	// Bit mask of WT field.
	PF_CCSIDR_WT_Msk = 0x80000000
	// Bit WT.
	PF_CCSIDR_WT = 0x80000000
)

// Bitfields for AC: Access control
const (
	// ITCMCR: Instruction and Data Tightly-Coupled Memory Control Registers
	// Position of EN field.
	AC_ITCMCR_EN_Pos = 0x0
	// Bit mask of EN field.
	AC_ITCMCR_EN_Msk = 0x1
	// Bit EN.
	AC_ITCMCR_EN = 0x1
	// Position of RMW field.
	AC_ITCMCR_RMW_Pos = 0x1
	// Bit mask of RMW field.
	AC_ITCMCR_RMW_Msk = 0x2
	// Bit RMW.
	AC_ITCMCR_RMW = 0x2
	// Position of RETEN field.
	AC_ITCMCR_RETEN_Pos = 0x2
	// Bit mask of RETEN field.
	AC_ITCMCR_RETEN_Msk = 0x4
	// Bit RETEN.
	AC_ITCMCR_RETEN = 0x4
	// Position of SZ field.
	AC_ITCMCR_SZ_Pos = 0x3
	// Bit mask of SZ field.
	AC_ITCMCR_SZ_Msk = 0x78

	// DTCMCR: Instruction and Data Tightly-Coupled Memory Control Registers
	// Position of EN field.
	AC_DTCMCR_EN_Pos = 0x0
	// Bit mask of EN field.
	AC_DTCMCR_EN_Msk = 0x1
	// Bit EN.
	AC_DTCMCR_EN = 0x1
	// Position of RMW field.
	AC_DTCMCR_RMW_Pos = 0x1
	// Bit mask of RMW field.
	AC_DTCMCR_RMW_Msk = 0x2
	// Bit RMW.
	AC_DTCMCR_RMW = 0x2
	// Position of RETEN field.
	AC_DTCMCR_RETEN_Pos = 0x2
	// Bit mask of RETEN field.
	AC_DTCMCR_RETEN_Msk = 0x4
	// Bit RETEN.
	AC_DTCMCR_RETEN = 0x4
	// Position of SZ field.
	AC_DTCMCR_SZ_Pos = 0x3
	// Bit mask of SZ field.
	AC_DTCMCR_SZ_Msk = 0x78

	// AHBPCR: AHBP Control register
	// Position of EN field.
	AC_AHBPCR_EN_Pos = 0x0
	// Bit mask of EN field.
	AC_AHBPCR_EN_Msk = 0x1
	// Bit EN.
	AC_AHBPCR_EN = 0x1
	// Position of SZ field.
	AC_AHBPCR_SZ_Pos = 0x1
	// Bit mask of SZ field.
	AC_AHBPCR_SZ_Msk = 0xe

	// CACR: Auxiliary Cache Control register
	// Position of SIWT field.
	AC_CACR_SIWT_Pos = 0x0
	// Bit mask of SIWT field.
	AC_CACR_SIWT_Msk = 0x1
	// Bit SIWT.
	AC_CACR_SIWT = 0x1
	// Position of ECCEN field.
	AC_CACR_ECCEN_Pos = 0x1
	// Bit mask of ECCEN field.
	AC_CACR_ECCEN_Msk = 0x2
	// Bit ECCEN.
	AC_CACR_ECCEN = 0x2
	// Position of FORCEWT field.
	AC_CACR_FORCEWT_Pos = 0x2
	// Bit mask of FORCEWT field.
	AC_CACR_FORCEWT_Msk = 0x4
	// Bit FORCEWT.
	AC_CACR_FORCEWT = 0x4

	// AHBSCR: AHB Slave Control register
	// Position of CTL field.
	AC_AHBSCR_CTL_Pos = 0x0
	// Bit mask of CTL field.
	AC_AHBSCR_CTL_Msk = 0x3
	// Position of TPRI field.
	AC_AHBSCR_TPRI_Pos = 0x2
	// Bit mask of TPRI field.
	AC_AHBSCR_TPRI_Msk = 0x7fc
	// Position of INITCOUNT field.
	AC_AHBSCR_INITCOUNT_Pos = 0xb
	// Bit mask of INITCOUNT field.
	AC_AHBSCR_INITCOUNT_Msk = 0xf800

	// ABFSR: Auxiliary Bus Fault Status register
	// Position of ITCM field.
	AC_ABFSR_ITCM_Pos = 0x0
	// Bit mask of ITCM field.
	AC_ABFSR_ITCM_Msk = 0x1
	// Bit ITCM.
	AC_ABFSR_ITCM = 0x1
	// Position of DTCM field.
	AC_ABFSR_DTCM_Pos = 0x1
	// Bit mask of DTCM field.
	AC_ABFSR_DTCM_Msk = 0x2
	// Bit DTCM.
	AC_ABFSR_DTCM = 0x2
	// Position of AHBP field.
	AC_ABFSR_AHBP_Pos = 0x2
	// Bit mask of AHBP field.
	AC_ABFSR_AHBP_Msk = 0x4
	// Bit AHBP.
	AC_ABFSR_AHBP = 0x4
	// Position of AXIM field.
	AC_ABFSR_AXIM_Pos = 0x3
	// Bit mask of AXIM field.
	AC_ABFSR_AXIM_Msk = 0x8
	// Bit AXIM.
	AC_ABFSR_AXIM = 0x8
	// Position of EPPB field.
	AC_ABFSR_EPPB_Pos = 0x4
	// Bit mask of EPPB field.
	AC_ABFSR_EPPB_Msk = 0x10
	// Bit EPPB.
	AC_ABFSR_EPPB = 0x10
	// Position of AXIMTYPE field.
	AC_ABFSR_AXIMTYPE_Pos = 0x8
	// Bit mask of AXIMTYPE field.
	AC_ABFSR_AXIMTYPE_Msk = 0x300
)

// Bitfields for DBGMCU: Debug support
const (
	// IDC: Identity code
	// Position of REV_ID field.
	DBG_IDC_REV_ID_Pos = 0x10
	// Bit mask of REV_ID field.
	DBG_IDC_REV_ID_Msk = 0xffff0000
	// Position of DEV_ID field.
	DBG_IDC_DEV_ID_Pos = 0x0
	// Bit mask of DEV_ID field.
	DBG_IDC_DEV_ID_Msk = 0xfff

	// CR: Configuration register
	// Position of TRGOEN field.
	DBG_CR_TRGOEN_Pos = 0x1c
	// Bit mask of TRGOEN field.
	DBG_CR_TRGOEN_Msk = 0x10000000
	// Bit TRGOEN.
	DBG_CR_TRGOEN = 0x10000000
	// Position of D3DBGCKEN field.
	DBG_CR_D3DBGCKEN_Pos = 0x16
	// Bit mask of D3DBGCKEN field.
	DBG_CR_D3DBGCKEN_Msk = 0x400000
	// Bit D3DBGCKEN.
	DBG_CR_D3DBGCKEN = 0x400000
	// Position of D1DBGCKEN field.
	DBG_CR_D1DBGCKEN_Pos = 0x15
	// Bit mask of D1DBGCKEN field.
	DBG_CR_D1DBGCKEN_Msk = 0x200000
	// Bit D1DBGCKEN.
	DBG_CR_D1DBGCKEN = 0x200000
	// Position of TRACECLKEN field.
	DBG_CR_TRACECLKEN_Pos = 0x14
	// Bit mask of TRACECLKEN field.
	DBG_CR_TRACECLKEN_Msk = 0x100000
	// Bit TRACECLKEN.
	DBG_CR_TRACECLKEN = 0x100000
	// Position of DBGSTBY_D1 field.
	DBG_CR_DBGSTBY_D1_Pos = 0x2
	// Bit mask of DBGSTBY_D1 field.
	DBG_CR_DBGSTBY_D1_Msk = 0x4
	// Bit DBGSTBY_D1.
	DBG_CR_DBGSTBY_D1 = 0x4
	// Position of DBGSTOP_D1 field.
	DBG_CR_DBGSTOP_D1_Pos = 0x1
	// Bit mask of DBGSTOP_D1 field.
	DBG_CR_DBGSTOP_D1_Msk = 0x2
	// Bit DBGSTOP_D1.
	DBG_CR_DBGSTOP_D1 = 0x2
	// Position of DBGSLEEP_D1 field.
	DBG_CR_DBGSLEEP_D1_Pos = 0x0
	// Bit mask of DBGSLEEP_D1 field.
	DBG_CR_DBGSLEEP_D1_Msk = 0x1
	// Bit DBGSLEEP_D1.
	DBG_CR_DBGSLEEP_D1 = 0x1

	// APB3FZ1: APB3 peripheral freeze register
	// Position of WWDG1 field.
	DBG_APB3FZ1_WWDG1_Pos = 0x6
	// Bit mask of WWDG1 field.
	DBG_APB3FZ1_WWDG1_Msk = 0x40
	// Bit WWDG1.
	DBG_APB3FZ1_WWDG1 = 0x40

	// APB1LFZ1: APB1L peripheral freeze register
	// Position of I2C3 field.
	DBG_APB1LFZ1_I2C3_Pos = 0x17
	// Bit mask of I2C3 field.
	DBG_APB1LFZ1_I2C3_Msk = 0x800000
	// Bit I2C3.
	DBG_APB1LFZ1_I2C3 = 0x800000
	// Position of I2C2 field.
	DBG_APB1LFZ1_I2C2_Pos = 0x16
	// Bit mask of I2C2 field.
	DBG_APB1LFZ1_I2C2_Msk = 0x400000
	// Bit I2C2.
	DBG_APB1LFZ1_I2C2 = 0x400000
	// Position of I2C1 field.
	DBG_APB1LFZ1_I2C1_Pos = 0x15
	// Bit mask of I2C1 field.
	DBG_APB1LFZ1_I2C1_Msk = 0x200000
	// Bit I2C1.
	DBG_APB1LFZ1_I2C1 = 0x200000
	// Position of LPTIM1 field.
	DBG_APB1LFZ1_LPTIM1_Pos = 0x9
	// Bit mask of LPTIM1 field.
	DBG_APB1LFZ1_LPTIM1_Msk = 0x200
	// Bit LPTIM1.
	DBG_APB1LFZ1_LPTIM1 = 0x200
	// Position of TIM14 field.
	DBG_APB1LFZ1_TIM14_Pos = 0x8
	// Bit mask of TIM14 field.
	DBG_APB1LFZ1_TIM14_Msk = 0x100
	// Bit TIM14.
	DBG_APB1LFZ1_TIM14 = 0x100
	// Position of TIM13 field.
	DBG_APB1LFZ1_TIM13_Pos = 0x7
	// Bit mask of TIM13 field.
	DBG_APB1LFZ1_TIM13_Msk = 0x80
	// Bit TIM13.
	DBG_APB1LFZ1_TIM13 = 0x80
	// Position of TIM12 field.
	DBG_APB1LFZ1_TIM12_Pos = 0x6
	// Bit mask of TIM12 field.
	DBG_APB1LFZ1_TIM12_Msk = 0x40
	// Bit TIM12.
	DBG_APB1LFZ1_TIM12 = 0x40
	// Position of TIM7 field.
	DBG_APB1LFZ1_TIM7_Pos = 0x5
	// Bit mask of TIM7 field.
	DBG_APB1LFZ1_TIM7_Msk = 0x20
	// Bit TIM7.
	DBG_APB1LFZ1_TIM7 = 0x20
	// Position of TIM6 field.
	DBG_APB1LFZ1_TIM6_Pos = 0x4
	// Bit mask of TIM6 field.
	DBG_APB1LFZ1_TIM6_Msk = 0x10
	// Bit TIM6.
	DBG_APB1LFZ1_TIM6 = 0x10
	// Position of TIM5 field.
	DBG_APB1LFZ1_TIM5_Pos = 0x3
	// Bit mask of TIM5 field.
	DBG_APB1LFZ1_TIM5_Msk = 0x8
	// Bit TIM5.
	DBG_APB1LFZ1_TIM5 = 0x8
	// Position of TIM4 field.
	DBG_APB1LFZ1_TIM4_Pos = 0x2
	// Bit mask of TIM4 field.
	DBG_APB1LFZ1_TIM4_Msk = 0x4
	// Bit TIM4.
	DBG_APB1LFZ1_TIM4 = 0x4
	// Position of TIM3 field.
	DBG_APB1LFZ1_TIM3_Pos = 0x1
	// Bit mask of TIM3 field.
	DBG_APB1LFZ1_TIM3_Msk = 0x2
	// Bit TIM3.
	DBG_APB1LFZ1_TIM3 = 0x2
	// Position of TIM2 field.
	DBG_APB1LFZ1_TIM2_Pos = 0x0
	// Bit mask of TIM2 field.
	DBG_APB1LFZ1_TIM2_Msk = 0x1
	// Bit TIM2.
	DBG_APB1LFZ1_TIM2 = 0x1

	// APB2FZ1: APB2 peripheral freeze register
	// Position of HRTIM field.
	DBG_APB2FZ1_HRTIM_Pos = 0x1d
	// Bit mask of HRTIM field.
	DBG_APB2FZ1_HRTIM_Msk = 0x20000000
	// Bit HRTIM.
	DBG_APB2FZ1_HRTIM = 0x20000000
	// Position of TIM17 field.
	DBG_APB2FZ1_TIM17_Pos = 0x12
	// Bit mask of TIM17 field.
	DBG_APB2FZ1_TIM17_Msk = 0x40000
	// Bit TIM17.
	DBG_APB2FZ1_TIM17 = 0x40000
	// Position of TIM16 field.
	DBG_APB2FZ1_TIM16_Pos = 0x11
	// Bit mask of TIM16 field.
	DBG_APB2FZ1_TIM16_Msk = 0x20000
	// Bit TIM16.
	DBG_APB2FZ1_TIM16 = 0x20000
	// Position of TIM15 field.
	DBG_APB2FZ1_TIM15_Pos = 0x10
	// Bit mask of TIM15 field.
	DBG_APB2FZ1_TIM15_Msk = 0x10000
	// Bit TIM15.
	DBG_APB2FZ1_TIM15 = 0x10000
	// Position of TIM8 field.
	DBG_APB2FZ1_TIM8_Pos = 0x1
	// Bit mask of TIM8 field.
	DBG_APB2FZ1_TIM8_Msk = 0x2
	// Bit TIM8.
	DBG_APB2FZ1_TIM8 = 0x2
	// Position of TIM1 field.
	DBG_APB2FZ1_TIM1_Pos = 0x0
	// Bit mask of TIM1 field.
	DBG_APB2FZ1_TIM1_Msk = 0x1
	// Bit TIM1.
	DBG_APB2FZ1_TIM1 = 0x1

	// APB4FZ1: APB4 peripheral freeze register
	// Position of IWDG1 field.
	DBG_APB4FZ1_IWDG1_Pos = 0x12
	// Bit mask of IWDG1 field.
	DBG_APB4FZ1_IWDG1_Msk = 0x40000
	// Bit IWDG1.
	DBG_APB4FZ1_IWDG1 = 0x40000
	// Position of RTC field.
	DBG_APB4FZ1_RTC_Pos = 0x10
	// Bit mask of RTC field.
	DBG_APB4FZ1_RTC_Msk = 0x10000
	// Bit RTC.
	DBG_APB4FZ1_RTC = 0x10000
	// Position of LPTIM5 field.
	DBG_APB4FZ1_LPTIM5_Pos = 0xc
	// Bit mask of LPTIM5 field.
	DBG_APB4FZ1_LPTIM5_Msk = 0x1000
	// Bit LPTIM5.
	DBG_APB4FZ1_LPTIM5 = 0x1000
	// Position of LPTIM4 field.
	DBG_APB4FZ1_LPTIM4_Pos = 0xb
	// Bit mask of LPTIM4 field.
	DBG_APB4FZ1_LPTIM4_Msk = 0x800
	// Bit LPTIM4.
	DBG_APB4FZ1_LPTIM4 = 0x800
	// Position of LPTIM3 field.
	DBG_APB4FZ1_LPTIM3_Pos = 0xa
	// Bit mask of LPTIM3 field.
	DBG_APB4FZ1_LPTIM3_Msk = 0x400
	// Bit LPTIM3.
	DBG_APB4FZ1_LPTIM3 = 0x400
	// Position of LPTIM2 field.
	DBG_APB4FZ1_LPTIM2_Pos = 0x9
	// Bit mask of LPTIM2 field.
	DBG_APB4FZ1_LPTIM2_Msk = 0x200
	// Bit LPTIM2.
	DBG_APB4FZ1_LPTIM2 = 0x200
	// Position of I2C4 field.
	DBG_APB4FZ1_I2C4_Pos = 0x7
	// Bit mask of I2C4 field.
	DBG_APB4FZ1_I2C4_Msk = 0x80
	// Bit I2C4.
	DBG_APB4FZ1_I2C4 = 0x80
)

// Bitfields for RAMECC1: RAM ECC monitoring
const (
	// IER: RAMECC interrupt enable register
	// Position of GECCDEBWIE field.
	RAMECC_IER_GECCDEBWIE_Pos = 0x3
	// Bit mask of GECCDEBWIE field.
	RAMECC_IER_GECCDEBWIE_Msk = 0x8
	// Bit GECCDEBWIE.
	RAMECC_IER_GECCDEBWIE = 0x8
	// Position of GECCDEIE field.
	RAMECC_IER_GECCDEIE_Pos = 0x2
	// Bit mask of GECCDEIE field.
	RAMECC_IER_GECCDEIE_Msk = 0x4
	// Bit GECCDEIE.
	RAMECC_IER_GECCDEIE = 0x4
	// Position of GECCSEIE field.
	RAMECC_IER_GECCSEIE_Pos = 0x1
	// Bit mask of GECCSEIE field.
	RAMECC_IER_GECCSEIE_Msk = 0x2
	// Bit GECCSEIE.
	RAMECC_IER_GECCSEIE = 0x2
	// Position of GIE field.
	RAMECC_IER_GIE_Pos = 0x0
	// Bit mask of GIE field.
	RAMECC_IER_GIE_Msk = 0x1
	// Bit GIE.
	RAMECC_IER_GIE = 0x1

	// M1CR: RAMECC monitor 1 configuration register
	// Position of ECCELEN field.
	RAMECC_M1CR_ECCELEN_Pos = 0x5
	// Bit mask of ECCELEN field.
	RAMECC_M1CR_ECCELEN_Msk = 0x20
	// Bit ECCELEN.
	RAMECC_M1CR_ECCELEN = 0x20
	// Position of ECCDEBWIE field.
	RAMECC_M1CR_ECCDEBWIE_Pos = 0x4
	// Bit mask of ECCDEBWIE field.
	RAMECC_M1CR_ECCDEBWIE_Msk = 0x10
	// Bit ECCDEBWIE.
	RAMECC_M1CR_ECCDEBWIE = 0x10
	// Position of ECCDEIE field.
	RAMECC_M1CR_ECCDEIE_Pos = 0x3
	// Bit mask of ECCDEIE field.
	RAMECC_M1CR_ECCDEIE_Msk = 0x8
	// Bit ECCDEIE.
	RAMECC_M1CR_ECCDEIE = 0x8
	// Position of ECCSEIE field.
	RAMECC_M1CR_ECCSEIE_Pos = 0x2
	// Bit mask of ECCSEIE field.
	RAMECC_M1CR_ECCSEIE_Msk = 0x4
	// Bit ECCSEIE.
	RAMECC_M1CR_ECCSEIE = 0x4

	// M1SR: RAMECC monitor 1 status register
	// Position of DEBWDF field.
	RAMECC_M1SR_DEBWDF_Pos = 0x2
	// Bit mask of DEBWDF field.
	RAMECC_M1SR_DEBWDF_Msk = 0x4
	// Bit DEBWDF.
	RAMECC_M1SR_DEBWDF = 0x4
	// Position of DEDF field.
	RAMECC_M1SR_DEDF_Pos = 0x1
	// Bit mask of DEDF field.
	RAMECC_M1SR_DEDF_Msk = 0x2
	// Bit DEDF.
	RAMECC_M1SR_DEDF = 0x2
	// Position of SEDCF field.
	RAMECC_M1SR_SEDCF_Pos = 0x0
	// Bit mask of SEDCF field.
	RAMECC_M1SR_SEDCF_Msk = 0x1
	// Bit SEDCF.
	RAMECC_M1SR_SEDCF = 0x1

	// M1FAR: RAMECC monitor 1 failing address register
	// Position of FADD field.
	RAMECC_M1FAR_FADD_Pos = 0x0
	// Bit mask of FADD field.
	RAMECC_M1FAR_FADD_Msk = 0xffffffff

	// M1FDRL: RAMECC monitor 1 failing data low register
	// Position of FDATAL field.
	RAMECC_M1FDRL_FDATAL_Pos = 0x0
	// Bit mask of FDATAL field.
	RAMECC_M1FDRL_FDATAL_Msk = 0xffffffff

	// M1FDRH: RAMECC monitor 1 failing data high register
	// Position of FDATAH field.
	RAMECC_M1FDRH_FDATAH_Pos = 0x0
	// Bit mask of FDATAH field.
	RAMECC_M1FDRH_FDATAH_Msk = 0xffffffff

	// M1FECR: RAMECC monitor 1 failing error code register
	// Position of FEC field.
	RAMECC_M1FECR_FEC_Pos = 0x0
	// Bit mask of FEC field.
	RAMECC_M1FECR_FEC_Msk = 0xffffffff

	// M2CR: RAMECC monitor 2 configuration register
	// Position of ECCELEN field.
	RAMECC_M2CR_ECCELEN_Pos = 0x5
	// Bit mask of ECCELEN field.
	RAMECC_M2CR_ECCELEN_Msk = 0x20
	// Bit ECCELEN.
	RAMECC_M2CR_ECCELEN = 0x20
	// Position of ECCDEBWIE field.
	RAMECC_M2CR_ECCDEBWIE_Pos = 0x4
	// Bit mask of ECCDEBWIE field.
	RAMECC_M2CR_ECCDEBWIE_Msk = 0x10
	// Bit ECCDEBWIE.
	RAMECC_M2CR_ECCDEBWIE = 0x10
	// Position of ECCDEIE field.
	RAMECC_M2CR_ECCDEIE_Pos = 0x3
	// Bit mask of ECCDEIE field.
	RAMECC_M2CR_ECCDEIE_Msk = 0x8
	// Bit ECCDEIE.
	RAMECC_M2CR_ECCDEIE = 0x8
	// Position of ECCSEIE field.
	RAMECC_M2CR_ECCSEIE_Pos = 0x2
	// Bit mask of ECCSEIE field.
	RAMECC_M2CR_ECCSEIE_Msk = 0x4
	// Bit ECCSEIE.
	RAMECC_M2CR_ECCSEIE = 0x4

	// M2SR: RAMECC monitor 2 status register
	// Position of DEBWDF field.
	RAMECC_M2SR_DEBWDF_Pos = 0x2
	// Bit mask of DEBWDF field.
	RAMECC_M2SR_DEBWDF_Msk = 0x4
	// Bit DEBWDF.
	RAMECC_M2SR_DEBWDF = 0x4
	// Position of DEDF field.
	RAMECC_M2SR_DEDF_Pos = 0x1
	// Bit mask of DEDF field.
	RAMECC_M2SR_DEDF_Msk = 0x2
	// Bit DEDF.
	RAMECC_M2SR_DEDF = 0x2
	// Position of SEDCF field.
	RAMECC_M2SR_SEDCF_Pos = 0x0
	// Bit mask of SEDCF field.
	RAMECC_M2SR_SEDCF_Msk = 0x1
	// Bit SEDCF.
	RAMECC_M2SR_SEDCF = 0x1

	// M2FAR: RAMECC monitor 2 failing address register
	// Position of FADD field.
	RAMECC_M2FAR_FADD_Pos = 0x0
	// Bit mask of FADD field.
	RAMECC_M2FAR_FADD_Msk = 0xffffffff

	// M2FDRL: RAMECC monitor 2 failing data low register
	// Position of FDATAL field.
	RAMECC_M2FDRL_FDATAL_Pos = 0x0
	// Bit mask of FDATAL field.
	RAMECC_M2FDRL_FDATAL_Msk = 0xffffffff

	// M2FDRH: RAMECC monitor 2 failing data high register
	// Position of FDATAH field.
	RAMECC_M2FDRH_FDATAH_Pos = 0x0
	// Bit mask of FDATAH field.
	RAMECC_M2FDRH_FDATAH_Msk = 0xffffffff

	// M2FECR: RAMECC monitor 2 failing error code register
	// Position of FEC field.
	RAMECC_M2FECR_FEC_Pos = 0x0
	// Bit mask of FEC field.
	RAMECC_M2FECR_FEC_Msk = 0xffffffff

	// M3CR: RAMECC monitor 3 configuration register
	// Position of ECCELEN field.
	RAMECC_M3CR_ECCELEN_Pos = 0x5
	// Bit mask of ECCELEN field.
	RAMECC_M3CR_ECCELEN_Msk = 0x20
	// Bit ECCELEN.
	RAMECC_M3CR_ECCELEN = 0x20
	// Position of ECCDEBWIE field.
	RAMECC_M3CR_ECCDEBWIE_Pos = 0x4
	// Bit mask of ECCDEBWIE field.
	RAMECC_M3CR_ECCDEBWIE_Msk = 0x10
	// Bit ECCDEBWIE.
	RAMECC_M3CR_ECCDEBWIE = 0x10
	// Position of ECCDEIE field.
	RAMECC_M3CR_ECCDEIE_Pos = 0x3
	// Bit mask of ECCDEIE field.
	RAMECC_M3CR_ECCDEIE_Msk = 0x8
	// Bit ECCDEIE.
	RAMECC_M3CR_ECCDEIE = 0x8
	// Position of ECCSEIE field.
	RAMECC_M3CR_ECCSEIE_Pos = 0x2
	// Bit mask of ECCSEIE field.
	RAMECC_M3CR_ECCSEIE_Msk = 0x4
	// Bit ECCSEIE.
	RAMECC_M3CR_ECCSEIE = 0x4

	// M3SR: RAMECC monitor 3 status register
	// Position of DEBWDF field.
	RAMECC_M3SR_DEBWDF_Pos = 0x2
	// Bit mask of DEBWDF field.
	RAMECC_M3SR_DEBWDF_Msk = 0x4
	// Bit DEBWDF.
	RAMECC_M3SR_DEBWDF = 0x4
	// Position of DEDF field.
	RAMECC_M3SR_DEDF_Pos = 0x1
	// Bit mask of DEDF field.
	RAMECC_M3SR_DEDF_Msk = 0x2
	// Bit DEDF.
	RAMECC_M3SR_DEDF = 0x2
	// Position of SEDCF field.
	RAMECC_M3SR_SEDCF_Pos = 0x0
	// Bit mask of SEDCF field.
	RAMECC_M3SR_SEDCF_Msk = 0x1
	// Bit SEDCF.
	RAMECC_M3SR_SEDCF = 0x1

	// M3FAR: RAMECC monitor 3 failing address register
	// Position of FADD field.
	RAMECC_M3FAR_FADD_Pos = 0x0
	// Bit mask of FADD field.
	RAMECC_M3FAR_FADD_Msk = 0xffffffff

	// M3FDRL: RAMECC monitor 3 failing data low register
	// Position of FDATAL field.
	RAMECC_M3FDRL_FDATAL_Pos = 0x0
	// Bit mask of FDATAL field.
	RAMECC_M3FDRL_FDATAL_Msk = 0xffffffff

	// M3FDRH: RAMECC monitor 3 failing data high register
	// Position of FDATAH field.
	RAMECC_M3FDRH_FDATAH_Pos = 0x0
	// Bit mask of FDATAH field.
	RAMECC_M3FDRH_FDATAH_Msk = 0xffffffff

	// M3FECR: RAMECC monitor 3 failing error code register
	// Position of FEC field.
	RAMECC_M3FECR_FEC_Pos = 0x0
	// Bit mask of FEC field.
	RAMECC_M3FECR_FEC_Msk = 0xffffffff

	// M4CR: RAMECC monitor 4 configuration register
	// Position of ECCELEN field.
	RAMECC_M4CR_ECCELEN_Pos = 0x5
	// Bit mask of ECCELEN field.
	RAMECC_M4CR_ECCELEN_Msk = 0x20
	// Bit ECCELEN.
	RAMECC_M4CR_ECCELEN = 0x20
	// Position of ECCDEBWIE field.
	RAMECC_M4CR_ECCDEBWIE_Pos = 0x4
	// Bit mask of ECCDEBWIE field.
	RAMECC_M4CR_ECCDEBWIE_Msk = 0x10
	// Bit ECCDEBWIE.
	RAMECC_M4CR_ECCDEBWIE = 0x10
	// Position of ECCDEIE field.
	RAMECC_M4CR_ECCDEIE_Pos = 0x3
	// Bit mask of ECCDEIE field.
	RAMECC_M4CR_ECCDEIE_Msk = 0x8
	// Bit ECCDEIE.
	RAMECC_M4CR_ECCDEIE = 0x8
	// Position of ECCSEIE field.
	RAMECC_M4CR_ECCSEIE_Pos = 0x2
	// Bit mask of ECCSEIE field.
	RAMECC_M4CR_ECCSEIE_Msk = 0x4
	// Bit ECCSEIE.
	RAMECC_M4CR_ECCSEIE = 0x4

	// M4SR: RAMECC monitor 4 status register
	// Position of DEBWDF field.
	RAMECC_M4SR_DEBWDF_Pos = 0x2
	// Bit mask of DEBWDF field.
	RAMECC_M4SR_DEBWDF_Msk = 0x4
	// Bit DEBWDF.
	RAMECC_M4SR_DEBWDF = 0x4
	// Position of DEDF field.
	RAMECC_M4SR_DEDF_Pos = 0x1
	// Bit mask of DEDF field.
	RAMECC_M4SR_DEDF_Msk = 0x2
	// Bit DEDF.
	RAMECC_M4SR_DEDF = 0x2
	// Position of SEDCF field.
	RAMECC_M4SR_SEDCF_Pos = 0x0
	// Bit mask of SEDCF field.
	RAMECC_M4SR_SEDCF_Msk = 0x1
	// Bit SEDCF.
	RAMECC_M4SR_SEDCF = 0x1

	// M4FAR: RAMECC monitor 4 failing address register
	// Position of FADD field.
	RAMECC_M4FAR_FADD_Pos = 0x0
	// Bit mask of FADD field.
	RAMECC_M4FAR_FADD_Msk = 0xffffffff

	// M4FDRL: RAMECC monitor 4 failing data low register
	// Position of FDATAL field.
	RAMECC_M4FDRL_FDATAL_Pos = 0x0
	// Bit mask of FDATAL field.
	RAMECC_M4FDRL_FDATAL_Msk = 0xffffffff

	// M4FDRH: RAMECC monitor 4 failing data high register
	// Position of FDATAH field.
	RAMECC_M4FDRH_FDATAH_Pos = 0x0
	// Bit mask of FDATAH field.
	RAMECC_M4FDRH_FDATAH_Msk = 0xffffffff

	// M4FECR: RAMECC monitor 4 failing error code register
	// Position of FEC field.
	RAMECC_M4FECR_FEC_Pos = 0x0
	// Bit mask of FEC field.
	RAMECC_M4FECR_FEC_Msk = 0xffffffff

	// M5CR: RAMECC monitor 5 configuration register
	// Position of ECCELEN field.
	RAMECC_M5CR_ECCELEN_Pos = 0x5
	// Bit mask of ECCELEN field.
	RAMECC_M5CR_ECCELEN_Msk = 0x20
	// Bit ECCELEN.
	RAMECC_M5CR_ECCELEN = 0x20
	// Position of ECCDEBWIE field.
	RAMECC_M5CR_ECCDEBWIE_Pos = 0x4
	// Bit mask of ECCDEBWIE field.
	RAMECC_M5CR_ECCDEBWIE_Msk = 0x10
	// Bit ECCDEBWIE.
	RAMECC_M5CR_ECCDEBWIE = 0x10
	// Position of ECCDEIE field.
	RAMECC_M5CR_ECCDEIE_Pos = 0x3
	// Bit mask of ECCDEIE field.
	RAMECC_M5CR_ECCDEIE_Msk = 0x8
	// Bit ECCDEIE.
	RAMECC_M5CR_ECCDEIE = 0x8
	// Position of ECCSEIE field.
	RAMECC_M5CR_ECCSEIE_Pos = 0x2
	// Bit mask of ECCSEIE field.
	RAMECC_M5CR_ECCSEIE_Msk = 0x4
	// Bit ECCSEIE.
	RAMECC_M5CR_ECCSEIE = 0x4

	// M5SR: RAMECC monitor 5 status register
	// Position of DEBWDF field.
	RAMECC_M5SR_DEBWDF_Pos = 0x2
	// Bit mask of DEBWDF field.
	RAMECC_M5SR_DEBWDF_Msk = 0x4
	// Bit DEBWDF.
	RAMECC_M5SR_DEBWDF = 0x4
	// Position of DEDF field.
	RAMECC_M5SR_DEDF_Pos = 0x1
	// Bit mask of DEDF field.
	RAMECC_M5SR_DEDF_Msk = 0x2
	// Bit DEDF.
	RAMECC_M5SR_DEDF = 0x2
	// Position of SEDCF field.
	RAMECC_M5SR_SEDCF_Pos = 0x0
	// Bit mask of SEDCF field.
	RAMECC_M5SR_SEDCF_Msk = 0x1
	// Bit SEDCF.
	RAMECC_M5SR_SEDCF = 0x1

	// M5FAR: RAMECC monitor 5 failing address register
	// Position of FADD field.
	RAMECC_M5FAR_FADD_Pos = 0x0
	// Bit mask of FADD field.
	RAMECC_M5FAR_FADD_Msk = 0xffffffff

	// M5FDRL: RAMECC monitor 5 failing data low register
	// Position of FDATAL field.
	RAMECC_M5FDRL_FDATAL_Pos = 0x0
	// Bit mask of FDATAL field.
	RAMECC_M5FDRL_FDATAL_Msk = 0xffffffff

	// M5FDRH: RAMECC monitor 5 failing data high register
	// Position of FDATAH field.
	RAMECC_M5FDRH_FDATAH_Pos = 0x0
	// Bit mask of FDATAH field.
	RAMECC_M5FDRH_FDATAH_Msk = 0xffffffff

	// M5FECR: RAMECC monitor 5 failing error code register
	// Position of FEC field.
	RAMECC_M5FECR_FEC_Pos = 0x0
	// Bit mask of FEC field.
	RAMECC_M5FECR_FEC_Msk = 0xffffffff
)
