LLVM 12.0.0 Release Notes — LLVM 12 documentation

# LLVM 12.0.0 Release Notes

- Introduction

- Non-comprehensive list of changes in this release

  - Changes to the LLVM IR

  - Changes to building LLVM

  - Changes to TableGen

  - Changes to the AArch64 Backend

  - Changes to the ARM Backend

  - Changes to the MIPS Target

  - Changes to the PowerPC Target

  - Changes to the X86 Target

  - Changes to the AMDGPU Target

  - Changes to the AVR Target

  - Changes to the WebAssembly Target

  - Changes to the OCaml bindings

  - Changes to the C API

  - Changes to the Go bindings

  - Changes to the DAG infrastructure

  - Changes to the Debug Info

  - Changes to the LLVM tools

  - Changes to LLDB

  - Changes to Sanitizers

- External Open Source Projects Using LLVM 12

- Additional Information

Warning

These are in-progress notes for the upcoming LLVM 12 release. Release notes for previous releases can be found on the Download Page.

## Introduction

This document contains the release notes for the LLVM Compiler Infrastructure, release 12.0.0. Here we describe the status of LLVM, including major improvements from the previous release, improvements in various subprojects of LLVM, and some of the current users of the code. All LLVM releases may be downloaded from the LLVM releases web site.

For more information about LLVM, including information about the latest release, please check out the main LLVM web site. If you have questions or comments, the LLVM Developer’s Mailing List is a good place to send them.

Note that if you are reading this file from a Git checkout or the main LLVM web page, this document applies to the next release, not the current one. To see the release notes for a specific release, please see the releases page.

## Non-comprehensive list of changes in this release

- The ConstantPropagation pass was removed. Users should use the InstSimplify pass instead.

### Changes to the LLVM IR

- …

- Added the `byref` attribute to better represent argument passing for the amdgpu_kernel calling convention.

- Added type parameter to the `sret` attribute to continue work on removing pointer element types.

- The `llvm.experimental.vector.reduce` family of intrinsics have been renamed to drop the “experimental” from the name, reflecting their now fully supported status in the IR.

### Changes to building LLVM

- The internal `llvm-build` Python script and the associated `LLVMBuild.txt` files used to describe the LLVM component structure have been removed and replaced by a pure `CMake` approach, where each component stores extra properties in the created targets. These properties are processed once all components are defined to resolve library dependencies and produce the header expected by llvm-config.

### Changes to TableGen

- The new “TableGen Programmer’s Reference” replaces the “TableGen Language Introduction” and “TableGen Language Reference” documents.

- The syntax for specifying an integer range in a range list has changed. The old syntax used a hyphen in the range (e.g., `{0-9}`). The new syntax uses the “…” range punctuation (e.g., `{0...9}`). The hyphen syntax is deprecated.

### Changes to the AArch64 Backend

During this release …

- Lots of improvements to generation of Windows unwind data; the unwind data is optimized and written in packed form where possible, reducing the size of unwind data (pdata and xdata sections) by around 60% compared with LLVM 11. The generation of prologs/epilogs is tweaked when targeting Windows, to increase the chances of being able to use the packed unwind info format.

- Support for creating Windows unwind data using `.seh_*` assembler directives.

- Produce proper assembly output for the Windows target, including `:lo12:` relocation specifiers, to allow the assembly output to actually be assembled.

- Changed the assembly comment string for MSVC targets to `//` (consistent with the MinGW and ELF targets), freeing up `;` to be used as statement separator.

### Changes to the ARM Backend

During this release …

### Changes to the MIPS Target

During this release …

### Changes to the PowerPC Target

Optimization:

- Made improvements to loop unroll-and-jam including fix to respect user provided #pragma unroll-and-jam for loops on targets other than ARM.

- Improved PartialInliner allowing it to handle code regions in a switch statements.

- Improved PGO support on AIX by building and linking with compiler-rt profile library.

- Add support for Epilogue Vectorization and enabled it by default.

CodeGen:

- POWER10 support * Implementation of PC Relative addressing in LLD including the associated

  > linker optimizations.

  - Add support for the new matrix multiplication (MMA) instructions to Clang and LLVM.

  - Implementation of Power10 builtins.

- Scheduling enhancements * Add a new algorithm to cluster more loads/stores if the DAG is not too

  > complicated.

  - Enable the PowerPC scheduling heuristic for Power10.

- Target dependent passes tuning * Enhance LoopStrengthReduce/PPCLoopInstrFormPrep pass for PowerPC,

  > especially for P10 intrinsics.

  - Enhance machine combiner pass to reduce register pressure for PowerPC.

  - Improve MachineSink to do more sinking based on register pressure and alias analysis.

- General improvements * Complete the constrained floating point operations support. * Improve the llvm-exegesis support. * Improve the stack clash protection to probe the gap between stackptr and

  > realigned stackptr.

  - Improve the IEEE long double support for Power8.

  - Enable MemorySSA for LoopSink.

  - Enhance LLVM debugging functionality via options such as -print-changed and -print-before-changed.

  - Add builtins for Power9 (i.e. darn, xvtdiv, xvtsqrt etc).

  - Add options to disable all or part of LoopIdiomRecognizePass.

  - Add support for printing the DDG in DOT form allowing for visual inspection of the Data Dependence Graph.

  - Remove the QPX support.

  - Significant number of bug fixes including all the fixes necessary to achieve a clean test run for Julia.

AIX Support:

- Compiler-rt support * Add support for building compiler-rt for AIX and 32-bit Power targets. * Made compiler-rt the default rtlib for AIX.

- General Improvements * Enable the AIX extended AltiVec ABI under option -mabi=vec-extabi. * Add partial C99 complex type support. * Implemente traceback table for functions (encodes vector information,

  > emits exception handling).

  - Implemente code generation for C++ dynamic initialization and finalization. of non-local variables for use with the -bcdtors option of the AIX linker.

  - Add new option -mignore-xcoff-visibility.

  - Enable explicit sections on AIX.

  - Enable -f[no-]data-sections on AIX and set -fdata-sections to be the default on AIX.

  - Enable -f[no-]function-sections.

  - Add support for relocation generation using the large code model.

  - Add pragma align natural and sorted out pragma pack stack effect.

### Changes to the X86 Target

During this release …

- The ‘mpx’ feature was removed from the backend. It had been removed from clang frontend in 10.0. Mention of the ‘mpx’ feature in an IR file will print a message to stderr, but IR should still compile.

- Support for `-march=alderlake`, `-march=sapphirerapids`, `-march=znver3` and `-march=x86-64-v[234]` has been added.

- The assembler now has support for {disp32} and {disp8} pseudo prefixes for controlling displacement size for memory operands and jump displacements. The assembler also supports the .d32 and .d8 mnemonic suffixes to do the same.

- A new function attribute “tune-cpu” has been added to support -mtune like gcc. This allows microarchitectural optimizations to be applied independent from the “target-cpu” attribute or TargetMachine CPU which will be used to select Instruction Set. If the attribute is not present, the tune CPU will follow the target CPU.

- Support for `HRESET` instructions has been added.

- Support for `UINTR` instructions has been added.

- Support for `AVXVNNI` instructions has been added.

### Changes to the AMDGPU Target

During this release …

- The new `byref` attribute is now the preferred method for representing aggregate kernel arguments.

### Changes to the AVR Target

During this release …

### Changes to the WebAssembly Target

During this release …

### Changes to the OCaml bindings

### Changes to the C API

### Changes to the Go bindings

### Changes to the DAG infrastructure

### Changes to the Debug Info

During this release …

- The DIModule metadata is extended with a field to indicate if it is a module declaration. This extension enables the emission of debug info for a Fortran ‘use <external module>’ statement. For more information on what the debug info entries should look like and how the debugger can use them, please see test/DebugInfo/X86/dimodule-external-fortran.ll.

### Changes to the LLVM tools

- llvm-readobj and llvm-readelf behavior has changed to report an error when executed with no input files instead of reading an input from stdin. Reading from stdin can still be achieved by specifying - as an input file.

- llvm-mca supports serialization of the timeline and summary views. The –json command line option prints a JSON representation of these views to stdout.

### Changes to LLDB

### Changes to Sanitizers

The integer sanitizer -fsanitize=integer now has a new sanitizer: -fsanitize=unsigned-shift-base. It’s not undefined behavior for an unsigned left shift to overflow (i.e. to shift bits out), but it has been the source of bugs and exploits in certain codebases in the past.

Many Sanitizers (asan, cfi, lsan, msan, tsan, ubsan) have support for musl-based Linux distributions. Some of them may be rudimentary.

## External Open Source Projects Using LLVM 12

- A project…

## Additional Information

A wide variety of additional information is available on the LLVM web page, in particular in the documentation section. The web page also contains versions of the API documentation which is up-to-date with the Git version of the source code. You can access versions of these documents specific to this release by going into the `llvm/docs/` directory in the LLVM tree.

If you have any questions or comments about LLVM, please feel free to contact us via the mailing lists.