/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_rtc.h"

uint16_t _TRACE_ALLWINNER_RTC_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_RTC_WRITE_DSTATE;
uint16_t _TRACE_SUN4V_RTC_READ_DSTATE;
uint16_t _TRACE_SUN4V_RTC_WRITE_DSTATE;
uint16_t _TRACE_XLNX_ZYNQMP_RTC_GETTIME_DSTATE;
uint16_t _TRACE_PL031_IRQ_STATE_DSTATE;
uint16_t _TRACE_PL031_READ_DSTATE;
uint16_t _TRACE_PL031_WRITE_DSTATE;
uint16_t _TRACE_PL031_ALARM_RAISED_DSTATE;
uint16_t _TRACE_PL031_SET_ALARM_DSTATE;
uint16_t _TRACE_ASPEED_RTC_READ_DSTATE;
uint16_t _TRACE_ASPEED_RTC_WRITE_DSTATE;
uint16_t _TRACE_M48TXX_NVRAM_IO_READ_DSTATE;
uint16_t _TRACE_M48TXX_NVRAM_IO_WRITE_DSTATE;
uint16_t _TRACE_M48TXX_NVRAM_MEM_READ_DSTATE;
uint16_t _TRACE_M48TXX_NVRAM_MEM_WRITE_DSTATE;
uint16_t _TRACE_GOLDFISH_RTC_READ_DSTATE;
uint16_t _TRACE_GOLDFISH_RTC_WRITE_DSTATE;
TraceEvent _TRACE_ALLWINNER_RTC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_rtc_read",
    .sstate = TRACE_ALLWINNER_RTC_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_RTC_READ_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_RTC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_rtc_write",
    .sstate = TRACE_ALLWINNER_RTC_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_RTC_WRITE_DSTATE 
};
TraceEvent _TRACE_SUN4V_RTC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sun4v_rtc_read",
    .sstate = TRACE_SUN4V_RTC_READ_ENABLED,
    .dstate = &_TRACE_SUN4V_RTC_READ_DSTATE 
};
TraceEvent _TRACE_SUN4V_RTC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sun4v_rtc_write",
    .sstate = TRACE_SUN4V_RTC_WRITE_ENABLED,
    .dstate = &_TRACE_SUN4V_RTC_WRITE_DSTATE 
};
TraceEvent _TRACE_XLNX_ZYNQMP_RTC_GETTIME_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xlnx_zynqmp_rtc_gettime",
    .sstate = TRACE_XLNX_ZYNQMP_RTC_GETTIME_ENABLED,
    .dstate = &_TRACE_XLNX_ZYNQMP_RTC_GETTIME_DSTATE 
};
TraceEvent _TRACE_PL031_IRQ_STATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pl031_irq_state",
    .sstate = TRACE_PL031_IRQ_STATE_ENABLED,
    .dstate = &_TRACE_PL031_IRQ_STATE_DSTATE 
};
TraceEvent _TRACE_PL031_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pl031_read",
    .sstate = TRACE_PL031_READ_ENABLED,
    .dstate = &_TRACE_PL031_READ_DSTATE 
};
TraceEvent _TRACE_PL031_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pl031_write",
    .sstate = TRACE_PL031_WRITE_ENABLED,
    .dstate = &_TRACE_PL031_WRITE_DSTATE 
};
TraceEvent _TRACE_PL031_ALARM_RAISED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pl031_alarm_raised",
    .sstate = TRACE_PL031_ALARM_RAISED_ENABLED,
    .dstate = &_TRACE_PL031_ALARM_RAISED_DSTATE 
};
TraceEvent _TRACE_PL031_SET_ALARM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pl031_set_alarm",
    .sstate = TRACE_PL031_SET_ALARM_ENABLED,
    .dstate = &_TRACE_PL031_SET_ALARM_DSTATE 
};
TraceEvent _TRACE_ASPEED_RTC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "aspeed_rtc_read",
    .sstate = TRACE_ASPEED_RTC_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_RTC_READ_DSTATE 
};
TraceEvent _TRACE_ASPEED_RTC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "aspeed_rtc_write",
    .sstate = TRACE_ASPEED_RTC_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_RTC_WRITE_DSTATE 
};
TraceEvent _TRACE_M48TXX_NVRAM_IO_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "m48txx_nvram_io_read",
    .sstate = TRACE_M48TXX_NVRAM_IO_READ_ENABLED,
    .dstate = &_TRACE_M48TXX_NVRAM_IO_READ_DSTATE 
};
TraceEvent _TRACE_M48TXX_NVRAM_IO_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "m48txx_nvram_io_write",
    .sstate = TRACE_M48TXX_NVRAM_IO_WRITE_ENABLED,
    .dstate = &_TRACE_M48TXX_NVRAM_IO_WRITE_DSTATE 
};
TraceEvent _TRACE_M48TXX_NVRAM_MEM_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "m48txx_nvram_mem_read",
    .sstate = TRACE_M48TXX_NVRAM_MEM_READ_ENABLED,
    .dstate = &_TRACE_M48TXX_NVRAM_MEM_READ_DSTATE 
};
TraceEvent _TRACE_M48TXX_NVRAM_MEM_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "m48txx_nvram_mem_write",
    .sstate = TRACE_M48TXX_NVRAM_MEM_WRITE_ENABLED,
    .dstate = &_TRACE_M48TXX_NVRAM_MEM_WRITE_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_RTC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_rtc_read",
    .sstate = TRACE_GOLDFISH_RTC_READ_ENABLED,
    .dstate = &_TRACE_GOLDFISH_RTC_READ_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_RTC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_rtc_write",
    .sstate = TRACE_GOLDFISH_RTC_WRITE_ENABLED,
    .dstate = &_TRACE_GOLDFISH_RTC_WRITE_DSTATE 
};
TraceEvent *hw_rtc_trace_events[] = {
    &_TRACE_ALLWINNER_RTC_READ_EVENT,
    &_TRACE_ALLWINNER_RTC_WRITE_EVENT,
    &_TRACE_SUN4V_RTC_READ_EVENT,
    &_TRACE_SUN4V_RTC_WRITE_EVENT,
    &_TRACE_XLNX_ZYNQMP_RTC_GETTIME_EVENT,
    &_TRACE_PL031_IRQ_STATE_EVENT,
    &_TRACE_PL031_READ_EVENT,
    &_TRACE_PL031_WRITE_EVENT,
    &_TRACE_PL031_ALARM_RAISED_EVENT,
    &_TRACE_PL031_SET_ALARM_EVENT,
    &_TRACE_ASPEED_RTC_READ_EVENT,
    &_TRACE_ASPEED_RTC_WRITE_EVENT,
    &_TRACE_M48TXX_NVRAM_IO_READ_EVENT,
    &_TRACE_M48TXX_NVRAM_IO_WRITE_EVENT,
    &_TRACE_M48TXX_NVRAM_MEM_READ_EVENT,
    &_TRACE_M48TXX_NVRAM_MEM_WRITE_EVENT,
    &_TRACE_GOLDFISH_RTC_READ_EVENT,
    &_TRACE_GOLDFISH_RTC_WRITE_EVENT,
  NULL,
};

static void trace_hw_rtc_register_events(void)
{
    trace_event_register_group(hw_rtc_trace_events);
}
trace_init(trace_hw_rtc_register_events)
