/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_display.h"

uint16_t _TRACE_JAZZ_LED_READ_DSTATE;
uint16_t _TRACE_JAZZ_LED_WRITE_DSTATE;
uint16_t _TRACE_XENFB_MOUSE_EVENT_DSTATE;
uint16_t _TRACE_XENFB_KEY_EVENT_DSTATE;
uint16_t _TRACE_XENFB_INPUT_CONNECTED_DSTATE;
uint16_t _TRACE_G364FB_READ_DSTATE;
uint16_t _TRACE_G364FB_WRITE_DSTATE;
uint16_t _TRACE_VMWARE_VALUE_READ_DSTATE;
uint16_t _TRACE_VMWARE_VALUE_WRITE_DSTATE;
uint16_t _TRACE_VMWARE_PALETTE_READ_DSTATE;
uint16_t _TRACE_VMWARE_PALETTE_WRITE_DSTATE;
uint16_t _TRACE_VMWARE_SCRATCH_READ_DSTATE;
uint16_t _TRACE_VMWARE_SCRATCH_WRITE_DSTATE;
uint16_t _TRACE_VMWARE_SETMODE_DSTATE;
uint16_t _TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_DSTATE;
uint16_t _TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_DSTATE;
uint16_t _TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_FEATURES_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_GET_EDID_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_UNREF_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_UPDATE_CURSOR_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_FENCE_CTRL_DSTATE;
uint16_t _TRACE_VIRTIO_GPU_FENCE_RESP_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_SET_MM_TIME_DSTATE;
uint16_t _TRACE_QXL_IO_WRITE_VGA_DSTATE;
uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_DSTATE;
uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_DSTATE;
uint16_t _TRACE_QXL_DESTROY_PRIMARY_DSTATE;
uint16_t _TRACE_QXL_ENTER_VGA_MODE_DSTATE;
uint16_t _TRACE_QXL_EXIT_VGA_MODE_DSTATE;
uint16_t _TRACE_QXL_HARD_RESET_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_ATTACH_WORKER_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_GET_INIT_INFO_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_DSTATE;
uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_DSTATE;
uint16_t _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_DSTATE;
uint16_t _TRACE_QXL_IO_LOG_DSTATE;
uint16_t _TRACE_QXL_IO_READ_UNEXPECTED_DSTATE;
uint16_t _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_DSTATE;
uint16_t _TRACE_QXL_IO_WRITE_DSTATE;
uint16_t _TRACE_QXL_MEMSLOT_ADD_GUEST_DSTATE;
uint16_t _TRACE_QXL_POST_LOAD_DSTATE;
uint16_t _TRACE_QXL_PRE_LOAD_DSTATE;
uint16_t _TRACE_QXL_PRE_SAVE_DSTATE;
uint16_t _TRACE_QXL_RESET_SURFACES_DSTATE;
uint16_t _TRACE_QXL_RING_COMMAND_CHECK_DSTATE;
uint16_t _TRACE_QXL_RING_COMMAND_GET_DSTATE;
uint16_t _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_DSTATE;
uint16_t _TRACE_QXL_RING_CURSOR_CHECK_DSTATE;
uint16_t _TRACE_QXL_RING_CURSOR_GET_DSTATE;
uint16_t _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_DSTATE;
uint16_t _TRACE_QXL_RING_RES_PUSH_DSTATE;
uint16_t _TRACE_QXL_RING_RES_PUSH_REST_DSTATE;
uint16_t _TRACE_QXL_RING_RES_PUT_DSTATE;
uint16_t _TRACE_QXL_SET_MODE_DSTATE;
uint16_t _TRACE_QXL_SOFT_RESET_DSTATE;
uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_DSTATE;
uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_DSTATE;
uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_DSTATE;
uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_DSTATE;
uint16_t _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_DSTATE;
uint16_t _TRACE_QXL_SPICE_MONITORS_CONFIG_DSTATE;
uint16_t _TRACE_QXL_SPICE_LOADVM_COMMANDS_DSTATE;
uint16_t _TRACE_QXL_SPICE_OOM_DSTATE;
uint16_t _TRACE_QXL_SPICE_RESET_CURSOR_DSTATE;
uint16_t _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_DSTATE;
uint16_t _TRACE_QXL_SPICE_RESET_MEMSLOTS_DSTATE;
uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_DSTATE;
uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_REST_DSTATE;
uint16_t _TRACE_QXL_SURFACES_DIRTY_DSTATE;
uint16_t _TRACE_QXL_SEND_EVENTS_DSTATE;
uint16_t _TRACE_QXL_SEND_EVENTS_VM_STOPPED_DSTATE;
uint16_t _TRACE_QXL_SET_GUEST_BUG_DSTATE;
uint16_t _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_DSTATE;
uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_DSTATE;
uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_DSTATE;
uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_DSTATE;
uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_DSTATE;
uint16_t _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_DSTATE;
uint16_t _TRACE_QXL_RENDER_BLIT_DSTATE;
uint16_t _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_DSTATE;
uint16_t _TRACE_QXL_RENDER_UPDATE_AREA_DONE_DSTATE;
uint16_t _TRACE_VGA_STD_READ_IO_DSTATE;
uint16_t _TRACE_VGA_STD_WRITE_IO_DSTATE;
uint16_t _TRACE_VGA_VBE_READ_DSTATE;
uint16_t _TRACE_VGA_VBE_WRITE_DSTATE;
uint16_t _TRACE_VGA_CIRRUS_READ_IO_DSTATE;
uint16_t _TRACE_VGA_CIRRUS_WRITE_IO_DSTATE;
uint16_t _TRACE_VGA_CIRRUS_WRITE_BLT_DSTATE;
uint16_t _TRACE_VGA_CIRRUS_WRITE_GR_DSTATE;
uint16_t _TRACE_VGA_CIRRUS_BITBLT_START_DSTATE;
uint16_t _TRACE_SII9022_READ_REG_DSTATE;
uint16_t _TRACE_SII9022_WRITE_REG_DSTATE;
uint16_t _TRACE_SII9022_SWITCH_MODE_DSTATE;
uint16_t _TRACE_ATI_MM_READ_DSTATE;
uint16_t _TRACE_ATI_MM_WRITE_DSTATE;
uint16_t _TRACE_ARTIST_REG_READ_DSTATE;
uint16_t _TRACE_ARTIST_REG_WRITE_DSTATE;
uint16_t _TRACE_ARTIST_VRAM_READ_DSTATE;
uint16_t _TRACE_ARTIST_VRAM_WRITE_DSTATE;
uint16_t _TRACE_ARTIST_FILL_WINDOW_DSTATE;
uint16_t _TRACE_ARTIST_BLOCK_MOVE_DSTATE;
uint16_t _TRACE_ARTIST_DRAW_LINE_DSTATE;
uint16_t _TRACE_CG3_READ_DSTATE;
uint16_t _TRACE_CG3_WRITE_DSTATE;
uint16_t _TRACE_DPCD_READ_DSTATE;
uint16_t _TRACE_DPCD_WRITE_DSTATE;
uint16_t _TRACE_SM501_SYSTEM_CONFIG_READ_DSTATE;
uint16_t _TRACE_SM501_SYSTEM_CONFIG_WRITE_DSTATE;
uint16_t _TRACE_SM501_I2C_READ_DSTATE;
uint16_t _TRACE_SM501_I2C_WRITE_DSTATE;
uint16_t _TRACE_SM501_PALETTE_READ_DSTATE;
uint16_t _TRACE_SM501_PALETTE_WRITE_DSTATE;
uint16_t _TRACE_SM501_DISP_CTRL_READ_DSTATE;
uint16_t _TRACE_SM501_DISP_CTRL_WRITE_DSTATE;
uint16_t _TRACE_SM501_2D_ENGINE_READ_DSTATE;
uint16_t _TRACE_SM501_2D_ENGINE_WRITE_DSTATE;
uint16_t _TRACE_MACFB_CTRL_READ_DSTATE;
uint16_t _TRACE_MACFB_CTRL_WRITE_DSTATE;
uint16_t _TRACE_MACFB_SENSE_READ_DSTATE;
uint16_t _TRACE_MACFB_SENSE_WRITE_DSTATE;
uint16_t _TRACE_MACFB_UPDATE_MODE_DSTATE;
TraceEvent _TRACE_JAZZ_LED_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "jazz_led_read",
    .sstate = TRACE_JAZZ_LED_READ_ENABLED,
    .dstate = &_TRACE_JAZZ_LED_READ_DSTATE 
};
TraceEvent _TRACE_JAZZ_LED_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "jazz_led_write",
    .sstate = TRACE_JAZZ_LED_WRITE_ENABLED,
    .dstate = &_TRACE_JAZZ_LED_WRITE_DSTATE 
};
TraceEvent _TRACE_XENFB_MOUSE_EVENT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xenfb_mouse_event",
    .sstate = TRACE_XENFB_MOUSE_EVENT_ENABLED,
    .dstate = &_TRACE_XENFB_MOUSE_EVENT_DSTATE 
};
TraceEvent _TRACE_XENFB_KEY_EVENT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xenfb_key_event",
    .sstate = TRACE_XENFB_KEY_EVENT_ENABLED,
    .dstate = &_TRACE_XENFB_KEY_EVENT_DSTATE 
};
TraceEvent _TRACE_XENFB_INPUT_CONNECTED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xenfb_input_connected",
    .sstate = TRACE_XENFB_INPUT_CONNECTED_ENABLED,
    .dstate = &_TRACE_XENFB_INPUT_CONNECTED_DSTATE 
};
TraceEvent _TRACE_G364FB_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "g364fb_read",
    .sstate = TRACE_G364FB_READ_ENABLED,
    .dstate = &_TRACE_G364FB_READ_DSTATE 
};
TraceEvent _TRACE_G364FB_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "g364fb_write",
    .sstate = TRACE_G364FB_WRITE_ENABLED,
    .dstate = &_TRACE_G364FB_WRITE_DSTATE 
};
TraceEvent _TRACE_VMWARE_VALUE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_value_read",
    .sstate = TRACE_VMWARE_VALUE_READ_ENABLED,
    .dstate = &_TRACE_VMWARE_VALUE_READ_DSTATE 
};
TraceEvent _TRACE_VMWARE_VALUE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_value_write",
    .sstate = TRACE_VMWARE_VALUE_WRITE_ENABLED,
    .dstate = &_TRACE_VMWARE_VALUE_WRITE_DSTATE 
};
TraceEvent _TRACE_VMWARE_PALETTE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_palette_read",
    .sstate = TRACE_VMWARE_PALETTE_READ_ENABLED,
    .dstate = &_TRACE_VMWARE_PALETTE_READ_DSTATE 
};
TraceEvent _TRACE_VMWARE_PALETTE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_palette_write",
    .sstate = TRACE_VMWARE_PALETTE_WRITE_ENABLED,
    .dstate = &_TRACE_VMWARE_PALETTE_WRITE_DSTATE 
};
TraceEvent _TRACE_VMWARE_SCRATCH_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_scratch_read",
    .sstate = TRACE_VMWARE_SCRATCH_READ_ENABLED,
    .dstate = &_TRACE_VMWARE_SCRATCH_READ_DSTATE 
};
TraceEvent _TRACE_VMWARE_SCRATCH_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_scratch_write",
    .sstate = TRACE_VMWARE_SCRATCH_WRITE_ENABLED,
    .dstate = &_TRACE_VMWARE_SCRATCH_WRITE_DSTATE 
};
TraceEvent _TRACE_VMWARE_SETMODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_setmode",
    .sstate = TRACE_VMWARE_SETMODE_ENABLED,
    .dstate = &_TRACE_VMWARE_SETMODE_DSTATE 
};
TraceEvent _TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_verify_rect_less_than_zero",
    .sstate = TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_ENABLED,
    .dstate = &_TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_DSTATE 
};
TraceEvent _TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_verify_rect_greater_than_bound",
    .sstate = TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_ENABLED,
    .dstate = &_TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_DSTATE 
};
TraceEvent _TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vmware_verify_rect_surface_bound_exceeded",
    .sstate = TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_ENABLED,
    .dstate = &_TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_FEATURES_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_features",
    .sstate = TRACE_VIRTIO_GPU_FEATURES_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_FEATURES_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_get_display_info",
    .sstate = TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_EDID_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_get_edid",
    .sstate = TRACE_VIRTIO_GPU_CMD_GET_EDID_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_GET_EDID_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_set_scanout",
    .sstate = TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_set_scanout_blob",
    .sstate = TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_create_2d",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_create_3d",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_create_blob",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_UNREF_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_unref",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_UNREF_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_UNREF_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_back_attach",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_back_detach",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_xfer_toh_2d",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_xfer_toh_3d",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_xfer_fromh_3d",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_res_flush",
    .sstate = TRACE_VIRTIO_GPU_CMD_RES_FLUSH_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_RES_FLUSH_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_ctx_create",
    .sstate = TRACE_VIRTIO_GPU_CMD_CTX_CREATE_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_CREATE_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_ctx_destroy",
    .sstate = TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_ctx_res_attach",
    .sstate = TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_ctx_res_detach",
    .sstate = TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_cmd_ctx_submit",
    .sstate = TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_UPDATE_CURSOR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_update_cursor",
    .sstate = TRACE_VIRTIO_GPU_UPDATE_CURSOR_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_UPDATE_CURSOR_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_FENCE_CTRL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_fence_ctrl",
    .sstate = TRACE_VIRTIO_GPU_FENCE_CTRL_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_FENCE_CTRL_DSTATE 
};
TraceEvent _TRACE_VIRTIO_GPU_FENCE_RESP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_gpu_fence_resp",
    .sstate = TRACE_VIRTIO_GPU_FENCE_RESP_ENABLED,
    .dstate = &_TRACE_VIRTIO_GPU_FENCE_RESP_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_SET_MM_TIME_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_set_mm_time",
    .sstate = TRACE_QXL_INTERFACE_SET_MM_TIME_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_SET_MM_TIME_DSTATE 
};
TraceEvent _TRACE_QXL_IO_WRITE_VGA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_io_write_vga",
    .sstate = TRACE_QXL_IO_WRITE_VGA_ENABLED,
    .dstate = &_TRACE_QXL_IO_WRITE_VGA_DSTATE 
};
TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_create_guest_primary",
    .sstate = TRACE_QXL_CREATE_GUEST_PRIMARY_ENABLED,
    .dstate = &_TRACE_QXL_CREATE_GUEST_PRIMARY_DSTATE 
};
TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_create_guest_primary_rest",
    .sstate = TRACE_QXL_CREATE_GUEST_PRIMARY_REST_ENABLED,
    .dstate = &_TRACE_QXL_CREATE_GUEST_PRIMARY_REST_DSTATE 
};
TraceEvent _TRACE_QXL_DESTROY_PRIMARY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_destroy_primary",
    .sstate = TRACE_QXL_DESTROY_PRIMARY_ENABLED,
    .dstate = &_TRACE_QXL_DESTROY_PRIMARY_DSTATE 
};
TraceEvent _TRACE_QXL_ENTER_VGA_MODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_enter_vga_mode",
    .sstate = TRACE_QXL_ENTER_VGA_MODE_ENABLED,
    .dstate = &_TRACE_QXL_ENTER_VGA_MODE_DSTATE 
};
TraceEvent _TRACE_QXL_EXIT_VGA_MODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_exit_vga_mode",
    .sstate = TRACE_QXL_EXIT_VGA_MODE_ENABLED,
    .dstate = &_TRACE_QXL_EXIT_VGA_MODE_DSTATE 
};
TraceEvent _TRACE_QXL_HARD_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_hard_reset",
    .sstate = TRACE_QXL_HARD_RESET_ENABLED,
    .dstate = &_TRACE_QXL_HARD_RESET_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_async_complete_io",
    .sstate = TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_ATTACH_WORKER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_attach_worker",
    .sstate = TRACE_QXL_INTERFACE_ATTACH_WORKER_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_ATTACH_WORKER_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_GET_INIT_INFO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_get_init_info",
    .sstate = TRACE_QXL_INTERFACE_GET_INIT_INFO_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_GET_INIT_INFO_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_set_compression_level",
    .sstate = TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_update_area_complete",
    .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_update_area_complete_rest",
    .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_update_area_complete_overflow",
    .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_DSTATE 
};
TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interface_update_area_complete_schedule_bh",
    .sstate = TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_ENABLED,
    .dstate = &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_DSTATE 
};
TraceEvent _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_io_destroy_primary_ignored",
    .sstate = TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_ENABLED,
    .dstate = &_TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_DSTATE 
};
TraceEvent _TRACE_QXL_IO_LOG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_io_log",
    .sstate = TRACE_QXL_IO_LOG_ENABLED,
    .dstate = &_TRACE_QXL_IO_LOG_DSTATE 
};
TraceEvent _TRACE_QXL_IO_READ_UNEXPECTED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_io_read_unexpected",
    .sstate = TRACE_QXL_IO_READ_UNEXPECTED_ENABLED,
    .dstate = &_TRACE_QXL_IO_READ_UNEXPECTED_DSTATE 
};
TraceEvent _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_io_unexpected_vga_mode",
    .sstate = TRACE_QXL_IO_UNEXPECTED_VGA_MODE_ENABLED,
    .dstate = &_TRACE_QXL_IO_UNEXPECTED_VGA_MODE_DSTATE 
};
TraceEvent _TRACE_QXL_IO_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_io_write",
    .sstate = TRACE_QXL_IO_WRITE_ENABLED,
    .dstate = &_TRACE_QXL_IO_WRITE_DSTATE 
};
TraceEvent _TRACE_QXL_MEMSLOT_ADD_GUEST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_memslot_add_guest",
    .sstate = TRACE_QXL_MEMSLOT_ADD_GUEST_ENABLED,
    .dstate = &_TRACE_QXL_MEMSLOT_ADD_GUEST_DSTATE 
};
TraceEvent _TRACE_QXL_POST_LOAD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_post_load",
    .sstate = TRACE_QXL_POST_LOAD_ENABLED,
    .dstate = &_TRACE_QXL_POST_LOAD_DSTATE 
};
TraceEvent _TRACE_QXL_PRE_LOAD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_pre_load",
    .sstate = TRACE_QXL_PRE_LOAD_ENABLED,
    .dstate = &_TRACE_QXL_PRE_LOAD_DSTATE 
};
TraceEvent _TRACE_QXL_PRE_SAVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_pre_save",
    .sstate = TRACE_QXL_PRE_SAVE_ENABLED,
    .dstate = &_TRACE_QXL_PRE_SAVE_DSTATE 
};
TraceEvent _TRACE_QXL_RESET_SURFACES_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_reset_surfaces",
    .sstate = TRACE_QXL_RESET_SURFACES_ENABLED,
    .dstate = &_TRACE_QXL_RESET_SURFACES_DSTATE 
};
TraceEvent _TRACE_QXL_RING_COMMAND_CHECK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_command_check",
    .sstate = TRACE_QXL_RING_COMMAND_CHECK_ENABLED,
    .dstate = &_TRACE_QXL_RING_COMMAND_CHECK_DSTATE 
};
TraceEvent _TRACE_QXL_RING_COMMAND_GET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_command_get",
    .sstate = TRACE_QXL_RING_COMMAND_GET_ENABLED,
    .dstate = &_TRACE_QXL_RING_COMMAND_GET_DSTATE 
};
TraceEvent _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_command_req_notification",
    .sstate = TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_ENABLED,
    .dstate = &_TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_DSTATE 
};
TraceEvent _TRACE_QXL_RING_CURSOR_CHECK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_cursor_check",
    .sstate = TRACE_QXL_RING_CURSOR_CHECK_ENABLED,
    .dstate = &_TRACE_QXL_RING_CURSOR_CHECK_DSTATE 
};
TraceEvent _TRACE_QXL_RING_CURSOR_GET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_cursor_get",
    .sstate = TRACE_QXL_RING_CURSOR_GET_ENABLED,
    .dstate = &_TRACE_QXL_RING_CURSOR_GET_DSTATE 
};
TraceEvent _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_cursor_req_notification",
    .sstate = TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_ENABLED,
    .dstate = &_TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_DSTATE 
};
TraceEvent _TRACE_QXL_RING_RES_PUSH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_res_push",
    .sstate = TRACE_QXL_RING_RES_PUSH_ENABLED,
    .dstate = &_TRACE_QXL_RING_RES_PUSH_DSTATE 
};
TraceEvent _TRACE_QXL_RING_RES_PUSH_REST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_res_push_rest",
    .sstate = TRACE_QXL_RING_RES_PUSH_REST_ENABLED,
    .dstate = &_TRACE_QXL_RING_RES_PUSH_REST_DSTATE 
};
TraceEvent _TRACE_QXL_RING_RES_PUT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_ring_res_put",
    .sstate = TRACE_QXL_RING_RES_PUT_ENABLED,
    .dstate = &_TRACE_QXL_RING_RES_PUT_DSTATE 
};
TraceEvent _TRACE_QXL_SET_MODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_set_mode",
    .sstate = TRACE_QXL_SET_MODE_ENABLED,
    .dstate = &_TRACE_QXL_SET_MODE_DSTATE 
};
TraceEvent _TRACE_QXL_SOFT_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_soft_reset",
    .sstate = TRACE_QXL_SOFT_RESET_ENABLED,
    .dstate = &_TRACE_QXL_SOFT_RESET_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_destroy_surfaces_complete",
    .sstate = TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_destroy_surfaces",
    .sstate = TRACE_QXL_SPICE_DESTROY_SURFACES_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACES_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_destroy_surface_wait_complete",
    .sstate = TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_destroy_surface_wait",
    .sstate = TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_flush_surfaces_async",
    .sstate = TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_MONITORS_CONFIG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_monitors_config",
    .sstate = TRACE_QXL_SPICE_MONITORS_CONFIG_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_MONITORS_CONFIG_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_LOADVM_COMMANDS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_loadvm_commands",
    .sstate = TRACE_QXL_SPICE_LOADVM_COMMANDS_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_LOADVM_COMMANDS_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_OOM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_oom",
    .sstate = TRACE_QXL_SPICE_OOM_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_OOM_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_RESET_CURSOR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_reset_cursor",
    .sstate = TRACE_QXL_SPICE_RESET_CURSOR_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_RESET_CURSOR_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_reset_image_cache",
    .sstate = TRACE_QXL_SPICE_RESET_IMAGE_CACHE_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_RESET_IMAGE_CACHE_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_RESET_MEMSLOTS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_reset_memslots",
    .sstate = TRACE_QXL_SPICE_RESET_MEMSLOTS_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_RESET_MEMSLOTS_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_update_area",
    .sstate = TRACE_QXL_SPICE_UPDATE_AREA_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_UPDATE_AREA_DSTATE 
};
TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_REST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_spice_update_area_rest",
    .sstate = TRACE_QXL_SPICE_UPDATE_AREA_REST_ENABLED,
    .dstate = &_TRACE_QXL_SPICE_UPDATE_AREA_REST_DSTATE 
};
TraceEvent _TRACE_QXL_SURFACES_DIRTY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_surfaces_dirty",
    .sstate = TRACE_QXL_SURFACES_DIRTY_ENABLED,
    .dstate = &_TRACE_QXL_SURFACES_DIRTY_DSTATE 
};
TraceEvent _TRACE_QXL_SEND_EVENTS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_send_events",
    .sstate = TRACE_QXL_SEND_EVENTS_ENABLED,
    .dstate = &_TRACE_QXL_SEND_EVENTS_DSTATE 
};
TraceEvent _TRACE_QXL_SEND_EVENTS_VM_STOPPED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_send_events_vm_stopped",
    .sstate = TRACE_QXL_SEND_EVENTS_VM_STOPPED_ENABLED,
    .dstate = &_TRACE_QXL_SEND_EVENTS_VM_STOPPED_DSTATE 
};
TraceEvent _TRACE_QXL_SET_GUEST_BUG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_set_guest_bug",
    .sstate = TRACE_QXL_SET_GUEST_BUG_ENABLED,
    .dstate = &_TRACE_QXL_SET_GUEST_BUG_DSTATE 
};
TraceEvent _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_interrupt_client_monitors_config",
    .sstate = TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_ENABLED,
    .dstate = &_TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_DSTATE 
};
TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_client_monitors_config_unsupported_by_guest",
    .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_ENABLED,
    .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_DSTATE 
};
TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_client_monitors_config_unsupported_by_device",
    .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_ENABLED,
    .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_DSTATE 
};
TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_client_monitors_config_capped",
    .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_ENABLED,
    .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_DSTATE 
};
TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_client_monitors_config_crc",
    .sstate = TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_ENABLED,
    .dstate = &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_DSTATE 
};
TraceEvent _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_set_client_capabilities_unsupported_by_revision",
    .sstate = TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_ENABLED,
    .dstate = &_TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_DSTATE 
};
TraceEvent _TRACE_QXL_RENDER_BLIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_render_blit",
    .sstate = TRACE_QXL_RENDER_BLIT_ENABLED,
    .dstate = &_TRACE_QXL_RENDER_BLIT_DSTATE 
};
TraceEvent _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_render_guest_primary_resized",
    .sstate = TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_ENABLED,
    .dstate = &_TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_DSTATE 
};
TraceEvent _TRACE_QXL_RENDER_UPDATE_AREA_DONE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qxl_render_update_area_done",
    .sstate = TRACE_QXL_RENDER_UPDATE_AREA_DONE_ENABLED,
    .dstate = &_TRACE_QXL_RENDER_UPDATE_AREA_DONE_DSTATE 
};
TraceEvent _TRACE_VGA_STD_READ_IO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_std_read_io",
    .sstate = TRACE_VGA_STD_READ_IO_ENABLED,
    .dstate = &_TRACE_VGA_STD_READ_IO_DSTATE 
};
TraceEvent _TRACE_VGA_STD_WRITE_IO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_std_write_io",
    .sstate = TRACE_VGA_STD_WRITE_IO_ENABLED,
    .dstate = &_TRACE_VGA_STD_WRITE_IO_DSTATE 
};
TraceEvent _TRACE_VGA_VBE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_vbe_read",
    .sstate = TRACE_VGA_VBE_READ_ENABLED,
    .dstate = &_TRACE_VGA_VBE_READ_DSTATE 
};
TraceEvent _TRACE_VGA_VBE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_vbe_write",
    .sstate = TRACE_VGA_VBE_WRITE_ENABLED,
    .dstate = &_TRACE_VGA_VBE_WRITE_DSTATE 
};
TraceEvent _TRACE_VGA_CIRRUS_READ_IO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_cirrus_read_io",
    .sstate = TRACE_VGA_CIRRUS_READ_IO_ENABLED,
    .dstate = &_TRACE_VGA_CIRRUS_READ_IO_DSTATE 
};
TraceEvent _TRACE_VGA_CIRRUS_WRITE_IO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_cirrus_write_io",
    .sstate = TRACE_VGA_CIRRUS_WRITE_IO_ENABLED,
    .dstate = &_TRACE_VGA_CIRRUS_WRITE_IO_DSTATE 
};
TraceEvent _TRACE_VGA_CIRRUS_WRITE_BLT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_cirrus_write_blt",
    .sstate = TRACE_VGA_CIRRUS_WRITE_BLT_ENABLED,
    .dstate = &_TRACE_VGA_CIRRUS_WRITE_BLT_DSTATE 
};
TraceEvent _TRACE_VGA_CIRRUS_WRITE_GR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_cirrus_write_gr",
    .sstate = TRACE_VGA_CIRRUS_WRITE_GR_ENABLED,
    .dstate = &_TRACE_VGA_CIRRUS_WRITE_GR_DSTATE 
};
TraceEvent _TRACE_VGA_CIRRUS_BITBLT_START_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "vga_cirrus_bitblt_start",
    .sstate = TRACE_VGA_CIRRUS_BITBLT_START_ENABLED,
    .dstate = &_TRACE_VGA_CIRRUS_BITBLT_START_DSTATE 
};
TraceEvent _TRACE_SII9022_READ_REG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sii9022_read_reg",
    .sstate = TRACE_SII9022_READ_REG_ENABLED,
    .dstate = &_TRACE_SII9022_READ_REG_DSTATE 
};
TraceEvent _TRACE_SII9022_WRITE_REG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sii9022_write_reg",
    .sstate = TRACE_SII9022_WRITE_REG_ENABLED,
    .dstate = &_TRACE_SII9022_WRITE_REG_DSTATE 
};
TraceEvent _TRACE_SII9022_SWITCH_MODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sii9022_switch_mode",
    .sstate = TRACE_SII9022_SWITCH_MODE_ENABLED,
    .dstate = &_TRACE_SII9022_SWITCH_MODE_DSTATE 
};
TraceEvent _TRACE_ATI_MM_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ati_mm_read",
    .sstate = TRACE_ATI_MM_READ_ENABLED,
    .dstate = &_TRACE_ATI_MM_READ_DSTATE 
};
TraceEvent _TRACE_ATI_MM_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ati_mm_write",
    .sstate = TRACE_ATI_MM_WRITE_ENABLED,
    .dstate = &_TRACE_ATI_MM_WRITE_DSTATE 
};
TraceEvent _TRACE_ARTIST_REG_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "artist_reg_read",
    .sstate = TRACE_ARTIST_REG_READ_ENABLED,
    .dstate = &_TRACE_ARTIST_REG_READ_DSTATE 
};
TraceEvent _TRACE_ARTIST_REG_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "artist_reg_write",
    .sstate = TRACE_ARTIST_REG_WRITE_ENABLED,
    .dstate = &_TRACE_ARTIST_REG_WRITE_DSTATE 
};
TraceEvent _TRACE_ARTIST_VRAM_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "artist_vram_read",
    .sstate = TRACE_ARTIST_VRAM_READ_ENABLED,
    .dstate = &_TRACE_ARTIST_VRAM_READ_DSTATE 
};
TraceEvent _TRACE_ARTIST_VRAM_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "artist_vram_write",
    .sstate = TRACE_ARTIST_VRAM_WRITE_ENABLED,
    .dstate = &_TRACE_ARTIST_VRAM_WRITE_DSTATE 
};
TraceEvent _TRACE_ARTIST_FILL_WINDOW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "artist_fill_window",
    .sstate = TRACE_ARTIST_FILL_WINDOW_ENABLED,
    .dstate = &_TRACE_ARTIST_FILL_WINDOW_DSTATE 
};
TraceEvent _TRACE_ARTIST_BLOCK_MOVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "artist_block_move",
    .sstate = TRACE_ARTIST_BLOCK_MOVE_ENABLED,
    .dstate = &_TRACE_ARTIST_BLOCK_MOVE_DSTATE 
};
TraceEvent _TRACE_ARTIST_DRAW_LINE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "artist_draw_line",
    .sstate = TRACE_ARTIST_DRAW_LINE_ENABLED,
    .dstate = &_TRACE_ARTIST_DRAW_LINE_DSTATE 
};
TraceEvent _TRACE_CG3_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "cg3_read",
    .sstate = TRACE_CG3_READ_ENABLED,
    .dstate = &_TRACE_CG3_READ_DSTATE 
};
TraceEvent _TRACE_CG3_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "cg3_write",
    .sstate = TRACE_CG3_WRITE_ENABLED,
    .dstate = &_TRACE_CG3_WRITE_DSTATE 
};
TraceEvent _TRACE_DPCD_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dpcd_read",
    .sstate = TRACE_DPCD_READ_ENABLED,
    .dstate = &_TRACE_DPCD_READ_DSTATE 
};
TraceEvent _TRACE_DPCD_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dpcd_write",
    .sstate = TRACE_DPCD_WRITE_ENABLED,
    .dstate = &_TRACE_DPCD_WRITE_DSTATE 
};
TraceEvent _TRACE_SM501_SYSTEM_CONFIG_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_system_config_read",
    .sstate = TRACE_SM501_SYSTEM_CONFIG_READ_ENABLED,
    .dstate = &_TRACE_SM501_SYSTEM_CONFIG_READ_DSTATE 
};
TraceEvent _TRACE_SM501_SYSTEM_CONFIG_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_system_config_write",
    .sstate = TRACE_SM501_SYSTEM_CONFIG_WRITE_ENABLED,
    .dstate = &_TRACE_SM501_SYSTEM_CONFIG_WRITE_DSTATE 
};
TraceEvent _TRACE_SM501_I2C_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_i2c_read",
    .sstate = TRACE_SM501_I2C_READ_ENABLED,
    .dstate = &_TRACE_SM501_I2C_READ_DSTATE 
};
TraceEvent _TRACE_SM501_I2C_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_i2c_write",
    .sstate = TRACE_SM501_I2C_WRITE_ENABLED,
    .dstate = &_TRACE_SM501_I2C_WRITE_DSTATE 
};
TraceEvent _TRACE_SM501_PALETTE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_palette_read",
    .sstate = TRACE_SM501_PALETTE_READ_ENABLED,
    .dstate = &_TRACE_SM501_PALETTE_READ_DSTATE 
};
TraceEvent _TRACE_SM501_PALETTE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_palette_write",
    .sstate = TRACE_SM501_PALETTE_WRITE_ENABLED,
    .dstate = &_TRACE_SM501_PALETTE_WRITE_DSTATE 
};
TraceEvent _TRACE_SM501_DISP_CTRL_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_disp_ctrl_read",
    .sstate = TRACE_SM501_DISP_CTRL_READ_ENABLED,
    .dstate = &_TRACE_SM501_DISP_CTRL_READ_DSTATE 
};
TraceEvent _TRACE_SM501_DISP_CTRL_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_disp_ctrl_write",
    .sstate = TRACE_SM501_DISP_CTRL_WRITE_ENABLED,
    .dstate = &_TRACE_SM501_DISP_CTRL_WRITE_DSTATE 
};
TraceEvent _TRACE_SM501_2D_ENGINE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_2d_engine_read",
    .sstate = TRACE_SM501_2D_ENGINE_READ_ENABLED,
    .dstate = &_TRACE_SM501_2D_ENGINE_READ_DSTATE 
};
TraceEvent _TRACE_SM501_2D_ENGINE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sm501_2d_engine_write",
    .sstate = TRACE_SM501_2D_ENGINE_WRITE_ENABLED,
    .dstate = &_TRACE_SM501_2D_ENGINE_WRITE_DSTATE 
};
TraceEvent _TRACE_MACFB_CTRL_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "macfb_ctrl_read",
    .sstate = TRACE_MACFB_CTRL_READ_ENABLED,
    .dstate = &_TRACE_MACFB_CTRL_READ_DSTATE 
};
TraceEvent _TRACE_MACFB_CTRL_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "macfb_ctrl_write",
    .sstate = TRACE_MACFB_CTRL_WRITE_ENABLED,
    .dstate = &_TRACE_MACFB_CTRL_WRITE_DSTATE 
};
TraceEvent _TRACE_MACFB_SENSE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "macfb_sense_read",
    .sstate = TRACE_MACFB_SENSE_READ_ENABLED,
    .dstate = &_TRACE_MACFB_SENSE_READ_DSTATE 
};
TraceEvent _TRACE_MACFB_SENSE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "macfb_sense_write",
    .sstate = TRACE_MACFB_SENSE_WRITE_ENABLED,
    .dstate = &_TRACE_MACFB_SENSE_WRITE_DSTATE 
};
TraceEvent _TRACE_MACFB_UPDATE_MODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "macfb_update_mode",
    .sstate = TRACE_MACFB_UPDATE_MODE_ENABLED,
    .dstate = &_TRACE_MACFB_UPDATE_MODE_DSTATE 
};
TraceEvent *hw_display_trace_events[] = {
    &_TRACE_JAZZ_LED_READ_EVENT,
    &_TRACE_JAZZ_LED_WRITE_EVENT,
    &_TRACE_XENFB_MOUSE_EVENT_EVENT,
    &_TRACE_XENFB_KEY_EVENT_EVENT,
    &_TRACE_XENFB_INPUT_CONNECTED_EVENT,
    &_TRACE_G364FB_READ_EVENT,
    &_TRACE_G364FB_WRITE_EVENT,
    &_TRACE_VMWARE_VALUE_READ_EVENT,
    &_TRACE_VMWARE_VALUE_WRITE_EVENT,
    &_TRACE_VMWARE_PALETTE_READ_EVENT,
    &_TRACE_VMWARE_PALETTE_WRITE_EVENT,
    &_TRACE_VMWARE_SCRATCH_READ_EVENT,
    &_TRACE_VMWARE_SCRATCH_WRITE_EVENT,
    &_TRACE_VMWARE_SETMODE_EVENT,
    &_TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_EVENT,
    &_TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_EVENT,
    &_TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_EVENT,
    &_TRACE_VIRTIO_GPU_FEATURES_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_GET_EDID_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_UNREF_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_RES_FLUSH_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_CTX_CREATE_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_EVENT,
    &_TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_EVENT,
    &_TRACE_VIRTIO_GPU_UPDATE_CURSOR_EVENT,
    &_TRACE_VIRTIO_GPU_FENCE_CTRL_EVENT,
    &_TRACE_VIRTIO_GPU_FENCE_RESP_EVENT,
    &_TRACE_QXL_INTERFACE_SET_MM_TIME_EVENT,
    &_TRACE_QXL_IO_WRITE_VGA_EVENT,
    &_TRACE_QXL_CREATE_GUEST_PRIMARY_EVENT,
    &_TRACE_QXL_CREATE_GUEST_PRIMARY_REST_EVENT,
    &_TRACE_QXL_DESTROY_PRIMARY_EVENT,
    &_TRACE_QXL_ENTER_VGA_MODE_EVENT,
    &_TRACE_QXL_EXIT_VGA_MODE_EVENT,
    &_TRACE_QXL_HARD_RESET_EVENT,
    &_TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_EVENT,
    &_TRACE_QXL_INTERFACE_ATTACH_WORKER_EVENT,
    &_TRACE_QXL_INTERFACE_GET_INIT_INFO_EVENT,
    &_TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_EVENT,
    &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_EVENT,
    &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_EVENT,
    &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_EVENT,
    &_TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_EVENT,
    &_TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_EVENT,
    &_TRACE_QXL_IO_LOG_EVENT,
    &_TRACE_QXL_IO_READ_UNEXPECTED_EVENT,
    &_TRACE_QXL_IO_UNEXPECTED_VGA_MODE_EVENT,
    &_TRACE_QXL_IO_WRITE_EVENT,
    &_TRACE_QXL_MEMSLOT_ADD_GUEST_EVENT,
    &_TRACE_QXL_POST_LOAD_EVENT,
    &_TRACE_QXL_PRE_LOAD_EVENT,
    &_TRACE_QXL_PRE_SAVE_EVENT,
    &_TRACE_QXL_RESET_SURFACES_EVENT,
    &_TRACE_QXL_RING_COMMAND_CHECK_EVENT,
    &_TRACE_QXL_RING_COMMAND_GET_EVENT,
    &_TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_EVENT,
    &_TRACE_QXL_RING_CURSOR_CHECK_EVENT,
    &_TRACE_QXL_RING_CURSOR_GET_EVENT,
    &_TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_EVENT,
    &_TRACE_QXL_RING_RES_PUSH_EVENT,
    &_TRACE_QXL_RING_RES_PUSH_REST_EVENT,
    &_TRACE_QXL_RING_RES_PUT_EVENT,
    &_TRACE_QXL_SET_MODE_EVENT,
    &_TRACE_QXL_SOFT_RESET_EVENT,
    &_TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_EVENT,
    &_TRACE_QXL_SPICE_DESTROY_SURFACES_EVENT,
    &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_EVENT,
    &_TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_EVENT,
    &_TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_EVENT,
    &_TRACE_QXL_SPICE_MONITORS_CONFIG_EVENT,
    &_TRACE_QXL_SPICE_LOADVM_COMMANDS_EVENT,
    &_TRACE_QXL_SPICE_OOM_EVENT,
    &_TRACE_QXL_SPICE_RESET_CURSOR_EVENT,
    &_TRACE_QXL_SPICE_RESET_IMAGE_CACHE_EVENT,
    &_TRACE_QXL_SPICE_RESET_MEMSLOTS_EVENT,
    &_TRACE_QXL_SPICE_UPDATE_AREA_EVENT,
    &_TRACE_QXL_SPICE_UPDATE_AREA_REST_EVENT,
    &_TRACE_QXL_SURFACES_DIRTY_EVENT,
    &_TRACE_QXL_SEND_EVENTS_EVENT,
    &_TRACE_QXL_SEND_EVENTS_VM_STOPPED_EVENT,
    &_TRACE_QXL_SET_GUEST_BUG_EVENT,
    &_TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_EVENT,
    &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_EVENT,
    &_TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_EVENT,
    &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_EVENT,
    &_TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_EVENT,
    &_TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_EVENT,
    &_TRACE_QXL_RENDER_BLIT_EVENT,
    &_TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_EVENT,
    &_TRACE_QXL_RENDER_UPDATE_AREA_DONE_EVENT,
    &_TRACE_VGA_STD_READ_IO_EVENT,
    &_TRACE_VGA_STD_WRITE_IO_EVENT,
    &_TRACE_VGA_VBE_READ_EVENT,
    &_TRACE_VGA_VBE_WRITE_EVENT,
    &_TRACE_VGA_CIRRUS_READ_IO_EVENT,
    &_TRACE_VGA_CIRRUS_WRITE_IO_EVENT,
    &_TRACE_VGA_CIRRUS_WRITE_BLT_EVENT,
    &_TRACE_VGA_CIRRUS_WRITE_GR_EVENT,
    &_TRACE_VGA_CIRRUS_BITBLT_START_EVENT,
    &_TRACE_SII9022_READ_REG_EVENT,
    &_TRACE_SII9022_WRITE_REG_EVENT,
    &_TRACE_SII9022_SWITCH_MODE_EVENT,
    &_TRACE_ATI_MM_READ_EVENT,
    &_TRACE_ATI_MM_WRITE_EVENT,
    &_TRACE_ARTIST_REG_READ_EVENT,
    &_TRACE_ARTIST_REG_WRITE_EVENT,
    &_TRACE_ARTIST_VRAM_READ_EVENT,
    &_TRACE_ARTIST_VRAM_WRITE_EVENT,
    &_TRACE_ARTIST_FILL_WINDOW_EVENT,
    &_TRACE_ARTIST_BLOCK_MOVE_EVENT,
    &_TRACE_ARTIST_DRAW_LINE_EVENT,
    &_TRACE_CG3_READ_EVENT,
    &_TRACE_CG3_WRITE_EVENT,
    &_TRACE_DPCD_READ_EVENT,
    &_TRACE_DPCD_WRITE_EVENT,
    &_TRACE_SM501_SYSTEM_CONFIG_READ_EVENT,
    &_TRACE_SM501_SYSTEM_CONFIG_WRITE_EVENT,
    &_TRACE_SM501_I2C_READ_EVENT,
    &_TRACE_SM501_I2C_WRITE_EVENT,
    &_TRACE_SM501_PALETTE_READ_EVENT,
    &_TRACE_SM501_PALETTE_WRITE_EVENT,
    &_TRACE_SM501_DISP_CTRL_READ_EVENT,
    &_TRACE_SM501_DISP_CTRL_WRITE_EVENT,
    &_TRACE_SM501_2D_ENGINE_READ_EVENT,
    &_TRACE_SM501_2D_ENGINE_WRITE_EVENT,
    &_TRACE_MACFB_CTRL_READ_EVENT,
    &_TRACE_MACFB_CTRL_WRITE_EVENT,
    &_TRACE_MACFB_SENSE_READ_EVENT,
    &_TRACE_MACFB_SENSE_WRITE_EVENT,
    &_TRACE_MACFB_UPDATE_MODE_EVENT,
  NULL,
};

static void trace_hw_display_register_events(void)
{
    trace_event_register_group(hw_display_trace_events);
}
trace_init(trace_hw_display_register_events)
