/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_net.h"

uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_DSTATE;
uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_DSTATE;
uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_DSTATE;
uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_DSTATE;
uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_RESET_DSTATE;
uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_DSTATE;
uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_WRITE_DSTATE;
uint16_t _TRACE_MDIO_PHY_READ_DSTATE;
uint16_t _TRACE_MDIO_PHY_WRITE_DSTATE;
uint16_t _TRACE_MDIO_BITBANG_DSTATE;
uint16_t _TRACE_LANCE_MEM_READW_DSTATE;
uint16_t _TRACE_LANCE_MEM_WRITEW_DSTATE;
uint16_t _TRACE_MIPSNET_SEND_DSTATE;
uint16_t _TRACE_MIPSNET_RECEIVE_DSTATE;
uint16_t _TRACE_MIPSNET_READ_DSTATE;
uint16_t _TRACE_MIPSNET_WRITE_DSTATE;
uint16_t _TRACE_MIPSNET_IRQ_DSTATE;
uint16_t _TRACE_NE2000_READ_DSTATE;
uint16_t _TRACE_NE2000_WRITE_DSTATE;
uint16_t _TRACE_NE2000_IOPORT_READ_DSTATE;
uint16_t _TRACE_NE2000_IOPORT_WRITE_DSTATE;
uint16_t _TRACE_OPEN_ETH_MII_WRITE_DSTATE;
uint16_t _TRACE_OPEN_ETH_MII_READ_DSTATE;
uint16_t _TRACE_OPEN_ETH_UPDATE_IRQ_DSTATE;
uint16_t _TRACE_OPEN_ETH_RECEIVE_DSTATE;
uint16_t _TRACE_OPEN_ETH_RECEIVE_MCAST_DSTATE;
uint16_t _TRACE_OPEN_ETH_RECEIVE_REJECT_DSTATE;
uint16_t _TRACE_OPEN_ETH_RECEIVE_DESC_DSTATE;
uint16_t _TRACE_OPEN_ETH_START_XMIT_DSTATE;
uint16_t _TRACE_OPEN_ETH_REG_READ_DSTATE;
uint16_t _TRACE_OPEN_ETH_REG_WRITE_DSTATE;
uint16_t _TRACE_OPEN_ETH_DESC_READ_DSTATE;
uint16_t _TRACE_OPEN_ETH_DESC_WRITE_DSTATE;
uint16_t _TRACE_PCNET_S_RESET_DSTATE;
uint16_t _TRACE_PCNET_USER_INT_DSTATE;
uint16_t _TRACE_PCNET_ISR_CHANGE_DSTATE;
uint16_t _TRACE_PCNET_INIT_DSTATE;
uint16_t _TRACE_PCNET_RLEN_TLEN_DSTATE;
uint16_t _TRACE_PCNET_SS32_RDRA_TDRA_DSTATE;
uint16_t _TRACE_PCNET_APROM_WRITEB_DSTATE;
uint16_t _TRACE_PCNET_APROM_READB_DSTATE;
uint16_t _TRACE_PCNET_IOPORT_READ_DSTATE;
uint16_t _TRACE_PCNET_IOPORT_WRITE_DSTATE;
uint16_t _TRACE_NET_RX_PKT_PARSED_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_DSTATE;
uint16_t _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP4_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP4_TCP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP4_UDP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP6_TCP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP6_UDP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP6_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP6_EX_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_HASH_DSTATE;
uint16_t _TRACE_NET_RX_PKT_RSS_ADD_CHUNK_DSTATE;
uint16_t _TRACE_E1000_RECEIVER_OVERRUN_DSTATE;
uint16_t _TRACE_E1000X_RX_CAN_RECV_DISABLED_DSTATE;
uint16_t _TRACE_E1000X_VLAN_IS_VLAN_PKT_DSTATE;
uint16_t _TRACE_E1000X_RX_FLT_UCAST_MATCH_DSTATE;
uint16_t _TRACE_E1000X_RX_FLT_UCAST_MISMATCH_DSTATE;
uint16_t _TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_DSTATE;
uint16_t _TRACE_E1000X_RX_LINK_DOWN_DSTATE;
uint16_t _TRACE_E1000X_RX_DISABLED_DSTATE;
uint16_t _TRACE_E1000X_RX_OVERSIZED_DSTATE;
uint16_t _TRACE_E1000X_MAC_INDICATE_DSTATE;
uint16_t _TRACE_E1000X_LINK_NEGOTIATION_START_DSTATE;
uint16_t _TRACE_E1000X_LINK_NEGOTIATION_DONE_DSTATE;
uint16_t _TRACE_E1000E_CORE_WRITE_DSTATE;
uint16_t _TRACE_E1000E_CORE_READ_DSTATE;
uint16_t _TRACE_E1000E_CORE_MDIC_READ_DSTATE;
uint16_t _TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_DSTATE;
uint16_t _TRACE_E1000E_CORE_MDIC_WRITE_DSTATE;
uint16_t _TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_DSTATE;
uint16_t _TRACE_E1000E_CORE_CTRL_WRITE_DSTATE;
uint16_t _TRACE_E1000E_CORE_CTRL_SW_RESET_DSTATE;
uint16_t _TRACE_E1000E_CORE_CTRL_PHY_RESET_DSTATE;
uint16_t _TRACE_E1000E_LINK_AUTONEG_FLOWCTL_DSTATE;
uint16_t _TRACE_E1000E_LINK_SET_PARAMS_DSTATE;
uint16_t _TRACE_E1000E_LINK_READ_PARAMS_DSTATE;
uint16_t _TRACE_E1000E_LINK_SET_EXT_PARAMS_DSTATE;
uint16_t _TRACE_E1000E_LINK_STATUS_DSTATE;
uint16_t _TRACE_E1000E_LINK_STATUS_CHANGED_DSTATE;
uint16_t _TRACE_E1000E_WRN_REGS_WRITE_RO_DSTATE;
uint16_t _TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_DSTATE;
uint16_t _TRACE_E1000E_WRN_REGS_READ_UNKNOWN_DSTATE;
uint16_t _TRACE_E1000E_WRN_REGS_READ_TRIVIAL_DSTATE;
uint16_t _TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_DSTATE;
uint16_t _TRACE_E1000E_WRN_NO_TS_SUPPORT_DSTATE;
uint16_t _TRACE_E1000E_WRN_NO_SNAP_SUPPORT_DSTATE;
uint16_t _TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_DSTATE;
uint16_t _TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_DSTATE;
uint16_t _TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_DSTATE;
uint16_t _TRACE_E1000E_TX_DISABLED_DSTATE;
uint16_t _TRACE_E1000E_TX_DESCR_DSTATE;
uint16_t _TRACE_E1000E_RING_FREE_SPACE_DSTATE;
uint16_t _TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_DSTATE;
uint16_t _TRACE_E1000E_RX_CAN_RECV_DSTATE;
uint16_t _TRACE_E1000E_RX_HAS_BUFFERS_DSTATE;
uint16_t _TRACE_E1000E_RX_NULL_DESCRIPTOR_DSTATE;
uint16_t _TRACE_E1000E_RX_FLT_VLAN_MISMATCH_DSTATE;
uint16_t _TRACE_E1000E_RX_FLT_VLAN_MATCH_DSTATE;
uint16_t _TRACE_E1000E_RX_DESC_PS_READ_DSTATE;
uint16_t _TRACE_E1000E_RX_DESC_PS_WRITE_DSTATE;
uint16_t _TRACE_E1000E_RX_DESC_BUFF_SIZES_DSTATE;
uint16_t _TRACE_E1000E_RX_DESC_LEN_DSTATE;
uint16_t _TRACE_E1000E_RX_DESC_BUFF_WRITE_DSTATE;
uint16_t _TRACE_E1000E_RX_DESCR_DSTATE;
uint16_t _TRACE_E1000E_RX_SET_RCTL_DSTATE;
uint16_t _TRACE_E1000E_RX_RECEIVE_IOV_DSTATE;
uint16_t _TRACE_E1000E_RX_FLT_DROPPED_DSTATE;
uint16_t _TRACE_E1000E_RX_WRITTEN_TO_GUEST_DSTATE;
uint16_t _TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_DSTATE;
uint16_t _TRACE_E1000E_RX_INTERRUPT_SET_DSTATE;
uint16_t _TRACE_E1000E_RX_INTERRUPT_DELAYED_DSTATE;
uint16_t _TRACE_E1000E_RX_SET_CSO_DSTATE;
uint16_t _TRACE_E1000E_RX_SET_RDT_DSTATE;
uint16_t _TRACE_E1000E_RX_SET_RFCTL_DSTATE;
uint16_t _TRACE_E1000E_RX_START_RECV_DSTATE;
uint16_t _TRACE_E1000E_RX_RSS_STARTED_DSTATE;
uint16_t _TRACE_E1000E_RX_RSS_DISABLED_DSTATE;
uint16_t _TRACE_E1000E_RX_RSS_TYPE_DSTATE;
uint16_t _TRACE_E1000E_RX_RSS_IP4_DSTATE;
uint16_t _TRACE_E1000E_RX_RSS_IP6_RFCTL_DSTATE;
uint16_t _TRACE_E1000E_RX_RSS_IP6_DSTATE;
uint16_t _TRACE_E1000E_RX_RSS_DISPATCHED_TO_QUEUE_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_PROTOCOLS_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_VLAN_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_RSS_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_IP_ID_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_ACK_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_PKT_TYPE_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_NO_VIRTHDR_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_STATUS_FLAGS_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_DSTATE;
uint16_t _TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_DSTATE;
uint16_t _TRACE_E1000E_VLAN_VET_DSTATE;
uint16_t _TRACE_E1000E_IRQ_MSI_NOTIFY_DSTATE;
uint16_t _TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_INTERRUPTS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_DSTATE;
uint16_t _TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_DSTATE;
uint16_t _TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_VEC_DSTATE;
uint16_t _TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_DSTATE;
uint16_t _TRACE_E1000E_IRQ_LEGACY_NOTIFY_DSTATE;
uint16_t _TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_DSTATE;
uint16_t _TRACE_E1000E_IRQ_POSTPONED_BY_XITR_DSTATE;
uint16_t _TRACE_E1000E_IRQ_CLEAR_IMS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_SET_IMS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ADD_MSI_OTHER_DSTATE;
uint16_t _TRACE_E1000E_IRQ_PENDING_INTERRUPTS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_SET_CAUSE_ENTRY_DSTATE;
uint16_t _TRACE_E1000E_IRQ_SET_CAUSE_EXIT_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_WRITE_DSTATE;
uint16_t _TRACE_E1000E_IRQ_WRITE_ICS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_PROCESS_IAME_DSTATE;
uint16_t _TRACE_E1000E_IRQ_READ_ICS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_READ_IMS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_READ_ENTRY_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_READ_EXIT_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_IAME_DSTATE;
uint16_t _TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_DSTATE;
uint16_t _TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_DSTATE;
uint16_t _TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_REARM_TIMER_DSTATE;
uint16_t _TRACE_E1000E_IRQ_THROTTLING_TIMER_DSTATE;
uint16_t _TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_DSTATE;
uint16_t _TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_DSTATE;
uint16_t _TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_DSTATE;
uint16_t _TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_DSTATE;
uint16_t _TRACE_E1000E_IRQ_EITR_SET_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ITR_SET_DSTATE;
uint16_t _TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_DSTATE;
uint16_t _TRACE_E1000E_IRQ_ADDING_DELAYED_CAUSES_DSTATE;
uint16_t _TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_DSTATE;
uint16_t _TRACE_E1000E_WRN_MSIX_VEC_WRONG_DSTATE;
uint16_t _TRACE_E1000E_WRN_MSIX_INVALID_DSTATE;
uint16_t _TRACE_E1000E_MAC_SET_SW_DSTATE;
uint16_t _TRACE_E1000E_VM_STATE_RUNNING_DSTATE;
uint16_t _TRACE_E1000E_VM_STATE_STOPPED_DSTATE;
uint16_t _TRACE_E1000E_CB_PCI_REALIZE_DSTATE;
uint16_t _TRACE_E1000E_CB_PCI_UNINIT_DSTATE;
uint16_t _TRACE_E1000E_CB_QDEV_RESET_DSTATE;
uint16_t _TRACE_E1000E_CB_PRE_SAVE_DSTATE;
uint16_t _TRACE_E1000E_CB_POST_LOAD_DSTATE;
uint16_t _TRACE_E1000E_IO_WRITE_ADDR_DSTATE;
uint16_t _TRACE_E1000E_IO_WRITE_DATA_DSTATE;
uint16_t _TRACE_E1000E_IO_READ_ADDR_DSTATE;
uint16_t _TRACE_E1000E_IO_READ_DATA_DSTATE;
uint16_t _TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_DSTATE;
uint16_t _TRACE_E1000E_WRN_IO_READ_UNKNOWN_DSTATE;
uint16_t _TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_DSTATE;
uint16_t _TRACE_E1000E_WRN_IO_ADDR_FLASH_DSTATE;
uint16_t _TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_DSTATE;
uint16_t _TRACE_E1000E_MSI_INIT_FAIL_DSTATE;
uint16_t _TRACE_E1000E_MSIX_INIT_FAIL_DSTATE;
uint16_t _TRACE_E1000E_MSIX_USE_VECTOR_FAIL_DSTATE;
uint16_t _TRACE_E1000E_MAC_SET_PERMANENT_DSTATE;
uint16_t _TRACE_E1000E_CFG_SUPPORT_VIRTIO_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_RECEIVE_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_RECEIVE_WROTE_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_DSTATE;
uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_DSTATE;
uint16_t _TRACE_SUNGEM_TX_CHECKSUM_DSTATE;
uint16_t _TRACE_SUNGEM_TX_CHECKSUM_OOB_DSTATE;
uint16_t _TRACE_SUNGEM_TX_UNFINISHED_DSTATE;
uint16_t _TRACE_SUNGEM_TX_OVERFLOW_DSTATE;
uint16_t _TRACE_SUNGEM_TX_FINISHED_DSTATE;
uint16_t _TRACE_SUNGEM_TX_KICK_DSTATE;
uint16_t _TRACE_SUNGEM_TX_DISABLED_DSTATE;
uint16_t _TRACE_SUNGEM_TX_PROCESS_DSTATE;
uint16_t _TRACE_SUNGEM_TX_DESC_DSTATE;
uint16_t _TRACE_SUNGEM_TX_RESET_DSTATE;
uint16_t _TRACE_SUNGEM_RX_MAC_DISABLED_DSTATE;
uint16_t _TRACE_SUNGEM_RX_TXDMA_DISABLED_DSTATE;
uint16_t _TRACE_SUNGEM_RX_CHECK_DSTATE;
uint16_t _TRACE_SUNGEM_RX_MAC_CHECK_DSTATE;
uint16_t _TRACE_SUNGEM_RX_MAC_MULTICAST_DSTATE;
uint16_t _TRACE_SUNGEM_RX_MAC_COMPARE_DSTATE;
uint16_t _TRACE_SUNGEM_RX_PACKET_DSTATE;
uint16_t _TRACE_SUNGEM_RX_DISABLED_DSTATE;
uint16_t _TRACE_SUNGEM_RX_BAD_FRAME_SIZE_DSTATE;
uint16_t _TRACE_SUNGEM_RX_UNMATCHED_DSTATE;
uint16_t _TRACE_SUNGEM_RX_PROCESS_DSTATE;
uint16_t _TRACE_SUNGEM_RX_RINGFULL_DSTATE;
uint16_t _TRACE_SUNGEM_RX_DESC_DSTATE;
uint16_t _TRACE_SUNGEM_RX_RESET_DSTATE;
uint16_t _TRACE_SUNGEM_RX_KICK_DSTATE;
uint16_t _TRACE_SUNGEM_RESET_DSTATE;
uint16_t _TRACE_SUNGEM_MII_WRITE_DSTATE;
uint16_t _TRACE_SUNGEM_MII_READ_DSTATE;
uint16_t _TRACE_SUNGEM_MII_INVALID_SOF_DSTATE;
uint16_t _TRACE_SUNGEM_MII_INVALID_OP_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_GREG_WRITE_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_GREG_READ_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_TXDMA_WRITE_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_TXDMA_READ_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_RXDMA_WRITE_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_RXDMA_READ_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_MAC_WRITE_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_MAC_READ_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_MIF_WRITE_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_MIF_READ_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_PCS_WRITE_DSTATE;
uint16_t _TRACE_SUNGEM_MMIO_PCS_READ_DSTATE;
uint16_t _TRACE_SUNHME_SEB_WRITE_DSTATE;
uint16_t _TRACE_SUNHME_SEB_READ_DSTATE;
uint16_t _TRACE_SUNHME_ETX_WRITE_DSTATE;
uint16_t _TRACE_SUNHME_ETX_READ_DSTATE;
uint16_t _TRACE_SUNHME_ERX_WRITE_DSTATE;
uint16_t _TRACE_SUNHME_ERX_READ_DSTATE;
uint16_t _TRACE_SUNHME_MAC_WRITE_DSTATE;
uint16_t _TRACE_SUNHME_MAC_READ_DSTATE;
uint16_t _TRACE_SUNHME_MII_WRITE_DSTATE;
uint16_t _TRACE_SUNHME_MII_READ_DSTATE;
uint16_t _TRACE_SUNHME_MIF_WRITE_DSTATE;
uint16_t _TRACE_SUNHME_MIF_READ_DSTATE;
uint16_t _TRACE_SUNHME_TX_DESC_DSTATE;
uint16_t _TRACE_SUNHME_TX_XSUM_ADD_DSTATE;
uint16_t _TRACE_SUNHME_TX_XSUM_STUFF_DSTATE;
uint16_t _TRACE_SUNHME_TX_DONE_DSTATE;
uint16_t _TRACE_SUNHME_RX_INCOMING_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_DESTMAC_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_BCAST_MATCH_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_HASH_MATCH_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_REJECT_DSTATE;
uint16_t _TRACE_SUNHME_RX_FILTER_ACCEPT_DSTATE;
uint16_t _TRACE_SUNHME_RX_DESC_DSTATE;
uint16_t _TRACE_SUNHME_RX_XSUM_CALC_DSTATE;
uint16_t _TRACE_SUNHME_RX_NORXD_DSTATE;
uint16_t _TRACE_SUNHME_UPDATE_IRQ_DSTATE;
uint16_t _TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_DSTATE;
uint16_t _TRACE_VIRTIO_NET_ANNOUNCE_TIMER_DSTATE;
uint16_t _TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_DSTATE;
uint16_t _TRACE_VIRTIO_NET_POST_LOAD_DEVICE_DSTATE;
uint16_t _TRACE_VIRTIO_NET_RSS_DISABLE_DSTATE;
uint16_t _TRACE_VIRTIO_NET_RSS_ERROR_DSTATE;
uint16_t _TRACE_VIRTIO_NET_RSS_ENABLE_DSTATE;
uint16_t _TRACE_TULIP_REG_WRITE_DSTATE;
uint16_t _TRACE_TULIP_REG_READ_DSTATE;
uint16_t _TRACE_TULIP_RECEIVE_DSTATE;
uint16_t _TRACE_TULIP_DESCRIPTOR_DSTATE;
uint16_t _TRACE_TULIP_RX_STATE_DSTATE;
uint16_t _TRACE_TULIP_TX_STATE_DSTATE;
uint16_t _TRACE_TULIP_IRQ_DSTATE;
uint16_t _TRACE_TULIP_MII_WRITE_DSTATE;
uint16_t _TRACE_TULIP_MII_READ_DSTATE;
uint16_t _TRACE_TULIP_RESET_DSTATE;
uint16_t _TRACE_TULIP_SETUP_FRAME_DSTATE;
uint16_t _TRACE_TULIP_SETUP_FILTER_DSTATE;
uint16_t _TRACE_LASI_82596_MEM_READW_DSTATE;
uint16_t _TRACE_LASI_82596_MEM_WRITEW_DSTATE;
uint16_t _TRACE_I82596_S_RESET_DSTATE;
uint16_t _TRACE_I82596_TRANSMIT_DSTATE;
uint16_t _TRACE_I82596_RECEIVE_ANALYSIS_DSTATE;
uint16_t _TRACE_I82596_RECEIVE_PACKET_DSTATE;
uint16_t _TRACE_I82596_NEW_MAC_DSTATE;
uint16_t _TRACE_I82596_SET_MULTICAST_DSTATE;
uint16_t _TRACE_I82596_CHANNEL_ATTENTION_DSTATE;
uint16_t _TRACE_IMX_PHY_READ_DSTATE;
uint16_t _TRACE_IMX_PHY_READ_NUM_DSTATE;
uint16_t _TRACE_IMX_PHY_WRITE_DSTATE;
uint16_t _TRACE_IMX_PHY_WRITE_NUM_DSTATE;
uint16_t _TRACE_IMX_PHY_UPDATE_LINK_DSTATE;
uint16_t _TRACE_IMX_PHY_RESET_DSTATE;
uint16_t _TRACE_IMX_FEC_READ_BD_DSTATE;
uint16_t _TRACE_IMX_ENET_READ_BD_DSTATE;
uint16_t _TRACE_IMX_ETH_TX_BD_BUSY_DSTATE;
uint16_t _TRACE_IMX_ETH_RX_BD_FULL_DSTATE;
uint16_t _TRACE_IMX_ETH_READ_DSTATE;
uint16_t _TRACE_IMX_ETH_WRITE_DSTATE;
uint16_t _TRACE_IMX_FEC_RECEIVE_DSTATE;
uint16_t _TRACE_IMX_FEC_RECEIVE_LEN_DSTATE;
uint16_t _TRACE_IMX_FEC_RECEIVE_LAST_DSTATE;
uint16_t _TRACE_IMX_ENET_RECEIVE_DSTATE;
uint16_t _TRACE_IMX_ENET_RECEIVE_LEN_DSTATE;
uint16_t _TRACE_IMX_ENET_RECEIVE_LAST_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_RESET_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_SET_MISTA_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_SENT_PACKET_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_TX_DONE_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_CAN_RECEIVE_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_PACKET_DROPPED_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_RECEIVING_PACKET_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_RECEIVED_PACKET_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_RX_DONE_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_REG_READ_DSTATE;
uint16_t _TRACE_NPCM7XX_EMC_REG_WRITE_DSTATE;
uint16_t _TRACE_DP8393X_RAISE_IRQ_DSTATE;
uint16_t _TRACE_DP8393X_LOWER_IRQ_DSTATE;
uint16_t _TRACE_DP8393X_LOAD_CAM_DSTATE;
uint16_t _TRACE_DP8393X_LOAD_CAM_DONE_DSTATE;
uint16_t _TRACE_DP8393X_READ_RRA_REGS_DSTATE;
uint16_t _TRACE_DP8393X_TRANSMIT_PACKET_DSTATE;
uint16_t _TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_DSTATE;
uint16_t _TRACE_DP8393X_READ_DSTATE;
uint16_t _TRACE_DP8393X_WRITE_DSTATE;
uint16_t _TRACE_DP8393X_WRITE_INVALID_DSTATE;
uint16_t _TRACE_DP8393X_WRITE_INVALID_DCR_DSTATE;
uint16_t _TRACE_DP8393X_RECEIVE_OVERSIZE_DSTATE;
uint16_t _TRACE_DP8393X_RECEIVE_NOT_NETCARD_DSTATE;
uint16_t _TRACE_DP8393X_RECEIVE_PACKET_DSTATE;
uint16_t _TRACE_DP8393X_RECEIVE_WRITE_STATUS_DSTATE;
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_mii_write_reg",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_mii_read_reg",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_receive",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_transmit",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_reset",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_RESET_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_RESET_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_set_link",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_read",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_READ_DSTATE 
};
TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "allwinner_sun8i_emac_write",
    .sstate = TRACE_ALLWINNER_SUN8I_EMAC_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SUN8I_EMAC_WRITE_DSTATE 
};
TraceEvent _TRACE_MDIO_PHY_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mdio_phy_read",
    .sstate = TRACE_MDIO_PHY_READ_ENABLED,
    .dstate = &_TRACE_MDIO_PHY_READ_DSTATE 
};
TraceEvent _TRACE_MDIO_PHY_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mdio_phy_write",
    .sstate = TRACE_MDIO_PHY_WRITE_ENABLED,
    .dstate = &_TRACE_MDIO_PHY_WRITE_DSTATE 
};
TraceEvent _TRACE_MDIO_BITBANG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mdio_bitbang",
    .sstate = TRACE_MDIO_BITBANG_ENABLED,
    .dstate = &_TRACE_MDIO_BITBANG_DSTATE 
};
TraceEvent _TRACE_LANCE_MEM_READW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "lance_mem_readw",
    .sstate = TRACE_LANCE_MEM_READW_ENABLED,
    .dstate = &_TRACE_LANCE_MEM_READW_DSTATE 
};
TraceEvent _TRACE_LANCE_MEM_WRITEW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "lance_mem_writew",
    .sstate = TRACE_LANCE_MEM_WRITEW_ENABLED,
    .dstate = &_TRACE_LANCE_MEM_WRITEW_DSTATE 
};
TraceEvent _TRACE_MIPSNET_SEND_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mipsnet_send",
    .sstate = TRACE_MIPSNET_SEND_ENABLED,
    .dstate = &_TRACE_MIPSNET_SEND_DSTATE 
};
TraceEvent _TRACE_MIPSNET_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mipsnet_receive",
    .sstate = TRACE_MIPSNET_RECEIVE_ENABLED,
    .dstate = &_TRACE_MIPSNET_RECEIVE_DSTATE 
};
TraceEvent _TRACE_MIPSNET_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mipsnet_read",
    .sstate = TRACE_MIPSNET_READ_ENABLED,
    .dstate = &_TRACE_MIPSNET_READ_DSTATE 
};
TraceEvent _TRACE_MIPSNET_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mipsnet_write",
    .sstate = TRACE_MIPSNET_WRITE_ENABLED,
    .dstate = &_TRACE_MIPSNET_WRITE_DSTATE 
};
TraceEvent _TRACE_MIPSNET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "mipsnet_irq",
    .sstate = TRACE_MIPSNET_IRQ_ENABLED,
    .dstate = &_TRACE_MIPSNET_IRQ_DSTATE 
};
TraceEvent _TRACE_NE2000_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ne2000_read",
    .sstate = TRACE_NE2000_READ_ENABLED,
    .dstate = &_TRACE_NE2000_READ_DSTATE 
};
TraceEvent _TRACE_NE2000_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ne2000_write",
    .sstate = TRACE_NE2000_WRITE_ENABLED,
    .dstate = &_TRACE_NE2000_WRITE_DSTATE 
};
TraceEvent _TRACE_NE2000_IOPORT_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ne2000_ioport_read",
    .sstate = TRACE_NE2000_IOPORT_READ_ENABLED,
    .dstate = &_TRACE_NE2000_IOPORT_READ_DSTATE 
};
TraceEvent _TRACE_NE2000_IOPORT_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ne2000_ioport_write",
    .sstate = TRACE_NE2000_IOPORT_WRITE_ENABLED,
    .dstate = &_TRACE_NE2000_IOPORT_WRITE_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_MII_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_mii_write",
    .sstate = TRACE_OPEN_ETH_MII_WRITE_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_MII_WRITE_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_MII_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_mii_read",
    .sstate = TRACE_OPEN_ETH_MII_READ_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_MII_READ_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_UPDATE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_update_irq",
    .sstate = TRACE_OPEN_ETH_UPDATE_IRQ_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_UPDATE_IRQ_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_receive",
    .sstate = TRACE_OPEN_ETH_RECEIVE_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_RECEIVE_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_RECEIVE_MCAST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_receive_mcast",
    .sstate = TRACE_OPEN_ETH_RECEIVE_MCAST_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_RECEIVE_MCAST_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_RECEIVE_REJECT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_receive_reject",
    .sstate = TRACE_OPEN_ETH_RECEIVE_REJECT_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_RECEIVE_REJECT_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_RECEIVE_DESC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_receive_desc",
    .sstate = TRACE_OPEN_ETH_RECEIVE_DESC_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_RECEIVE_DESC_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_START_XMIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_start_xmit",
    .sstate = TRACE_OPEN_ETH_START_XMIT_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_START_XMIT_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_REG_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_reg_read",
    .sstate = TRACE_OPEN_ETH_REG_READ_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_REG_READ_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_REG_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_reg_write",
    .sstate = TRACE_OPEN_ETH_REG_WRITE_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_REG_WRITE_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_DESC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_desc_read",
    .sstate = TRACE_OPEN_ETH_DESC_READ_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_DESC_READ_DSTATE 
};
TraceEvent _TRACE_OPEN_ETH_DESC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "open_eth_desc_write",
    .sstate = TRACE_OPEN_ETH_DESC_WRITE_ENABLED,
    .dstate = &_TRACE_OPEN_ETH_DESC_WRITE_DSTATE 
};
TraceEvent _TRACE_PCNET_S_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_s_reset",
    .sstate = TRACE_PCNET_S_RESET_ENABLED,
    .dstate = &_TRACE_PCNET_S_RESET_DSTATE 
};
TraceEvent _TRACE_PCNET_USER_INT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_user_int",
    .sstate = TRACE_PCNET_USER_INT_ENABLED,
    .dstate = &_TRACE_PCNET_USER_INT_DSTATE 
};
TraceEvent _TRACE_PCNET_ISR_CHANGE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_isr_change",
    .sstate = TRACE_PCNET_ISR_CHANGE_ENABLED,
    .dstate = &_TRACE_PCNET_ISR_CHANGE_DSTATE 
};
TraceEvent _TRACE_PCNET_INIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_init",
    .sstate = TRACE_PCNET_INIT_ENABLED,
    .dstate = &_TRACE_PCNET_INIT_DSTATE 
};
TraceEvent _TRACE_PCNET_RLEN_TLEN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_rlen_tlen",
    .sstate = TRACE_PCNET_RLEN_TLEN_ENABLED,
    .dstate = &_TRACE_PCNET_RLEN_TLEN_DSTATE 
};
TraceEvent _TRACE_PCNET_SS32_RDRA_TDRA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_ss32_rdra_tdra",
    .sstate = TRACE_PCNET_SS32_RDRA_TDRA_ENABLED,
    .dstate = &_TRACE_PCNET_SS32_RDRA_TDRA_DSTATE 
};
TraceEvent _TRACE_PCNET_APROM_WRITEB_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_aprom_writeb",
    .sstate = TRACE_PCNET_APROM_WRITEB_ENABLED,
    .dstate = &_TRACE_PCNET_APROM_WRITEB_DSTATE 
};
TraceEvent _TRACE_PCNET_APROM_READB_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_aprom_readb",
    .sstate = TRACE_PCNET_APROM_READB_ENABLED,
    .dstate = &_TRACE_PCNET_APROM_READB_DSTATE 
};
TraceEvent _TRACE_PCNET_IOPORT_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_ioport_read",
    .sstate = TRACE_PCNET_IOPORT_READ_ENABLED,
    .dstate = &_TRACE_PCNET_IOPORT_READ_DSTATE 
};
TraceEvent _TRACE_PCNET_IOPORT_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pcnet_ioport_write",
    .sstate = TRACE_PCNET_IOPORT_WRITE_ENABLED,
    .dstate = &_TRACE_PCNET_IOPORT_WRITE_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_PARSED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_parsed",
    .sstate = TRACE_NET_RX_PKT_PARSED_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_PARSED_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_validate_entry",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_validate_not_xxp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_validate_udp_with_no_checksum",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_validate_ip4_fragment",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_validate_csum",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_calc_entry",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_calc_ip4_udp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_calc_ip4_tcp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_calc_ip6_udp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_calc_ip6_tcp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_calc_ph_csum",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_calc_csum",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_fix_entry",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_fix_tcp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_fix_udp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_fix_not_xxp",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_fix_ip4_fragment",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_fix_udp_with_no_checksum",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l4_csum_fix_csum",
    .sstate = TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l3_csum_validate_entry",
    .sstate = TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l3_csum_validate_not_ip4",
    .sstate = TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_l3_csum_validate_csum",
    .sstate = TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP4_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip4",
    .sstate = TRACE_NET_RX_PKT_RSS_IP4_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP4_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP4_TCP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip4_tcp",
    .sstate = TRACE_NET_RX_PKT_RSS_IP4_TCP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP4_TCP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP4_UDP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip4_udp",
    .sstate = TRACE_NET_RX_PKT_RSS_IP4_UDP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP4_UDP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_TCP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip6_tcp",
    .sstate = TRACE_NET_RX_PKT_RSS_IP6_TCP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP6_TCP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_UDP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip6_udp",
    .sstate = TRACE_NET_RX_PKT_RSS_IP6_UDP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP6_UDP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip6",
    .sstate = TRACE_NET_RX_PKT_RSS_IP6_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP6_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EX_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip6_ex",
    .sstate = TRACE_NET_RX_PKT_RSS_IP6_EX_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP6_EX_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip6_ex_tcp",
    .sstate = TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_ip6_ex_udp",
    .sstate = TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_HASH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_hash",
    .sstate = TRACE_NET_RX_PKT_RSS_HASH_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_HASH_DSTATE 
};
TraceEvent _TRACE_NET_RX_PKT_RSS_ADD_CHUNK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "net_rx_pkt_rss_add_chunk",
    .sstate = TRACE_NET_RX_PKT_RSS_ADD_CHUNK_ENABLED,
    .dstate = &_TRACE_NET_RX_PKT_RSS_ADD_CHUNK_DSTATE 
};
TraceEvent _TRACE_E1000_RECEIVER_OVERRUN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000_receiver_overrun",
    .sstate = TRACE_E1000_RECEIVER_OVERRUN_ENABLED,
    .dstate = &_TRACE_E1000_RECEIVER_OVERRUN_DSTATE 
};
TraceEvent _TRACE_E1000X_RX_CAN_RECV_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_rx_can_recv_disabled",
    .sstate = TRACE_E1000X_RX_CAN_RECV_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000X_RX_CAN_RECV_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000X_VLAN_IS_VLAN_PKT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_vlan_is_vlan_pkt",
    .sstate = TRACE_E1000X_VLAN_IS_VLAN_PKT_ENABLED,
    .dstate = &_TRACE_E1000X_VLAN_IS_VLAN_PKT_DSTATE 
};
TraceEvent _TRACE_E1000X_RX_FLT_UCAST_MATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_rx_flt_ucast_match",
    .sstate = TRACE_E1000X_RX_FLT_UCAST_MATCH_ENABLED,
    .dstate = &_TRACE_E1000X_RX_FLT_UCAST_MATCH_DSTATE 
};
TraceEvent _TRACE_E1000X_RX_FLT_UCAST_MISMATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_rx_flt_ucast_mismatch",
    .sstate = TRACE_E1000X_RX_FLT_UCAST_MISMATCH_ENABLED,
    .dstate = &_TRACE_E1000X_RX_FLT_UCAST_MISMATCH_DSTATE 
};
TraceEvent _TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_rx_flt_inexact_mismatch",
    .sstate = TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_ENABLED,
    .dstate = &_TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_DSTATE 
};
TraceEvent _TRACE_E1000X_RX_LINK_DOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_rx_link_down",
    .sstate = TRACE_E1000X_RX_LINK_DOWN_ENABLED,
    .dstate = &_TRACE_E1000X_RX_LINK_DOWN_DSTATE 
};
TraceEvent _TRACE_E1000X_RX_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_rx_disabled",
    .sstate = TRACE_E1000X_RX_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000X_RX_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000X_RX_OVERSIZED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_rx_oversized",
    .sstate = TRACE_E1000X_RX_OVERSIZED_ENABLED,
    .dstate = &_TRACE_E1000X_RX_OVERSIZED_DSTATE 
};
TraceEvent _TRACE_E1000X_MAC_INDICATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_mac_indicate",
    .sstate = TRACE_E1000X_MAC_INDICATE_ENABLED,
    .dstate = &_TRACE_E1000X_MAC_INDICATE_DSTATE 
};
TraceEvent _TRACE_E1000X_LINK_NEGOTIATION_START_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_link_negotiation_start",
    .sstate = TRACE_E1000X_LINK_NEGOTIATION_START_ENABLED,
    .dstate = &_TRACE_E1000X_LINK_NEGOTIATION_START_DSTATE 
};
TraceEvent _TRACE_E1000X_LINK_NEGOTIATION_DONE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000x_link_negotiation_done",
    .sstate = TRACE_E1000X_LINK_NEGOTIATION_DONE_ENABLED,
    .dstate = &_TRACE_E1000X_LINK_NEGOTIATION_DONE_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_write",
    .sstate = TRACE_E1000E_CORE_WRITE_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_WRITE_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_read",
    .sstate = TRACE_E1000E_CORE_READ_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_READ_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_MDIC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_mdic_read",
    .sstate = TRACE_E1000E_CORE_MDIC_READ_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_MDIC_READ_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_mdic_read_unhandled",
    .sstate = TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_MDIC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_mdic_write",
    .sstate = TRACE_E1000E_CORE_MDIC_WRITE_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_MDIC_WRITE_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_mdic_write_unhandled",
    .sstate = TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_CTRL_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_ctrl_write",
    .sstate = TRACE_E1000E_CORE_CTRL_WRITE_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_CTRL_WRITE_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_CTRL_SW_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_ctrl_sw_reset",
    .sstate = TRACE_E1000E_CORE_CTRL_SW_RESET_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_CTRL_SW_RESET_DSTATE 
};
TraceEvent _TRACE_E1000E_CORE_CTRL_PHY_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_core_ctrl_phy_reset",
    .sstate = TRACE_E1000E_CORE_CTRL_PHY_RESET_ENABLED,
    .dstate = &_TRACE_E1000E_CORE_CTRL_PHY_RESET_DSTATE 
};
TraceEvent _TRACE_E1000E_LINK_AUTONEG_FLOWCTL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_link_autoneg_flowctl",
    .sstate = TRACE_E1000E_LINK_AUTONEG_FLOWCTL_ENABLED,
    .dstate = &_TRACE_E1000E_LINK_AUTONEG_FLOWCTL_DSTATE 
};
TraceEvent _TRACE_E1000E_LINK_SET_PARAMS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_link_set_params",
    .sstate = TRACE_E1000E_LINK_SET_PARAMS_ENABLED,
    .dstate = &_TRACE_E1000E_LINK_SET_PARAMS_DSTATE 
};
TraceEvent _TRACE_E1000E_LINK_READ_PARAMS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_link_read_params",
    .sstate = TRACE_E1000E_LINK_READ_PARAMS_ENABLED,
    .dstate = &_TRACE_E1000E_LINK_READ_PARAMS_DSTATE 
};
TraceEvent _TRACE_E1000E_LINK_SET_EXT_PARAMS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_link_set_ext_params",
    .sstate = TRACE_E1000E_LINK_SET_EXT_PARAMS_ENABLED,
    .dstate = &_TRACE_E1000E_LINK_SET_EXT_PARAMS_DSTATE 
};
TraceEvent _TRACE_E1000E_LINK_STATUS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_link_status",
    .sstate = TRACE_E1000E_LINK_STATUS_ENABLED,
    .dstate = &_TRACE_E1000E_LINK_STATUS_DSTATE 
};
TraceEvent _TRACE_E1000E_LINK_STATUS_CHANGED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_link_status_changed",
    .sstate = TRACE_E1000E_LINK_STATUS_CHANGED_ENABLED,
    .dstate = &_TRACE_E1000E_LINK_STATUS_CHANGED_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_REGS_WRITE_RO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_regs_write_ro",
    .sstate = TRACE_E1000E_WRN_REGS_WRITE_RO_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_REGS_WRITE_RO_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_regs_write_unknown",
    .sstate = TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_REGS_READ_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_regs_read_unknown",
    .sstate = TRACE_E1000E_WRN_REGS_READ_UNKNOWN_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_REGS_READ_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_REGS_READ_TRIVIAL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_regs_read_trivial",
    .sstate = TRACE_E1000E_WRN_REGS_READ_TRIVIAL_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_REGS_READ_TRIVIAL_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_regs_write_trivial",
    .sstate = TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_NO_TS_SUPPORT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_no_ts_support",
    .sstate = TRACE_E1000E_WRN_NO_TS_SUPPORT_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_NO_TS_SUPPORT_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_NO_SNAP_SUPPORT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_no_snap_support",
    .sstate = TRACE_E1000E_WRN_NO_SNAP_SUPPORT_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_NO_SNAP_SUPPORT_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_iscsi_filtering_not_supported",
    .sstate = TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_nfsw_filtering_not_supported",
    .sstate = TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_nfsr_filtering_not_supported",
    .sstate = TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_DSTATE 
};
TraceEvent _TRACE_E1000E_TX_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_tx_disabled",
    .sstate = TRACE_E1000E_TX_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000E_TX_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000E_TX_DESCR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_tx_descr",
    .sstate = TRACE_E1000E_TX_DESCR_ENABLED,
    .dstate = &_TRACE_E1000E_TX_DESCR_DSTATE 
};
TraceEvent _TRACE_E1000E_RING_FREE_SPACE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_ring_free_space",
    .sstate = TRACE_E1000E_RING_FREE_SPACE_ENABLED,
    .dstate = &_TRACE_E1000E_RING_FREE_SPACE_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_can_recv_rings_full",
    .sstate = TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_ENABLED,
    .dstate = &_TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_CAN_RECV_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_can_recv",
    .sstate = TRACE_E1000E_RX_CAN_RECV_ENABLED,
    .dstate = &_TRACE_E1000E_RX_CAN_RECV_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_HAS_BUFFERS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_has_buffers",
    .sstate = TRACE_E1000E_RX_HAS_BUFFERS_ENABLED,
    .dstate = &_TRACE_E1000E_RX_HAS_BUFFERS_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_NULL_DESCRIPTOR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_null_descriptor",
    .sstate = TRACE_E1000E_RX_NULL_DESCRIPTOR_ENABLED,
    .dstate = &_TRACE_E1000E_RX_NULL_DESCRIPTOR_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_FLT_VLAN_MISMATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_flt_vlan_mismatch",
    .sstate = TRACE_E1000E_RX_FLT_VLAN_MISMATCH_ENABLED,
    .dstate = &_TRACE_E1000E_RX_FLT_VLAN_MISMATCH_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_FLT_VLAN_MATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_flt_vlan_match",
    .sstate = TRACE_E1000E_RX_FLT_VLAN_MATCH_ENABLED,
    .dstate = &_TRACE_E1000E_RX_FLT_VLAN_MATCH_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_DESC_PS_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_desc_ps_read",
    .sstate = TRACE_E1000E_RX_DESC_PS_READ_ENABLED,
    .dstate = &_TRACE_E1000E_RX_DESC_PS_READ_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_DESC_PS_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_desc_ps_write",
    .sstate = TRACE_E1000E_RX_DESC_PS_WRITE_ENABLED,
    .dstate = &_TRACE_E1000E_RX_DESC_PS_WRITE_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_DESC_BUFF_SIZES_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_desc_buff_sizes",
    .sstate = TRACE_E1000E_RX_DESC_BUFF_SIZES_ENABLED,
    .dstate = &_TRACE_E1000E_RX_DESC_BUFF_SIZES_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_DESC_LEN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_desc_len",
    .sstate = TRACE_E1000E_RX_DESC_LEN_ENABLED,
    .dstate = &_TRACE_E1000E_RX_DESC_LEN_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_DESC_BUFF_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_desc_buff_write",
    .sstate = TRACE_E1000E_RX_DESC_BUFF_WRITE_ENABLED,
    .dstate = &_TRACE_E1000E_RX_DESC_BUFF_WRITE_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_DESCR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_descr",
    .sstate = TRACE_E1000E_RX_DESCR_ENABLED,
    .dstate = &_TRACE_E1000E_RX_DESCR_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_SET_RCTL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_set_rctl",
    .sstate = TRACE_E1000E_RX_SET_RCTL_ENABLED,
    .dstate = &_TRACE_E1000E_RX_SET_RCTL_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RECEIVE_IOV_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_receive_iov",
    .sstate = TRACE_E1000E_RX_RECEIVE_IOV_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RECEIVE_IOV_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_FLT_DROPPED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_flt_dropped",
    .sstate = TRACE_E1000E_RX_FLT_DROPPED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_FLT_DROPPED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_WRITTEN_TO_GUEST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_written_to_guest",
    .sstate = TRACE_E1000E_RX_WRITTEN_TO_GUEST_ENABLED,
    .dstate = &_TRACE_E1000E_RX_WRITTEN_TO_GUEST_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_not_written_to_guest",
    .sstate = TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_ENABLED,
    .dstate = &_TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_INTERRUPT_SET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_interrupt_set",
    .sstate = TRACE_E1000E_RX_INTERRUPT_SET_ENABLED,
    .dstate = &_TRACE_E1000E_RX_INTERRUPT_SET_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_INTERRUPT_DELAYED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_interrupt_delayed",
    .sstate = TRACE_E1000E_RX_INTERRUPT_DELAYED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_INTERRUPT_DELAYED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_SET_CSO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_set_cso",
    .sstate = TRACE_E1000E_RX_SET_CSO_ENABLED,
    .dstate = &_TRACE_E1000E_RX_SET_CSO_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_SET_RDT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_set_rdt",
    .sstate = TRACE_E1000E_RX_SET_RDT_ENABLED,
    .dstate = &_TRACE_E1000E_RX_SET_RDT_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_SET_RFCTL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_set_rfctl",
    .sstate = TRACE_E1000E_RX_SET_RFCTL_ENABLED,
    .dstate = &_TRACE_E1000E_RX_SET_RFCTL_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_START_RECV_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_start_recv",
    .sstate = TRACE_E1000E_RX_START_RECV_ENABLED,
    .dstate = &_TRACE_E1000E_RX_START_RECV_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RSS_STARTED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_rss_started",
    .sstate = TRACE_E1000E_RX_RSS_STARTED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RSS_STARTED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RSS_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_rss_disabled",
    .sstate = TRACE_E1000E_RX_RSS_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RSS_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RSS_TYPE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_rss_type",
    .sstate = TRACE_E1000E_RX_RSS_TYPE_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RSS_TYPE_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RSS_IP4_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_rss_ip4",
    .sstate = TRACE_E1000E_RX_RSS_IP4_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RSS_IP4_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RSS_IP6_RFCTL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_rss_ip6_rfctl",
    .sstate = TRACE_E1000E_RX_RSS_IP6_RFCTL_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RSS_IP6_RFCTL_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RSS_IP6_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_rss_ip6",
    .sstate = TRACE_E1000E_RX_RSS_IP6_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RSS_IP6_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_RSS_DISPATCHED_TO_QUEUE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_rss_dispatched_to_queue",
    .sstate = TRACE_E1000E_RX_RSS_DISPATCHED_TO_QUEUE_ENABLED,
    .dstate = &_TRACE_E1000E_RX_RSS_DISPATCHED_TO_QUEUE_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_PROTOCOLS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_protocols",
    .sstate = TRACE_E1000E_RX_METADATA_PROTOCOLS_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_PROTOCOLS_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_VLAN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_vlan",
    .sstate = TRACE_E1000E_RX_METADATA_VLAN_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_VLAN_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_RSS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_rss",
    .sstate = TRACE_E1000E_RX_METADATA_RSS_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_RSS_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_IP_ID_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_ip_id",
    .sstate = TRACE_E1000E_RX_METADATA_IP_ID_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_IP_ID_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_ACK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_ack",
    .sstate = TRACE_E1000E_RX_METADATA_ACK_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_ACK_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_PKT_TYPE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_pkt_type",
    .sstate = TRACE_E1000E_RX_METADATA_PKT_TYPE_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_PKT_TYPE_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_NO_VIRTHDR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_no_virthdr",
    .sstate = TRACE_E1000E_RX_METADATA_NO_VIRTHDR_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_NO_VIRTHDR_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_virthdr_no_csum_info",
    .sstate = TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_l3_cso_disabled",
    .sstate = TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_l4_cso_disabled",
    .sstate = TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_l3_csum_validation_failed",
    .sstate = TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_l4_csum_validation_failed",
    .sstate = TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_STATUS_FLAGS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_status_flags",
    .sstate = TRACE_E1000E_RX_METADATA_STATUS_FLAGS_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_STATUS_FLAGS_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_ipv6_sum_disabled",
    .sstate = TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_rx_metadata_ipv6_filtering_disabled",
    .sstate = TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_ENABLED,
    .dstate = &_TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_DSTATE 
};
TraceEvent _TRACE_E1000E_VLAN_VET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_vlan_vet",
    .sstate = TRACE_E1000E_VLAN_VET_ENABLED,
    .dstate = &_TRACE_E1000E_VLAN_VET_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_MSI_NOTIFY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_msi_notify",
    .sstate = TRACE_E1000E_IRQ_MSI_NOTIFY_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_MSI_NOTIFY_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_INTERRUPTS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_throttling_no_pending_interrupts",
    .sstate = TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_INTERRUPTS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_INTERRUPTS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_msi_notify_postponed",
    .sstate = TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_legacy_notify_postponed",
    .sstate = TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_VEC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_throttling_no_pending_vec",
    .sstate = TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_VEC_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_VEC_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_msix_notify_postponed_vec",
    .sstate = TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_LEGACY_NOTIFY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_legacy_notify",
    .sstate = TRACE_E1000E_IRQ_LEGACY_NOTIFY_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_LEGACY_NOTIFY_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_msix_notify_vec",
    .sstate = TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_POSTPONED_BY_XITR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_postponed_by_xitr",
    .sstate = TRACE_E1000E_IRQ_POSTPONED_BY_XITR_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_POSTPONED_BY_XITR_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_CLEAR_IMS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_clear_ims",
    .sstate = TRACE_E1000E_IRQ_CLEAR_IMS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_CLEAR_IMS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_SET_IMS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_set_ims",
    .sstate = TRACE_E1000E_IRQ_SET_IMS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_SET_IMS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_fix_icr_asserted",
    .sstate = TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ADD_MSI_OTHER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_add_msi_other",
    .sstate = TRACE_E1000E_IRQ_ADD_MSI_OTHER_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ADD_MSI_OTHER_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_PENDING_INTERRUPTS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_pending_interrupts",
    .sstate = TRACE_E1000E_IRQ_PENDING_INTERRUPTS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_PENDING_INTERRUPTS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_SET_CAUSE_ENTRY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_set_cause_entry",
    .sstate = TRACE_E1000E_IRQ_SET_CAUSE_ENTRY_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_SET_CAUSE_ENTRY_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_SET_CAUSE_EXIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_set_cause_exit",
    .sstate = TRACE_E1000E_IRQ_SET_CAUSE_EXIT_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_SET_CAUSE_EXIT_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_write",
    .sstate = TRACE_E1000E_IRQ_ICR_WRITE_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_WRITE_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_WRITE_ICS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_write_ics",
    .sstate = TRACE_E1000E_IRQ_WRITE_ICS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_WRITE_ICS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_PROCESS_IAME_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_process_iame",
    .sstate = TRACE_E1000E_IRQ_ICR_PROCESS_IAME_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_PROCESS_IAME_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_READ_ICS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_read_ics",
    .sstate = TRACE_E1000E_IRQ_READ_ICS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_READ_ICS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_READ_IMS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_read_ims",
    .sstate = TRACE_E1000E_IRQ_READ_IMS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_READ_IMS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_clear_nonmsix_icr_read",
    .sstate = TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_READ_ENTRY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_read_entry",
    .sstate = TRACE_E1000E_IRQ_ICR_READ_ENTRY_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_READ_ENTRY_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_READ_EXIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_read_exit",
    .sstate = TRACE_E1000E_IRQ_ICR_READ_EXIT_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_READ_EXIT_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_clear_zero_ims",
    .sstate = TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_IAME_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_clear_iame",
    .sstate = TRACE_E1000E_IRQ_ICR_CLEAR_IAME_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_CLEAR_IAME_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_iam_clear_eiame",
    .sstate = TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_icr_clear_eiac",
    .sstate = TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_ims_clear_set_imc",
    .sstate = TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_fire_delayed_interrupts",
    .sstate = TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_REARM_TIMER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_rearm_timer",
    .sstate = TRACE_E1000E_IRQ_REARM_TIMER_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_REARM_TIMER_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_THROTTLING_TIMER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_throttling_timer",
    .sstate = TRACE_E1000E_IRQ_THROTTLING_TIMER_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_THROTTLING_TIMER_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_rdtr_fpd_running",
    .sstate = TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_rdtr_fpd_not_running",
    .sstate = TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_tidv_fpd_running",
    .sstate = TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_tidv_fpd_not_running",
    .sstate = TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_EITR_SET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_eitr_set",
    .sstate = TRACE_E1000E_IRQ_EITR_SET_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_EITR_SET_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ITR_SET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_itr_set",
    .sstate = TRACE_E1000E_IRQ_ITR_SET_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ITR_SET_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_fire_all_timers",
    .sstate = TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_ADDING_DELAYED_CAUSES_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_adding_delayed_causes",
    .sstate = TRACE_E1000E_IRQ_ADDING_DELAYED_CAUSES_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_ADDING_DELAYED_CAUSES_DSTATE 
};
TraceEvent _TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_irq_msix_pending_clearing",
    .sstate = TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_ENABLED,
    .dstate = &_TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_MSIX_VEC_WRONG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_msix_vec_wrong",
    .sstate = TRACE_E1000E_WRN_MSIX_VEC_WRONG_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_MSIX_VEC_WRONG_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_MSIX_INVALID_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_msix_invalid",
    .sstate = TRACE_E1000E_WRN_MSIX_INVALID_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_MSIX_INVALID_DSTATE 
};
TraceEvent _TRACE_E1000E_MAC_SET_SW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_mac_set_sw",
    .sstate = TRACE_E1000E_MAC_SET_SW_ENABLED,
    .dstate = &_TRACE_E1000E_MAC_SET_SW_DSTATE 
};
TraceEvent _TRACE_E1000E_VM_STATE_RUNNING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_vm_state_running",
    .sstate = TRACE_E1000E_VM_STATE_RUNNING_ENABLED,
    .dstate = &_TRACE_E1000E_VM_STATE_RUNNING_DSTATE 
};
TraceEvent _TRACE_E1000E_VM_STATE_STOPPED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_vm_state_stopped",
    .sstate = TRACE_E1000E_VM_STATE_STOPPED_ENABLED,
    .dstate = &_TRACE_E1000E_VM_STATE_STOPPED_DSTATE 
};
TraceEvent _TRACE_E1000E_CB_PCI_REALIZE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_cb_pci_realize",
    .sstate = TRACE_E1000E_CB_PCI_REALIZE_ENABLED,
    .dstate = &_TRACE_E1000E_CB_PCI_REALIZE_DSTATE 
};
TraceEvent _TRACE_E1000E_CB_PCI_UNINIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_cb_pci_uninit",
    .sstate = TRACE_E1000E_CB_PCI_UNINIT_ENABLED,
    .dstate = &_TRACE_E1000E_CB_PCI_UNINIT_DSTATE 
};
TraceEvent _TRACE_E1000E_CB_QDEV_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_cb_qdev_reset",
    .sstate = TRACE_E1000E_CB_QDEV_RESET_ENABLED,
    .dstate = &_TRACE_E1000E_CB_QDEV_RESET_DSTATE 
};
TraceEvent _TRACE_E1000E_CB_PRE_SAVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_cb_pre_save",
    .sstate = TRACE_E1000E_CB_PRE_SAVE_ENABLED,
    .dstate = &_TRACE_E1000E_CB_PRE_SAVE_DSTATE 
};
TraceEvent _TRACE_E1000E_CB_POST_LOAD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_cb_post_load",
    .sstate = TRACE_E1000E_CB_POST_LOAD_ENABLED,
    .dstate = &_TRACE_E1000E_CB_POST_LOAD_DSTATE 
};
TraceEvent _TRACE_E1000E_IO_WRITE_ADDR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_io_write_addr",
    .sstate = TRACE_E1000E_IO_WRITE_ADDR_ENABLED,
    .dstate = &_TRACE_E1000E_IO_WRITE_ADDR_DSTATE 
};
TraceEvent _TRACE_E1000E_IO_WRITE_DATA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_io_write_data",
    .sstate = TRACE_E1000E_IO_WRITE_DATA_ENABLED,
    .dstate = &_TRACE_E1000E_IO_WRITE_DATA_DSTATE 
};
TraceEvent _TRACE_E1000E_IO_READ_ADDR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_io_read_addr",
    .sstate = TRACE_E1000E_IO_READ_ADDR_ENABLED,
    .dstate = &_TRACE_E1000E_IO_READ_ADDR_DSTATE 
};
TraceEvent _TRACE_E1000E_IO_READ_DATA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_io_read_data",
    .sstate = TRACE_E1000E_IO_READ_DATA_ENABLED,
    .dstate = &_TRACE_E1000E_IO_READ_DATA_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_io_write_unknown",
    .sstate = TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_IO_READ_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_io_read_unknown",
    .sstate = TRACE_E1000E_WRN_IO_READ_UNKNOWN_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_IO_READ_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_io_addr_undefined",
    .sstate = TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_IO_ADDR_FLASH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_io_addr_flash",
    .sstate = TRACE_E1000E_WRN_IO_ADDR_FLASH_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_IO_ADDR_FLASH_DSTATE 
};
TraceEvent _TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_wrn_io_addr_unknown",
    .sstate = TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_ENABLED,
    .dstate = &_TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_E1000E_MSI_INIT_FAIL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_msi_init_fail",
    .sstate = TRACE_E1000E_MSI_INIT_FAIL_ENABLED,
    .dstate = &_TRACE_E1000E_MSI_INIT_FAIL_DSTATE 
};
TraceEvent _TRACE_E1000E_MSIX_INIT_FAIL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_msix_init_fail",
    .sstate = TRACE_E1000E_MSIX_INIT_FAIL_ENABLED,
    .dstate = &_TRACE_E1000E_MSIX_INIT_FAIL_DSTATE 
};
TraceEvent _TRACE_E1000E_MSIX_USE_VECTOR_FAIL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_msix_use_vector_fail",
    .sstate = TRACE_E1000E_MSIX_USE_VECTOR_FAIL_ENABLED,
    .dstate = &_TRACE_E1000E_MSIX_USE_VECTOR_FAIL_DSTATE 
};
TraceEvent _TRACE_E1000E_MAC_SET_PERMANENT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_mac_set_permanent",
    .sstate = TRACE_E1000E_MAC_SET_PERMANENT_ENABLED,
    .dstate = &_TRACE_E1000E_MAC_SET_PERMANENT_DSTATE 
};
TraceEvent _TRACE_E1000E_CFG_SUPPORT_VIRTIO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "e1000e_cfg_support_virtio",
    .sstate = TRACE_E1000E_CFG_SUPPORT_VIRTIO_ENABLED,
    .dstate = &_TRACE_E1000E_CFG_SUPPORT_VIRTIO_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_get_rx_bd_from_pool_found",
    .sstate = TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_get_rx_bd_from_page",
    .sstate = TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_get_rx_bd_from_page_found",
    .sstate = TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_receive",
    .sstate = TRACE_SPAPR_VLAN_RECEIVE_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_RECEIVE_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_receive_dma_completed",
    .sstate = TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_RECEIVE_WROTE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_receive_wrote",
    .sstate = TRACE_SPAPR_VLAN_RECEIVE_WROTE_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_RECEIVE_WROTE_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_add_rxbuf_to_pool_create",
    .sstate = TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_add_rxbuf_to_pool",
    .sstate = TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_add_rxbuf_to_page",
    .sstate = TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_h_add_logical_lan_buffer",
    .sstate = TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_h_send_logical_lan",
    .sstate = TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_h_send_logical_lan_rxbufs",
    .sstate = TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_h_send_logical_lan_buf_desc",
    .sstate = TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_DSTATE 
};
TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_vlan_h_send_logical_lan_total",
    .sstate = TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_ENABLED,
    .dstate = &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_CHECKSUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_checksum",
    .sstate = TRACE_SUNGEM_TX_CHECKSUM_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_CHECKSUM_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_CHECKSUM_OOB_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_checksum_oob",
    .sstate = TRACE_SUNGEM_TX_CHECKSUM_OOB_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_CHECKSUM_OOB_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_UNFINISHED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_unfinished",
    .sstate = TRACE_SUNGEM_TX_UNFINISHED_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_UNFINISHED_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_OVERFLOW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_overflow",
    .sstate = TRACE_SUNGEM_TX_OVERFLOW_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_OVERFLOW_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_FINISHED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_finished",
    .sstate = TRACE_SUNGEM_TX_FINISHED_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_FINISHED_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_KICK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_kick",
    .sstate = TRACE_SUNGEM_TX_KICK_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_KICK_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_disabled",
    .sstate = TRACE_SUNGEM_TX_DISABLED_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_DISABLED_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_PROCESS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_process",
    .sstate = TRACE_SUNGEM_TX_PROCESS_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_PROCESS_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_DESC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_desc",
    .sstate = TRACE_SUNGEM_TX_DESC_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_DESC_DSTATE 
};
TraceEvent _TRACE_SUNGEM_TX_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_tx_reset",
    .sstate = TRACE_SUNGEM_TX_RESET_ENABLED,
    .dstate = &_TRACE_SUNGEM_TX_RESET_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_MAC_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_mac_disabled",
    .sstate = TRACE_SUNGEM_RX_MAC_DISABLED_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_MAC_DISABLED_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_TXDMA_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_txdma_disabled",
    .sstate = TRACE_SUNGEM_RX_TXDMA_DISABLED_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_TXDMA_DISABLED_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_CHECK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_check",
    .sstate = TRACE_SUNGEM_RX_CHECK_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_CHECK_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_MAC_CHECK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_mac_check",
    .sstate = TRACE_SUNGEM_RX_MAC_CHECK_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_MAC_CHECK_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_MAC_MULTICAST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_mac_multicast",
    .sstate = TRACE_SUNGEM_RX_MAC_MULTICAST_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_MAC_MULTICAST_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_MAC_COMPARE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_mac_compare",
    .sstate = TRACE_SUNGEM_RX_MAC_COMPARE_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_MAC_COMPARE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_PACKET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_packet",
    .sstate = TRACE_SUNGEM_RX_PACKET_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_PACKET_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_disabled",
    .sstate = TRACE_SUNGEM_RX_DISABLED_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_DISABLED_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_BAD_FRAME_SIZE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_bad_frame_size",
    .sstate = TRACE_SUNGEM_RX_BAD_FRAME_SIZE_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_BAD_FRAME_SIZE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_UNMATCHED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_unmatched",
    .sstate = TRACE_SUNGEM_RX_UNMATCHED_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_UNMATCHED_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_PROCESS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_process",
    .sstate = TRACE_SUNGEM_RX_PROCESS_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_PROCESS_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_RINGFULL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_ringfull",
    .sstate = TRACE_SUNGEM_RX_RINGFULL_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_RINGFULL_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_DESC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_desc",
    .sstate = TRACE_SUNGEM_RX_DESC_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_DESC_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_reset",
    .sstate = TRACE_SUNGEM_RX_RESET_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_RESET_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RX_KICK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_rx_kick",
    .sstate = TRACE_SUNGEM_RX_KICK_ENABLED,
    .dstate = &_TRACE_SUNGEM_RX_KICK_DSTATE 
};
TraceEvent _TRACE_SUNGEM_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_reset",
    .sstate = TRACE_SUNGEM_RESET_ENABLED,
    .dstate = &_TRACE_SUNGEM_RESET_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MII_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mii_write",
    .sstate = TRACE_SUNGEM_MII_WRITE_ENABLED,
    .dstate = &_TRACE_SUNGEM_MII_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MII_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mii_read",
    .sstate = TRACE_SUNGEM_MII_READ_ENABLED,
    .dstate = &_TRACE_SUNGEM_MII_READ_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MII_INVALID_SOF_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mii_invalid_sof",
    .sstate = TRACE_SUNGEM_MII_INVALID_SOF_ENABLED,
    .dstate = &_TRACE_SUNGEM_MII_INVALID_SOF_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MII_INVALID_OP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mii_invalid_op",
    .sstate = TRACE_SUNGEM_MII_INVALID_OP_ENABLED,
    .dstate = &_TRACE_SUNGEM_MII_INVALID_OP_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_GREG_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_greg_write",
    .sstate = TRACE_SUNGEM_MMIO_GREG_WRITE_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_GREG_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_GREG_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_greg_read",
    .sstate = TRACE_SUNGEM_MMIO_GREG_READ_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_GREG_READ_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_TXDMA_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_txdma_write",
    .sstate = TRACE_SUNGEM_MMIO_TXDMA_WRITE_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_TXDMA_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_TXDMA_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_txdma_read",
    .sstate = TRACE_SUNGEM_MMIO_TXDMA_READ_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_TXDMA_READ_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_RXDMA_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_rxdma_write",
    .sstate = TRACE_SUNGEM_MMIO_RXDMA_WRITE_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_RXDMA_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_RXDMA_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_rxdma_read",
    .sstate = TRACE_SUNGEM_MMIO_RXDMA_READ_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_RXDMA_READ_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_MAC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_mac_write",
    .sstate = TRACE_SUNGEM_MMIO_MAC_WRITE_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_MAC_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_MAC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_mac_read",
    .sstate = TRACE_SUNGEM_MMIO_MAC_READ_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_MAC_READ_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_MIF_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_mif_write",
    .sstate = TRACE_SUNGEM_MMIO_MIF_WRITE_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_MIF_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_MIF_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_mif_read",
    .sstate = TRACE_SUNGEM_MMIO_MIF_READ_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_MIF_READ_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_PCS_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_pcs_write",
    .sstate = TRACE_SUNGEM_MMIO_PCS_WRITE_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_PCS_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNGEM_MMIO_PCS_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sungem_mmio_pcs_read",
    .sstate = TRACE_SUNGEM_MMIO_PCS_READ_ENABLED,
    .dstate = &_TRACE_SUNGEM_MMIO_PCS_READ_DSTATE 
};
TraceEvent _TRACE_SUNHME_SEB_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_seb_write",
    .sstate = TRACE_SUNHME_SEB_WRITE_ENABLED,
    .dstate = &_TRACE_SUNHME_SEB_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNHME_SEB_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_seb_read",
    .sstate = TRACE_SUNHME_SEB_READ_ENABLED,
    .dstate = &_TRACE_SUNHME_SEB_READ_DSTATE 
};
TraceEvent _TRACE_SUNHME_ETX_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_etx_write",
    .sstate = TRACE_SUNHME_ETX_WRITE_ENABLED,
    .dstate = &_TRACE_SUNHME_ETX_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNHME_ETX_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_etx_read",
    .sstate = TRACE_SUNHME_ETX_READ_ENABLED,
    .dstate = &_TRACE_SUNHME_ETX_READ_DSTATE 
};
TraceEvent _TRACE_SUNHME_ERX_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_erx_write",
    .sstate = TRACE_SUNHME_ERX_WRITE_ENABLED,
    .dstate = &_TRACE_SUNHME_ERX_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNHME_ERX_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_erx_read",
    .sstate = TRACE_SUNHME_ERX_READ_ENABLED,
    .dstate = &_TRACE_SUNHME_ERX_READ_DSTATE 
};
TraceEvent _TRACE_SUNHME_MAC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_mac_write",
    .sstate = TRACE_SUNHME_MAC_WRITE_ENABLED,
    .dstate = &_TRACE_SUNHME_MAC_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNHME_MAC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_mac_read",
    .sstate = TRACE_SUNHME_MAC_READ_ENABLED,
    .dstate = &_TRACE_SUNHME_MAC_READ_DSTATE 
};
TraceEvent _TRACE_SUNHME_MII_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_mii_write",
    .sstate = TRACE_SUNHME_MII_WRITE_ENABLED,
    .dstate = &_TRACE_SUNHME_MII_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNHME_MII_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_mii_read",
    .sstate = TRACE_SUNHME_MII_READ_ENABLED,
    .dstate = &_TRACE_SUNHME_MII_READ_DSTATE 
};
TraceEvent _TRACE_SUNHME_MIF_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_mif_write",
    .sstate = TRACE_SUNHME_MIF_WRITE_ENABLED,
    .dstate = &_TRACE_SUNHME_MIF_WRITE_DSTATE 
};
TraceEvent _TRACE_SUNHME_MIF_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_mif_read",
    .sstate = TRACE_SUNHME_MIF_READ_ENABLED,
    .dstate = &_TRACE_SUNHME_MIF_READ_DSTATE 
};
TraceEvent _TRACE_SUNHME_TX_DESC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_tx_desc",
    .sstate = TRACE_SUNHME_TX_DESC_ENABLED,
    .dstate = &_TRACE_SUNHME_TX_DESC_DSTATE 
};
TraceEvent _TRACE_SUNHME_TX_XSUM_ADD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_tx_xsum_add",
    .sstate = TRACE_SUNHME_TX_XSUM_ADD_ENABLED,
    .dstate = &_TRACE_SUNHME_TX_XSUM_ADD_DSTATE 
};
TraceEvent _TRACE_SUNHME_TX_XSUM_STUFF_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_tx_xsum_stuff",
    .sstate = TRACE_SUNHME_TX_XSUM_STUFF_ENABLED,
    .dstate = &_TRACE_SUNHME_TX_XSUM_STUFF_DSTATE 
};
TraceEvent _TRACE_SUNHME_TX_DONE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_tx_done",
    .sstate = TRACE_SUNHME_TX_DONE_ENABLED,
    .dstate = &_TRACE_SUNHME_TX_DONE_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_INCOMING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_incoming",
    .sstate = TRACE_SUNHME_RX_INCOMING_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_INCOMING_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_DESTMAC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_destmac",
    .sstate = TRACE_SUNHME_RX_FILTER_DESTMAC_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_DESTMAC_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_local_match",
    .sstate = TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_BCAST_MATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_bcast_match",
    .sstate = TRACE_SUNHME_RX_FILTER_BCAST_MATCH_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_BCAST_MATCH_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_hash_nomatch",
    .sstate = TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_HASH_MATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_hash_match",
    .sstate = TRACE_SUNHME_RX_FILTER_HASH_MATCH_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_HASH_MATCH_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_promisc_match",
    .sstate = TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_REJECT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_reject",
    .sstate = TRACE_SUNHME_RX_FILTER_REJECT_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_REJECT_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_FILTER_ACCEPT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_filter_accept",
    .sstate = TRACE_SUNHME_RX_FILTER_ACCEPT_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_FILTER_ACCEPT_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_DESC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_desc",
    .sstate = TRACE_SUNHME_RX_DESC_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_DESC_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_XSUM_CALC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_xsum_calc",
    .sstate = TRACE_SUNHME_RX_XSUM_CALC_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_XSUM_CALC_DSTATE 
};
TraceEvent _TRACE_SUNHME_RX_NORXD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_rx_norxd",
    .sstate = TRACE_SUNHME_RX_NORXD_ENABLED,
    .dstate = &_TRACE_SUNHME_RX_NORXD_DSTATE 
};
TraceEvent _TRACE_SUNHME_UPDATE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sunhme_update_irq",
    .sstate = TRACE_SUNHME_UPDATE_IRQ_ENABLED,
    .dstate = &_TRACE_SUNHME_UPDATE_IRQ_DSTATE 
};
TraceEvent _TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_net_announce_notify",
    .sstate = TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_ENABLED,
    .dstate = &_TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_DSTATE 
};
TraceEvent _TRACE_VIRTIO_NET_ANNOUNCE_TIMER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_net_announce_timer",
    .sstate = TRACE_VIRTIO_NET_ANNOUNCE_TIMER_ENABLED,
    .dstate = &_TRACE_VIRTIO_NET_ANNOUNCE_TIMER_DSTATE 
};
TraceEvent _TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_net_handle_announce",
    .sstate = TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_ENABLED,
    .dstate = &_TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_DSTATE 
};
TraceEvent _TRACE_VIRTIO_NET_POST_LOAD_DEVICE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_net_post_load_device",
    .sstate = TRACE_VIRTIO_NET_POST_LOAD_DEVICE_ENABLED,
    .dstate = &_TRACE_VIRTIO_NET_POST_LOAD_DEVICE_DSTATE 
};
TraceEvent _TRACE_VIRTIO_NET_RSS_DISABLE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_net_rss_disable",
    .sstate = TRACE_VIRTIO_NET_RSS_DISABLE_ENABLED,
    .dstate = &_TRACE_VIRTIO_NET_RSS_DISABLE_DSTATE 
};
TraceEvent _TRACE_VIRTIO_NET_RSS_ERROR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_net_rss_error",
    .sstate = TRACE_VIRTIO_NET_RSS_ERROR_ENABLED,
    .dstate = &_TRACE_VIRTIO_NET_RSS_ERROR_DSTATE 
};
TraceEvent _TRACE_VIRTIO_NET_RSS_ENABLE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virtio_net_rss_enable",
    .sstate = TRACE_VIRTIO_NET_RSS_ENABLE_ENABLED,
    .dstate = &_TRACE_VIRTIO_NET_RSS_ENABLE_DSTATE 
};
TraceEvent _TRACE_TULIP_REG_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_reg_write",
    .sstate = TRACE_TULIP_REG_WRITE_ENABLED,
    .dstate = &_TRACE_TULIP_REG_WRITE_DSTATE 
};
TraceEvent _TRACE_TULIP_REG_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_reg_read",
    .sstate = TRACE_TULIP_REG_READ_ENABLED,
    .dstate = &_TRACE_TULIP_REG_READ_DSTATE 
};
TraceEvent _TRACE_TULIP_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_receive",
    .sstate = TRACE_TULIP_RECEIVE_ENABLED,
    .dstate = &_TRACE_TULIP_RECEIVE_DSTATE 
};
TraceEvent _TRACE_TULIP_DESCRIPTOR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_descriptor",
    .sstate = TRACE_TULIP_DESCRIPTOR_ENABLED,
    .dstate = &_TRACE_TULIP_DESCRIPTOR_DSTATE 
};
TraceEvent _TRACE_TULIP_RX_STATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_rx_state",
    .sstate = TRACE_TULIP_RX_STATE_ENABLED,
    .dstate = &_TRACE_TULIP_RX_STATE_DSTATE 
};
TraceEvent _TRACE_TULIP_TX_STATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_tx_state",
    .sstate = TRACE_TULIP_TX_STATE_ENABLED,
    .dstate = &_TRACE_TULIP_TX_STATE_DSTATE 
};
TraceEvent _TRACE_TULIP_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_irq",
    .sstate = TRACE_TULIP_IRQ_ENABLED,
    .dstate = &_TRACE_TULIP_IRQ_DSTATE 
};
TraceEvent _TRACE_TULIP_MII_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_mii_write",
    .sstate = TRACE_TULIP_MII_WRITE_ENABLED,
    .dstate = &_TRACE_TULIP_MII_WRITE_DSTATE 
};
TraceEvent _TRACE_TULIP_MII_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_mii_read",
    .sstate = TRACE_TULIP_MII_READ_ENABLED,
    .dstate = &_TRACE_TULIP_MII_READ_DSTATE 
};
TraceEvent _TRACE_TULIP_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_reset",
    .sstate = TRACE_TULIP_RESET_ENABLED,
    .dstate = &_TRACE_TULIP_RESET_DSTATE 
};
TraceEvent _TRACE_TULIP_SETUP_FRAME_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_setup_frame",
    .sstate = TRACE_TULIP_SETUP_FRAME_ENABLED,
    .dstate = &_TRACE_TULIP_SETUP_FRAME_DSTATE 
};
TraceEvent _TRACE_TULIP_SETUP_FILTER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "tulip_setup_filter",
    .sstate = TRACE_TULIP_SETUP_FILTER_ENABLED,
    .dstate = &_TRACE_TULIP_SETUP_FILTER_DSTATE 
};
TraceEvent _TRACE_LASI_82596_MEM_READW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "lasi_82596_mem_readw",
    .sstate = TRACE_LASI_82596_MEM_READW_ENABLED,
    .dstate = &_TRACE_LASI_82596_MEM_READW_DSTATE 
};
TraceEvent _TRACE_LASI_82596_MEM_WRITEW_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "lasi_82596_mem_writew",
    .sstate = TRACE_LASI_82596_MEM_WRITEW_ENABLED,
    .dstate = &_TRACE_LASI_82596_MEM_WRITEW_DSTATE 
};
TraceEvent _TRACE_I82596_S_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "i82596_s_reset",
    .sstate = TRACE_I82596_S_RESET_ENABLED,
    .dstate = &_TRACE_I82596_S_RESET_DSTATE 
};
TraceEvent _TRACE_I82596_TRANSMIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "i82596_transmit",
    .sstate = TRACE_I82596_TRANSMIT_ENABLED,
    .dstate = &_TRACE_I82596_TRANSMIT_DSTATE 
};
TraceEvent _TRACE_I82596_RECEIVE_ANALYSIS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "i82596_receive_analysis",
    .sstate = TRACE_I82596_RECEIVE_ANALYSIS_ENABLED,
    .dstate = &_TRACE_I82596_RECEIVE_ANALYSIS_DSTATE 
};
TraceEvent _TRACE_I82596_RECEIVE_PACKET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "i82596_receive_packet",
    .sstate = TRACE_I82596_RECEIVE_PACKET_ENABLED,
    .dstate = &_TRACE_I82596_RECEIVE_PACKET_DSTATE 
};
TraceEvent _TRACE_I82596_NEW_MAC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "i82596_new_mac",
    .sstate = TRACE_I82596_NEW_MAC_ENABLED,
    .dstate = &_TRACE_I82596_NEW_MAC_DSTATE 
};
TraceEvent _TRACE_I82596_SET_MULTICAST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "i82596_set_multicast",
    .sstate = TRACE_I82596_SET_MULTICAST_ENABLED,
    .dstate = &_TRACE_I82596_SET_MULTICAST_DSTATE 
};
TraceEvent _TRACE_I82596_CHANNEL_ATTENTION_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "i82596_channel_attention",
    .sstate = TRACE_I82596_CHANNEL_ATTENTION_ENABLED,
    .dstate = &_TRACE_I82596_CHANNEL_ATTENTION_DSTATE 
};
TraceEvent _TRACE_IMX_PHY_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_phy_read",
    .sstate = TRACE_IMX_PHY_READ_ENABLED,
    .dstate = &_TRACE_IMX_PHY_READ_DSTATE 
};
TraceEvent _TRACE_IMX_PHY_READ_NUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_phy_read_num",
    .sstate = TRACE_IMX_PHY_READ_NUM_ENABLED,
    .dstate = &_TRACE_IMX_PHY_READ_NUM_DSTATE 
};
TraceEvent _TRACE_IMX_PHY_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_phy_write",
    .sstate = TRACE_IMX_PHY_WRITE_ENABLED,
    .dstate = &_TRACE_IMX_PHY_WRITE_DSTATE 
};
TraceEvent _TRACE_IMX_PHY_WRITE_NUM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_phy_write_num",
    .sstate = TRACE_IMX_PHY_WRITE_NUM_ENABLED,
    .dstate = &_TRACE_IMX_PHY_WRITE_NUM_DSTATE 
};
TraceEvent _TRACE_IMX_PHY_UPDATE_LINK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_phy_update_link",
    .sstate = TRACE_IMX_PHY_UPDATE_LINK_ENABLED,
    .dstate = &_TRACE_IMX_PHY_UPDATE_LINK_DSTATE 
};
TraceEvent _TRACE_IMX_PHY_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_phy_reset",
    .sstate = TRACE_IMX_PHY_RESET_ENABLED,
    .dstate = &_TRACE_IMX_PHY_RESET_DSTATE 
};
TraceEvent _TRACE_IMX_FEC_READ_BD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_fec_read_bd",
    .sstate = TRACE_IMX_FEC_READ_BD_ENABLED,
    .dstate = &_TRACE_IMX_FEC_READ_BD_DSTATE 
};
TraceEvent _TRACE_IMX_ENET_READ_BD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_enet_read_bd",
    .sstate = TRACE_IMX_ENET_READ_BD_ENABLED,
    .dstate = &_TRACE_IMX_ENET_READ_BD_DSTATE 
};
TraceEvent _TRACE_IMX_ETH_TX_BD_BUSY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_eth_tx_bd_busy",
    .sstate = TRACE_IMX_ETH_TX_BD_BUSY_ENABLED,
    .dstate = &_TRACE_IMX_ETH_TX_BD_BUSY_DSTATE 
};
TraceEvent _TRACE_IMX_ETH_RX_BD_FULL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_eth_rx_bd_full",
    .sstate = TRACE_IMX_ETH_RX_BD_FULL_ENABLED,
    .dstate = &_TRACE_IMX_ETH_RX_BD_FULL_DSTATE 
};
TraceEvent _TRACE_IMX_ETH_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_eth_read",
    .sstate = TRACE_IMX_ETH_READ_ENABLED,
    .dstate = &_TRACE_IMX_ETH_READ_DSTATE 
};
TraceEvent _TRACE_IMX_ETH_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_eth_write",
    .sstate = TRACE_IMX_ETH_WRITE_ENABLED,
    .dstate = &_TRACE_IMX_ETH_WRITE_DSTATE 
};
TraceEvent _TRACE_IMX_FEC_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_fec_receive",
    .sstate = TRACE_IMX_FEC_RECEIVE_ENABLED,
    .dstate = &_TRACE_IMX_FEC_RECEIVE_DSTATE 
};
TraceEvent _TRACE_IMX_FEC_RECEIVE_LEN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_fec_receive_len",
    .sstate = TRACE_IMX_FEC_RECEIVE_LEN_ENABLED,
    .dstate = &_TRACE_IMX_FEC_RECEIVE_LEN_DSTATE 
};
TraceEvent _TRACE_IMX_FEC_RECEIVE_LAST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_fec_receive_last",
    .sstate = TRACE_IMX_FEC_RECEIVE_LAST_ENABLED,
    .dstate = &_TRACE_IMX_FEC_RECEIVE_LAST_DSTATE 
};
TraceEvent _TRACE_IMX_ENET_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_enet_receive",
    .sstate = TRACE_IMX_ENET_RECEIVE_ENABLED,
    .dstate = &_TRACE_IMX_ENET_RECEIVE_DSTATE 
};
TraceEvent _TRACE_IMX_ENET_RECEIVE_LEN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_enet_receive_len",
    .sstate = TRACE_IMX_ENET_RECEIVE_LEN_ENABLED,
    .dstate = &_TRACE_IMX_ENET_RECEIVE_LEN_DSTATE 
};
TraceEvent _TRACE_IMX_ENET_RECEIVE_LAST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "imx_enet_receive_last",
    .sstate = TRACE_IMX_ENET_RECEIVE_LAST_ENABLED,
    .dstate = &_TRACE_IMX_ENET_RECEIVE_LAST_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_reset",
    .sstate = TRACE_NPCM7XX_EMC_RESET_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_RESET_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_update_tx_irq",
    .sstate = TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_update_rx_irq",
    .sstate = TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_SET_MISTA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_set_mista",
    .sstate = TRACE_NPCM7XX_EMC_SET_MISTA_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_SET_MISTA_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_cpu_owned_desc",
    .sstate = TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_SENT_PACKET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_sent_packet",
    .sstate = TRACE_NPCM7XX_EMC_SENT_PACKET_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_SENT_PACKET_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_TX_DONE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_tx_done",
    .sstate = TRACE_NPCM7XX_EMC_TX_DONE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_TX_DONE_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_CAN_RECEIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_can_receive",
    .sstate = TRACE_NPCM7XX_EMC_CAN_RECEIVE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_CAN_RECEIVE_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_packet_filtered_out",
    .sstate = TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_PACKET_DROPPED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_packet_dropped",
    .sstate = TRACE_NPCM7XX_EMC_PACKET_DROPPED_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_PACKET_DROPPED_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_RECEIVING_PACKET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_receiving_packet",
    .sstate = TRACE_NPCM7XX_EMC_RECEIVING_PACKET_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_RECEIVING_PACKET_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_RECEIVED_PACKET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_received_packet",
    .sstate = TRACE_NPCM7XX_EMC_RECEIVED_PACKET_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_RECEIVED_PACKET_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_RX_DONE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_rx_done",
    .sstate = TRACE_NPCM7XX_EMC_RX_DONE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_RX_DONE_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_REG_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_reg_read",
    .sstate = TRACE_NPCM7XX_EMC_REG_READ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_REG_READ_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_EMC_REG_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "npcm7xx_emc_reg_write",
    .sstate = TRACE_NPCM7XX_EMC_REG_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_EMC_REG_WRITE_DSTATE 
};
TraceEvent _TRACE_DP8393X_RAISE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_raise_irq",
    .sstate = TRACE_DP8393X_RAISE_IRQ_ENABLED,
    .dstate = &_TRACE_DP8393X_RAISE_IRQ_DSTATE 
};
TraceEvent _TRACE_DP8393X_LOWER_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_lower_irq",
    .sstate = TRACE_DP8393X_LOWER_IRQ_ENABLED,
    .dstate = &_TRACE_DP8393X_LOWER_IRQ_DSTATE 
};
TraceEvent _TRACE_DP8393X_LOAD_CAM_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_load_cam",
    .sstate = TRACE_DP8393X_LOAD_CAM_ENABLED,
    .dstate = &_TRACE_DP8393X_LOAD_CAM_DSTATE 
};
TraceEvent _TRACE_DP8393X_LOAD_CAM_DONE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_load_cam_done",
    .sstate = TRACE_DP8393X_LOAD_CAM_DONE_ENABLED,
    .dstate = &_TRACE_DP8393X_LOAD_CAM_DONE_DSTATE 
};
TraceEvent _TRACE_DP8393X_READ_RRA_REGS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_read_rra_regs",
    .sstate = TRACE_DP8393X_READ_RRA_REGS_ENABLED,
    .dstate = &_TRACE_DP8393X_READ_RRA_REGS_DSTATE 
};
TraceEvent _TRACE_DP8393X_TRANSMIT_PACKET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_transmit_packet",
    .sstate = TRACE_DP8393X_TRANSMIT_PACKET_ENABLED,
    .dstate = &_TRACE_DP8393X_TRANSMIT_PACKET_DSTATE 
};
TraceEvent _TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_transmit_txlen_error",
    .sstate = TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_ENABLED,
    .dstate = &_TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_DSTATE 
};
TraceEvent _TRACE_DP8393X_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_read",
    .sstate = TRACE_DP8393X_READ_ENABLED,
    .dstate = &_TRACE_DP8393X_READ_DSTATE 
};
TraceEvent _TRACE_DP8393X_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_write",
    .sstate = TRACE_DP8393X_WRITE_ENABLED,
    .dstate = &_TRACE_DP8393X_WRITE_DSTATE 
};
TraceEvent _TRACE_DP8393X_WRITE_INVALID_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_write_invalid",
    .sstate = TRACE_DP8393X_WRITE_INVALID_ENABLED,
    .dstate = &_TRACE_DP8393X_WRITE_INVALID_DSTATE 
};
TraceEvent _TRACE_DP8393X_WRITE_INVALID_DCR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_write_invalid_dcr",
    .sstate = TRACE_DP8393X_WRITE_INVALID_DCR_ENABLED,
    .dstate = &_TRACE_DP8393X_WRITE_INVALID_DCR_DSTATE 
};
TraceEvent _TRACE_DP8393X_RECEIVE_OVERSIZE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_receive_oversize",
    .sstate = TRACE_DP8393X_RECEIVE_OVERSIZE_ENABLED,
    .dstate = &_TRACE_DP8393X_RECEIVE_OVERSIZE_DSTATE 
};
TraceEvent _TRACE_DP8393X_RECEIVE_NOT_NETCARD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_receive_not_netcard",
    .sstate = TRACE_DP8393X_RECEIVE_NOT_NETCARD_ENABLED,
    .dstate = &_TRACE_DP8393X_RECEIVE_NOT_NETCARD_DSTATE 
};
TraceEvent _TRACE_DP8393X_RECEIVE_PACKET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_receive_packet",
    .sstate = TRACE_DP8393X_RECEIVE_PACKET_ENABLED,
    .dstate = &_TRACE_DP8393X_RECEIVE_PACKET_DSTATE 
};
TraceEvent _TRACE_DP8393X_RECEIVE_WRITE_STATUS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "dp8393x_receive_write_status",
    .sstate = TRACE_DP8393X_RECEIVE_WRITE_STATUS_ENABLED,
    .dstate = &_TRACE_DP8393X_RECEIVE_WRITE_STATUS_DSTATE 
};
TraceEvent *hw_net_trace_events[] = {
    &_TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_EVENT,
    &_TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_EVENT,
    &_TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_EVENT,
    &_TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_EVENT,
    &_TRACE_ALLWINNER_SUN8I_EMAC_RESET_EVENT,
    &_TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_EVENT,
    &_TRACE_ALLWINNER_SUN8I_EMAC_READ_EVENT,
    &_TRACE_ALLWINNER_SUN8I_EMAC_WRITE_EVENT,
    &_TRACE_MDIO_PHY_READ_EVENT,
    &_TRACE_MDIO_PHY_WRITE_EVENT,
    &_TRACE_MDIO_BITBANG_EVENT,
    &_TRACE_LANCE_MEM_READW_EVENT,
    &_TRACE_LANCE_MEM_WRITEW_EVENT,
    &_TRACE_MIPSNET_SEND_EVENT,
    &_TRACE_MIPSNET_RECEIVE_EVENT,
    &_TRACE_MIPSNET_READ_EVENT,
    &_TRACE_MIPSNET_WRITE_EVENT,
    &_TRACE_MIPSNET_IRQ_EVENT,
    &_TRACE_NE2000_READ_EVENT,
    &_TRACE_NE2000_WRITE_EVENT,
    &_TRACE_NE2000_IOPORT_READ_EVENT,
    &_TRACE_NE2000_IOPORT_WRITE_EVENT,
    &_TRACE_OPEN_ETH_MII_WRITE_EVENT,
    &_TRACE_OPEN_ETH_MII_READ_EVENT,
    &_TRACE_OPEN_ETH_UPDATE_IRQ_EVENT,
    &_TRACE_OPEN_ETH_RECEIVE_EVENT,
    &_TRACE_OPEN_ETH_RECEIVE_MCAST_EVENT,
    &_TRACE_OPEN_ETH_RECEIVE_REJECT_EVENT,
    &_TRACE_OPEN_ETH_RECEIVE_DESC_EVENT,
    &_TRACE_OPEN_ETH_START_XMIT_EVENT,
    &_TRACE_OPEN_ETH_REG_READ_EVENT,
    &_TRACE_OPEN_ETH_REG_WRITE_EVENT,
    &_TRACE_OPEN_ETH_DESC_READ_EVENT,
    &_TRACE_OPEN_ETH_DESC_WRITE_EVENT,
    &_TRACE_PCNET_S_RESET_EVENT,
    &_TRACE_PCNET_USER_INT_EVENT,
    &_TRACE_PCNET_ISR_CHANGE_EVENT,
    &_TRACE_PCNET_INIT_EVENT,
    &_TRACE_PCNET_RLEN_TLEN_EVENT,
    &_TRACE_PCNET_SS32_RDRA_TDRA_EVENT,
    &_TRACE_PCNET_APROM_WRITEB_EVENT,
    &_TRACE_PCNET_APROM_READB_EVENT,
    &_TRACE_PCNET_IOPORT_READ_EVENT,
    &_TRACE_PCNET_IOPORT_WRITE_EVENT,
    &_TRACE_NET_RX_PKT_PARSED_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_EVENT,
    &_TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_EVENT,
    &_TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_EVENT,
    &_TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_EVENT,
    &_TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP4_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP4_TCP_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP4_UDP_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP6_TCP_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP6_UDP_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP6_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP6_EX_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_EVENT,
    &_TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_EVENT,
    &_TRACE_NET_RX_PKT_RSS_HASH_EVENT,
    &_TRACE_NET_RX_PKT_RSS_ADD_CHUNK_EVENT,
    &_TRACE_E1000_RECEIVER_OVERRUN_EVENT,
    &_TRACE_E1000X_RX_CAN_RECV_DISABLED_EVENT,
    &_TRACE_E1000X_VLAN_IS_VLAN_PKT_EVENT,
    &_TRACE_E1000X_RX_FLT_UCAST_MATCH_EVENT,
    &_TRACE_E1000X_RX_FLT_UCAST_MISMATCH_EVENT,
    &_TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_EVENT,
    &_TRACE_E1000X_RX_LINK_DOWN_EVENT,
    &_TRACE_E1000X_RX_DISABLED_EVENT,
    &_TRACE_E1000X_RX_OVERSIZED_EVENT,
    &_TRACE_E1000X_MAC_INDICATE_EVENT,
    &_TRACE_E1000X_LINK_NEGOTIATION_START_EVENT,
    &_TRACE_E1000X_LINK_NEGOTIATION_DONE_EVENT,
    &_TRACE_E1000E_CORE_WRITE_EVENT,
    &_TRACE_E1000E_CORE_READ_EVENT,
    &_TRACE_E1000E_CORE_MDIC_READ_EVENT,
    &_TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_EVENT,
    &_TRACE_E1000E_CORE_MDIC_WRITE_EVENT,
    &_TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_EVENT,
    &_TRACE_E1000E_CORE_CTRL_WRITE_EVENT,
    &_TRACE_E1000E_CORE_CTRL_SW_RESET_EVENT,
    &_TRACE_E1000E_CORE_CTRL_PHY_RESET_EVENT,
    &_TRACE_E1000E_LINK_AUTONEG_FLOWCTL_EVENT,
    &_TRACE_E1000E_LINK_SET_PARAMS_EVENT,
    &_TRACE_E1000E_LINK_READ_PARAMS_EVENT,
    &_TRACE_E1000E_LINK_SET_EXT_PARAMS_EVENT,
    &_TRACE_E1000E_LINK_STATUS_EVENT,
    &_TRACE_E1000E_LINK_STATUS_CHANGED_EVENT,
    &_TRACE_E1000E_WRN_REGS_WRITE_RO_EVENT,
    &_TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_EVENT,
    &_TRACE_E1000E_WRN_REGS_READ_UNKNOWN_EVENT,
    &_TRACE_E1000E_WRN_REGS_READ_TRIVIAL_EVENT,
    &_TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_EVENT,
    &_TRACE_E1000E_WRN_NO_TS_SUPPORT_EVENT,
    &_TRACE_E1000E_WRN_NO_SNAP_SUPPORT_EVENT,
    &_TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_EVENT,
    &_TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_EVENT,
    &_TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_EVENT,
    &_TRACE_E1000E_TX_DISABLED_EVENT,
    &_TRACE_E1000E_TX_DESCR_EVENT,
    &_TRACE_E1000E_RING_FREE_SPACE_EVENT,
    &_TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_EVENT,
    &_TRACE_E1000E_RX_CAN_RECV_EVENT,
    &_TRACE_E1000E_RX_HAS_BUFFERS_EVENT,
    &_TRACE_E1000E_RX_NULL_DESCRIPTOR_EVENT,
    &_TRACE_E1000E_RX_FLT_VLAN_MISMATCH_EVENT,
    &_TRACE_E1000E_RX_FLT_VLAN_MATCH_EVENT,
    &_TRACE_E1000E_RX_DESC_PS_READ_EVENT,
    &_TRACE_E1000E_RX_DESC_PS_WRITE_EVENT,
    &_TRACE_E1000E_RX_DESC_BUFF_SIZES_EVENT,
    &_TRACE_E1000E_RX_DESC_LEN_EVENT,
    &_TRACE_E1000E_RX_DESC_BUFF_WRITE_EVENT,
    &_TRACE_E1000E_RX_DESCR_EVENT,
    &_TRACE_E1000E_RX_SET_RCTL_EVENT,
    &_TRACE_E1000E_RX_RECEIVE_IOV_EVENT,
    &_TRACE_E1000E_RX_FLT_DROPPED_EVENT,
    &_TRACE_E1000E_RX_WRITTEN_TO_GUEST_EVENT,
    &_TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_EVENT,
    &_TRACE_E1000E_RX_INTERRUPT_SET_EVENT,
    &_TRACE_E1000E_RX_INTERRUPT_DELAYED_EVENT,
    &_TRACE_E1000E_RX_SET_CSO_EVENT,
    &_TRACE_E1000E_RX_SET_RDT_EVENT,
    &_TRACE_E1000E_RX_SET_RFCTL_EVENT,
    &_TRACE_E1000E_RX_START_RECV_EVENT,
    &_TRACE_E1000E_RX_RSS_STARTED_EVENT,
    &_TRACE_E1000E_RX_RSS_DISABLED_EVENT,
    &_TRACE_E1000E_RX_RSS_TYPE_EVENT,
    &_TRACE_E1000E_RX_RSS_IP4_EVENT,
    &_TRACE_E1000E_RX_RSS_IP6_RFCTL_EVENT,
    &_TRACE_E1000E_RX_RSS_IP6_EVENT,
    &_TRACE_E1000E_RX_RSS_DISPATCHED_TO_QUEUE_EVENT,
    &_TRACE_E1000E_RX_METADATA_PROTOCOLS_EVENT,
    &_TRACE_E1000E_RX_METADATA_VLAN_EVENT,
    &_TRACE_E1000E_RX_METADATA_RSS_EVENT,
    &_TRACE_E1000E_RX_METADATA_IP_ID_EVENT,
    &_TRACE_E1000E_RX_METADATA_ACK_EVENT,
    &_TRACE_E1000E_RX_METADATA_PKT_TYPE_EVENT,
    &_TRACE_E1000E_RX_METADATA_NO_VIRTHDR_EVENT,
    &_TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_EVENT,
    &_TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_EVENT,
    &_TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_EVENT,
    &_TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_EVENT,
    &_TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_EVENT,
    &_TRACE_E1000E_RX_METADATA_STATUS_FLAGS_EVENT,
    &_TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_EVENT,
    &_TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_EVENT,
    &_TRACE_E1000E_VLAN_VET_EVENT,
    &_TRACE_E1000E_IRQ_MSI_NOTIFY_EVENT,
    &_TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_INTERRUPTS_EVENT,
    &_TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_EVENT,
    &_TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_EVENT,
    &_TRACE_E1000E_IRQ_THROTTLING_NO_PENDING_VEC_EVENT,
    &_TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_EVENT,
    &_TRACE_E1000E_IRQ_LEGACY_NOTIFY_EVENT,
    &_TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_EVENT,
    &_TRACE_E1000E_IRQ_POSTPONED_BY_XITR_EVENT,
    &_TRACE_E1000E_IRQ_CLEAR_IMS_EVENT,
    &_TRACE_E1000E_IRQ_SET_IMS_EVENT,
    &_TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_EVENT,
    &_TRACE_E1000E_IRQ_ADD_MSI_OTHER_EVENT,
    &_TRACE_E1000E_IRQ_PENDING_INTERRUPTS_EVENT,
    &_TRACE_E1000E_IRQ_SET_CAUSE_ENTRY_EVENT,
    &_TRACE_E1000E_IRQ_SET_CAUSE_EXIT_EVENT,
    &_TRACE_E1000E_IRQ_ICR_WRITE_EVENT,
    &_TRACE_E1000E_IRQ_WRITE_ICS_EVENT,
    &_TRACE_E1000E_IRQ_ICR_PROCESS_IAME_EVENT,
    &_TRACE_E1000E_IRQ_READ_ICS_EVENT,
    &_TRACE_E1000E_IRQ_READ_IMS_EVENT,
    &_TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_EVENT,
    &_TRACE_E1000E_IRQ_ICR_READ_ENTRY_EVENT,
    &_TRACE_E1000E_IRQ_ICR_READ_EXIT_EVENT,
    &_TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_EVENT,
    &_TRACE_E1000E_IRQ_ICR_CLEAR_IAME_EVENT,
    &_TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_EVENT,
    &_TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_EVENT,
    &_TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_EVENT,
    &_TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_EVENT,
    &_TRACE_E1000E_IRQ_REARM_TIMER_EVENT,
    &_TRACE_E1000E_IRQ_THROTTLING_TIMER_EVENT,
    &_TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_EVENT,
    &_TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_EVENT,
    &_TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_EVENT,
    &_TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_EVENT,
    &_TRACE_E1000E_IRQ_EITR_SET_EVENT,
    &_TRACE_E1000E_IRQ_ITR_SET_EVENT,
    &_TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_EVENT,
    &_TRACE_E1000E_IRQ_ADDING_DELAYED_CAUSES_EVENT,
    &_TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_EVENT,
    &_TRACE_E1000E_WRN_MSIX_VEC_WRONG_EVENT,
    &_TRACE_E1000E_WRN_MSIX_INVALID_EVENT,
    &_TRACE_E1000E_MAC_SET_SW_EVENT,
    &_TRACE_E1000E_VM_STATE_RUNNING_EVENT,
    &_TRACE_E1000E_VM_STATE_STOPPED_EVENT,
    &_TRACE_E1000E_CB_PCI_REALIZE_EVENT,
    &_TRACE_E1000E_CB_PCI_UNINIT_EVENT,
    &_TRACE_E1000E_CB_QDEV_RESET_EVENT,
    &_TRACE_E1000E_CB_PRE_SAVE_EVENT,
    &_TRACE_E1000E_CB_POST_LOAD_EVENT,
    &_TRACE_E1000E_IO_WRITE_ADDR_EVENT,
    &_TRACE_E1000E_IO_WRITE_DATA_EVENT,
    &_TRACE_E1000E_IO_READ_ADDR_EVENT,
    &_TRACE_E1000E_IO_READ_DATA_EVENT,
    &_TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_EVENT,
    &_TRACE_E1000E_WRN_IO_READ_UNKNOWN_EVENT,
    &_TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_EVENT,
    &_TRACE_E1000E_WRN_IO_ADDR_FLASH_EVENT,
    &_TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_EVENT,
    &_TRACE_E1000E_MSI_INIT_FAIL_EVENT,
    &_TRACE_E1000E_MSIX_INIT_FAIL_EVENT,
    &_TRACE_E1000E_MSIX_USE_VECTOR_FAIL_EVENT,
    &_TRACE_E1000E_MAC_SET_PERMANENT_EVENT,
    &_TRACE_E1000E_CFG_SUPPORT_VIRTIO_EVENT,
    &_TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_EVENT,
    &_TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_EVENT,
    &_TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_EVENT,
    &_TRACE_SPAPR_VLAN_RECEIVE_EVENT,
    &_TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_EVENT,
    &_TRACE_SPAPR_VLAN_RECEIVE_WROTE_EVENT,
    &_TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_EVENT,
    &_TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_EVENT,
    &_TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_EVENT,
    &_TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_EVENT,
    &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_EVENT,
    &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_EVENT,
    &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_EVENT,
    &_TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_EVENT,
    &_TRACE_SUNGEM_TX_CHECKSUM_EVENT,
    &_TRACE_SUNGEM_TX_CHECKSUM_OOB_EVENT,
    &_TRACE_SUNGEM_TX_UNFINISHED_EVENT,
    &_TRACE_SUNGEM_TX_OVERFLOW_EVENT,
    &_TRACE_SUNGEM_TX_FINISHED_EVENT,
    &_TRACE_SUNGEM_TX_KICK_EVENT,
    &_TRACE_SUNGEM_TX_DISABLED_EVENT,
    &_TRACE_SUNGEM_TX_PROCESS_EVENT,
    &_TRACE_SUNGEM_TX_DESC_EVENT,
    &_TRACE_SUNGEM_TX_RESET_EVENT,
    &_TRACE_SUNGEM_RX_MAC_DISABLED_EVENT,
    &_TRACE_SUNGEM_RX_TXDMA_DISABLED_EVENT,
    &_TRACE_SUNGEM_RX_CHECK_EVENT,
    &_TRACE_SUNGEM_RX_MAC_CHECK_EVENT,
    &_TRACE_SUNGEM_RX_MAC_MULTICAST_EVENT,
    &_TRACE_SUNGEM_RX_MAC_COMPARE_EVENT,
    &_TRACE_SUNGEM_RX_PACKET_EVENT,
    &_TRACE_SUNGEM_RX_DISABLED_EVENT,
    &_TRACE_SUNGEM_RX_BAD_FRAME_SIZE_EVENT,
    &_TRACE_SUNGEM_RX_UNMATCHED_EVENT,
    &_TRACE_SUNGEM_RX_PROCESS_EVENT,
    &_TRACE_SUNGEM_RX_RINGFULL_EVENT,
    &_TRACE_SUNGEM_RX_DESC_EVENT,
    &_TRACE_SUNGEM_RX_RESET_EVENT,
    &_TRACE_SUNGEM_RX_KICK_EVENT,
    &_TRACE_SUNGEM_RESET_EVENT,
    &_TRACE_SUNGEM_MII_WRITE_EVENT,
    &_TRACE_SUNGEM_MII_READ_EVENT,
    &_TRACE_SUNGEM_MII_INVALID_SOF_EVENT,
    &_TRACE_SUNGEM_MII_INVALID_OP_EVENT,
    &_TRACE_SUNGEM_MMIO_GREG_WRITE_EVENT,
    &_TRACE_SUNGEM_MMIO_GREG_READ_EVENT,
    &_TRACE_SUNGEM_MMIO_TXDMA_WRITE_EVENT,
    &_TRACE_SUNGEM_MMIO_TXDMA_READ_EVENT,
    &_TRACE_SUNGEM_MMIO_RXDMA_WRITE_EVENT,
    &_TRACE_SUNGEM_MMIO_RXDMA_READ_EVENT,
    &_TRACE_SUNGEM_MMIO_MAC_WRITE_EVENT,
    &_TRACE_SUNGEM_MMIO_MAC_READ_EVENT,
    &_TRACE_SUNGEM_MMIO_MIF_WRITE_EVENT,
    &_TRACE_SUNGEM_MMIO_MIF_READ_EVENT,
    &_TRACE_SUNGEM_MMIO_PCS_WRITE_EVENT,
    &_TRACE_SUNGEM_MMIO_PCS_READ_EVENT,
    &_TRACE_SUNHME_SEB_WRITE_EVENT,
    &_TRACE_SUNHME_SEB_READ_EVENT,
    &_TRACE_SUNHME_ETX_WRITE_EVENT,
    &_TRACE_SUNHME_ETX_READ_EVENT,
    &_TRACE_SUNHME_ERX_WRITE_EVENT,
    &_TRACE_SUNHME_ERX_READ_EVENT,
    &_TRACE_SUNHME_MAC_WRITE_EVENT,
    &_TRACE_SUNHME_MAC_READ_EVENT,
    &_TRACE_SUNHME_MII_WRITE_EVENT,
    &_TRACE_SUNHME_MII_READ_EVENT,
    &_TRACE_SUNHME_MIF_WRITE_EVENT,
    &_TRACE_SUNHME_MIF_READ_EVENT,
    &_TRACE_SUNHME_TX_DESC_EVENT,
    &_TRACE_SUNHME_TX_XSUM_ADD_EVENT,
    &_TRACE_SUNHME_TX_XSUM_STUFF_EVENT,
    &_TRACE_SUNHME_TX_DONE_EVENT,
    &_TRACE_SUNHME_RX_INCOMING_EVENT,
    &_TRACE_SUNHME_RX_FILTER_DESTMAC_EVENT,
    &_TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_EVENT,
    &_TRACE_SUNHME_RX_FILTER_BCAST_MATCH_EVENT,
    &_TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_EVENT,
    &_TRACE_SUNHME_RX_FILTER_HASH_MATCH_EVENT,
    &_TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_EVENT,
    &_TRACE_SUNHME_RX_FILTER_REJECT_EVENT,
    &_TRACE_SUNHME_RX_FILTER_ACCEPT_EVENT,
    &_TRACE_SUNHME_RX_DESC_EVENT,
    &_TRACE_SUNHME_RX_XSUM_CALC_EVENT,
    &_TRACE_SUNHME_RX_NORXD_EVENT,
    &_TRACE_SUNHME_UPDATE_IRQ_EVENT,
    &_TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_EVENT,
    &_TRACE_VIRTIO_NET_ANNOUNCE_TIMER_EVENT,
    &_TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_EVENT,
    &_TRACE_VIRTIO_NET_POST_LOAD_DEVICE_EVENT,
    &_TRACE_VIRTIO_NET_RSS_DISABLE_EVENT,
    &_TRACE_VIRTIO_NET_RSS_ERROR_EVENT,
    &_TRACE_VIRTIO_NET_RSS_ENABLE_EVENT,
    &_TRACE_TULIP_REG_WRITE_EVENT,
    &_TRACE_TULIP_REG_READ_EVENT,
    &_TRACE_TULIP_RECEIVE_EVENT,
    &_TRACE_TULIP_DESCRIPTOR_EVENT,
    &_TRACE_TULIP_RX_STATE_EVENT,
    &_TRACE_TULIP_TX_STATE_EVENT,
    &_TRACE_TULIP_IRQ_EVENT,
    &_TRACE_TULIP_MII_WRITE_EVENT,
    &_TRACE_TULIP_MII_READ_EVENT,
    &_TRACE_TULIP_RESET_EVENT,
    &_TRACE_TULIP_SETUP_FRAME_EVENT,
    &_TRACE_TULIP_SETUP_FILTER_EVENT,
    &_TRACE_LASI_82596_MEM_READW_EVENT,
    &_TRACE_LASI_82596_MEM_WRITEW_EVENT,
    &_TRACE_I82596_S_RESET_EVENT,
    &_TRACE_I82596_TRANSMIT_EVENT,
    &_TRACE_I82596_RECEIVE_ANALYSIS_EVENT,
    &_TRACE_I82596_RECEIVE_PACKET_EVENT,
    &_TRACE_I82596_NEW_MAC_EVENT,
    &_TRACE_I82596_SET_MULTICAST_EVENT,
    &_TRACE_I82596_CHANNEL_ATTENTION_EVENT,
    &_TRACE_IMX_PHY_READ_EVENT,
    &_TRACE_IMX_PHY_READ_NUM_EVENT,
    &_TRACE_IMX_PHY_WRITE_EVENT,
    &_TRACE_IMX_PHY_WRITE_NUM_EVENT,
    &_TRACE_IMX_PHY_UPDATE_LINK_EVENT,
    &_TRACE_IMX_PHY_RESET_EVENT,
    &_TRACE_IMX_FEC_READ_BD_EVENT,
    &_TRACE_IMX_ENET_READ_BD_EVENT,
    &_TRACE_IMX_ETH_TX_BD_BUSY_EVENT,
    &_TRACE_IMX_ETH_RX_BD_FULL_EVENT,
    &_TRACE_IMX_ETH_READ_EVENT,
    &_TRACE_IMX_ETH_WRITE_EVENT,
    &_TRACE_IMX_FEC_RECEIVE_EVENT,
    &_TRACE_IMX_FEC_RECEIVE_LEN_EVENT,
    &_TRACE_IMX_FEC_RECEIVE_LAST_EVENT,
    &_TRACE_IMX_ENET_RECEIVE_EVENT,
    &_TRACE_IMX_ENET_RECEIVE_LEN_EVENT,
    &_TRACE_IMX_ENET_RECEIVE_LAST_EVENT,
    &_TRACE_NPCM7XX_EMC_RESET_EVENT,
    &_TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_EVENT,
    &_TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_EVENT,
    &_TRACE_NPCM7XX_EMC_SET_MISTA_EVENT,
    &_TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_EVENT,
    &_TRACE_NPCM7XX_EMC_SENT_PACKET_EVENT,
    &_TRACE_NPCM7XX_EMC_TX_DONE_EVENT,
    &_TRACE_NPCM7XX_EMC_CAN_RECEIVE_EVENT,
    &_TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_EVENT,
    &_TRACE_NPCM7XX_EMC_PACKET_DROPPED_EVENT,
    &_TRACE_NPCM7XX_EMC_RECEIVING_PACKET_EVENT,
    &_TRACE_NPCM7XX_EMC_RECEIVED_PACKET_EVENT,
    &_TRACE_NPCM7XX_EMC_RX_DONE_EVENT,
    &_TRACE_NPCM7XX_EMC_REG_READ_EVENT,
    &_TRACE_NPCM7XX_EMC_REG_WRITE_EVENT,
    &_TRACE_DP8393X_RAISE_IRQ_EVENT,
    &_TRACE_DP8393X_LOWER_IRQ_EVENT,
    &_TRACE_DP8393X_LOAD_CAM_EVENT,
    &_TRACE_DP8393X_LOAD_CAM_DONE_EVENT,
    &_TRACE_DP8393X_READ_RRA_REGS_EVENT,
    &_TRACE_DP8393X_TRANSMIT_PACKET_EVENT,
    &_TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_EVENT,
    &_TRACE_DP8393X_READ_EVENT,
    &_TRACE_DP8393X_WRITE_EVENT,
    &_TRACE_DP8393X_WRITE_INVALID_EVENT,
    &_TRACE_DP8393X_WRITE_INVALID_DCR_EVENT,
    &_TRACE_DP8393X_RECEIVE_OVERSIZE_EVENT,
    &_TRACE_DP8393X_RECEIVE_NOT_NETCARD_EVENT,
    &_TRACE_DP8393X_RECEIVE_PACKET_EVENT,
    &_TRACE_DP8393X_RECEIVE_WRITE_STATUS_EVENT,
  NULL,
};

static void trace_hw_net_register_events(void)
{
    trace_event_register_group(hw_net_trace_events);
}
trace_init(trace_hw_net_register_events)
