/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_arm.h"

uint16_t _TRACE_VIRT_ACPI_SETUP_DSTATE;
uint16_t _TRACE_SMMU_ADD_MR_DSTATE;
uint16_t _TRACE_SMMU_PTW_LEVEL_DSTATE;
uint16_t _TRACE_SMMU_PTW_INVALID_PTE_DSTATE;
uint16_t _TRACE_SMMU_PTW_PAGE_PTE_DSTATE;
uint16_t _TRACE_SMMU_PTW_BLOCK_PTE_DSTATE;
uint16_t _TRACE_SMMU_GET_PTE_DSTATE;
uint16_t _TRACE_SMMU_IOTLB_INV_ALL_DSTATE;
uint16_t _TRACE_SMMU_IOTLB_INV_ASID_DSTATE;
uint16_t _TRACE_SMMU_IOTLB_INV_IOVA_DSTATE;
uint16_t _TRACE_SMMU_INV_NOTIFIERS_MR_DSTATE;
uint16_t _TRACE_SMMU_IOTLB_LOOKUP_HIT_DSTATE;
uint16_t _TRACE_SMMU_IOTLB_LOOKUP_MISS_DSTATE;
uint16_t _TRACE_SMMU_IOTLB_INSERT_DSTATE;
uint16_t _TRACE_SMMUV3_READ_MMIO_DSTATE;
uint16_t _TRACE_SMMUV3_TRIGGER_IRQ_DSTATE;
uint16_t _TRACE_SMMUV3_WRITE_GERROR_DSTATE;
uint16_t _TRACE_SMMUV3_WRITE_GERRORN_DSTATE;
uint16_t _TRACE_SMMUV3_UNHANDLED_CMD_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_CONSUME_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_OPCODE_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_CONSUME_OUT_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_CONSUME_ERROR_DSTATE;
uint16_t _TRACE_SMMUV3_WRITE_MMIO_DSTATE;
uint16_t _TRACE_SMMUV3_RECORD_EVENT_DSTATE;
uint16_t _TRACE_SMMUV3_FIND_STE_DSTATE;
uint16_t _TRACE_SMMUV3_FIND_STE_2LVL_DSTATE;
uint16_t _TRACE_SMMUV3_GET_STE_DSTATE;
uint16_t _TRACE_SMMUV3_TRANSLATE_DISABLE_DSTATE;
uint16_t _TRACE_SMMUV3_TRANSLATE_BYPASS_DSTATE;
uint16_t _TRACE_SMMUV3_TRANSLATE_ABORT_DSTATE;
uint16_t _TRACE_SMMUV3_TRANSLATE_SUCCESS_DSTATE;
uint16_t _TRACE_SMMUV3_GET_CD_DSTATE;
uint16_t _TRACE_SMMUV3_DECODE_CD_DSTATE;
uint16_t _TRACE_SMMUV3_DECODE_CD_TT_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_CFGI_STE_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_CFGI_CD_DSTATE;
uint16_t _TRACE_SMMUV3_CONFIG_CACHE_HIT_DSTATE;
uint16_t _TRACE_SMMUV3_CONFIG_CACHE_MISS_DSTATE;
uint16_t _TRACE_SMMUV3_S1_RANGE_INVAL_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_TLBI_NH_DSTATE;
uint16_t _TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_DSTATE;
uint16_t _TRACE_SMMUV3_CONFIG_CACHE_INV_DSTATE;
uint16_t _TRACE_SMMUV3_NOTIFY_FLAG_ADD_DSTATE;
uint16_t _TRACE_SMMUV3_NOTIFY_FLAG_DEL_DSTATE;
uint16_t _TRACE_SMMUV3_INV_NOTIFIERS_IOVA_DSTATE;
TraceEvent _TRACE_VIRT_ACPI_SETUP_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "virt_acpi_setup",
    .sstate = TRACE_VIRT_ACPI_SETUP_ENABLED,
    .dstate = &_TRACE_VIRT_ACPI_SETUP_DSTATE 
};
TraceEvent _TRACE_SMMU_ADD_MR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_add_mr",
    .sstate = TRACE_SMMU_ADD_MR_ENABLED,
    .dstate = &_TRACE_SMMU_ADD_MR_DSTATE 
};
TraceEvent _TRACE_SMMU_PTW_LEVEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_ptw_level",
    .sstate = TRACE_SMMU_PTW_LEVEL_ENABLED,
    .dstate = &_TRACE_SMMU_PTW_LEVEL_DSTATE 
};
TraceEvent _TRACE_SMMU_PTW_INVALID_PTE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_ptw_invalid_pte",
    .sstate = TRACE_SMMU_PTW_INVALID_PTE_ENABLED,
    .dstate = &_TRACE_SMMU_PTW_INVALID_PTE_DSTATE 
};
TraceEvent _TRACE_SMMU_PTW_PAGE_PTE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_ptw_page_pte",
    .sstate = TRACE_SMMU_PTW_PAGE_PTE_ENABLED,
    .dstate = &_TRACE_SMMU_PTW_PAGE_PTE_DSTATE 
};
TraceEvent _TRACE_SMMU_PTW_BLOCK_PTE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_ptw_block_pte",
    .sstate = TRACE_SMMU_PTW_BLOCK_PTE_ENABLED,
    .dstate = &_TRACE_SMMU_PTW_BLOCK_PTE_DSTATE 
};
TraceEvent _TRACE_SMMU_GET_PTE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_get_pte",
    .sstate = TRACE_SMMU_GET_PTE_ENABLED,
    .dstate = &_TRACE_SMMU_GET_PTE_DSTATE 
};
TraceEvent _TRACE_SMMU_IOTLB_INV_ALL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_iotlb_inv_all",
    .sstate = TRACE_SMMU_IOTLB_INV_ALL_ENABLED,
    .dstate = &_TRACE_SMMU_IOTLB_INV_ALL_DSTATE 
};
TraceEvent _TRACE_SMMU_IOTLB_INV_ASID_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_iotlb_inv_asid",
    .sstate = TRACE_SMMU_IOTLB_INV_ASID_ENABLED,
    .dstate = &_TRACE_SMMU_IOTLB_INV_ASID_DSTATE 
};
TraceEvent _TRACE_SMMU_IOTLB_INV_IOVA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_iotlb_inv_iova",
    .sstate = TRACE_SMMU_IOTLB_INV_IOVA_ENABLED,
    .dstate = &_TRACE_SMMU_IOTLB_INV_IOVA_DSTATE 
};
TraceEvent _TRACE_SMMU_INV_NOTIFIERS_MR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_inv_notifiers_mr",
    .sstate = TRACE_SMMU_INV_NOTIFIERS_MR_ENABLED,
    .dstate = &_TRACE_SMMU_INV_NOTIFIERS_MR_DSTATE 
};
TraceEvent _TRACE_SMMU_IOTLB_LOOKUP_HIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_iotlb_lookup_hit",
    .sstate = TRACE_SMMU_IOTLB_LOOKUP_HIT_ENABLED,
    .dstate = &_TRACE_SMMU_IOTLB_LOOKUP_HIT_DSTATE 
};
TraceEvent _TRACE_SMMU_IOTLB_LOOKUP_MISS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_iotlb_lookup_miss",
    .sstate = TRACE_SMMU_IOTLB_LOOKUP_MISS_ENABLED,
    .dstate = &_TRACE_SMMU_IOTLB_LOOKUP_MISS_DSTATE 
};
TraceEvent _TRACE_SMMU_IOTLB_INSERT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmu_iotlb_insert",
    .sstate = TRACE_SMMU_IOTLB_INSERT_ENABLED,
    .dstate = &_TRACE_SMMU_IOTLB_INSERT_DSTATE 
};
TraceEvent _TRACE_SMMUV3_READ_MMIO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_read_mmio",
    .sstate = TRACE_SMMUV3_READ_MMIO_ENABLED,
    .dstate = &_TRACE_SMMUV3_READ_MMIO_DSTATE 
};
TraceEvent _TRACE_SMMUV3_TRIGGER_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_trigger_irq",
    .sstate = TRACE_SMMUV3_TRIGGER_IRQ_ENABLED,
    .dstate = &_TRACE_SMMUV3_TRIGGER_IRQ_DSTATE 
};
TraceEvent _TRACE_SMMUV3_WRITE_GERROR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_write_gerror",
    .sstate = TRACE_SMMUV3_WRITE_GERROR_ENABLED,
    .dstate = &_TRACE_SMMUV3_WRITE_GERROR_DSTATE 
};
TraceEvent _TRACE_SMMUV3_WRITE_GERRORN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_write_gerrorn",
    .sstate = TRACE_SMMUV3_WRITE_GERRORN_ENABLED,
    .dstate = &_TRACE_SMMUV3_WRITE_GERRORN_DSTATE 
};
TraceEvent _TRACE_SMMUV3_UNHANDLED_CMD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_unhandled_cmd",
    .sstate = TRACE_SMMUV3_UNHANDLED_CMD_ENABLED,
    .dstate = &_TRACE_SMMUV3_UNHANDLED_CMD_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_CONSUME_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_consume",
    .sstate = TRACE_SMMUV3_CMDQ_CONSUME_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_CONSUME_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_OPCODE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_opcode",
    .sstate = TRACE_SMMUV3_CMDQ_OPCODE_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_OPCODE_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_CONSUME_OUT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_consume_out",
    .sstate = TRACE_SMMUV3_CMDQ_CONSUME_OUT_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_CONSUME_OUT_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_CONSUME_ERROR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_consume_error",
    .sstate = TRACE_SMMUV3_CMDQ_CONSUME_ERROR_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_CONSUME_ERROR_DSTATE 
};
TraceEvent _TRACE_SMMUV3_WRITE_MMIO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_write_mmio",
    .sstate = TRACE_SMMUV3_WRITE_MMIO_ENABLED,
    .dstate = &_TRACE_SMMUV3_WRITE_MMIO_DSTATE 
};
TraceEvent _TRACE_SMMUV3_RECORD_EVENT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_record_event",
    .sstate = TRACE_SMMUV3_RECORD_EVENT_ENABLED,
    .dstate = &_TRACE_SMMUV3_RECORD_EVENT_DSTATE 
};
TraceEvent _TRACE_SMMUV3_FIND_STE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_find_ste",
    .sstate = TRACE_SMMUV3_FIND_STE_ENABLED,
    .dstate = &_TRACE_SMMUV3_FIND_STE_DSTATE 
};
TraceEvent _TRACE_SMMUV3_FIND_STE_2LVL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_find_ste_2lvl",
    .sstate = TRACE_SMMUV3_FIND_STE_2LVL_ENABLED,
    .dstate = &_TRACE_SMMUV3_FIND_STE_2LVL_DSTATE 
};
TraceEvent _TRACE_SMMUV3_GET_STE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_get_ste",
    .sstate = TRACE_SMMUV3_GET_STE_ENABLED,
    .dstate = &_TRACE_SMMUV3_GET_STE_DSTATE 
};
TraceEvent _TRACE_SMMUV3_TRANSLATE_DISABLE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_translate_disable",
    .sstate = TRACE_SMMUV3_TRANSLATE_DISABLE_ENABLED,
    .dstate = &_TRACE_SMMUV3_TRANSLATE_DISABLE_DSTATE 
};
TraceEvent _TRACE_SMMUV3_TRANSLATE_BYPASS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_translate_bypass",
    .sstate = TRACE_SMMUV3_TRANSLATE_BYPASS_ENABLED,
    .dstate = &_TRACE_SMMUV3_TRANSLATE_BYPASS_DSTATE 
};
TraceEvent _TRACE_SMMUV3_TRANSLATE_ABORT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_translate_abort",
    .sstate = TRACE_SMMUV3_TRANSLATE_ABORT_ENABLED,
    .dstate = &_TRACE_SMMUV3_TRANSLATE_ABORT_DSTATE 
};
TraceEvent _TRACE_SMMUV3_TRANSLATE_SUCCESS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_translate_success",
    .sstate = TRACE_SMMUV3_TRANSLATE_SUCCESS_ENABLED,
    .dstate = &_TRACE_SMMUV3_TRANSLATE_SUCCESS_DSTATE 
};
TraceEvent _TRACE_SMMUV3_GET_CD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_get_cd",
    .sstate = TRACE_SMMUV3_GET_CD_ENABLED,
    .dstate = &_TRACE_SMMUV3_GET_CD_DSTATE 
};
TraceEvent _TRACE_SMMUV3_DECODE_CD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_decode_cd",
    .sstate = TRACE_SMMUV3_DECODE_CD_ENABLED,
    .dstate = &_TRACE_SMMUV3_DECODE_CD_DSTATE 
};
TraceEvent _TRACE_SMMUV3_DECODE_CD_TT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_decode_cd_tt",
    .sstate = TRACE_SMMUV3_DECODE_CD_TT_ENABLED,
    .dstate = &_TRACE_SMMUV3_DECODE_CD_TT_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_CFGI_STE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_cfgi_ste",
    .sstate = TRACE_SMMUV3_CMDQ_CFGI_STE_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_CFGI_STE_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_cfgi_ste_range",
    .sstate = TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_CFGI_CD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_cfgi_cd",
    .sstate = TRACE_SMMUV3_CMDQ_CFGI_CD_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_CFGI_CD_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CONFIG_CACHE_HIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_config_cache_hit",
    .sstate = TRACE_SMMUV3_CONFIG_CACHE_HIT_ENABLED,
    .dstate = &_TRACE_SMMUV3_CONFIG_CACHE_HIT_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CONFIG_CACHE_MISS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_config_cache_miss",
    .sstate = TRACE_SMMUV3_CONFIG_CACHE_MISS_ENABLED,
    .dstate = &_TRACE_SMMUV3_CONFIG_CACHE_MISS_DSTATE 
};
TraceEvent _TRACE_SMMUV3_S1_RANGE_INVAL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_s1_range_inval",
    .sstate = TRACE_SMMUV3_S1_RANGE_INVAL_ENABLED,
    .dstate = &_TRACE_SMMUV3_S1_RANGE_INVAL_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_TLBI_NH_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_tlbi_nh",
    .sstate = TRACE_SMMUV3_CMDQ_TLBI_NH_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_TLBI_NH_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_cmdq_tlbi_nh_asid",
    .sstate = TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_ENABLED,
    .dstate = &_TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_DSTATE 
};
TraceEvent _TRACE_SMMUV3_CONFIG_CACHE_INV_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_config_cache_inv",
    .sstate = TRACE_SMMUV3_CONFIG_CACHE_INV_ENABLED,
    .dstate = &_TRACE_SMMUV3_CONFIG_CACHE_INV_DSTATE 
};
TraceEvent _TRACE_SMMUV3_NOTIFY_FLAG_ADD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_notify_flag_add",
    .sstate = TRACE_SMMUV3_NOTIFY_FLAG_ADD_ENABLED,
    .dstate = &_TRACE_SMMUV3_NOTIFY_FLAG_ADD_DSTATE 
};
TraceEvent _TRACE_SMMUV3_NOTIFY_FLAG_DEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_notify_flag_del",
    .sstate = TRACE_SMMUV3_NOTIFY_FLAG_DEL_ENABLED,
    .dstate = &_TRACE_SMMUV3_NOTIFY_FLAG_DEL_DSTATE 
};
TraceEvent _TRACE_SMMUV3_INV_NOTIFIERS_IOVA_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "smmuv3_inv_notifiers_iova",
    .sstate = TRACE_SMMUV3_INV_NOTIFIERS_IOVA_ENABLED,
    .dstate = &_TRACE_SMMUV3_INV_NOTIFIERS_IOVA_DSTATE 
};
TraceEvent *hw_arm_trace_events[] = {
    &_TRACE_VIRT_ACPI_SETUP_EVENT,
    &_TRACE_SMMU_ADD_MR_EVENT,
    &_TRACE_SMMU_PTW_LEVEL_EVENT,
    &_TRACE_SMMU_PTW_INVALID_PTE_EVENT,
    &_TRACE_SMMU_PTW_PAGE_PTE_EVENT,
    &_TRACE_SMMU_PTW_BLOCK_PTE_EVENT,
    &_TRACE_SMMU_GET_PTE_EVENT,
    &_TRACE_SMMU_IOTLB_INV_ALL_EVENT,
    &_TRACE_SMMU_IOTLB_INV_ASID_EVENT,
    &_TRACE_SMMU_IOTLB_INV_IOVA_EVENT,
    &_TRACE_SMMU_INV_NOTIFIERS_MR_EVENT,
    &_TRACE_SMMU_IOTLB_LOOKUP_HIT_EVENT,
    &_TRACE_SMMU_IOTLB_LOOKUP_MISS_EVENT,
    &_TRACE_SMMU_IOTLB_INSERT_EVENT,
    &_TRACE_SMMUV3_READ_MMIO_EVENT,
    &_TRACE_SMMUV3_TRIGGER_IRQ_EVENT,
    &_TRACE_SMMUV3_WRITE_GERROR_EVENT,
    &_TRACE_SMMUV3_WRITE_GERRORN_EVENT,
    &_TRACE_SMMUV3_UNHANDLED_CMD_EVENT,
    &_TRACE_SMMUV3_CMDQ_CONSUME_EVENT,
    &_TRACE_SMMUV3_CMDQ_OPCODE_EVENT,
    &_TRACE_SMMUV3_CMDQ_CONSUME_OUT_EVENT,
    &_TRACE_SMMUV3_CMDQ_CONSUME_ERROR_EVENT,
    &_TRACE_SMMUV3_WRITE_MMIO_EVENT,
    &_TRACE_SMMUV3_RECORD_EVENT_EVENT,
    &_TRACE_SMMUV3_FIND_STE_EVENT,
    &_TRACE_SMMUV3_FIND_STE_2LVL_EVENT,
    &_TRACE_SMMUV3_GET_STE_EVENT,
    &_TRACE_SMMUV3_TRANSLATE_DISABLE_EVENT,
    &_TRACE_SMMUV3_TRANSLATE_BYPASS_EVENT,
    &_TRACE_SMMUV3_TRANSLATE_ABORT_EVENT,
    &_TRACE_SMMUV3_TRANSLATE_SUCCESS_EVENT,
    &_TRACE_SMMUV3_GET_CD_EVENT,
    &_TRACE_SMMUV3_DECODE_CD_EVENT,
    &_TRACE_SMMUV3_DECODE_CD_TT_EVENT,
    &_TRACE_SMMUV3_CMDQ_CFGI_STE_EVENT,
    &_TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_EVENT,
    &_TRACE_SMMUV3_CMDQ_CFGI_CD_EVENT,
    &_TRACE_SMMUV3_CONFIG_CACHE_HIT_EVENT,
    &_TRACE_SMMUV3_CONFIG_CACHE_MISS_EVENT,
    &_TRACE_SMMUV3_S1_RANGE_INVAL_EVENT,
    &_TRACE_SMMUV3_CMDQ_TLBI_NH_EVENT,
    &_TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_EVENT,
    &_TRACE_SMMUV3_CONFIG_CACHE_INV_EVENT,
    &_TRACE_SMMUV3_NOTIFY_FLAG_ADD_EVENT,
    &_TRACE_SMMUV3_NOTIFY_FLAG_DEL_EVENT,
    &_TRACE_SMMUV3_INV_NOTIFIERS_IOVA_EVENT,
  NULL,
};

static void trace_hw_arm_register_events(void)
{
    trace_event_register_group(hw_arm_trace_events);
}
trace_init(trace_hw_arm_register_events)
