/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_intc.h"

uint16_t _TRACE_PIC_UPDATE_IRQ_DSTATE;
uint16_t _TRACE_PIC_SET_IRQ_DSTATE;
uint16_t _TRACE_PIC_INTERRUPT_DSTATE;
uint16_t _TRACE_PIC_IOPORT_WRITE_DSTATE;
uint16_t _TRACE_PIC_IOPORT_READ_DSTATE;
uint16_t _TRACE_CPU_SET_APIC_BASE_DSTATE;
uint16_t _TRACE_CPU_GET_APIC_BASE_DSTATE;
uint16_t _TRACE_APIC_REPORT_IRQ_DELIVERED_DSTATE;
uint16_t _TRACE_APIC_RESET_IRQ_DELIVERED_DSTATE;
uint16_t _TRACE_APIC_GET_IRQ_DELIVERED_DSTATE;
uint16_t _TRACE_APIC_LOCAL_DELIVER_DSTATE;
uint16_t _TRACE_APIC_DELIVER_IRQ_DSTATE;
uint16_t _TRACE_APIC_MEM_READL_DSTATE;
uint16_t _TRACE_APIC_MEM_WRITEL_DSTATE;
uint16_t _TRACE_IOAPIC_SET_REMOTE_IRR_DSTATE;
uint16_t _TRACE_IOAPIC_CLEAR_REMOTE_IRR_DSTATE;
uint16_t _TRACE_IOAPIC_EOI_BROADCAST_DSTATE;
uint16_t _TRACE_IOAPIC_EOI_DELAYED_REASSERT_DSTATE;
uint16_t _TRACE_IOAPIC_MEM_READ_DSTATE;
uint16_t _TRACE_IOAPIC_MEM_WRITE_DSTATE;
uint16_t _TRACE_IOAPIC_SET_IRQ_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTL_MEM_READL_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTLM_MEM_READL_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_DSTATE;
uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_DSTATE;
uint16_t _TRACE_SLAVIO_CHECK_INTERRUPTS_DSTATE;
uint16_t _TRACE_SLAVIO_SET_IRQ_DSTATE;
uint16_t _TRACE_SLAVIO_SET_TIMER_IRQ_CPU_DSTATE;
uint16_t _TRACE_GRLIB_IRQMP_CHECK_IRQS_DSTATE;
uint16_t _TRACE_GRLIB_IRQMP_ACK_DSTATE;
uint16_t _TRACE_GRLIB_IRQMP_SET_IRQ_DSTATE;
uint16_t _TRACE_GRLIB_IRQMP_READL_UNKNOWN_DSTATE;
uint16_t _TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_DSTATE;
uint16_t _TRACE_XICS_ICP_CHECK_IPI_DSTATE;
uint16_t _TRACE_XICS_ICP_ACCEPT_DSTATE;
uint16_t _TRACE_XICS_ICP_EOI_DSTATE;
uint16_t _TRACE_XICS_ICP_IRQ_DSTATE;
uint16_t _TRACE_XICS_ICP_RAISE_DSTATE;
uint16_t _TRACE_XICS_ICS_SET_IRQ_MSI_DSTATE;
uint16_t _TRACE_XICS_MASKED_PENDING_DSTATE;
uint16_t _TRACE_XICS_ICS_SET_IRQ_LSI_DSTATE;
uint16_t _TRACE_XICS_ICS_WRITE_XIVE_DSTATE;
uint16_t _TRACE_XICS_ICS_REJECT_DSTATE;
uint16_t _TRACE_XICS_ICS_EOI_DSTATE;
uint16_t _TRACE_FLIC_CREATE_DEVICE_DSTATE;
uint16_t _TRACE_FLIC_RESET_FAILED_DSTATE;
uint16_t _TRACE_QEMU_S390_AIRQ_SUPPRESSED_DSTATE;
uint16_t _TRACE_QEMU_S390_SUPPRESS_AIRQ_DSTATE;
uint16_t _TRACE_ASPEED_VIC_SET_IRQ_DSTATE;
uint16_t _TRACE_ASPEED_VIC_UPDATE_FIQ_DSTATE;
uint16_t _TRACE_ASPEED_VIC_UPDATE_IRQ_DSTATE;
uint16_t _TRACE_ASPEED_VIC_READ_DSTATE;
uint16_t _TRACE_ASPEED_VIC_WRITE_DSTATE;
uint16_t _TRACE_GIC_ENABLE_IRQ_DSTATE;
uint16_t _TRACE_GIC_DISABLE_IRQ_DSTATE;
uint16_t _TRACE_GIC_SET_IRQ_DSTATE;
uint16_t _TRACE_GIC_UPDATE_BESTIRQ_DSTATE;
uint16_t _TRACE_GIC_UPDATE_SET_IRQ_DSTATE;
uint16_t _TRACE_GIC_ACKNOWLEDGE_IRQ_DSTATE;
uint16_t _TRACE_GIC_CPU_WRITE_DSTATE;
uint16_t _TRACE_GIC_CPU_READ_DSTATE;
uint16_t _TRACE_GIC_HYP_READ_DSTATE;
uint16_t _TRACE_GIC_HYP_WRITE_DSTATE;
uint16_t _TRACE_GIC_DIST_READ_DSTATE;
uint16_t _TRACE_GIC_DIST_WRITE_DSTATE;
uint16_t _TRACE_GIC_LR_ENTRY_DSTATE;
uint16_t _TRACE_GIC_UPDATE_MAINTENANCE_IRQ_DSTATE;
uint16_t _TRACE_GICV3_ICC_PMR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_PMR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_BPR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_BPR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_AP_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_AP_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_IGRPEN_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_IGRPEN_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_IGRPEN1_EL3_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_CTLR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_CTLR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_CTLR_EL3_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_CTLR_EL3_WRITE_DSTATE;
uint16_t _TRACE_GICV3_CPUIF_UPDATE_DSTATE;
uint16_t _TRACE_GICV3_CPUIF_SET_IRQS_DSTATE;
uint16_t _TRACE_GICV3_ICC_GENERATE_SGI_DSTATE;
uint16_t _TRACE_GICV3_ICC_IAR0_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_IAR1_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_EOIR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_HPPIR0_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_HPPIR1_READ_DSTATE;
uint16_t _TRACE_GICV3_ICC_DIR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICC_RPR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_AP_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_AP_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICH_HCR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_HCR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICH_VMCR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_VMCR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICH_LR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_LR32_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_LRC_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_LR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICH_LR32_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICH_LRC_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICH_VTR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_MISR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_EISR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICH_ELRSR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_AP_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_AP_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICV_BPR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_BPR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICV_PMR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_PMR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICV_IGRPEN_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_IGRPEN_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICV_CTLR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_CTLR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICV_RPR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_HPPIR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_DIR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ICV_IAR_READ_DSTATE;
uint16_t _TRACE_GICV3_ICV_EOIR_WRITE_DSTATE;
uint16_t _TRACE_GICV3_CPUIF_VIRT_UPDATE_DSTATE;
uint16_t _TRACE_GICV3_CPUIF_VIRT_SET_IRQS_DSTATE;
uint16_t _TRACE_GICV3_DIST_READ_DSTATE;
uint16_t _TRACE_GICV3_DIST_BADREAD_DSTATE;
uint16_t _TRACE_GICV3_DIST_WRITE_DSTATE;
uint16_t _TRACE_GICV3_DIST_BADWRITE_DSTATE;
uint16_t _TRACE_GICV3_DIST_SET_IRQ_DSTATE;
uint16_t _TRACE_GICV3_REDIST_READ_DSTATE;
uint16_t _TRACE_GICV3_REDIST_BADREAD_DSTATE;
uint16_t _TRACE_GICV3_REDIST_WRITE_DSTATE;
uint16_t _TRACE_GICV3_REDIST_BADWRITE_DSTATE;
uint16_t _TRACE_GICV3_REDIST_SET_IRQ_DSTATE;
uint16_t _TRACE_GICV3_REDIST_SEND_SGI_DSTATE;
uint16_t _TRACE_GICV3_ITS_READ_DSTATE;
uint16_t _TRACE_GICV3_ITS_BADREAD_DSTATE;
uint16_t _TRACE_GICV3_ITS_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ITS_BADWRITE_DSTATE;
uint16_t _TRACE_GICV3_ITS_TRANSLATION_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ITS_PROCESS_COMMAND_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_INT_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_CLEAR_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_DISCARD_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_SYNC_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_MAPD_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_MAPC_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_MAPI_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_MAPTI_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_INV_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_MOVALL_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_MOVI_DSTATE;
uint16_t _TRACE_GICV3_ITS_CMD_UNKNOWN_DSTATE;
uint16_t _TRACE_GICV3_ITS_CTE_READ_DSTATE;
uint16_t _TRACE_GICV3_ITS_CTE_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ITS_CTE_READ_FAULT_DSTATE;
uint16_t _TRACE_GICV3_ITS_ITE_READ_DSTATE;
uint16_t _TRACE_GICV3_ITS_ITE_READ_FAULT_DSTATE;
uint16_t _TRACE_GICV3_ITS_ITE_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ITS_DTE_READ_DSTATE;
uint16_t _TRACE_GICV3_ITS_DTE_WRITE_DSTATE;
uint16_t _TRACE_GICV3_ITS_DTE_READ_FAULT_DSTATE;
uint16_t _TRACE_NVIC_RECOMPUTE_STATE_DSTATE;
uint16_t _TRACE_NVIC_RECOMPUTE_STATE_SECURE_DSTATE;
uint16_t _TRACE_NVIC_SET_PRIO_DSTATE;
uint16_t _TRACE_NVIC_IRQ_UPDATE_DSTATE;
uint16_t _TRACE_NVIC_ESCALATE_PRIO_DSTATE;
uint16_t _TRACE_NVIC_ESCALATE_DISABLED_DSTATE;
uint16_t _TRACE_NVIC_SET_PENDING_DSTATE;
uint16_t _TRACE_NVIC_CLEAR_PENDING_DSTATE;
uint16_t _TRACE_NVIC_ACKNOWLEDGE_IRQ_DSTATE;
uint16_t _TRACE_NVIC_GET_PENDING_IRQ_INFO_DSTATE;
uint16_t _TRACE_NVIC_COMPLETE_IRQ_DSTATE;
uint16_t _TRACE_NVIC_SET_IRQ_LEVEL_DSTATE;
uint16_t _TRACE_NVIC_SET_NMI_LEVEL_DSTATE;
uint16_t _TRACE_NVIC_SYSREG_READ_DSTATE;
uint16_t _TRACE_NVIC_SYSREG_WRITE_DSTATE;
uint16_t _TRACE_HEATHROW_WRITE_DSTATE;
uint16_t _TRACE_HEATHROW_READ_DSTATE;
uint16_t _TRACE_HEATHROW_SET_IRQ_DSTATE;
uint16_t _TRACE_BCM2835_IC_SET_GPU_IRQ_DSTATE;
uint16_t _TRACE_BCM2835_IC_SET_CPU_IRQ_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_CLAIM_IRQ_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_FREE_IRQ_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_SET_IRQ_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_GET_SOURCE_INFO_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_GET_QUEUE_INFO_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_ESB_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_SYNC_DSTATE;
uint16_t _TRACE_SPAPR_XIVE_RESET_DSTATE;
uint16_t _TRACE_KVM_XIVE_CPU_CONNECT_DSTATE;
uint16_t _TRACE_KVM_XIVE_SOURCE_RESET_DSTATE;
uint16_t _TRACE_XIVE_TCTX_ACCEPT_DSTATE;
uint16_t _TRACE_XIVE_TCTX_NOTIFY_DSTATE;
uint16_t _TRACE_XIVE_TCTX_SET_CPPR_DSTATE;
uint16_t _TRACE_XIVE_SOURCE_ESB_READ_DSTATE;
uint16_t _TRACE_XIVE_SOURCE_ESB_WRITE_DSTATE;
uint16_t _TRACE_XIVE_ROUTER_END_NOTIFY_DSTATE;
uint16_t _TRACE_XIVE_ROUTER_END_ESCALATE_DSTATE;
uint16_t _TRACE_XIVE_TCTX_TM_WRITE_DSTATE;
uint16_t _TRACE_XIVE_TCTX_TM_READ_DSTATE;
uint16_t _TRACE_XIVE_PRESENTER_NOTIFY_DSTATE;
uint16_t _TRACE_XIVE_END_SOURCE_READ_DSTATE;
uint16_t _TRACE_PNV_XIVE_IC_HW_TRIGGER_DSTATE;
uint16_t _TRACE_GOLDFISH_IRQ_REQUEST_DSTATE;
uint16_t _TRACE_GOLDFISH_PIC_READ_DSTATE;
uint16_t _TRACE_GOLDFISH_PIC_WRITE_DSTATE;
uint16_t _TRACE_GOLDFISH_PIC_RESET_DSTATE;
uint16_t _TRACE_GOLDFISH_PIC_REALIZE_DSTATE;
uint16_t _TRACE_GOLDFISH_PIC_INSTANCE_INIT_DSTATE;
uint16_t _TRACE_SH_INTC_SOURCES_DSTATE;
uint16_t _TRACE_SH_INTC_PENDING_DSTATE;
uint16_t _TRACE_SH_INTC_REGISTER_DSTATE;
uint16_t _TRACE_SH_INTC_READ_DSTATE;
uint16_t _TRACE_SH_INTC_WRITE_DSTATE;
uint16_t _TRACE_SH_INTC_SET_DSTATE;
TraceEvent _TRACE_PIC_UPDATE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pic_update_irq",
    .sstate = TRACE_PIC_UPDATE_IRQ_ENABLED,
    .dstate = &_TRACE_PIC_UPDATE_IRQ_DSTATE 
};
TraceEvent _TRACE_PIC_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pic_set_irq",
    .sstate = TRACE_PIC_SET_IRQ_ENABLED,
    .dstate = &_TRACE_PIC_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_PIC_INTERRUPT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pic_interrupt",
    .sstate = TRACE_PIC_INTERRUPT_ENABLED,
    .dstate = &_TRACE_PIC_INTERRUPT_DSTATE 
};
TraceEvent _TRACE_PIC_IOPORT_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pic_ioport_write",
    .sstate = TRACE_PIC_IOPORT_WRITE_ENABLED,
    .dstate = &_TRACE_PIC_IOPORT_WRITE_DSTATE 
};
TraceEvent _TRACE_PIC_IOPORT_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pic_ioport_read",
    .sstate = TRACE_PIC_IOPORT_READ_ENABLED,
    .dstate = &_TRACE_PIC_IOPORT_READ_DSTATE 
};
TraceEvent _TRACE_CPU_SET_APIC_BASE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "cpu_set_apic_base",
    .sstate = TRACE_CPU_SET_APIC_BASE_ENABLED,
    .dstate = &_TRACE_CPU_SET_APIC_BASE_DSTATE 
};
TraceEvent _TRACE_CPU_GET_APIC_BASE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "cpu_get_apic_base",
    .sstate = TRACE_CPU_GET_APIC_BASE_ENABLED,
    .dstate = &_TRACE_CPU_GET_APIC_BASE_DSTATE 
};
TraceEvent _TRACE_APIC_REPORT_IRQ_DELIVERED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "apic_report_irq_delivered",
    .sstate = TRACE_APIC_REPORT_IRQ_DELIVERED_ENABLED,
    .dstate = &_TRACE_APIC_REPORT_IRQ_DELIVERED_DSTATE 
};
TraceEvent _TRACE_APIC_RESET_IRQ_DELIVERED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "apic_reset_irq_delivered",
    .sstate = TRACE_APIC_RESET_IRQ_DELIVERED_ENABLED,
    .dstate = &_TRACE_APIC_RESET_IRQ_DELIVERED_DSTATE 
};
TraceEvent _TRACE_APIC_GET_IRQ_DELIVERED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "apic_get_irq_delivered",
    .sstate = TRACE_APIC_GET_IRQ_DELIVERED_ENABLED,
    .dstate = &_TRACE_APIC_GET_IRQ_DELIVERED_DSTATE 
};
TraceEvent _TRACE_APIC_LOCAL_DELIVER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "apic_local_deliver",
    .sstate = TRACE_APIC_LOCAL_DELIVER_ENABLED,
    .dstate = &_TRACE_APIC_LOCAL_DELIVER_DSTATE 
};
TraceEvent _TRACE_APIC_DELIVER_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "apic_deliver_irq",
    .sstate = TRACE_APIC_DELIVER_IRQ_ENABLED,
    .dstate = &_TRACE_APIC_DELIVER_IRQ_DSTATE 
};
TraceEvent _TRACE_APIC_MEM_READL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "apic_mem_readl",
    .sstate = TRACE_APIC_MEM_READL_ENABLED,
    .dstate = &_TRACE_APIC_MEM_READL_DSTATE 
};
TraceEvent _TRACE_APIC_MEM_WRITEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "apic_mem_writel",
    .sstate = TRACE_APIC_MEM_WRITEL_ENABLED,
    .dstate = &_TRACE_APIC_MEM_WRITEL_DSTATE 
};
TraceEvent _TRACE_IOAPIC_SET_REMOTE_IRR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ioapic_set_remote_irr",
    .sstate = TRACE_IOAPIC_SET_REMOTE_IRR_ENABLED,
    .dstate = &_TRACE_IOAPIC_SET_REMOTE_IRR_DSTATE 
};
TraceEvent _TRACE_IOAPIC_CLEAR_REMOTE_IRR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ioapic_clear_remote_irr",
    .sstate = TRACE_IOAPIC_CLEAR_REMOTE_IRR_ENABLED,
    .dstate = &_TRACE_IOAPIC_CLEAR_REMOTE_IRR_DSTATE 
};
TraceEvent _TRACE_IOAPIC_EOI_BROADCAST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ioapic_eoi_broadcast",
    .sstate = TRACE_IOAPIC_EOI_BROADCAST_ENABLED,
    .dstate = &_TRACE_IOAPIC_EOI_BROADCAST_DSTATE 
};
TraceEvent _TRACE_IOAPIC_EOI_DELAYED_REASSERT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ioapic_eoi_delayed_reassert",
    .sstate = TRACE_IOAPIC_EOI_DELAYED_REASSERT_ENABLED,
    .dstate = &_TRACE_IOAPIC_EOI_DELAYED_REASSERT_DSTATE 
};
TraceEvent _TRACE_IOAPIC_MEM_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ioapic_mem_read",
    .sstate = TRACE_IOAPIC_MEM_READ_ENABLED,
    .dstate = &_TRACE_IOAPIC_MEM_READ_DSTATE 
};
TraceEvent _TRACE_IOAPIC_MEM_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ioapic_mem_write",
    .sstate = TRACE_IOAPIC_MEM_WRITE_ENABLED,
    .dstate = &_TRACE_IOAPIC_MEM_WRITE_DSTATE 
};
TraceEvent _TRACE_IOAPIC_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "ioapic_set_irq",
    .sstate = TRACE_IOAPIC_SET_IRQ_ENABLED,
    .dstate = &_TRACE_IOAPIC_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTL_MEM_READL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctl_mem_readl",
    .sstate = TRACE_SLAVIO_INTCTL_MEM_READL_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTL_MEM_READL_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctl_mem_writel",
    .sstate = TRACE_SLAVIO_INTCTL_MEM_WRITEL_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTL_MEM_WRITEL_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctl_mem_writel_clear",
    .sstate = TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctl_mem_writel_set",
    .sstate = TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_READL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctlm_mem_readl",
    .sstate = TRACE_SLAVIO_INTCTLM_MEM_READL_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTLM_MEM_READL_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctlm_mem_writel",
    .sstate = TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctlm_mem_writel_enable",
    .sstate = TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctlm_mem_writel_disable",
    .sstate = TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_DSTATE 
};
TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_intctlm_mem_writel_target",
    .sstate = TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_ENABLED,
    .dstate = &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_DSTATE 
};
TraceEvent _TRACE_SLAVIO_CHECK_INTERRUPTS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_check_interrupts",
    .sstate = TRACE_SLAVIO_CHECK_INTERRUPTS_ENABLED,
    .dstate = &_TRACE_SLAVIO_CHECK_INTERRUPTS_DSTATE 
};
TraceEvent _TRACE_SLAVIO_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_set_irq",
    .sstate = TRACE_SLAVIO_SET_IRQ_ENABLED,
    .dstate = &_TRACE_SLAVIO_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_SLAVIO_SET_TIMER_IRQ_CPU_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "slavio_set_timer_irq_cpu",
    .sstate = TRACE_SLAVIO_SET_TIMER_IRQ_CPU_ENABLED,
    .dstate = &_TRACE_SLAVIO_SET_TIMER_IRQ_CPU_DSTATE 
};
TraceEvent _TRACE_GRLIB_IRQMP_CHECK_IRQS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "grlib_irqmp_check_irqs",
    .sstate = TRACE_GRLIB_IRQMP_CHECK_IRQS_ENABLED,
    .dstate = &_TRACE_GRLIB_IRQMP_CHECK_IRQS_DSTATE 
};
TraceEvent _TRACE_GRLIB_IRQMP_ACK_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "grlib_irqmp_ack",
    .sstate = TRACE_GRLIB_IRQMP_ACK_ENABLED,
    .dstate = &_TRACE_GRLIB_IRQMP_ACK_DSTATE 
};
TraceEvent _TRACE_GRLIB_IRQMP_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "grlib_irqmp_set_irq",
    .sstate = TRACE_GRLIB_IRQMP_SET_IRQ_ENABLED,
    .dstate = &_TRACE_GRLIB_IRQMP_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_GRLIB_IRQMP_READL_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "grlib_irqmp_readl_unknown",
    .sstate = TRACE_GRLIB_IRQMP_READL_UNKNOWN_ENABLED,
    .dstate = &_TRACE_GRLIB_IRQMP_READL_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "grlib_irqmp_writel_unknown",
    .sstate = TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_ENABLED,
    .dstate = &_TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_XICS_ICP_CHECK_IPI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_icp_check_ipi",
    .sstate = TRACE_XICS_ICP_CHECK_IPI_ENABLED,
    .dstate = &_TRACE_XICS_ICP_CHECK_IPI_DSTATE 
};
TraceEvent _TRACE_XICS_ICP_ACCEPT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_icp_accept",
    .sstate = TRACE_XICS_ICP_ACCEPT_ENABLED,
    .dstate = &_TRACE_XICS_ICP_ACCEPT_DSTATE 
};
TraceEvent _TRACE_XICS_ICP_EOI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_icp_eoi",
    .sstate = TRACE_XICS_ICP_EOI_ENABLED,
    .dstate = &_TRACE_XICS_ICP_EOI_DSTATE 
};
TraceEvent _TRACE_XICS_ICP_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_icp_irq",
    .sstate = TRACE_XICS_ICP_IRQ_ENABLED,
    .dstate = &_TRACE_XICS_ICP_IRQ_DSTATE 
};
TraceEvent _TRACE_XICS_ICP_RAISE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_icp_raise",
    .sstate = TRACE_XICS_ICP_RAISE_ENABLED,
    .dstate = &_TRACE_XICS_ICP_RAISE_DSTATE 
};
TraceEvent _TRACE_XICS_ICS_SET_IRQ_MSI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_ics_set_irq_msi",
    .sstate = TRACE_XICS_ICS_SET_IRQ_MSI_ENABLED,
    .dstate = &_TRACE_XICS_ICS_SET_IRQ_MSI_DSTATE 
};
TraceEvent _TRACE_XICS_MASKED_PENDING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_masked_pending",
    .sstate = TRACE_XICS_MASKED_PENDING_ENABLED,
    .dstate = &_TRACE_XICS_MASKED_PENDING_DSTATE 
};
TraceEvent _TRACE_XICS_ICS_SET_IRQ_LSI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_ics_set_irq_lsi",
    .sstate = TRACE_XICS_ICS_SET_IRQ_LSI_ENABLED,
    .dstate = &_TRACE_XICS_ICS_SET_IRQ_LSI_DSTATE 
};
TraceEvent _TRACE_XICS_ICS_WRITE_XIVE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_ics_write_xive",
    .sstate = TRACE_XICS_ICS_WRITE_XIVE_ENABLED,
    .dstate = &_TRACE_XICS_ICS_WRITE_XIVE_DSTATE 
};
TraceEvent _TRACE_XICS_ICS_REJECT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_ics_reject",
    .sstate = TRACE_XICS_ICS_REJECT_ENABLED,
    .dstate = &_TRACE_XICS_ICS_REJECT_DSTATE 
};
TraceEvent _TRACE_XICS_ICS_EOI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xics_ics_eoi",
    .sstate = TRACE_XICS_ICS_EOI_ENABLED,
    .dstate = &_TRACE_XICS_ICS_EOI_DSTATE 
};
TraceEvent _TRACE_FLIC_CREATE_DEVICE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "flic_create_device",
    .sstate = TRACE_FLIC_CREATE_DEVICE_ENABLED,
    .dstate = &_TRACE_FLIC_CREATE_DEVICE_DSTATE 
};
TraceEvent _TRACE_FLIC_RESET_FAILED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "flic_reset_failed",
    .sstate = TRACE_FLIC_RESET_FAILED_ENABLED,
    .dstate = &_TRACE_FLIC_RESET_FAILED_DSTATE 
};
TraceEvent _TRACE_QEMU_S390_AIRQ_SUPPRESSED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qemu_s390_airq_suppressed",
    .sstate = TRACE_QEMU_S390_AIRQ_SUPPRESSED_ENABLED,
    .dstate = &_TRACE_QEMU_S390_AIRQ_SUPPRESSED_DSTATE 
};
TraceEvent _TRACE_QEMU_S390_SUPPRESS_AIRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "qemu_s390_suppress_airq",
    .sstate = TRACE_QEMU_S390_SUPPRESS_AIRQ_ENABLED,
    .dstate = &_TRACE_QEMU_S390_SUPPRESS_AIRQ_DSTATE 
};
TraceEvent _TRACE_ASPEED_VIC_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "aspeed_vic_set_irq",
    .sstate = TRACE_ASPEED_VIC_SET_IRQ_ENABLED,
    .dstate = &_TRACE_ASPEED_VIC_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_ASPEED_VIC_UPDATE_FIQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "aspeed_vic_update_fiq",
    .sstate = TRACE_ASPEED_VIC_UPDATE_FIQ_ENABLED,
    .dstate = &_TRACE_ASPEED_VIC_UPDATE_FIQ_DSTATE 
};
TraceEvent _TRACE_ASPEED_VIC_UPDATE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "aspeed_vic_update_irq",
    .sstate = TRACE_ASPEED_VIC_UPDATE_IRQ_ENABLED,
    .dstate = &_TRACE_ASPEED_VIC_UPDATE_IRQ_DSTATE 
};
TraceEvent _TRACE_ASPEED_VIC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "aspeed_vic_read",
    .sstate = TRACE_ASPEED_VIC_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_VIC_READ_DSTATE 
};
TraceEvent _TRACE_ASPEED_VIC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "aspeed_vic_write",
    .sstate = TRACE_ASPEED_VIC_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_VIC_WRITE_DSTATE 
};
TraceEvent _TRACE_GIC_ENABLE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_enable_irq",
    .sstate = TRACE_GIC_ENABLE_IRQ_ENABLED,
    .dstate = &_TRACE_GIC_ENABLE_IRQ_DSTATE 
};
TraceEvent _TRACE_GIC_DISABLE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_disable_irq",
    .sstate = TRACE_GIC_DISABLE_IRQ_ENABLED,
    .dstate = &_TRACE_GIC_DISABLE_IRQ_DSTATE 
};
TraceEvent _TRACE_GIC_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_set_irq",
    .sstate = TRACE_GIC_SET_IRQ_ENABLED,
    .dstate = &_TRACE_GIC_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_GIC_UPDATE_BESTIRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_update_bestirq",
    .sstate = TRACE_GIC_UPDATE_BESTIRQ_ENABLED,
    .dstate = &_TRACE_GIC_UPDATE_BESTIRQ_DSTATE 
};
TraceEvent _TRACE_GIC_UPDATE_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_update_set_irq",
    .sstate = TRACE_GIC_UPDATE_SET_IRQ_ENABLED,
    .dstate = &_TRACE_GIC_UPDATE_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_GIC_ACKNOWLEDGE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_acknowledge_irq",
    .sstate = TRACE_GIC_ACKNOWLEDGE_IRQ_ENABLED,
    .dstate = &_TRACE_GIC_ACKNOWLEDGE_IRQ_DSTATE 
};
TraceEvent _TRACE_GIC_CPU_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_cpu_write",
    .sstate = TRACE_GIC_CPU_WRITE_ENABLED,
    .dstate = &_TRACE_GIC_CPU_WRITE_DSTATE 
};
TraceEvent _TRACE_GIC_CPU_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_cpu_read",
    .sstate = TRACE_GIC_CPU_READ_ENABLED,
    .dstate = &_TRACE_GIC_CPU_READ_DSTATE 
};
TraceEvent _TRACE_GIC_HYP_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_hyp_read",
    .sstate = TRACE_GIC_HYP_READ_ENABLED,
    .dstate = &_TRACE_GIC_HYP_READ_DSTATE 
};
TraceEvent _TRACE_GIC_HYP_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_hyp_write",
    .sstate = TRACE_GIC_HYP_WRITE_ENABLED,
    .dstate = &_TRACE_GIC_HYP_WRITE_DSTATE 
};
TraceEvent _TRACE_GIC_DIST_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_dist_read",
    .sstate = TRACE_GIC_DIST_READ_ENABLED,
    .dstate = &_TRACE_GIC_DIST_READ_DSTATE 
};
TraceEvent _TRACE_GIC_DIST_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_dist_write",
    .sstate = TRACE_GIC_DIST_WRITE_ENABLED,
    .dstate = &_TRACE_GIC_DIST_WRITE_DSTATE 
};
TraceEvent _TRACE_GIC_LR_ENTRY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_lr_entry",
    .sstate = TRACE_GIC_LR_ENTRY_ENABLED,
    .dstate = &_TRACE_GIC_LR_ENTRY_DSTATE 
};
TraceEvent _TRACE_GIC_UPDATE_MAINTENANCE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gic_update_maintenance_irq",
    .sstate = TRACE_GIC_UPDATE_MAINTENANCE_IRQ_ENABLED,
    .dstate = &_TRACE_GIC_UPDATE_MAINTENANCE_IRQ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_PMR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_pmr_read",
    .sstate = TRACE_GICV3_ICC_PMR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_PMR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_PMR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_pmr_write",
    .sstate = TRACE_GICV3_ICC_PMR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_PMR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_BPR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_bpr_read",
    .sstate = TRACE_GICV3_ICC_BPR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_BPR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_BPR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_bpr_write",
    .sstate = TRACE_GICV3_ICC_BPR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_BPR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_AP_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_ap_read",
    .sstate = TRACE_GICV3_ICC_AP_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_AP_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_AP_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_ap_write",
    .sstate = TRACE_GICV3_ICC_AP_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_AP_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_IGRPEN_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_igrpen_read",
    .sstate = TRACE_GICV3_ICC_IGRPEN_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_IGRPEN_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_IGRPEN_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_igrpen_write",
    .sstate = TRACE_GICV3_ICC_IGRPEN_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_IGRPEN_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_IGRPEN1_EL3_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_igrpen1_el3_read",
    .sstate = TRACE_GICV3_ICC_IGRPEN1_EL3_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_IGRPEN1_EL3_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_igrpen1_el3_write",
    .sstate = TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_CTLR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_ctlr_read",
    .sstate = TRACE_GICV3_ICC_CTLR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_CTLR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_CTLR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_ctlr_write",
    .sstate = TRACE_GICV3_ICC_CTLR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_CTLR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_CTLR_EL3_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_ctlr_el3_read",
    .sstate = TRACE_GICV3_ICC_CTLR_EL3_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_CTLR_EL3_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_CTLR_EL3_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_ctlr_el3_write",
    .sstate = TRACE_GICV3_ICC_CTLR_EL3_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_CTLR_EL3_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_CPUIF_UPDATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_cpuif_update",
    .sstate = TRACE_GICV3_CPUIF_UPDATE_ENABLED,
    .dstate = &_TRACE_GICV3_CPUIF_UPDATE_DSTATE 
};
TraceEvent _TRACE_GICV3_CPUIF_SET_IRQS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_cpuif_set_irqs",
    .sstate = TRACE_GICV3_CPUIF_SET_IRQS_ENABLED,
    .dstate = &_TRACE_GICV3_CPUIF_SET_IRQS_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_GENERATE_SGI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_generate_sgi",
    .sstate = TRACE_GICV3_ICC_GENERATE_SGI_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_GENERATE_SGI_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_IAR0_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_iar0_read",
    .sstate = TRACE_GICV3_ICC_IAR0_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_IAR0_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_IAR1_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_iar1_read",
    .sstate = TRACE_GICV3_ICC_IAR1_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_IAR1_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_EOIR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_eoir_write",
    .sstate = TRACE_GICV3_ICC_EOIR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_EOIR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_HPPIR0_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_hppir0_read",
    .sstate = TRACE_GICV3_ICC_HPPIR0_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_HPPIR0_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_HPPIR1_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_hppir1_read",
    .sstate = TRACE_GICV3_ICC_HPPIR1_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_HPPIR1_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_DIR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_dir_write",
    .sstate = TRACE_GICV3_ICC_DIR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_DIR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICC_RPR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icc_rpr_read",
    .sstate = TRACE_GICV3_ICC_RPR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICC_RPR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_AP_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_ap_read",
    .sstate = TRACE_GICV3_ICH_AP_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_AP_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_AP_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_ap_write",
    .sstate = TRACE_GICV3_ICH_AP_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_AP_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_HCR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_hcr_read",
    .sstate = TRACE_GICV3_ICH_HCR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_HCR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_HCR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_hcr_write",
    .sstate = TRACE_GICV3_ICH_HCR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_HCR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_VMCR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_vmcr_read",
    .sstate = TRACE_GICV3_ICH_VMCR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_VMCR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_VMCR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_vmcr_write",
    .sstate = TRACE_GICV3_ICH_VMCR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_VMCR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_LR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_lr_read",
    .sstate = TRACE_GICV3_ICH_LR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_LR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_LR32_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_lr32_read",
    .sstate = TRACE_GICV3_ICH_LR32_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_LR32_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_LRC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_lrc_read",
    .sstate = TRACE_GICV3_ICH_LRC_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_LRC_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_LR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_lr_write",
    .sstate = TRACE_GICV3_ICH_LR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_LR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_LR32_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_lr32_write",
    .sstate = TRACE_GICV3_ICH_LR32_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_LR32_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_LRC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_lrc_write",
    .sstate = TRACE_GICV3_ICH_LRC_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_LRC_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_VTR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_vtr_read",
    .sstate = TRACE_GICV3_ICH_VTR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_VTR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_MISR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_misr_read",
    .sstate = TRACE_GICV3_ICH_MISR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_MISR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_EISR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_eisr_read",
    .sstate = TRACE_GICV3_ICH_EISR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_EISR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICH_ELRSR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_ich_elrsr_read",
    .sstate = TRACE_GICV3_ICH_ELRSR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICH_ELRSR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_AP_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_ap_read",
    .sstate = TRACE_GICV3_ICV_AP_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_AP_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_AP_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_ap_write",
    .sstate = TRACE_GICV3_ICV_AP_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_AP_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_BPR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_bpr_read",
    .sstate = TRACE_GICV3_ICV_BPR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_BPR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_BPR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_bpr_write",
    .sstate = TRACE_GICV3_ICV_BPR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_BPR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_PMR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_pmr_read",
    .sstate = TRACE_GICV3_ICV_PMR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_PMR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_PMR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_pmr_write",
    .sstate = TRACE_GICV3_ICV_PMR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_PMR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_IGRPEN_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_igrpen_read",
    .sstate = TRACE_GICV3_ICV_IGRPEN_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_IGRPEN_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_IGRPEN_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_igrpen_write",
    .sstate = TRACE_GICV3_ICV_IGRPEN_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_IGRPEN_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_CTLR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_ctlr_read",
    .sstate = TRACE_GICV3_ICV_CTLR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_CTLR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_CTLR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_ctlr_write",
    .sstate = TRACE_GICV3_ICV_CTLR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_CTLR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_RPR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_rpr_read",
    .sstate = TRACE_GICV3_ICV_RPR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_RPR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_HPPIR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_hppir_read",
    .sstate = TRACE_GICV3_ICV_HPPIR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_HPPIR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_DIR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_dir_write",
    .sstate = TRACE_GICV3_ICV_DIR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_DIR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_IAR_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_iar_read",
    .sstate = TRACE_GICV3_ICV_IAR_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_IAR_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ICV_EOIR_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_icv_eoir_write",
    .sstate = TRACE_GICV3_ICV_EOIR_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ICV_EOIR_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_CPUIF_VIRT_UPDATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_cpuif_virt_update",
    .sstate = TRACE_GICV3_CPUIF_VIRT_UPDATE_ENABLED,
    .dstate = &_TRACE_GICV3_CPUIF_VIRT_UPDATE_DSTATE 
};
TraceEvent _TRACE_GICV3_CPUIF_VIRT_SET_IRQS_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_cpuif_virt_set_irqs",
    .sstate = TRACE_GICV3_CPUIF_VIRT_SET_IRQS_ENABLED,
    .dstate = &_TRACE_GICV3_CPUIF_VIRT_SET_IRQS_DSTATE 
};
TraceEvent _TRACE_GICV3_DIST_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_dist_read",
    .sstate = TRACE_GICV3_DIST_READ_ENABLED,
    .dstate = &_TRACE_GICV3_DIST_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_DIST_BADREAD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_dist_badread",
    .sstate = TRACE_GICV3_DIST_BADREAD_ENABLED,
    .dstate = &_TRACE_GICV3_DIST_BADREAD_DSTATE 
};
TraceEvent _TRACE_GICV3_DIST_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_dist_write",
    .sstate = TRACE_GICV3_DIST_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_DIST_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_DIST_BADWRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_dist_badwrite",
    .sstate = TRACE_GICV3_DIST_BADWRITE_ENABLED,
    .dstate = &_TRACE_GICV3_DIST_BADWRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_DIST_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_dist_set_irq",
    .sstate = TRACE_GICV3_DIST_SET_IRQ_ENABLED,
    .dstate = &_TRACE_GICV3_DIST_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_GICV3_REDIST_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_redist_read",
    .sstate = TRACE_GICV3_REDIST_READ_ENABLED,
    .dstate = &_TRACE_GICV3_REDIST_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_REDIST_BADREAD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_redist_badread",
    .sstate = TRACE_GICV3_REDIST_BADREAD_ENABLED,
    .dstate = &_TRACE_GICV3_REDIST_BADREAD_DSTATE 
};
TraceEvent _TRACE_GICV3_REDIST_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_redist_write",
    .sstate = TRACE_GICV3_REDIST_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_REDIST_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_REDIST_BADWRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_redist_badwrite",
    .sstate = TRACE_GICV3_REDIST_BADWRITE_ENABLED,
    .dstate = &_TRACE_GICV3_REDIST_BADWRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_REDIST_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_redist_set_irq",
    .sstate = TRACE_GICV3_REDIST_SET_IRQ_ENABLED,
    .dstate = &_TRACE_GICV3_REDIST_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_GICV3_REDIST_SEND_SGI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_redist_send_sgi",
    .sstate = TRACE_GICV3_REDIST_SEND_SGI_ENABLED,
    .dstate = &_TRACE_GICV3_REDIST_SEND_SGI_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_read",
    .sstate = TRACE_GICV3_ITS_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_BADREAD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_badread",
    .sstate = TRACE_GICV3_ITS_BADREAD_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_BADREAD_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_write",
    .sstate = TRACE_GICV3_ITS_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_BADWRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_badwrite",
    .sstate = TRACE_GICV3_ITS_BADWRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_BADWRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_TRANSLATION_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_translation_write",
    .sstate = TRACE_GICV3_ITS_TRANSLATION_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_TRANSLATION_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_PROCESS_COMMAND_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_process_command",
    .sstate = TRACE_GICV3_ITS_PROCESS_COMMAND_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_PROCESS_COMMAND_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_INT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_int",
    .sstate = TRACE_GICV3_ITS_CMD_INT_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_INT_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_CLEAR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_clear",
    .sstate = TRACE_GICV3_ITS_CMD_CLEAR_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_CLEAR_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_DISCARD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_discard",
    .sstate = TRACE_GICV3_ITS_CMD_DISCARD_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_DISCARD_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_SYNC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_sync",
    .sstate = TRACE_GICV3_ITS_CMD_SYNC_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_SYNC_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_MAPD_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_mapd",
    .sstate = TRACE_GICV3_ITS_CMD_MAPD_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_MAPD_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_MAPC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_mapc",
    .sstate = TRACE_GICV3_ITS_CMD_MAPC_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_MAPC_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_MAPI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_mapi",
    .sstate = TRACE_GICV3_ITS_CMD_MAPI_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_MAPI_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_MAPTI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_mapti",
    .sstate = TRACE_GICV3_ITS_CMD_MAPTI_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_MAPTI_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_INV_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_inv",
    .sstate = TRACE_GICV3_ITS_CMD_INV_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_INV_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_MOVALL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_movall",
    .sstate = TRACE_GICV3_ITS_CMD_MOVALL_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_MOVALL_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_MOVI_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_movi",
    .sstate = TRACE_GICV3_ITS_CMD_MOVI_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_MOVI_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CMD_UNKNOWN_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cmd_unknown",
    .sstate = TRACE_GICV3_ITS_CMD_UNKNOWN_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CMD_UNKNOWN_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CTE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cte_read",
    .sstate = TRACE_GICV3_ITS_CTE_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CTE_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CTE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cte_write",
    .sstate = TRACE_GICV3_ITS_CTE_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CTE_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_CTE_READ_FAULT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_cte_read_fault",
    .sstate = TRACE_GICV3_ITS_CTE_READ_FAULT_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_CTE_READ_FAULT_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_ITE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_ite_read",
    .sstate = TRACE_GICV3_ITS_ITE_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_ITE_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_ITE_READ_FAULT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_ite_read_fault",
    .sstate = TRACE_GICV3_ITS_ITE_READ_FAULT_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_ITE_READ_FAULT_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_ITE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_ite_write",
    .sstate = TRACE_GICV3_ITS_ITE_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_ITE_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_DTE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_dte_read",
    .sstate = TRACE_GICV3_ITS_DTE_READ_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_DTE_READ_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_DTE_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_dte_write",
    .sstate = TRACE_GICV3_ITS_DTE_WRITE_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_DTE_WRITE_DSTATE 
};
TraceEvent _TRACE_GICV3_ITS_DTE_READ_FAULT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "gicv3_its_dte_read_fault",
    .sstate = TRACE_GICV3_ITS_DTE_READ_FAULT_ENABLED,
    .dstate = &_TRACE_GICV3_ITS_DTE_READ_FAULT_DSTATE 
};
TraceEvent _TRACE_NVIC_RECOMPUTE_STATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_recompute_state",
    .sstate = TRACE_NVIC_RECOMPUTE_STATE_ENABLED,
    .dstate = &_TRACE_NVIC_RECOMPUTE_STATE_DSTATE 
};
TraceEvent _TRACE_NVIC_RECOMPUTE_STATE_SECURE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_recompute_state_secure",
    .sstate = TRACE_NVIC_RECOMPUTE_STATE_SECURE_ENABLED,
    .dstate = &_TRACE_NVIC_RECOMPUTE_STATE_SECURE_DSTATE 
};
TraceEvent _TRACE_NVIC_SET_PRIO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_set_prio",
    .sstate = TRACE_NVIC_SET_PRIO_ENABLED,
    .dstate = &_TRACE_NVIC_SET_PRIO_DSTATE 
};
TraceEvent _TRACE_NVIC_IRQ_UPDATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_irq_update",
    .sstate = TRACE_NVIC_IRQ_UPDATE_ENABLED,
    .dstate = &_TRACE_NVIC_IRQ_UPDATE_DSTATE 
};
TraceEvent _TRACE_NVIC_ESCALATE_PRIO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_escalate_prio",
    .sstate = TRACE_NVIC_ESCALATE_PRIO_ENABLED,
    .dstate = &_TRACE_NVIC_ESCALATE_PRIO_DSTATE 
};
TraceEvent _TRACE_NVIC_ESCALATE_DISABLED_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_escalate_disabled",
    .sstate = TRACE_NVIC_ESCALATE_DISABLED_ENABLED,
    .dstate = &_TRACE_NVIC_ESCALATE_DISABLED_DSTATE 
};
TraceEvent _TRACE_NVIC_SET_PENDING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_set_pending",
    .sstate = TRACE_NVIC_SET_PENDING_ENABLED,
    .dstate = &_TRACE_NVIC_SET_PENDING_DSTATE 
};
TraceEvent _TRACE_NVIC_CLEAR_PENDING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_clear_pending",
    .sstate = TRACE_NVIC_CLEAR_PENDING_ENABLED,
    .dstate = &_TRACE_NVIC_CLEAR_PENDING_DSTATE 
};
TraceEvent _TRACE_NVIC_ACKNOWLEDGE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_acknowledge_irq",
    .sstate = TRACE_NVIC_ACKNOWLEDGE_IRQ_ENABLED,
    .dstate = &_TRACE_NVIC_ACKNOWLEDGE_IRQ_DSTATE 
};
TraceEvent _TRACE_NVIC_GET_PENDING_IRQ_INFO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_get_pending_irq_info",
    .sstate = TRACE_NVIC_GET_PENDING_IRQ_INFO_ENABLED,
    .dstate = &_TRACE_NVIC_GET_PENDING_IRQ_INFO_DSTATE 
};
TraceEvent _TRACE_NVIC_COMPLETE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_complete_irq",
    .sstate = TRACE_NVIC_COMPLETE_IRQ_ENABLED,
    .dstate = &_TRACE_NVIC_COMPLETE_IRQ_DSTATE 
};
TraceEvent _TRACE_NVIC_SET_IRQ_LEVEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_set_irq_level",
    .sstate = TRACE_NVIC_SET_IRQ_LEVEL_ENABLED,
    .dstate = &_TRACE_NVIC_SET_IRQ_LEVEL_DSTATE 
};
TraceEvent _TRACE_NVIC_SET_NMI_LEVEL_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_set_nmi_level",
    .sstate = TRACE_NVIC_SET_NMI_LEVEL_ENABLED,
    .dstate = &_TRACE_NVIC_SET_NMI_LEVEL_DSTATE 
};
TraceEvent _TRACE_NVIC_SYSREG_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_sysreg_read",
    .sstate = TRACE_NVIC_SYSREG_READ_ENABLED,
    .dstate = &_TRACE_NVIC_SYSREG_READ_DSTATE 
};
TraceEvent _TRACE_NVIC_SYSREG_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "nvic_sysreg_write",
    .sstate = TRACE_NVIC_SYSREG_WRITE_ENABLED,
    .dstate = &_TRACE_NVIC_SYSREG_WRITE_DSTATE 
};
TraceEvent _TRACE_HEATHROW_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "heathrow_write",
    .sstate = TRACE_HEATHROW_WRITE_ENABLED,
    .dstate = &_TRACE_HEATHROW_WRITE_DSTATE 
};
TraceEvent _TRACE_HEATHROW_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "heathrow_read",
    .sstate = TRACE_HEATHROW_READ_ENABLED,
    .dstate = &_TRACE_HEATHROW_READ_DSTATE 
};
TraceEvent _TRACE_HEATHROW_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "heathrow_set_irq",
    .sstate = TRACE_HEATHROW_SET_IRQ_ENABLED,
    .dstate = &_TRACE_HEATHROW_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_BCM2835_IC_SET_GPU_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "bcm2835_ic_set_gpu_irq",
    .sstate = TRACE_BCM2835_IC_SET_GPU_IRQ_ENABLED,
    .dstate = &_TRACE_BCM2835_IC_SET_GPU_IRQ_DSTATE 
};
TraceEvent _TRACE_BCM2835_IC_SET_CPU_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "bcm2835_ic_set_cpu_irq",
    .sstate = TRACE_BCM2835_IC_SET_CPU_IRQ_ENABLED,
    .dstate = &_TRACE_BCM2835_IC_SET_CPU_IRQ_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_CLAIM_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_claim_irq",
    .sstate = TRACE_SPAPR_XIVE_CLAIM_IRQ_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_CLAIM_IRQ_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_FREE_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_free_irq",
    .sstate = TRACE_SPAPR_XIVE_FREE_IRQ_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_FREE_IRQ_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_SET_IRQ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_set_irq",
    .sstate = TRACE_SPAPR_XIVE_SET_IRQ_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_GET_SOURCE_INFO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_get_source_info",
    .sstate = TRACE_SPAPR_XIVE_GET_SOURCE_INFO_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_GET_SOURCE_INFO_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_set_source_config",
    .sstate = TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_get_source_config",
    .sstate = TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_GET_QUEUE_INFO_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_get_queue_info",
    .sstate = TRACE_SPAPR_XIVE_GET_QUEUE_INFO_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_GET_QUEUE_INFO_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_set_queue_config",
    .sstate = TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_get_queue_config",
    .sstate = TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_set_os_reporting_line",
    .sstate = TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_get_os_reporting_line",
    .sstate = TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_ESB_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_esb",
    .sstate = TRACE_SPAPR_XIVE_ESB_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_ESB_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_SYNC_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_sync",
    .sstate = TRACE_SPAPR_XIVE_SYNC_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_SYNC_DSTATE 
};
TraceEvent _TRACE_SPAPR_XIVE_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "spapr_xive_reset",
    .sstate = TRACE_SPAPR_XIVE_RESET_ENABLED,
    .dstate = &_TRACE_SPAPR_XIVE_RESET_DSTATE 
};
TraceEvent _TRACE_KVM_XIVE_CPU_CONNECT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "kvm_xive_cpu_connect",
    .sstate = TRACE_KVM_XIVE_CPU_CONNECT_ENABLED,
    .dstate = &_TRACE_KVM_XIVE_CPU_CONNECT_DSTATE 
};
TraceEvent _TRACE_KVM_XIVE_SOURCE_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "kvm_xive_source_reset",
    .sstate = TRACE_KVM_XIVE_SOURCE_RESET_ENABLED,
    .dstate = &_TRACE_KVM_XIVE_SOURCE_RESET_DSTATE 
};
TraceEvent _TRACE_XIVE_TCTX_ACCEPT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_tctx_accept",
    .sstate = TRACE_XIVE_TCTX_ACCEPT_ENABLED,
    .dstate = &_TRACE_XIVE_TCTX_ACCEPT_DSTATE 
};
TraceEvent _TRACE_XIVE_TCTX_NOTIFY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_tctx_notify",
    .sstate = TRACE_XIVE_TCTX_NOTIFY_ENABLED,
    .dstate = &_TRACE_XIVE_TCTX_NOTIFY_DSTATE 
};
TraceEvent _TRACE_XIVE_TCTX_SET_CPPR_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_tctx_set_cppr",
    .sstate = TRACE_XIVE_TCTX_SET_CPPR_ENABLED,
    .dstate = &_TRACE_XIVE_TCTX_SET_CPPR_DSTATE 
};
TraceEvent _TRACE_XIVE_SOURCE_ESB_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_source_esb_read",
    .sstate = TRACE_XIVE_SOURCE_ESB_READ_ENABLED,
    .dstate = &_TRACE_XIVE_SOURCE_ESB_READ_DSTATE 
};
TraceEvent _TRACE_XIVE_SOURCE_ESB_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_source_esb_write",
    .sstate = TRACE_XIVE_SOURCE_ESB_WRITE_ENABLED,
    .dstate = &_TRACE_XIVE_SOURCE_ESB_WRITE_DSTATE 
};
TraceEvent _TRACE_XIVE_ROUTER_END_NOTIFY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_router_end_notify",
    .sstate = TRACE_XIVE_ROUTER_END_NOTIFY_ENABLED,
    .dstate = &_TRACE_XIVE_ROUTER_END_NOTIFY_DSTATE 
};
TraceEvent _TRACE_XIVE_ROUTER_END_ESCALATE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_router_end_escalate",
    .sstate = TRACE_XIVE_ROUTER_END_ESCALATE_ENABLED,
    .dstate = &_TRACE_XIVE_ROUTER_END_ESCALATE_DSTATE 
};
TraceEvent _TRACE_XIVE_TCTX_TM_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_tctx_tm_write",
    .sstate = TRACE_XIVE_TCTX_TM_WRITE_ENABLED,
    .dstate = &_TRACE_XIVE_TCTX_TM_WRITE_DSTATE 
};
TraceEvent _TRACE_XIVE_TCTX_TM_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_tctx_tm_read",
    .sstate = TRACE_XIVE_TCTX_TM_READ_ENABLED,
    .dstate = &_TRACE_XIVE_TCTX_TM_READ_DSTATE 
};
TraceEvent _TRACE_XIVE_PRESENTER_NOTIFY_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_presenter_notify",
    .sstate = TRACE_XIVE_PRESENTER_NOTIFY_ENABLED,
    .dstate = &_TRACE_XIVE_PRESENTER_NOTIFY_DSTATE 
};
TraceEvent _TRACE_XIVE_END_SOURCE_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "xive_end_source_read",
    .sstate = TRACE_XIVE_END_SOURCE_READ_ENABLED,
    .dstate = &_TRACE_XIVE_END_SOURCE_READ_DSTATE 
};
TraceEvent _TRACE_PNV_XIVE_IC_HW_TRIGGER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "pnv_xive_ic_hw_trigger",
    .sstate = TRACE_PNV_XIVE_IC_HW_TRIGGER_ENABLED,
    .dstate = &_TRACE_PNV_XIVE_IC_HW_TRIGGER_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_IRQ_REQUEST_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_irq_request",
    .sstate = TRACE_GOLDFISH_IRQ_REQUEST_ENABLED,
    .dstate = &_TRACE_GOLDFISH_IRQ_REQUEST_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_PIC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_pic_read",
    .sstate = TRACE_GOLDFISH_PIC_READ_ENABLED,
    .dstate = &_TRACE_GOLDFISH_PIC_READ_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_PIC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_pic_write",
    .sstate = TRACE_GOLDFISH_PIC_WRITE_ENABLED,
    .dstate = &_TRACE_GOLDFISH_PIC_WRITE_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_PIC_RESET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_pic_reset",
    .sstate = TRACE_GOLDFISH_PIC_RESET_ENABLED,
    .dstate = &_TRACE_GOLDFISH_PIC_RESET_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_PIC_REALIZE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_pic_realize",
    .sstate = TRACE_GOLDFISH_PIC_REALIZE_ENABLED,
    .dstate = &_TRACE_GOLDFISH_PIC_REALIZE_DSTATE 
};
TraceEvent _TRACE_GOLDFISH_PIC_INSTANCE_INIT_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "goldfish_pic_instance_init",
    .sstate = TRACE_GOLDFISH_PIC_INSTANCE_INIT_ENABLED,
    .dstate = &_TRACE_GOLDFISH_PIC_INSTANCE_INIT_DSTATE 
};
TraceEvent _TRACE_SH_INTC_SOURCES_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sh_intc_sources",
    .sstate = TRACE_SH_INTC_SOURCES_ENABLED,
    .dstate = &_TRACE_SH_INTC_SOURCES_DSTATE 
};
TraceEvent _TRACE_SH_INTC_PENDING_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sh_intc_pending",
    .sstate = TRACE_SH_INTC_PENDING_ENABLED,
    .dstate = &_TRACE_SH_INTC_PENDING_DSTATE 
};
TraceEvent _TRACE_SH_INTC_REGISTER_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sh_intc_register",
    .sstate = TRACE_SH_INTC_REGISTER_ENABLED,
    .dstate = &_TRACE_SH_INTC_REGISTER_DSTATE 
};
TraceEvent _TRACE_SH_INTC_READ_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sh_intc_read",
    .sstate = TRACE_SH_INTC_READ_ENABLED,
    .dstate = &_TRACE_SH_INTC_READ_DSTATE 
};
TraceEvent _TRACE_SH_INTC_WRITE_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sh_intc_write",
    .sstate = TRACE_SH_INTC_WRITE_ENABLED,
    .dstate = &_TRACE_SH_INTC_WRITE_DSTATE 
};
TraceEvent _TRACE_SH_INTC_SET_EVENT = {
    .id = 0,
    .vcpu_id = TRACE_VCPU_EVENT_NONE,
    .name = "sh_intc_set",
    .sstate = TRACE_SH_INTC_SET_ENABLED,
    .dstate = &_TRACE_SH_INTC_SET_DSTATE 
};
TraceEvent *hw_intc_trace_events[] = {
    &_TRACE_PIC_UPDATE_IRQ_EVENT,
    &_TRACE_PIC_SET_IRQ_EVENT,
    &_TRACE_PIC_INTERRUPT_EVENT,
    &_TRACE_PIC_IOPORT_WRITE_EVENT,
    &_TRACE_PIC_IOPORT_READ_EVENT,
    &_TRACE_CPU_SET_APIC_BASE_EVENT,
    &_TRACE_CPU_GET_APIC_BASE_EVENT,
    &_TRACE_APIC_REPORT_IRQ_DELIVERED_EVENT,
    &_TRACE_APIC_RESET_IRQ_DELIVERED_EVENT,
    &_TRACE_APIC_GET_IRQ_DELIVERED_EVENT,
    &_TRACE_APIC_LOCAL_DELIVER_EVENT,
    &_TRACE_APIC_DELIVER_IRQ_EVENT,
    &_TRACE_APIC_MEM_READL_EVENT,
    &_TRACE_APIC_MEM_WRITEL_EVENT,
    &_TRACE_IOAPIC_SET_REMOTE_IRR_EVENT,
    &_TRACE_IOAPIC_CLEAR_REMOTE_IRR_EVENT,
    &_TRACE_IOAPIC_EOI_BROADCAST_EVENT,
    &_TRACE_IOAPIC_EOI_DELAYED_REASSERT_EVENT,
    &_TRACE_IOAPIC_MEM_READ_EVENT,
    &_TRACE_IOAPIC_MEM_WRITE_EVENT,
    &_TRACE_IOAPIC_SET_IRQ_EVENT,
    &_TRACE_SLAVIO_INTCTL_MEM_READL_EVENT,
    &_TRACE_SLAVIO_INTCTL_MEM_WRITEL_EVENT,
    &_TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_EVENT,
    &_TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_EVENT,
    &_TRACE_SLAVIO_INTCTLM_MEM_READL_EVENT,
    &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_EVENT,
    &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_EVENT,
    &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_EVENT,
    &_TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_EVENT,
    &_TRACE_SLAVIO_CHECK_INTERRUPTS_EVENT,
    &_TRACE_SLAVIO_SET_IRQ_EVENT,
    &_TRACE_SLAVIO_SET_TIMER_IRQ_CPU_EVENT,
    &_TRACE_GRLIB_IRQMP_CHECK_IRQS_EVENT,
    &_TRACE_GRLIB_IRQMP_ACK_EVENT,
    &_TRACE_GRLIB_IRQMP_SET_IRQ_EVENT,
    &_TRACE_GRLIB_IRQMP_READL_UNKNOWN_EVENT,
    &_TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_EVENT,
    &_TRACE_XICS_ICP_CHECK_IPI_EVENT,
    &_TRACE_XICS_ICP_ACCEPT_EVENT,
    &_TRACE_XICS_ICP_EOI_EVENT,
    &_TRACE_XICS_ICP_IRQ_EVENT,
    &_TRACE_XICS_ICP_RAISE_EVENT,
    &_TRACE_XICS_ICS_SET_IRQ_MSI_EVENT,
    &_TRACE_XICS_MASKED_PENDING_EVENT,
    &_TRACE_XICS_ICS_SET_IRQ_LSI_EVENT,
    &_TRACE_XICS_ICS_WRITE_XIVE_EVENT,
    &_TRACE_XICS_ICS_REJECT_EVENT,
    &_TRACE_XICS_ICS_EOI_EVENT,
    &_TRACE_FLIC_CREATE_DEVICE_EVENT,
    &_TRACE_FLIC_RESET_FAILED_EVENT,
    &_TRACE_QEMU_S390_AIRQ_SUPPRESSED_EVENT,
    &_TRACE_QEMU_S390_SUPPRESS_AIRQ_EVENT,
    &_TRACE_ASPEED_VIC_SET_IRQ_EVENT,
    &_TRACE_ASPEED_VIC_UPDATE_FIQ_EVENT,
    &_TRACE_ASPEED_VIC_UPDATE_IRQ_EVENT,
    &_TRACE_ASPEED_VIC_READ_EVENT,
    &_TRACE_ASPEED_VIC_WRITE_EVENT,
    &_TRACE_GIC_ENABLE_IRQ_EVENT,
    &_TRACE_GIC_DISABLE_IRQ_EVENT,
    &_TRACE_GIC_SET_IRQ_EVENT,
    &_TRACE_GIC_UPDATE_BESTIRQ_EVENT,
    &_TRACE_GIC_UPDATE_SET_IRQ_EVENT,
    &_TRACE_GIC_ACKNOWLEDGE_IRQ_EVENT,
    &_TRACE_GIC_CPU_WRITE_EVENT,
    &_TRACE_GIC_CPU_READ_EVENT,
    &_TRACE_GIC_HYP_READ_EVENT,
    &_TRACE_GIC_HYP_WRITE_EVENT,
    &_TRACE_GIC_DIST_READ_EVENT,
    &_TRACE_GIC_DIST_WRITE_EVENT,
    &_TRACE_GIC_LR_ENTRY_EVENT,
    &_TRACE_GIC_UPDATE_MAINTENANCE_IRQ_EVENT,
    &_TRACE_GICV3_ICC_PMR_READ_EVENT,
    &_TRACE_GICV3_ICC_PMR_WRITE_EVENT,
    &_TRACE_GICV3_ICC_BPR_READ_EVENT,
    &_TRACE_GICV3_ICC_BPR_WRITE_EVENT,
    &_TRACE_GICV3_ICC_AP_READ_EVENT,
    &_TRACE_GICV3_ICC_AP_WRITE_EVENT,
    &_TRACE_GICV3_ICC_IGRPEN_READ_EVENT,
    &_TRACE_GICV3_ICC_IGRPEN_WRITE_EVENT,
    &_TRACE_GICV3_ICC_IGRPEN1_EL3_READ_EVENT,
    &_TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_EVENT,
    &_TRACE_GICV3_ICC_CTLR_READ_EVENT,
    &_TRACE_GICV3_ICC_CTLR_WRITE_EVENT,
    &_TRACE_GICV3_ICC_CTLR_EL3_READ_EVENT,
    &_TRACE_GICV3_ICC_CTLR_EL3_WRITE_EVENT,
    &_TRACE_GICV3_CPUIF_UPDATE_EVENT,
    &_TRACE_GICV3_CPUIF_SET_IRQS_EVENT,
    &_TRACE_GICV3_ICC_GENERATE_SGI_EVENT,
    &_TRACE_GICV3_ICC_IAR0_READ_EVENT,
    &_TRACE_GICV3_ICC_IAR1_READ_EVENT,
    &_TRACE_GICV3_ICC_EOIR_WRITE_EVENT,
    &_TRACE_GICV3_ICC_HPPIR0_READ_EVENT,
    &_TRACE_GICV3_ICC_HPPIR1_READ_EVENT,
    &_TRACE_GICV3_ICC_DIR_WRITE_EVENT,
    &_TRACE_GICV3_ICC_RPR_READ_EVENT,
    &_TRACE_GICV3_ICH_AP_READ_EVENT,
    &_TRACE_GICV3_ICH_AP_WRITE_EVENT,
    &_TRACE_GICV3_ICH_HCR_READ_EVENT,
    &_TRACE_GICV3_ICH_HCR_WRITE_EVENT,
    &_TRACE_GICV3_ICH_VMCR_READ_EVENT,
    &_TRACE_GICV3_ICH_VMCR_WRITE_EVENT,
    &_TRACE_GICV3_ICH_LR_READ_EVENT,
    &_TRACE_GICV3_ICH_LR32_READ_EVENT,
    &_TRACE_GICV3_ICH_LRC_READ_EVENT,
    &_TRACE_GICV3_ICH_LR_WRITE_EVENT,
    &_TRACE_GICV3_ICH_LR32_WRITE_EVENT,
    &_TRACE_GICV3_ICH_LRC_WRITE_EVENT,
    &_TRACE_GICV3_ICH_VTR_READ_EVENT,
    &_TRACE_GICV3_ICH_MISR_READ_EVENT,
    &_TRACE_GICV3_ICH_EISR_READ_EVENT,
    &_TRACE_GICV3_ICH_ELRSR_READ_EVENT,
    &_TRACE_GICV3_ICV_AP_READ_EVENT,
    &_TRACE_GICV3_ICV_AP_WRITE_EVENT,
    &_TRACE_GICV3_ICV_BPR_READ_EVENT,
    &_TRACE_GICV3_ICV_BPR_WRITE_EVENT,
    &_TRACE_GICV3_ICV_PMR_READ_EVENT,
    &_TRACE_GICV3_ICV_PMR_WRITE_EVENT,
    &_TRACE_GICV3_ICV_IGRPEN_READ_EVENT,
    &_TRACE_GICV3_ICV_IGRPEN_WRITE_EVENT,
    &_TRACE_GICV3_ICV_CTLR_READ_EVENT,
    &_TRACE_GICV3_ICV_CTLR_WRITE_EVENT,
    &_TRACE_GICV3_ICV_RPR_READ_EVENT,
    &_TRACE_GICV3_ICV_HPPIR_READ_EVENT,
    &_TRACE_GICV3_ICV_DIR_WRITE_EVENT,
    &_TRACE_GICV3_ICV_IAR_READ_EVENT,
    &_TRACE_GICV3_ICV_EOIR_WRITE_EVENT,
    &_TRACE_GICV3_CPUIF_VIRT_UPDATE_EVENT,
    &_TRACE_GICV3_CPUIF_VIRT_SET_IRQS_EVENT,
    &_TRACE_GICV3_DIST_READ_EVENT,
    &_TRACE_GICV3_DIST_BADREAD_EVENT,
    &_TRACE_GICV3_DIST_WRITE_EVENT,
    &_TRACE_GICV3_DIST_BADWRITE_EVENT,
    &_TRACE_GICV3_DIST_SET_IRQ_EVENT,
    &_TRACE_GICV3_REDIST_READ_EVENT,
    &_TRACE_GICV3_REDIST_BADREAD_EVENT,
    &_TRACE_GICV3_REDIST_WRITE_EVENT,
    &_TRACE_GICV3_REDIST_BADWRITE_EVENT,
    &_TRACE_GICV3_REDIST_SET_IRQ_EVENT,
    &_TRACE_GICV3_REDIST_SEND_SGI_EVENT,
    &_TRACE_GICV3_ITS_READ_EVENT,
    &_TRACE_GICV3_ITS_BADREAD_EVENT,
    &_TRACE_GICV3_ITS_WRITE_EVENT,
    &_TRACE_GICV3_ITS_BADWRITE_EVENT,
    &_TRACE_GICV3_ITS_TRANSLATION_WRITE_EVENT,
    &_TRACE_GICV3_ITS_PROCESS_COMMAND_EVENT,
    &_TRACE_GICV3_ITS_CMD_INT_EVENT,
    &_TRACE_GICV3_ITS_CMD_CLEAR_EVENT,
    &_TRACE_GICV3_ITS_CMD_DISCARD_EVENT,
    &_TRACE_GICV3_ITS_CMD_SYNC_EVENT,
    &_TRACE_GICV3_ITS_CMD_MAPD_EVENT,
    &_TRACE_GICV3_ITS_CMD_MAPC_EVENT,
    &_TRACE_GICV3_ITS_CMD_MAPI_EVENT,
    &_TRACE_GICV3_ITS_CMD_MAPTI_EVENT,
    &_TRACE_GICV3_ITS_CMD_INV_EVENT,
    &_TRACE_GICV3_ITS_CMD_MOVALL_EVENT,
    &_TRACE_GICV3_ITS_CMD_MOVI_EVENT,
    &_TRACE_GICV3_ITS_CMD_UNKNOWN_EVENT,
    &_TRACE_GICV3_ITS_CTE_READ_EVENT,
    &_TRACE_GICV3_ITS_CTE_WRITE_EVENT,
    &_TRACE_GICV3_ITS_CTE_READ_FAULT_EVENT,
    &_TRACE_GICV3_ITS_ITE_READ_EVENT,
    &_TRACE_GICV3_ITS_ITE_READ_FAULT_EVENT,
    &_TRACE_GICV3_ITS_ITE_WRITE_EVENT,
    &_TRACE_GICV3_ITS_DTE_READ_EVENT,
    &_TRACE_GICV3_ITS_DTE_WRITE_EVENT,
    &_TRACE_GICV3_ITS_DTE_READ_FAULT_EVENT,
    &_TRACE_NVIC_RECOMPUTE_STATE_EVENT,
    &_TRACE_NVIC_RECOMPUTE_STATE_SECURE_EVENT,
    &_TRACE_NVIC_SET_PRIO_EVENT,
    &_TRACE_NVIC_IRQ_UPDATE_EVENT,
    &_TRACE_NVIC_ESCALATE_PRIO_EVENT,
    &_TRACE_NVIC_ESCALATE_DISABLED_EVENT,
    &_TRACE_NVIC_SET_PENDING_EVENT,
    &_TRACE_NVIC_CLEAR_PENDING_EVENT,
    &_TRACE_NVIC_ACKNOWLEDGE_IRQ_EVENT,
    &_TRACE_NVIC_GET_PENDING_IRQ_INFO_EVENT,
    &_TRACE_NVIC_COMPLETE_IRQ_EVENT,
    &_TRACE_NVIC_SET_IRQ_LEVEL_EVENT,
    &_TRACE_NVIC_SET_NMI_LEVEL_EVENT,
    &_TRACE_NVIC_SYSREG_READ_EVENT,
    &_TRACE_NVIC_SYSREG_WRITE_EVENT,
    &_TRACE_HEATHROW_WRITE_EVENT,
    &_TRACE_HEATHROW_READ_EVENT,
    &_TRACE_HEATHROW_SET_IRQ_EVENT,
    &_TRACE_BCM2835_IC_SET_GPU_IRQ_EVENT,
    &_TRACE_BCM2835_IC_SET_CPU_IRQ_EVENT,
    &_TRACE_SPAPR_XIVE_CLAIM_IRQ_EVENT,
    &_TRACE_SPAPR_XIVE_FREE_IRQ_EVENT,
    &_TRACE_SPAPR_XIVE_SET_IRQ_EVENT,
    &_TRACE_SPAPR_XIVE_GET_SOURCE_INFO_EVENT,
    &_TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_EVENT,
    &_TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_EVENT,
    &_TRACE_SPAPR_XIVE_GET_QUEUE_INFO_EVENT,
    &_TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_EVENT,
    &_TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_EVENT,
    &_TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_EVENT,
    &_TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_EVENT,
    &_TRACE_SPAPR_XIVE_ESB_EVENT,
    &_TRACE_SPAPR_XIVE_SYNC_EVENT,
    &_TRACE_SPAPR_XIVE_RESET_EVENT,
    &_TRACE_KVM_XIVE_CPU_CONNECT_EVENT,
    &_TRACE_KVM_XIVE_SOURCE_RESET_EVENT,
    &_TRACE_XIVE_TCTX_ACCEPT_EVENT,
    &_TRACE_XIVE_TCTX_NOTIFY_EVENT,
    &_TRACE_XIVE_TCTX_SET_CPPR_EVENT,
    &_TRACE_XIVE_SOURCE_ESB_READ_EVENT,
    &_TRACE_XIVE_SOURCE_ESB_WRITE_EVENT,
    &_TRACE_XIVE_ROUTER_END_NOTIFY_EVENT,
    &_TRACE_XIVE_ROUTER_END_ESCALATE_EVENT,
    &_TRACE_XIVE_TCTX_TM_WRITE_EVENT,
    &_TRACE_XIVE_TCTX_TM_READ_EVENT,
    &_TRACE_XIVE_PRESENTER_NOTIFY_EVENT,
    &_TRACE_XIVE_END_SOURCE_READ_EVENT,
    &_TRACE_PNV_XIVE_IC_HW_TRIGGER_EVENT,
    &_TRACE_GOLDFISH_IRQ_REQUEST_EVENT,
    &_TRACE_GOLDFISH_PIC_READ_EVENT,
    &_TRACE_GOLDFISH_PIC_WRITE_EVENT,
    &_TRACE_GOLDFISH_PIC_RESET_EVENT,
    &_TRACE_GOLDFISH_PIC_REALIZE_EVENT,
    &_TRACE_GOLDFISH_PIC_INSTANCE_INIT_EVENT,
    &_TRACE_SH_INTC_SOURCES_EVENT,
    &_TRACE_SH_INTC_PENDING_EVENT,
    &_TRACE_SH_INTC_REGISTER_EVENT,
    &_TRACE_SH_INTC_READ_EVENT,
    &_TRACE_SH_INTC_WRITE_EVENT,
    &_TRACE_SH_INTC_SET_EVENT,
  NULL,
};

static void trace_hw_intc_register_events(void)
{
    trace_event_register_group(hw_intc_trace_events);
}
trace_init(trace_hw_intc_register_events)
