%FILENAME%
verilator-5.006-1-armv7h.pkg.tar.xz

%NAME%
verilator

%BASE%
verilator

%VERSION%
5.006-1

%DESC%
The fastest free Verilog HDL simulator

%CSIZE%
4414784

%ISIZE%
21764686

%MD5SUM%
e899999bb4624bf42e20d59167443160

%SHA256SUM%
2c219adc4d35aabee75054f3ffa82ad55f640144ef903cbe6d7e8e0d2f9d90ae

%PGPSIG%
iQIzBAABCAAdFiEEaLNTfzmjE7PldNBndxk/FSvb5qYFAmPOh/EACgkQdxk/FSvb5qZrGxAAyCOoI2NDmQPQ5GXfxIlBQ4a5671dR3QwC0/+xL9Dm4YYgqA/g+APOBR7Cu1CSJHuwxUEjEO6LS+zwtd+F1Q6F3g3IPZOSa9MmCYphVvH6gw648z92JHxV/EyO8Z8bdOK423Nh5ED4QbrZgQC4UrSn6RB7eLeaH4pgAdKUKB3cpkHZNx9s2vtBuD2Y6BrRKDFEA5+0Y4X5Xls/qF/IUof1gZUnZQcvCsyM8Pbq5vcPxO44KoY0FyxnlRpGB/QZ+u714GXmFpJZEoUmC8jdWV0BZDg0RtkLyskbDcs1N7y9jJNSI/R7eSxLxPuTA7QBCDB7P3BRltm0927goLA2Mc9fdrpdwcxVtYBnrlTbAylCx9/HgMKIQKfnhwOkVP9hFyFJ0i74zaokm4jXoGkmlXa2IV/UXFHa1gO1GVbOvBDV/qnfgayYHnSIe8AYMu0oxYDTjibFPy041emYhAnaeJNNwLbOJLKYiRExfy+MFavgn30Z+CpP8qXgdwFkqgia9mnMtYI0ip3c3drZT7g0AGJoUZmlolTt5zxIYmx/M3w08t5T4mPy5CAyjjM1v+qV70p60jScBbvBhbsV8wFMYsmTzLSsEyEaD5MzrCfoGlqfKmWAoCpMHU/AHWClXnn3IX7uH2ORZEfPIubDZNTvpTcT8p0vwaH38HSbWn+hifUdaQ=

%URL%
https://www.veripool.org/projects/verilator/wiki/Intro

%LICENSE%
LGPL

%ARCH%
armv7h

%BUILDDATE%
1674479124

%PACKAGER%
Arch Linux ARM Build System <builder+xu1@archlinuxarm.org>

