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/*                  Atmel Microcontroller Software Support                      */
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#ifndef _SAM4E_PIOD_INSTANCE_
#define _SAM4E_PIOD_INSTANCE_

/* ========== Register definition for PIOD peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOD_PER                (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
#define REG_PIOD_PDR                (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
#define REG_PIOD_PSR                (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
#define REG_PIOD_OER                (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
#define REG_PIOD_ODR                (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
#define REG_PIOD_OSR                (0x400E1418U) /**< \brief (PIOD) Output Status Register */
#define REG_PIOD_IFER               (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR               (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR               (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR               (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
#define REG_PIOD_CODR               (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR               (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR               (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
#define REG_PIOD_IER                (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR                (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR                (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR                (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER               (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR               (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR               (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR               (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER               (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR               (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR             (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
#define REG_PIOD_IFSCDR             (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER             (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR             (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR               (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR              (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER              (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR              (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER               (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
#define REG_PIOD_OWDR               (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
#define REG_PIOD_OWSR               (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER              (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR              (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
#define REG_PIOD_AIMMR              (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR                (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
#define REG_PIOD_LSR                (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
#define REG_PIOD_ELSR               (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR             (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
#define REG_PIOD_REHLSR             (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
#define REG_PIOD_FRLHSR             (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR             (0x400E14E0U) /**< \brief (PIOD) Lock Status */
#define REG_PIOD_WPMR               (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
#define REG_PIOD_WPSR               (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
#define REG_PIOD_SCHMITT            (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DELAYR             (0x400E1510U) /**< \brief (PIOD) IO Delay Register */
#define REG_PIOD_PCMR               (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
#define REG_PIOD_PCIER              (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
#define REG_PIOD_PCIDR              (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
#define REG_PIOD_PCIMR              (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
#define REG_PIOD_PCISR              (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
#define REG_PIOD_PCRHR              (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
#else
#define REG_PIOD_PER       (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
#define REG_PIOD_PDR       (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
#define REG_PIOD_PSR       (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
#define REG_PIOD_OER       (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
#define REG_PIOD_ODR       (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
#define REG_PIOD_OSR       (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
#define REG_PIOD_IFER      (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR      (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR      (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR      (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
#define REG_PIOD_CODR      (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR      (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR      (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
#define REG_PIOD_IER       (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR       (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR       (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR       (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER      (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR      (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR      (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR      (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER      (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR      (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR    (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
#define REG_PIOD_IFSCDR    (*(WoReg*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER    (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR    (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR      (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR     (*(WoReg*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER     (*(WoReg*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR     (*(RoReg*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER      (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
#define REG_PIOD_OWDR      (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
#define REG_PIOD_OWSR      (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER     (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR     (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
#define REG_PIOD_AIMMR     (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR       (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
#define REG_PIOD_LSR       (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
#define REG_PIOD_ELSR      (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR    (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
#define REG_PIOD_REHLSR    (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
#define REG_PIOD_FRLHSR    (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR    (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
#define REG_PIOD_WPMR      (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
#define REG_PIOD_WPSR      (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
#define REG_PIOD_SCHMITT   (*(RwReg*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DELAYR    (*(RwReg*)0x400E1510U) /**< \brief (PIOD) IO Delay Register */
#define REG_PIOD_PCMR      (*(RwReg*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
#define REG_PIOD_PCIER     (*(WoReg*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
#define REG_PIOD_PCIDR     (*(WoReg*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
#define REG_PIOD_PCIMR     (*(RoReg*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
#define REG_PIOD_PCISR     (*(RoReg*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
#define REG_PIOD_PCRHR     (*(RoReg*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#endif /* _SAM4E_PIOD_INSTANCE_ */
