# Generated by EDAlize

[GENERAL]
run_engine = openfpga_shell
power_tech_file = {{ power_tech_file }}
power_analysis = true
spice_output = false
verilog_output = true
timeout_each_job = 1*60
fpga_flow = yosys_vpr
arch_variable_file = {{ arch_variable_file }}

[OpenFPGA_SHELL]
openfpga_shell_template = {{ openfpga_shell_template }}
openfpga_arch_file = {{ openfpga_arch_file }}
openfpga_sim_setting_file = {{ openfpga_sim_setting_file }}
external_fabric_key_file = {{ external_fabric_key_file }}
openfpga_vpr_device_layout = {{ vpr_device_layout }}
openfpga_vpr_route_chan_width = {{ vpr_route_chan_width }}

[ARCHITECTURES]
arch0 = {{ vpr_arch_file }}

[BENCHMARKS]
bench0 = {{ tb_verilog_file }}

[SYNTHESIS_PARAM]
bench0_top = {{ tb_top_entity }}

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
